Commit Graph

61 Commits

Author SHA1 Message Date
tangxifan 9c43b1b753 complete refacotriing the inv and buf part in submodules 2019-08-21 14:54:05 -06:00
tangxifan a40e5c91ca refactored power-gate inverter 2019-08-20 21:56:55 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 29104b6fa5 rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
tangxifan a7ac1e4980 remame methods in circuit_library 2019-08-20 15:24:53 -06:00
tangxifan dcca9f4f0f finish mux graph builders 2019-08-20 15:24:52 -06:00
tangxifan 638969c3c9 adding mux graph data structures 2019-08-20 15:24:52 -06:00
tangxifan c7526cb43c memory sanitized 2019-08-13 14:19:40 -06:00
tangxifan ef4d15df4e reorganize the libarchfpga repository 2019-08-13 13:37:35 -06:00
tangxifan 392f579836 add linking functions for circuit models and architecture, memory sanitizing is ongoing 2019-08-13 13:25:23 -06:00
tangxifan c56f289d3e add checkers for circuit library 2019-08-12 16:45:33 -06:00
tangxifan d4ae160d3a start adding circuit library checkers 2019-08-12 14:20:11 -06:00
tangxifan fbdab32a2d timing graph for circuit models are working 2019-08-10 13:03:24 -06:00
tangxifan c004699a14 complete parsers for ports 2019-08-09 21:00:41 -06:00
tangxifan 2c7d6e3de4 adding port parsers 2019-08-09 17:48:55 -06:00
tangxifan f80e58c753 developing a in-house tokenizer 2019-08-09 16:36:22 -06:00
tangxifan 3d7adb3dd9 start developing parsers for delay values 2019-08-09 15:52:28 -06:00
tangxifan 6b5ac2e1ef add timing graph builder for circuit models 2019-08-09 12:45:03 -06:00
tangxifan c8d04c4f00 plug in fast look-up builder 2019-08-08 21:20:28 -06:00
tangxifan 158c67075e built a conversion from spice_models to circuit_library and plug in 2019-08-08 17:25:27 -06:00
tangxifan e19485bbb7 add more accessors and more to be added when plug into framework 2019-08-08 14:16:29 -06:00
tangxifan ad8c33e1ba complete the mutators 2019-08-08 11:33:11 -06:00
tangxifan 5b0c9572c3 add mutators for delay_info 2019-08-07 21:19:16 -06:00
tangxifan 03a64e2ad8 complete the mutators for ports 2019-08-07 20:54:27 -06:00
tangxifan 9f8c7a3fc7 adding port mutators 2019-08-07 17:47:39 -06:00
tangxifan ed4642a23f adding basic mutators 2019-08-07 17:12:05 -06:00
tangxifan 38962c4607 adding member functions for circuit library 2019-08-07 15:45:27 -06:00
tangxifan 74da4ed51a start creating the class for circuit models 2019-08-07 11:38:45 -06:00
tangxifan fb2ca66ce9 start adding submodules of local encoders to multiplexer 2019-08-06 14:17:55 -06:00
tangxifan 33f3a991b5 init effort to start developing mux local encoders 2019-08-06 14:17:55 -06:00
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
AurelienUoU 19ccbce9d0 Rename option to use circuit_model rather than spice_model 2019-07-12 16:18:28 -06:00
Baudouin Chauviere 4ca0967453 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-09 14:35:51 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 548242b368 plug-in tileable rr generator which can be enable by a XML property 2019-06-20 21:06:26 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan f5b6ee6adf update travis configuration and clean up repository 2019-06-07 22:19:11 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
tangxifan 502344b13a add missing files 2019-05-22 12:35:12 -06:00
tangxifan efbc454cdd Add Class for RRSwtichBlock and plug-in to replace the old t_sb 2019-05-22 12:34:06 -06:00
tangxifan b185a17359 add routing_channel unique module generation 2019-05-20 22:33:17 -06:00
BaudouinChauviere cd4dc8b2e8
Delete read_xml_arch_file.c
Already present in SRC
2019-05-06 12:55:18 -06:00
Baudouin Chauviere a5a1a376ab Modified code for cleaner delay naming convention 2019-05-06 12:52:49 -06:00
Baudouin Chauviere e7b1d89985 Change syntax name for loop_breaker_delay_before/after which is more explicit 2019-05-06 12:25:26 -06:00
Baudouin Chauviere 7c257ebda7 Fix on the makefile which was not targetting the right folder 2019-05-06 12:21:53 -06:00
tangxifan 6e6ae1cc3d fixed bugs in CMakeLists.txt and Makefile 2019-05-03 23:03:04 -06:00