5d55456c99
Merge pull request #854 from lnis-uofu/yosys_upgrade
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[yosys] update to v0.22
2022-10-21 22:13:45 -07:00
40f1f2fbc6
[test] update golden results for iwls
2022-10-21 20:28:10 -07:00
04286508c8
[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
2022-10-21 20:26:56 -07:00
57b86eaebf
[yosys] update to v0.22
2022-10-21 16:57:00 -07:00
2bed188d66
Merge pull request #852 from lnis-uofu/pcf_hotfix
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Pcf hotfix - Avoid key collision when validating pcf data
2022-10-21 15:24:02 -07:00
0e48e74240
Merge pull request #850 from lnis-uofu/dependabot/submodules/yosys-plugins-e4d820f
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Bump yosys-plugins from `b3430d2` to `e4d820f`
2022-10-21 13:41:02 -07:00
2d42826919
[lib] code format
2022-10-21 13:03:03 -07:00
0999c9444b
[lib] remove debugging messages
2022-10-21 12:44:56 -07:00
b720b49eb1
[lib] now count pcf errors
2022-10-21 11:48:09 -07:00
72e7090421
Merge branch 'master' into dependabot/submodules/yosys-plugins-e4d820f
2022-10-21 09:52:39 -07:00
62a437a3a1
Merge branch 'master' into patch-3
2022-10-21 09:41:26 -07:00
c385bab3aa
Merge pull request #851 from mustafaarslan0/master
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Added new cell library for fracturable dsp36
2022-10-21 09:39:31 -07:00
db0e5dff93
Added new cell library for fracturable dsp36
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Added new divisible 36x36 multiplier cell library for architectures which has fracturable dsp36:
- The 36x36 multiplier is form from sixteen 9x9 multipliers.
- It operates same modes with existing library. It can operate in 3 fracturable modes:
1. one 36-bit multiplier
2. two 18-bit multipliers
3. four 9-bit multipliers
- It provides ~%20 better area than existing cell library (mult_36x36.v)
Comparison made with Synopsys Design Compiler NXT:
mult_36x36.v Total cell area 20470 um2
frac_mult_36x36.v Total cell area 15103 um2
2022-10-21 17:30:20 +03:00
98fcfd4ceb
Bump yosys-plugins from `b3430d2` to `e4d820f`
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Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins ) from `b3430d2` to `e4d820f`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases )
- [Commits](b3430d2e55...e4d820f63c
2022-10-21 06:35:23 +00:00
29d4b3cced
Update frac_mem_32k.v
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1. Mixed use of non-blocking and blocking statements are unsynthesizable in Synopsys Design Compiler.
2. While defining a multidimensional array, the first array size is for the length and the second one is for the depth. The order for ram_a and ram_b arrays was wrong and it caused "out of bounds" error in DC.
2022-10-20 09:48:29 +03:00
69e0aa2c2a
Merge pull request #846 from lnis-uofu/patch_update
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Pulling refs/heads/master into master
2022-10-17 22:40:19 -07:00
829ebce861
Updated Patch Count
2022-10-18 05:39:18 +00:00
783fa24521
Merge pull request #845 from lnis-uofu/empty_pcf
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Multiple improvements on I/O constraint support
2022-10-17 22:15:40 -07:00
00a485cbeb
[test] add missing file
2022-10-17 19:44:25 -07:00
c9631497e2
[engine] syntax
2022-10-17 16:11:49 -07:00
60c448c98d
[engine] syntax
2022-10-17 15:49:34 -07:00
76862efa57
[engine] syntax
2022-10-17 15:46:19 -07:00
c3f180372d
[engine] do not error out when ql-style is used in pin table
2022-10-17 15:42:22 -07:00
70b0d2e505
[doc] update pin table file format for pin direction keywords
2022-10-17 15:32:00 -07:00
c4de6655b6
[engine] bug
2022-10-17 15:26:21 -07:00
609e096b1a
[test] added a new test to validate explicit port direction in pin table support
2022-10-17 15:25:19 -07:00
b82ebf2f23
[script] suppress warnings for vtr libs
2022-10-17 15:16:23 -07:00
0f2b8da7f0
[engine] code format
2022-10-17 14:55:34 -07:00
63d8b00630
[engine] syntax
2022-10-17 14:54:18 -07:00
811438c20e
[engine] syntax
2022-10-17 14:20:23 -07:00
11624cd0c6
[engine] enabling new feature: pin_table_direction_convention
2022-10-17 14:08:21 -07:00
aef94171c2
[doc] update options for pcf2place command
2022-10-17 13:55:18 -07:00
2f434fd4d3
[lib] developing pin dir convention support
2022-10-17 12:35:06 -07:00
dbbabbc098
[lib] developing the support on forcing pin direction from a specific column in pin table .csv
2022-10-17 12:23:39 -07:00
8b00bfdff9
[test] replace hardcoded paths in task config files with relative paths
2022-10-17 11:55:57 -07:00
aa78981e37
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
2022-10-17 11:18:21 -07:00
18fc9071ab
Merge pull request #844 from lnis-uofu/patch_update
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Pulling refs/heads/master into master
2022-10-13 19:06:27 -07:00
3a1c1f326a
Updated Patch Count
2022-10-14 02:02:34 +00:00
7468daf456
Merge pull request #842 from lnis-uofu/rst_on_lut_strong
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Strong test case to validate that repacker can handle reset signal on LUTs
2022-10-13 18:59:43 -07:00
6611fba9d5
Merge branch 'rst_on_lut_strong' of https://github.com/lnis-uofu/OpenFPGA into rst_on_lut_strong
2022-10-13 16:28:22 -07:00
0af6c76239
[engine] code format
2022-10-13 16:27:57 -07:00
d1f3338837
[engine] now repacker find only routable pins when given a net to search routing traces
2022-10-13 16:26:45 -07:00
e9ee039e60
Merge branch 'master' into rst_on_lut_strong
2022-10-13 16:01:57 -07:00
33e2b16cb1
[arch] fixed a bug which caused verification failed
2022-10-13 15:33:43 -07:00
31da9bf6ea
[engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node
2022-10-13 15:10:25 -07:00
1c36ac28f1
[arch] code format
2022-10-13 12:17:32 -07:00
32f48f16c7
[arch] fixed a few bugs
2022-10-13 11:54:58 -07:00
b0be27b384
[test] add repack design constraints files
2022-10-13 11:22:48 -07:00
5cf315958d
[test] deploy new test to basic regression tests
2022-10-13 11:17:34 -07:00
7b7217d116
[arch]add new arch to test
2022-10-13 11:08:51 -07:00
tangxifan
mustafa.arslan
dependabot[bot]
Yunus Emre ERYILMAZ
github-actions[bot]