Merge pull request #845 from lnis-uofu/empty_pcf

Multiple improvements on I/O constraint support

CMakeLists.txt

@@ -82,6 +82,9 @@ set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Rou
 set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
 set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
 
+#Compiler flag configuration checks
+include(CheckCXXCompilerFlag)
+
 #
 # We require c++14 support
 #
@@ -218,9 +221,21 @@ endif()
 
 # Set final flags
 #
-set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${WARN_FLAGS} ${SANITIZE_FLAGS}")
-message(STATUS "CMAKE_CXX_FLAGS: ${CMAKE_CXX_FLAGS}")
+separate_arguments(
+    ADDITIONAL_FLAGS UNIX_COMMAND "${SANITIZE_FLAGS} ${PROFILING_FLAGS} ${COVERAGE_FLAGS} ${LOGGING_FLAGS} ${COLORED_COMPILE} ${EXTRA_FLAGS}"
+    )
+separate_arguments(
+    WARN_FLAGS UNIX_COMMAND "${WARN_FLAGS}"
+    )
 
+# 
+# Sub-projects with their own compiler settings
+#
+add_subdirectory(vtr-verilog-to-routing)
+
+add_compile_options(${WARN_FLAGS}) #Add warn flags for VTR tools
+add_compile_options(${ADDITIONAL_FLAGS})
+link_libraries(${ADDITIONAL_FLAGS})
 
 # Unit Testing
 #
@@ -229,9 +244,8 @@ if (OPENFPGA_WITH_TEST)
 endif()
 
 # 
-# Sub-projects
+# Sub-projects to apply current complier settings
 #
-add_subdirectory(vtr-verilog-to-routing)
 add_subdirectory(libs)
 add_subdirectory(openfpga)
 
@@ -260,17 +274,14 @@ if (YOSYS_ENABLE_READLINE)
   find_package(Readline REQUIRED)
 endif()
 
-#
-#########################
-##                      #
-## Compiler Flags Setup #
-##                      #
-#########################
-#
-## Compiler flag configuration checks
-include(CheckCCompilerFlag)
-include(CheckCXXCompilerFlag)
-#
+#PugiXml has some deliberate switch fallthrough cases (as indicated by comments), but they
+#are tagged as warnings with g++-7 (the comments don't match g++-7's suppression regexes).
+#Since we don't want to change PugiXml (it is developed externally), we relax the warning
+#level so no fallthrough warnings are generated
+CHECK_CXX_COMPILER_FLAG("-Wimplicit-fallthrough=0" CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0)
+if(CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0)
+    target_compile_options(libpugixml PRIVATE "-Wimplicit-fallthrough=0")
+endif()
 
 # we will check if yosys already exist. if not then build it
 if (OPENFPGA_WITH_YOSYS)

docs/source/manual/file_formats/pin_table_file.rst

@@ -14,22 +14,22 @@ An example of the file is shown as follows.
 .. code-block:: xml
 
   orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
-  TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,,
-  TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,,
-  TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],,,
-  TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],,,
-  TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],,,
-  TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],,,
-  TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],,,
-  TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],,,
-  RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],,,
-  RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],,,
-  RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],,,
-  RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,,
-  BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,,
-  BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,,
-  LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,,
-  LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,,
+  TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
+  TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
+  TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],in,,
+  TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],out,,
+  TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],in,,
+  TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],out,,
+  TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],in,,
+  TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],out,,
+  RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],in,,
+  RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],out,,
+  RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],in,,
+  RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],out,,
+  BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],in,,
+  BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],out,,
+  LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],in,,
+  LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],out,,
 
 An pin table may serve in various purposes. However, for OpenFPGA, the following attributes are required
 
@@ -45,4 +45,8 @@ An pin table may serve in various purposes. However, for OpenFPGA, the following
 
   Specify the pin name of the FPGA chip
 
-.. warning:: Currently, the direction of the port is inferred by the ``port_name``. A postfix of ``A2F`` indicates an input port, while a postfix of ``F2A`` indicates an output port. 
+.. option:: GPIO_type
+
+  Specify the pin direction. Can be [``in``|``out``].
+
+  .. note:: This column can be left as empty if users follow quicklogic style. See details in :ref:`openfpga_setup_commands_pcf2place`

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -267,6 +267,8 @@ write_fabric_io_info
 
   .. note:: This file is designed for pin constraint file conversion.
 
+.. _openfpga_setup_commands_pcf2place:
+
 pcf2place
 ~~~~~~~~~
 
@@ -292,6 +294,10 @@ pcf2place
 
     Specify the path to the placement file which will be outputted by running this command 
 
+  .. option:: --pin_table_direction_convention <string>
+
+    Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [``explicit``|``quicklogic``]. When ``explicit`` is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in :ref:`file_format_pin_table_file`). When ``quicklogic`` is selected, pin direction is inferred by port name: a port whose postfix is ``_A2F`` is an input, while a port whose postfix is ``_A2F`` is an output. By default, it is ``explicit``.
+
   .. option:: --no_time_stamp
 
     Do not print time stamp in bitstream files

libs/libpcf/src/io/read_csv_io_pin_table.cpp

@@ -18,10 +18,20 @@
 /* Begin namespace openfpga */
 namespace openfpga {
 
+/* Constants for io pin table csv parser */
+constexpr const int ROW_INDEX_INTERNAL_PIN = 4;
+constexpr const int ROW_INDEX_EXTERNAL_PIN = 5;
+constexpr const int ROW_INDEX_DIRECTION = 6;
+constexpr const int ROW_INDEX_SIDE = 0;
+constexpr const char* DIRECTION_INPUT = "in";
+constexpr const char* DIRECTION_OUTPUT = "out";
+
 /********************************************************************
  * Parse XML codes about <pin_constraints> to an object of PinConstraints
  *******************************************************************/
-IoPinTable read_csv_io_pin_table(const char* fname) {
+IoPinTable read_csv_io_pin_table(
+  const char* fname,
+  const e_pin_table_direction_convention& pin_dir_convention) {
   vtr::ScopedStartFinishTimer timer("Read I/O Pin Table");
 
   IoPinTable io_pin_table;
@@ -40,13 +50,13 @@ IoPinTable read_csv_io_pin_table(const char* fname) {
     std::vector<std::string> row_vec = doc.GetRow<std::string>(irow);
     IoPinTableId pin_id = io_pin_table.create_pin();
     /* Fill pin-level information */
-    PortParser internal_pin_parser(row_vec.at(4));
+    PortParser internal_pin_parser(row_vec.at(ROW_INDEX_INTERNAL_PIN));
     io_pin_table.set_internal_pin(pin_id, internal_pin_parser.port());
 
-    PortParser external_pin_parser(row_vec.at(5));
+    PortParser external_pin_parser(row_vec.at(ROW_INDEX_EXTERNAL_PIN));
     io_pin_table.set_external_pin(pin_id, external_pin_parser.port());
 
-    std::string pin_side_str = row_vec.at(0);
+    std::string pin_side_str = row_vec.at(ROW_INDEX_SIDE);
     if (side_str_map.end() == side_str_map.find(pin_side_str)) {
       VTR_LOG(
         "Invalid side defintion (='%s')! Expect [TOP|RIGHT|LEFT|BOTTOM]\n",
@@ -58,15 +68,33 @@ IoPinTable read_csv_io_pin_table(const char* fname) {
 
     /*This is not general purpose: we should have an explicit attribute in the
      * csv file to decalare direction */
-    if (internal_pin_parser.port().get_name().find("A2F") !=
-        std::string::npos) {
+    if (pin_dir_convention == e_pin_table_direction_convention::QUICKLOGIC) {
+      if (internal_pin_parser.port().get_name().find("A2F") !=
+          std::string::npos) {
+        io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT);
+      } else if (internal_pin_parser.port().get_name().find("F2A") !=
+                 std::string::npos) {
+        io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT);
+      } else {
+        VTR_LOG(
+          "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n");
+        exit(1);
+      }
+    }
+
+    /* Parse pin direction from a specific column, this has a higher priority
+     * than inferring from pin names */
+    std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION);
+    if (port_dir_str == std::string(DIRECTION_INPUT)) {
       io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT);
-    } else if (internal_pin_parser.port().get_name().find("F2A") !=
-               std::string::npos) {
+    } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) {
       io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT);
-    } else {
+    } else if (pin_dir_convention ==
+               e_pin_table_direction_convention::EXPLICIT) {
+      /* Error out only when we need explicit port direction */
       VTR_LOG(
-        "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n");
+        "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n",
+        DIRECTION_INPUT, DIRECTION_OUTPUT);
       exit(1);
     }
   }

libs/libpcf/src/io/read_csv_io_pin_table.h

@@ -14,7 +14,21 @@
 /* Begin namespace openfpga */
 namespace openfpga {
 
-IoPinTable read_csv_io_pin_table(const char* fname);
+/* Option to read csv */
+enum class e_pin_table_direction_convention {
+  EXPLICIT = 0,
+  QUICKLOGIC,
+  NUM_TYPES
+};
+const std::map<e_pin_table_direction_convention, const char*>
+  PIN_TABLE_DIRECTION_CONVENTION_STRING = {
+    {e_pin_table_direction_convention::EXPLICIT, "explicit"},
+    {e_pin_table_direction_convention::QUICKLOGIC,
+     "quicklogic"}};  // String versions of side orientations
+
+IoPinTable read_csv_io_pin_table(
+  const char* fname,
+  const e_pin_table_direction_convention& pin_dir_convention);
 
 } /* End namespace openfpga*/
 

libs/libpcf/test/test_csv_io_pin_table.cpp

@@ -16,7 +16,8 @@ int main(int argc, const char** argv) {
   VTR_ASSERT((2 == argc) || (3 == argc));
 
   /* Parse the fabric key from an XML file */
-  openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1]);
+  openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(
+    argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC);
   VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[1]);
 
   /* Output to an XML file

libs/libpcf/test/test_pcf2place.cpp

@@ -42,7 +42,8 @@ int main(int argc, const char** argv) {
     openfpga::read_xml_io_location_map(argv[3]);
   VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]);
 
-  openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4]);
+  openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(
+    argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC);
   VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]);
 
   /* Convert */

openfpga/src/base/openfpga_pcf2place.cpp

@@ -36,6 +36,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context,
   CommandOptionId opt_pin_table = cmd.option("pin_table");
   CommandOptionId opt_fpga_fix_pins = cmd.option("fpga_fix_pins");
   CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
+  CommandOptionId opt_pin_table_dir_convention =
+    cmd.option("pin_table_direction_convention");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf);
@@ -45,6 +47,30 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context,
   std::string pin_table_fname = cmd_context.option_value(cmd, opt_pin_table);
   std::string fpga_fix_pins_fname =
     cmd_context.option_value(cmd, opt_fpga_fix_pins);
+  e_pin_table_direction_convention pin_table_dir_convention =
+    e_pin_table_direction_convention::EXPLICIT;
+  if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) {
+    std::string pin_table_dir_convention_str =
+      cmd_context.option_value(cmd, opt_pin_table_dir_convention);
+    if (pin_table_dir_convention_str ==
+        std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
+          e_pin_table_direction_convention::EXPLICIT))) {
+      pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT;
+    } else if (pin_table_dir_convention_str ==
+               std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
+                 e_pin_table_direction_convention::QUICKLOGIC))) {
+      pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC;
+    } else {
+      VTR_LOG_ERROR(
+        "Invalid pin naming convention ('%s') to identify port direction for "
+        "pin table! Expect ['%s'|'%s'].\n",
+        pin_table_dir_convention_str.c_str(),
+        PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
+          e_pin_table_direction_convention::EXPLICIT),
+        PIN_TABLE_DIRECTION_CONVENTION_STRING.at(
+          e_pin_table_direction_convention::QUICKLOGIC));
+    }
+  }
 
   /* Parse the input files */
   openfpga::PcfData pcf_data;
@@ -65,7 +91,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context,
   VTR_LOG("Read the I/O location map from an XML file: %s.\n",
           fpga_io_map_fname.c_str());
 
-  IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str());
+  IoPinTable io_pin_table =
+    read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention);
   VTR_LOG("Read the I/O pin table from a csv file: %s.\n",
           pin_table_fname.c_str());
 

openfpga/src/base/openfpga_setup_command.cpp

@@ -528,6 +528,14 @@ static ShellCommandId add_openfpga_pcf2place_command(
   shell_cmd.set_option_require_value(opt_fpga_fix_pins_file,
                                      openfpga::OPT_STRING);
 
+  /* Add an option '--pin_table_direction_convention'*/
+  CommandOptionId opt_pin_table_dir_convention =
+    shell_cmd.add_option("pin_table_direction_convention", false,
+                         "the convention to follow when inferring pin "
+                         "direction from the name of ports in pin table file");
+  shell_cmd.set_option_require_value(opt_pin_table_dir_convention,
+                                     openfpga::OPT_STRING);
+
   /* Add an option '--no_time_stamp' */
   shell_cmd.add_option("no_time_stamp", false,
                        "Do not print time stamp in output files");

openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga

@@ -1,5 +1,5 @@
 # Convert .pcf to a .place file that VPR can accept
-pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE}
+pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION}
 
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -185,8 +185,10 @@ run-task basic_tests/bus_group/full_testbench_explicit_mapping $@
 run-task basic_tests/bus_group/full_testbench_implicit_mapping $@
 
 echo -e "Testing fix pins features";
-run-task basic_tests/fix_pins $@
-run-task basic_tests/constrain_pin_location $@
+run-task basic_tests/io_constraints/fix_pins $@
+run-task basic_tests/io_constraints/example_pcf $@
+run-task basic_tests/io_constraints/empty_pcf $@
+run-task basic_tests/io_constraints/pcf_ql_style $@
 
 echo -e "Testing project templates";
 run-task template_tasks/vpr_blif_template $@

openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf

@@ -0,0 +1 @@
+# Intended to be empt

openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv

@@ -0,0 +1,17 @@
+orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
+TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
+TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
+TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
+TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
+TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
+TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
+TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
+TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
+BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
+BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
+LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
+LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,

openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf

@@ -21,10 +21,11 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_vpr_device_layout=4x4
 openfpga_vpr_route_chan_width=20
-openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf
-openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml
-openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv
+openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
+openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
+openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
 openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=explicit
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml

@@ -0,0 +1,18 @@
+<io_coordinates>
+  <io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
+  <io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
+</io_coordinates>

openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv

@@ -0,0 +1,17 @@
+orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
+TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,,
+TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,,
+TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,,
+TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,,
+TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,,
+TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,,
+TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,,
+TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,,
+RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,,
+RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,,
+BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,,
+BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,,
+LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,,
+LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,,

openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf

@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
+openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
+openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
+openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=explicit
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf

@@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=20
-openfpga_vpr_fix_pins_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place
+openfpga_vpr_fix_pins_file=${PATH:TASK_DIR}/config/and2_fix_pins.place
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf

@@ -0,0 +1,3 @@
+set_io a pad_fpga_io[0]
+set_io b pad_fpga_io[4]
+set_io c pad_fpga_io[6]

openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml

@@ -0,0 +1,18 @@
+<io_coordinates>
+  <io pad="gfpga_pad_IO_A2F[0]" x="1" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[0]" x="1" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[1]" x="1" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[1]" x="1" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[2]" x="1" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[2]" x="1" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[3]" x="1" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[3]" x="1" y="0" z="7"/>
+  <io pad="gfpga_pad_IO_A2F[4]" x="2" y="0" z="0"/>
+  <io pad="gfpga_pad_IO_F2A[4]" x="2" y="0" z="1"/>
+  <io pad="gfpga_pad_IO_A2F[5]" x="2" y="0" z="2"/>
+  <io pad="gfpga_pad_IO_F2A[5]" x="2" y="0" z="3"/>
+  <io pad="gfpga_pad_IO_A2F[6]" x="2" y="0" z="4"/>
+  <io pad="gfpga_pad_IO_F2A[6]" x="2" y="0" z="5"/>
+  <io pad="gfpga_pad_IO_A2F[7]" x="2" y="0" z="6"/>
+  <io pad="gfpga_pad_IO_F2A[7]" x="2" y="0" z="7"/>
+</io_coordinates>

openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf

@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf
+openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml
+openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv
+openfpga_vpr_fix_pins_file=and2_fix_pins.place 
+openfpga_pin_table_direction_convention=quicklogic
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=