From aa78981e37de57fb29e9748c60ced60b5d3d3e89 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 11:18:21 -0700 Subject: [PATCH 01/18] [test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory --- .../regression_test_scripts/basic_reg_test.sh | 5 ++- .../fix_pins/config/and2_fix_pins.place | 3 -- .../io_constraints/empty_pcf/config/and2.pcf | 1 + .../empty_pcf}/config/fpga_io_location.xml | 0 .../config/pinmap_k4_N4_tileable_40nm.csv | 0 .../empty_pcf}/config/task.conf | 0 .../example_pcf}/config/and2.pcf | 0 .../example_pcf/config/fpga_io_location.xml | 18 ++++++++ .../config/pinmap_k4_N4_tileable_40nm.csv | 17 ++++++++ .../example_pcf/config/task.conf | 41 +++++++++++++++++++ .../fix_pins/config/task.conf | 0 11 files changed, 80 insertions(+), 5 deletions(-) delete mode 100644 openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/empty_pcf}/config/fpga_io_location.xml (100%) rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/empty_pcf}/config/pinmap_k4_N4_tileable_40nm.csv (100%) rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/empty_pcf}/config/task.conf (100%) rename openfpga_flow/tasks/basic_tests/{constrain_pin_location => io_constraints/example_pcf}/config/and2.pcf (100%) create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf rename openfpga_flow/tasks/basic_tests/{ => io_constraints}/fix_pins/config/task.conf (100%) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 47d7067f7..221426609 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -185,8 +185,9 @@ run-task basic_tests/bus_group/full_testbench_explicit_mapping $@ run-task basic_tests/bus_group/full_testbench_implicit_mapping $@ echo -e "Testing fix pins features"; -run-task basic_tests/fix_pins $@ -run-task basic_tests/constrain_pin_location $@ +run-task basic_tests/io_constraints/fix_pins $@ +run-task basic_tests/io_constraints/example_pcf $@ +run-task basic_tests/io_constraints/empty_pcf $@ echo -e "Testing project templates"; run-task template_tasks/vpr_blif_template $@ diff --git a/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place b/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place deleted file mode 100644 index 5f24ccebe..000000000 --- a/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place +++ /dev/null @@ -1,3 +0,0 @@ -a 0 1 0 -b 2 0 3 -out:c 1 3 7 diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf new file mode 100644 index 000000000..43a5d7296 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/and2.pcf @@ -0,0 +1 @@ +# Intended to be empt diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/fpga_io_location.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml rename to openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/fpga_io_location.xml diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv rename to openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/task.conf rename to openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/and2.pcf similarity index 100% rename from openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf rename to openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/and2.pcf diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml new file mode 100644 index 000000000..03eb56357 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/fpga_io_location.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv new file mode 100644 index 000000000..ba0691940 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv @@ -0,0 +1,17 @@ +orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf new file mode 100644 index 000000000..a7d18889b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf +openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml +openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_vpr_fix_pins_file=and2_fix_pins.place + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/fix_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf similarity index 100% rename from openfpga_flow/tasks/basic_tests/fix_pins/config/task.conf rename to openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf From 8b00bfdff986c26a77724f4c0dea1fcd310f70bc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 11:55:57 -0700 Subject: [PATCH 02/18] [test] replace hardcoded paths in task config files with relative paths --- .../basic_tests/io_constraints/empty_pcf/config/task.conf | 6 +++--- .../basic_tests/io_constraints/example_pcf/config/task.conf | 6 +++--- .../basic_tests/io_constraints/fix_pins/config/task.conf | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf index a7d18889b..b16acaecc 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 openfpga_vpr_route_chan_width=20 -openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf -openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml -openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf +openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml +openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf index a7d18889b..b16acaecc 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 openfpga_vpr_route_chan_width=20 -openfpga_pcf=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/and2.pcf -openfpga_io_map_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/fpga_io_location.xml -openfpga_pin_table=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/constrain_pin_location/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf +openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml +openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf index 56fd9ff4f..3aef18436 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 openfpga_vpr_route_chan_width=20 -openfpga_vpr_fix_pins_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/fix_pins/config/and2_fix_pins.place +openfpga_vpr_fix_pins_file=${PATH:TASK_DIR}/config/and2_fix_pins.place [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml From dbbabbc0981dd1952c7f642f85753d5aedf9389b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 12:23:39 -0700 Subject: [PATCH 03/18] [lib] developing the support on forcing pin direction from a specific column in pin table .csv --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 26 +++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 18bc0499c..0a1e90d9c 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -18,6 +18,14 @@ /* Begin namespace openfpga */ namespace openfpga { +/* Constants for io pin table csv parser */ +constexpr const int ROW_INDEX_INTERNAL_PIN = 4; +constexpr const int ROW_INDEX_EXTERNAL_PIN = 5; +constexpr const int ROW_INDEX_DIRECTION = 6; +constexpr const int ROW_INDEX_SIDE = 0; +constexpr const char* DIRECTION_INPUT = "in"; +constexpr const char* DIRECTION_OUTPUT = "out"; + /******************************************************************** * Parse XML codes about to an object of PinConstraints *******************************************************************/ @@ -40,13 +48,13 @@ IoPinTable read_csv_io_pin_table(const char* fname) { std::vector row_vec = doc.GetRow(irow); IoPinTableId pin_id = io_pin_table.create_pin(); /* Fill pin-level information */ - PortParser internal_pin_parser(row_vec.at(4)); + PortParser internal_pin_parser(row_vec.at(ROW_INDEX_INTERNAL_PIN)); io_pin_table.set_internal_pin(pin_id, internal_pin_parser.port()); - PortParser external_pin_parser(row_vec.at(5)); + PortParser external_pin_parser(row_vec.at(ROW_INDEX_EXTERNAL_PIN)); io_pin_table.set_external_pin(pin_id, external_pin_parser.port()); - std::string pin_side_str = row_vec.at(0); + std::string pin_side_str = row_vec.at(ROW_INDEX_SIDE); if (side_str_map.end() == side_str_map.find(pin_side_str)) { VTR_LOG( "Invalid side defintion (='%s')! Expect [TOP|RIGHT|LEFT|BOTTOM]\n", @@ -69,6 +77,18 @@ IoPinTable read_csv_io_pin_table(const char* fname) { "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); exit(1); } + + /* Parse pin direction from a specific column, this has a higher priority than inferring from pin names */ + std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); + if (port_dir_str == std::string(DIRECTION_INPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else { + VTR_LOG( + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", DIRECTION_INPUT, DIRECTION_OUTPUT); + exit(1); + } } return io_pin_table; From 2f434fd4d31422c637f49c34d93bbe0c992cda5f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 12:35:06 -0700 Subject: [PATCH 04/18] [lib] developing pin dir convention support --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 24 +++++++++++--------- libs/libpcf/src/io/read_csv_io_pin_table.h | 10 +++++++- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 0a1e90d9c..8f07e1b7d 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -29,7 +29,7 @@ constexpr const char* DIRECTION_OUTPUT = "out"; /******************************************************************** * Parse XML codes about to an object of PinConstraints *******************************************************************/ -IoPinTable read_csv_io_pin_table(const char* fname) { +IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention) { vtr::ScopedStartFinishTimer timer("Read I/O Pin Table"); IoPinTable io_pin_table; @@ -66,16 +66,18 @@ IoPinTable read_csv_io_pin_table(const char* fname) { /*This is not general purpose: we should have an explicit attribute in the * csv file to decalare direction */ - if (internal_pin_parser.port().get_name().find("A2F") != - std::string::npos) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); - } else if (internal_pin_parser.port().get_name().find("F2A") != - std::string::npos) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); - } else { - VTR_LOG( - "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); - exit(1); + if (pin_dir_convention == e_pin_table_direction_convention::QUICKLOGIC) { + if (internal_pin_parser.port().get_name().find("A2F") != + std::string::npos) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (internal_pin_parser.port().get_name().find("F2A") != + std::string::npos) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else { + VTR_LOG( + "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); + exit(1); + } } /* Parse pin direction from a specific column, this has a higher priority than inferring from pin names */ diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index c82b5f9cf..acf3473a5 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -14,7 +14,15 @@ /* Begin namespace openfpga */ namespace openfpga { -IoPinTable read_csv_io_pin_table(const char* fname); +/* Option to read csv */ +enum class e_pin_table_direction_convention { + EXPLICIT = 0, + QUICKLOGIC, + NUM_PIN_DIRECTION_CONVENTION +}; +constexpr std::array PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations + +IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); } /* End namespace openfpga*/ From aef94171c27183b88c21f4426c157d028a0a53c8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 13:55:18 -0700 Subject: [PATCH 05/18] [doc] update options for pcf2place command --- .../openfpga_shell/openfpga_commands/setup_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 98e539044..7e84351da 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -292,6 +292,10 @@ pcf2place Specify the path to the placement file which will be outputted by running this command + .. option:: --pin_table_direction_convention + + Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [``explicit``|``quicklogic``]. When ``explicit`` is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in :ref:`file_format_pin_table_file`). When ``quicklogic`` is selected, pin direction is inferred by port name: a port whose postfix is ``_A2F`` is an input, while a port whose postfix is ``_A2F`` is an output. By default, it is ``explicit``. + .. option:: --no_time_stamp Do not print time stamp in bitstream files From 11624cd0c6315ad00b2249bae1df8315095f3a41 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:08:21 -0700 Subject: [PATCH 06/18] [engine] enabling new feature: pin_table_direction_convention --- libs/libpcf/test/test_csv_io_pin_table.cpp | 2 +- libs/libpcf/test/test_pcf2place.cpp | 2 +- openfpga/src/base/openfpga_pcf2place.cpp | 15 ++++++++++++++- openfpga/src/base/openfpga_setup_command.cpp | 7 +++++++ 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/libs/libpcf/test/test_csv_io_pin_table.cpp b/libs/libpcf/test/test_csv_io_pin_table.cpp index 22084d6b9..b918b7775 100644 --- a/libs/libpcf/test/test_csv_io_pin_table.cpp +++ b/libs/libpcf/test/test_csv_io_pin_table.cpp @@ -16,7 +16,7 @@ int main(int argc, const char** argv) { VTR_ASSERT((2 == argc) || (3 == argc)); /* Parse the fabric key from an XML file */ - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1]); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[1]); /* Output to an XML file diff --git a/libs/libpcf/test/test_pcf2place.cpp b/libs/libpcf/test/test_pcf2place.cpp index 05b9614d2..b70e5339b 100644 --- a/libs/libpcf/test/test_pcf2place.cpp +++ b/libs/libpcf/test/test_pcf2place.cpp @@ -43,7 +43,7 @@ int main(int argc, const char** argv) { VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]); openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4]); - VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]); + VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); /* Convert */ openfpga::IoNetPlace io_net_place; diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place.cpp index 02ecea463..bcb069b8b 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place.cpp @@ -36,6 +36,7 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, CommandOptionId opt_pin_table = cmd.option("pin_table"); CommandOptionId opt_fpga_fix_pins = cmd.option("fpga_fix_pins"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + CommandOptionId opt_pin_table_dir_convention = cmd.option("pin_table_direction_convention"); CommandOptionId opt_verbose = cmd.option("verbose"); std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf); @@ -45,6 +46,18 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, std::string pin_table_fname = cmd_context.option_value(cmd, opt_pin_table); std::string fpga_fix_pins_fname = cmd_context.option_value(cmd, opt_fpga_fix_pins); + e_pin_table_direction_convention pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; + if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) { + std::string pin_table_dir_convention_str = cmd_context.option_value(cmd, opt_pin_table_dir_convention); + if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT])) { + pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; + } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC])) { + pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC; + } else { + VTR_LOG_ERROR("Invalid pin naming convention ('%s') to identify port direction for pin table! Expect ['%s'|'%s'].\n", + pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT], PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC]); + } + } /* Parse the input files */ openfpga::PcfData pcf_data; @@ -65,7 +78,7 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, VTR_LOG("Read the I/O location map from an XML file: %s.\n", fpga_io_map_fname.c_str()); - IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str()); + IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", pin_table_fname.c_str()); diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 50719d026..7be458bfd 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -528,6 +528,13 @@ static ShellCommandId add_openfpga_pcf2place_command( shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, openfpga::OPT_STRING); + /* Add an option '--pin_table_direction_convention'*/ + CommandOptionId opt_pin_table_dir_convention = shell_cmd.add_option( + "pin_table_direction_convention", false, + "the convention to follow when inferring pin direction from the name of ports in pin table file"); + shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, + openfpga::OPT_STRING); + /* Add an option '--no_time_stamp' */ shell_cmd.add_option("no_time_stamp", false, "Do not print time stamp in output files"); From 811438c20e7f4c7ac6ab30968f55aad8559f526e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:20:23 -0700 Subject: [PATCH 07/18] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index acf3473a5..50f5e3d2a 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -18,9 +18,9 @@ namespace openfpga { enum class e_pin_table_direction_convention { EXPLICIT = 0, QUICKLOGIC, - NUM_PIN_DIRECTION_CONVENTION + NUM_TYPES }; -constexpr std::array PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations +constexpr std::array(e_pin_table_direction_convention::NUM_TYPES)> PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); From 63d8b00630ac1eb76dea6bb9bab9f85ad049a299 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:54:18 -0700 Subject: [PATCH 08/18] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.h | 5 ++++- libs/libpcf/test/test_pcf2place.cpp | 4 ++-- openfpga/src/base/openfpga_pcf2place.cpp | 6 +++--- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index 50f5e3d2a..e1b121bff 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -20,7 +20,10 @@ enum class e_pin_table_direction_convention { QUICKLOGIC, NUM_TYPES }; -constexpr std::array(e_pin_table_direction_convention::NUM_TYPES)> PIN_TABLE_DIRECTION_CONVENTION_STRING = {{"explicit", "quicklogic"}}; //String versions of side orientations +const std::map PIN_TABLE_DIRECTION_CONVENTION_STRING = { + {e_pin_table_direction_convention::EXPLICIT, "explicit"}, + {e_pin_table_direction_convention::QUICKLOGIC, "quicklogic"} +}; //String versions of side orientations IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); diff --git a/libs/libpcf/test/test_pcf2place.cpp b/libs/libpcf/test/test_pcf2place.cpp index b70e5339b..38e1c18c4 100644 --- a/libs/libpcf/test/test_pcf2place.cpp +++ b/libs/libpcf/test/test_pcf2place.cpp @@ -42,8 +42,8 @@ int main(int argc, const char** argv) { openfpga::read_xml_io_location_map(argv[3]); VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]); - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4]); - VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]); /* Convert */ openfpga::IoNetPlace io_net_place; diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place.cpp index bcb069b8b..215d54b3b 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place.cpp @@ -49,13 +49,13 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, e_pin_table_direction_convention pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) { std::string pin_table_dir_convention_str = cmd_context.option_value(cmd, opt_pin_table_dir_convention); - if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT])) { + if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT))) { pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; - } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC])) { + } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC))) { pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC; } else { VTR_LOG_ERROR("Invalid pin naming convention ('%s') to identify port direction for pin table! Expect ['%s'|'%s'].\n", - pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::EXPLICIT], PIN_TABLE_DIRECTION_CONVENTION_STRING[e_pin_table_direction_convention::QUICKLOGIC]); + pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC)); } } From 0f2b8da7f01707741d8c160ee38ceafd007d090c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 14:55:34 -0700 Subject: [PATCH 09/18] [engine] code format --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 16 +++++++---- libs/libpcf/src/io/read_csv_io_pin_table.h | 13 +++++---- libs/libpcf/test/test_csv_io_pin_table.cpp | 3 +- libs/libpcf/test/test_pcf2place.cpp | 3 +- openfpga/src/base/openfpga_pcf2place.cpp | 30 ++++++++++++++------ openfpga/src/base/openfpga_setup_command.cpp | 7 +++-- 6 files changed, 48 insertions(+), 24 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 8f07e1b7d..a3f3f775a 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -20,16 +20,18 @@ namespace openfpga { /* Constants for io pin table csv parser */ constexpr const int ROW_INDEX_INTERNAL_PIN = 4; -constexpr const int ROW_INDEX_EXTERNAL_PIN = 5; -constexpr const int ROW_INDEX_DIRECTION = 6; -constexpr const int ROW_INDEX_SIDE = 0; +constexpr const int ROW_INDEX_EXTERNAL_PIN = 5; +constexpr const int ROW_INDEX_DIRECTION = 6; +constexpr const int ROW_INDEX_SIDE = 0; constexpr const char* DIRECTION_INPUT = "in"; constexpr const char* DIRECTION_OUTPUT = "out"; /******************************************************************** * Parse XML codes about to an object of PinConstraints *******************************************************************/ -IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention) { +IoPinTable read_csv_io_pin_table( + const char* fname, + const e_pin_table_direction_convention& pin_dir_convention) { vtr::ScopedStartFinishTimer timer("Read I/O Pin Table"); IoPinTable io_pin_table; @@ -80,7 +82,8 @@ IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_ } } - /* Parse pin direction from a specific column, this has a higher priority than inferring from pin names */ + /* Parse pin direction from a specific column, this has a higher priority + * than inferring from pin names */ std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); if (port_dir_str == std::string(DIRECTION_INPUT)) { io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); @@ -88,7 +91,8 @@ IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_ io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); } else { VTR_LOG( - "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", DIRECTION_INPUT, DIRECTION_OUTPUT); + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", + DIRECTION_INPUT, DIRECTION_OUTPUT); exit(1); } } diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.h b/libs/libpcf/src/io/read_csv_io_pin_table.h index e1b121bff..a3a7d7281 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.h +++ b/libs/libpcf/src/io/read_csv_io_pin_table.h @@ -20,12 +20,15 @@ enum class e_pin_table_direction_convention { QUICKLOGIC, NUM_TYPES }; -const std::map PIN_TABLE_DIRECTION_CONVENTION_STRING = { - {e_pin_table_direction_convention::EXPLICIT, "explicit"}, - {e_pin_table_direction_convention::QUICKLOGIC, "quicklogic"} -}; //String versions of side orientations +const std::map + PIN_TABLE_DIRECTION_CONVENTION_STRING = { + {e_pin_table_direction_convention::EXPLICIT, "explicit"}, + {e_pin_table_direction_convention::QUICKLOGIC, + "quicklogic"}}; // String versions of side orientations -IoPinTable read_csv_io_pin_table(const char* fname, const e_pin_table_direction_convention& pin_dir_convention); +IoPinTable read_csv_io_pin_table( + const char* fname, + const e_pin_table_direction_convention& pin_dir_convention); } /* End namespace openfpga*/ diff --git a/libs/libpcf/test/test_csv_io_pin_table.cpp b/libs/libpcf/test/test_csv_io_pin_table.cpp index b918b7775..e9d51fb90 100644 --- a/libs/libpcf/test/test_csv_io_pin_table.cpp +++ b/libs/libpcf/test/test_csv_io_pin_table.cpp @@ -16,7 +16,8 @@ int main(int argc, const char** argv) { VTR_ASSERT((2 == argc) || (3 == argc)); /* Parse the fabric key from an XML file */ - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table( + argv[1], openfpga::e_pin_table_direction_convention::QUICKLOGIC); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[1]); /* Output to an XML file diff --git a/libs/libpcf/test/test_pcf2place.cpp b/libs/libpcf/test/test_pcf2place.cpp index 38e1c18c4..ba72651d7 100644 --- a/libs/libpcf/test/test_pcf2place.cpp +++ b/libs/libpcf/test/test_pcf2place.cpp @@ -42,7 +42,8 @@ int main(int argc, const char** argv) { openfpga::read_xml_io_location_map(argv[3]); VTR_LOG("Read the I/O location map from an XML file: %s.\n", argv[3]); - openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table(argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); + openfpga::IoPinTable io_pin_table = openfpga::read_csv_io_pin_table( + argv[4], openfpga::e_pin_table_direction_convention::QUICKLOGIC); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", argv[4]); /* Convert */ diff --git a/openfpga/src/base/openfpga_pcf2place.cpp b/openfpga/src/base/openfpga_pcf2place.cpp index 215d54b3b..c3b70e85c 100644 --- a/openfpga/src/base/openfpga_pcf2place.cpp +++ b/openfpga/src/base/openfpga_pcf2place.cpp @@ -36,7 +36,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, CommandOptionId opt_pin_table = cmd.option("pin_table"); CommandOptionId opt_fpga_fix_pins = cmd.option("fpga_fix_pins"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); - CommandOptionId opt_pin_table_dir_convention = cmd.option("pin_table_direction_convention"); + CommandOptionId opt_pin_table_dir_convention = + cmd.option("pin_table_direction_convention"); CommandOptionId opt_verbose = cmd.option("verbose"); std::string pcf_fname = cmd_context.option_value(cmd, opt_pcf); @@ -46,16 +47,28 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, std::string pin_table_fname = cmd_context.option_value(cmd, opt_pin_table); std::string fpga_fix_pins_fname = cmd_context.option_value(cmd, opt_fpga_fix_pins); - e_pin_table_direction_convention pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; + e_pin_table_direction_convention pin_table_dir_convention = + e_pin_table_direction_convention::EXPLICIT; if (cmd_context.option_enable(cmd, opt_pin_table_dir_convention)) { - std::string pin_table_dir_convention_str = cmd_context.option_value(cmd, opt_pin_table_dir_convention); - if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT))) { + std::string pin_table_dir_convention_str = + cmd_context.option_value(cmd, opt_pin_table_dir_convention); + if (pin_table_dir_convention_str == + std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::EXPLICIT))) { pin_table_dir_convention = e_pin_table_direction_convention::EXPLICIT; - } else if (pin_table_dir_convention_str == std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC))) { + } else if (pin_table_dir_convention_str == + std::string(PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::QUICKLOGIC))) { pin_table_dir_convention = e_pin_table_direction_convention::QUICKLOGIC; } else { - VTR_LOG_ERROR("Invalid pin naming convention ('%s') to identify port direction for pin table! Expect ['%s'|'%s'].\n", - pin_table_dir_convention_str.c_str(), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::EXPLICIT), PIN_TABLE_DIRECTION_CONVENTION_STRING.at(e_pin_table_direction_convention::QUICKLOGIC)); + VTR_LOG_ERROR( + "Invalid pin naming convention ('%s') to identify port direction for " + "pin table! Expect ['%s'|'%s'].\n", + pin_table_dir_convention_str.c_str(), + PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::EXPLICIT), + PIN_TABLE_DIRECTION_CONVENTION_STRING.at( + e_pin_table_direction_convention::QUICKLOGIC)); } } @@ -78,7 +91,8 @@ int pcf2place_wrapper(const OpenfpgaContext& openfpga_context, VTR_LOG("Read the I/O location map from an XML file: %s.\n", fpga_io_map_fname.c_str()); - IoPinTable io_pin_table = read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention); + IoPinTable io_pin_table = + read_csv_io_pin_table(pin_table_fname.c_str(), pin_table_dir_convention); VTR_LOG("Read the I/O pin table from a csv file: %s.\n", pin_table_fname.c_str()); diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index 7be458bfd..ec8252aca 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -529,9 +529,10 @@ static ShellCommandId add_openfpga_pcf2place_command( openfpga::OPT_STRING); /* Add an option '--pin_table_direction_convention'*/ - CommandOptionId opt_pin_table_dir_convention = shell_cmd.add_option( - "pin_table_direction_convention", false, - "the convention to follow when inferring pin direction from the name of ports in pin table file"); + CommandOptionId opt_pin_table_dir_convention = + shell_cmd.add_option("pin_table_direction_convention", false, + "the convention to follow when inferring pin " + "direction from the name of ports in pin table file"); shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, openfpga::OPT_STRING); From b82ebf2f231802ebeeeacb99eb6a3000c1a5dc9d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:16:23 -0700 Subject: [PATCH 10/18] [script] suppress warnings for vtr libs --- CMakeLists.txt | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 9077328fc..748735ad0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -82,6 +82,9 @@ set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Rou set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing") set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number") +#Compiler flag configuration checks +include(CheckCXXCompilerFlag) + # # We require c++14 support # @@ -218,9 +221,21 @@ endif() # Set final flags # -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${WARN_FLAGS} ${SANITIZE_FLAGS}") -message(STATUS "CMAKE_CXX_FLAGS: ${CMAKE_CXX_FLAGS}") +separate_arguments( + ADDITIONAL_FLAGS UNIX_COMMAND "${SANITIZE_FLAGS} ${PROFILING_FLAGS} ${COVERAGE_FLAGS} ${LOGGING_FLAGS} ${COLORED_COMPILE} ${EXTRA_FLAGS}" + ) +separate_arguments( + WARN_FLAGS UNIX_COMMAND "${WARN_FLAGS}" + ) +# +# Sub-projects with their own compiler settings +# +add_subdirectory(vtr-verilog-to-routing) + +add_compile_options(${WARN_FLAGS}) #Add warn flags for VTR tools +add_compile_options(${ADDITIONAL_FLAGS}) +link_libraries(${ADDITIONAL_FLAGS}) # Unit Testing # @@ -229,9 +244,8 @@ if (OPENFPGA_WITH_TEST) endif() # -# Sub-projects +# Sub-projects to apply current complier settings # -add_subdirectory(vtr-verilog-to-routing) add_subdirectory(libs) add_subdirectory(openfpga) @@ -260,17 +274,14 @@ if (YOSYS_ENABLE_READLINE) find_package(Readline REQUIRED) endif() -# -######################### -## # -## Compiler Flags Setup # -## # -######################### -# -## Compiler flag configuration checks -include(CheckCCompilerFlag) -include(CheckCXXCompilerFlag) -# +#PugiXml has some deliberate switch fallthrough cases (as indicated by comments), but they +#are tagged as warnings with g++-7 (the comments don't match g++-7's suppression regexes). +#Since we don't want to change PugiXml (it is developed externally), we relax the warning +#level so no fallthrough warnings are generated +CHECK_CXX_COMPILER_FLAG("-Wimplicit-fallthrough=0" CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0) +if(CXX_COMPILER_SUPPORTS_-Wimplicit-fallthrough=0) + target_compile_options(libpugixml PRIVATE "-Wimplicit-fallthrough=0") +endif() # we will check if yosys already exist. if not then build it if (OPENFPGA_WITH_YOSYS) From 609e096b1a10bd9f310024921a23eeb98abb7667 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:25:19 -0700 Subject: [PATCH 11/18] [test] added a new test to validate explicit port direction in pin table support --- .../pin_constrain_example_script.openfpga | 2 +- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/pinmap_k4_N4_tileable_40nm.csv | 32 +++++++------- .../io_constraints/empty_pcf/config/task.conf | 1 + .../config/pinmap_k4_N4_tileable_40nm.csv | 32 +++++++------- .../example_pcf/config/task.conf | 1 + .../pcf_ql_style/config/and2.pcf | 3 ++ .../pcf_ql_style/config/fpga_io_location.xml | 18 ++++++++ .../config/pinmap_k4_N4_tileable_40nm.csv | 17 ++++++++ .../pcf_ql_style/config/task.conf | 42 +++++++++++++++++++ 10 files changed, 116 insertions(+), 33 deletions(-) create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf diff --git a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga index ad29fc51e..f25bf0323 100644 --- a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga @@ -1,5 +1,5 @@ # Convert .pcf to a .place file that VPR can accept -pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} +pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENFPGA_PIN_TABLE} --fpga_io_map ${OPENFPGA_IO_MAP_FILE} --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION} # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 221426609..e4bd6cff0 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -188,6 +188,7 @@ echo -e "Testing fix pins features"; run-task basic_tests/io_constraints/fix_pins $@ run-task basic_tests/io_constraints/example_pcf $@ run-task basic_tests/io_constraints/empty_pcf $@ +run-task basic_tests/io_constraints/pcf_ql_style $@ echo -e "Testing project templates"; run-task template_tasks/vpr_blif_template $@ diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv index ba0691940..9b7206eba 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/pinmap_k4_N4_tileable_40nm.csv @@ -1,17 +1,17 @@ orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge -TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, -TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, -RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, -RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, -BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, -BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, -LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, -LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf index b16acaecc..131d6246a 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/empty_pcf/config/task.conf @@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=explicit [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv index ba0691940..9b7206eba 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/pinmap_k4_N4_tileable_40nm.csv @@ -1,17 +1,17 @@ orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge -TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, -TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, -TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, -TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, -TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, -RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, -RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, -RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, -BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, -BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, -LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, -LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],in,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],out,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],in,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],out,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],in,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],out,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],in,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],out,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],in,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],out,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],in,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],out,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],in,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],out,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf index b16acaecc..131d6246a 100644 --- a/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/io_constraints/example_pcf/config/task.conf @@ -25,6 +25,7 @@ openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=explicit [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf new file mode 100644 index 000000000..839f8a857 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/and2.pcf @@ -0,0 +1,3 @@ +set_io a pad_fpga_io[0] +set_io b pad_fpga_io[4] +set_io c pad_fpga_io[6] diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml new file mode 100644 index 000000000..03eb56357 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/fpga_io_location.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv new file mode 100644 index 000000000..ba0691940 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/pinmap_k4_N4_tileable_40nm.csv @@ -0,0 +1,17 @@ +orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge +TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, +TOP,,,,gfpga_pad_IO_A2F[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_F2A[2],pad_fpga_io[1],,, +TOP,,,,gfpga_pad_IO_A2F[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_F2A[1],pad_fpga_io[2],,, +TOP,,,,gfpga_pad_IO_A2F[3],pad_fpga_io[3],,, +TOP,,,,gfpga_pad_IO_F2A[3],pad_fpga_io[3],,, +RIGHT,,,,gfpga_pad_IO_A2F[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_F2A[5],pad_fpga_io[4],,, +RIGHT,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[5],,, +RIGHT,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[5],,, +BOTTOM,,,,gfpga_pad_IO_A2F[6],pad_fpga_io[6],,, +BOTTOM,,,,gfpga_pad_IO_F2A[6],pad_fpga_io[6],,, +LEFT,,,,gfpga_pad_IO_F2A[7],pad_fpga_io[7],,, +LEFT,,,,gfpga_pad_IO_A2F[7],pad_fpga_io[7],,, diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf new file mode 100644 index 000000000..cc57345e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/pcf_ql_style/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_pcf=${PATH:TASK_DIR}/config/and2.pcf +openfpga_io_map_file=${PATH:TASK_DIR}/config/fpga_io_location.xml +openfpga_pin_table=${PATH:TASK_DIR}/config/pinmap_k4_N4_tileable_40nm.csv +openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=quicklogic + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From c4de6655b6959d491b888b26f2f4fc9aa099c7e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:26:21 -0700 Subject: [PATCH 12/18] [engine] bug --- openfpga/src/base/openfpga_setup_command.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_setup_command.cpp b/openfpga/src/base/openfpga_setup_command.cpp index ec8252aca..08e9c7497 100644 --- a/openfpga/src/base/openfpga_setup_command.cpp +++ b/openfpga/src/base/openfpga_setup_command.cpp @@ -533,7 +533,7 @@ static ShellCommandId add_openfpga_pcf2place_command( shell_cmd.add_option("pin_table_direction_convention", false, "the convention to follow when inferring pin " "direction from the name of ports in pin table file"); - shell_cmd.set_option_require_value(opt_fpga_fix_pins_file, + shell_cmd.set_option_require_value(opt_pin_table_dir_convention, openfpga::OPT_STRING); /* Add an option '--no_time_stamp' */ From 70b0d2e505a56b91da6c1779fcf0bcce14622d7c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:32:00 -0700 Subject: [PATCH 13/18] [doc] update pin table file format for pin direction keywords --- .../manual/file_formats/pin_table_file.rst | 38 ++++++++++--------- .../openfpga_commands/setup_commands.rst | 2 + 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/docs/source/manual/file_formats/pin_table_file.rst b/docs/source/manual/file_formats/pin_table_file.rst index 033f7c9b7..46b316e7b 100644 --- a/docs/source/manual/file_formats/pin_table_file.rst +++ b/docs/source/manual/file_formats/pin_table_file.rst @@ -14,22 +14,22 @@ An example of the file is shown as follows. .. code-block:: xml orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge - TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],,, - TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],,, - TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],,, - TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],,, - TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],,, - TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],,, - TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],,, - TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],,, - RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],,, - RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],,, - RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],,, - RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,, - BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,, - BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,, - LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,, - LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,, + TOP,,,,gfpga_pad_IO_A2F[0],pad_fpga_io[0],in,, + TOP,,,,gfpga_pad_IO_F2A[0],pad_fpga_io[0],out,, + TOP,,,,gfpga_pad_IO_A2F[4],pad_fpga_io[1],in,, + TOP,,,,gfpga_pad_IO_F2A[4],pad_fpga_io[1],out,, + TOP,,,,gfpga_pad_IO_A2F[8],pad_fpga_io[2],in,, + TOP,,,,gfpga_pad_IO_F2A[8],pad_fpga_io[2],out,, + TOP,,,,gfpga_pad_IO_A2F[31],pad_fpga_io[3],in,, + TOP,,,,gfpga_pad_IO_F2A[31],pad_fpga_io[3],out,, + RIGHT,,,,gfpga_pad_IO_A2F[32],pad_fpga_io[4],in,, + RIGHT,,,,gfpga_pad_IO_F2A[32],pad_fpga_io[4],out,, + RIGHT,,,,gfpga_pad_IO_A2F[40],pad_fpga_io[5],in,, + RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],out,, + BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],in,, + BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],out,, + LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],in,, + LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],out,, An pin table may serve in various purposes. However, for OpenFPGA, the following attributes are required @@ -45,4 +45,8 @@ An pin table may serve in various purposes. However, for OpenFPGA, the following Specify the pin name of the FPGA chip -.. warning:: Currently, the direction of the port is inferred by the ``port_name``. A postfix of ``A2F`` indicates an input port, while a postfix of ``F2A`` indicates an output port. +.. option:: GPIO_type + + Specify the pin direction. Can be [``in``|``out``]. + + .. note:: This column can be left as empty if users follow quicklogic style. See details in :ref:`openfpga_setup_commands_pcf2place` diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 7e84351da..9c05ee00c 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -267,6 +267,8 @@ write_fabric_io_info .. note:: This file is designed for pin constraint file conversion. +.. _openfpga_setup_commands_pcf2place: + pcf2place ~~~~~~~~~ From c3f180372debbc34a6d0110211db7a28f27c64ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:42:22 -0700 Subject: [PATCH 14/18] [engine] do not error out when ql-style is used in pin table --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 33 ++++++++++---------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index a3f3f775a..9431ee579 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -80,24 +80,25 @@ IoPinTable read_csv_io_pin_table( "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); exit(1); } + + /* Parse pin direction from a specific column, this has a higher priority + * than inferring from pin names */ + std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); + if (port_dir_str == std::string(DIRECTION_INPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else if (pin_dir_convention == + e_pin_table_direction_convention::EXPLICIT) { + /* Error out only when we need explicit port direction */ + VTR_LOG( + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", + DIRECTION_INPUT, DIRECTION_OUTPUT); + exit(1); + } } - /* Parse pin direction from a specific column, this has a higher priority - * than inferring from pin names */ - std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); - if (port_dir_str == std::string(DIRECTION_INPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); - } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); - } else { - VTR_LOG( - "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", - DIRECTION_INPUT, DIRECTION_OUTPUT); - exit(1); - } + return io_pin_table; } - return io_pin_table; -} - } /* End namespace openfpga*/ From 76862efa5703b3c4c13d44011f7007ee8207b545 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:46:19 -0700 Subject: [PATCH 15/18] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 29 ++++++++++---------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 9431ee579..1138aeb5a 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -81,21 +81,20 @@ IoPinTable read_csv_io_pin_table( exit(1); } - /* Parse pin direction from a specific column, this has a higher priority - * than inferring from pin names */ - std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); - if (port_dir_str == std::string(DIRECTION_INPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); - } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { - io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); - } else if (pin_dir_convention == - e_pin_table_direction_convention::EXPLICIT) { - /* Error out only when we need explicit port direction */ - VTR_LOG( - "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", - DIRECTION_INPUT, DIRECTION_OUTPUT); - exit(1); - } + /* Parse pin direction from a specific column, this has a higher priority + * than inferring from pin names */ + std::string port_dir_str = row_vec.at(ROW_INDEX_DIRECTION); + if (port_dir_str == std::string(DIRECTION_INPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT); + } else if (port_dir_str == std::string(DIRECTION_OUTPUT)) { + io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT); + } else if (pin_dir_convention == + e_pin_table_direction_convention::EXPLICIT) { + /* Error out only when we need explicit port direction */ + VTR_LOG( + "Invalid direction defintion! Expect [%s|%s] in the GPIO direction\n", + DIRECTION_INPUT, DIRECTION_OUTPUT); + exit(1); } return io_pin_table; From 60c448c98dbf16975db4acbbcfd5b9057f7415c7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 15:49:34 -0700 Subject: [PATCH 16/18] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 1138aeb5a..9df012290 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -80,6 +80,7 @@ IoPinTable read_csv_io_pin_table( "Invalid direction defintion! Expect [A2F|F2A] in the pin name\n"); exit(1); } + } /* Parse pin direction from a specific column, this has a higher priority * than inferring from pin names */ From c9631497e2a2ef923df201857e341f2e16ab6f75 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 16:11:49 -0700 Subject: [PATCH 17/18] [engine] syntax --- libs/libpcf/src/io/read_csv_io_pin_table.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/libs/libpcf/src/io/read_csv_io_pin_table.cpp b/libs/libpcf/src/io/read_csv_io_pin_table.cpp index 9df012290..6c7c2cc3f 100644 --- a/libs/libpcf/src/io/read_csv_io_pin_table.cpp +++ b/libs/libpcf/src/io/read_csv_io_pin_table.cpp @@ -97,8 +97,9 @@ IoPinTable read_csv_io_pin_table( DIRECTION_INPUT, DIRECTION_OUTPUT); exit(1); } - - return io_pin_table; } + return io_pin_table; +} + } /* End namespace openfpga*/ From 00a485cbeb63f7e10331a52f3cb57011a8b2612b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 17 Oct 2022 19:44:25 -0700 Subject: [PATCH 18/18] [test] add missing file --- .../io_constraints/fix_pins/config/and2_fix_pins.place | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place diff --git a/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place new file mode 100644 index 000000000..5f24ccebe --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/io_constraints/fix_pins/config/and2_fix_pins.place @@ -0,0 +1,3 @@ +a 0 1 0 +b 2 0 3 +out:c 1 3 7