riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,621 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

3621 Commits

Author SHA1 Message Date
tangxifan ed9b567d19
Merge branch 'master' into doc_patch 2021-03-18 22:34:43 -06:00
ganeshgore 35567fb3c3
Merge pull request #272 from lnis-uofu/yosys_heterogeneous_block_support 
Yosys heterogeneous block support
 2021-03-18 16:17:55 -06:00
tangxifan 73e37060a5
Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-18 15:14:24 -06:00
tangxifan 3c1e3ed400
Merge branch 'master' into doc_patch 2021-03-18 15:14:05 -06:00
ganeshgore a8f06db62f
Merge pull request #270 from lnis-uofu/netlist_name_patch 
Name grid module pins in Verilog netlist with architecture port defintion
 2021-03-18 15:13:13 -06:00
tangxifan 3ef292bdbb Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch 2021-03-17 20:28:40 -06:00
tangxifan fa11410425 [Tool] Remove exceptions on outputing verilog port with lsb=0 2021-03-17 20:27:08 -06:00
tangxifan d22d935322 [CI] Update regressiont tests run in CI script 2021-03-17 16:08:33 -06:00
tangxifan 6bf4880c50 [benchmark] Add vtr benchmark 2021-03-17 15:24:26 -06:00
tangxifan 7a986defba [CI] Deploy vtr benchmark regression test to CI 2021-03-17 15:15:54 -06:00
tangxifan f9dc7c1b54 [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells 2021-03-17 15:15:22 -06:00
tangxifan 08a86e056a [Test] Add vtr benchmark regression test 2021-03-17 15:13:58 -06:00
tangxifan 7eeb35d21f [Script] Bug fix in yosys script to synthesis BRAM 2021-03-17 15:12:04 -06:00
tangxifan 1976a8068f [Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added) 2021-03-17 15:11:17 -06:00
tangxifan deee7ba366 [Script] Add example script to run vtr benchmarks 2021-03-17 15:10:56 -06:00
tangxifan 910f8471dd [Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys) 2021-03-17 15:10:05 -06:00
tangxifan 76113a80fa [HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture 2021-03-17 15:09:12 -06:00
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan d12a8a03fd [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
tangxifan 094b3e9b90 [Script] Use parameters in template yosys script supporting BRAMs 2021-03-16 19:51:48 -06:00
tangxifan cea43c2c45 [HDL] Add SPRAM module to generic yosys tech lib for openfpga usage 2021-03-16 18:04:31 -06:00
tangxifan 73b06256d0 [Test] Deploy the new yosys script supporting BRAM to regression tests 2021-03-16 16:52:59 -06:00
tangxifan 84778bd38d [Script] Add new yosys script to support architectures with BRAMs 2021-03-16 16:52:18 -06:00
tangxifan 090f483a11 [Script] Now task-run script support the use of env variables openfpga_path in yosys scripts 2021-03-16 16:45:57 -06:00
tangxifan 76837e02e6 [Script] Rename yosys script supporting bram and restructure techlib files 2021-03-16 16:16:53 -06:00
tangxifan 19b2641839
Merge branch 'master' into doc_patch 2021-03-15 11:45:32 -06:00
tangxifan fb7d76545e [Doc] Patch the schematic of LUT circuit models to be consistent with netlists 2021-03-15 11:40:09 -06:00
tangxifan 87006e1374
Merge branch 'master' into netlist_name_patch 2021-03-15 10:06:24 -06:00
tangxifan 063c58b6cb
Merge pull request #266 from lnis-uofu/ganesh_dev 
[Task/Flow] Extended Yosys support in OpenFPGA task
 2021-03-15 10:06:11 -06:00
tangxifan d2fbda4070
Merge branch 'master' into netlist_name_patch 2021-03-15 09:13:04 -06:00
tangxifan b080bcf018
Merge branch 'master' into ganesh_dev 2021-03-15 09:12:50 -06:00
tangxifan fcfe143f2f
Merge pull request #257 from antmicro/enhanced_gsb_dump 
GSB dump enhancement
 2021-03-15 09:12:19 -06:00
Maciej Kurc 66745a85f2 Fixed an issue with the CI workflow 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-03-15 09:29:37 +01:00
Maciej Kurc 02967f2870 Added writing rr graph node indices to GSB dump. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-03-15 09:28:38 +01:00
tangxifan c8d41b4e69 [Tool] Change routing module port naming to include architecture port names 2021-03-14 19:35:49 -06:00
tangxifan 956b9aca01 [Tool] Trim dead codes in port naming function 2021-03-13 20:23:08 -07:00
tangxifan 2c5634ee76 [Tool] Change pin naming of grid modules to be related to architecture port names 2021-03-13 20:05:18 -07:00
tangxifan e61857aa2b
Merge branch 'master' into ganesh_dev 2021-03-11 19:17:02 -07:00
tangxifan 74785f328c
Merge pull request #263 from lnis-uofu/yosys_bump 
update yosys submodule with ff and shift register mapping support for quicklogic architecture
 2021-03-11 19:16:40 -07:00
tangxifan 366bec232c [Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI 2021-03-11 15:25:48 -07:00
tangxifan bb2a02c9ad [HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v] 2021-03-11 15:23:14 -07:00
tangxifan baf162e401 [Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification 2021-03-10 22:45:19 -07:00
tangxifan ff0faeb285 [Doc] Update documentation about the extended bitstream setting 2021-03-10 21:41:59 -07:00
tangxifan d877a02534 [Tool] Patch the extended bitstream setting support on mode-select bits 2021-03-10 21:28:09 -07:00
tangxifan 85640a7403 [Tool] Extend bitstream setting to support mode bits overload from eblif file 2021-03-10 20:45:48 -07:00
tangxifan a6186db315 [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
tangxifan 7d07f5d8cb [Test] Update bitstream setting example with mode bit overwriting 2021-03-10 15:34:53 -07:00
tangxifan b42541d84e [Flow] Support multiple iterations in rewriting yosys scripts 2021-03-10 14:10:35 -07:00
tangxifan 90a00da1df [Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset' 2021-03-10 13:56:35 -07:00
tangxifan d21909ad6c [Test] Use custom rewriting script in lut_adder test 2021-03-10 13:48:20 -07:00