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Merge branch 'master' into doc_patch

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tangxifan 2021-03-18 15:14:05 -06:00 committed by GitHub
parent 19b2641839 a8f06db62f
commit 3c1e3ed400
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29 changed files with 628 additions and 209 deletions
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48
openfpga/src/annotation/annotate_physical_tiles.cpp Normal file
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@ -0,0 +1,48 @@
/********************************************************************
* This file includes functions to build links between pb_types
* in particular to annotate the physical mode and physical pb_type
*******************************************************************/
/* Headers from vtrutil library */
#include "vtr_time.h"
#include "vtr_assert.h"
#include "vtr_log.h"
#include "annotate_physical_tiles.h"
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Build the fast look-up for each physical tile between
* pin index and the physical port information, i.e., port name and port index
*******************************************************************/
void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx,
VprDeviceAnnotation& vpr_device_annotation) {
vtr::ScopedStartFinishTimer timer("Build fast look-up for physical tile pins");
for (const t_physical_tile_type& physical_tile : vpr_device_ctx.physical_tile_types) {
/* Count the number of pins for each sub tile */
int num_pins_per_subtile = 0;
for (const t_physical_tile_port& tile_port : physical_tile.ports) {
num_pins_per_subtile += tile_port.num_pins;
}
/* For each sub tile, the starting pin index is (num_pins_per_subtile * index) + abs_index */
for (int subtile_index = 0; subtile_index < physical_tile.capacity; ++subtile_index) {
for (const t_physical_tile_port& tile_port : physical_tile.ports) {
for (int pin_index = 0; pin_index < tile_port.num_pins; ++pin_index) {
int absolute_pin_index = subtile_index * num_pins_per_subtile + tile_port.absolute_first_pin_index + pin_index;
BasicPort tile_port_info(tile_port.name, pin_index, pin_index);
vpr_device_annotation.add_physical_tile_pin2port_info_pair(&physical_tile,
absolute_pin_index,
tile_port_info);
vpr_device_annotation.add_physical_tile_pin_subtile_index(&physical_tile,
absolute_pin_index,
subtile_index);
}
}
}
}
}
} /* end namespace openfpga */

23
openfpga/src/annotation/annotate_physical_tiles.h Normal file
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@ -0,0 +1,23 @@
#ifndef ANNOTATE_PHYSICAL_TILES_H
#define ANNOTATE_PHYSICAL_TILES_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include "vpr_context.h"
#include "openfpga_context.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
void build_physical_tile_pin2port_info(const DeviceContext& vpr_device_ctx,
VprDeviceAnnotation& vpr_device_annotation);
} /* end namespace openfpga */
#endif

52
openfpga/src/annotation/vpr_device_annotation.cpp
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@ -278,6 +278,46 @@ LbRRGraph VprDeviceAnnotation::physical_lb_rr_graph(t_pb_graph_node* pb_graph_he
return physical_lb_rr_graphs_.at(pb_graph_head);
}
BasicPort VprDeviceAnnotation::physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const {
/* Try to find the physical tile in the fast look-up */
auto physical_tile_search_result = physical_tile_pin2port_info_map_.find(physical_tile);
if (physical_tile_search_result == physical_tile_pin2port_info_map_.end()) {
/* Not found. Return an invalid port */
return BasicPort();
}
/* Try to find the physical tile port info with pin index */
auto pin_search_result = physical_tile_search_result->second.find(pin_index);
if (pin_search_result == physical_tile_search_result->second.end()) {
/* Not found. Return an invalid port */
return BasicPort();
}
/* Reach here, we should find a port. Return the port information */
return pin_search_result->second;
}
int VprDeviceAnnotation::physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const {
/* Try to find the physical tile in the fast look-up */
auto physical_tile_search_result = physical_tile_pin_subtile_indices_.find(physical_tile);
if (physical_tile_search_result == physical_tile_pin_subtile_indices_.end()) {
/* Not found. Return an invalid index */
return -1;
}
/* Try to find the physical tile port info with pin index */
auto pin_search_result = physical_tile_search_result->second.find(pin_index);
if (pin_search_result == physical_tile_search_result->second.end()) {
/* Not found. Return an invalid index */
return -1;
}
/* Reach here, we should find a port. Return the port information */
return pin_search_result->second;
}
/************************************************************************
* Public mutators
***********************************************************************/
@ -533,4 +573,16 @@ void VprDeviceAnnotation::add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_hea
physical_lb_rr_graphs_[pb_graph_head] = lb_rr_graph;
}
void VprDeviceAnnotation::add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const BasicPort& port) {
physical_tile_pin2port_info_map_[physical_tile][pin_index] = port;
}
void VprDeviceAnnotation::add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const int& subtile_index) {
physical_tile_pin_subtile_indices_[physical_tile][pin_index] = subtile_index;
}
} /* End namespace openfpga*/

15
openfpga/src/annotation/vpr_device_annotation.h
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@ -81,6 +81,10 @@ class VprDeviceAnnotation {
CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
ArchDirectId direct_annotation(const size_t& direct) const;
LbRRGraph physical_lb_rr_graph(t_pb_graph_node* pb_graph_head) const;
BasicPort physical_tile_pin_port_info(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const;
int physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index) const;
public: /* Public mutators */
void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
@ -110,6 +114,12 @@ class VprDeviceAnnotation {
void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
void add_direct_annotation(const size_t& direct, const ArchDirectId& arch_direct_id);
void add_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head, const LbRRGraph& lb_rr_graph);
void add_physical_tile_pin2port_info_pair(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const BasicPort& port);
void add_physical_tile_pin_subtile_index(t_physical_tile_type_ptr physical_tile,
const int& pin_index,
const int& subtile_index);
private: /* Internal data */
/* Pair a regular pb_type to its physical pb_type */
std::map<t_pb_type*, t_pb_type*> physical_pb_types_;
@ -197,6 +207,11 @@ class VprDeviceAnnotation {
/* Logical type routing resource graphs built from physical modes */
std::map<t_pb_graph_node*, LbRRGraph> physical_lb_rr_graphs_;
/* A fast look-up from pin index in physical tile to physical tile port */
std::map<t_physical_tile_type_ptr, std::map<int, BasicPort>> physical_tile_pin2port_info_map_;
/* A fast look-up from pin index in physical tile to sub tile index */
std::map<t_physical_tile_type_ptr, std::map<int, int>> physical_tile_pin_subtile_indices_;
};
} /* End namespace openfpga*/

5
openfpga/src/base/openfpga_link_arch.cpp
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@ -16,6 +16,7 @@
#include "vpr_device_annotation.h"
#include "pb_type_utils.h"
#include "annotate_physical_tiles.h"
#include "annotate_pb_types.h"
#include "annotate_pb_graph.h"
#include "annotate_routing.h"
@ -72,6 +73,10 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_sort_edge = cmd.option("sort_gsb_chan_node_in_edges");
CommandOptionId opt_verbose = cmd.option("verbose");
/* Build fast look-up between physical tile pin index and port information */
build_physical_tile_pin2port_info(g_vpr_ctx.device(),
openfpga_ctx.mutable_vpr_device_annotation());
/* Annotate pb_type graphs
* - physical pb_type
* - mode selection bits for pb_type and pb interconnect

148
openfpga/src/base/openfpga_naming.cpp
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@ -505,36 +505,26 @@ std::string generate_connection_block_module_name(const t_rr_type& cb_type,
* This function will generate a full port name including coordinates
* so that each pin in top-level netlists is unique!
*********************************************************************/
std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
const size_t& width,
std::string generate_grid_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const size_t& pin_id,
const bool& for_top_netlist) {
if (true == for_top_netlist) {
std::string port_name = std::string("grid_");
port_name += std::to_string(coordinate.x());
port_name += std::string("__");
port_name += std::to_string(coordinate.y());
port_name += std::string("__pin_");
port_name += std::to_string(height);
port_name += std::string("__");
port_name += std::to_string(size_t(side));
port_name += std::string("__");
port_name += std::to_string(pin_id);
port_name += std::string("_");
return port_name;
}
/* For non-top netlist */
VTR_ASSERT( false == for_top_netlist );
const BasicPort& pin_info) {
/* Ensure that the pin is 1-bit ONLY !!! */
VTR_ASSERT(1 == pin_info.get_width());
SideManager side_manager(side);
std::string port_name = std::string(side_manager.to_string());
port_name += std::string("_width_");
port_name += std::to_string(width);
port_name += std::string("_height_");
port_name += std::to_string(height);
port_name += std::string("_subtile_");
port_name += std::to_string(subtile_index);
port_name += std::string("__pin_");
port_name += std::to_string(pin_id);
port_name += pin_info.get_name();
port_name += std::string("_");
port_name += std::to_string(pin_info.get_lsb());
port_name += std::string("_");
return port_name;
}
@ -547,18 +537,25 @@ std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
*********************************************************************/
std::string generate_grid_duplicated_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const size_t& pin_id,
const BasicPort& pin_info,
const bool& upper_port) {
/* For non-top netlist */
/* Ensure that the pin is 1-bit ONLY !!! */
VTR_ASSERT(1 == pin_info.get_width());
SideManager side_manager(side);
std::string port_name = std::string(side_manager.to_string());
port_name += std::string("_width_");
port_name += std::to_string(width);
port_name += std::string("_height_");
port_name += std::to_string(height);
port_name += std::string("_subtile_");
port_name += std::to_string(subtile_index);
port_name += std::string("__pin_");
port_name += std::to_string(pin_id);
port_name += pin_info.get_name();
port_name += std::string("_");
port_name += std::to_string(pin_info.get_lsb());
port_name += std::string("_");
if (true == upper_port) {
@ -571,106 +568,19 @@ std::string generate_grid_duplicated_port_name(const size_t& width,
return port_name;
}
/*********************************************************************
* Generate the port name for a grid in the context of a module
* Generate the port name for a grid in the context of a routing module
* To keep a short and simple name, this function will not
* include any grid coorindate information!
*********************************************************************/
std::string generate_grid_module_port_name(const size_t& pin_id) {
**********************************************************************/
std::string generate_routing_module_grid_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const BasicPort& pin_info) {
/* For non-top netlist */
std::string port_name = std::string("grid_");
port_name += std::string("pin_");
port_name += std::to_string(pin_id);
port_name += std::string("_");
return port_name;
}
/*********************************************************************
* Generate the port name for a Grid
* This is a wrapper function for generate_port_name()
* which can automatically decode the port name by the pin side and height
*********************************************************************/
std::string generate_grid_side_port_name(const DeviceGrid& grids,
const vtr::Point<size_t>& coordinate,
const e_side& side,
const size_t& pin_id) {
/* Output the pins on the side*/
size_t width = grids[coordinate.x()][coordinate.y()].type->pin_width_offset[pin_id];
size_t height = grids[coordinate.x()][coordinate.y()].type->pin_height_offset[pin_id];
if (true != grids[coordinate.x()][coordinate.y()].type->pinloc[width][height][side][pin_id]) {
SideManager side_manager(side);
VTR_LOG_ERROR("Fail to generate a grid pin (x=%lu, y=%lu, width=%lu, height=%lu, side=%s, index=%d)\n",
coordinate.x(), coordinate.y(), width, height, side_manager.c_str(), pin_id);
exit(1);
}
return generate_grid_port_name(coordinate, width, height, side, pin_id, true);
}
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*
* The prefix is created by considering the the grid coordinate
* and switch block coordinate
* Detailed rules in conversion is as follows:
*
* top_left top_right
* +------------------------+
* left_top | | right_top
* | Switch Block |
* | [x][y] |
* | |
* | |
* left_right | | right_bottom
* +------------------------+
* bottom_left bottom_right
*
* +--------------------------------------------------------
* | Grid Coordinate | Pin side of grid | module side
* +--------------------------------------------------------
* | [x][y+1] | right | top_left
* +--------------------------------------------------------
* | [x][y+1] | bottom | left_top
* +--------------------------------------------------------
* | [x+1][y+1] | left | top_right
* +--------------------------------------------------------
* | [x+1][y+1] | bottom | right_top
* +--------------------------------------------------------
* | [x][y] | top | left_right
* +--------------------------------------------------------
* | [x][y] | right | bottom_left
* +--------------------------------------------------------
* | [x+1][y] | top | right_bottom
* +--------------------------------------------------------
* | [x+1][y] | left | bottom_right
* +--------------------------------------------------------
*
*********************************************************************/
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const size_t& pin_id) {
SideManager sb_side_manager(sb_side);
SideManager grid_side_manager(grid_side);
/* Relative location is opposite to the side in grid context */
grid_side_manager.set_opposite();
std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string();
return prefix + std::string("_") + generate_grid_module_port_name(pin_id);
}
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*********************************************************************/
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const size_t& pin_id) {
SideManager side_manager(cb_side);
std::string prefix = side_manager.to_string();
return prefix + std::string("_") + generate_grid_module_port_name(pin_id);
return port_name + generate_grid_port_name(width, height, subtile_index, side, pin_info);
}
/*********************************************************************

29
openfpga/src/base/openfpga_naming.h
View File

@ -15,6 +15,7 @@
#include "vtr_geometry.h"
#include "circuit_library.h"
#include "device_grid.h"
#include "openfpga_port.h"
/********************************************************************
* Function declaration
@ -134,32 +135,24 @@ std::string generate_pb_memory_instance_name(const std::string& prefix,
t_pb_graph_pin* pb_graph_pin,
const std::string& postfix);
std::string generate_grid_port_name(const vtr::Point<size_t>& coordinate,
const size_t& width,
std::string generate_grid_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const size_t& pin_id,
const bool& for_top_netlist);
const BasicPort& pin_info);
std::string generate_grid_duplicated_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const size_t& pin_id,
const BasicPort& pin_info,
const bool& upper_port);
std::string generate_grid_module_port_name(const size_t& pin_id);
std::string generate_grid_side_port_name(const DeviceGrid& grids,
const vtr::Point<size_t>& coordinate,
const e_side& side,
const size_t& pin_id);
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const size_t& pin_id);
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const size_t& pin_id);
std::string generate_routing_module_grid_port_name(const size_t& width,
const size_t& height,
const int& subtile_index,
const e_side& side,
const BasicPort& pin_info);
std::string generate_reserved_sram_port_name(const e_circuit_model_port_type& port_type);

1
openfpga/src/fabric/build_device_module.cpp
View File

@ -113,6 +113,7 @@ int build_device_module_graph(ModuleManager& module_manager,
status = build_top_module(module_manager,
decoder_lib,
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.vpr_device_annotation(),
vpr_device_ctx.grid,
openfpga_ctx.arch().tile_annotations,
vpr_device_ctx.rr_graph,

31
openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
View File

@ -55,6 +55,7 @@ namespace openfpga {
*******************************************************************/
void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
@ -87,6 +88,11 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
/* Reach here, it means this pin is on this side */
int class_id = grid_type_descriptor->pin_class[ipin];
e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type;
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
/* Generate the pin name
* For each RECEIVER PIN or DRIVER PIN for direct connection,
* we do not duplicate in these cases */
@ -94,8 +100,7 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
/* Xifan: I assume that each direct connection pin must have Fc=0. */
|| ( (DRIVER == pin_class_type)
&& (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)) ) ) {
vtr::Point<size_t> dummy_coordinate;
std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info);
BasicPort grid_port(port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
@ -105,12 +110,12 @@ void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
* The other with a postfix of lower, indicating it is located on the lower part of a side
*/
VTR_ASSERT(DRIVER == pin_class_type);
std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, true);
std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, subtile_index, side, pin_info, true);
BasicPort grid_upper_port(upper_port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]);
std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, false);
std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, subtile_index, side, pin_info, false);
BasicPort grid_lower_port(lower_port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]);
@ -134,6 +139,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
const ModuleId& grid_module,
const ModuleId& child_module,
const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
t_pb_graph_pin* pb_graph_pin,
const e_side& border_side,
@ -162,6 +168,12 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
int pin_width = grid_type_descriptor->pin_width_offset[grid_pin_index];
int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
for (const e_side& side : grid_pin_sides) {
if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) {
continue;
@ -175,8 +187,7 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
/* Create a net to connect the grid pin to child module pin */
ModuleNetId net = module_manager.create_module_net(grid_module);
/* Find the port in grid_module */
vtr::Point<size_t> dummy_coordinate;
std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false);
std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info);
ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
@ -200,12 +211,12 @@ void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_m
/* Create a net to connect the grid pin to child module pin */
ModuleNetId net = module_manager.create_module_net(grid_module);
/* Find the upper port in grid_module */
std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, true);
std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, subtile_index, side, pin_info, true);
ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id));
/* Find the lower port in grid_module */
std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, false);
std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, subtile_index, side, pin_info, false);
ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id));
@ -238,6 +249,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module
const ModuleId& grid_module,
const ModuleId& child_module,
const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
@ -251,6 +263,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module
for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) {
add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
child_module, child_instance,
vpr_device_annotation,
grid_type_descriptor,
&(top_pb_graph_node->input_pins[iport][ipin]),
border_side,
@ -263,6 +276,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module
for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) {
add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module,
child_module, child_instance,
vpr_device_annotation,
grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]),
border_side,
@ -274,6 +288,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module
for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) {
add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
child_module, child_instance,
vpr_device_annotation,
grid_type_descriptor,
&(top_pb_graph_node->clock_pins[iport][ipin]),
border_side,

3
openfpga/src/fabric/build_grid_module_duplicated_pins.h
View File

@ -6,6 +6,7 @@
*******************************************************************/
#include "physical_types.h"
#include "module_manager.h"
#include "vpr_device_annotation.h"
#include "openfpga_side_manager.h"
/********************************************************************
@ -17,6 +18,7 @@ namespace openfpga {
void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const e_side& border_side);
@ -24,6 +26,7 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module
const ModuleId& grid_module,
const ModuleId& child_module,
const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const e_side& border_side);

8
openfpga/src/fabric/build_grid_module_utils.cpp
View File

@ -46,6 +46,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
const ModuleId& grid_module,
const ModuleId& child_module,
const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
t_pb_graph_pin* pb_graph_pin,
const e_side& border_side,
@ -78,8 +79,11 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
/* Create a net to connect the grid pin to child module pin */
ModuleNetId net = module_manager.create_module_net(grid_module);
/* Find the port in grid_module */
vtr::Point<size_t> dummy_coordinate;
std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false);
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, grid_pin_index);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, grid_pin_index);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
std::string grid_port_name = generate_grid_port_name(pin_width, pin_height, subtile_index, side, pin_info);
ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
/* Grid port always has only 1 pin, it is assumed when adding these ports to the module

2
openfpga/src/fabric/build_grid_module_utils.h
View File

@ -9,6 +9,7 @@
#include "openfpga_interconnect_types.h"
#include "module_manager.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
@ -24,6 +25,7 @@ void add_grid_module_net_connect_pb_graph_pin(ModuleManager& module_manager,
const ModuleId& grid_module,
const ModuleId& child_module,
const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
t_pb_graph_pin* pb_graph_pin,
const e_side& border_side,

19
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -41,6 +41,7 @@ namespace openfpga {
static
void add_grid_module_pb_type_ports(ModuleManager& module_manager,
const ModuleId& grid_module,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
@ -76,8 +77,11 @@ void add_grid_module_pb_type_ports(ModuleManager& module_manager,
/* Generate the pin name,
* we give a empty coordinate but it will not be used (see details in the function
*/
vtr::Point<size_t> dummy_coordinate;
std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, ipin);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, ipin);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
std::string port_name = generate_grid_port_name(iwidth, iheight, subtile_index, side, pin_info);
BasicPort grid_port(port_name, 0, 0);
/* Add the port to the module */
module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
@ -99,6 +103,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
const ModuleId& grid_module,
const ModuleId& child_module,
const size_t& child_instance,
const VprDeviceAnnotation& vpr_device_annotation,
t_physical_tile_type_ptr grid_type_descriptor,
const e_side& border_side) {
/* Ensure that we have a valid grid_type_descriptor */
@ -112,6 +117,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) {
add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
child_module, child_instance,
vpr_device_annotation,
grid_type_descriptor,
&(top_pb_graph_node->input_pins[iport][ipin]),
border_side,
@ -124,6 +130,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) {
add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
child_module, child_instance,
vpr_device_annotation,
grid_type_descriptor,
&(top_pb_graph_node->output_pins[iport][ipin]),
border_side,
@ -135,6 +142,7 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) {
add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
child_module, child_instance,
vpr_device_annotation,
grid_type_descriptor,
&(top_pb_graph_node->clock_pins[iport][ipin]),
border_side,
@ -974,6 +982,7 @@ void rec_build_logical_tile_modules(ModuleManager& module_manager,
static
void build_physical_tile_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model,
@ -1035,6 +1044,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
if (false == duplicate_grid_pin) {
/* Default way to add these ports by following the definition in pb_types */
add_grid_module_pb_type_ports(module_manager, grid_module,
vpr_device_annotation,
phy_block_type, border_side);
/* Add module nets to connect the pb_type ports to sub modules */
for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
@ -1048,6 +1058,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) {
add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module,
pb_module, child_instance,
vpr_device_annotation,
phy_block_type, border_side);
}
}
@ -1055,6 +1066,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
VTR_ASSERT_SAFE(true == duplicate_grid_pin);
/* Add these ports with duplication */
add_grid_module_duplicated_pb_type_ports(module_manager, grid_module,
vpr_device_annotation,
phy_block_type, border_side);
/* Add module nets to connect the duplicated pb_type ports to sub modules */
@ -1069,6 +1081,7 @@ void build_physical_tile_module(ModuleManager& module_manager,
for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) {
add_grid_module_nets_connect_duplicated_pb_type_ports(module_manager, grid_module,
pb_module, child_instance,
vpr_device_annotation,
phy_block_type, border_side);
}
}
@ -1186,6 +1199,7 @@ void build_grid_modules(ModuleManager& module_manager,
&physical_tile);
for (const e_side& io_type_side : io_type_sides) {
build_physical_tile_module(module_manager, decoder_lib,
device_annotation,
circuit_lib,
sram_orgz_type, sram_model,
&physical_tile,
@ -1196,6 +1210,7 @@ void build_grid_modules(ModuleManager& module_manager,
} else {
/* For CLB and heterogenenous blocks */
build_physical_tile_module(module_manager, decoder_lib,
device_annotation,
circuit_lib,
sram_orgz_type, sram_model,
&physical_tile,

117
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -10,6 +10,7 @@
#include "vtr_assert.h"
#include "vtr_geometry.h"
#include "openfpga_side_manager.h"
#include "openfpga_naming.h"
#include "build_routing_module_utils.h"
@ -17,6 +18,104 @@
/* begin namespace openfpga */
namespace openfpga {
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*
* The prefix is created by considering the the grid coordinate
* and switch block coordinate
* Detailed rules in conversion is as follows:
*
* top_left top_right
* +------------------------+
* left_top | | right_top
* | Switch Block |
* | [x][y] |
* | |
* | |
* left_right | | right_bottom
* +------------------------+
* bottom_left bottom_right
*
* +--------------------------------------------------------
* | Grid Coordinate | Pin side of grid | module side
* +--------------------------------------------------------
* | [x][y+1] | right | top_left
* +--------------------------------------------------------
* | [x][y+1] | bottom | left_top
* +--------------------------------------------------------
* | [x+1][y+1] | left | top_right
* +--------------------------------------------------------
* | [x+1][y+1] | bottom | right_top
* +--------------------------------------------------------
* | [x][y] | top | left_right
* +--------------------------------------------------------
* | [x][y] | right | bottom_left
* +--------------------------------------------------------
* | [x+1][y] | top | right_bottom
* +--------------------------------------------------------
* | [x+1][y] | left | bottom_right
* +--------------------------------------------------------
*
*********************************************************************/
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node) {
SideManager sb_side_manager(sb_side);
SideManager grid_side_manager(grid_side);
/* Relative location is opposite to the side in grid context */
grid_side_manager.set_opposite();
std::string prefix = sb_side_manager.to_string() + std::string("_") + grid_side_manager.to_string();
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = rr_graph.node_side(rr_node);
t_physical_tile_type_ptr physical_tile = vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type;
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, pin_id);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, pin_id);
VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity);
return prefix + std::string("_") + generate_routing_module_grid_port_name(pin_width_offset, pin_height_offset, subtile_index, pin_side, pin_info);
}
/*********************************************************************
* Generate the port name of a grid pin for a routing module,
* which could be a switch block or a connection block
* Note that to ensure unique grid port name in the context of a routing module,
* we need a prefix which denotes the relative location of the port in the routing module
*********************************************************************/
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node) {
SideManager side_manager(cb_side);
std::string prefix = side_manager.to_string();
/* Collect the attributes of the rr_node required to generate the port name */
int pin_id = rr_graph.node_pin_num(rr_node);
e_side pin_side = rr_graph.node_side(rr_node);
t_physical_tile_type_ptr physical_tile = vpr_device_grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type;
int pin_width_offset = physical_tile->pin_width_offset[pin_id];
int pin_height_offset = physical_tile->pin_height_offset[pin_id];
BasicPort pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, pin_id);
VTR_ASSERT(true == pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, pin_id);
VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity);
return prefix + std::string("_") + generate_routing_module_grid_port_name(pin_width_offset, pin_height_offset, subtile_index, pin_side, pin_info);
}
/*********************************************************************
* Find the port id and pin id for a routing track in the switch
* block module with a given rr_node
@ -64,6 +163,8 @@ ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_man
********************************************************************/
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
@ -84,7 +185,10 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
std::string input_port_name = generate_sb_module_grid_port_name(input_side,
grid_pin_side,
rr_graph.node_pin_num(input_rr_node));
grids,
vpr_device_annotation,
rr_graph,
input_rr_node);
/* Must find a valid port id in the Switch Block module */
input_port.first = module_manager.find_module_port(sb_module, input_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port.first));
@ -109,6 +213,8 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
********************************************************************/
std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes) {
@ -123,7 +229,7 @@ std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleMana
VTR_ASSERT(NUM_SIDES != input_pin_side);
VTR_ASSERT(-1 != index);
input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, input_rr_node));
input_ports.push_back(find_switch_block_module_input_port(module_manager, sb_module, grids, vpr_device_annotation, rr_graph, rr_gsb, input_pin_side, input_rr_node));
}
return input_ports;
@ -169,6 +275,8 @@ ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module
********************************************************************/
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node) {
@ -184,7 +292,10 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
/* We need to be sure that drive_rr_node is part of the CB */
VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side));
std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index)));
grids,
vpr_device_annotation,
rr_graph,
rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index));
/* Must find a valid port id in the Switch Block module */
ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name);

21
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -10,6 +10,8 @@
#include "rr_gsb.h"
#include "module_manager.h"
#include "vpr_types.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
@ -20,6 +22,19 @@ namespace openfpga {
typedef std::pair<ModulePortId, size_t> ModulePinInfo;
std::string generate_sb_module_grid_port_name(const e_side& sb_side,
const e_side& grid_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node);
std::string generate_cb_module_grid_port_name(const e_side& cb_side,
const DeviceGrid& vpr_device_grid,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRNodeId& rr_node);
ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
@ -30,6 +45,8 @@ ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_man
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
@ -37,6 +54,8 @@ ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_ma
std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes);
@ -50,6 +69,8 @@ ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const DeviceGrid& grids,
const VprDeviceAnnotation& vpr_device_annotation,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);

48
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -42,6 +42,8 @@ namespace openfpga {
static
void build_switch_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
@ -81,7 +83,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
exit(1);
}
/* Find the name of input port */
ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, grids, device_annotation, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(sb_module, input_port_info.first);
@ -102,6 +104,7 @@ static
void build_switch_block_mux_module(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
@ -137,7 +140,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name);
/* Generate input ports that are wired to the input bus of the routing multiplexer */
std::vector<ModulePinInfo> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_graph, rr_gsb, driver_rr_nodes);
std::vector<ModulePinInfo> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, grids, device_annotation, rr_graph, rr_gsb, driver_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
@ -211,6 +214,7 @@ static
void build_switch_block_interc_modules(ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const CircuitLibrary& circuit_lib,
@ -234,6 +238,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
if (0 == driver_rr_nodes.size()) {
/* Print a special direct connection*/
build_switch_block_module_short_interc(module_manager, sb_module,
device_annotation,
grids,
rr_graph, rr_gsb,
chan_side, cur_rr_node,
cur_rr_node,
@ -241,6 +247,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
} else if (1 == driver_rr_nodes.size()) {
/* Print a direct connection*/
build_switch_block_module_short_interc(module_manager, sb_module,
device_annotation,
grids,
rr_graph, rr_gsb, chan_side, cur_rr_node,
driver_rr_nodes[0],
input_port_to_module_nets);
@ -249,7 +257,8 @@ void build_switch_block_interc_modules(ModuleManager& module_manager,
std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node);
VTR_ASSERT(1 == driver_switches.size());
build_switch_block_mux_module(module_manager,
sb_module, device_annotation, rr_graph, rr_gsb,
sb_module, device_annotation,
grids, rr_graph, rr_gsb,
circuit_lib,
chan_side, chan_node_id, cur_rr_node,
driver_rr_nodes,
@ -327,6 +336,7 @@ static
void build_switch_block_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
@ -400,7 +410,10 @@ void build_switch_block_module(ModuleManager& module_manager,
rr_graph.node_ylow(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode)));
grids,
device_annotation,
rr_graph,
rr_gsb.get_opin_node(side_manager.get_side(), inode));
BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
ModulePortId input_port_id = module_manager.add_port(sb_module, module_port, ModuleManager::MODULE_INPUT_PORT);
@ -418,7 +431,8 @@ void build_switch_block_module(ModuleManager& module_manager,
/* We care OUTPUT tracks at this time only */
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
build_switch_block_interc_modules(module_manager,
sb_module, device_annotation, rr_graph, rr_gsb,
sb_module, device_annotation,
grids, rr_graph, rr_gsb,
circuit_lib,
side_manager.get_side(),
itrack,
@ -469,6 +483,8 @@ void build_switch_block_module(ModuleManager& module_manager,
static
void build_connection_block_module_short_interc(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -507,7 +523,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
ModulePinInfo input_port_info = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
/* Create port description for input pin of a CLB */
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, src_rr_node);
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, src_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(cb_module, input_port_info.first);
@ -529,6 +545,7 @@ static
void build_connection_block_mux_module(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -595,7 +612,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0]));
VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, cur_rr_node);
ModulePortId cb_output_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, grids, device_annotation, rr_graph, rr_gsb, cur_rr_node);
BasicPort cb_output_port = module_manager.module_port(cb_module, cb_output_port_id);
/* Check port size should match */
@ -642,6 +659,7 @@ static
void build_connection_block_interc_modules(ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -655,13 +673,13 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
return; /* This port has no driver, skip it */
} else if (1 == rr_graph.node_in_edges(src_rr_node).size()) {
/* Print a direct connection */
build_connection_block_module_short_interc(module_manager, cb_module, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets);
build_connection_block_module_short_interc(module_manager, cb_module, device_annotation, grids, rr_graph, rr_gsb, cb_type, src_rr_node, input_port_to_module_nets);
} else if (1 < rr_graph.node_in_edges(src_rr_node).size()) {
/* Print the multiplexer, fan_in >= 2 */
build_connection_block_mux_module(module_manager,
cb_module, device_annotation,
rr_graph, rr_gsb, cb_type,
grids, rr_graph, rr_gsb, cb_type,
circuit_lib,
cb_ipin_side, ipin_index,
input_port_to_module_nets);
@ -726,6 +744,7 @@ static
void build_connection_block_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
@ -799,7 +818,10 @@ void build_connection_block_module(ModuleManager& module_manager,
const RRNodeId& ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
vtr::Point<size_t> port_coord(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node));
std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(ipin_node));
grids,
device_annotation,
rr_graph,
ipin_node);
BasicPort module_port(port_name, 1); /* Every grid output has a port size of 1 */
/* Grid outputs are inputs of switch blocks */
module_manager.add_port(cb_module, module_port, ModuleManager::MODULE_OUTPUT_PORT);
@ -838,6 +860,7 @@ void build_connection_block_module(ModuleManager& module_manager,
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
build_connection_block_interc_modules(module_manager,
cb_module, device_annotation,
grids,
rr_graph,
rr_gsb, cb_type,
circuit_lib,
@ -914,6 +937,7 @@ void build_flatten_connection_block_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -956,6 +980,7 @@ void build_flatten_routing_modules(ModuleManager& module_manager,
build_switch_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -1014,6 +1039,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_switch_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -1028,6 +1054,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,
@ -1042,6 +1069,7 @@ void build_unique_routing_modules(ModuleManager& module_manager,
build_connection_block_module(module_manager,
decoder_lib,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
circuit_lib,
sram_orgz_type, sram_model,

5
openfpga/src/fabric/build_top_module.cpp
View File

@ -284,6 +284,7 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
int build_top_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const TileAnnotation& tile_annotation,
const RRGraph& rr_graph,
@ -329,11 +330,13 @@ int build_top_module(ModuleManager& module_manager,
/* Add module nets to connect the sub modules */
add_top_module_nets_connect_grids_and_gsbs(module_manager, top_module,
vpr_device_annotation,
grids, grid_instance_ids,
rr_graph, device_rr_gsb, sb_instance_ids, cb_instance_ids,
compact_routing_hierarchy, duplicate_grid_pin);
/* Add inter-CLB direct connections */
add_top_module_nets_tile_direct_connections(module_manager, top_module, circuit_lib,
vpr_device_annotation,
grids, grid_instance_ids,
tile_direct, arch_direct);
}
@ -345,7 +348,7 @@ int build_top_module(ModuleManager& module_manager,
add_module_global_ports_from_child_modules(module_manager, top_module);
/* Add global ports from grid ports that are defined as global in tile annotation */
status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, grids, grid_instance_ids);
status = add_top_module_global_ports_from_grid_modules(module_manager, top_module, tile_annotation, vpr_device_annotation, grids, grid_instance_ids);
if (CMD_EXEC_FATAL_ERROR == status) {
return status;
}

2
openfpga/src/fabric/build_top_module.h
View File

@ -8,6 +8,7 @@
#include <string>
#include "vtr_geometry.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
#include "tile_annotation.h"
#include "rr_graph_obj.h"
#include "device_rr_gsb.h"
@ -29,6 +30,7 @@ namespace openfpga {
int build_top_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const TileAnnotation& tile_annotation,
const RRGraph& rr_graph,

89
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -23,6 +23,7 @@
#include "openfpga_device_grid_utils.h"
#include "module_manager_utils.h"
#include "build_routing_module_utils.h"
#include "build_top_module_utils.h"
#include "build_top_module_connection.h"
@ -64,6 +65,7 @@ namespace openfpga {
static
void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
@ -112,11 +114,17 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module));
size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode));
size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index];
std::string src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height,
t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type;
size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height = grid_type_descriptor->pin_height_offset[src_grid_pin_index];
BasicPort src_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, src_grid_pin_index);
VTR_ASSERT(true == src_grid_pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
std::string src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
src_grid_pin_index, false);
src_grid_pin_info);
ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
BasicPort src_grid_port = module_manager.module_port(src_grid_module, src_grid_port_id);
@ -124,10 +132,12 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
/* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
sink_grid_pin_index);
grids,
vpr_device_annotation,
rr_graph,
module_sb.get_opin_node(side_manager.get_side(), inode));
ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id);
@ -184,6 +194,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
static
void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
@ -242,8 +253,15 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
VTR_ASSERT(true == module_manager.valid_module_id(src_grid_module));
size_t src_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
size_t src_grid_pin_index = rr_graph.node_pin_num(rr_gsb.get_opin_node(side_manager.get_side(), inode));
size_t src_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[src_grid_pin_index];
t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type;
size_t src_grid_pin_width = grid_type_descriptor->pin_width_offset[src_grid_pin_index];
size_t src_grid_pin_height = grid_type_descriptor->pin_height_offset[src_grid_pin_index];
BasicPort src_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, src_grid_pin_index);
VTR_ASSERT(true == src_grid_pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, src_grid_pin_index);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
/* Pins for direct connection are NOT duplicated.
* Follow the traditional recipe when adding nets!
@ -251,14 +269,14 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
* For other duplicated pins, we follow the new naming
*/
std::string src_grid_port_name;
if (0. == find_physical_tile_pin_Fc(grids[grid_coordinate.x()][grid_coordinate.y()].type, src_grid_pin_index)) {
src_grid_port_name = generate_grid_port_name(grid_coordinate, src_grid_pin_width, src_grid_pin_height,
if (0. == find_physical_tile_pin_Fc(grid_type_descriptor, src_grid_pin_index)) {
src_grid_port_name = generate_grid_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
src_grid_pin_index, false);
src_grid_pin_info);
} else {
src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height,
src_grid_port_name = generate_grid_duplicated_port_name(src_grid_pin_width, src_grid_pin_height, subtile_index,
rr_graph.node_side(rr_gsb.get_opin_node(side_manager.get_side(), inode)),
src_grid_pin_index, sb_side2postfix_map[side_manager.get_side()]);
src_grid_pin_info, sb_side2postfix_map[side_manager.get_side()]);
}
ModulePortId src_grid_port_id = module_manager.find_module_port(src_grid_module, src_grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_grid_module, src_grid_port_id));
@ -267,10 +285,12 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
/* Collect sink-related information */
vtr::Point<size_t> sink_sb_port_coord(rr_graph.node_xlow(module_sb.get_opin_node(side_manager.get_side(), inode)),
rr_graph.node_ylow(module_sb.get_opin_node(side_manager.get_side(), inode)));
size_t sink_grid_pin_index = rr_graph.node_pin_num(module_sb.get_opin_node(side_manager.get_side(), inode));
std::string sink_sb_port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(module_sb.get_opin_node(side_manager.get_side(), inode)),
sink_grid_pin_index);
grids,
vpr_device_annotation,
rr_graph,
module_sb.get_opin_node(side_manager.get_side(), inode));
ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, sink_sb_port_id));
BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id);
@ -346,6 +366,7 @@ void add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(ModuleManager
static
void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
@ -397,7 +418,10 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
vtr::Point<size_t> cb_src_port_coord(rr_graph.node_xlow(module_ipin_node),
rr_graph.node_ylow(module_ipin_node));
std::string src_cb_port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(module_ipin_node));
grids,
vpr_device_annotation,
rr_graph,
module_ipin_node);
ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, src_cb_port_id));
BasicPort src_cb_port = module_manager.module_port(src_cb_module, src_cb_port_id);
@ -414,11 +438,17 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
VTR_ASSERT(true == module_manager.valid_module_id(sink_grid_module));
size_t sink_grid_instance = grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node);
size_t sink_grid_pin_width = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height = grids[grid_coordinate.x()][grid_coordinate.y()].type->pin_height_offset[sink_grid_pin_index];
std::string sink_grid_port_name = generate_grid_port_name(grid_coordinate, sink_grid_pin_width, sink_grid_pin_height,
t_physical_tile_type_ptr grid_type_descriptor = grids[grid_coordinate.x()][grid_coordinate.y()].type;
size_t sink_grid_pin_width = grid_type_descriptor->pin_width_offset[sink_grid_pin_index];
size_t sink_grid_pin_height = grid_type_descriptor->pin_height_offset[sink_grid_pin_index];
BasicPort sink_grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(grid_type_descriptor, sink_grid_pin_index);
VTR_ASSERT(true == sink_grid_pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(grid_type_descriptor, sink_grid_pin_index);
VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity);
std::string sink_grid_port_name = generate_grid_port_name(sink_grid_pin_width, sink_grid_pin_height, subtile_index,
rr_graph.node_side(rr_gsb.get_ipin_node(cb_ipin_side, inode)),
sink_grid_pin_index, false);
sink_grid_pin_info);
ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_grid_port_id));
BasicPort sink_grid_port = module_manager.module_port(sink_grid_module, sink_grid_port_id);
@ -640,6 +670,7 @@ void add_top_module_nets_connect_sb_and_cb(ModuleManager& module_manager,
*******************************************************************/
void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
@ -661,23 +692,27 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
/* Connect the grid pins of the GSB to adjacent grids */
if (false == duplicate_grid_pin) {
add_top_module_nets_connect_grids_and_sb(module_manager, top_module,
vpr_device_annotation,
grids, grid_instance_ids,
rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids,
compact_routing_hierarchy);
} else {
VTR_ASSERT_SAFE(true == duplicate_grid_pin);
add_top_module_nets_connect_grids_and_sb_with_duplicated_pins(module_manager, top_module,
vpr_device_annotation,
grids, grid_instance_ids,
rr_graph, device_rr_gsb, rr_gsb, sb_instance_ids,
compact_routing_hierarchy);
}
add_top_module_nets_connect_grids_and_cb(module_manager, top_module,
vpr_device_annotation,
grids, grid_instance_ids,
rr_graph, device_rr_gsb, rr_gsb, CHANX, cb_instance_ids.at(CHANX),
compact_routing_hierarchy);
add_top_module_nets_connect_grids_and_cb(module_manager, top_module,
vpr_device_annotation,
grids, grid_instance_ids,
rr_graph, device_rr_gsb, rr_gsb, CHANY, cb_instance_ids.at(CHANY),
compact_routing_hierarchy);
@ -701,6 +736,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
const TileAnnotation& tile_annotation,
const TileGlobalPortId& tile_global_port,
const BasicPort& tile_port_to_connect,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Point<size_t>& grid_coordinate,
const e_side& border_side,
@ -757,12 +793,16 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index];
std::vector<e_side> pin_sides = find_physical_tile_pin_side(physical_tile, grid_pin_index, border_side);
BasicPort grid_pin_info = vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index);
VTR_ASSERT(true == grid_pin_info.is_valid());
int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(physical_tile, grid_pin_index);
VTR_ASSERT(OPEN != subtile_index && subtile_index < physical_tile->capacity);
/* Build nets */
for (const e_side& pin_side : pin_sides) {
std::string grid_port_name = generate_grid_port_name(grid_coordinate,
grid_pin_width, grid_pin_height,
std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index,
pin_side,
grid_pin_index, false);
grid_pin_info);
ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id));
@ -789,6 +829,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager,
const ModuleId& top_module,
const TileAnnotation& tile_annotation,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids) {
int status = CMD_EXEC_SUCCESS;
@ -888,6 +929,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager,
tile_annotation,
tile_global_port,
tile_port,
vpr_device_annotation,
grids,
vtr::Point<size_t>(ix, iy),
NUM_SIDES,
@ -935,6 +977,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager,
tile_annotation,
tile_global_port,
tile_port,
vpr_device_annotation,
grids,
io_coordinate,
io_side,

3
openfpga/src/fabric/build_top_module_connection.h
View File

@ -11,6 +11,7 @@
#include "rr_graph_obj.h"
#include "device_rr_gsb.h"
#include "tile_annotation.h"
#include "vpr_device_annotation.h"
#include "module_manager.h"
/********************************************************************
@ -22,6 +23,7 @@ namespace openfpga {
void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const RRGraph& rr_graph,
@ -34,6 +36,7 @@ void add_top_module_nets_connect_grids_and_gsbs(ModuleManager& module_manager,
int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager,
const ModuleId& top_module,
const TileAnnotation& tile_annotation,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids);

28
openfpga/src/fabric/build_top_module_directs.cpp
View File

@ -41,6 +41,7 @@ static
void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const TileDirect& tile_direct,
@ -92,9 +93,16 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
/* Generate the pin name of source port/pin in the grid */
e_side src_pin_grid_side = tile_direct.from_tile_side(tile_direct_id);
size_t src_tile_pin = tile_direct.from_tile_pin(tile_direct_id);
size_t src_pin_width = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_width_offset[src_tile_pin];
size_t src_pin_height = grids[src_clb_coord.x()][src_clb_coord.y()].type->pin_height_offset[src_tile_pin];
std::string src_port_name = generate_grid_port_name(src_clb_coord, src_pin_width, src_pin_height, src_pin_grid_side, src_tile_pin, false);
t_physical_tile_type_ptr src_grid_type_descriptor = grids[src_clb_coord.x()][src_clb_coord.y()].type;
size_t src_pin_width = src_grid_type_descriptor->pin_width_offset[src_tile_pin];
size_t src_pin_height = src_grid_type_descriptor->pin_height_offset[src_tile_pin];
BasicPort src_pin_info = vpr_device_annotation.physical_tile_pin_port_info(src_grid_type_descriptor, src_tile_pin);
VTR_ASSERT(true == src_pin_info.is_valid());
int src_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(src_grid_type_descriptor, src_tile_pin);
VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < src_grid_type_descriptor->capacity);
std::string src_port_name = generate_grid_port_name(src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info);
ModulePortId src_port_id = module_manager.find_module_port(src_grid_module, src_port_name);
if (true != module_manager.valid_module_port_id(src_grid_module, src_port_id)) {
VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n",
@ -107,10 +115,16 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
/* Generate the pin name of sink port/pin in the grid */
e_side sink_pin_grid_side = tile_direct.to_tile_side(tile_direct_id);
size_t sink_tile_pin = tile_direct.to_tile_pin(tile_direct_id);
size_t sink_pin_width = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_width_offset[src_tile_pin];
size_t sink_pin_height = grids[des_clb_coord.x()][des_clb_coord.y()].type->pin_height_offset[src_tile_pin];
std::string sink_port_name = generate_grid_port_name(des_clb_coord, sink_pin_width, sink_pin_height, sink_pin_grid_side, sink_tile_pin, false);
t_physical_tile_type_ptr sink_grid_type_descriptor = grids[des_clb_coord.x()][des_clb_coord.y()].type;
size_t sink_pin_width = sink_grid_type_descriptor->pin_width_offset[src_tile_pin];
size_t sink_pin_height = sink_grid_type_descriptor->pin_height_offset[src_tile_pin];
BasicPort sink_pin_info = vpr_device_annotation.physical_tile_pin_port_info(sink_grid_type_descriptor, sink_tile_pin);
VTR_ASSERT(true == sink_pin_info.is_valid());
int sink_subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index(sink_grid_type_descriptor, sink_tile_pin);
VTR_ASSERT(OPEN != src_subtile_index && src_subtile_index < sink_grid_type_descriptor->capacity);
std::string sink_port_name = generate_grid_port_name(sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info);
ModulePortId sink_port_id = module_manager.find_module_port(sink_grid_module, sink_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_grid_module, sink_port_id));
VTR_ASSERT(1 == module_manager.module_port(sink_grid_module, sink_port_id).get_width());
@ -141,6 +155,7 @@ void add_module_nets_tile_direct_connection(ModuleManager& module_manager,
void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const TileDirect& tile_direct,
@ -150,6 +165,7 @@ void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager,
for (const TileDirectId& tile_direct_id : tile_direct.directs()) {
add_module_nets_tile_direct_connection(module_manager, top_module, circuit_lib,
vpr_device_annotation,
grids, grid_instance_ids,
tile_direct, tile_direct_id,
arch_direct);

2
openfpga/src/fabric/build_top_module_directs.h
View File

@ -9,6 +9,7 @@
#include "vtr_ndmatrix.h"
#include "arch_direct.h"
#include "tile_direct.h"
#include "vpr_device_annotation.h"
#include "device_grid.h"
#include "module_manager.h"
#include "circuit_library.h"
@ -23,6 +24,7 @@ namespace openfpga {
void add_top_module_nets_tile_direct_connections(ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids,
const TileDirect& tile_direct,

49
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.cpp
View File

@ -16,6 +16,7 @@
#include "openfpga_reserved_words.h"
#include "openfpga_naming.h"
#include "build_routing_module_utils.h"
#include "sdc_writer_utils.h"
#include "analysis_sdc_writer_utils.h"
#include "analysis_sdc_routing_writer.h"
@ -33,6 +34,8 @@ static
void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -140,7 +143,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
}
std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(ipin_node));
grids,
device_annotation,
rr_graph,
ipin_node);
/* Find the port in unique mirror! */
if (true == compact_routing_hierarchy) {
@ -149,7 +155,10 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(cb_type, cb_coord);
const RRNodeId& unique_mirror_ipin_node = unique_mirror.get_ipin_node(cb_ipin_side, inode);
port_name = generate_cb_module_grid_port_name(cb_ipin_side,
rr_graph.node_pin_num(unique_mirror_ipin_node));
grids,
device_annotation,
rr_graph,
unique_mirror_ipin_node);
}
/* Ensure we have this port in the module! */
@ -211,6 +220,8 @@ static
void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -233,6 +244,8 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
print_analysis_sdc_disable_cb_unused_resources(fp,
atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,
@ -250,6 +263,8 @@ void print_analysis_sdc_disable_unused_cb_ports(std::fstream& fp,
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -257,6 +272,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,
@ -264,6 +281,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
print_analysis_sdc_disable_unused_cb_ports(fp, atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,
@ -280,6 +299,8 @@ static
void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -370,7 +391,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(opin_node),
rr_graph.node_pin_num(opin_node));
grids,
device_annotation,
rr_graph,
opin_node);
if (true == compact_routing_hierarchy) {
/* Note: use GSB coordinate when inquire for unique modules!!! */
@ -380,7 +404,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(unique_mirror_opin_node),
rr_graph.node_pin_num(unique_mirror_opin_node));
grids,
device_annotation,
rr_graph,
unique_mirror_opin_node);
}
@ -432,7 +459,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
std::string port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(opin_node),
rr_graph.node_pin_num(opin_node));
grids,
device_annotation,
rr_graph,
opin_node);
if (true == compact_routing_hierarchy) {
/* Note: use GSB coordinate when inquire for unique modules!!! */
@ -442,7 +472,10 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
port_name = generate_sb_module_grid_port_name(side_manager.get_side(),
rr_graph.node_side(unique_mirror_opin_node),
rr_graph.node_pin_num(unique_mirror_opin_node));
grids,
device_annotation,
rr_graph,
unique_mirror_opin_node);
}
@ -512,6 +545,8 @@ void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -534,6 +569,8 @@ void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
print_analysis_sdc_disable_sb_unused_resources(fp,
atom_ctx,
module_manager,
device_annotation,
grids,
rr_graph,
routing_annotation,
device_rr_gsb,

5
openfpga/src/fpga_sdc/analysis_sdc_routing_writer.h
View File

@ -8,6 +8,7 @@
#include <vector>
#include "vpr_context.h"
#include "module_manager.h"
#include "device_grid.h"
#include "device_rr_gsb.h"
#include "vpr_routing_annotation.h"
@ -21,6 +22,8 @@ namespace openfpga {
void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -29,6 +32,8 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
const AtomContext& atom_ctx,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const VprRoutingAnnotation& routing_annotation,
const DeviceRRGSB& device_rr_gsb,

4
openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
View File

@ -267,6 +267,8 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
print_analysis_sdc_disable_unused_cbs(fp,
vpr_ctx.atom(),
openfpga_ctx.module_graph(),
openfpga_ctx.vpr_device_annotation(),
vpr_ctx.device().grid,
vpr_ctx.device().rr_graph,
openfpga_ctx.vpr_routing_annotation(),
openfpga_ctx.device_rr_gsb(),
@ -276,6 +278,8 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
print_analysis_sdc_disable_unused_sbs(fp,
vpr_ctx.atom(),
openfpga_ctx.module_graph(),
openfpga_ctx.vpr_device_annotation(),
vpr_ctx.device().grid,
vpr_ctx.device().rr_graph,
openfpga_ctx.vpr_routing_annotation(),
openfpga_ctx.device_rr_gsb(),

60
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -55,6 +55,8 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
const std::string& module_path,
const ModuleManager& module_manager,
const ModuleId& sb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& output_node_side,
@ -68,19 +70,21 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
/* Find the module port corresponding to the output rr_node */
ModulePinInfo module_output_port = find_switch_block_module_chan_port(module_manager,
sb_module,
rr_graph,
rr_gsb,
output_node_side,
output_rr_node,
OUT_PORT);
sb_module,
rr_graph,
rr_gsb,
output_node_side,
output_rr_node,
OUT_PORT);
/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
std::vector<ModulePinInfo> module_input_ports = find_switch_block_module_input_ports(module_manager,
sb_module,
rr_graph,
rr_gsb,
get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
sb_module,
grids,
device_annotation,
rr_graph,
rr_gsb,
get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
/* Find timing constraints for each path (edge) */
std::map<ModulePinInfo, float> switch_delays;
@ -143,6 +147,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
const bool& hierarchical,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -186,6 +192,8 @@ void print_pnr_sdc_constrain_sb_timing(const std::string& sdc_dir,
hierarchical,
module_path,
module_manager, sb_module,
device_annotation,
grids,
rr_graph,
rr_gsb,
side_manager.get_side(),
@ -207,6 +215,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -239,6 +249,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
constrain_zero_delay_paths);
@ -255,6 +267,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -286,6 +300,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
constrain_zero_delay_paths);
@ -303,6 +319,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
const std::string& module_path,
const ModuleManager& module_manager,
const ModuleId& cb_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -338,6 +356,8 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
/* Find the module port corresponding to the output rr_node */
ModulePortId module_output_port = find_connection_block_module_ipin_port(module_manager,
cb_module,
grids,
device_annotation,
rr_graph,
rr_gsb,
output_rr_node);
@ -405,6 +425,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
const bool& hierarchical,
const std::string& module_path,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -499,6 +521,8 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
time_unit,
hierarchical, module_path,
module_manager, cb_module,
device_annotation,
grids,
rr_graph, rr_gsb, cb_type,
ipin_rr_node,
constrain_zero_delay_paths);
@ -519,6 +543,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const t_rr_type& cb_type,
@ -554,6 +580,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
rr_gsb,
cb_type,
@ -572,6 +600,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -582,6 +612,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
hierarchical,
module_manager, top_module,
device_annotation,
grids,
rr_graph,
device_rr_gsb,
CHANX,
@ -590,6 +622,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
print_pnr_sdc_flatten_routing_constrain_cb_timing(sdc_dir, time_unit,
hierarchical,
module_manager, top_module,
device_annotation,
grids,
rr_graph,
device_rr_gsb,
CHANY,
@ -605,6 +639,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths) {
@ -633,6 +669,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
unique_mirror,
CHANX,
@ -658,6 +696,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
hierarchical,
module_path,
module_manager,
device_annotation,
grids,
rr_graph,
unique_mirror,
CHANY,

10
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.h
View File

@ -9,6 +9,8 @@
#include "module_manager.h"
#include "device_rr_gsb.h"
#include "rr_graph_obj.h"
#include "device_grid.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration
@ -22,6 +24,8 @@ void print_pnr_sdc_flatten_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
@ -31,6 +35,8 @@ void print_pnr_sdc_compact_routing_constrain_sb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
@ -40,6 +46,8 @@ void print_pnr_sdc_flatten_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);
@ -49,6 +57,8 @@ void print_pnr_sdc_compact_routing_constrain_cb_timing(const std::string& sdc_di
const bool& hierarchical,
const ModuleManager& module_manager,
const ModuleId& top_module,
const VprDeviceAnnotation& device_annotation,
const DeviceGrid& grids,
const RRGraph& rr_graph,
const DeviceRRGSB& device_rr_gsb,
const bool& constrain_zero_delay_paths);

8
openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
View File

@ -382,6 +382,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
@ -392,6 +394,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
@ -416,6 +420,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());
@ -426,6 +432,8 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
sdc_options.hierarchical(),
module_manager,
top_module,
device_annotation,
device_ctx.grid,
device_ctx.rr_graph,
device_rr_gsb,
sdc_options.constrain_zero_delay_paths());

2
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -488,7 +488,7 @@ std::string generate_verilog_port(const enum e_dump_verilog_port_type& verilog_p
&& (0 == port_info.get_lsb())
&& (1 == port_info.get_origin_port_width())) {
size_str.clear();
} else if ((1 == port_info.get_width()) && (0 != port_info.get_lsb())) {
} else if ((1 == port_info.get_width())) {
size_str = "[" + std::to_string(port_info.get_lsb()) + "]";
}
verilog_line = port_info.get_name() + size_str;