Merge branch 'master' into doc_patch
This commit is contained in:
tangxifan
GitHub
commit
ed9b567d19
|
|
@ -211,6 +211,7 @@ jobs:
|
|||
- name: fpga_sdc_reg_test
|
||||
- name: fpga_spice_reg_test
|
||||
- name: quicklogic_reg_test
|
||||
- name: vtr_benchmark_reg_test
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
|
|
@ -256,6 +257,7 @@ jobs:
|
|||
- name: fpga_sdc_reg_test
|
||||
- name: fpga_spice_reg_test
|
||||
- name: quicklogic_reg_test
|
||||
- name: vtr_benchmark_reg_test
|
||||
steps:
|
||||
- name: Checkout OpenFPGA repo
|
||||
uses: actions/checkout@v2
|
||||
|
|
|
|||
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -0,0 +1,317 @@
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|||
|
||||
|
||||
`define MEMORY_CONTROLLER_TAGS 1
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||||
`define MEMORY_CONTROLLER_TAG_SIZE 1
|
||||
`define TAG__str 1'b0
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`define MEMORY_CONTROLLER_ADDR_SIZE 32
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`define MEMORY_CONTROLLER_DATA_SIZE 32
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||||
|
||||
|
||||
module memory_controller
|
||||
(
|
||||
clk,
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||||
memory_controller_address,
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||||
memory_controller_write_enable,
|
||||
memory_controller_in,
|
||||
memory_controller_out
|
||||
);
|
||||
input clk;
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||||
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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||||
input memory_controller_write_enable;
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||||
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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||||
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
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||||
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||||
|
||||
reg [4:0] str_address;
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reg str_write_enable;
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||||
reg [7:0] str_in;
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||||
wire [7:0] str_out;
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||||
|
||||
single_port_ram _str (
|
||||
.clk( clk ),
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||||
.addr( str_address ),
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||||
.we( str_write_enable ),
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||||
.data( str_in ),
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||||
.out( str_out )
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||||
);
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||||
|
||||
|
||||
wire tag;
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||||
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||||
//must use all wires inside module.....
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||||
assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
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reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
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always @(posedge clk)
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prevTag <= tag;
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always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
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begin
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||||
|
||||
case(tag)
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||||
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||||
1'b0:
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||||
begin
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||||
str_address = memory_controller_address[5-1+0:0];
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||||
str_write_enable = memory_controller_write_enable;
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str_in[8-1:0] = memory_controller_in[8-1:0];
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||||
end
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||||
endcase
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||||
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||||
case(prevTag)
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||||
|
||||
1'b0:
|
||||
memory_controller_out = str_out;
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||||
endcase
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||||
end
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||||
|
||||
endmodule
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||||
|
||||
|
||||
module memset
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||||
(
|
||||
clk,
|
||||
reset,
|
||||
start,
|
||||
finish,
|
||||
return_val,
|
||||
m,
|
||||
c,
|
||||
n,
|
||||
memory_controller_write_enable,
|
||||
memory_controller_address,
|
||||
memory_controller_in,
|
||||
memory_controller_out
|
||||
);
|
||||
|
||||
output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
|
||||
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
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||||
input clk;
|
||||
input reset;
|
||||
input start;
|
||||
|
||||
output finish;
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||||
reg finish;
|
||||
|
||||
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
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||||
input [31:0] c;
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input [31:0] n;
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|
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output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
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|
||||
output memory_controller_write_enable;
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||||
reg memory_controller_write_enable;
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||||
|
||||
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
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||||
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
|
||||
|
||||
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
|
||||
|
||||
reg [3:0] cur_state;
|
||||
|
||||
/*
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||||
parameter Wait = 4'd0;
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||||
parameter entry = 4'd1;
|
||||
parameter entry_1 = 4'd2;
|
||||
parameter entry_2 = 4'd3;
|
||||
parameter bb = 4'd4;
|
||||
parameter bb_1 = 4'd5;
|
||||
parameter bb1 = 4'd6;
|
||||
parameter bb1_1 = 4'd7;
|
||||
parameter bb_nph = 4'd8;
|
||||
parameter bb2 = 4'd9;
|
||||
parameter bb2_1 = 4'd10;
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||||
parameter bb2_2 = 4'd11;
|
||||
parameter bb2_3 = 4'd12;
|
||||
parameter bb2_4 = 4'd13;
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parameter bb4 = 4'd14;
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||||
*/
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|
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memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out);
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||||
|
||||
|
||||
reg [31:0] indvar;
|
||||
reg var1;
|
||||
reg [31:0] tmp;
|
||||
reg [31:0] tmp8;
|
||||
reg var2;
|
||||
reg [31:0] var0;
|
||||
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
|
||||
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
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reg [31:0] indvar_next;
|
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reg exitcond;
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always @(posedge clk)
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if (reset)
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||||
cur_state <= 4'b0000;
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||||
else
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case(cur_state)
|
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4'b0000:
|
||||
begin
|
||||
finish <= 1'b0;
|
||||
if (start == 1'b1)
|
||||
cur_state <= 4'b0001;
|
||||
else
|
||||
cur_state <= 4'b0000;
|
||||
end
|
||||
4'b0001:
|
||||
begin
|
||||
|
||||
|
||||
|
||||
var0 <= n & 32'b00000000000000000000000000000011;
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||||
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||||
cur_state <= 4'b0010;
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||||
end
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||||
4'b0010:
|
||||
begin
|
||||
|
||||
var1 <= 1'b0;
|
||||
var0 <= 32'b00000000000000000000000000000000;
|
||||
|
||||
cur_state <= 4'b0011;
|
||||
end
|
||||
4'b0011:
|
||||
begin
|
||||
|
||||
|
||||
if (|var1) begin
|
||||
cur_state <= 4'b0110;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
cur_state <= 4'b0100;
|
||||
end
|
||||
end
|
||||
4'b0100:
|
||||
begin
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||||
|
||||
cur_state <= 4'b0101;
|
||||
end
|
||||
4'b0101:
|
||||
begin
|
||||
cur_state <= 4'b0110;
|
||||
end
|
||||
4'b0110:
|
||||
begin
|
||||
|
||||
var2 <= | (n [31:4]);
|
||||
|
||||
cur_state <= 4'b0111;
|
||||
end
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||||
4'b0111:
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||||
begin
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||||
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||||
if (|var2)
|
||||
begin
|
||||
cur_state <= 4'b1110;
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||||
end
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||||
else
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||||
begin
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||||
cur_state <= 4'b1000;
|
||||
end
|
||||
end
|
||||
4'b1000:
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||||
begin
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||||
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||||
tmp <= n ;
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||||
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||||
indvar <= 32'b00000000000000000000000000000000;
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||||
cur_state <= 4'b1001;
|
||||
end
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||||
4'b1001:
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||||
begin
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||||
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||||
cur_state <= 4'b1010;
|
||||
end
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||||
4'b1010:
|
||||
begin
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||||
tmp8 <= indvar;
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||||
indvar_next <= indvar;
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||||
cur_state <= 4'b1011;
|
||||
end
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||||
4'b1011:
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||||
begin
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||||
|
||||
scevgep <= (m & tmp8);
|
||||
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||||
exitcond <= (indvar_next == tmp);
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||||
|
||||
cur_state <= 4'b1100;
|
||||
end
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||||
4'b1100:
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||||
begin
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||||
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||||
s_07 <= scevgep;
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||||
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||||
cur_state <= 4'b1101;
|
||||
end
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||||
4'b1101:
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||||
|
||||
begin
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||||
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||||
|
||||
if (exitcond)
|
||||
begin
|
||||
cur_state <= 4'b1110;
|
||||
end
|
||||
else
|
||||
begin
|
||||
indvar <= indvar_next;
|
||||
cur_state <= 4'b1001;
|
||||
end
|
||||
end
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||||
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||||
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||||
4'b1110:
|
||||
begin
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||||
|
||||
return_val <= m;
|
||||
finish <= 1'b1;
|
||||
cur_state <= 4'b0000;
|
||||
end
|
||||
endcase
|
||||
|
||||
always @(cur_state)
|
||||
begin
|
||||
|
||||
case(cur_state)
|
||||
4'b1101:
|
||||
begin
|
||||
memory_controller_address = s_07;
|
||||
memory_controller_write_enable = 1'b1;
|
||||
memory_controller_in = c;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//---------------------------------------
|
||||
// A single-port 32x8bit RAM
|
||||
// This module is tuned for VTR's benchmarks
|
||||
//---------------------------------------
|
||||
module single_port_ram (
|
||||
input clk,
|
||||
input we,
|
||||
input [4:0] addr,
|
||||
input [7:0] data,
|
||||
output [7:0] out );
|
||||
|
||||
reg [7:0] ram[31:0];
|
||||
reg [7:0] internal;
|
||||
|
||||
assign out = internal;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(wen) begin
|
||||
ram[addr] <= data;
|
||||
end
|
||||
|
||||
if(ren) begin
|
||||
internal <= ram[addr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, clk, reset);
|
||||
input[31:0] Xinport;
|
||||
input[31:0] Yinport;
|
||||
input[31:0] Uinport;
|
||||
input[31:0] Aport;
|
||||
input[31:0] DXport;
|
||||
input clk;
|
||||
input reset;
|
||||
output[31:0] Xoutport;
|
||||
output[31:0] Youtport;
|
||||
output[31:0] Uoutport;
|
||||
reg[31:0] Xoutport;
|
||||
reg[31:0] Youtport;
|
||||
reg[31:0] Uoutport;
|
||||
|
||||
reg[31:0] x_var;
|
||||
reg[31:0] y_var;
|
||||
reg[31:0] u_var;
|
||||
wire[31:0] temp;
|
||||
reg looping;
|
||||
|
||||
assign temp = u_var * DXport;
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (reset == 1'b1)
|
||||
begin
|
||||
looping <= 1'b0;
|
||||
x_var <= 0;
|
||||
y_var <= 0;
|
||||
u_var <= 0;
|
||||
end
|
||||
else
|
||||
if (looping == 1'b0)
|
||||
begin
|
||||
x_var <= Xinport;
|
||||
y_var <= Yinport;
|
||||
u_var <= Uinport;
|
||||
looping <= 1'b1;
|
||||
end
|
||||
else if (x_var < Aport)
|
||||
begin
|
||||
u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
|
||||
y_var <= y_var + temp;//(u_var * DXport);
|
||||
x_var <= x_var + DXport;
|
||||
looping <= looping;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Xoutport <= x_var ;
|
||||
Youtport <= y_var ;
|
||||
Uoutport <= u_var ;
|
||||
looping <= 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
|
||||
/*--------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------
|
||||
-- File Name : diffeq.v
|
||||
-- Author(s) : P. Sridhar
|
||||
-- Affiliation : Laboratory for Digital Design Environments
|
||||
-- Department of Electrical & Computer Engineering
|
||||
-- University of Cincinnati
|
||||
-- Date Created : June 1991.
|
||||
-- Introduction : Behavioral description of a differential equation
|
||||
-- solver written in a synthesizable subset of VHDL.
|
||||
-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ.
|
||||
-- Obtained from the Highlevel Synthesis Workshop
|
||||
-- Repository.
|
||||
--
|
||||
-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
|
||||
-- Date Modified : Sept, 91.
|
||||
--
|
||||
-- Disclaimer : This comes with absolutely no guarantees of any
|
||||
-- kind (just stating the obvious ...)
|
||||
--
|
||||
-- Acknowledgement : The Distributed Synthesis Systems research at
|
||||
-- the Laboratory for Digital Design Environments,
|
||||
-- University of Cincinnati, is sponsored in part
|
||||
-- by the Defense Advanced Research Projects Agency
|
||||
-- under order number 7056 monitored by the Federal
|
||||
-- Bureau of Investigation under contract number
|
||||
-- J-FBI-89-094.
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------*/
|
||||
module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
|
||||
|
||||
input clk;
|
||||
input reset;
|
||||
input [31:0]aport;
|
||||
input [31:0]dxport;
|
||||
output [31:0]xport;
|
||||
output [31:0]yport;
|
||||
output [31:0]uport;
|
||||
reg [31:0]xport;
|
||||
reg [31:0]yport;
|
||||
reg [31:0]uport;
|
||||
wire [31:0]temp;
|
||||
|
||||
assign temp = uport * dxport;
|
||||
always @(posedge clk )
|
||||
begin
|
||||
if (reset == 1'b1)
|
||||
begin
|
||||
xport <= 0;
|
||||
yport <= 0;
|
||||
uport <= 0;
|
||||
end
|
||||
else
|
||||
if (xport < aport)
|
||||
begin
|
||||
xport <= xport + dxport;
|
||||
yport <= yport + temp;//(uport * dxport);
|
||||
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,41 +0,0 @@
|
|||
# Yosys synthesis script for alu4
|
||||
# read Verilog
|
||||
read_verilog /full_path/design.v #can be repeated if project has many files
|
||||
read_verilog -lib /full_path/cells_sim.v # file we provide
|
||||
|
||||
hierarchy -check -top top_module
|
||||
proc
|
||||
|
||||
flatten
|
||||
tribuf -logic
|
||||
|
||||
synth -run coarse
|
||||
opt -fast
|
||||
|
||||
memory -nomap
|
||||
opt_clean
|
||||
|
||||
|
||||
memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt
|
||||
techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v
|
||||
opt -fast -mux_undef -undriven -fine
|
||||
memory_map
|
||||
|
||||
# Technology mapping
|
||||
#proc
|
||||
techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v
|
||||
|
||||
# Synthesis
|
||||
synth -top top_module -flatten -run fine
|
||||
clean
|
||||
|
||||
# LUT mapping
|
||||
abc -lut 6
|
||||
|
||||
# Check
|
||||
synth -run check
|
||||
|
||||
# Clean and output blif
|
||||
opt_clean -purge
|
||||
write_blif design.blif
|
||||
write_verilog design.v
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
# Yosys synthesis script for ${TOP_MODULE}
|
||||
|
||||
#########################
|
||||
# Parse input files
|
||||
#########################
|
||||
# Read verilog files
|
||||
${READ_VERILOG_FILE}
|
||||
# Read technology library
|
||||
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
|
||||
|
||||
#########################
|
||||
# Prepare for synthesis
|
||||
#########################
|
||||
# Identify top module from hierarchy
|
||||
hierarchy -check -top ${TOP_MODULE}
|
||||
# - Convert process blocks to AST
|
||||
proc
|
||||
# Flatten all the gates/primitives
|
||||
flatten
|
||||
# Identify tri-state buffers from 'z' signal in AST
|
||||
# with follow-up optimizations to clean up AST
|
||||
tribuf -logic
|
||||
opt_expr
|
||||
opt_clean
|
||||
# demote inout ports to input or output port
|
||||
# with follow-up optimizations to clean up AST
|
||||
deminout
|
||||
opt
|
||||
|
||||
#########################
|
||||
# Run coarse synthesis
|
||||
#########################
|
||||
opt_expr
|
||||
opt_clean
|
||||
check
|
||||
opt
|
||||
wreduce -keepdc
|
||||
peepopt
|
||||
pmuxtree
|
||||
opt_clean
|
||||
# Extract arithmetic functions
|
||||
alumacc
|
||||
opt
|
||||
fsm
|
||||
# Run a quick follow-up optimization to sweep out unused nets/signals
|
||||
opt -fast
|
||||
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
|
||||
memory -nomap
|
||||
opt_clean
|
||||
|
||||
#########################
|
||||
# Map logics to BRAMs
|
||||
#########################
|
||||
memory_bram -rules ${YOSYS_BRAM_MAP_RULES}
|
||||
techmap -map ${YOSYS_BRAM_MAP_VERILOG}
|
||||
opt -fast -mux_undef -undriven -fine
|
||||
memory_map
|
||||
opt -undriven -fine
|
||||
|
||||
#########################
|
||||
# Map flip-flops
|
||||
#########################
|
||||
techmap -map +/adff2dff.v
|
||||
opt_expr -mux_undef
|
||||
simplemap
|
||||
opt_expr
|
||||
opt_merge
|
||||
opt_rmdff
|
||||
opt_clean
|
||||
opt
|
||||
|
||||
#########################
|
||||
# Map LUTs
|
||||
#########################
|
||||
abc -lut ${LUT_SIZE}
|
||||
|
||||
#########################
|
||||
# Check and show statisitics
|
||||
#########################
|
||||
hierarchy -check
|
||||
stat
|
||||
|
||||
#########################
|
||||
# Output netlists
|
||||
#########################
|
||||
opt_clean -purge
|
||||
write_blif ${OUTPUT_BLIF}
|
||||
|
|
@ -0,0 +1,273 @@
|
|||
<!-- Architecture annotation for OpenFPGA framework
|
||||
This annotation supports the k6_N10_40nm.xml
|
||||
- General purpose logic block
|
||||
- K = 6, N = 10, I = 40
|
||||
- Single mode
|
||||
- Routing architecture
|
||||
- L = 4, fc_in = 0.15, fc_out = 0.1
|
||||
-->
|
||||
<openfpga_architecture>
|
||||
<technology_library>
|
||||
<device_library>
|
||||
<device_model name="logic" type="transistor">
|
||||
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="0.9" pn_ratio="2"/>
|
||||
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
|
||||
</device_model>
|
||||
<device_model name="io" type="transistor">
|
||||
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
||||
<design vdd="2.5" pn_ratio="3"/>
|
||||
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
||||
</device_model>
|
||||
</device_library>
|
||||
<variation_library>
|
||||
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
||||
</variation_library>
|
||||
</technology_library>
|
||||
<circuit_library>
|
||||
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="input" prefix="sel" size="1"/>
|
||||
<port type="input" prefix="selb" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
|
||||
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="64"/>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="1"/>
|
||||
<port type="input" prefix="cin" lib_name="CI" size="1"/>
|
||||
<port type="output" prefix="sumout" lib_name="SUM" size="1"/>
|
||||
<port type="output" prefix="cout" lib_name="CO" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="dpram_1024x8" prefix="dpram_1024x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="waddr" size="10"/>
|
||||
<port type="input" prefix="raddr" size="10"/>
|
||||
<port type="input" prefix="data_in" size="8"/>
|
||||
<port type="input" prefix="wen" size="1"/>
|
||||
<port type="input" prefix="ren" size="1"/>
|
||||
<port type="output" prefix="data_out" size="8"/>
|
||||
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
|
||||
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<!-- Binding operating pb_types in mode 'n2_lut5' -->
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:4]"/>
|
||||
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'ble6' -->
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
|
||||
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:5]"/>
|
||||
<port name="out" physical_mode_port="lut6_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<!-- End physical pb_type binding in complex block clb -->
|
||||
|
||||
|
||||
<!-- physical pb_type binding in complex block memory -->
|
||||
<pb_type name="memory[mem_1024x8_dp].mem_1024x8_dp" circuit_model_name="dpram_1024x8"/>
|
||||
<!-- END physical pb_type binding in complex block memory -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
//-----------------------------------------------------
|
||||
// Design Name : dpram_1024x8
|
||||
// File Name : dpram8.v
|
||||
// Function : Wrapper module of dual port RAM 1024 addresses x 8 bit
|
||||
// Coder : Xifan tang
|
||||
//-----------------------------------------------------
|
||||
module dpram_1024x8 (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input[0:9] waddr,
|
||||
input[0:9] raddr,
|
||||
input[0:7] data_in,
|
||||
output[0:7] data_out );
|
||||
|
||||
dpram_1024x8_core memory_0 (
|
||||
.wclk (clk),
|
||||
.wen (wen),
|
||||
.waddr (waddr),
|
||||
.data_in (data_in),
|
||||
.rclk (clk),
|
||||
.ren (ren),
|
||||
.raddr (raddr),
|
||||
.data_out (data_out) );
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------------------------------
|
||||
// Design Name : dpram_1024x8_core
|
||||
// File Name : dpram8.v
|
||||
// Function : Core module of dual port RAM 1024 addresses x 8 bit
|
||||
// Coder : Xifan tang
|
||||
//-----------------------------------------------------
|
||||
module dpram_1024x8_core (
|
||||
input wclk,
|
||||
input wen,
|
||||
input [0:9] waddr,
|
||||
input [0:7] data_in,
|
||||
input rclk,
|
||||
input ren,
|
||||
input [0:9] raddr,
|
||||
output [0:7] data_out );
|
||||
|
||||
reg[0:7] ram[0:1023];
|
||||
reg[0:7] internal;
|
||||
|
||||
assign data_out = internal;
|
||||
|
||||
always @(posedge wclk) begin
|
||||
if(wen) begin
|
||||
ram[waddr] <= data_in;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rclk) begin
|
||||
if(ren) begin
|
||||
internal <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
# Run VPR for the 'and' design
|
||||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
# Note: no need to assign activity file when you used a fixed number
|
||||
# of clock cycles in simulation settings
|
||||
# Also, ACE2 does not support multiple clocks
|
||||
# Therefore, activity file is not recommended for multi-clock fabric/implementations
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing #--verbose
|
||||
|
||||
# Write the fabric hierarchy of module graph to a file
|
||||
# This is used by hierarchical PnR flows
|
||||
write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
|
||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
|
||||
# Write the Verilog netlist for FPGA fabric
|
||||
# - Enable the use of explicit port mapping in Verilog netlist
|
||||
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
# - Must specify the reference benchmark file if you want to output any testbenches
|
||||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write SDC to disable timing for configure ports
|
||||
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
bram $__MY_DPRAM_1024x8
|
||||
init 0
|
||||
abits 10
|
||||
dbits 8
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 1 0
|
||||
enable 1 1
|
||||
transp 0 0
|
||||
clocks 1 1
|
||||
clkpol 1 1
|
||||
endbram
|
||||
|
||||
match $__MY_DPRAM_1024x8
|
||||
min efficiency 0
|
||||
make_transp
|
||||
endmatch
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module $__MY_DPRAM_1024x8 (
|
||||
output [7:0] B1DATA,
|
||||
input CLK1,
|
||||
input [9:0] B1ADDR,
|
||||
input [9:0] A1ADDR,
|
||||
input [7:0] A1DATA,
|
||||
input A1EN,
|
||||
input B1EN );
|
||||
|
||||
generate
|
||||
dpram_1024x8 #() _TECHMAP_REPLACE_ (
|
||||
.clk (CLK1),
|
||||
.wen (A1EN),
|
||||
.waddr (A1ADDR),
|
||||
.data_in (A1DATA),
|
||||
.ren (B1EN),
|
||||
.raddr (B1ADDR),
|
||||
.data_out (B1DATA) );
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
//-----------------------------
|
||||
// Dual-port RAM 1024x8 bit (8Kbit)
|
||||
// Core logic
|
||||
//-----------------------------
|
||||
module dpram_1024x8_core (
|
||||
input wclk,
|
||||
input wen,
|
||||
input [9:0] waddr,
|
||||
input [7:0] data_in,
|
||||
input rclk,
|
||||
input ren,
|
||||
input [9:0] raddr,
|
||||
output [7:0] data_out );
|
||||
|
||||
reg [7:0] ram[1023:0];
|
||||
reg [7:0] internal;
|
||||
|
||||
assign data_out = internal;
|
||||
|
||||
always @(posedge wclk) begin
|
||||
if(wen) begin
|
||||
ram[waddr] <= data_in;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rclk) begin
|
||||
if(ren) begin
|
||||
internal <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// Dual-port RAM 1024x8 bit (8Kbit) wrapper
|
||||
// where the read clock and write clock
|
||||
// are combined to a unified clock
|
||||
//-----------------------------
|
||||
module dpram_1024x8 (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input [9:0] waddr,
|
||||
input [9:0] raddr,
|
||||
input [7:0] data_in,
|
||||
output [7:0] data_out );
|
||||
|
||||
dpram_1024x8_core memory_0 (
|
||||
.wclk (clk),
|
||||
.wen (wen),
|
||||
.waddr (waddr),
|
||||
.data_in (data_in),
|
||||
.rclk (clk),
|
||||
.ren (ren),
|
||||
.raddr (raddr),
|
||||
.data_out (data_out) );
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
//---------------------------------------
|
||||
// 1-bit adder
|
||||
//---------------------------------------
|
||||
module adder(
|
||||
input cin,
|
||||
input a,
|
||||
input b,
|
||||
output cout,
|
||||
output sumout );
|
||||
|
||||
|
||||
assign sumout = a ^ b ^ cin;
|
||||
assign cout = (a & b) | ((a | b) & cin);
|
||||
|
||||
endmodule
|
||||
|
|
@ -48,15 +48,4 @@ module dual_port_sram (
|
|||
|
||||
endmodule
|
||||
|
||||
module adder(
|
||||
input cin,
|
||||
input a,
|
||||
input b,
|
||||
output cout,
|
||||
output sumout );
|
||||
|
||||
|
||||
assign sumout = a ^ b ^ cin;
|
||||
assign cout = (a & b) | ((a | b) & cin);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "VTR benchmark regression tests";
|
||||
run-task benchmark_sweep/vtr_benchmarks --debug --show_thread_logs
|
||||
|
|
@ -483,15 +483,14 @@ def run_yosys_with_abc():
|
|||
clean_up_and_exit("")
|
||||
args.K = lut_size
|
||||
# Yosys script parameter mapping
|
||||
ys_params = {
|
||||
"READ_VERILOG_FILE": " \n".join([
|
||||
ys_params = script_env_vars["PATH"]
|
||||
ys_params["READ_VERILOG_FILE"] = " \n".join([
|
||||
"read_verilog -nolatches " + shlex.quote(eachfile)
|
||||
for eachfile in args.benchmark_files]),
|
||||
"TOP_MODULE": args.top_module,
|
||||
"LUT_SIZE": lut_size,
|
||||
"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
|
||||
"OUTPUT_VERILOG": args.top_module+"_output_verilog.v"
|
||||
}
|
||||
for eachfile in args.benchmark_files])
|
||||
ys_params["TOP_MODULE"] = args.top_module
|
||||
ys_params["LUT_SIZE"] = lut_size
|
||||
ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif"
|
||||
ys_params["OUTPUT_VERILOG"] = args.top_module+"_output_verilog.v"
|
||||
|
||||
for indx in range(0, len(OpenFPGAArgs), 2):
|
||||
tmpVar = OpenFPGAArgs[indx][2:].upper()
|
||||
|
|
|
|||
|
|
@ -12,26 +12,28 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
|||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
timeout_each_job = 3*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=3x2
|
||||
# Yosys script parameters
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
|
||||
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
|
||||
bench0_top = and2
|
||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
bench0_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = false
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_40nm_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
# Yosys script parameters
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v
|
||||
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys
|
||||
# Benchmark ch_intrinsics
|
||||
bench0_top = memset
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
#end_flow_with_test=
|
||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
|
|
@ -0,0 +1,748 @@
|
|||
<!--
|
||||
Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
|
||||
|
||||
- 40 nm technology
|
||||
- General purpose logic block:
|
||||
K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs)
|
||||
with optionally registered outputs
|
||||
Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
|
||||
Carry chain links to vertically adjacent logic blocks
|
||||
- Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.
|
||||
Height = 6, found on every (8n+2)th column
|
||||
- Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.
|
||||
Height = 4, found on every (8n+6)th column
|
||||
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
||||
|
||||
Details on Modelling:
|
||||
|
||||
The electrical design of the architecture described here is NOT from an
|
||||
optimized, SPICED architecture. Instead, we attempt to create a reasonable
|
||||
architecture file by using an existing commercial FPGA to approximate the area,
|
||||
delay, and power of the underlying components. This is combined with a reasonable 40 nm
|
||||
model of wiring and circuit design for low-level routing components, where available.
|
||||
The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also
|
||||
has wiring electrical parameters that allow the wire lengths and switch patterns to be
|
||||
modified and you will still get reasonable delay results for the new architecture.
|
||||
The following describes, in detail, how we obtained the various electrical values for this
|
||||
architecture.
|
||||
|
||||
Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar
|
||||
architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture.
|
||||
(n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)
|
||||
This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to
|
||||
match the overall target (a 40 nm FPGA).
|
||||
|
||||
We obtain delay numbers by measuring delays of routing, soft logic blocks,
|
||||
memories, and multipliers from test circuits on a Stratix IV GX device
|
||||
(EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4
|
||||
wires. Rmetal and Cmetal values for the routing wires were obtained from work done by Charles
|
||||
Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and
|
||||
take the R and C data from the ITRS roadmap.
|
||||
|
||||
For the general purpose logic block, we assume that the area and delays of the Stratix IV
|
||||
crossbar is close enough to the crossbar modelled here.
|
||||
Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to
|
||||
36:1 multiplexers. We match these parameters in this architecture.
|
||||
|
||||
For LUTs, we include LUT
|
||||
delays measured from Stratix IV which is dependant on the input used (ie. some
|
||||
LUT inputs are faster than others). The CAD tools at the time of VTR 7 does
|
||||
not consider differences in LUT input delays.
|
||||
|
||||
Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.
|
||||
Delay obtained by compiling a 256 bit adder (registered inputs and outputs,
|
||||
all pins except clock virtual) then measuring the delays in chip-planner,
|
||||
sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns,
|
||||
inter-block carry delay = 0.327 ns. Given this data, I will approximate
|
||||
sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and
|
||||
inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has
|
||||
overhead that we don't have, I'll approximate the delay of a simpler chain at
|
||||
one half what they have. This is very rough, anything from 0.01ns to 0.327ns
|
||||
can be justified).
|
||||
|
||||
Logic block area numbers obtained by scaling overall tile area of a 65nm
|
||||
Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out
|
||||
routing area at a channel width of 300. We use a channel width of 300 because it can route
|
||||
all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
|
||||
total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
|
||||
choosing a width that provides high routability. The architecture can be routed at different channel
|
||||
widths, but we estimate the tile size and hence the physical length of routing wires assuming
|
||||
a channel width of 300.
|
||||
|
||||
Sanity checks employed:
|
||||
1. We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches
|
||||
common electrical design.
|
||||
|
||||
|
||||
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
|
||||
-->
|
||||
<architecture>
|
||||
<!--
|
||||
ODIN II specific config begins
|
||||
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||
".model [type_of_block]") that this architecture supports.
|
||||
|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<model name="adder">
|
||||
<input_ports>
|
||||
<port name="a" combinational_sink_ports="sumout cout"/>
|
||||
<port name="b" combinational_sink_ports="sumout cout"/>
|
||||
<port name="cin" combinational_sink_ports="sumout cout"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="cout"/>
|
||||
<port name="sumout"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="frac_lut6">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut4_out"/>
|
||||
<port name="lut5_out"/>
|
||||
<port name="lut6_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="dpram_1024x8">
|
||||
<input_ports>
|
||||
<!-- write address lines -->
|
||||
<port name="waddr" clock="clk"/>
|
||||
<!-- read address lines -->
|
||||
<port name="raddr" clock="clk"/>
|
||||
<!-- data lines can be broken down into smaller bit widths minimum size 1 -->
|
||||
<port name="data_in" clock="clk"/>
|
||||
<!-- write enable -->
|
||||
<port name="wen" clock="clk"/>
|
||||
<!-- read enable -->
|
||||
<port name="ren" clock="clk"/>
|
||||
<!-- memories are often clocked -->
|
||||
<port name="clk" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<!-- output can be broken down into smaller bit widths minimum size 1 -->
|
||||
<port name="data_out" clock="clk"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<tile name="io" capacity="8" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad</loc>
|
||||
<loc side="top">io.outpad io.inpad</loc>
|
||||
<loc side="right">io.outpad io.inpad</loc>
|
||||
<loc side="bottom">io.outpad io.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<tile name="clb" area="53894">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="40" equivalent="full"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="O" num_pins="20" equivalent="none"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="cout" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<!-- Highly recommand to customize pin location when direct connection is used!!! -->
|
||||
<!--pinlocations pattern="spread"/-->
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">clb.clk</loc>
|
||||
<loc side="top">clb.cin</loc>
|
||||
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
|
||||
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<tile name="memory" height="2" area="548000">
|
||||
<equivalent_sites>
|
||||
<site pb_type="memory"/>
|
||||
</equivalent_sites>
|
||||
<input name="waddr" num_pins="10"/>
|
||||
<input name="raddr" num_pins="10"/>
|
||||
<input name="data_in" num_pins="8"/>
|
||||
<input name="wen" num_pins="1"/>
|
||||
<input name="ren" num_pins="1"/>
|
||||
<output name="data_out" num_pins="8"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<!--pinlocations pattern="spread"/-->
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">memory.clk</loc>
|
||||
<loc side="top"></loc>
|
||||
<loc side="right">memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
|
||||
<loc side="bottom">memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true" through_channel="false">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
|
||||
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
|
||||
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="3x2" width="5" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
|
||||
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
|
||||
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<directlist>
|
||||
<direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
|
||||
</directlist>
|
||||
<complexblocklist>
|
||||
<!-- Define I/O pads begin -->
|
||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||
-->
|
||||
<!-- Place I/Os on the sides of the FPGA -->
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define general purpose logic block (CLB) begin -->
|
||||
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||
block. Note that the crossbar / local interconnect is considered part of the logic block
|
||||
area in this analysis. That is a lower proportion of of routing area than most academics
|
||||
assume, but note that the total routing area really includes the crossbar, which would push
|
||||
routing area up significantly, we estimate into the ~70% range.
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="40" equivalent="full"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="O" num_pins="20" equivalent="none"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Describe fracturable logic element.
|
||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||
The outputs of the fracturable logic element can be optionally registered
|
||||
-->
|
||||
<pb_type name="fle" num_pb="10">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="fabric" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="lut4_out" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="lut4_out" num_pins="4"/>
|
||||
<output name="lut5_out" num_pins="2"/>
|
||||
<output name="lut6_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
|
||||
<direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
|
||||
<direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
|
||||
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
|
||||
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<!-- Define adders -->
|
||||
<pb_type name="adder" blif_model=".subckt adder" num_pb="2">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="sumout" num_pins="1"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
|
||||
<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
|
||||
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
|
||||
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
|
||||
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
|
||||
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
|
||||
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
|
||||
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
|
||||
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
|
||||
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
|
||||
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct2" input="fle.cin" output="fabric.cin"/>
|
||||
<direct name="direct3" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct4" input="fabric.cout" output="fle.cout"/>
|
||||
<direct name="direct5" input="fle.clk" output="fabric.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<!-- BEGIN fle mode of dual lut5 -->
|
||||
<mode name="n2_lut5">
|
||||
<pb_type name="ble5" num_pb="2">
|
||||
<input name="in" num_pins="5"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Regular LUT mode -->
|
||||
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in" output="lut5.in"/>
|
||||
<direct name="direct2" input="lut5.out" output="ff.D">
|
||||
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble5.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
|
||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
|
||||
<direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
|
||||
<complete name="direct3" input="fle.clk" output="ble5.clk"/>
|
||||
<direct name="direct4" input="ble5.out" output="fle.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- END fle mode of dual lut5 -->
|
||||
<!-- BEGIN arithmetic mode of dual lut4 + adders -->
|
||||
<mode name="arithmetic">
|
||||
<pb_type name="arithmetic" num_pb="2">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Special dual-LUT mode that drives adder only -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
195e-12
|
||||
195e-12
|
||||
195e-12
|
||||
195e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="adder" blif_model=".subckt adder" num_pb="1">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="sumout" num_pins="1"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
|
||||
<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="clock" input="arithmetic.clk" output="ff.clk"/>
|
||||
<direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
|
||||
<direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
|
||||
<direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
|
||||
</direct>
|
||||
<direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
|
||||
</direct>
|
||||
<direct name="add_to_ff" input="adder.sumout" output="ff.D">
|
||||
<pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="carry_in" input="arithmetic.cin" output="adder.cin">
|
||||
<pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
|
||||
</direct>
|
||||
<direct name="carry_out" input="adder.cout" output="arithmetic.cout">
|
||||
<pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
|
||||
</direct>
|
||||
<mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
|
||||
<delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
|
||||
<direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
|
||||
<direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
|
||||
<pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
|
||||
</direct>
|
||||
<direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
|
||||
<pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
|
||||
</direct>
|
||||
<direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
|
||||
<pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
|
||||
</direct>
|
||||
<complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
|
||||
<direct name="direct4" input="arithmetic.out" output="fle.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n2_lut5 -->
|
||||
<mode name="n1_lut6">
|
||||
<pb_type name="ble6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
397e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
|
||||
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n1_lut6 -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB
|
||||
The delays below come from Stratix IV. the delay through a connection block
|
||||
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||
delay within the crossbar is 95 ps.
|
||||
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
|
||||
</complete>
|
||||
|
||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
naive specification).
|
||||
-->
|
||||
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
||||
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
||||
<!-- Carry chain links -->
|
||||
<direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
<pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
|
||||
</direct>
|
||||
<direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
|
||||
<pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
|
||||
</direct>
|
||||
<direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
|
||||
<pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
<!-- Define single-mode dual-port memory begin -->
|
||||
<pb_type name="memory">
|
||||
<input name="waddr" num_pins="10"/>
|
||||
<input name="raddr" num_pins="10"/>
|
||||
<input name="data_in" num_pins="8"/>
|
||||
<input name="wen" num_pins="1"/>
|
||||
<input name="ren" num_pins="1"/>
|
||||
<output name="data_out" num_pins="8"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Specify the 1024x8=8Kbit memory block
|
||||
Note: the delay numbers are extracted from VPR flagship XML without modification
|
||||
Should align to the process technology we using to create the 16K dual-port RAM
|
||||
-->
|
||||
<mode name="mem_1024x8_dp">
|
||||
<pb_type name="mem_1024x8_dp" blif_model=".subckt dpram_1024x8" num_pb="1">
|
||||
<input name="waddr" num_pins="10" port_class="address1"/>
|
||||
<input name="raddr" num_pins="10" port_class="address2"/>
|
||||
<input name="data_in" num_pins="8" port_class="data_in1"/>
|
||||
<input name="wen" num_pins="1" port_class="write_en1"/>
|
||||
<input name="ren" num_pins="1" port_class="write_en2"/>
|
||||
<output name="data_out" num_pins="8" port_class="data_out1"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="509e-12" port="mem_1024x8_dp.waddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_1024x8_dp.raddr" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_1024x8_dp.data_in" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_1024x8_dp.wen" clock="clk"/>
|
||||
<T_setup value="509e-12" port="mem_1024x8_dp.ren" clock="clk"/>
|
||||
<T_clock_to_Q max="1.234e-9" port="mem_1024x8_dp.data_out" clock="clk"/>
|
||||
<power method="pin-toggle">
|
||||
<port name="clk" energy_per_toggle="17.9e-12"/>
|
||||
<static_power power_per_instance="0.0"/>
|
||||
</power>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="waddress" input="memory.waddr" output="mem_1024x8_dp.waddr">
|
||||
<delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_1024x8_dp.waddr"/>
|
||||
</direct>
|
||||
<direct name="raddress" input="memory.raddr" output="mem_1024x8_dp.raddr">
|
||||
<delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_1024x8_dp.raddr"/>
|
||||
</direct>
|
||||
<direct name="data_input" input="memory.data_in" output="mem_1024x8_dp.data_in">
|
||||
<delay_constant max="132e-12" in_port="memory.data_in" out_port="mem_1024x8_dp.data_in"/>
|
||||
</direct>
|
||||
<direct name="writeen" input="memory.wen" output="mem_1024x8_dp.wen">
|
||||
<delay_constant max="132e-12" in_port="memory.wen" out_port="mem_1024x8_dp.wen"/>
|
||||
</direct>
|
||||
<direct name="readen" input="memory.ren" output="mem_1024x8_dp.ren">
|
||||
<delay_constant max="132e-12" in_port="memory.ren" out_port="mem_1024x8_dp.ren"/>
|
||||
</direct>
|
||||
<direct name="dataout" input="mem_1024x8_dp.data_out" output="memory.data_out">
|
||||
<delay_constant max="40e-12" in_port="mem_1024x8_dp.data_out" out_port="memory.data_out"/>
|
||||
</direct>
|
||||
<direct name="clk" input="memory.clk" output="mem_1024x8_dp.clk">
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<!-- Define single-mode dual-port memory end -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
Loading…
Reference in New Issue