From 76837e02e6dff68aa0c62430e6049f25347d0a0a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 16:16:53 -0600 Subject: [PATCH 01/17] [Script] Rename yosys script supporting bram and restructure techlib files --- .../misc/yosys_bram_adder_template.ys | 41 ------------------- .../openfpga_arith_map.v} | 0 .../openfpga_brams.txt} | 0 .../openfpga_brams_map.v} | 0 .../openfpga_brams_sim.v} | 0 5 files changed, 41 deletions(-) delete mode 100644 openfpga_flow/misc/yosys_bram_adder_template.ys rename openfpga_flow/{misc/OpenFPGA_lib/fpga_techmap.v => openfpga_yosys_techlib/openfpga_arith_map.v} (100%) rename openfpga_flow/{misc/OpenFPGA_lib/brams.txt => openfpga_yosys_techlib/openfpga_brams.txt} (100%) rename openfpga_flow/{misc/OpenFPGA_lib/brams_map.v => openfpga_yosys_techlib/openfpga_brams_map.v} (100%) rename openfpga_flow/{misc/OpenFPGA_lib/cells_sim.v => openfpga_yosys_techlib/openfpga_brams_sim.v} (100%) diff --git a/openfpga_flow/misc/yosys_bram_adder_template.ys b/openfpga_flow/misc/yosys_bram_adder_template.ys deleted file mode 100644 index fe82173f4..000000000 --- a/openfpga_flow/misc/yosys_bram_adder_template.ys +++ /dev/null @@ -1,41 +0,0 @@ -# Yosys synthesis script for alu4 -# read Verilog -read_verilog /full_path/design.v #can be repeated if project has many files -read_verilog -lib /full_path/cells_sim.v # file we provide - -hierarchy -check -top top_module -proc - -flatten -tribuf -logic - -synth -run coarse -opt -fast - -memory -nomap -opt_clean - - -memory_bram -rules /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams.txt -techmap -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/brams_map.v -opt -fast -mux_undef -undriven -fine -memory_map - -# Technology mapping -#proc -techmap -D NO_LUT -map /full_OpenFPGA_path/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v -map +/adff2dff.v - -# Synthesis -synth -top top_module -flatten -run fine -clean - -# LUT mapping -abc -lut 6 - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_blif design.blif -write_verilog design.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/fpga_techmap.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/brams.txt b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/brams.txt rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt diff --git a/openfpga_flow/misc/OpenFPGA_lib/brams_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/brams_map.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v diff --git a/openfpga_flow/misc/OpenFPGA_lib/cells_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v similarity index 100% rename from openfpga_flow/misc/OpenFPGA_lib/cells_sim.v rename to openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v From 090f483a112abf42339d7d0507fbf7943788792d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 16:45:57 -0600 Subject: [PATCH 02/17] [Script] Now task-run script support the use of env variables openfpga_path in yosys scripts --- openfpga_flow/scripts/run_fpga_flow.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index e91d34a78..9205879b3 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -481,14 +481,13 @@ def run_yosys_with_abc(): clean_up_and_exit("") args.K = lut_size # Yosys script parameter mapping - ys_params = { - "READ_VERILOG_FILE": " \n".join([ + ys_params = script_env_vars["PATH"] + ys_params["READ_VERILOG_FILE"] = " \n".join([ "read_verilog -nolatches " + shlex.quote(eachfile) - for eachfile in args.benchmark_files]), - "TOP_MODULE": args.top_module, - "LUT_SIZE": lut_size, - "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", - } + for eachfile in args.benchmark_files]) + ys_params["TOP_MODULE"] = args.top_module + ys_params["LUT_SIZE"] = lut_size + ys_params["OUTPUT_BLIF"] = args.top_module+"_yosys_out.blif" for indx in range(0, len(OpenFPGAArgs), 2): tmpVar = OpenFPGAArgs[indx][2:].upper() From 84778bd38d4c8f61c07635da8a51f2972d5c9101 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 16:52:18 -0600 Subject: [PATCH 03/17] [Script] Add new yosys script to support architectures with BRAMs --- .../misc/ys_tmpl_yosys_vpr_bram_flow.ys | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys new file mode 100644 index 000000000..b7d7671c7 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys @@ -0,0 +1,76 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +######################### +# Run coarse synthesis +######################### +synth -run coarse +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt +techmap -map ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map flip-flops +######################### +techmap -map +/adff2dff.v +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} From 73b06256d087a5b11ee5d5f5e40b9b68c7a96681 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 16:52:59 -0600 Subject: [PATCH 04/17] [Test] Deploy the new yosys script supporting BRAM to regression tests --- .../basic_tests/k4_series/k4n4_bram/config/task.conf | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index ff0985799..dfeb94f35 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -12,8 +12,8 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif +timeout_each_job = 3*60 +fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga @@ -25,13 +25,11 @@ openfpga_vpr_device_layout=3x2 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v [SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From cea43c2c4529ba8b4fd8598228996085b2540451 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 18:04:31 -0600 Subject: [PATCH 05/17] [HDL] Add SPRAM module to generic yosys tech lib for openfpga usage --- .../openfpga_adders_sim.v | 15 +++++++++ .../openfpga_brams_sim.v | 31 ++++++++++++++----- 2 files changed, 38 insertions(+), 8 deletions(-) create mode 100644 openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v new file mode 100644 index 000000000..9d82dc715 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v @@ -0,0 +1,15 @@ +//--------------------------------------- +// 1-bit adder +//--------------------------------------- +module adder( + input cin, + input a, + input b, + output cout, + output sumout ); + + + assign sumout = a ^ b ^ cin; + assign cout = (a & b) | ((a | b) & cin); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v index 514aefd85..5f8a12e5a 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v @@ -48,15 +48,30 @@ module dual_port_sram ( endmodule -module adder( - input cin, - input a, - input b, - output cout, - output sumout ); +//--------------------------------------- +// A single-port 32x8bit RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram ( + input clk, + input we, + input [4:0] addr, + input [7:0] data, + output [7:0] out ); + reg [7:0] ram[31:0]; + reg [7:0] internal; - assign sumout = a ^ b ^ cin; - assign cout = (a & b) | ((a | b) & cin); + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end endmodule From 094b3e9b901db5689688837d7ae1434504183b05 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 19:51:48 -0600 Subject: [PATCH 06/17] [Script] Use parameters in template yosys script supporting BRAMs --- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys index b7d7671c7..267a4b991 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys @@ -6,7 +6,7 @@ # Read verilog files ${READ_VERILOG_FILE} # Read technology library -read_verilog -lib -specify ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} ######################### # Prepare for synthesis @@ -40,8 +40,8 @@ opt_clean ######################### # Map logics to BRAMs ######################### -memory_bram -rules ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt -techmap -map ${OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} opt -fast -mux_undef -undriven -fine memory_map opt -undriven -fine From d12a8a03fd4e275d69fad4cb9d6aebc22cd83693 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Mar 2021 19:52:17 -0600 Subject: [PATCH 07/17] [Test] Update test case using yosys bram parameters --- .../tasks/basic_tests/k4_series/k4n4_bram/config/task.conf | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index dfeb94f35..6caa13456 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -20,6 +20,10 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml From 76113a80fa9515084de16b582d82ffd5fc410797 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:09:12 -0600 Subject: [PATCH 08/17] [HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture --- ...tileable_adder_chain_dpram8K_40nm_bram.txt | 18 ++++++ ...leable_adder_chain_dpram8K_40nm_bram_map.v | 21 +++++++ ...leable_adder_chain_dpram8K_40nm_cell_sim.v | 59 +++++++++++++++++++ .../openfpga_brams_sim.v | 26 -------- 4 files changed, 98 insertions(+), 26 deletions(-) create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt new file mode 100644 index 000000000..00e6a7ce2 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt @@ -0,0 +1,18 @@ +bram $__MY_DPRAM_1024x8 + init 0 + abits 10 + dbits 8 + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + +match $__MY_DPRAM_1024x8 + min efficiency 0 + make_transp +endmatch + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v new file mode 100644 index 000000000..fdc8bef43 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v @@ -0,0 +1,21 @@ +module $__MY_DPRAM_1024x8 ( + output [7:0] B1DATA, + input CLK1, + input [9:0] B1ADDR, + input [9:0] A1ADDR, + input [7:0] A1DATA, + input A1EN, + input B1EN ); + + generate + dpram_1024x8 #() _TECHMAP_REPLACE_ ( + .clk (CLK1), + .wen (A1EN), + .waddr (A1ADDR), + .data_in (A1DATA), + .ren (B1EN), + .raddr (B1ADDR), + .data_out (B1DATA) ); + endgenerate + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v new file mode 100644 index 000000000..9d9c61636 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v @@ -0,0 +1,59 @@ +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) +// Core logic +//----------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [9:0] waddr, + input [7:0] data_in, + input rclk, + input ren, + input [9:0] raddr, + output [7:0] data_out ); + + reg [7:0] ram[1023:0]; + reg [7:0] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input [9:0] waddr, + input [9:0] raddr, + input [7:0] data_in, + output [7:0] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v index 5f8a12e5a..cd1f2e8f4 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v @@ -48,30 +48,4 @@ module dual_port_sram ( endmodule -//--------------------------------------- -// A single-port 32x8bit RAM -// This module is tuned for VTR's benchmarks -//--------------------------------------- -module single_port_ram ( - input clk, - input we, - input [4:0] addr, - input [7:0] data, - output [7:0] out ); - reg [7:0] ram[31:0]; - reg [7:0] internal; - - assign out = internal; - - always @(posedge clk) begin - if(wen) begin - ram[addr] <= data; - end - - if(ren) begin - internal <= ram[addr]; - end - end - -endmodule From 910f8471dd88471e44596afb6598711aff18bc62 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:10:05 -0600 Subject: [PATCH 09/17] [Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys) --- ..._N10_adder_chain_dpram8K_40nm_openfpga.xml | 273 +++++++ ..._N10_tileable_adder_chain_dpram8K_40nm.xml | 748 ++++++++++++++++++ 2 files changed, 1021 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_40nm_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_40nm.xml diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_40nm_openfpga.xml new file mode 100644 index 000000000..37beb67bf --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_40nm_openfpga.xml @@ -0,0 +1,273 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_40nm.xml new file mode 100644 index 000000000..d697a1e8d --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_40nm.xml @@ -0,0 +1,748 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + memory.clk + + memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From deee7ba366452c02131135d399d0e5b21ddbe080 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:10:56 -0600 Subject: [PATCH 10/17] [Script] Add example script to run vtr benchmarks --- .../vtr_benchmark_example_script.openfpga | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga new file mode 100644 index 000000000..999ba8dfc --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga @@ -0,0 +1,80 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +# Note: no need to assign activity file when you used a fixed number +# of clock cycles in simulation settings +# Also, ACE2 does not support multiple clocks +# Therefore, activity file is not recommended for multi-clock fabric/implementations +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --include_signal_init --support_icarus_simulator #--explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory From 1976a8068f47578480a8276b21198ef4dddc5b1e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:11:17 -0600 Subject: [PATCH 11/17] [Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added) --- .../vtr_benchmarks/config/task.conf | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf new file mode 100644 index 000000000..ee728be59 --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf @@ -0,0 +1,40 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +# Yosys script parameters +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v + +[SYNTHESIS_PARAM] +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +# Benchmark ch_intrinsics +bench0_top = memset + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist= From 7eeb35d21f575a4fc6022de0fc56e15df825633f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:12:04 -0600 Subject: [PATCH 12/17] [Script] Bug fix in yosys script to synthesis BRAM --- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys index 267a4b991..d680cf71c 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_flow.ys @@ -30,7 +30,18 @@ opt ######################### # Run coarse synthesis ######################### -synth -run coarse +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean +# Extract arithmetic functions +alumacc +opt +fsm # Run a quick follow-up optimization to sweep out unused nets/signals opt -fast # Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells From 08a86e056add41c9341878f20a2cc5007b2a9e99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:13:58 -0600 Subject: [PATCH 13/17] [Test] Add vtr benchmark regression test --- .../regression_test_scripts/vtr_benchmark_reg_test.sh | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100755 openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh diff --git a/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh new file mode 100755 index 000000000..ead638405 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/vtr_benchmark_reg_test.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "VTR benchmark regression tests"; +run-task benchmark_sweep/vtr_benchmarks --debug --show_thread_logs From f9dc7c1b54dc3a272516d67272969f883923fe1d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:15:22 -0600 Subject: [PATCH 14/17] [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells --- .../openfpga_cell_library/verilog/dpram8k.v | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dpram8k.v diff --git a/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v new file mode 100644 index 000000000..bf5b630be --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dpram8k.v @@ -0,0 +1,61 @@ +//----------------------------------------------------- +// Design Name : dpram_1024x8 +// File Name : dpram8.v +// Function : Wrapper module of dual port RAM 1024 addresses x 8 bit +// Coder : Xifan tang +//----------------------------------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input[0:9] waddr, + input[0:9] raddr, + input[0:7] data_in, + output[0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------------------------------- +// Design Name : dpram_1024x8_core +// File Name : dpram8.v +// Function : Core module of dual port RAM 1024 addresses x 8 bit +// Coder : Xifan tang +//----------------------------------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg[0:7] ram[0:1023]; + reg[0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule From 7a986defba236e8e070812a874aab1c65f56a8bb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:15:54 -0600 Subject: [PATCH 15/17] [CI] Deploy vtr benchmark regression test to CI --- .github/workflows/build.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 9b81db480..c94e91abd 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -256,6 +256,7 @@ jobs: - name: fpga_sdc_reg_test - name: fpga_spice_reg_test - name: quicklogic_reg_test + - name: vtr_benchmark_reg_test steps: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 From 6bf4880c50ec3313b912cb8a1f9d3abfb2007a23 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 15:24:26 -0600 Subject: [PATCH 16/17] [benchmark] Add vtr benchmark --- .../benchmarks/vtr_benchmark/LU32PEEng.v | 5433 ++++ .../benchmarks/vtr_benchmark/LU64PEEng.v | 6009 ++++ .../benchmarks/vtr_benchmark/LU8PEEng.v | 5001 ++++ .../benchmarks/vtr_benchmark/arm_core.v | 8210 +++++ openfpga_flow/benchmarks/vtr_benchmark/bgm.v | 2659 ++ .../benchmarks/vtr_benchmark/blob_merge.v | 1617 + .../benchmarks/vtr_benchmark/boundtop.v | 2820 ++ .../benchmarks/vtr_benchmark/ch_intrinsics.v | 317 + .../benchmarks/vtr_benchmark/diffeq1.v | 56 + .../benchmarks/vtr_benchmark/diffeq2.v | 63 + .../vtr_benchmark/matmul_8x8_fp16.v | 1662 ++ openfpga_flow/benchmarks/vtr_benchmark/mcml.v | 24777 ++++++++++++++++ .../vtr_benchmark/mkDelayWorker32B.v | 6582 ++++ .../benchmarks/vtr_benchmark/mkPktMerge.v | 1494 + .../benchmarks/vtr_benchmark/mkSMAdapter4B.v | 4375 +++ .../benchmarks/vtr_benchmark/or1200.v | 5236 ++++ .../benchmarks/vtr_benchmark/raygentop.v | 2976 ++ openfpga_flow/benchmarks/vtr_benchmark/sha.v | 2171 ++ .../benchmarks/vtr_benchmark/spree.v | 3063 ++ .../benchmarks/vtr_benchmark/stereovision0.v | 3905 +++ .../benchmarks/vtr_benchmark/stereovision1.v | 2553 ++ .../benchmarks/vtr_benchmark/stereovision2.v | 1846 ++ .../benchmarks/vtr_benchmark/stereovision3.v | 1054 + .../benchmarks/vtr_benchmark/tpu.16x16.int8.v | 5711 ++++ .../benchmarks/vtr_benchmark/tpu.32x32.int8.v | 15437 ++++++++++ 25 files changed, 115027 insertions(+) create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v create mode 100644 openfpga_flow/benchmarks/vtr_benchmark/arm_core.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/bgm.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/boundtop.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v create mode 100644 openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/mcml.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/or1200.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/raygentop.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/sha.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/spree.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v create mode 100755 openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v create mode 100644 openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v create mode 100644 openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v diff --git a/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v b/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v new file mode 100755 index 000000000..ddda843d6 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v @@ -0,0 +1,5433 @@ +//auto-generated top.v +//top level module of LU factorization +//by Wei Zhang + +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0111 +`define DDRWIDTH 7'b0100000 +`define DDRNUMDQS 4'b0100 +`define DDRSIZEWIDTH 6'b011000 +`define BURSTLEN 3'b010 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define RAMWIDTH 12'b010000000000 +`define RAMNUMBYTES 9'b010000000 +`define RAMSIZEWIDTH 4'b0111 +`define TOPWIDTH 7'b0100000 +`define rFIFOINPUTWIDTH 8'b01000000 +`define wFIFOINPUTWIDTH 12'b010000000000 +`define mFIFOWIDTH 6'b011100 +`define aFIFOWIDTH 4'b0111 + +module LU32PEEng (clk, //ref_clk, global_reset_n, + start, N, offset, done, + //mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, +burst_begin, +mem_local_be, +mem_local_read_req, +mem_local_size, +mem_local_wdata, +mem_local_write_req, +mem_local_rdata, +mem_local_rdata_valid, +mem_local_ready, +mem_local_wdata_req, +reset_n, +mem_local_addr +//Cong: dummy output +//a_junk, +//w_junk, +//m_junk, +//r_junk, +//Cong:dummy output +//junk_r, +//junk_r1, +//junk_r2, +//junk_r3, +//junk_top + ); + +input start; +input[`NWIDTH-1:0] N; +input[`DDRSIZEWIDTH-1:0] offset; +output done; +input clk; + +output burst_begin; +output [`MEMCONNUMBYTES-1:0] mem_local_be; +output mem_local_read_req; +output [`BURSTLEN-1:0] mem_local_size; +output [`MEMCONWIDTH-1:0] mem_local_wdata; +output mem_local_write_req; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +input [`MEMCONWIDTH-1:0] mem_local_rdata; +input mem_local_rdata_valid; +input mem_local_ready; +input reset_n; +input mem_local_wdata_req; +wire[`BLOCKWIDTH-1:0] m, n, loop; +wire[1:0] mode; +wire comp_start, comp_done; +wire dtu_write_req, dtu_read_req, dtu_ack, dtu_done; +wire [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +wire [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +wire [`BLOCKWIDTH-1:0] dtu_size; +wire left_sel; + +wire[`RAMWIDTH-1:0] curWriteDataMem, curReadDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnMem; +wire curWriteEnMem; +wire[`RAMWIDTH-1:0] leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +wire leftWriteEnMem; +wire curMemSel, leftMemSel; + +wire burst_begin; +wire [`MEMCONNUMBYTES-1:0] mem_local_be; +wire mem_local_read_req; +wire [`BURSTLEN-1:0] mem_local_size; +wire [`MEMCONWIDTH-1:0] mem_local_wdata; +wire mem_local_write_req; +wire [`MEMCONWIDTH-1:0] mem_local_rdata; +wire mem_local_rdata_valid; +wire mem_local_ready; +wire mem_local_wdata_req; +wire reset_n; +wire [`DDRSIZEWIDTH-1:0] mem_local_addr; + +wire[`RAMWIDTH-1:0] ram_write_data, ram_read_data; +wire[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +wire[`RAMNUMBYTES-1:0] ram_write_byte_en; +wire ram_write_en; + +MarshallerController MC (clk, start, done, N, offset, + comp_start, m, n, loop, mode, comp_done, curMemSel, leftMemSel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + +// block that computes the LU factorization, with answer stored back into ram block +LU compBlock (clk, comp_start, m, n, loop, mode, comp_done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel); + +DataTransferUnit DTU (.clk(clk), .dtu_write_req(dtu_write_req), .dtu_read_req(dtu_read_req), .dtu_mem_addr(dtu_mem_addr), .dtu_ram_addr(dtu_ram_addr), .dtu_size(dtu_size), .dtu_ack(dtu_ack), .dtu_done(dtu_done), + .ram_read_addr(ram_read_addr), .ram_read_data(ram_read_data), .ram_write_byte_en(ram_write_byte_en), .ram_write_data(ram_write_data), .ram_write_addr(ram_write_addr), .ram_write_en(ram_write_en), + .mem_rdata(mem_local_rdata), .mem_rdata_valid(mem_local_rdata_valid), .mem_ready(mem_local_ready), .mem_wdata_req(mem_local_wdata_req), .reset_n(reset_n), + .burst_begin(burst_begin), .mem_local_addr(mem_local_addr), .mem_be(mem_local_be), .mem_read_req(mem_local_read_req), .mem_size(mem_local_size), + .mem_wdata(mem_local_wdata), .mem_write_req(mem_local_write_req) + //Cong: dummy output + ); + +assign curReadAddrMem = ram_read_addr; +assign curWriteByteEnMem = ram_write_byte_en; +assign curWriteDataMem = ram_write_data; +assign curWriteAddrMem = ram_write_addr; +assign curWriteEnMem = ram_write_en && (left_sel == 0); +assign leftWriteByteEnMem = ram_write_byte_en; +assign leftWriteDataMem = ram_write_data; +assign leftWriteAddrMem = ram_write_addr; +assign leftWriteEnMem = ram_write_en && (left_sel == 1); +assign ram_read_data = curReadDataMem; +endmodule +`define BLOCKM 8'b01000000 +`define BLOCKN 8'b01000000 +`define BLOCKMDIVK 3'b010 +`define MEMBLOCKM 7'b0100000 +`define MEMBLOCKN 7'b0100000 +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0111 +`define DDRSIZEWIDTH 6'b011000 +`define RAMSIZEWIDTH 4'b0111 +`define START 1'b0 //0 +`define SETUP 2'b01 //1 +`define FIRST 3'b010 //2 +`define MODE0_SETUP 3'b011 //3 +`define MODE0_WAIT 4'b0100 //4 +`define MODE0 4'b0101 //5 +`define MODE1_SETUP 4'b0110 //6 +`define MODE1_WAIT 4'b0111 //7 +`define MODE1 5'b01000 //8 +`define MODE2_SETUP 5'b01001 //9 +`define MODE2_WAIT 5'b01010 //10 +`define MODE2 5'b01011 //11 +`define MODE3_SETUP 5'b01100 //12 +`define MODE3_WAIT 5'b01101 //13 +`define MODE3 5'b01110 //14 +`define STALL 5'b01111 //15 +`define STALL_WAIT 6'b010000 //16 +`define WAIT 6'b010001 //17 +`define FINAL_WRITE 6'b010010 //18 +`define FINAL_WAIT 6'b010011 //19 +`define IDLE 6'b010100 //20 +`define LAST_SETUP 6'b010101 //21 +`define LAST_SETUP_WAIT 6'b010110 //22 +`define LAST 6'b010111 //23 +`define LAST_WAIT 6'b011000 //24 +`define MEM_IDLE 1'b0 //0 +`define MEM_WRITE 2'b01 //1 +`define MEM_WRITE_WAIT 3'b010 //2 +`define MEM_CHECK_DONE 3'b011 //3 +`define MEM_READ 4'b0100 //4 +`define MEM_READ_WAIT 4'b0101 //5 +`define MEM_DONE 4'b0110 //6 +`define MEM_WAIT_DONE 4'b0111 //7 + +module MarshallerController (clk, start, done, input_N, offset, + comp_start, block_m, block_n, loop, mode, comp_done, cur_mem_sel, left_mem_sel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + + +input clk; +input start; +output done; +input [`NWIDTH-1:0] input_N; +input [`DDRSIZEWIDTH-1:0] offset; + +// for computation section +output comp_start; +output [`BLOCKWIDTH-1:0] block_m, block_n, loop; +output [1:0] mode; +input comp_done; +output cur_mem_sel, left_mem_sel; + +// for data marshaller section +output dtu_write_req, dtu_read_req; +output [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +output [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +output [`BLOCKWIDTH-1:0] dtu_size; +input dtu_ack, dtu_done; +output left_sel; + +reg [4:0] cur_state, next_state; +reg [`NWIDTH-1:0] comp_N, N, mcount, ncount, Ndivk, mem_N; +reg [1:0] mode; +reg [`BLOCKWIDTH-1:0] block_m, block_n, loop, read_n; +reg [`BLOCKWIDTH-1:0] write_n, write_n_buf; +reg left_mem_sel, cur_mem_sel, no_left_switch; + +reg [3:0] cur_mem_state, next_mem_state; +reg [`RAMSIZEWIDTH-1:0] ram_addr; +reg [`DDRSIZEWIDTH-1:0] mem_addr; +reg [`DDRSIZEWIDTH-1:0] mem_base, mem_top, mem_write, mem_left, mem_cur; +reg [`DDRSIZEWIDTH-1:0] mem_write_buf; +reg [`BLOCKWIDTH-1:0] mem_count; +reg [1:0] mem_read; +reg [`BLOCKWIDTH-1:0] mem_write_size, mem_write_size_buf, mem_read_size; +wire mem_done; + +assign done = (cur_state == `IDLE); +assign dtu_ram_addr = ram_addr; +assign dtu_mem_addr = mem_addr; +assign dtu_size = (cur_mem_state == `MEM_WRITE) ? mem_write_size : mem_read_size; +assign comp_start = (cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)||(cur_state == `FIRST)||(cur_state == `LAST); +assign dtu_write_req = (cur_mem_state == `MEM_WRITE); +assign dtu_read_req = (cur_mem_state == `MEM_READ); +assign mem_done = (cur_mem_state == `MEM_DONE)&&(dtu_done == 1'b1); +assign left_sel = mem_read == 2'b01 && (cur_mem_state == `MEM_READ || cur_mem_state == `MEM_READ_WAIT || cur_mem_state == `MEM_WAIT_DONE); + +// FSM to produce memory instructions to DTU +always @ (posedge clk) +begin + case (cur_mem_state) + `MEM_IDLE: + begin + if (cur_state == `START) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_IDLE; + end + `MEM_DONE: + begin + if (cur_state == `MODE0 || cur_state == `MODE1 || cur_state == `MODE2 || + cur_state == `MODE3 || cur_state == `FINAL_WRITE || cur_state == `LAST_SETUP) + next_mem_state <= `MEM_WRITE; + else if (cur_state == `FIRST) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_DONE; + end + `MEM_WRITE: + begin + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WRITE_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == write_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_WRITE; + end + else + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WAIT_DONE: + begin + if (dtu_done == 1'b1) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_WAIT_DONE; + end + `MEM_CHECK_DONE: + begin + if (mem_read == 2'b10) + next_mem_state <= `MEM_DONE; + else + next_mem_state <= `MEM_READ; + end + `MEM_READ: + begin + next_mem_state <= `MEM_READ_WAIT; + end + `MEM_READ_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == read_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_READ; + end + else + next_mem_state <= `MEM_READ_WAIT; + end + default: + next_mem_state <= `MEM_IDLE; + endcase +end + +always @ (posedge clk) +begin + if (cur_mem_state == `MEM_DONE || cur_mem_state == `MEM_IDLE) + begin + ram_addr <= 7'b0; + mem_addr <= mem_write; + if (next_state == `LAST_WAIT || next_state == `FINAL_WAIT || next_state == `STALL) + mem_read <= 2'b00; + else if (next_state == `MODE0_SETUP || next_state == `SETUP || cur_state == `MODE0 || next_state == `LAST_SETUP_WAIT) + mem_read <= 2'b01; + else + mem_read <= 2'b10; + mem_count <= 7'b0; + end + else if (cur_mem_state == `MEM_CHECK_DONE) + begin + if (mem_read == 2'b10) + begin + mem_addr <= mem_left; + read_n <= loop; + end + else + begin + mem_addr <= mem_cur; + read_n <= block_n; + end + mem_read <= mem_read - 2'b01; + mem_count <= 7'b0; + ram_addr <= 7'b0; + end + else if (cur_mem_state == `MEM_WRITE || cur_mem_state == `MEM_READ) + begin + ram_addr <= ram_addr + `BLOCKMDIVK; + mem_addr <= mem_addr + Ndivk; + mem_count <= mem_count + 2'b01; + end + +end + +// FSM to determine the block LU factorization algorithm +always @ (posedge clk) +begin + case (cur_state) + `START: + begin + next_state <= `SETUP; + end + `SETUP: + begin + next_state <= `WAIT; + end + `WAIT: + begin + if (mem_done == 1'b1) + next_state <= `FIRST; + else + next_state <= `WAIT; + + end + `FIRST: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + next_state <= `LAST_WAIT; + end + `MODE0_SETUP: + begin + next_state <= `MODE0_WAIT; + end + `MODE0_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE0; + else + next_state <= `MODE0_WAIT; + + end + `MODE0: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + begin + next_state <= `LAST_WAIT; + end + end + `MODE1_SETUP: + begin + next_state <= `MODE1_WAIT; + end + `MODE1_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE1; + else + next_state <= `MODE1_WAIT; + + end + `MODE1: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE2_SETUP: + begin + next_state <= `MODE2_WAIT; + end + `MODE2_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE2; + else + next_state <= `MODE2_WAIT; + end + `MODE2: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE3_SETUP: + begin + next_state <= `MODE3_WAIT; + end + `MODE3_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE3; + else + next_state <= `MODE3_WAIT; + end + `MODE3: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `STALL: + next_state <= `STALL_WAIT; + `STALL_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST_SETUP; + else + next_state <= `STALL_WAIT; + `LAST_SETUP: + next_state <= `LAST_SETUP_WAIT; + `LAST_SETUP_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST; + else + next_state <= `LAST_SETUP_WAIT; + `LAST: + next_state <= `LAST_WAIT; + `LAST_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `FINAL_WRITE; + else + next_state <= `LAST_WAIT; + `FINAL_WRITE: + next_state <= `FINAL_WAIT; + `FINAL_WAIT: + if (mem_done == 1'b1) + next_state <= `IDLE; + else + next_state <= `FINAL_WAIT; + `IDLE: + if (start) + next_state <= `SETUP; + else + next_state <= `IDLE; + default: + next_state <= `START; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + cur_state <= `START; + cur_mem_state <= `MEM_IDLE; + end + else + begin + cur_state <= next_state; + cur_mem_state <= next_mem_state; + end +end + +always @ (cur_state) +begin + case (cur_state) + `MODE1: + mode = 2'b01; + `MODE2: + mode = 2'b10; + `MODE3: + mode = 2'b11; + default: + mode = 2'b00; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + comp_N <= input_N; + N <= input_N; + end + else if (next_state == `MODE0) + begin + comp_N <= comp_N - `BLOCKN; + end + + Ndivk <= ((N+`BLOCKM-1)>>6)<<5; + mem_N <= Ndivk<<6; + + if (start) + begin + mem_base <= offset; + mem_top <= offset; + mem_left <= offset; + mem_cur <= offset; + end + else if (cur_state == `MODE0_SETUP) + begin + mem_base <= mem_base + mem_N+`MEMBLOCKN; + mem_top <= mem_base + mem_N+`MEMBLOCKN; + mem_cur <= mem_base + mem_N+`MEMBLOCKN; + mem_left <= mem_base + mem_N+`MEMBLOCKN; + end + else if (cur_state == `MODE1_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + end + else if (cur_state == `MODE3_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + mem_left <= mem_left + `MEMBLOCKM; + end + else if (cur_state == `MODE2_SETUP) + begin + mem_cur <= mem_top + mem_N; + mem_top <= mem_top + mem_N; + mem_left <= mem_base; + end + + if (cur_state == `SETUP) + begin + mem_write <= 24'b0; + mem_write_buf <= 24'b0; + mem_write_size <= `BLOCKMDIVK; + mem_write_size_buf <= `BLOCKMDIVK; + write_n <= block_n; + write_n_buf <= block_n; + end + else if (cur_mem_state == `MEM_CHECK_DONE && mem_read == 0) + begin + mem_write <= mem_write_buf; + mem_write_buf <= mem_cur; + mem_write_size <= mem_write_size_buf; + mem_write_size_buf <= mem_read_size; + write_n <= write_n_buf; + write_n_buf <= block_n; + end + + mem_read_size <= `BLOCKMDIVK; + + if (start) begin + loop <= `BLOCKN; + end else if (next_state == `LAST) begin + loop <= comp_N[8:0] - `BLOCKN; + end + + if (cur_state == `MODE0_SETUP || cur_state == `MODE2_SETUP || start) begin + mcount <= `BLOCKM; + end else if (cur_state == `MODE1_SETUP || cur_state == `MODE3_SETUP) begin + mcount <= mcount+`BLOCKM; + end + + if (cur_state == `MODE0_SETUP || start) begin + ncount <= `BLOCKN; + end else if (cur_state == `MODE2_SETUP) begin + ncount <= ncount+`BLOCKN; + end + + if (mcount < comp_N) begin + block_m <= `BLOCKM; + end else begin + block_m <= comp_N - mcount + `BLOCKM; + end + + if (ncount < comp_N) begin + block_n <= `BLOCKN; + end else begin + block_n <= comp_N - ncount + `BLOCKN; + end + + if (start) begin + cur_mem_sel <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)||(cur_state == `LAST)) begin + cur_mem_sel <= !cur_mem_sel; + end + + if (start) begin + no_left_switch <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `FIRST)) begin + no_left_switch <= 1'b1; + end else if ((cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)) begin + no_left_switch <= 1'b0; + end + + if (start) begin + left_mem_sel <= 1'b0; + end else if (((cur_state == `MODE0)||(cur_state ==`MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP))&&(no_left_switch == 1'b0)) begin + left_mem_sel <= !left_mem_sel; + end +end + +endmodule + + +//topoutputdelay = 1 +//auto-generated LU.v +//datapath for computating LU factorization +//by Wei Zhang + +`define rRAMSIZEWIDTH 7 +`define cSETUP 4'b0000 +`define cSTART 4'b0001 +`define cFETCH_COL 4'b0010 +`define cWAIT_COL 4'b0011 +`define cFIND_REC 4'b0100 +`define cMULT_COL 4'b0101 +`define cUPDATE_J 4'b0110 +`define cSTORE_MO 4'b0111 +`define cMULT_SUB 4'b1000 +`define cINCRE_I 4'b1001 +`define cWAIT 4'b1010 +`define cDONE 4'b1011 +`define cSTORE_DIAG 4'b1100 +`define cSTORE_DIAG2 4'b1101 +`define cSTART_FETCH_ROW 4'b1110 +`define cROW_WAIT 2'b00 +`define cFETCH_ROW 2'b01 +`define cDONE_FETCH_ROW 2'b10 +`define cLOAD_ROW_INC_J 2'b11 + +`define PRECISION 7'b0100000 +`define NUMPE 7'b0100000 +`define PEWIDTH 4'b0101 +`define BLOCKWIDTH 4'b0111 +`define RAMWIDTH 12'b010000000000 +`define RAMNUMBYTES 9'b010000000 +`define RAMSIZEWIDTH 4'b0111 +`define TOPSIZEWIDTH 5'b01100 +`define TOPINPUTDELAY 3'b011 +`define TOPOUTPUTDELAY 2'b01 +`define MEMINPUTDELAY 3'b010 +`define MEMOUTPUTDELAY 2'b01 +`define TOPWIDTH 7'b0100000 + +module LU (clk, start, m, n, loop, mode, done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel +); + + +input clk, start; +input[`BLOCKWIDTH-1:0] m, n, loop; +input[1:0] mode; +output done; +wire[`RAMWIDTH-1:0] curWriteData0, curWriteData1; +wire[`RAMSIZEWIDTH-1:0] curWriteAddr0, curReadAddr0, curWriteAddr1, curReadAddr1; +wire[`RAMWIDTH-1:0] curReadData0, curReadData1; +wire[`RAMNUMBYTES-1:0] curWriteByteEn0, curWriteByteEn1; +wire curWriteEn0, curWriteEn1; + +input[`RAMWIDTH-1:0] curWriteDataMem; +output[`RAMWIDTH-1:0] curReadDataMem; +input[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +input[`RAMNUMBYTES-1:0] curWriteByteEnMem; +input curWriteEnMem; +input[`RAMWIDTH-1:0] leftWriteDataMem; +input[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +input[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +input leftWriteEnMem; +input leftMemSel, curMemSel; + +wire[`RAMWIDTH-1:0] curReadDataLU, curReadDataMem; +wire[`RAMWIDTH-1:0] curWriteDataLU, curWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrLU, curWriteAddrMem, curReadAddrLU, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnLU, curWriteByteEnMem; +wire curWriteEnLU, curWriteEnMem; + +reg[`RAMWIDTH-1:0] curReadData0Reg0; +reg[`RAMWIDTH-1:0] curReadData1Reg0; +reg[`RAMWIDTH-1:0] leftReadData0Reg0; +reg[`RAMWIDTH-1:0] leftReadData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg1; +reg[`RAMWIDTH-1:0] curWriteData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg1; +reg curWriteEn0Reg0; +reg curWriteEn0Reg1; +reg curWriteEn1Reg0; +reg curWriteEn1Reg1; +reg[`RAMWIDTH-1:0] leftWriteData0Reg0; +reg[`RAMWIDTH-1:0] leftWriteData0Reg1; +reg[`RAMWIDTH-1:0] leftWriteData1Reg0; +reg[`RAMWIDTH-1:0] leftWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg1; +reg leftWriteEn0Reg0; +reg leftWriteEn0Reg1; +reg leftWriteEn1Reg0; +reg leftWriteEn1Reg1; + +reg[`PRECISION-1:0] multOperand; +reg[`PRECISION-1:0] diag; +wire[`PRECISION-1:0] recResult; +wire[`PRECISION-1:0] multA0; +wire[`PRECISION-1:0] multA1; +wire[`PRECISION-1:0] multA2; +wire[`PRECISION-1:0] multA3; +wire[`PRECISION-1:0] multA4; +wire[`PRECISION-1:0] multA5; +wire[`PRECISION-1:0] multA6; +wire[`PRECISION-1:0] multA7; +wire[`PRECISION-1:0] multA8; +wire[`PRECISION-1:0] multA9; +wire[`PRECISION-1:0] multA10; +wire[`PRECISION-1:0] multA11; +wire[`PRECISION-1:0] multA12; +wire[`PRECISION-1:0] multA13; +wire[`PRECISION-1:0] multA14; +wire[`PRECISION-1:0] multA15; +wire[`PRECISION-1:0] multA16; +wire[`PRECISION-1:0] multA17; +wire[`PRECISION-1:0] multA18; +wire[`PRECISION-1:0] multA19; +wire[`PRECISION-1:0] multA20; +wire[`PRECISION-1:0] multA21; +wire[`PRECISION-1:0] multA22; +wire[`PRECISION-1:0] multA23; +wire[`PRECISION-1:0] multA24; +wire[`PRECISION-1:0] multA25; +wire[`PRECISION-1:0] multA26; +wire[`PRECISION-1:0] multA27; +wire[`PRECISION-1:0] multA28; +wire[`PRECISION-1:0] multA29; +wire[`PRECISION-1:0] multA30; +wire[`PRECISION-1:0] multA31; +wire[`PRECISION-1:0] multResult0; +wire[`PRECISION-1:0] multResult1; +wire[`PRECISION-1:0] multResult2; +wire[`PRECISION-1:0] multResult3; +wire[`PRECISION-1:0] multResult4; +wire[`PRECISION-1:0] multResult5; +wire[`PRECISION-1:0] multResult6; +wire[`PRECISION-1:0] multResult7; +wire[`PRECISION-1:0] multResult8; +wire[`PRECISION-1:0] multResult9; +wire[`PRECISION-1:0] multResult10; +wire[`PRECISION-1:0] multResult11; +wire[`PRECISION-1:0] multResult12; +wire[`PRECISION-1:0] multResult13; +wire[`PRECISION-1:0] multResult14; +wire[`PRECISION-1:0] multResult15; +wire[`PRECISION-1:0] multResult16; +wire[`PRECISION-1:0] multResult17; +wire[`PRECISION-1:0] multResult18; +wire[`PRECISION-1:0] multResult19; +wire[`PRECISION-1:0] multResult20; +wire[`PRECISION-1:0] multResult21; +wire[`PRECISION-1:0] multResult22; +wire[`PRECISION-1:0] multResult23; +wire[`PRECISION-1:0] multResult24; +wire[`PRECISION-1:0] multResult25; +wire[`PRECISION-1:0] multResult26; +wire[`PRECISION-1:0] multResult27; +wire[`PRECISION-1:0] multResult28; +wire[`PRECISION-1:0] multResult29; +wire[`PRECISION-1:0] multResult30; +wire[`PRECISION-1:0] multResult31; +wire[`PRECISION-1:0] addA0; +wire[`PRECISION-1:0] addA1; +wire[`PRECISION-1:0] addA2; +wire[`PRECISION-1:0] addA3; +wire[`PRECISION-1:0] addA4; +wire[`PRECISION-1:0] addA5; +wire[`PRECISION-1:0] addA6; +wire[`PRECISION-1:0] addA7; +wire[`PRECISION-1:0] addA8; +wire[`PRECISION-1:0] addA9; +wire[`PRECISION-1:0] addA10; +wire[`PRECISION-1:0] addA11; +wire[`PRECISION-1:0] addA12; +wire[`PRECISION-1:0] addA13; +wire[`PRECISION-1:0] addA14; +wire[`PRECISION-1:0] addA15; +wire[`PRECISION-1:0] addA16; +wire[`PRECISION-1:0] addA17; +wire[`PRECISION-1:0] addA18; +wire[`PRECISION-1:0] addA19; +wire[`PRECISION-1:0] addA20; +wire[`PRECISION-1:0] addA21; +wire[`PRECISION-1:0] addA22; +wire[`PRECISION-1:0] addA23; +wire[`PRECISION-1:0] addA24; +wire[`PRECISION-1:0] addA25; +wire[`PRECISION-1:0] addA26; +wire[`PRECISION-1:0] addA27; +wire[`PRECISION-1:0] addA28; +wire[`PRECISION-1:0] addA29; +wire[`PRECISION-1:0] addA30; +wire[`PRECISION-1:0] addA31; +wire[`PRECISION-1:0] addResult0; +wire[`PRECISION-1:0] addResult1; +wire[`PRECISION-1:0] addResult2; +wire[`PRECISION-1:0] addResult3; +wire[`PRECISION-1:0] addResult4; +wire[`PRECISION-1:0] addResult5; +wire[`PRECISION-1:0] addResult6; +wire[`PRECISION-1:0] addResult7; +wire[`PRECISION-1:0] addResult8; +wire[`PRECISION-1:0] addResult9; +wire[`PRECISION-1:0] addResult10; +wire[`PRECISION-1:0] addResult11; +wire[`PRECISION-1:0] addResult12; +wire[`PRECISION-1:0] addResult13; +wire[`PRECISION-1:0] addResult14; +wire[`PRECISION-1:0] addResult15; +wire[`PRECISION-1:0] addResult16; +wire[`PRECISION-1:0] addResult17; +wire[`PRECISION-1:0] addResult18; +wire[`PRECISION-1:0] addResult19; +wire[`PRECISION-1:0] addResult20; +wire[`PRECISION-1:0] addResult21; +wire[`PRECISION-1:0] addResult22; +wire[`PRECISION-1:0] addResult23; +wire[`PRECISION-1:0] addResult24; +wire[`PRECISION-1:0] addResult25; +wire[`PRECISION-1:0] addResult26; +wire[`PRECISION-1:0] addResult27; +wire[`PRECISION-1:0] addResult28; +wire[`PRECISION-1:0] addResult29; +wire[`PRECISION-1:0] addResult30; +wire[`PRECISION-1:0] addResult31; +wire[`RAMWIDTH-1:0] leftReadData0, leftReadData1, leftWriteData0, leftWriteData1; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddr0, leftWriteAddr1, leftReadAddr0, leftReadAddr1; +wire[`RAMNUMBYTES-1:0] leftWriteByteEn0, leftWriteByteEn1; +wire leftWriteEn0, leftWriteEn1; +wire[`RAMWIDTH-1:0] leftReadDataLU, leftWriteDataLU, leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrLU, leftWriteAddrMem, leftReadAddrLU; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnLU, leftWriteByteEnMem; +wire leftWriteEnLU, leftWriteEnMem; + +wire[`PRECISION-1:0] topWriteData; +reg[`PRECISION-1:0] topWriteDataLU; +wire[`PRECISION-1:0] topReadData, topReadDataLU; +wire[`TOPSIZEWIDTH-1:0] topWriteAddr, topWriteAddrLU, topReadAddr, topReadAddrLU; +wire topWriteEn, topWriteEnLU; + +reg[`PRECISION-1:0] topReadDataReg0; +reg[`PRECISION-1:0] topWriteDataReg0; +reg[`PRECISION-1:0] topWriteDataReg1; +reg[`PRECISION-1:0] topWriteDataReg2; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg2; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg2; +reg topWriteEnReg0; +reg topWriteEnReg1; +reg topWriteEnReg2; +wire[`RAMWIDTH-1:0] rcWriteData; +wire leftWriteSel, curWriteSel, topSourceSel; +wire diagEn; +wire[`PEWIDTH-1:0] topWriteSel; + +wire MOSel; +wire MOEn; + +// control block +LUControl conBlock (clk, start, m, n, loop, mode, done, + curReadAddrLU, curWriteAddrLU, curWriteByteEnLU, curWriteEnLU, curWriteSel, + leftReadAddrLU, leftWriteAddrLU, leftWriteByteEnLU, leftWriteEnLU, leftWriteSel, + topReadAddrLU, topWriteAddrLU, topWriteEnLU, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +// fp_div unit +//floating point divider here +fpu_div rec(.clock(clk), .n(32'h3F800000), .d(diag), .div(recResult)); +// on-chip memory blocks that store the matrix to be LU factorized +// store current blocks data +ram currentBlock0 (curWriteByteEn0, clk, curWriteData0, curReadAddr0, curWriteAddr0, curWriteEn0, curReadData0 ); +ram1 currentBlock1 (curWriteByteEn1, clk, curWriteData1, curReadAddr1, curWriteAddr1, curWriteEn1, curReadData1 ); +// store left blocks data +ram2 leftBlock0(leftWriteByteEn0, clk, leftWriteData0, leftReadAddr0, leftWriteAddr0, leftWriteEn0, leftReadData0 ); + +ram3 leftBlock1(leftWriteByteEn1, clk, leftWriteData1, leftReadAddr1, leftWriteAddr1, leftWriteEn1, leftReadData1 ); + +// store top block data +top_ram topBlock(clk, topWriteData, topReadAddr, topWriteAddr, topWriteEn, topReadDataLU ); + +// processing elements that does the main computation of LU factorization +mult_add PE0 (clk, multA0, multOperand, addA0, multResult0, addResult0); +mult_add PE1 (clk, multA1, multOperand, addA1, multResult1, addResult1); +mult_add PE2 (clk, multA2, multOperand, addA2, multResult2, addResult2); +mult_add PE3 (clk, multA3, multOperand, addA3, multResult3, addResult3); +mult_add PE4 (clk, multA4, multOperand, addA4, multResult4, addResult4); +mult_add PE5 (clk, multA5, multOperand, addA5, multResult5, addResult5); +mult_add PE6 (clk, multA6, multOperand, addA6, multResult6, addResult6); +mult_add PE7 (clk, multA7, multOperand, addA7, multResult7, addResult7); +mult_add PE8 (clk, multA8, multOperand, addA8, multResult8, addResult8); +mult_add PE9 (clk, multA9, multOperand, addA9, multResult9, addResult9); +mult_add PE10 (clk, multA10, multOperand, addA10, multResult10, addResult10); +mult_add PE11 (clk, multA11, multOperand, addA11, multResult11, addResult11); +mult_add PE12 (clk, multA12, multOperand, addA12, multResult12, addResult12); +mult_add PE13 (clk, multA13, multOperand, addA13, multResult13, addResult13); +mult_add PE14 (clk, multA14, multOperand, addA14, multResult14, addResult14); +mult_add PE15 (clk, multA15, multOperand, addA15, multResult15, addResult15); +mult_add PE16 (clk, multA16, multOperand, addA16, multResult16, addResult16); +mult_add PE17 (clk, multA17, multOperand, addA17, multResult17, addResult17); +mult_add PE18 (clk, multA18, multOperand, addA18, multResult18, addResult18); +mult_add PE19 (clk, multA19, multOperand, addA19, multResult19, addResult19); +mult_add PE20 (clk, multA20, multOperand, addA20, multResult20, addResult20); +mult_add PE21 (clk, multA21, multOperand, addA21, multResult21, addResult21); +mult_add PE22 (clk, multA22, multOperand, addA22, multResult22, addResult22); +mult_add PE23 (clk, multA23, multOperand, addA23, multResult23, addResult23); +mult_add PE24 (clk, multA24, multOperand, addA24, multResult24, addResult24); +mult_add PE25 (clk, multA25, multOperand, addA25, multResult25, addResult25); +mult_add PE26 (clk, multA26, multOperand, addA26, multResult26, addResult26); +mult_add PE27 (clk, multA27, multOperand, addA27, multResult27, addResult27); +mult_add PE28 (clk, multA28, multOperand, addA28, multResult28, addResult28); +mult_add PE29 (clk, multA29, multOperand, addA29, multResult29, addResult29); +mult_add PE30 (clk, multA30, multOperand, addA30, multResult30, addResult30); +mult_add PE31 (clk, multA31, multOperand, addA31, multResult31, addResult31); + +// connect to ports of the left blocks +assign leftWriteDataLU = (leftWriteSel == 1'b0) ? curReadDataLU : rcWriteData; +always @ (posedge clk) +begin + if(leftMemSel == 1'b0) + begin + leftWriteData0Reg0 <= leftWriteDataMem; + leftWriteAddr0Reg0 <= leftWriteAddrMem; + leftWriteByteEn0Reg0 <= leftWriteByteEnMem; + leftWriteEn0Reg0 <= leftWriteEnMem; + leftWriteData1Reg0 <= leftWriteDataLU; + leftWriteAddr1Reg0 <= leftWriteAddrLU; + leftWriteByteEn1Reg0 <= leftWriteByteEnLU; + leftWriteEn1Reg0 <= leftWriteEnLU; + end + else + begin + leftWriteData0Reg0 <= leftWriteDataLU; + leftWriteAddr0Reg0 <= leftWriteAddrLU; + leftWriteByteEn0Reg0 <= leftWriteByteEnLU; + leftWriteEn0Reg0 <= leftWriteEnLU; + leftWriteData1Reg0 <= leftWriteDataMem; + leftWriteAddr1Reg0 <= leftWriteAddrMem; + leftWriteByteEn1Reg0 <= leftWriteByteEnMem; + leftWriteEn1Reg0 <= leftWriteEnMem; + end + leftReadAddr0Reg0 <= leftReadAddrLU; + leftReadAddr1Reg0 <= leftReadAddrLU; + leftWriteData0Reg1 <= leftWriteData0Reg0; + leftWriteAddr0Reg1 <= leftWriteAddr0Reg0; + leftReadAddr0Reg1 <= leftReadAddr0Reg0; + leftWriteByteEn0Reg1 <= leftWriteByteEn0Reg0; + leftWriteEn0Reg1 <= leftWriteEn0Reg0; + leftWriteData1Reg1 <= leftWriteData1Reg0; + leftWriteAddr1Reg1 <= leftWriteAddr1Reg0; + leftReadAddr1Reg1 <= leftReadAddr1Reg0; + leftWriteByteEn1Reg1 <= leftWriteByteEn1Reg0; + leftWriteEn1Reg1 <= leftWriteEn1Reg0; +end +assign leftWriteData0 = leftWriteData0Reg1; +assign leftWriteAddr0 = leftWriteAddr0Reg1; +assign leftReadAddr0 = leftReadAddr0Reg1; +assign leftWriteByteEn0 = leftWriteByteEn0Reg1; +assign leftWriteEn0 = leftWriteEn0Reg1; +assign leftWriteData1 = leftWriteData1Reg1; +assign leftWriteAddr1 = leftWriteAddr1Reg1; +assign leftReadAddr1 = leftReadAddr1Reg1; +assign leftWriteByteEn1 = leftWriteByteEn1Reg1; +assign leftWriteEn1 = leftWriteEn1Reg1; + +always @ (posedge clk) +begin + leftReadData0Reg0 <= leftReadData0; + leftReadData1Reg0 <= leftReadData1; +end +assign leftReadDataLU = (leftMemSel == 1'b0) ? leftReadData1Reg0 : leftReadData0Reg0; +// data feed to fp div unit +always @ (posedge clk) +begin + if (diagEn == 1'b1) + begin + diag <= topReadData; + end +end +// one of the inputs to the PE +always @ (posedge clk) +begin + if (start == 1'b1) + multOperand <= 0; + else if (MOEn == 1'b1) + begin + if (MOSel == 1'b0) + multOperand <= recResult; + else + multOperand <= topReadData; + end +end + +// connections to top block memory ports +always @ (topSourceSel or topWriteSel or curReadDataLU or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +begin + if (topSourceSel == 1'b0) + case (topWriteSel) + 0: + topWriteDataLU = curReadDataLU[1023:992]; + 1: + topWriteDataLU = curReadDataLU[991:960]; + 2: + topWriteDataLU = curReadDataLU[959:928]; + 3: + topWriteDataLU = curReadDataLU[927:896]; + 4: + topWriteDataLU = curReadDataLU[895:864]; + 5: + topWriteDataLU = curReadDataLU[863:832]; + 6: + topWriteDataLU = curReadDataLU[831:800]; + 7: + topWriteDataLU = curReadDataLU[799:768]; + 8: + topWriteDataLU = curReadDataLU[767:736]; + 9: + topWriteDataLU = curReadDataLU[735:704]; + 10: + topWriteDataLU = curReadDataLU[703:672]; + 11: + topWriteDataLU = curReadDataLU[671:640]; + 12: + topWriteDataLU = curReadDataLU[639:608]; + 13: + topWriteDataLU = curReadDataLU[607:576]; + 14: + topWriteDataLU = curReadDataLU[575:544]; + 15: + topWriteDataLU = curReadDataLU[543:512]; + 16: + topWriteDataLU = curReadDataLU[511:480]; + 17: + topWriteDataLU = curReadDataLU[479:448]; + 18: + topWriteDataLU = curReadDataLU[447:416]; + 19: + topWriteDataLU = curReadDataLU[415:384]; + 20: + topWriteDataLU = curReadDataLU[383:352]; + 21: + topWriteDataLU = curReadDataLU[351:320]; + 22: + topWriteDataLU = curReadDataLU[319:288]; + 23: + topWriteDataLU = curReadDataLU[287:256]; + 24: + topWriteDataLU = curReadDataLU[255:224]; + 25: + topWriteDataLU = curReadDataLU[223:192]; + 26: + topWriteDataLU = curReadDataLU[191:160]; + 27: + topWriteDataLU = curReadDataLU[159:128]; + 28: + topWriteDataLU = curReadDataLU[127:96]; + 29: + topWriteDataLU = curReadDataLU[95:64]; + 30: + topWriteDataLU = curReadDataLU[63:32]; + 31: + topWriteDataLU = curReadDataLU[31:0]; + default: + topWriteDataLU = curReadDataLU[`PRECISION-1:0]; + endcase + else + case (topWriteSel) + 0: + topWriteDataLU = addResult31; + 1: + topWriteDataLU = addResult30; + 2: + topWriteDataLU = addResult29; + 3: + topWriteDataLU = addResult28; + 4: + topWriteDataLU = addResult27; + 5: + topWriteDataLU = addResult26; + 6: + topWriteDataLU = addResult25; + 7: + topWriteDataLU = addResult24; + 8: + topWriteDataLU = addResult23; + 9: + topWriteDataLU = addResult22; + 10: + topWriteDataLU = addResult21; + 11: + topWriteDataLU = addResult20; + 12: + topWriteDataLU = addResult19; + 13: + topWriteDataLU = addResult18; + 14: + topWriteDataLU = addResult17; + 15: + topWriteDataLU = addResult16; + 16: + topWriteDataLU = addResult15; + 17: + topWriteDataLU = addResult14; + 18: + topWriteDataLU = addResult13; + 19: + topWriteDataLU = addResult12; + 20: + topWriteDataLU = addResult11; + 21: + topWriteDataLU = addResult10; + 22: + topWriteDataLU = addResult9; + 23: + topWriteDataLU = addResult8; + 24: + topWriteDataLU = addResult7; + 25: + topWriteDataLU = addResult6; + 26: + topWriteDataLU = addResult5; + 27: + topWriteDataLU = addResult4; + 28: + topWriteDataLU = addResult3; + 29: + topWriteDataLU = addResult2; + 30: + topWriteDataLU = addResult1; + 31: + topWriteDataLU = addResult0; + default: + topWriteDataLU = addResult0; + endcase +end + +always @ (posedge clk) +begin + topWriteDataReg0 <= topWriteDataLU; + topReadAddrReg0 <= topReadAddrLU; + topWriteAddrReg0 <= topWriteAddrLU; + topWriteEnReg0 <= topWriteEnLU; + topWriteDataReg1 <= topWriteDataReg0; + topReadAddrReg1 <= topReadAddrReg0; + topWriteAddrReg1 <= topWriteAddrReg0; + topWriteEnReg1 <= topWriteEnReg0; + topWriteDataReg2 <= topWriteDataReg1; + topReadAddrReg2 <= topReadAddrReg1; + topWriteAddrReg2 <= topWriteAddrReg1; + topWriteEnReg2 <= topWriteEnReg1; +end +assign topWriteData = topWriteDataReg2; +assign topReadAddr = topReadAddrReg2; +assign topWriteAddr = topWriteAddrReg2; +assign topWriteEn = topWriteEnReg2; +always @ (posedge clk) +begin + topReadDataReg0 <= topReadDataLU; +end +assign topReadData = topReadDataReg0; + +// connections to processing element +assign multA0 = leftReadDataLU[31:0]; +assign multA1 = leftReadDataLU[63:32]; +assign multA2 = leftReadDataLU[95:64]; +assign multA3 = leftReadDataLU[127:96]; +assign multA4 = leftReadDataLU[159:128]; +assign multA5 = leftReadDataLU[191:160]; +assign multA6 = leftReadDataLU[223:192]; +assign multA7 = leftReadDataLU[255:224]; +assign multA8 = leftReadDataLU[287:256]; +assign multA9 = leftReadDataLU[319:288]; +assign multA10 = leftReadDataLU[351:320]; +assign multA11 = leftReadDataLU[383:352]; +assign multA12 = leftReadDataLU[415:384]; +assign multA13 = leftReadDataLU[447:416]; +assign multA14 = leftReadDataLU[479:448]; +assign multA15 = leftReadDataLU[511:480]; +assign multA16 = leftReadDataLU[543:512]; +assign multA17 = leftReadDataLU[575:544]; +assign multA18 = leftReadDataLU[607:576]; +assign multA19 = leftReadDataLU[639:608]; +assign multA20 = leftReadDataLU[671:640]; +assign multA21 = leftReadDataLU[703:672]; +assign multA22 = leftReadDataLU[735:704]; +assign multA23 = leftReadDataLU[767:736]; +assign multA24 = leftReadDataLU[799:768]; +assign multA25 = leftReadDataLU[831:800]; +assign multA26 = leftReadDataLU[863:832]; +assign multA27 = leftReadDataLU[895:864]; +assign multA28 = leftReadDataLU[927:896]; +assign multA29 = leftReadDataLU[959:928]; +assign multA30 = leftReadDataLU[991:960]; +assign multA31 = leftReadDataLU[1023:992]; + +assign addA0 = curReadDataLU[31:0]; +assign addA1 = curReadDataLU[63:32]; +assign addA2 = curReadDataLU[95:64]; +assign addA3 = curReadDataLU[127:96]; +assign addA4 = curReadDataLU[159:128]; +assign addA5 = curReadDataLU[191:160]; +assign addA6 = curReadDataLU[223:192]; +assign addA7 = curReadDataLU[255:224]; +assign addA8 = curReadDataLU[287:256]; +assign addA9 = curReadDataLU[319:288]; +assign addA10 = curReadDataLU[351:320]; +assign addA11 = curReadDataLU[383:352]; +assign addA12 = curReadDataLU[415:384]; +assign addA13 = curReadDataLU[447:416]; +assign addA14 = curReadDataLU[479:448]; +assign addA15 = curReadDataLU[511:480]; +assign addA16 = curReadDataLU[543:512]; +assign addA17 = curReadDataLU[575:544]; +assign addA18 = curReadDataLU[607:576]; +assign addA19 = curReadDataLU[639:608]; +assign addA20 = curReadDataLU[671:640]; +assign addA21 = curReadDataLU[703:672]; +assign addA22 = curReadDataLU[735:704]; +assign addA23 = curReadDataLU[767:736]; +assign addA24 = curReadDataLU[799:768]; +assign addA25 = curReadDataLU[831:800]; +assign addA26 = curReadDataLU[863:832]; +assign addA27 = curReadDataLU[895:864]; +assign addA28 = curReadDataLU[927:896]; +assign addA29 = curReadDataLU[959:928]; +assign addA30 = curReadDataLU[991:960]; +assign addA31 = curReadDataLU[1023:992]; + +// connections to ports of the current blocks +assign rcWriteData[31:0] = (curWriteSel == 0) ? multResult0 : addResult0; +assign rcWriteData[63:32] = (curWriteSel == 0) ? multResult1 : addResult1; +assign rcWriteData[95:64] = (curWriteSel == 0) ? multResult2 : addResult2; +assign rcWriteData[127:96] = (curWriteSel == 0) ? multResult3 : addResult3; +assign rcWriteData[159:128] = (curWriteSel == 0) ? multResult4 : addResult4; +assign rcWriteData[191:160] = (curWriteSel == 0) ? multResult5 : addResult5; +assign rcWriteData[223:192] = (curWriteSel == 0) ? multResult6 : addResult6; +assign rcWriteData[255:224] = (curWriteSel == 0) ? multResult7 : addResult7; +assign rcWriteData[287:256] = (curWriteSel == 0) ? multResult8 : addResult8; +assign rcWriteData[319:288] = (curWriteSel == 0) ? multResult9 : addResult9; +assign rcWriteData[351:320] = (curWriteSel == 0) ? multResult10 : addResult10; +assign rcWriteData[383:352] = (curWriteSel == 0) ? multResult11 : addResult11; +assign rcWriteData[415:384] = (curWriteSel == 0) ? multResult12 : addResult12; +assign rcWriteData[447:416] = (curWriteSel == 0) ? multResult13 : addResult13; +assign rcWriteData[479:448] = (curWriteSel == 0) ? multResult14 : addResult14; +assign rcWriteData[511:480] = (curWriteSel == 0) ? multResult15 : addResult15; +assign rcWriteData[543:512] = (curWriteSel == 0) ? multResult16 : addResult16; +assign rcWriteData[575:544] = (curWriteSel == 0) ? multResult17 : addResult17; +assign rcWriteData[607:576] = (curWriteSel == 0) ? multResult18 : addResult18; +assign rcWriteData[639:608] = (curWriteSel == 0) ? multResult19 : addResult19; +assign rcWriteData[671:640] = (curWriteSel == 0) ? multResult20 : addResult20; +assign rcWriteData[703:672] = (curWriteSel == 0) ? multResult21 : addResult21; +assign rcWriteData[735:704] = (curWriteSel == 0) ? multResult22 : addResult22; +assign rcWriteData[767:736] = (curWriteSel == 0) ? multResult23 : addResult23; +assign rcWriteData[799:768] = (curWriteSel == 0) ? multResult24 : addResult24; +assign rcWriteData[831:800] = (curWriteSel == 0) ? multResult25 : addResult25; +assign rcWriteData[863:832] = (curWriteSel == 0) ? multResult26 : addResult26; +assign rcWriteData[895:864] = (curWriteSel == 0) ? multResult27 : addResult27; +assign rcWriteData[927:896] = (curWriteSel == 0) ? multResult28 : addResult28; +assign rcWriteData[959:928] = (curWriteSel == 0) ? multResult29 : addResult29; +assign rcWriteData[991:960] = (curWriteSel == 0) ? multResult30 : addResult30; +assign rcWriteData[1023:992] = (curWriteSel == 0) ? multResult31 : addResult31; +assign curWriteDataLU = rcWriteData; + +always @ (posedge clk) +begin + if(curMemSel == 1'b0) + begin + curWriteData0Reg0 <= curWriteDataMem; + curWriteAddr0Reg0 <= curWriteAddrMem; + curReadAddr0Reg0 <= curReadAddrMem; + curWriteByteEn0Reg0 <= curWriteByteEnMem; + curWriteEn0Reg0 <= curWriteEnMem; + curWriteData1Reg0 <= curWriteDataLU; + curWriteAddr1Reg0 <= curWriteAddrLU; + curReadAddr1Reg0 <= curReadAddrLU; + curWriteByteEn1Reg0 <= curWriteByteEnLU; + curWriteEn1Reg0 <= curWriteEnLU; + end + else + begin + curWriteData0Reg0 <= curWriteDataLU; + curWriteAddr0Reg0 <= curWriteAddrLU; + curReadAddr0Reg0 <= curReadAddrLU; + curWriteByteEn0Reg0 <= curWriteByteEnLU; + curWriteEn0Reg0 <= curWriteEnLU; + curWriteData1Reg0 <= curWriteDataMem; + curWriteAddr1Reg0 <= curWriteAddrMem; + curReadAddr1Reg0 <= curReadAddrMem; + curWriteByteEn1Reg0 <= curWriteByteEnMem; + curWriteEn1Reg0 <= curWriteEnMem; + end + curWriteData0Reg1 <= curWriteData0Reg0; + curWriteAddr0Reg1 <= curWriteAddr0Reg0; + curReadAddr0Reg1 <= curReadAddr0Reg0; + curWriteByteEn0Reg1 <= curWriteByteEn0Reg0; + curWriteEn0Reg1 <= curWriteEn0Reg0; + curWriteData1Reg1 <= curWriteData1Reg0; + curWriteAddr1Reg1 <= curWriteAddr1Reg0; + curReadAddr1Reg1 <= curReadAddr1Reg0; + curWriteByteEn1Reg1 <= curWriteByteEn1Reg0; + curWriteEn1Reg1 <= curWriteEn1Reg0; +end +assign curWriteData0 = curWriteData0Reg1; +assign curWriteAddr0 = curWriteAddr0Reg1; +assign curReadAddr0 = curReadAddr0Reg1; +assign curWriteByteEn0 = curWriteByteEn0Reg1; +assign curWriteEn0 = curWriteEn0Reg1; +assign curWriteData1 = curWriteData1Reg1; +assign curWriteAddr1 = curWriteAddr1Reg1; +assign curReadAddr1 = curReadAddr1Reg1; +assign curWriteByteEn1 = curWriteByteEn1Reg1; +assign curWriteEn1 = curWriteEn1Reg1; + +always @ (posedge clk) +begin + curReadData0Reg0 <= curReadData0; + curReadData1Reg0 <= curReadData1; +end +assign curReadDataMem = (curMemSel == 0) ? curReadData0Reg0 : curReadData1Reg0; +assign curReadDataLU = (curMemSel == 0) ? curReadData1Reg0 : curReadData0Reg0; +endmodule + +module LUControl (clk, start_in, m_in, n_in, loop_in, mode_in, done, + curReadAddr, curWriteAddr, curWriteByteEn, curWriteEn, curWriteSel, + leftReadAddr, leftWriteAddr, leftWriteByteEn, leftWriteEn, leftWriteSel, + topReadAddr, topWriteAddr, topWriteEn, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +input clk, start_in; +input[7-1:0] m_in, n_in, loop_in; +input[1:0] mode_in; +output done; + +output[128-1:0] curWriteByteEn; +output[7-1:0] curWriteAddr, curReadAddr; +output curWriteEn; + +output[128-1:0] leftWriteByteEn; +output[7-1:0] leftWriteAddr, leftReadAddr; +output leftWriteEn; + +output[12-1:0] topWriteAddr, topReadAddr; +output topWriteEn; + +output leftWriteSel, curWriteSel, topSourceSel, diagEn; +output[5-1:0] topWriteSel; + +output MOSel; +output MOEn; + +reg start; +reg[15:0]startDelay; +reg[7-1:0] m, n, stop, stop2, loop; +reg[1:0] mode; +reg[3:0] nextState, currentState; +reg[1:0] nextRowState, currentRowState; +reg startFetchRow, doneFetchRow, loadRow, writeRow; +reg updateCounter; + +reg[7-1:0] i1, j; +reg[12-1:0] nextTopIdx, nextTopIdx2, curTopIdx, nextTopIdxCounter; +reg[2-1:0] topIdx, topIdxCounter, mdivk; +reg[7-1:0] diagIdx, leftIdx, msIdx; +reg[5-1:0] imodk, i1modk; +reg[7-1:0] diagIdxCounter, leftIdxCounter, msIdxCounter, readRowCounter, topWriteCounter; +reg[128-1:0] byteEn, i1modkByteEn; + +reg done; + +reg[128-1:0] curWriteByteEn; +reg[7-1:0] curWriteAddr, curReadAddr; +reg curWriteEn; + +reg[128-1:0] leftWriteByteEn; +reg[7-1:0] leftWriteAddr, leftReadAddr; +reg leftWriteEn; + +reg[12-1:0] topWriteAddr, topReadAddr; +reg topWriteEn; + +reg leftWriteSel, curWriteSel, topSourceSel, diagEn; +reg[5-1:0] topWriteSel; + +reg MOSel; +reg MOEn; + +reg[7-1:0] counter; +reg[6-1:0] divCounter; + +reg[128-1:0]writeByteEnDelay0; +reg[128-1:0]writeByteEnDelay1; +reg[128-1:0]writeByteEnDelay2; +reg[128-1:0]writeByteEnDelay3; +reg[128-1:0]writeByteEnDelay4; +reg[128-1:0]writeByteEnDelay5; +reg[128-1:0]writeByteEnDelay6; +reg[128-1:0]writeByteEnDelay7; +reg[128-1:0]writeByteEnDelay8; +reg[128-1:0]writeByteEnDelay9; +reg[128-1:0]writeByteEnDelay10; +reg[128-1:0]writeByteEnDelay11; +reg[128-1:0]writeByteEnDelay12; +reg[128-1:0]writeByteEnDelay13; +reg[128-1:0]writeByteEnDelay14; +reg[128-1:0]writeByteEnDelay15; +reg[128-1:0]writeByteEnDelay16; +reg[128-1:0]writeByteEnDelay17; +reg[128-1:0]writeByteEnDelay18; +reg[128-1:0]writeByteEnDelay19; +reg[128-1:0]writeByteEnDelay20; +reg[128-1:0]writeByteEnDelay21; +reg[128-1:0]writeByteEnDelay22; +reg[128-1:0]writeByteEnDelay23; +reg[128-1:0]writeByteEnDelay24; +reg[128-1:0]writeByteEnDelay25; +reg[128-1:0]writeByteEnDelay26; +reg[128-1:0]writeByteEnDelay27; +reg[128-1:0]writeByteEnDelay28; +reg[128-1:0]writeByteEnDelay29; +reg[128-1:0]writeByteEnDelay30; +reg[128-1:0]writeByteEnDelay31; + +reg[7-1:0]curWriteAddrDelay0; +reg[7-1:0]curWriteAddrDelay1; +reg[7-1:0]curWriteAddrDelay2; +reg[7-1:0]curWriteAddrDelay3; +reg[7-1:0]curWriteAddrDelay4; +reg[7-1:0]curWriteAddrDelay5; +reg[7-1:0]curWriteAddrDelay6; +reg[7-1:0]curWriteAddrDelay7; +reg[7-1:0]curWriteAddrDelay8; +reg[7-1:0]curWriteAddrDelay9; +reg[7-1:0]curWriteAddrDelay10; +reg[7-1:0]curWriteAddrDelay11; +reg[7-1:0]curWriteAddrDelay12; +reg[7-1:0]curWriteAddrDelay13; +reg[7-1:0]curWriteAddrDelay14; +reg[7-1:0]curWriteAddrDelay15; +reg[7-1:0]curWriteAddrDelay16; +reg[7-1:0]curWriteAddrDelay17; +reg[7-1:0]curWriteAddrDelay18; +reg[7-1:0]curWriteAddrDelay19; +reg[7-1:0]curWriteAddrDelay20; +reg[7-1:0]curWriteAddrDelay21; +reg[7-1:0]curWriteAddrDelay22; +reg[7-1:0]curWriteAddrDelay23; +reg[7-1:0]curWriteAddrDelay24; +reg[7-1:0]curWriteAddrDelay25; +reg[7-1:0]curWriteAddrDelay26; +reg[7-1:0]curWriteAddrDelay27; +reg[7-1:0]curWriteAddrDelay28; +reg[7-1:0]curWriteAddrDelay29; +reg[7-1:0]curWriteAddrDelay30; +reg[7-1:0]curWriteAddrDelay31; + +reg[7-1:0]curReadAddrDelay0; +reg[7-1:0]curReadAddrDelay1; +reg[7-1:0]curReadAddrDelay2; +reg[7-1:0]curReadAddrDelay3; +reg[7-1:0]curReadAddrDelay4; +reg[7-1:0]curReadAddrDelay5; +reg[7-1:0]curReadAddrDelay6; +reg[7-1:0]curReadAddrDelay7; +reg[7-1:0]curReadAddrDelay8; +reg[7-1:0]curReadAddrDelay9; +reg[7-1:0]curReadAddrDelay10; +reg[7-1:0]curReadAddrDelay11; + +reg[32-1:0]leftWriteEnDelay; +reg[32-1:0]curWriteEnDelay; +reg[5-1:0]leftWriteSelDelay; +reg[16-1:0]curWriteSelDelay; +reg[7-1:0]leftReadAddrDelay0; +reg[12-1:0]topWriteAddrDelay0; +reg[12-1:0]topWriteAddrDelay1; +reg[12-1:0]topWriteAddrDelay2; +reg[12-1:0]topWriteAddrDelay3; +reg[12-1:0]topWriteAddrDelay4; +reg[12-1:0]topWriteAddrDelay5; +reg[12-1:0]topWriteAddrDelay6; +reg[12-1:0]topWriteAddrDelay7; +reg[12-1:0]topWriteAddrDelay8; +reg[12-1:0]topWriteAddrDelay9; +reg[12-1:0]topWriteAddrDelay10; +reg[12-1:0]topWriteAddrDelay11; +reg[12-1:0]topWriteAddrDelay12; +reg[12-1:0]topWriteAddrDelay13; +reg[12-1:0]topWriteAddrDelay14; +reg[12-1:0]topWriteAddrDelay15; +reg[12-1:0]topWriteAddrDelay16; +reg[12-1:0]topWriteAddrDelay17; +reg[12-1:0]topWriteAddrDelay18; +reg[12-1:0]topWriteAddrDelay19; +reg[12-1:0]topWriteAddrDelay20; +reg[12-1:0]topWriteAddrDelay21; +reg[12-1:0]topWriteAddrDelay22; +reg[12-1:0]topWriteAddrDelay23; +reg[12-1:0]topWriteAddrDelay24; +reg[12-1:0]topWriteAddrDelay25; +reg[12-1:0]topWriteAddrDelay26; +reg[12-1:0]topWriteAddrDelay27; +reg[12-1:0]topWriteAddrDelay28; +reg[12-1:0]topWriteAddrDelay29; +reg[12-1:0]topWriteAddrDelay30; +reg[12-1:0]topWriteAddrDelay31; + +reg [32-1:0]topWriteEnDelay; +reg [5-1:0]topSourceSelDelay; +reg[5-1:0]topWriteSelDelay0; +reg[5-1:0]topWriteSelDelay1; +reg[5-1:0]topWriteSelDelay2; +reg[5-1:0]topWriteSelDelay3; +reg[5-1:0]topWriteSelDelay4; +reg[5-1:0]topWriteSelDelay5; +reg[5-1:0]topWriteSelDelay6; +reg[5-1:0]topWriteSelDelay7; +reg[5-1:0]topWriteSelDelay8; +reg[5-1:0]topWriteSelDelay9; +reg[5-1:0]topWriteSelDelay10; +reg[5-1:0]topWriteSelDelay11; +reg[5-1:0]topWriteSelDelay12; +reg[5-1:0]topWriteSelDelay13; +reg[5-1:0]topWriteSelDelay14; +reg[5-1:0]topWriteSelDelay15; +reg[5-1:0]topWriteSelDelay16; +reg[5-1:0]topWriteSelDelay17; +reg[5-1:0]topWriteSelDelay18; +reg[5-1:0]topWriteSelDelay19; +reg[5-1:0]topWriteSelDelay20; +reg[5-1:0]topWriteSelDelay21; +reg[5-1:0]topWriteSelDelay22; +reg[5-1:0]topWriteSelDelay23; +reg[5-1:0]topWriteSelDelay24; +reg[5-1:0]topWriteSelDelay25; +reg[5-1:0]topWriteSelDelay26; +reg[5-1:0]topWriteSelDelay27; +reg[5-1:0]topWriteSelDelay28; +reg[5-1:0]topWriteSelDelay29; +reg[5-1:0]topWriteSelDelay30; +reg[5-1:0]topWriteSelDelay31; + +reg [6-1:0]diagEnDelay; +reg[6-1:0]MOEnDelay; +reg [7-1:0]waitCycles; + +// register store m, n and mdivk value +always @ (posedge clk) +begin + if (start_in == 1'b1) + begin + n <= n_in; + m <= m_in; + loop <= loop_in; + mode <= mode_in; + end + if (mode[0] == 1'b0 && m == loop) + stop <= loop; + else + stop <= loop+1'b1; + stop2 <= loop; + startDelay[0] <= start_in; + startDelay[1] <= startDelay[0]; + startDelay[2] <= startDelay[1]; + startDelay[3] <= startDelay[2]; + startDelay[4] <= startDelay[3]; + startDelay[5] <= startDelay[4]; + startDelay[6] <= startDelay[5]; + startDelay[7] <= startDelay[6]; + startDelay[8] <= startDelay[7]; + startDelay[9] <= startDelay[8]; + startDelay[10] <= startDelay[9]; + startDelay[11] <= startDelay[10]; + startDelay[12] <= startDelay[11]; + startDelay[13] <= startDelay[12]; + startDelay[14] <= startDelay[13]; + startDelay[15] <= startDelay[14]; + start <= startDelay[15]; + mdivk <= (m+32-1)>>5; +end + +// registers that store values that are used in FSM, dependent on i and/or j +always @ (posedge clk) +begin + if (start == 1'b1) + topIdx <= 2'b00; //offset1divk; + else if (currentState == `cINCRE_I && i1modk == 32-1 && mode[0] == 1'b0) + topIdx <= topIdx + 1'b1; + + if (start == 1'b1) + diagIdx <= 7'b0000000; + else if (currentState == `cSTORE_DIAG && mode == 2'b01) + diagIdx <= 2; else if (currentState == `cINCRE_I) + begin + if ((imodk == 32-1 && mode == 2'b00) || (i1modk == 32-1 && mode == 2'b01)) + diagIdx <= diagIdx + 2 + 1; + else + diagIdx <= diagIdx + 2; + end + + if (start == 1'b1) + leftIdx <= 7'b0000000; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 32-1 && mode[0] == 1'b0) + leftIdx <= leftIdx + 2 + 1; + else + leftIdx <= leftIdx + 2; + end + + if (start == 1'b1) + msIdx <= 7'b0000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + msIdx <= leftIdx + 2; + else + msIdx <= topIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + msIdx <= msIdx + 2; + + if (start == 1'b1) + imodk <= 5'b00000; + else if (currentState == `cINCRE_I) + begin + if (imodk == 32-1) + imodk <= 5'b00000; + else + imodk <= imodk + 1'b1; + end + + if (start == 1'b1) + i1modk <= 5'b00001; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 32-1) + i1modk <= 5'b00000; + else + i1modk <= i1modk + 1'b1; + end + + if (start == 1'b1) + nextTopIdx <= 12'b000000000000; + else if (currentState == `cINCRE_I) + if (mode[1] == 0) + nextTopIdx <= nextTopIdx + n + 1; + else + nextTopIdx <= nextTopIdx + n; + nextTopIdx2 <= nextTopIdx + n + 1; + + if (start == 1'b1) + curTopIdx <= 12'b000000000001; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + curTopIdx <= nextTopIdx+1; + else + curTopIdx <= nextTopIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + curTopIdx <= curTopIdx + 1; + + if (start == 1'b1) + i1 <= 7'b0000001; + else if (currentState == `cINCRE_I) + i1 <= i1 + 1; + + if (start == 1'b1) + j <= 7'b0000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + j <= i1; + else + j <= 7'b0000000; + else if (currentRowState == `cLOAD_ROW_INC_J) + j <= j + 1; + +// compute cycles of delay in FSM + if (currentState == `cSTORE_MO) + waitCycles <= 32-1; + else if (currentState == `cINCRE_I) + begin + if (i1 == stop-1) + if (mode[1] == 1'b1) + waitCycles <= 32-1 + 6 - 3; + else + waitCycles <= waitCycles + 5 - 2; + else if (mode == 2'b01 && waitCycles < 32-1 - (16-1) - 4) + waitCycles <= 32-1 - (16-1) - 4; + else if (mode == 2'b10 && i1modk == 32-1) + waitCycles <= 32-1 + 6 - 3; + else if (mode == 2'b00) + waitCycles <= waitCycles + 6 ; + end +else if (waitCycles >7'b0000000) + waitCycles <= waitCycles - 1; + +end + +// determining next state of main FSM +always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +begin + case (currentState) + `cSETUP: + begin + if (start == 1'b1) + nextState = `cSTART; + else + nextState = `cSETUP; + updateCounter = 1'b1; + end + `cSTART: + begin + if (mode == 2'b00) + begin + if (m == 1 && n == 1) + nextState = `cDONE; + else + nextState = `cFETCH_COL; + end + else if (mode == 2'b01) + nextState = `cSTORE_DIAG; + else if (mode == 2'b10) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cUPDATE_J; + updateCounter = 1'b1; + end + `cSTART_FETCH_ROW: + begin + if (counter == 5+6-1) + begin + if (mode == 2'b00) + nextState = `cSTORE_DIAG; + else + nextState = `cUPDATE_J; + end + else + nextState = `cSTART_FETCH_ROW; + updateCounter = 1'b0; + end + `cFETCH_COL: + if (counter >= mdivk-1) + begin + if (mode == 2'b00 && counter < 5) + begin + nextState = `cWAIT_COL; + updateCounter = 1'b0; + end + else + begin + if (mode == 2'b00) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1'b1; + end + end + else + begin + nextState = `cFETCH_COL; + updateCounter = 1'b0; + end + `cWAIT_COL: + if (counter >= 5) + begin + if (mode == 0) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1; + end + else + begin + nextState = `cWAIT_COL; + updateCounter = 0; + end + `cSTORE_DIAG: + begin + if (mode == 0) + nextState = `cFIND_REC; + else + nextState = `cFETCH_COL; + updateCounter = 1; + end + `cFIND_REC: + if (divCounter == 56) + begin + if (mode == 0) + nextState = `cMULT_COL; + else + nextState = `cSTORE_DIAG2; + updateCounter = 1; + end + else + begin + nextState = `cFIND_REC; + updateCounter = 0; + end + `cSTORE_DIAG2: + begin + nextState = `cMULT_COL; + updateCounter = 1; + end + `cMULT_COL: + if (topIdxCounter == mdivk-1) + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + else + begin + nextState = `cMULT_COL; + updateCounter = 0; + end + `cUPDATE_J: + if ((mode[1] == 1 || counter >= 16-1) && doneFetchRow == 1) + begin + nextState = `cSTORE_MO; + updateCounter = 1; + end + else + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + `cSTORE_MO: + begin + if (j == stop2) + begin + if (counter == mdivk-1+5-2) + nextState = `cDONE; + else + nextState = `cSTORE_MO; + updateCounter = 0; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 1; + end + end + `cMULT_SUB: + if (topIdxCounter == mdivk-1) + begin + if (j == n-1) + nextState = `cINCRE_I; + else + nextState = `cMULT_SUB; + updateCounter = 1; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 0; + end + `cINCRE_I: + begin + nextState = `cWAIT; + updateCounter = 1; + end + `cWAIT: + if (waitCycles == 0) + begin + if (i1 == stop) + nextState = `cDONE; + else if (mode == 0) + nextState = `cSTORE_DIAG; + else if (mode == 1) + nextState = `cFIND_REC; + else + nextState = `cUPDATE_J; + updateCounter = 1; + end + else + begin + nextState = `cWAIT; + updateCounter = 0; + end + `cDONE: + begin + nextState = `cDONE; + updateCounter = 0; + end + default: + begin + nextState = `cSETUP; + updateCounter = 1; + end + endcase +end + +always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +begin + if (currentRowState == `cDONE_FETCH_ROW) + doneFetchRow = 1; + else + doneFetchRow = 0; + if((nextState == `cSTART_FETCH_ROW && currentState != `cSTART_FETCH_ROW && i1 == 1)) + startFetchRow = 1; + else + startFetchRow = 0; + if (currentState == `cMULT_SUB && topIdxCounter+2 == mdivk) + loadRow = 1; + else + loadRow = 0; + writeRow = (msIdxCounter == readRowCounter)&&(currentState==`cMULT_SUB)&&(j!=n)&&(mode[0] == 0); +end + +// second FSM that controls the control signals to temp_top block +always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +begin + case (currentRowState) + `cFETCH_ROW: + if (nextTopIdxCounter == n-1) + nextRowState = `cDONE_FETCH_ROW; + else + nextRowState = `cFETCH_ROW; + `cDONE_FETCH_ROW: + if (startFetchRow == 1) + nextRowState = `cFETCH_ROW; + else if (loadRow == 1 || (topIdx+1 == mdivk && nextState == `cMULT_SUB)) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + `cLOAD_ROW_INC_J: + if (topIdx+1 == mdivk && nextState == `cMULT_SUB) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + default: + nextRowState = `cDONE_FETCH_ROW; + endcase +end + +// address counters +always @ (posedge clk) +begin + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + topIdxCounter <= topIdx; + else + topIdxCounter <= topIdxCounter + 1; + + if (updateCounter == 1) + diagIdxCounter <= diagIdx; + else + diagIdxCounter <= diagIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + msIdxCounter <= msIdx; + else + msIdxCounter <= msIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + leftIdxCounter <= leftIdx; + else + leftIdxCounter <= leftIdxCounter + 1; + + if (currentState == `cFETCH_COL || currentState == `cSTORE_MO) + topWriteCounter <= i1; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + topWriteCounter <= topWriteCounter + 1; + + if (currentState == `cSTART) + nextTopIdxCounter <= nextTopIdx; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + nextTopIdxCounter <= nextTopIdx + n + 1; + else + nextTopIdxCounter <= nextTopIdx + n; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + nextTopIdxCounter <= nextTopIdxCounter + 1; + + if (currentState == `cSTART) + readRowCounter <= 0; //offsetdivk; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + readRowCounter <= leftIdx + 2; + else + readRowCounter <= topIdx; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + readRowCounter <= readRowCounter + 2; + + if (updateCounter == 1) + counter <= 0; + else + counter <= counter + 1; + + if (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2) + divCounter <= 0; + else if (divCounter < 56) + divCounter <= divCounter + 1; + + case (i1modk) + 5'b00000: begin + i1modkByteEn <= ~(128'b0) >> (5'b00000<<2'b10); + end + 5'b00001: begin + i1modkByteEn <= ~(128'b0) >> (5'b00001<<2'b10); + end + 5'b00010: begin + i1modkByteEn <= ~(128'b0) >> (5'b00010<<2'b10); + end + 5'b00011: begin + i1modkByteEn <= ~(128'b0) >> (5'b00011<<2'b10); + end + 5'b00100: begin + i1modkByteEn <= ~(128'b0) >> (5'b00100<<2'b10); + end + 5'b00101: begin + i1modkByteEn <= ~(128'b0) >> (5'b00101<<2'b10); + end + 5'b00110: begin + i1modkByteEn <= ~(128'b0) >> (5'b00110<<2'b10); + end + 5'b00111: begin + i1modkByteEn <= ~(128'b0) >> (5'b00111<<2'b10); + end + 5'b01000: begin + i1modkByteEn <= ~(128'b0) >> (5'b01000<<2'b10); + end + 5'b01001: begin + i1modkByteEn <= ~(128'b0) >> (5'b01001<<2'b10); + end + 5'b01010: begin + i1modkByteEn <= ~(128'b0) >> (5'b01010<<2'b10); + end + 5'b01011: begin + i1modkByteEn <= ~(128'b0) >> (5'b01011<<2'b10); + end + 5'b01100: begin + i1modkByteEn <= ~(128'b0) >> (5'b01100<<2'b10); + end + 5'b01101: begin + i1modkByteEn <= ~(128'b0) >> (5'b01101<<2'b10); + end + 5'b01110: begin + i1modkByteEn <= ~(128'b0) >> (5'b01110<<2'b10); + end + 5'b01111: begin + i1modkByteEn <= ~(128'b0) >> (5'b01111<<2'b10); + end + 5'b10000: begin + i1modkByteEn <= ~(128'b0) >> (5'b10000<<2'b10); + end + 5'b10001: begin + i1modkByteEn <= ~(128'b0) >> (5'b10001<<2'b10); + end + 5'b10010: begin + i1modkByteEn <= ~(128'b0) >> (5'b10010<<2'b10); + end + 5'b10011: begin + i1modkByteEn <= ~(128'b0) >> (5'b10011<<2'b10); + end + 5'b10100: begin + i1modkByteEn <= ~(128'b0) >> (5'b10100<<2'b10); + end + 5'b10101: begin + i1modkByteEn <= ~(128'b0) >> (5'b10101<<2'b10); + end + 5'b10110: begin + i1modkByteEn <= ~(128'b0) >> (5'b10110<<2'b10); + end + 5'b10111: begin + i1modkByteEn <= ~(128'b0) >> (5'b10111<<2'b10); + end + 5'b11000: begin + i1modkByteEn <= ~(128'b0) >> (5'b11000<<2'b10); + end + 5'b11001: begin + i1modkByteEn <= ~(128'b0) >> (5'b11001<<2'b10); + end + 5'b11010: begin + i1modkByteEn <= ~(128'b0) >> (5'b11010<<2'b10); + end + 5'b11011: begin + i1modkByteEn <= ~(128'b0) >> (5'b11011<<2'b10); + end + 5'b11100: begin + i1modkByteEn <= ~(128'b0) >> (5'b11100<<2'b10); + end + 5'b11101: begin + i1modkByteEn <= ~(128'b0) >> (5'b11101<<2'b10); + end + 5'b11110: begin + i1modkByteEn <= ~(128'b0) >> (5'b11110<<2'b10); + end + 5'b11111: begin + i1modkByteEn <= ~(128'b0) >> (5'b11111<<2'b10); + end + default: begin + i1modkByteEn <= ~(128'b0); + end + endcase +end + +// compute Byte Enable +always @ (posedge clk) +begin + if ((nextState == `cMULT_COL && currentState != `cMULT_COL) || (currentState == `cSTORE_MO) || currentRowState == `cLOAD_ROW_INC_J) + byteEn <= i1modkByteEn; + else + byteEn <= 128'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; +end + +// update FSM state register +always @ (posedge clk) +begin + if (start_in == 1'b1) + currentState <= `cSETUP; + else + currentState <= nextState; + if (start == 1'b1) + currentRowState <= `cDONE_FETCH_ROW; + else + currentRowState <= nextRowState; +end + +// delay register for control signals +// control signals are delayed to match latency of operations and/or memory access +always @ (posedge clk) +begin + curReadAddrDelay0 <= curReadAddrDelay1; + curReadAddrDelay1 <= curReadAddrDelay2; + curReadAddrDelay2 <= curReadAddrDelay3; + curReadAddrDelay3 <= curReadAddrDelay4; + curReadAddrDelay4 <= curReadAddrDelay5; + curReadAddrDelay5 <= curReadAddrDelay6; + curReadAddrDelay6 <= curReadAddrDelay7; + curReadAddrDelay7 <= curReadAddrDelay8; + curReadAddrDelay8 <= curReadAddrDelay9; + curReadAddrDelay9 <= curReadAddrDelay10; + curReadAddrDelay10 <= curReadAddrDelay11; + curReadAddrDelay11 <= msIdxCounter; + + curWriteAddrDelay0 <= curWriteAddrDelay1; + curWriteAddrDelay1 <= curWriteAddrDelay2; + curWriteAddrDelay2 <= curWriteAddrDelay3; + curWriteAddrDelay3 <= curWriteAddrDelay4; + if (currentState == `cFETCH_COL) + curWriteAddrDelay4 <= diagIdxCounter; + else + curWriteAddrDelay4 <= curWriteAddrDelay5; + curWriteAddrDelay5 <= curWriteAddrDelay6; + curWriteAddrDelay6 <= curWriteAddrDelay7; + curWriteAddrDelay7 <= curWriteAddrDelay8; + curWriteAddrDelay8 <= curWriteAddrDelay9; + curWriteAddrDelay9 <= curWriteAddrDelay10; + curWriteAddrDelay10 <= curWriteAddrDelay11; + curWriteAddrDelay11 <= curWriteAddrDelay12; + curWriteAddrDelay12 <= curWriteAddrDelay13; + curWriteAddrDelay13 <= curWriteAddrDelay14; + curWriteAddrDelay14 <= curWriteAddrDelay15; + if (currentState == `cMULT_COL) + curWriteAddrDelay15 <= leftIdxCounter; + else + curWriteAddrDelay15 <= curWriteAddrDelay16; + curWriteAddrDelay16 <= curWriteAddrDelay17; + curWriteAddrDelay17 <= curWriteAddrDelay18; + curWriteAddrDelay18 <= curWriteAddrDelay19; + curWriteAddrDelay19 <= curWriteAddrDelay20; + curWriteAddrDelay20 <= curWriteAddrDelay21; + curWriteAddrDelay21 <= curWriteAddrDelay22; + curWriteAddrDelay22 <= curWriteAddrDelay23; + curWriteAddrDelay23 <= curWriteAddrDelay24; + curWriteAddrDelay24 <= curWriteAddrDelay25; + curWriteAddrDelay25 <= curWriteAddrDelay26; + curWriteAddrDelay26 <= curWriteAddrDelay27; + curWriteAddrDelay27 <= curWriteAddrDelay28; + curWriteAddrDelay28 <= curWriteAddrDelay29; + curWriteAddrDelay29 <= curWriteAddrDelay30; + curWriteAddrDelay30 <= curWriteAddrDelay31; + curWriteAddrDelay31 <= msIdxCounter; + + writeByteEnDelay0 <= writeByteEnDelay1; + writeByteEnDelay1 <= writeByteEnDelay2; + writeByteEnDelay2 <= writeByteEnDelay3; + writeByteEnDelay3 <= writeByteEnDelay4; + if (mode[0] == 1'b1) + writeByteEnDelay4 <= ~0; + else if (currentState == `cFETCH_COL) + writeByteEnDelay4 <= byteEn; + else + writeByteEnDelay4 <= writeByteEnDelay5; + writeByteEnDelay5 <= writeByteEnDelay6; + writeByteEnDelay6 <= writeByteEnDelay7; + writeByteEnDelay7 <= writeByteEnDelay8; + writeByteEnDelay8 <= writeByteEnDelay9; + writeByteEnDelay9 <= writeByteEnDelay10; + writeByteEnDelay10 <= writeByteEnDelay11; + writeByteEnDelay11 <= writeByteEnDelay12; + writeByteEnDelay12 <= writeByteEnDelay13; + writeByteEnDelay13 <= writeByteEnDelay14; + writeByteEnDelay14 <= writeByteEnDelay15; + if (currentState == `cMULT_COL) + writeByteEnDelay15 <= byteEn; + else + writeByteEnDelay15 <= writeByteEnDelay16; + writeByteEnDelay16 <= writeByteEnDelay17; + writeByteEnDelay17 <= writeByteEnDelay18; + writeByteEnDelay18 <= writeByteEnDelay19; + writeByteEnDelay19 <= writeByteEnDelay20; + writeByteEnDelay20 <= writeByteEnDelay21; + writeByteEnDelay21 <= writeByteEnDelay22; + writeByteEnDelay22 <= writeByteEnDelay23; + writeByteEnDelay23 <= writeByteEnDelay24; + writeByteEnDelay24 <= writeByteEnDelay25; + writeByteEnDelay25 <= writeByteEnDelay26; + writeByteEnDelay26 <= writeByteEnDelay27; + writeByteEnDelay27 <= writeByteEnDelay28; + writeByteEnDelay28 <= writeByteEnDelay29; + writeByteEnDelay29 <= writeByteEnDelay30; + writeByteEnDelay30 <= writeByteEnDelay31; + writeByteEnDelay31 <= byteEn; + + curWriteSelDelay[0] <= curWriteSelDelay[1]; + curWriteSelDelay[1] <= curWriteSelDelay[2]; + curWriteSelDelay[2] <= curWriteSelDelay[3]; + curWriteSelDelay[3] <= curWriteSelDelay[4]; + curWriteSelDelay[4] <= curWriteSelDelay[5]; + curWriteSelDelay[5] <= curWriteSelDelay[6]; + curWriteSelDelay[6] <= curWriteSelDelay[7]; + curWriteSelDelay[7] <= curWriteSelDelay[8]; + curWriteSelDelay[8] <= curWriteSelDelay[9]; + curWriteSelDelay[9] <= curWriteSelDelay[10]; + curWriteSelDelay[10] <= curWriteSelDelay[11]; + curWriteSelDelay[11] <= curWriteSelDelay[12]; + curWriteSelDelay[12] <= curWriteSelDelay[13]; + curWriteSelDelay[13] <= curWriteSelDelay[14]; + curWriteSelDelay[14] <= curWriteSelDelay[15]; + if (currentState == `cMULT_COL) + curWriteSelDelay[15] <= 1'b0; + else + curWriteSelDelay[15] <= 1'b1; + + curWriteEnDelay[0] <= curWriteEnDelay[1]; + curWriteEnDelay[1] <= curWriteEnDelay[2]; + curWriteEnDelay[2] <= curWriteEnDelay[3]; + curWriteEnDelay[3] <= curWriteEnDelay[4]; + curWriteEnDelay[4] <= curWriteEnDelay[5]; + curWriteEnDelay[5] <= curWriteEnDelay[6]; + curWriteEnDelay[6] <= curWriteEnDelay[7]; + curWriteEnDelay[7] <= curWriteEnDelay[8]; + curWriteEnDelay[8] <= curWriteEnDelay[9]; + curWriteEnDelay[9] <= curWriteEnDelay[10]; + curWriteEnDelay[10] <= curWriteEnDelay[11]; + curWriteEnDelay[11] <= curWriteEnDelay[12]; + curWriteEnDelay[12] <= curWriteEnDelay[13]; + curWriteEnDelay[13] <= curWriteEnDelay[14]; + curWriteEnDelay[14] <= curWriteEnDelay[15]; + if (currentState == `cMULT_COL) + curWriteEnDelay[15] <= 1'b1; + else + curWriteEnDelay[15] <= curWriteEnDelay[16]; + curWriteEnDelay[16] <= curWriteEnDelay[17]; + curWriteEnDelay[17] <= curWriteEnDelay[18]; + curWriteEnDelay[18] <= curWriteEnDelay[19]; + curWriteEnDelay[19] <= curWriteEnDelay[20]; + curWriteEnDelay[20] <= curWriteEnDelay[21]; + curWriteEnDelay[21] <= curWriteEnDelay[22]; + curWriteEnDelay[22] <= curWriteEnDelay[23]; + curWriteEnDelay[23] <= curWriteEnDelay[24]; + curWriteEnDelay[24] <= curWriteEnDelay[25]; + curWriteEnDelay[25] <= curWriteEnDelay[26]; + curWriteEnDelay[26] <= curWriteEnDelay[27]; + curWriteEnDelay[27] <= curWriteEnDelay[28]; + curWriteEnDelay[28] <= curWriteEnDelay[29]; + curWriteEnDelay[29] <= curWriteEnDelay[30]; + curWriteEnDelay[30] <= curWriteEnDelay[31]; + if (currentState == `cMULT_SUB) + curWriteEnDelay[31] <= 1'b1; + else + curWriteEnDelay[31] <= 1'b0; + + leftWriteSelDelay[0] <= leftWriteSelDelay[1]; + leftWriteSelDelay[1] <= leftWriteSelDelay[2]; + leftWriteSelDelay[2] <= leftWriteSelDelay[3]; + leftWriteSelDelay[3] <= leftWriteSelDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteSelDelay[4] <= 1'b0; + else + leftWriteSelDelay[4] <= 1'b1; + + leftWriteEnDelay[0] <= leftWriteEnDelay[1]; + leftWriteEnDelay[1] <= leftWriteEnDelay[2]; + leftWriteEnDelay[2] <= leftWriteEnDelay[3]; + leftWriteEnDelay[3] <= leftWriteEnDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteEnDelay[4] <= 1'b1; + else + leftWriteEnDelay[4] <= leftWriteEnDelay[5]; + leftWriteEnDelay[5] <= leftWriteEnDelay[6]; + leftWriteEnDelay[6] <= leftWriteEnDelay[7]; + leftWriteEnDelay[7] <= leftWriteEnDelay[8]; + leftWriteEnDelay[8] <= leftWriteEnDelay[9]; + leftWriteEnDelay[9] <= leftWriteEnDelay[10]; + leftWriteEnDelay[10] <= leftWriteEnDelay[11]; + leftWriteEnDelay[11] <= leftWriteEnDelay[12]; + leftWriteEnDelay[12] <= leftWriteEnDelay[13]; + leftWriteEnDelay[13] <= leftWriteEnDelay[14]; + leftWriteEnDelay[14] <= leftWriteEnDelay[15]; + if (currentState == `cMULT_COL) + leftWriteEnDelay[15] <= 1'b1; + else + leftWriteEnDelay[15] <= leftWriteEnDelay[16]; + leftWriteEnDelay[16] <= leftWriteEnDelay[17]; + leftWriteEnDelay[17] <= leftWriteEnDelay[18]; + leftWriteEnDelay[18] <= leftWriteEnDelay[19]; + leftWriteEnDelay[19] <= leftWriteEnDelay[20]; + leftWriteEnDelay[20] <= leftWriteEnDelay[21]; + leftWriteEnDelay[21] <= leftWriteEnDelay[22]; + leftWriteEnDelay[22] <= leftWriteEnDelay[23]; + leftWriteEnDelay[23] <= leftWriteEnDelay[24]; + leftWriteEnDelay[24] <= leftWriteEnDelay[25]; + leftWriteEnDelay[25] <= leftWriteEnDelay[26]; + leftWriteEnDelay[26] <= leftWriteEnDelay[27]; + leftWriteEnDelay[27] <= leftWriteEnDelay[28]; + leftWriteEnDelay[28] <= leftWriteEnDelay[29]; + leftWriteEnDelay[29] <= leftWriteEnDelay[30]; + leftWriteEnDelay[30] <= leftWriteEnDelay[31]; + if (currentState == `cMULT_SUB && (mode == 0 || (mode == 1 && j == i1))) + leftWriteEnDelay[31] <= 1'b1; + else + leftWriteEnDelay[31] <= 1'b0; + + topWriteAddrDelay0 <= topWriteAddrDelay1; + topWriteAddrDelay1 <= topWriteAddrDelay2; + topWriteAddrDelay2 <= topWriteAddrDelay3; + topWriteAddrDelay3 <= topWriteAddrDelay4; + if (currentRowState == `cFETCH_ROW) + topWriteAddrDelay4 <= nextTopIdxCounter; + else + topWriteAddrDelay4 <= topWriteAddrDelay5; + topWriteAddrDelay5 <= topWriteAddrDelay6; + topWriteAddrDelay6 <= topWriteAddrDelay7; + topWriteAddrDelay7 <= topWriteAddrDelay8; + topWriteAddrDelay8 <= topWriteAddrDelay9; + topWriteAddrDelay9 <= topWriteAddrDelay10; + topWriteAddrDelay10 <= topWriteAddrDelay11; + topWriteAddrDelay11 <= topWriteAddrDelay12; + topWriteAddrDelay12 <= topWriteAddrDelay13; + topWriteAddrDelay13 <= topWriteAddrDelay14; + topWriteAddrDelay14 <= topWriteAddrDelay15; + topWriteAddrDelay15 <= topWriteAddrDelay16; + topWriteAddrDelay16 <= topWriteAddrDelay17; + topWriteAddrDelay17 <= topWriteAddrDelay18; + topWriteAddrDelay18 <= topWriteAddrDelay19; + topWriteAddrDelay19 <= topWriteAddrDelay20; + topWriteAddrDelay20 <= topWriteAddrDelay21; + topWriteAddrDelay21 <= topWriteAddrDelay22; + topWriteAddrDelay22 <= topWriteAddrDelay23; + topWriteAddrDelay23 <= topWriteAddrDelay24; + topWriteAddrDelay24 <= topWriteAddrDelay25; + topWriteAddrDelay25 <= topWriteAddrDelay26; + topWriteAddrDelay26 <= topWriteAddrDelay27; + topWriteAddrDelay27 <= topWriteAddrDelay28; + topWriteAddrDelay28 <= topWriteAddrDelay29; + topWriteAddrDelay29 <= topWriteAddrDelay30; + topWriteAddrDelay30 <= topWriteAddrDelay31; + topWriteAddrDelay31 <= nextTopIdxCounter; + + topWriteEnDelay[0] <= topWriteEnDelay[1]; + topWriteEnDelay[1] <= topWriteEnDelay[2]; + topWriteEnDelay[2] <= topWriteEnDelay[3]; + topWriteEnDelay[3] <= topWriteEnDelay[4]; + if (currentRowState == `cFETCH_ROW) + topWriteEnDelay[4] <= 1'b1; + else + topWriteEnDelay[4] <= topWriteEnDelay[5]; + topWriteEnDelay[5] <= topWriteEnDelay[6]; + topWriteEnDelay[6] <= topWriteEnDelay[7]; + topWriteEnDelay[7] <= topWriteEnDelay[8]; + topWriteEnDelay[8] <= topWriteEnDelay[9]; + topWriteEnDelay[9] <= topWriteEnDelay[10]; + topWriteEnDelay[10] <= topWriteEnDelay[11]; + topWriteEnDelay[11] <= topWriteEnDelay[12]; + topWriteEnDelay[12] <= topWriteEnDelay[13]; + topWriteEnDelay[13] <= topWriteEnDelay[14]; + topWriteEnDelay[14] <= topWriteEnDelay[15]; + topWriteEnDelay[15] <= topWriteEnDelay[16]; + topWriteEnDelay[16] <= topWriteEnDelay[17]; + topWriteEnDelay[17] <= topWriteEnDelay[18]; + topWriteEnDelay[18] <= topWriteEnDelay[19]; + topWriteEnDelay[19] <= topWriteEnDelay[20]; + topWriteEnDelay[20] <= topWriteEnDelay[21]; + topWriteEnDelay[21] <= topWriteEnDelay[22]; + topWriteEnDelay[22] <= topWriteEnDelay[23]; + topWriteEnDelay[23] <= topWriteEnDelay[24]; + topWriteEnDelay[24] <= topWriteEnDelay[25]; + topWriteEnDelay[25] <= topWriteEnDelay[26]; + topWriteEnDelay[26] <= topWriteEnDelay[27]; + topWriteEnDelay[27] <= topWriteEnDelay[28]; + topWriteEnDelay[28] <= topWriteEnDelay[29]; + topWriteEnDelay[29] <= topWriteEnDelay[30]; + topWriteEnDelay[30] <= topWriteEnDelay[31]; + topWriteEnDelay[31] <= writeRow; + + topWriteSelDelay0 <= topWriteSelDelay1; + topWriteSelDelay1 <= topWriteSelDelay2; + topWriteSelDelay2 <= topWriteSelDelay3; + topWriteSelDelay3 <= topWriteSelDelay4; + if (currentRowState == `cFETCH_ROW || currentState == `cUPDATE_J && i1 == 1) + topWriteSelDelay4 <= imodk; + else + topWriteSelDelay4 <= topWriteSelDelay5; + topWriteSelDelay5 <= topWriteSelDelay6; + topWriteSelDelay6 <= topWriteSelDelay7; + topWriteSelDelay7 <= topWriteSelDelay8; + topWriteSelDelay8 <= topWriteSelDelay9; + topWriteSelDelay9 <= topWriteSelDelay10; + topWriteSelDelay10 <= topWriteSelDelay11; + topWriteSelDelay11 <= topWriteSelDelay12; + topWriteSelDelay12 <= topWriteSelDelay13; + topWriteSelDelay13 <= topWriteSelDelay14; + topWriteSelDelay14 <= topWriteSelDelay15; + topWriteSelDelay15 <= topWriteSelDelay16; + topWriteSelDelay16 <= topWriteSelDelay17; + topWriteSelDelay17 <= topWriteSelDelay18; + topWriteSelDelay18 <= topWriteSelDelay19; + topWriteSelDelay19 <= topWriteSelDelay20; + topWriteSelDelay20 <= topWriteSelDelay21; + topWriteSelDelay21 <= topWriteSelDelay22; + topWriteSelDelay22 <= topWriteSelDelay23; + topWriteSelDelay23 <= topWriteSelDelay24; + topWriteSelDelay24 <= topWriteSelDelay25; + topWriteSelDelay25 <= topWriteSelDelay26; + topWriteSelDelay26 <= topWriteSelDelay27; + topWriteSelDelay27 <= topWriteSelDelay28; + topWriteSelDelay28 <= topWriteSelDelay29; + topWriteSelDelay29 <= topWriteSelDelay30; + topWriteSelDelay30 <= topWriteSelDelay31; + topWriteSelDelay31 <= i1modk; + + topSourceSelDelay[0] <= topSourceSelDelay[1]; + topSourceSelDelay[1] <= topSourceSelDelay[2]; + topSourceSelDelay[2] <= topSourceSelDelay[3]; + topSourceSelDelay[3] <= topSourceSelDelay[4]; + if (start == 1'b1) + topSourceSelDelay[4] <= 1'b0; + else if (currentState == `cSTORE_MO) + topSourceSelDelay[4] <= 1'b1; + + leftReadAddrDelay0 <= leftIdxCounter; + + + diagEnDelay[0] <= diagEnDelay[1]; + diagEnDelay[1] <= diagEnDelay[2]; + diagEnDelay[2] <= diagEnDelay[3]; + diagEnDelay[3] <= diagEnDelay[4]; + diagEnDelay[4] <= diagEnDelay[5]; + diagEnDelay[5] <= (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2); + + MOEnDelay[0] <= MOEnDelay[1]; + MOEnDelay[1] <= MOEnDelay[2]; + MOEnDelay[2] <= MOEnDelay[3]; + MOEnDelay[3] <= MOEnDelay[4]; + MOEnDelay[4] <= MOEnDelay[5]; + if (currentState == `cSTORE_MO || currentRowState == `cLOAD_ROW_INC_J) + MOEnDelay[5] <= 1'b1; + else + MOEnDelay[5] <= 1'b0; +end + +// output contorl signals +always @ (posedge clk) +begin + if (currentState == `cFETCH_COL) + curReadAddr <= diagIdxCounter; + else if (currentRowState == `cFETCH_ROW) + curReadAddr <= readRowCounter; + else + curReadAddr <= curReadAddrDelay0; + curWriteAddr <= curWriteAddrDelay0; + curWriteByteEn <= writeByteEnDelay0; + curWriteSel <= curWriteSelDelay; + curWriteEn <= curWriteEnDelay; + + if (currentState == `cMULT_COL) + leftReadAddr <= leftIdxCounter; + else + leftReadAddr <= leftReadAddrDelay0; + leftWriteAddr <= curWriteAddrDelay0; + leftWriteByteEn <= writeByteEnDelay0; + leftWriteSel <= leftWriteSelDelay; + leftWriteEn <= leftWriteEnDelay; + + if (currentState == `cSTORE_DIAG) + topReadAddr <= nextTopIdx; +else if (currentState == `cSTORE_DIAG2) + topReadAddr <= nextTopIdx2; + else + topReadAddr <= curTopIdx; + topWriteAddr <= topWriteAddrDelay0; + topWriteEn <= topWriteEnDelay; + topWriteSel <= topWriteSelDelay0; + topSourceSel <= topSourceSelDelay; + + MOSel <= ~(currentState == `cFIND_REC); +if (currentState == `cFIND_REC) + MOEn <= 1'b1; + else + MOEn <= MOEnDelay; + + diagEn <= diagEnDelay; + + if (currentState == `cDONE) + done <= 1'b1; + else + done <= 1'b0; +end + +endmodule + +module ram ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram1 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram2 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram3 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 1024'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 1024'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + + +module top_ram ( + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + //parameter TOPSIZE = 4096, TOPSIZEWIDTH = 12, TOPWIDTH = 32; + + input clk; + input [32-1:0] data; + input [12-1:0] rdaddress; + input [12-1:0] wraddress; + input wren; + output [32-1:0] q; + + wire [32-1:0] sub_wire0; + wire [32-1:0] q; + wire [32-1:0] junk_output; + assign q = sub_wire0 | dummy; + wire[32-1:0] dummy; + assign dummy = junk_output & 32'b0; + dual_port_ram inst2( + .clk (clk), + .we1(wren), + .we2(1'b0), + .data1(data), + .data2(data), + .out1(junk_output), + .out2(sub_wire0), + .addr1(wraddress), + .addr2(rdaddress)); + +endmodule + +module mult_add (clk, A, B, C, mult_result, add_result); +//parameter PRECISION = 32; +input clk; +input [32-1:0] A, B, C; +output [32-1:0] mult_result, add_result; +reg [32-1:0] mult_result; +reg [32-1:0] add_result; +wire [32-1:0] mult_comp_result; +reg [32-1:0] add_a, add_b; +wire [32-1:0] addition_result; +wire [31:0] dummy_wire; +assign dummy_wire = mult_comp_result>>2'b10; +//divsp MUL(.clk(clk), .rmode(2'b00), .fpu_op(3'b010), .opa(A), .opb(B), .ans(mult_comp_result) ); +wire [4:0]dummy_wire_2; +fpmul MUL(.clk(clk), .a(A), .b(B), .y_out(mult_comp_result), .control(2'b00), .flags(dummy_wire_2)); +fpu_add ADD(.clock(clk), .a1(C), .b1(dummy_wire), .sum(addition_result)); +always @ (posedge clk) +begin + add_result <= addition_result; + mult_result <= mult_comp_result[31:0]; +end +endmodule + + +//`define rFIFOINPUTWIDTH 64 +`define rFIFOSIZE 256 +`define rFIFOSIZEWIDTH 8 +`define rFIFOOUTPUTWIDTH 1024 +`define rFIFORSIZEWIDTH 4 + `define wFIFOINPUTWIDTH 12'b010000000000 + `define wFIFOSIZE 6'b010000 + `define wFIFOSIZEWIDTH 4'b0100 + `define wFIFOOUTPUTWIDTH 8'b01000000 + `define wFIFORSIZEWIDTH 5'b01000 + //for addr_fifo +`define aFIFOSIZE 6'b010000 +`define aFIFOSIZEWIDTH 4'b0100 +`define aFIFOWIDTH 4'b0111 +//for memfifo +`define mFIFOSIZE 16 +`define mFIFOSIZEWIDTH 4 +//`define mFIFOWIDTH 28 + +`define BURSTLEN 3'b010 +`define BURSTWIDTH 3'b010 +`define DATAWIDTH 12'b010000000000 +`define DATANUMBYTES 9'b010000000 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define FIFOSIZE 6'b010000 +`define FIFOSIZEWIDTH 4'b0100 +`define RAMWIDTH 12'b010000000000 +`define RAMNUMBYTES 9'b010000000 +`define RAMSIZEWIDTH 4'b0111 +`define RATIO 6'b010000 +`define RAMLAT 4'b0101 + +`define dIDLE 0 +`define dWRITE 1 +`define dREAD 2 + +module DataTransferUnit (clk, dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, + ram_read_addr, ram_read_data, ram_write_byte_en, ram_write_data, ram_write_addr, ram_write_en, + mem_rdata, mem_rdata_valid, mem_ready, mem_wdata_req, reset_n, + burst_begin, mem_local_addr, mem_be, mem_read_req, mem_size, mem_wdata, mem_write_req + ); + +output burst_begin; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +output [`MEMCONNUMBYTES-1: 0] mem_be; +output mem_read_req; +output [`BURSTWIDTH-1:0] mem_size; +output [`MEMCONWIDTH-1:0] mem_wdata; +output mem_write_req; +input clk; +input [`MEMCONWIDTH-1:0] mem_rdata; +input mem_rdata_valid; +input mem_ready; +input mem_wdata_req; +input reset_n; + +input dtu_write_req; +input dtu_read_req; +input [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +input [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +input [6:0] dtu_size; +output dtu_ack; +output dtu_done; + +output[`RAMWIDTH-1:0] ram_write_data; +input[`RAMWIDTH-1:0] ram_read_data; +output[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +output[`RAMNUMBYTES-1:0] ram_write_byte_en; +output ram_write_en; + +reg[`DDRSIZEWIDTH-1:0] mem_addr0; +reg[`DDRSIZEWIDTH-1:0] mem_addr1; +reg[`DDRSIZEWIDTH-1:0] mem_addr2; +reg[`DDRSIZEWIDTH-1:0] mem_addr3; +reg[`DDRSIZEWIDTH-1:0] mem_addr4; +reg[`DDRSIZEWIDTH-1:0] mem_addr5; + +reg [1:0] state; +wire [`DATAWIDTH-1:0] rdata, ram_write_dataw, ram_read_dataw; + +wire [`RAMSIZEWIDTH-1:0] rfifo_addr; +reg [`RAMLAT-1:0]fifo_write_reg; +reg [`RAMLAT-1:0]write_req_reg; +reg [`RAMLAT-1:0]read_req_reg; +reg [0:0]fifo_read_reg; +reg rdata_valid; +reg [1:0]test_complete_reg; +reg [`BURSTWIDTH-1:0] size_count0; +reg [`BURSTWIDTH-1:0] size_count1; +reg [`BURSTWIDTH-1:0] size_count2; +reg [`BURSTWIDTH-1:0] size_count3; +reg [`BURSTWIDTH-1:0] size_count4; + +reg [`RAMSIZEWIDTH-1:0] size; +reg [`RAMSIZEWIDTH-1:0]ram_addr0; +reg [`RAMSIZEWIDTH-1:0]ram_addr1; +reg [`RAMSIZEWIDTH-1:0]ram_addr2; +reg [`RAMSIZEWIDTH-1:0]ram_addr3; +reg [`RAMSIZEWIDTH-1:0]ram_addr4; + +reg [4:0] data_count; +reg ram_write_en_reg; + +wire read_req; +wire write_req; +wire [`FIFOSIZEWIDTH-1:0] wfifo_count; +wire rfull, wempty, rempty, rdcmd_empty, wrcmd_full, wrcmd_empty, rdata_empty; +wire [`DATAWIDTH-1:0] mem_data; +wire not_stall; +wire fifo_write, fifo_read; +wire rdata_req; +wire [`BURSTWIDTH+`DDRSIZEWIDTH+1:0] wrmem_cmd, rdmem_cmd; +wire mem_cmd_ready, mem_cmd_issue; + +// FIFOs to interact with off-chip memory +memcmd_fifo cmd_store( + //.aclr(~reset_n), + //.rdclk(phy_clk), + .clk(clk), + .data(wrmem_cmd), + .rdreq(mem_cmd_ready), + //.rdempty(rdcmd_empty), + .wrreq(mem_cmd_issue), + .full(wrcmd_full), + .empty(wrcmd_empty), + .q(rdmem_cmd) + ); + +wfifo wdata_store( + //.rdclk(phy_clk), + .clk(clk), + .data(mem_data), + .rdreq(mem_wdata_req), + .wrreq(fifo_write), + .empty(wempty), + .q(mem_wdata), + .usedw(wfifo_count) + ); + +addr_fifo raddress_store ( + .clk(clk), + .data(ram_addr3), + .wrreq(fifo_read), + .rdreq(rdata_req), + .empty(rempty), + .full(rfull), + .q(rfifo_addr) + ); + +rfifo rdata_store( + .clk(clk), + .data(mem_rdata), + .rdreq(rdata_req), + //.wrclk(phy_clk), + .wrreq(mem_rdata_valid), + .empty(rdata_empty), + .q(rdata) + ); + +assign mem_cmd_ready = (mem_ready == 1'b1);// && (rdcmd_empty == 0); +assign mem_cmd_issue = (wrcmd_full == 1'b0) && (write_req == 1 || read_req == 1'b1 || wrcmd_empty == 1'b1); +assign wrmem_cmd[27:26] = size_count0; +assign wrmem_cmd[`DDRSIZEWIDTH+1:2] = mem_addr0; +assign wrmem_cmd[1] = read_req; +assign wrmem_cmd[0] = write_req; +assign mem_write_req = rdmem_cmd[0];// && rdcmd_empty == 0; +assign mem_read_req = rdmem_cmd[1];// && rdcmd_empty == 0; +assign mem_local_addr = rdmem_cmd[`DDRSIZEWIDTH+1:2]; +assign burst_begin = 0; +assign mem_size = rdmem_cmd[`BURSTWIDTH+`DDRSIZEWIDTH+1:`DDRSIZEWIDTH+2]; +assign mem_be = ~0; +assign fifo_write = fifo_write_reg[0]; +assign write_req = (not_stall) ? write_req_reg[0] : 0; +assign read_req = (not_stall) ? read_req_reg[0] : 0; +assign fifo_read = (not_stall) ? fifo_read_reg[0] : 0; +assign not_stall = (wfifo_count < `FIFOSIZE-5) && (rfull == 0) && (wrcmd_full == 0); +assign dtu_ack = (state == `dIDLE); +assign dtu_done = (state == `dIDLE) && wempty && rempty; + +assign ram_write_dataw[63:0] = rdata[1023:960]; +assign mem_data[63:0] = ram_read_dataw[1023:960]; +assign ram_write_dataw[127:64] = rdata[959:896]; +assign mem_data[127:64] = ram_read_dataw[959:896]; +assign ram_write_dataw[191:128] = rdata[895:832]; +assign mem_data[191:128] = ram_read_dataw[895:832]; +assign ram_write_dataw[255:192] = rdata[831:768]; +assign mem_data[255:192] = ram_read_dataw[831:768]; +assign ram_write_dataw[319:256] = rdata[767:704]; +assign mem_data[319:256] = ram_read_dataw[767:704]; +assign ram_write_dataw[383:320] = rdata[703:640]; +assign mem_data[383:320] = ram_read_dataw[703:640]; +assign ram_write_dataw[447:384] = rdata[639:576]; +assign mem_data[447:384] = ram_read_dataw[639:576]; +assign ram_write_dataw[511:448] = rdata[575:512]; +assign mem_data[511:448] = ram_read_dataw[575:512]; +assign ram_write_dataw[575:512] = rdata[511:448]; +assign mem_data[575:512] = ram_read_dataw[511:448]; +assign ram_write_dataw[639:576] = rdata[447:384]; +assign mem_data[639:576] = ram_read_dataw[447:384]; +assign ram_write_dataw[703:640] = rdata[383:320]; +assign mem_data[703:640] = ram_read_dataw[383:320]; +assign ram_write_dataw[767:704] = rdata[319:256]; +assign mem_data[767:704] = ram_read_dataw[319:256]; +assign ram_write_dataw[831:768] = rdata[255:192]; +assign mem_data[831:768] = ram_read_dataw[255:192]; +assign ram_write_dataw[895:832] = rdata[191:128]; +assign mem_data[895:832] = ram_read_dataw[191:128]; +assign ram_write_dataw[959:896] = rdata[127:64]; +assign mem_data[959:896] = ram_read_dataw[127:64]; +assign ram_write_dataw[1023:960] = rdata[63:0]; +assign mem_data[1023:960] = ram_read_dataw[63:0]; +assign ram_write_data = ram_write_dataw[1023:0]; +assign ram_read_dataw[1023:0] = ram_read_data; +assign ram_write_addr = rfifo_addr; +assign ram_read_addr = ram_addr4; +assign ram_write_byte_en = ~0; +assign ram_write_en = ram_write_en_reg; +assign rdata_req = !rdata_empty; + +// FSM to produce off-chip memory commands +always @ (posedge clk) +begin + if (reset_n == 1'b0) + begin + state <= `dIDLE; + end + else + begin + case (state) + `dIDLE: + begin + if (dtu_write_req) + state <= `dWRITE; + else if (dtu_read_req) + state <= `dREAD; + else + state <= `dIDLE; + end + `dWRITE: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dWRITE; + end + `dREAD: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dREAD; + end + default: + begin + state <= `dIDLE; + end + endcase + end +end + +always @ (posedge clk) +begin + + if (reset_n == 0) + begin + size <= 0; + data_count <= 0; + size_count4 <= 1; + mem_addr5 <= 0; + ram_addr4 <= 0; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (state == `dIDLE) + begin + size <= dtu_size; + size_count4 <= `BURSTLEN; + mem_addr5 <= dtu_mem_addr; + ram_addr4 <= dtu_ram_addr; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= 1'b0; + fifo_read_reg[0] <= 1'b0; + read_req_reg[`RAMLAT-1] <= 1'b0; + data_count <= 0; + end + else if (data_count >= `BURSTLEN && not_stall) + begin + data_count <= data_count - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (size == 0 && data_count == 0 && not_stall==1'b1) + begin + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (size == 0 && not_stall==1'b1) + begin + size_count4 <= data_count[`BURSTWIDTH-1:0]; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (not_stall==1'b1) + begin + size <= size - 1; + data_count <= data_count + `RATIO - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + ram_addr4 <= ram_addr4+1; + fifo_write_reg[`RAMLAT-1] <= state == `dWRITE; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= state == `dREAD; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else + begin + fifo_write_reg[`RAMLAT-1] <= 0; + end +end + + +always @ (posedge clk) +begin + if (reset_n == 0) + begin + fifo_write_reg[0] <= 1'b0; + fifo_write_reg[1] <= 1'b0; + fifo_write_reg[2] <= 1'b0; + fifo_write_reg[3] <= 1'b0; + end + else + begin + fifo_write_reg[0] <= fifo_write_reg[1]; + fifo_write_reg[1] <= fifo_write_reg[2]; + fifo_write_reg[2] <= fifo_write_reg[3]; + fifo_write_reg[3] <= fifo_write_reg[4]; + end + + if (reset_n == 1'b0) + begin + mem_addr0 <= 0; + ram_addr0 <= 0; + size_count0 <= 1; + write_req_reg[0] <= 0; + read_req_reg[0] <= 0; + mem_addr1 <= 0; + ram_addr1 <= 0; + size_count1 <= 1; + write_req_reg[1] <= 0; + read_req_reg[1] <= 0; + mem_addr2 <= 0; + ram_addr2 <= 0; + size_count2 <= 1; + write_req_reg[2] <= 0; + read_req_reg[2] <= 0; + mem_addr3 <= 0; + ram_addr3 <= 0; + size_count3 <= 1; + write_req_reg[3] <= 0; + read_req_reg[3] <= 0; + mem_addr4 <= 0; + end + else if (not_stall) + begin + size_count0 <= size_count1; + mem_addr0 <= mem_addr1; + ram_addr0 <= ram_addr1; + write_req_reg[0] <= write_req_reg[1]; + read_req_reg[0] <= read_req_reg[1]; + size_count1 <= size_count2; + mem_addr1 <= mem_addr2; + ram_addr1 <= ram_addr2; + write_req_reg[1] <= write_req_reg[2]; + read_req_reg[1] <= read_req_reg[2]; + size_count2 <= size_count3; + mem_addr2 <= mem_addr3; + ram_addr2 <= ram_addr3; + write_req_reg[2] <= write_req_reg[3]; + read_req_reg[2] <= read_req_reg[3]; + size_count3 <= size_count4; + mem_addr3 <= mem_addr4; + ram_addr3 <= ram_addr4; + write_req_reg[3] <= write_req_reg[4]; + read_req_reg[3] <= read_req_reg[4]; + mem_addr4 <= mem_addr5; + end + + ram_write_en_reg <= rdata_req; +end + +endmodule + +module rfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q + ); + + + input clk; + input wrreq; + input rdreq; + input [`rFIFOINPUTWIDTH-1:0] data; + output empty; + output [`rFIFOOUTPUTWIDTH-1:0] q; + + reg [`rFIFORSIZEWIDTH-1:0] wr_pointer; + reg [`rFIFORSIZEWIDTH-1:0] rd_pointer; + reg [`rFIFORSIZEWIDTH:0] status_cnt; + reg [`rFIFOOUTPUTWIDTH-1:0] q ; + reg[3:0] counter; + wire [`rFIFOINPUTWIDTH-1:0] data_ram; +assign empty = (status_cnt == 9'b000000000); +wire [`rFIFOINPUTWIDTH-1:0]junk_input; +wire [`rFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 64'b0000000000000000000000000000000000000000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q[`rFIFOINPUTWIDTH-1:0] <= data_ram; +else if (counter == 1) + q[127:64] <= data_ram; +else if (counter == 2) + q[191:128] <= data_ram; +else if (counter == 3) + q[255:192] <= data_ram; +else if (counter == 4) + q[319:256] <= data_ram; +else if (counter == 5) + q[383:320] <= data_ram; +else if (counter == 6) + q[447:384] <= data_ram; +else if (counter == 7) + q[511:448] <= data_ram; +else if (counter == 8) + q[575:512] <= data_ram; +else if (counter == 9) + q[639:576] <= data_ram; +else if (counter == 10) + q[703:640] <= data_ram; +else if (counter == 11) + q[767:704] <= data_ram; +else if (counter == 12) + q[831:768] <= data_ram; +else if (counter == 13) + q[895:832] <= data_ram; +else if (counter == 14) + q[959:896] <= data_ram; +else if (counter == 15) + q[1023:960] <= data_ram; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; +// Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module wfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q, + usedw + ); + + input clk; + input wrreq; + input rdreq; + input [`wFIFOINPUTWIDTH-1:0] data; + output empty; + output [`wFIFOOUTPUTWIDTH-1:0] q; + output [`wFIFOSIZEWIDTH-1:0] usedw; +//-----------Internal variables------------------- +reg [`wFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`wFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`wFIFOSIZEWIDTH:0] status_cnt; +reg [`wFIFOOUTPUTWIDTH-1:0] q ; +reg[3:0] counter; +wire [`wFIFOINPUTWIDTH-1:0] data_ram ; +assign empty = (status_cnt == 5'b00000); +wire [`wFIFOINPUTWIDTH-1:0]junk_input; +wire [`wFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 1024'b0; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q <= data_ram[63:0]; +else if(counter == 1) + q <= data_ram[127:64]; +else if(counter == 2) + q <= data_ram[191:128]; +else if(counter == 3) + q <= data_ram[255:192]; +else if(counter == 4) + q <= data_ram[319:256]; +else if(counter == 5) + q <= data_ram[383:320]; +else if(counter == 6) + q <= data_ram[447:384]; +else if(counter == 7) + q <= data_ram[511:448]; +else if(counter == 8) + q <= data_ram[575:512]; +else if(counter == 9) + q <= data_ram[639:576]; +else if(counter == 10) + q <= data_ram[703:640]; +else if(counter == 11) + q <= data_ram[767:704]; +else if(counter == 12) + q <= data_ram[831:768]; +else if(counter == 13) + q <= data_ram[895:832]; +else if(counter == 14) + q <= data_ram[959:896]; +else if(counter == 15) + q <= data_ram[1023:960]; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000 )) + status_cnt <= status_cnt + 1'b1; +end +assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module addr_fifo ( + clk, + data, + wrreq, + rdreq, + empty, + full, + q + ); + + input clk; + input [`aFIFOWIDTH-1:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [`aFIFOWIDTH-1:0] q; + +reg [`aFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`aFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`aFIFOSIZEWIDTH:0] status_cnt; +reg [`aFIFOWIDTH-1:0] q ; +wire [`aFIFOWIDTH-1:0] data_ram ; +assign full = (status_cnt == 5'b01111); +assign empty = (status_cnt == 5'b00000); +wire [`aFIFOWIDTH-1:0]junk_input; +wire [`aFIFOWIDTH-1:0]junk_output; +assign junk_input = 7'b0000000; +always @ (posedge clk) +begin //WRITE_POINTER +if (wrreq) +begin +wr_pointer <= wr_pointer + 1'b1; +end +end +always @ (posedge clk) +begin //READ_POINTER +if (rdreq) +begin +rd_pointer <= rd_pointer + 1'b1; +end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) begin +q <= data_ram; +end +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000)) + status_cnt <= status_cnt + 1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +module memcmd_fifo ( + clk, + data, + rdreq, + wrreq, + full, + empty, + q + ); + + input clk; + input [`mFIFOWIDTH-1:0] data; + input wrreq; + input rdreq; + output full; + output empty; + output [`mFIFOWIDTH-1:0] q; + + reg [`mFIFOSIZEWIDTH-1:0] wr_pointer; + reg [`mFIFOSIZEWIDTH-1:0] rd_pointer; + reg [`mFIFOSIZEWIDTH:0] status_cnt; + reg [`mFIFOWIDTH-1:0] q ; + wire [`mFIFOWIDTH-1:0] data_ram; + assign full = (status_cnt ==5'b01111); + assign empty = (status_cnt == 5'b00000); + wire [`mFIFOWIDTH-1:0]junk_input; + wire [`mFIFOWIDTH-1:0]junk_output; + assign junk_input = 28'b0000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end + end + always @ (posedge clk) + begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 1'b1; + end + end + always @ (posedge clk ) + begin //READ_DATA + if (rdreq) begin + q <= data_ram; + end + end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; + else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( + .we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable + .addr1 (wr_pointer) , // address_0 input + .addr2 (rd_pointer) , // address_q input + .data1 (data) , // data_0 bi-directional + .data2 (junk_input), // data_1 bi-directional + .clk(clk), + .out1 (data_ram), + .out2 (junk_output)); + + +endmodule + + +`define ZERO 8'b00000000 +`define ONE 8'b00000001 +`define TWO 8'b00000010 +`define THREE 8'b00000011 +`define FOUR 8'b00000100 +`define FIVE 8'b00000101 +`define SIX 8'b00000110 +`define SEVEN 8'b00000111 +`define EIGHT 8'b00001000 +`define NINE 8'b00001001 +`define TEN 8'b00001010 +`define ELEVEN 8'b00001011 +`define TWELVE 8'b00001100 +`define THIRTEEN 8'b00001101 +`define FOURTEEN 8'b00001110 +`define FIFTEEN 8'b00001111 +`define SIXTEEN 8'b00010000 +`define SEVENTEEN 8'b00010001 +`define EIGHTEEN 8'b00010010 +`define NINETEEN 8'b00010011 +`define TWENTY 8'b00010100 +`define TWENTYONE 8'b00010101 +`define TWENTYTWO 8'b00010110 +`define TWENTYTHREE 8'b00010111 +`define TWENTYFOUR 8'b00011000 + +module fpu_add (clock, a1, b1, sum); + input clock; + input [31:0]a1; + input [31:0]b1; + output [31:0]sum; + reg [31:0]sum; + + //Split up the numbers into exponents and mantissa. + reg [7:0]a_exp; + //reg [7:0]b_exp; + reg [23:0]a_man; + reg [23:0]b_man; + + reg [7:0]temp; + + reg [24:0]sum_man; + //reg [7:0]sum_exp; + + //introduce latency on inputs + reg [31:0]a; + reg [31:0]b; + + always @ (posedge clock) begin + a <= a1; + b <= b1; + end + + reg smaller; //smaller is 1 if a < b, 0 otherwise + + //Shift mantissa's to have the same exponent + always @ (a or b) begin + //a_exp = a[30:23]; + //b_exp = b[30:23]; + //a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]}; + + if (a[30:23] < b[30:23]) begin + temp = b[30:23] - a[30:23]; + //a_man = {1'b1, a[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + a_man = {1'b1, a[22:0]} >> `ONE; + end + `TWO: begin + a_man = {1'b1, a[22:0]} >> `TWO; + end + `THREE: begin + a_man = {1'b1, a[22:0]} >> `THREE; + end + `FOUR: begin + a_man = {1'b1, a[22:0]} >> `FOUR; + end + `FIVE: begin + a_man = {1'b1, a[22:0]} >> `FIVE; + end + `SIX: begin + a_man = {1'b1, a[22:0]} >> `SIX; + end + `SEVEN: begin + a_man = {1'b1, a[22:0]} >> `SEVEN; + end + `EIGHT: begin + a_man = {1'b1, a[22:0]} >> `EIGHT; + end + `NINE: begin + a_man = {1'b1, a[22:0]} >> `NINE; + end + `TEN: begin + a_man = {1'b1, a[22:0]} >> `TEN; + end + `ELEVEN: begin + a_man = {1'b1, a[22:0]} >> `ELEVEN; + end + `TWELVE: begin + a_man = {1'b1, a[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + a_man = {1'b1, a[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + a_man = {1'b1, a[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + a_man = {1'b1, a[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + a_man = {1'b1, a[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + a_man = {1'b1, a[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + a_man = {1'b1, a[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + a_man = {1'b1, a[22:0]} >> `NINETEEN; + end + `TWENTY: begin + a_man = {1'b1, a[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + endcase + + b_man = {1'b1, b[22:0]}; + a_exp = b[30:23]; + //b_exp = b[30:23]; + + end else if (a[30:23] > b[30:23]) begin + temp = a[30:23] - b[30:23]; + a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + b_man = {1'b1, b[22:0]} >> `ONE; + end + `TWO: begin + b_man = {1'b1, b[22:0]} >> `TWO; + end + `THREE: begin + b_man = {1'b1, b[22:0]} >> `THREE; + end + `FOUR: begin + b_man = {1'b1, b[22:0]} >> `FOUR; + end + `FIVE: begin + b_man = {1'b1, b[22:0]} >> `FIVE; + end + `SIX: begin + b_man = {1'b1, b[22:0]} >> `SIX; + end + `SEVEN: begin + b_man = {1'b1, b[22:0]} >> `SEVEN; + end + `EIGHT: begin + b_man = {1'b1, b[22:0]} >> `EIGHT; + end + `NINE: begin + b_man = {1'b1, b[22:0]} >> `NINE; + end + `TEN: begin + b_man = {1'b1, b[22:0]} >> `TEN; + end + `ELEVEN: begin + b_man = {1'b1, b[22:0]} >> `ELEVEN; + end + `TWELVE: begin + b_man = {1'b1, b[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + b_man = {1'b1, b[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + b_man = {1'b1, b[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + b_man = {1'b1, b[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + b_man = {1'b1, b[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + b_man = {1'b1, b[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + b_man = {1'b1, b[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + b_man = {1'b1, b[22:0]} >> `NINETEEN; + end + `TWENTY: begin + b_man = {1'b1, b[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + endcase + + a_exp = a[30:23]; + //b_exp = a[30:23]; + end else begin + temp = 8'b0; + a_man = {1'b1, a[22:0]}; + b_man = {1'b1, b[22:0]}; + a_exp = a[30:23]; + end + + end + + //Perform the addition operation + always @ (a_man or b_man or a or b) begin + if (a_man < b_man) begin + smaller = 1'b1; + end else begin + smaller = 1'b0; + end + + //both positive + if (~a[31] && ~b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b0; + end + + //both negative + else if (a[31] && b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b1; + end + + //a pos, b neg + else if (~a[31] && b[31]) begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b1; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b0; + end + end + + //a neg, b pos + else /*if (a[31] && ~b[31])*/ begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b0; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b1; + end + end + end + + //Store the number + // we already have the sign. + + always @ (sum_man or a_exp) begin + if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. + sum[22:0] = sum_man[23:1]; + sum[30:23] = a_exp + 8'b00000001; + + end else if (sum_man[23]) begin //do nothing + sum[22:0] = sum_man[22:0]; + sum[30:23] = a_exp; + + end else if (sum_man[22]) begin //shift << by 1, subtract 1 from exponent. + sum[22:0] = {sum_man[21:0], 1'b0}; + sum[30:23] = a_exp - 8'b00000001; + + end else if (sum_man[21]) begin //shift << by 2, subtract 2 from exponent. + sum[22:0] = {sum_man[20:0], 2'b0}; + sum[30:23] = a_exp - 8'b00000010; + + end else if (sum_man[20]) begin //shift << by 3, subtract 3 from exponent. + sum[22:0] = {sum_man[19:0], 3'b0}; + sum[30:23] = a_exp - 8'b00000011; + + end else if (sum_man[19]) begin //shift << by 4, subtract 4 from exponent. + sum[22:0] = {sum_man[18:0], 4'b0}; + sum[30:23] = a_exp - 8'b00000100; + + end else if (sum_man[18]) begin //shift << by 5, subtract 5 from exponent. + sum[22:0] = {sum_man[17:0], 5'b0}; + sum[30:23] = a_exp - 8'b00000101; + + end else if (sum_man[17]) begin //shift << by 6, subtract 6 from exponent. + sum[22:0] = {sum_man[16:0], 6'b0}; + sum[30:23] = a_exp - 8'b00000110; + + end else if (sum_man[16]) begin //shift << by 7, subtract 7 from exponent. + sum[22:0] = {sum_man[15:0], 7'b0}; + sum[30:23] = a_exp - 8'b00000111; + + end else if (sum_man[15]) begin //shift << by 8, subtract 8 from exponent. + sum[22:0] = {sum_man[14:0], 8'b0}; + sum[30:23] = a_exp - 8'b00001000; + + end else if (sum_man[14]) begin //shift << by 9, subtract 9 from exponent. + sum[22:0] = {sum_man[13:0], 9'b0}; + sum[30:23] = a_exp - 8'b00001001; + + end else if (sum_man[13]) begin //shift << by 10, subtract 10 from exponent. + sum[22:0] = {sum_man[12:0], 10'b0}; + sum[30:23] = a_exp - 8'b00001010; + + end else if (sum_man[12]) begin //shift << by 11, subtract 11 from exponent. + sum[22:0] = {sum_man[11:0], 11'b0}; + sum[30:23] = a_exp - 8'b00001011; + + end else if (sum_man[11]) begin //shift << by 12, subtract 12 from exponent. + sum[22:0] = {sum_man[10:0], 12'b0}; + sum[30:23] = a_exp - 8'b00001100; + + end else if (sum_man[10]) begin //shift << by 13, subtract 13 from exponent. + sum[22:0] = {sum_man[9:0], 13'b0}; + sum[30:23] = a_exp - 8'b00001101; + + end else if (sum_man[9]) begin //shift << by 14, subtract 14 from exponent. + sum[22:0] = {sum_man[8:0], 14'b0}; + sum[30:23] = a_exp - 8'b00001110; + + end else if (sum_man[8]) begin //shift << by 15, subtract 15 from exponent. + sum[22:0] = {sum_man[7:0], 15'b0}; + sum[30:23] = a_exp - 8'b00001111; + + end else if (sum_man[7]) begin //shift << by 16, subtract 16 from exponent. + sum[22:0] = {sum_man[6:0], 16'b0}; + sum[30:23] = a_exp - 8'b00010000; + + end else if (sum_man[6]) begin //shift << by 17, subtract 17 from exponent. + sum[22:0] = {sum_man[5:0], 17'b0}; + sum[30:23] = a_exp - 8'b00010001; + + end else if (sum_man[5]) begin //shift << by 18, subtract 18 from exponent. + sum[22:0] = {sum_man[4:0], 18'b0}; + sum[30:23] = a_exp - 8'b00010010; + + end else if (sum_man[4]) begin //shift << by 19, subtract 19 from exponent. + sum[22:0] = {sum_man[3:0], 19'b0}; + sum[30:23] = a_exp - 8'b00010011; + + end else if (sum_man[3]) begin //shift << by 20, subtract 20 from exponent. + sum[22:0] = {sum_man[2:0], 20'b0}; + sum[30:23] = a_exp - 8'b00010100; + + end else if (sum_man[2]) begin //shift << by 21, subtract 21 from exponent. + sum[22:0] = {sum_man[1:0], 21'b0}; + sum[30:23] = a_exp - 8'b00010101; + + end else if (sum_man[1]) begin //shift << by 22, subtract 22 from exponent. + sum[22:0] = {sum_man[0:0], 22'b0}; + sum[30:23] = a_exp - 8'b00010110; + + end else /*if (sum_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + sum[22:0] = 23'b0; + sum[30:23] = a_exp - 8'b00010111; + end + + end + +endmodule + +module fpu_div(clock, n, d, div); +//n = numerator +//d = denomenator +//div = result + input clock; + + input [31:0]n; + input [31:0]d; + output [31:0]div; + reg [31:0]div; + + //Store the mantissa and exponents separately. Introduce the latency of 1. + reg [7:0]n_exp; + reg [7:0]d_exp; + reg [23:0]n_man; + reg [23:0]d_man; + reg n_sign; + reg d_sign; + + wire [23:0]div_man; + reg [7:0]div_exp; + + always @ (posedge clock) begin + n_exp <= n[30:23]; + d_exp <= d[30:23]; + n_man <= {1'b1, n[22:0]}; + d_man <= {1'b1, d[22:0]}; + n_sign <= n[31]; + d_sign <= d[31]; + end + + //Find the exponent, store in div_exp. + always @ (n_exp or d_exp) begin + if (n_exp >= d_exp) begin + div_exp = 8'b01111111 + (n_exp - d_exp); + end else begin + div_exp = 8'b01111111 - (d_exp - n_exp); + end + end + + //Divide the mantissas, store in div_man. + div_24b divide(.numer(n_man), .denom(d_man), .res(div_man)); + + //Store the result. Shift exponents appropriately. Store sign. + //Sign + always @ (n_sign or d_sign) begin + div[31] = n_sign ^ d_sign; + end + + //Mantissa and Exponent + always @ (div_man or div_exp) begin + if (div_man[23]) begin //do nothing + div[22:0] = div_man[22:0]; + div[30:23] = div_exp; + + end else if (div_man[22]) begin //shift << by 1, subtract 1 from exponent. + div[22:0] = {div_man[21:0], 1'b0}; + div[30:23] = div_exp - 8'b00000001; + + end else if (div_man[21]) begin //shift << by 2, subtract 2 from exponent. + div[22:0] = {div_man[20:0], 2'b0}; + div[30:23] = div_exp - 8'b00000010; + + end else if (div_man[20]) begin //shift << by 3, subtract 3 from exponent. + div[22:0] = {div_man[19:0], 3'b0}; + div[30:23] = div_exp - 8'b00000011; + + end else if (div_man[19]) begin //shift << by 4, subtract 4 from exponent. + div[22:0] = {div_man[18:0], 4'b0}; + div[30:23] = div_exp - 8'b00000100; + + end else if (div_man[18]) begin //shift << by 5, subtract 5 from exponent. + div[22:0] = {div_man[17:0], 5'b0}; + div[30:23] = div_exp - 8'b00000101; + + end else if (div_man[17]) begin //shift << by 6, subtract 6 from exponent. + div[22:0] = {div_man[16:0], 6'b0}; + div[30:23] = div_exp - 8'b00000110; + + end else if (div_man[16]) begin //shift << by 7, subtract 7 from exponent. + div[22:0] = {div_man[15:0], 7'b0}; + div[30:23] = div_exp - 8'b00000111; + + end else if (div_man[15]) begin //shift << by 8, subtract 8 from exponent. + div[22:0] = {div_man[14:0], 8'b0}; + div[30:23] = div_exp - 8'b00001000; + + end else if (div_man[14]) begin //shift << by 9, subtract 9 from exponent. + div[22:0] = {div_man[13:0], 9'b0}; + div[30:23] = div_exp - 8'b00001001; + + end else if (div_man[13]) begin //shift << by 10, subtract 10 from exponent. + div[22:0] = {div_man[12:0], 10'b0}; + div[30:23] = div_exp - 8'b00001010; + + end else if (div_man[12]) begin //shift << by 11, subtract 11 from exponent. + div[22:0] = {div_man[11:0], 11'b0}; + div[30:23] = div_exp - 8'b00001011; + + end else if (div_man[11]) begin //shift << by 12, subtract 12 from exponent. + div[22:0] = {div_man[10:0], 12'b0}; + div[30:23] = div_exp - 8'b00001100; + + end else if (div_man[10]) begin //shift << by 13, subtract 13 from exponent. + div[22:0] = {div_man[9:0], 13'b0}; + div[30:23] = div_exp - 8'b00001101; + + end else if (div_man[9]) begin //shift << by 14, subtract 14 from exponent. + div[22:0] = {div_man[8:0], 14'b0}; + div[30:23] = div_exp - 8'b00001110; + + end else if (div_man[8]) begin //shift << by 15, subtract 15 from exponent. + div[22:0] = {div_man[7:0], 15'b0}; + div[30:23] = div_exp - 8'b00001111; + + end else if (div_man[7]) begin //shift << by 16, subtract 16 from exponent. + div[22:0] = {div_man[6:0], 16'b0}; + div[30:23] = div_exp - 8'b00010000; + + end else if (div_man[6]) begin //shift << by 17, subtract 17 from exponent. + div[22:0] = {div_man[5:0], 17'b0}; + div[30:23] = div_exp - 8'b00010001; + + end else if (div_man[5]) begin //shift << by 18, subtract 18 from exponent. + div[22:0] = {div_man[4:0], 18'b0}; + div[30:23] = div_exp - 8'b00010010; + + end else if (div_man[4]) begin //shift << by 19, subtract 19 from exponent. + div[22:0] = {div_man[3:0], 19'b0}; + div[30:23] = div_exp - 8'b00010011; + + end else if (div_man[3]) begin //shift << by 20, subtract 20 from exponent. + div[22:0] = {div_man[2:0], 20'b0}; + div[30:23] = div_exp - 8'b00010100; + + end else if (div_man[2]) begin //shift << by 21, subtract 21 from exponent. + div[22:0] = {div_man[1:0], 21'b0}; + div[30:23] = div_exp - 8'b00010101; + + end else if (div_man[1]) begin //shift << by 22, subtract 22 from exponent. + div[22:0] = {div_man[0:0], 22'b0}; + div[30:23] = div_exp - 8'b00010110; + + end else /*if (div_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + div[22:0] = 23'b0; + div[30:23] = div_exp - 8'b00010111; + end + + end + +endmodule + + + + + +module div_24b(numer, denom, res); + //input clock; + + input [23:0]numer; + input [23:0]denom; + output [23:0]res; + reg [23:0]res; + + //Pad with 23 zeros. + wire [46:0]denom_pad; + wire [46:0]numer23; + reg [46:0]numer22; + reg [46:0]numer21; + reg [46:0]numer20; + reg [46:0]numer19; + reg [46:0]numer18; + reg [46:0]numer17; + reg [46:0]numer16; + reg [46:0]numer15; + reg [46:0]numer14; + reg [46:0]numer13; + reg [46:0]numer12; + reg [46:0]numer11; + reg [46:0]numer10; + reg [46:0]numer9; + reg [46:0]numer8; + reg [46:0]numer7; + reg [46:0]numer6; + reg [46:0]numer5; + reg [46:0]numer4; + reg [46:0]numer3; + reg [46:0]numer2; + reg [46:0]numer1; + reg [46:0]numer0; + + //always @ (posedge clock) begin + assign denom_pad = {23'b0, denom}; + assign numer23 = {numer, 23'b0}; + // end + + //res[23] + always @ (denom_pad or numer23) begin + + if (denom_pad[23:0] <= numer23[46:23]) begin + res[23] = 1'b1; + numer22 = {numer23[46:23] - denom_pad[23:0], 23'b0}; + end else begin + res[23] = 1'b0; + numer22 = numer23; + end + + if (denom_pad[24:0] <= numer22[46:22]) begin + res[22] = 1'b1; + numer21 = {numer22[46:22] - denom_pad[24:0], 22'b0}; + end else begin + res[22] = 1'b0; + numer21 = numer22; + end + + if (denom_pad[25:0] <= numer21[46:21]) begin + res[21] = 1'b1; + numer20 = {numer21[46:21] - denom_pad[25:0], 21'b0}; + end else begin + res[21] = 1'b0; + numer20 = numer21; + end + + if (denom_pad[26:0] <= numer20[46:20]) begin + res[20] = 1'b1; + numer19 = {numer20[46:20] - denom_pad[26:0], 20'b0}; + end else begin + res[20] = 1'b0; + numer19 = numer20; + end + + if (denom_pad[27:0] <= numer19[46:19]) begin + res[19] = 1'b1; + numer18 = {numer19[46:19] - denom_pad[27:0], 19'b0}; + end else begin + res[19] = 1'b0; + numer18 = numer19; + end + + if (denom_pad[28:0] <= numer18[46:18]) begin + res[18] = 1'b1; + numer17 = {numer18[46:18] - denom_pad[28:0], 18'b0}; + end else begin + res[18] = 1'b0; + numer17 = numer18; + end + + if (denom_pad[29:0] <= numer17[46:17]) begin + res[17] = 1'b1; + numer16 = {numer17[46:17] - denom_pad[29:0], 17'b0}; + end else begin + res[17] = 1'b0; + numer16 = numer17; + end + + if (denom_pad[30:0] <= numer16[46:16]) begin + res[16] = 1'b1; + numer15 = {numer16[46:16] - denom_pad[30:0], 16'b0}; + end else begin + res[16] = 1'b0; + numer15 = numer16; + end + + if (denom_pad[31:0] <= numer15[46:15]) begin + res[15] = 1'b1; + numer14 = {numer15[46:15] - denom_pad[31:0], 15'b0}; + end else begin + res[15] = 1'b0; + numer14 = numer15; + end + + if (denom_pad[32:0] <= numer14[46:14]) begin + res[14] = 1'b1; + numer13 = {numer14[46:14] - denom_pad[32:0], 14'b0}; + end else begin + res[14] = 1'b0; + numer13 = numer14; + end + + if (denom_pad[33:0] <= numer13[46:13]) begin + res[13] = 1'b1; + numer12 = {numer13[46:13] - denom_pad[33:0], 13'b0}; + end else begin + res[13] = 1'b0; + numer12 = numer13; + end + + if (denom_pad[34:0] <= numer12[46:12]) begin + res[12] = 1'b1; + numer11 = {numer12[46:12] - denom_pad[34:0], 12'b0}; + end else begin + res[12] = 1'b0; + numer11 = numer12; + end + + if (denom_pad[35:0] <= numer11[46:11]) begin + res[11] = 1'b1; + numer10 = {numer11[46:11] - denom_pad[35:0], 11'b0}; + end else begin + res[11] = 1'b0; + numer10 = numer11; + end + + if (denom_pad[36:0] <= numer10[46:10]) begin + res[10] = 1'b1; + numer9 = {numer10[46:10] - denom_pad[36:0], 10'b0}; + end else begin + res[10] = 1'b0; + numer9 = numer10; + end + + if (denom_pad[37:0] <= numer9[46:9]) begin + res[9] = 1'b1; + numer8 = {numer9[46:9] - denom_pad[37:0], 9'b0}; + end else begin + res[9] = 1'b0; + numer8 = numer9; + end + + if (denom_pad[38:0] <= numer8[46:8]) begin + res[8] = 1'b1; + numer7 = {numer8[46:8] - denom_pad[38:0], 8'b0}; + end else begin + res[8] = 1'b0; + numer7 = numer8; + end + + if (denom_pad[39:0] <= numer7[46:7]) begin + res[7] = 1'b1; + numer6 = {numer7[46:7] - denom_pad[39:0], 7'b0}; + end else begin + res[7] = 1'b0; + numer6 = numer7; + end + + if (denom_pad[40:0] <= numer6[46:6]) begin + res[6] = 1'b1; + numer5 = {numer6[46:6] - denom_pad[40:0], 6'b0}; + end else begin + res[6] = 1'b0; + numer5 = numer6; + end + + if (denom_pad[41:0] <= numer5[46:5]) begin + res[5] = 1'b1; + numer4 = {numer5[46:5] - denom_pad[41:0], 5'b0}; + end else begin + res[5] = 1'b0; + numer4 = numer5; + end + + if (denom_pad[42:0] <= numer4[46:4]) begin + res[4] = 1'b1; + numer3 = {numer4[46:4] - denom_pad[42:0], 4'b0}; + end else begin + res[4] = 1'b0; + numer3 = numer4; + end + + if (denom_pad[43:0] <= numer3[46:3]) begin + res[3] = 1'b1; + numer2 = {numer3[46:3] - denom_pad[43:0], 3'b0}; + end else begin + res[3] = 1'b0; + numer2 = numer3; + end + + if (denom_pad[44:0] <= numer2[46:2]) begin + res[2] = 1'b1; + numer1 = {numer2[46:2] - denom_pad[44:0], 2'b0}; + end else begin + res[2] = 1'b0; + numer1 = numer2; + end + + if (denom_pad[45:0] <= numer1[46:1]) begin + res[1] = 1'b1; + numer0 = {numer1[46:1] - denom_pad[45:0], 1'b0}; + end else begin + res[1] = 1'b0; + numer0 = numer1; + end + + if (denom_pad <= numer0) begin + res[0] = 1'b1; + end else begin + res[0] = 1'b0; + end + + end + +endmodule + + +////////////////////////////////////////////// +// +// constants.v +// +// Version 1.3 +// Written 7/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 8/20/01 Mark_Phair@hmc.edu and Justin_Schauer@hmc.edu +// +// A set of constants for a parameterized floating point multiplier and adder. +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// FREE VARIABLES +////////////////////////////////////////////// + +// Widths of Fields +`define WEXP 8 +`define WSIG 23 +`define WFLAG 5 +`define WCONTROL 5 + +// output flag select (flags[x]) +`define DIVZERO 0 +`define INVALID 1 +`define INEXACT 2 +`define OVERFLOW 3 +`define UNDERFLOW 4 + +////////////////////////////////////////////// +// DEPENDENT VARIABLES +////////////////////////////////////////////// + +`define WIDTH 32 //(`WEXP + `WSIG + 1) +`define PRODWIDTH 48 //(2 * (`WSIG + 1)) +`define SHIFTWIDTH 96 //(2 * `PRODWIDTH)) +`define WPRENORM 24 // `WSIG + 1 +`define WEXPSUM 10 // `WEXP + 2 +`define BIAS 127 // (2^(`WEXP)) - 1 +`define WSIGMINUS1 22 // `WSIG - 1, used for rounding +`define WSHIFTAMT 5 // log2(`WSIG + 1) rounded up + +// for trapped over/underflow +`define UNDERBIAS 192 // 3 * 2 ^ (`WEXP -2) +`define OVERBIAS -192 // -`UNDERBIAS + +// specialized constants for fpadd +`define EXTRASIG 25 // `WSIG+2 this is the amount of precision needed so no + // subtraction errors occur +`define SHIFT 5 // # bits the max alignment shift will fit in (log2(`WSIG+2) + // rounded up to nearest int) +`define MAX_EXP 8'b11111110 // the maximum non-infinite exponent, + // `WEXP bits, the most significant + // `WEXP-1 bits are 1, the LSB is 0 +`define INF_EXP 8'b11111111 // Infinity exponent, `WEXP bits, all 1 +// Max significand, `WSIG bits, all 1 +`define MAX_SIG 23'b11111111111111111111111 +`define WEXP_0 8'b0 // Exponent equals `WEXP'b0 +`define WEXP_1 8'b1 // Exponent equals one `WEXP'b1 +`define WSIG_0 23'b0 // Significand equals zero `WSIG'b0 +`define WSIG_1 23'b1 // Significand equals one `WSIG'b1 +`define EXTRASIG_0 25'b0 // All result bits for adder zero `EXTRASIG'b0 + +// specialized constants for fpmul +`define MAXSHIFT 24 // `WSIG + 1 + +// GENERAL SPECIAL NUMBERS - Exp + Significand of special numbers +// plain NaN `WIDTH-1, all 1 +`define CONSTNAN {9'b111111111,22'b0} +// zero `WIDTH-1, all 0 +`define CONSTZERO 31'b0 +// infinity `WEXP all 1, `WSIG all 0 +`define CONSTINFINITY {8'b11111111, 23'b0} +// largest number maximum exponent(all 1's - 1) and maximum significand (all 1's) +`define CONSTLARGEST {`MAX_EXP, `MAX_SIG} +`define PRESHIFTZEROS 48'b0 // `PRODWIDTH'b0 + +////////////////////////////////////////////// +// +// fpmul.v +// +// Version 1.6 +// Written 07/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 08/20/01 Mark_Phair@hmc.edu +// +// A parameterized floating point multiplier. +// +// BLOCK DESCRIPTIONS +// +// preprocess - general processing, such as zero detection, computing sign, NaN +// +// prenorm - normalize denorms +// +// exponent - sum the exponents, check for tininess before rounding +// +// multiply - multiply the mantissae +// +// special - calculate special cases, such as NaN and infinities +// +// shift - shift the sig and exp if nesc. +// +// round - round product +// +// normalize - normalizes the result if appropriate (i.e. not a denormalized #) +// +// flag - general flag processing +// +// assemble - assemble results +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// Includes +////////////////////////////////////////////// + + + +////////////////////////////////////////////// +// fpmul module +////////////////////////////////////////////// + +module fpmul(clk, a, b, y_out, control, flags) ; + + input clk; + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-1:0] y_out; // floating-point product + reg [`WIDTH-1:0] y_out; + input [1:0] control; // control including rounding mode + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + //intermediate y_out + wire [`WIDTH-1:0]y; + + // internal signals + wire multsign; // sign of product + wire specialsign; // sign of special + + wire [`WSIG:0] norma; // normal-form mantissa a, 1 bit larger to hold leading 1 + wire [`WSIG:0] normb; // normal-form mantissa b, 1 bit larger to hold leading 1 + + wire [`WEXPSUM-1:0] expa, expb; // the two exponents, after prenormalization + wire [`WEXPSUM-1:0] expsum; // sum of exponents (two's complement) + wire [`WEXPSUM-1:0] shiftexp; // shifted exponent + wire [`WEXP-1:0] roundexp; // rounded, correct exponent + + wire [`PRODWIDTH-1:0] prod; // product of mantissae + wire [`PRODWIDTH-1:0] normalized; // Normalized product + wire [`SHIFTWIDTH-1:0] shiftprod; // shifted product + wire [`WSIG-1:0] roundprod; // rounded product + wire [`WIDTH-2:0] special; // special case exponent and product + + wire twoormore; // product is outside range [1,2) + wire zero; // zero detected + wire infinity; // infinity detected + wire aisnan; // NaN detected in A + wire bisnan; // NaN detected in B + wire aisdenorm; // Denormalized number detected in A + wire bisdenorm; // Denormalized number detected in B + wire specialcase; // This is a special case + wire specialsigncase; // Use the special case sign + wire roundoverflow; // overflow in rounding, need to add 1 to exponent + wire invalid; // invalid operation + wire overflow; // exponent result too high, standard overflow + wire inexact; // inexact flag + wire shiftloss; // lost digits due to a shift, result inaccurate + wire [1:0] roundmode; // rounding mode information extracted from control field + wire tiny; // Result is tiny (denormalized #) after multiplication + wire stilltiny; // Result is tiny (denormalized #) after rounding + wire denormround; // rounding occured only because the initial result was + // a denormalized number. This is used to determine + // underflow in cases of denormalized numbers rounding + // up to normalized numbers + + preprocess preprocesser(a, b, zero, aisnan, bisnan, + aisdenorm, bisdenorm, infinity, + control, roundmode, sign); + + special specialer(a, b, special, specialsign, zero, + aisnan, bisnan, + infinity, invalid, + specialcase, specialsigncase); + + prenorm prenormer(a[`WIDTH-2:0], b[`WIDTH-2:0], norma, normb, expa, expb, aisdenorm, bisdenorm); + + multiply_a multiplier(norma, normb, prod, twoormore); + + exponent exponenter(expa, expb, expsum, twoormore, tiny); + + normalize normalizer(prod, normalized, tiny, twoormore); + + shift shifter(normalized, expsum, shiftprod, + shiftexp, shiftloss); + + round rounder(shiftprod, shiftexp, shiftloss, + roundprod, roundexp, + roundmode, sign, tiny, inexact, + overflow, stilltiny, denormround); + + // *** To check for tininess before rounding, use tiny + // To check after rounding, use stilltiny + // *** for underflow detect: + // To check for inexact result use (inexact | (shiftloss & stilltiny)), + // To check for denormilization loss use (shiftloss & stilltiny) +// flag flager(invalid, overflow, inexact | shiftloss, +// shiftloss | inexact, +// /* tiny */ (stilltiny | (tiny & denormround)), +// specialcase, flags); + + //ODIN cannot have operations in module instantiations. + wire inexact_or_shiftloss; + assign inexact_or_shiftloss = inexact | shiftloss; + wire shiftloss_or_inexact; + assign shiftloss_or_inexact = shiftloss | inexact; + wire still_tiny_or_tiny_and_denormround; + assign still_tiny_or_tiny_and_denormround = stilltiny | (tiny & denormround); + + flag flager(invalid, overflow, inexact_or_shiftloss, + shiftloss_or_inexact, + /* tiny */ stilltiny_or_tiny_and_denormround, + specialcase, flags); + + + assemble assembler(roundprod, special, y, + sign, specialsign, roundexp, + specialcase, specialsigncase, + roundmode, flags[`OVERFLOW]); + + always @ (posedge clk) begin + y_out <= y; + end + +endmodule + + + + +module preprocess(a, b, zero, aisnan, bisnan, aisdenorm, bisdenorm, infinity, control, roundmode, sign); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output zero; // is there a zero? + //input [`WCONTROL-1:0] control; // control field + input [1:0] control; //the rest is unused, not necessary for ODIN. + output [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + output aisnan; // NaN detected in A + output bisnan; // NaN detected in B + output aisdenorm; // denormalized number detected in A + output bisdenorm; // denormalized number detected in B + output infinity; // infinity detected in A + output sign; // sign of product + + // internal signals + wire signa, signb; // sign of a and b + wire [`WEXP-1:0] expa, expb; // the exponents of a and b + wire [`WSIG-1:0] siga, sigb; // the significands of a and b + wire aexpfull; // the exponent of a is all 1's + wire bexpfull; // the exponent of b is all 1's + wire aexpzero; // the exponent of a is all 0's + wire bexpzero; // the exponent of b is all 0's + wire asigzero; // the significand of a is all 0's + wire bsigzero; // the significand of b is all 0's + + // Sign calculation + assign signa = a[`WIDTH-1]; + assign signb = b[`WIDTH-1]; + assign sign = signa ^ signb; + + // Significand calcuations + + assign siga = a[`WSIG-1:0]; + assign sigb = b[`WSIG-1:0]; + // Are the significands all 0's? + assign asigzero = ~|siga; + assign bsigzero = ~|sigb; + + // Exponent calculations + + assign expa = a[`WIDTH-2:`WIDTH-`WEXP-1]; + assign expb = b[`WIDTH-2:`WIDTH-`WEXP-1]; + // Are the exponents all 0's? + assign aexpzero = ~|expa; + assign bexpzero = ~|expb; + // Are the exponents all 1's? + assign aexpfull = &expa; + assign bexpfull = &expb; + + // General calculations + + // Zero Detect + assign zero = (aexpzero & asigzero) | (bexpzero & bsigzero); + + // NaN detect + assign aisnan = aexpfull & ~asigzero; + assign bisnan = bexpfull & ~bsigzero; + + // Infinity detect + assign infinity = (aexpfull & asigzero) | (bexpfull & bsigzero); + + // Denorm detect + assign aisdenorm = aexpzero & ~asigzero; + assign bisdenorm = bexpzero & ~bsigzero; + + // Round mode extraction + assign roundmode = control[1:0]; + +endmodule + +module special (a, b, special, specialsign, + zero, aisnan, bisnan, infinity, + invalid, specialcase, specialsigncase); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-2:0] special; // special case output, exp + sig + output specialsign; // the special-case sign + input zero; // is there a zero? + input aisnan; // NaN detected in A + input bisnan; // NaN detected in B + input infinity; // infinity detected + output invalid; // invalid operation + output specialcase; // this is a special case + output specialsigncase; // Use the special sign + + // internal signals + wire infandzero; // infinity and zero detected + wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input, + // and dont care if neither a nor b are NaNs + wire aishighernan; // a is the higher NaN + + assign infandzero = (infinity & zero); + + //#######SPECIAL ASSIGNMENT###### + // #######return higher NaN########## + // Use this block if you want to return the higher of two NaNs + + assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan)); + + assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0]; + + assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) : + (zero ? + (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)); + // #######return first NaN########## + // Use this block to return the first NaN encountered +// assign special = aisnan ? (a[`WIDTH-2:0]) : +// (bisnan ? (b[`WIDTH-2:0]) : +// (zero ? +// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY))); + //######END SPECIAL ASSIGNMENT####### + + assign specialcase = zero | aisnan | bisnan | infinity; + + assign invalid = infandzero; //*** need to include something about signaling NaNs here + + // dont need to check if b is NaN, if it defaults to that point, and b isnt NAN + // then it wont be used anyway + assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]); + + assign specialsigncase = infandzero | aisnan | bisnan; + +endmodule + +module prenorm(a, b, norma, normb, modexpa, modexpb, aisdenorm, bisdenorm); + + //input [`WIDTH-1:0] a, b; // the input floating point numbers + input [`WIDTH-2:0] a, b; //We don't need bit 31 here, unused in ODIN. + output [`WSIG:0] norma, normb; // the mantissae in normal form + output [`WEXPSUM-1:0] modexpa, modexpb; // the output exponents, larger to accomodate + // two's complement form + input aisdenorm; // a is a denormalized number + input bisdenorm; // b is a denormalized nubmer + + // internal signals + wire [`WEXPSUM-1:0] expa, expb; // exponents in two's complement form + // are negative if shifted for a + // denormalized number + wire [`SHIFT-1:0] shifta, shiftb; // the shift amounts + reg [`WSIG:0] shifteda, shiftedb; // the shifted significands, used to be wire, changed for ODIN. + + // pull out the exponents + assign expa = a[`WIDTH-2:`WIDTH-1-`WEXP]; + assign expb = b[`WIDTH-2:`WIDTH-1-`WEXP]; + + // when breaking appart for paramaterizing: + // ### RUN ./prenormshift.pl wsig_in ### +assign shifta = a[23 - 1] ? 1 : + a[23 - 2] ? 2 : + a[23 - 3] ? 3 : + a[23 - 4] ? 4 : + a[23 - 5] ? 5 : + a[23 - 6] ? 6 : + a[23 - 7] ? 7 : + a[23 - 8] ? 8 : + a[23 - 9] ? 9 : + a[23 - 10] ? 10 : + a[23 - 11] ? 11 : + a[23 - 12] ? 12 : + a[23 - 13] ? 13 : + a[23 - 14] ? 14 : + a[23 - 15] ? 15 : + a[23 - 16] ? 16 : + a[23 - 17] ? 17 : + a[23 - 18] ? 18 : + a[23 - 19] ? 19 : + a[23 - 20] ? 20 : + a[23 - 21] ? 21 : + a[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + +assign shiftb = b[23 - 1] ? 1 : + b[23 - 2] ? 2 : + b[23 - 3] ? 3 : + b[23 - 4] ? 4 : + b[23 - 5] ? 5 : + b[23 - 6] ? 6 : + b[23 - 7] ? 7 : + b[23 - 8] ? 8 : + b[23 - 9] ? 9 : + b[23 - 10] ? 10 : + b[23 - 11] ? 11 : + b[23 - 12] ? 12 : + b[23 - 13] ? 13 : + b[23 - 14] ? 14 : + b[23 - 15] ? 15 : + b[23 - 16] ? 16 : + b[23 - 17] ? 17 : + b[23 - 18] ? 18 : + b[23 - 19] ? 19 : + b[23 - 20] ? 20 : + b[23 - 21] ? 21 : + b[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + + + + // If number is a denorm, the exponent must be + // decremented by the shift amount + assign modexpa = aisdenorm ? 1 - shifta : expa; + assign modexpb = bisdenorm ? 1 - shiftb : expb; + + // If number is denorm, shift the significand the appropriate amount +// assign shifteda = a[`WSIG-1:0] << shifta; + //Must have constant shifts for ODIN + always @ (shifta or a) begin + case (shifta) + 5'b00001: begin + shifteda = a[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shifteda = a[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shifteda = a[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shifteda = a[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shifteda = a[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shifteda = a[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shifteda = a[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shifteda = a[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shifteda = a[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shifteda = a[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shifteda = a[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shifteda = a[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shifteda = a[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shifteda = a[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shifteda = a[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shifteda = a[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shifteda = a[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shifteda = a[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shifteda = a[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shifteda = a[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shifteda = a[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shifteda = a[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shifteda = a[`WSIG-1:0] << 5'b10111; + end + + default: begin //Won't be higher than 23. + shifteda = a[`WSIG-1:0]; + end + endcase + end + + assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; + + // assign shiftedb = b[`WSIG-1:0] << shiftb; + always @ (shiftb or b) begin + case (shiftb) + 5'b00001: begin + shiftedb = b[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shiftedb = b[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shiftedb = b[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shiftedb = b[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shiftedb = b[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shiftedb = b[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shiftedb = b[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shiftedb = b[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shiftedb = b[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shiftedb = b[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shiftedb = b[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shiftedb = b[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shiftedb = b[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shiftedb = b[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shiftedb = b[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shiftedb = b[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shiftedb = b[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shiftedb = b[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shiftedb = b[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shiftedb = b[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shiftedb = b[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shiftedb = b[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shiftedb = b[`WSIG-1:0] << 5'b10111; + end + + default: begin // Won't be higher than 23. + shiftedb = b[`WSIG-1:0]; + end + endcase + end + + + assign normb = bisdenorm ? shiftedb : {1'b1, b[`WSIG-1:0]}; + +endmodule + +module multiply_a (norma, normb, prod, twoormore); + + input [`WSIG:0] norma, normb; // normalized mantissae + + output [`PRODWIDTH-1:0] prod; // product of mantissae + output twoormore; // Product overflowed range [1,2) + + // multiplier array + // (*** need a more effecient multiplier, + // designware might work, though) + assign prod = norma * normb; + + // did the multiply overflow the range [1,2)? + assign twoormore = prod[`PRODWIDTH-1]; + +endmodule + + + +module exponent(expa, expb, expsum, twoormore, tiny); + + input [`WEXPSUM-1:0] expa, expb; // the input exponents in 2's complement form + // to accomodate denorms that have been + // prenormalized + input twoormore; // product is outside range [1,2) + + output [`WEXPSUM-1:0] expsum; // the sum of the exponents + output tiny; // Result is tiny (denormalized #) + + // Sum the exponents, subtract the bias + // and add 1 (twoormore) if multiply went out of [1,2) range + assign expsum = expa + expb - `BIAS + twoormore; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is in 2's-complement form, + // it is negative if the first bit is 1, and zero if + // all the bits are zero + assign tiny = ~|expsum[`WEXPSUM-2:0] | expsum[`WEXPSUM-1]; + + +endmodule + + + + +module normalize(prod, normalized, tiny, twoormore); + + // external signals + input [`PRODWIDTH-1:0] prod; // Product of multiplication + output [`PRODWIDTH-1:0] normalized; // Normalized product + input tiny; // Result is tiny (denormalized #) + input twoormore; // Product overflowed range [1,2) + + // normalize product if appropriate + // There are three possible cases here: + // 1) tiny and prod overfl. [1,2) -> take the whole prod, including the leading 1 + // 2) tiny or prod overfl. [1,2) -> dont take the first bit. its zero if its tiny, + // and it's the implied 1 if its not + // 3) neither tiny nor prod overfl.-> dont take the first 2 bits, the 2nd one is the + // implied 1 + assign normalized = (tiny & twoormore) ? prod[`PRODWIDTH-1:0] : + ((tiny ^ twoormore) ? {prod[`PRODWIDTH-2:0],1'b0} : + {prod[`PRODWIDTH-3:0],2'b0}); + +endmodule + +module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); + + // external signals + input [`PRODWIDTH-1:0] normalized; // normalized product of mantissae + input [`WEXPSUM-1:0] selectedexp; // sum of exponents + output [`SHIFTWIDTH-1:0] shiftprod; // shifted and normalized product + output [`WEXPSUM-1:0] shiftexp; // shifted exponent + output shiftloss; // loss of accuaracy due to shifting + + // internal signals + wire [`WEXPSUM-1:0] roundedexp; // selected exponent + 1 if rounding caused overflow +// wire negexp; // exponent is negative + wire [`WEXPSUM-1:0] shiftamt; // theoretical amount to shift product by + wire [`WSHIFTAMT-1:0] actualshiftamt; // actual amount to shift product by + wire tozero; // need more shifts than possible with width of significand + wire doshift; // only shift if value is nonnegative + wire [`SHIFTWIDTH-1:0] preshift; // value before shifting, with more room to ensure lossless shifting + reg [`SHIFTWIDTH-1:0] postshift; // value after shifting, with more room to ensure lossless shifting, used to be wire, changed for ODIN. + + // set up value for shifting + assign preshift = {normalized, `PRESHIFTZEROS}; + + // determine shift amount + assign shiftamt = -selectedexp; + + // make sure shift amount is nonnegative + // If the exponent is negative, the shift amount should + // come out positive, otherwise there shouldn't be any + // shifting to be done + assign doshift = ~shiftamt[`WEXPSUM-1]; + + // Determine if the result must be shifted more than + // will show up in the significand, even if it rounds up + assign tozero = doshift & (shiftamt > `MAXSHIFT); + + // If the shift is big enough to shift all the bits out of the final significand, + // then it stops being relevent how much it has been shifted. + assign actualshiftamt = tozero ? `MAXSHIFT : shiftamt[`WSHIFTAMT-1:0]; + + // shift significand + //assign postshift = preshift >> actualshiftamt; + //We can only have constant shifts for ODIN: + always @ (actualshiftamt or preshift) begin + case (actualshiftamt) + 5'b00001: begin + postshift = preshift >> 5'b00001; + end + + 5'b00010: begin + postshift = preshift >> 5'b00010; + end + + 5'b00011: begin + postshift = preshift >> 5'b00011; + end + + 5'b00100: begin + postshift = preshift >> 5'b00100; + end + + 5'b00101: begin + postshift = preshift >> 5'b00101; + end + + 5'b00110: begin + postshift = preshift >> 5'b00110; + end + + 5'b00111: begin + postshift = preshift >> 5'b00111; + end + + 5'b01000: begin + postshift = preshift >> 5'b01000; + end + + 5'b01001: begin + postshift = preshift >> 5'b01001; + end + + 5'b01010: begin + postshift = preshift >> 5'b01010; + end + + 5'b01011: begin + postshift = preshift >> 5'b01011; + end + + 5'b01100: begin + postshift = preshift >> 5'b01100; + end + + 5'b01101: begin + postshift = preshift >> 5'b01101; + end + + 5'b01110: begin + postshift = preshift >> 5'b01110; + end + + 5'b01111: begin + postshift = preshift >> 5'b01111; + end + + 5'b10000: begin + postshift = preshift >> 5'b10000; + end + + 5'b10001: begin + postshift = preshift >> 5'b10001; + end + + 5'b10010: begin + postshift = preshift >> 5'b10010; + end + + 5'b10011: begin + postshift = preshift >> 5'b10011; + end + + 5'b10100: begin + postshift = preshift >> 5'b10100; + end + + 5'b10101: begin + postshift = preshift >> 5'b10101; + end + + 5'b10110: begin + postshift = preshift >> 5'b10110; + end + + 5'b10111: begin + postshift = preshift >> 5'b10111; + end + + 5'b11000: begin + postshift = preshift >> 5'b11000; + end + + 5'b11001: begin + postshift = preshift >> 5'b11001; + end + + 5'b11010: begin + postshift = preshift >> 5'b11010; + end + + 5'b11011: begin + postshift = preshift >> 5'b11011; + end + + 5'b11100: begin + postshift = preshift >> 5'b11100; + end + + 5'b11101: begin + postshift = preshift >> 5'b11101; + end + + 5'b11110: begin + postshift = preshift >> 5'b11110; + end + + 5'b11111: begin + postshift = preshift >> 5'b11111; + end + + default: begin + postshift = preshift; + end + endcase + end + + + // assign appropriate significand + assign shiftprod = doshift ? postshift : preshift; + + // determine if any bits were lost from the shift + //assign shiftloss = tozero | (negexp & |postshift[`WSIG-1:0]); + assign shiftloss = tozero | (doshift & |postshift[`SHIFTWIDTH-`PRODWIDTH-1:0]); + + // assign appropriate exponent + assign shiftexp = doshift ? 0 : selectedexp; + +endmodule + + + +module round(shiftprod, shiftexp, shiftloss, roundprod, roundexp, roundmode, + sign, tiny, inexact, overflow, stilltiny, denormround); + + // external signals + input [`SHIFTWIDTH-1:0] shiftprod; // normalized and shifted product of mantissae + input [`WEXPSUM-1:0] shiftexp; // shifted exponent + input shiftloss; // bits were lost in the shifting process + output [`WSIG-1:0] roundprod; // rounded floating-point product + output [`WEXP-1:0] roundexp; // rounded exponent + input [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + input sign; // sign bit for rounding mode direction + input tiny; // denormalized number after rounding + output inexact; // rounding occured + output overflow; // overflow occured + output stilltiny; // Result is tiny (denormalized #) after rounding + output denormround; // result was rounded only because it was a denormalized number + + // internal signals + wire roundzero; // rounding towards zero + wire roundinf; // rounding towards infinity + wire stickybit; // there one or more 1 bits in the LS bits + wire denormsticky; // sticky bit if this weren't a denorm + wire [`WSIG-1:0] MSBits; // most significant bits + wire [`WSIG:0] MSBitsplus1; // most significant bits plus 1 + // for rounding purposes. needs to be one + // bit bigger for overflow + wire [1:0] roundbits; // bits used to compute rounding decision + wire rounddecision; // round up + wire roundoverflow; // rounding overflow occured + wire [`WEXPSUM-1:0] tempexp; // exponent after rounding + + //reduce round mode to three modes + // dont need round nearest, it is implied + // by roundzero and roundinf being false + //assign roundnearest = ~&roundmode; +// assign roundzero = &roundmode || (^roundmode && (roundmode[0] || sign)); + assign roundzero = (~roundmode[1] & roundmode[0]) | (roundmode[1] & (roundmode[0] ^ sign)); + assign roundinf = roundmode[1] & ~(sign ^ roundmode[0]); + + // pull out the most significant bits for the product + assign MSBits = shiftprod[`SHIFTWIDTH-1:`SHIFTWIDTH-`WSIG]; + + // add a 1 to the end of MSBits for round up + assign MSBitsplus1 = MSBits + 1; + + // pull out the last of the most significant bits + // and the first of the least significant bits + // to use for calculating the rounding decision + assign roundbits[1:0] = shiftprod[`SHIFTWIDTH-`WSIG:`SHIFTWIDTH-`WSIG-1]; + + // calculate the sticky bit. Are any of the least significant bits 1? + // also: was anything lost while shifting? + // *** Optimization: some of these bits are already checked from the shiftloss *** + // *** Optimization: stickybit can be calculated from denormsticky + // with only 1 more gate, instead of duplication of effort *** + assign stickybit = |shiftprod[`SHIFTWIDTH-`WSIG-2:0] | shiftloss; + assign denormsticky = |shiftprod[`SHIFTWIDTH-`WSIG-3:0] | shiftloss; + + // Compute rounding decision + assign rounddecision = ~roundzero & ( (roundbits[0] & (roundinf | roundbits[1])) + | (stickybit & (roundinf | roundbits[0])) + ); + + // Was this only rounded because it is a denorm? + assign denormround = tiny & rounddecision & ~denormsticky & roundbits[0]; + + // detect rounding overflow. it only overflows if: + // 1) the top bit of MSBitsplus1 is 1 + // 2) it decides to round up + assign roundoverflow = MSBitsplus1[`WSIG] & rounddecision; + + // assign significand (and postnormalize) + // rounddecision decides whether to use msbits+1 or msbits. + // if using msbits+1 and there is an rounding overflow (i.e. result=2), + // then should return 1 instead + assign roundprod = rounddecision ? + (roundoverflow ? 0 : + MSBitsplus1[`WSIG-1:0]) : + MSBits; + + // detect inexact + assign inexact = rounddecision | stickybit | roundbits[0]; + + // compensate for a rounding overflow + assign tempexp = roundoverflow + shiftexp; + + // check for overflow in exponent + // overflow occured if the number + // is too large to be represented, + // i.e. can't fit in `WEXP bits, or + // all `WEXP bits are 1's + assign overflow = &tempexp[`WEXP-1:0] | |tempexp[`WEXPSUM-1:`WEXP]; + + // two possible cases: + // 1) Overflow: then exponent doesnt matter, + // it will be changed to infinity anyway + // 2) not overflow: the leading bits will be 0 + assign roundexp = tempexp[`WEXP-1:0]; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is NOT in 2's-complement form, + // it is only less than one if its is zero, i.e. + // all the bits are 0 + assign stilltiny = ~|roundexp; + +endmodule + + +module flag (invalid, overflow, inexact, underflow, tiny, specialcase, flags); + + input invalid; // invalid operation + input overflow; // the result was too large + input inexact; // The result was rounded + input specialcase; // Using special result, shouldn't throw flags + input underflow; // Underflow detected + input tiny; // The result is tiny + + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + // flags + assign flags[`DIVZERO] = 1'b0; + assign flags[`INVALID] = invalid; + assign flags[`INEXACT] = ~specialcase & (inexact | underflow | overflow); + assign flags[`OVERFLOW] = ~specialcase & overflow; + assign flags[`UNDERFLOW] = tiny; //~specialcase & tiny & underflow & ~overflow; + +endmodule + +module assemble(roundprod, special, y, sign, specialsign, + shiftexp, specialcase, specialsigncase, + roundmode, overflow); + + // external signals + input [`WSIG-1:0] roundprod; // shifted, rounded and normalized + // product of mantissae + input [`WIDTH-2:0] special; // special case product + exponent + output [`WIDTH-1:0] y; // floating-point product + input sign; // sign of product (+ = 0, - = 1) + input specialsign; // special case sign + input [`WEXP-1:0] shiftexp; // shifted exponent + input specialcase; // this is a special case + input specialsigncase; // use the special case sign + input [1:0] roundmode; // rounding mode information extracted from control field + input overflow; // overflow detected + + // internal signals + wire [`WIDTH-2:0] rounded; // final product + exponent + wire [`WIDTH-2:0] overflowvalue; // product + exponent for overflow condition + wire undenormed; // the result was denormalized before rounding, but rounding + // caused it to become a small normalized number. + + // SET UP ROUNDED PRODUCT + EXPONENT + + // assign significand + assign rounded[`WSIG-1:0] = roundprod; + + // assign exponent + assign rounded[`WIDTH-2:`WIDTH-`WEXP-1] = shiftexp; + + // SET UP OVERFLOW CONDITION + assign overflowvalue[`WIDTH-2:0] = roundmode[1] ? + (sign ^ roundmode[0] ? `CONSTLARGEST : `CONSTINFINITY) : + (roundmode[0] ? `CONSTLARGEST: `CONSTINFINITY); + + // FINAL PRODUCT ASSIGN + + // assign sign + assign y[`WIDTH-1] = specialsigncase ? specialsign : sign; + + // assign product vs special vs overflowed + assign y[`WIDTH-2:0] = specialcase ? special[`WIDTH-2:0] : + (overflow ? overflowvalue[`WIDTH-2:0] : + rounded[`WIDTH-2:0]); + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v b/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v new file mode 100755 index 000000000..c5d441b7c --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/LU64PEEng.v @@ -0,0 +1,6009 @@ +//auto-generated top.v +//top level module of LU factorization +//by Wei Zhang + +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 5'b01000 +`define DDRWIDTH 7'b0100000 +`define DDRNUMDQS 4'b0100 +`define DDRSIZEWIDTH 6'b011000 +`define BURSTLEN 3'b010 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define RAMWIDTH 13'b0100000000000 +`define RAMNUMBYTES 10'b0100000000 +`define RAMSIZEWIDTH 5'b01000 +`define TOPWIDTH 7'b0100000 +`define rFIFOINPUTWIDTH 8'b01000000 +`define wFIFOINPUTWIDTH 13'b0100000000000 +`define mFIFOWIDTH 6'b011100 +`define aFIFOWIDTH 5'b01000 + +module LU64PEEng (clk, //ref_clk, global_reset_n, + start, N, offset, done, + //mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, +burst_begin, +mem_local_be, +mem_local_read_req, +mem_local_size, +mem_local_wdata, +mem_local_write_req, +mem_local_rdata, +mem_local_rdata_valid, +mem_local_ready, +mem_local_wdata_req, +reset_n, +mem_local_addr +//Cong: dummy output +//a_junk, +//w_junk, +//m_junk, +//r_junk, +//Cong:dummy output +//junk_r, +//junk_r1, +//junk_r2, +//junk_r3, +//junk_top + ); + +input start; +input[`NWIDTH-1:0] N; +input[`DDRSIZEWIDTH-1:0] offset; +output done; +input clk; + +output burst_begin; +output [`MEMCONNUMBYTES-1:0] mem_local_be; +output mem_local_read_req; +output [`BURSTLEN-1:0] mem_local_size; +output [`MEMCONWIDTH-1:0] mem_local_wdata; +output mem_local_write_req; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +input [`MEMCONWIDTH-1:0] mem_local_rdata; +input mem_local_rdata_valid; +input mem_local_ready; +input reset_n; +input mem_local_wdata_req; +wire[`BLOCKWIDTH-1:0] m, n, loop; +wire[1:0] mode; +wire comp_start, comp_done; +wire dtu_write_req, dtu_read_req, dtu_ack, dtu_done; +wire [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +wire [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +wire [`BLOCKWIDTH-1:0] dtu_size; +wire left_sel; + +wire[`RAMWIDTH-1:0] curWriteDataMem, curReadDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnMem; +wire curWriteEnMem; +wire[`RAMWIDTH-1:0] leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +wire leftWriteEnMem; +wire curMemSel, leftMemSel; + +wire burst_begin; +wire [`MEMCONNUMBYTES-1:0] mem_local_be; +wire mem_local_read_req; +wire [`BURSTLEN-1:0] mem_local_size; +wire [`MEMCONWIDTH-1:0] mem_local_wdata; +wire mem_local_write_req; +wire [`MEMCONWIDTH-1:0] mem_local_rdata; +wire mem_local_rdata_valid; +wire mem_local_ready; +wire mem_local_wdata_req; +wire reset_n; +wire [`DDRSIZEWIDTH-1:0] mem_local_addr; + +wire[`RAMWIDTH-1:0] ram_write_data, ram_read_data; +wire[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +wire[`RAMNUMBYTES-1:0] ram_write_byte_en; +wire ram_write_en; + +MarshallerController MC (clk, start, done, N, offset, + comp_start, m, n, loop, mode, comp_done, curMemSel, leftMemSel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + +// block that computes the LU factorization, with answer stored back into ram block +LU compBlock (clk, comp_start, m, n, loop, mode, comp_done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel); + +DataTransferUnit DTU (.clk(clk), .dtu_write_req(dtu_write_req), .dtu_read_req(dtu_read_req), .dtu_mem_addr(dtu_mem_addr), .dtu_ram_addr(dtu_ram_addr), .dtu_size(dtu_size), .dtu_ack(dtu_ack), .dtu_done(dtu_done), + .ram_read_addr(ram_read_addr), .ram_read_data(ram_read_data), .ram_write_byte_en(ram_write_byte_en), .ram_write_data(ram_write_data), .ram_write_addr(ram_write_addr), .ram_write_en(ram_write_en), + .mem_rdata(mem_local_rdata), .mem_rdata_valid(mem_local_rdata_valid), .mem_ready(mem_local_ready), .mem_wdata_req(mem_local_wdata_req), .reset_n(reset_n), + .burst_begin(burst_begin), .mem_local_addr(mem_local_addr), .mem_be(mem_local_be), .mem_read_req(mem_local_read_req), .mem_size(mem_local_size), + .mem_wdata(mem_local_wdata), .mem_write_req(mem_local_write_req) + //Cong: dummy output + ); + +assign curReadAddrMem = ram_read_addr; +assign curWriteByteEnMem = ram_write_byte_en; +assign curWriteDataMem = ram_write_data; +assign curWriteAddrMem = ram_write_addr; +assign curWriteEnMem = ram_write_en && (left_sel == 0); +assign leftWriteByteEnMem = ram_write_byte_en; +assign leftWriteDataMem = ram_write_data; +assign leftWriteAddrMem = ram_write_addr; +assign leftWriteEnMem = ram_write_en && (left_sel == 1); +assign ram_read_data = curReadDataMem; +endmodule +`define BLOCKM 9'b010000000 +`define BLOCKN 9'b010000000 +`define BLOCKMDIVK 3'b010 +`define MEMBLOCKM 8'b01000000 +`define MEMBLOCKN 8'b01000000 +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define RAMSIZEWIDTH 5'b01000 +`define START 1'b0 //0 +`define SETUP 2'b01 //1 +`define FIRST 3'b010 //2 +`define MODE0_SETUP 3'b011 //3 +`define MODE0_WAIT 4'b0100 //4 +`define MODE0 4'b0101 //5 +`define MODE1_SETUP 4'b0110 //6 +`define MODE1_WAIT 4'b0111 //7 +`define MODE1 5'b01000 //8 +`define MODE2_SETUP 5'b01001 //9 +`define MODE2_WAIT 5'b01010 //10 +`define MODE2 5'b01011 //11 +`define MODE3_SETUP 5'b01100 //12 +`define MODE3_WAIT 5'b01101 //13 +`define MODE3 5'b01110 //14 +`define STALL 5'b01111 //15 +`define STALL_WAIT 6'b010000 //16 +`define WAIT 6'b010001 //17 +`define FINAL_WRITE 6'b010010 //18 +`define FINAL_WAIT 6'b010011 //19 +`define IDLE 6'b010100 //20 +`define LAST_SETUP 6'b010101 //21 +`define LAST_SETUP_WAIT 6'b010110 //22 +`define LAST 6'b010111 //23 +`define LAST_WAIT 6'b011000 //24 +`define MEM_IDLE 1'b0 //0 +`define MEM_WRITE 2'b01 //1 +`define MEM_WRITE_WAIT 3'b010 //2 +`define MEM_CHECK_DONE 3'b011 //3 +`define MEM_READ 4'b0100 //4 +`define MEM_READ_WAIT 4'b0101 //5 +`define MEM_DONE 4'b0110 //6 +`define MEM_WAIT_DONE 4'b0111 //7 + +module MarshallerController (clk, start, done, input_N, offset, + comp_start, block_m, block_n, loop, mode, comp_done, cur_mem_sel, left_mem_sel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + + +input clk; +input start; +output done; +input [`NWIDTH-1:0] input_N; +input [`DDRSIZEWIDTH-1:0] offset; + +// for computation section +output comp_start; +output [`BLOCKWIDTH-1:0] block_m, block_n, loop; +output [1:0] mode; +input comp_done; +output cur_mem_sel, left_mem_sel; + +// for data marshaller section +output dtu_write_req, dtu_read_req; +output [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +output [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +output [`BLOCKWIDTH-1:0] dtu_size; +input dtu_ack, dtu_done; +output left_sel; + +reg [4:0] cur_state, next_state; +reg [`NWIDTH-1:0] comp_N, N, mcount, ncount, Ndivk, mem_N; +reg [1:0] mode; +reg [`BLOCKWIDTH-1:0] block_m, block_n, loop, read_n; +reg [`BLOCKWIDTH-1:0] write_n, write_n_buf; +reg left_mem_sel, cur_mem_sel, no_left_switch; + +reg [3:0] cur_mem_state, next_mem_state; +reg [`RAMSIZEWIDTH-1:0] ram_addr; +reg [`DDRSIZEWIDTH-1:0] mem_addr; +reg [`DDRSIZEWIDTH-1:0] mem_base, mem_top, mem_write, mem_left, mem_cur; +reg [`DDRSIZEWIDTH-1:0] mem_write_buf; +reg [`BLOCKWIDTH-1:0] mem_count; +reg [1:0] mem_read; +reg [`BLOCKWIDTH-1:0] mem_write_size, mem_write_size_buf, mem_read_size; +wire mem_done; + +assign done = (cur_state == `IDLE); +assign dtu_ram_addr = ram_addr; +assign dtu_mem_addr = mem_addr; +assign dtu_size = (cur_mem_state == `MEM_WRITE) ? mem_write_size : mem_read_size; +assign comp_start = (cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)||(cur_state == `FIRST)||(cur_state == `LAST); +assign dtu_write_req = (cur_mem_state == `MEM_WRITE); +assign dtu_read_req = (cur_mem_state == `MEM_READ); +assign mem_done = (cur_mem_state == `MEM_DONE)&&(dtu_done == 1'b1); +assign left_sel = mem_read == 2'b01 && (cur_mem_state == `MEM_READ || cur_mem_state == `MEM_READ_WAIT || cur_mem_state == `MEM_WAIT_DONE); + +// FSM to produce memory instructions to DTU +always @ (posedge clk) +begin + case (cur_mem_state) + `MEM_IDLE: + begin + if (cur_state == `START) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_IDLE; + end + `MEM_DONE: + begin + if (cur_state == `MODE0 || cur_state == `MODE1 || cur_state == `MODE2 || + cur_state == `MODE3 || cur_state == `FINAL_WRITE || cur_state == `LAST_SETUP) + next_mem_state <= `MEM_WRITE; + else if (cur_state == `FIRST) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_DONE; + end + `MEM_WRITE: + begin + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WRITE_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == write_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_WRITE; + end + else + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WAIT_DONE: + begin + if (dtu_done == 1'b1) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_WAIT_DONE; + end + `MEM_CHECK_DONE: + begin + if (mem_read == 2'b10) + next_mem_state <= `MEM_DONE; + else + next_mem_state <= `MEM_READ; + end + `MEM_READ: + begin + next_mem_state <= `MEM_READ_WAIT; + end + `MEM_READ_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == read_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_READ; + end + else + next_mem_state <= `MEM_READ_WAIT; + end + default: + next_mem_state <= `MEM_IDLE; + endcase +end + +always @ (posedge clk) +begin + if (cur_mem_state == `MEM_DONE || cur_mem_state == `MEM_IDLE) + begin + ram_addr <= 8'b0; + mem_addr <= mem_write; + if (next_state == `LAST_WAIT || next_state == `FINAL_WAIT || next_state == `STALL) + mem_read <= 2'b00; + else if (next_state == `MODE0_SETUP || next_state == `SETUP || cur_state == `MODE0 || next_state == `LAST_SETUP_WAIT) + mem_read <= 2'b01; + else + mem_read <= 2'b10; + mem_count <= 8'b0; + end + else if (cur_mem_state == `MEM_CHECK_DONE) + begin + if (mem_read == 2'b10) + begin + mem_addr <= mem_left; + read_n <= loop; + end + else + begin + mem_addr <= mem_cur; + read_n <= block_n; + end + mem_read <= mem_read - 2'b01; + mem_count <= 8'b0; + ram_addr <= 8'b0; + end + else if (cur_mem_state == `MEM_WRITE || cur_mem_state == `MEM_READ) + begin + ram_addr <= ram_addr + `BLOCKMDIVK; + mem_addr <= mem_addr + Ndivk; + mem_count <= mem_count + 2'b01; + end + +end + +// FSM to determine the block LU factorization algorithm +always @ (posedge clk) +begin + case (cur_state) + `START: + begin + next_state <= `SETUP; + end + `SETUP: + begin + next_state <= `WAIT; + end + `WAIT: + begin + if (mem_done == 1'b1) + next_state <= `FIRST; + else + next_state <= `WAIT; + + end + `FIRST: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + next_state <= `LAST_WAIT; + end + `MODE0_SETUP: + begin + next_state <= `MODE0_WAIT; + end + `MODE0_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE0; + else + next_state <= `MODE0_WAIT; + + end + `MODE0: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + begin + next_state <= `LAST_WAIT; + end + end + `MODE1_SETUP: + begin + next_state <= `MODE1_WAIT; + end + `MODE1_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE1; + else + next_state <= `MODE1_WAIT; + + end + `MODE1: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE2_SETUP: + begin + next_state <= `MODE2_WAIT; + end + `MODE2_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE2; + else + next_state <= `MODE2_WAIT; + end + `MODE2: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE3_SETUP: + begin + next_state <= `MODE3_WAIT; + end + `MODE3_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE3; + else + next_state <= `MODE3_WAIT; + end + `MODE3: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `STALL: + next_state <= `STALL_WAIT; + `STALL_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST_SETUP; + else + next_state <= `STALL_WAIT; + `LAST_SETUP: + next_state <= `LAST_SETUP_WAIT; + `LAST_SETUP_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST; + else + next_state <= `LAST_SETUP_WAIT; + `LAST: + next_state <= `LAST_WAIT; + `LAST_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `FINAL_WRITE; + else + next_state <= `LAST_WAIT; + `FINAL_WRITE: + next_state <= `FINAL_WAIT; + `FINAL_WAIT: + if (mem_done == 1'b1) + next_state <= `IDLE; + else + next_state <= `FINAL_WAIT; + `IDLE: + if (start) + next_state <= `SETUP; + else + next_state <= `IDLE; + default: + next_state <= `START; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + cur_state <= `START; + cur_mem_state <= `MEM_IDLE; + end + else + begin + cur_state <= next_state; + cur_mem_state <= next_mem_state; + end +end + +always @ (cur_state) +begin + case (cur_state) + `MODE1: + mode = 2'b01; + `MODE2: + mode = 2'b10; + `MODE3: + mode = 2'b11; + default: + mode = 2'b00; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + comp_N <= input_N; + N <= input_N; + end + else if (next_state == `MODE0) + begin + comp_N <= comp_N - `BLOCKN; + end + + Ndivk <= ((N+`BLOCKM-1)>>7)<<6; + mem_N <= Ndivk<<7; + + if (start) + begin + mem_base <= offset; + mem_top <= offset; + mem_left <= offset; + mem_cur <= offset; + end + else if (cur_state == `MODE0_SETUP) + begin + mem_base <= mem_base + mem_N+`MEMBLOCKN; + mem_top <= mem_base + mem_N+`MEMBLOCKN; + mem_cur <= mem_base + mem_N+`MEMBLOCKN; + mem_left <= mem_base + mem_N+`MEMBLOCKN; + end + else if (cur_state == `MODE1_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + end + else if (cur_state == `MODE3_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + mem_left <= mem_left + `MEMBLOCKM; + end + else if (cur_state == `MODE2_SETUP) + begin + mem_cur <= mem_top + mem_N; + mem_top <= mem_top + mem_N; + mem_left <= mem_base; + end + + if (cur_state == `SETUP) + begin + mem_write <= 24'b0; + mem_write_buf <= 24'b0; + mem_write_size <= `BLOCKMDIVK; + mem_write_size_buf <= `BLOCKMDIVK; + write_n <= block_n; + write_n_buf <= block_n; + end + else if (cur_mem_state == `MEM_CHECK_DONE && mem_read == 0) + begin + mem_write <= mem_write_buf; + mem_write_buf <= mem_cur; + mem_write_size <= mem_write_size_buf; + mem_write_size_buf <= mem_read_size; + write_n <= write_n_buf; + write_n_buf <= block_n; + end + + mem_read_size <= `BLOCKMDIVK; + + if (start) begin + loop <= `BLOCKN; + end else if (next_state == `LAST) begin + loop <= comp_N[8:0] - `BLOCKN; + end + + if (cur_state == `MODE0_SETUP || cur_state == `MODE2_SETUP || start) begin + mcount <= `BLOCKM; + end else if (cur_state == `MODE1_SETUP || cur_state == `MODE3_SETUP) begin + mcount <= mcount+`BLOCKM; + end + + if (cur_state == `MODE0_SETUP || start) begin + ncount <= `BLOCKN; + end else if (cur_state == `MODE2_SETUP) begin + ncount <= ncount+`BLOCKN; + end + + if (mcount < comp_N) begin + block_m <= `BLOCKM; + end else begin + block_m <= comp_N - mcount + `BLOCKM; + end + + if (ncount < comp_N) begin + block_n <= `BLOCKN; + end else begin + block_n <= comp_N - ncount + `BLOCKN; + end + + if (start) begin + cur_mem_sel <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)||(cur_state == `LAST)) begin + cur_mem_sel <= !cur_mem_sel; + end + + if (start) begin + no_left_switch <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `FIRST)) begin + no_left_switch <= 1'b1; + end else if ((cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)) begin + no_left_switch <= 1'b0; + end + + if (start) begin + left_mem_sel <= 1'b0; + end else if (((cur_state == `MODE0)||(cur_state ==`MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP))&&(no_left_switch == 1'b0)) begin + left_mem_sel <= !left_mem_sel; + end +end + +endmodule + + +//topoutputdelay = 1 +//auto-generated LU.v +//datapath for computating LU factorization +//by Wei Zhang + +`define rRAMSIZEWIDTH 8 +`define cSETUP 4'b0000 +`define cSTART 4'b0001 +`define cFETCH_COL 4'b0010 +`define cWAIT_COL 4'b0011 +`define cFIND_REC 4'b0100 +`define cMULT_COL 4'b0101 +`define cUPDATE_J 4'b0110 +`define cSTORE_MO 4'b0111 +`define cMULT_SUB 4'b1000 +`define cINCRE_I 4'b1001 +`define cWAIT 4'b1010 +`define cDONE 4'b1011 +`define cSTORE_DIAG 4'b1100 +`define cSTORE_DIAG2 4'b1101 +`define cSTART_FETCH_ROW 4'b1110 +`define cROW_WAIT 2'b00 +`define cFETCH_ROW 2'b01 +`define cDONE_FETCH_ROW 2'b10 +`define cLOAD_ROW_INC_J 2'b11 + +`define PRECISION 7'b0100000 +`define NUMPE 8'b01000000 +`define PEWIDTH 4'b0110 +`define BLOCKWIDTH 5'b01000 +`define RAMWIDTH 13'b0100000000000 +`define RAMNUMBYTES 10'b0100000000 +`define RAMSIZEWIDTH 5'b01000 +`define TOPSIZEWIDTH 5'b01110 +`define TOPINPUTDELAY 3'b011 +`define TOPOUTPUTDELAY 2'b01 +`define MEMINPUTDELAY 3'b010 +`define MEMOUTPUTDELAY 2'b01 +`define TOPWIDTH 7'b0100000 + +module LU (clk, start, m, n, loop, mode, done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel +); + + +input clk, start; +input[`BLOCKWIDTH-1:0] m, n, loop; +input[1:0] mode; +output done; +wire[`RAMWIDTH-1:0] curWriteData0, curWriteData1; +wire[`RAMSIZEWIDTH-1:0] curWriteAddr0, curReadAddr0, curWriteAddr1, curReadAddr1; +wire[`RAMWIDTH-1:0] curReadData0, curReadData1; +wire[`RAMNUMBYTES-1:0] curWriteByteEn0, curWriteByteEn1; +wire curWriteEn0, curWriteEn1; + +input[`RAMWIDTH-1:0] curWriteDataMem; +output[`RAMWIDTH-1:0] curReadDataMem; +input[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +input[`RAMNUMBYTES-1:0] curWriteByteEnMem; +input curWriteEnMem; +input[`RAMWIDTH-1:0] leftWriteDataMem; +input[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +input[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +input leftWriteEnMem; +input leftMemSel, curMemSel; + +wire[`RAMWIDTH-1:0] curReadDataLU, curReadDataMem; +wire[`RAMWIDTH-1:0] curWriteDataLU, curWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrLU, curWriteAddrMem, curReadAddrLU, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnLU, curWriteByteEnMem; +wire curWriteEnLU, curWriteEnMem; + +reg[`RAMWIDTH-1:0] curReadData0Reg0; +reg[`RAMWIDTH-1:0] curReadData1Reg0; +reg[`RAMWIDTH-1:0] leftReadData0Reg0; +reg[`RAMWIDTH-1:0] leftReadData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg1; +reg[`RAMWIDTH-1:0] curWriteData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg1; +reg curWriteEn0Reg0; +reg curWriteEn0Reg1; +reg curWriteEn1Reg0; +reg curWriteEn1Reg1; +reg[`RAMWIDTH-1:0] leftWriteData0Reg0; +reg[`RAMWIDTH-1:0] leftWriteData0Reg1; +reg[`RAMWIDTH-1:0] leftWriteData1Reg0; +reg[`RAMWIDTH-1:0] leftWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg1; +reg leftWriteEn0Reg0; +reg leftWriteEn0Reg1; +reg leftWriteEn1Reg0; +reg leftWriteEn1Reg1; + +reg[`PRECISION-1:0] multOperand; +reg[`PRECISION-1:0] diag; +wire[`PRECISION-1:0] recResult; +wire[`PRECISION-1:0] multA0; +wire[`PRECISION-1:0] multA1; +wire[`PRECISION-1:0] multA2; +wire[`PRECISION-1:0] multA3; +wire[`PRECISION-1:0] multA4; +wire[`PRECISION-1:0] multA5; +wire[`PRECISION-1:0] multA6; +wire[`PRECISION-1:0] multA7; +wire[`PRECISION-1:0] multA8; +wire[`PRECISION-1:0] multA9; +wire[`PRECISION-1:0] multA10; +wire[`PRECISION-1:0] multA11; +wire[`PRECISION-1:0] multA12; +wire[`PRECISION-1:0] multA13; +wire[`PRECISION-1:0] multA14; +wire[`PRECISION-1:0] multA15; +wire[`PRECISION-1:0] multA16; +wire[`PRECISION-1:0] multA17; +wire[`PRECISION-1:0] multA18; +wire[`PRECISION-1:0] multA19; +wire[`PRECISION-1:0] multA20; +wire[`PRECISION-1:0] multA21; +wire[`PRECISION-1:0] multA22; +wire[`PRECISION-1:0] multA23; +wire[`PRECISION-1:0] multA24; +wire[`PRECISION-1:0] multA25; +wire[`PRECISION-1:0] multA26; +wire[`PRECISION-1:0] multA27; +wire[`PRECISION-1:0] multA28; +wire[`PRECISION-1:0] multA29; +wire[`PRECISION-1:0] multA30; +wire[`PRECISION-1:0] multA31; +wire[`PRECISION-1:0] multA32; +wire[`PRECISION-1:0] multA33; +wire[`PRECISION-1:0] multA34; +wire[`PRECISION-1:0] multA35; +wire[`PRECISION-1:0] multA36; +wire[`PRECISION-1:0] multA37; +wire[`PRECISION-1:0] multA38; +wire[`PRECISION-1:0] multA39; +wire[`PRECISION-1:0] multA40; +wire[`PRECISION-1:0] multA41; +wire[`PRECISION-1:0] multA42; +wire[`PRECISION-1:0] multA43; +wire[`PRECISION-1:0] multA44; +wire[`PRECISION-1:0] multA45; +wire[`PRECISION-1:0] multA46; +wire[`PRECISION-1:0] multA47; +wire[`PRECISION-1:0] multA48; +wire[`PRECISION-1:0] multA49; +wire[`PRECISION-1:0] multA50; +wire[`PRECISION-1:0] multA51; +wire[`PRECISION-1:0] multA52; +wire[`PRECISION-1:0] multA53; +wire[`PRECISION-1:0] multA54; +wire[`PRECISION-1:0] multA55; +wire[`PRECISION-1:0] multA56; +wire[`PRECISION-1:0] multA57; +wire[`PRECISION-1:0] multA58; +wire[`PRECISION-1:0] multA59; +wire[`PRECISION-1:0] multA60; +wire[`PRECISION-1:0] multA61; +wire[`PRECISION-1:0] multA62; +wire[`PRECISION-1:0] multA63; +wire[`PRECISION-1:0] multResult0; +wire[`PRECISION-1:0] multResult1; +wire[`PRECISION-1:0] multResult2; +wire[`PRECISION-1:0] multResult3; +wire[`PRECISION-1:0] multResult4; +wire[`PRECISION-1:0] multResult5; +wire[`PRECISION-1:0] multResult6; +wire[`PRECISION-1:0] multResult7; +wire[`PRECISION-1:0] multResult8; +wire[`PRECISION-1:0] multResult9; +wire[`PRECISION-1:0] multResult10; +wire[`PRECISION-1:0] multResult11; +wire[`PRECISION-1:0] multResult12; +wire[`PRECISION-1:0] multResult13; +wire[`PRECISION-1:0] multResult14; +wire[`PRECISION-1:0] multResult15; +wire[`PRECISION-1:0] multResult16; +wire[`PRECISION-1:0] multResult17; +wire[`PRECISION-1:0] multResult18; +wire[`PRECISION-1:0] multResult19; +wire[`PRECISION-1:0] multResult20; +wire[`PRECISION-1:0] multResult21; +wire[`PRECISION-1:0] multResult22; +wire[`PRECISION-1:0] multResult23; +wire[`PRECISION-1:0] multResult24; +wire[`PRECISION-1:0] multResult25; +wire[`PRECISION-1:0] multResult26; +wire[`PRECISION-1:0] multResult27; +wire[`PRECISION-1:0] multResult28; +wire[`PRECISION-1:0] multResult29; +wire[`PRECISION-1:0] multResult30; +wire[`PRECISION-1:0] multResult31; +wire[`PRECISION-1:0] multResult32; +wire[`PRECISION-1:0] multResult33; +wire[`PRECISION-1:0] multResult34; +wire[`PRECISION-1:0] multResult35; +wire[`PRECISION-1:0] multResult36; +wire[`PRECISION-1:0] multResult37; +wire[`PRECISION-1:0] multResult38; +wire[`PRECISION-1:0] multResult39; +wire[`PRECISION-1:0] multResult40; +wire[`PRECISION-1:0] multResult41; +wire[`PRECISION-1:0] multResult42; +wire[`PRECISION-1:0] multResult43; +wire[`PRECISION-1:0] multResult44; +wire[`PRECISION-1:0] multResult45; +wire[`PRECISION-1:0] multResult46; +wire[`PRECISION-1:0] multResult47; +wire[`PRECISION-1:0] multResult48; +wire[`PRECISION-1:0] multResult49; +wire[`PRECISION-1:0] multResult50; +wire[`PRECISION-1:0] multResult51; +wire[`PRECISION-1:0] multResult52; +wire[`PRECISION-1:0] multResult53; +wire[`PRECISION-1:0] multResult54; +wire[`PRECISION-1:0] multResult55; +wire[`PRECISION-1:0] multResult56; +wire[`PRECISION-1:0] multResult57; +wire[`PRECISION-1:0] multResult58; +wire[`PRECISION-1:0] multResult59; +wire[`PRECISION-1:0] multResult60; +wire[`PRECISION-1:0] multResult61; +wire[`PRECISION-1:0] multResult62; +wire[`PRECISION-1:0] multResult63; +wire[`PRECISION-1:0] addA0; +wire[`PRECISION-1:0] addA1; +wire[`PRECISION-1:0] addA2; +wire[`PRECISION-1:0] addA3; +wire[`PRECISION-1:0] addA4; +wire[`PRECISION-1:0] addA5; +wire[`PRECISION-1:0] addA6; +wire[`PRECISION-1:0] addA7; +wire[`PRECISION-1:0] addA8; +wire[`PRECISION-1:0] addA9; +wire[`PRECISION-1:0] addA10; +wire[`PRECISION-1:0] addA11; +wire[`PRECISION-1:0] addA12; +wire[`PRECISION-1:0] addA13; +wire[`PRECISION-1:0] addA14; +wire[`PRECISION-1:0] addA15; +wire[`PRECISION-1:0] addA16; +wire[`PRECISION-1:0] addA17; +wire[`PRECISION-1:0] addA18; +wire[`PRECISION-1:0] addA19; +wire[`PRECISION-1:0] addA20; +wire[`PRECISION-1:0] addA21; +wire[`PRECISION-1:0] addA22; +wire[`PRECISION-1:0] addA23; +wire[`PRECISION-1:0] addA24; +wire[`PRECISION-1:0] addA25; +wire[`PRECISION-1:0] addA26; +wire[`PRECISION-1:0] addA27; +wire[`PRECISION-1:0] addA28; +wire[`PRECISION-1:0] addA29; +wire[`PRECISION-1:0] addA30; +wire[`PRECISION-1:0] addA31; +wire[`PRECISION-1:0] addA32; +wire[`PRECISION-1:0] addA33; +wire[`PRECISION-1:0] addA34; +wire[`PRECISION-1:0] addA35; +wire[`PRECISION-1:0] addA36; +wire[`PRECISION-1:0] addA37; +wire[`PRECISION-1:0] addA38; +wire[`PRECISION-1:0] addA39; +wire[`PRECISION-1:0] addA40; +wire[`PRECISION-1:0] addA41; +wire[`PRECISION-1:0] addA42; +wire[`PRECISION-1:0] addA43; +wire[`PRECISION-1:0] addA44; +wire[`PRECISION-1:0] addA45; +wire[`PRECISION-1:0] addA46; +wire[`PRECISION-1:0] addA47; +wire[`PRECISION-1:0] addA48; +wire[`PRECISION-1:0] addA49; +wire[`PRECISION-1:0] addA50; +wire[`PRECISION-1:0] addA51; +wire[`PRECISION-1:0] addA52; +wire[`PRECISION-1:0] addA53; +wire[`PRECISION-1:0] addA54; +wire[`PRECISION-1:0] addA55; +wire[`PRECISION-1:0] addA56; +wire[`PRECISION-1:0] addA57; +wire[`PRECISION-1:0] addA58; +wire[`PRECISION-1:0] addA59; +wire[`PRECISION-1:0] addA60; +wire[`PRECISION-1:0] addA61; +wire[`PRECISION-1:0] addA62; +wire[`PRECISION-1:0] addA63; +wire[`PRECISION-1:0] addResult0; +wire[`PRECISION-1:0] addResult1; +wire[`PRECISION-1:0] addResult2; +wire[`PRECISION-1:0] addResult3; +wire[`PRECISION-1:0] addResult4; +wire[`PRECISION-1:0] addResult5; +wire[`PRECISION-1:0] addResult6; +wire[`PRECISION-1:0] addResult7; +wire[`PRECISION-1:0] addResult8; +wire[`PRECISION-1:0] addResult9; +wire[`PRECISION-1:0] addResult10; +wire[`PRECISION-1:0] addResult11; +wire[`PRECISION-1:0] addResult12; +wire[`PRECISION-1:0] addResult13; +wire[`PRECISION-1:0] addResult14; +wire[`PRECISION-1:0] addResult15; +wire[`PRECISION-1:0] addResult16; +wire[`PRECISION-1:0] addResult17; +wire[`PRECISION-1:0] addResult18; +wire[`PRECISION-1:0] addResult19; +wire[`PRECISION-1:0] addResult20; +wire[`PRECISION-1:0] addResult21; +wire[`PRECISION-1:0] addResult22; +wire[`PRECISION-1:0] addResult23; +wire[`PRECISION-1:0] addResult24; +wire[`PRECISION-1:0] addResult25; +wire[`PRECISION-1:0] addResult26; +wire[`PRECISION-1:0] addResult27; +wire[`PRECISION-1:0] addResult28; +wire[`PRECISION-1:0] addResult29; +wire[`PRECISION-1:0] addResult30; +wire[`PRECISION-1:0] addResult31; +wire[`PRECISION-1:0] addResult32; +wire[`PRECISION-1:0] addResult33; +wire[`PRECISION-1:0] addResult34; +wire[`PRECISION-1:0] addResult35; +wire[`PRECISION-1:0] addResult36; +wire[`PRECISION-1:0] addResult37; +wire[`PRECISION-1:0] addResult38; +wire[`PRECISION-1:0] addResult39; +wire[`PRECISION-1:0] addResult40; +wire[`PRECISION-1:0] addResult41; +wire[`PRECISION-1:0] addResult42; +wire[`PRECISION-1:0] addResult43; +wire[`PRECISION-1:0] addResult44; +wire[`PRECISION-1:0] addResult45; +wire[`PRECISION-1:0] addResult46; +wire[`PRECISION-1:0] addResult47; +wire[`PRECISION-1:0] addResult48; +wire[`PRECISION-1:0] addResult49; +wire[`PRECISION-1:0] addResult50; +wire[`PRECISION-1:0] addResult51; +wire[`PRECISION-1:0] addResult52; +wire[`PRECISION-1:0] addResult53; +wire[`PRECISION-1:0] addResult54; +wire[`PRECISION-1:0] addResult55; +wire[`PRECISION-1:0] addResult56; +wire[`PRECISION-1:0] addResult57; +wire[`PRECISION-1:0] addResult58; +wire[`PRECISION-1:0] addResult59; +wire[`PRECISION-1:0] addResult60; +wire[`PRECISION-1:0] addResult61; +wire[`PRECISION-1:0] addResult62; +wire[`PRECISION-1:0] addResult63; +wire[`RAMWIDTH-1:0] leftReadData0, leftReadData1, leftWriteData0, leftWriteData1; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddr0, leftWriteAddr1, leftReadAddr0, leftReadAddr1; +wire[`RAMNUMBYTES-1:0] leftWriteByteEn0, leftWriteByteEn1; +wire leftWriteEn0, leftWriteEn1; +wire[`RAMWIDTH-1:0] leftReadDataLU, leftWriteDataLU, leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrLU, leftWriteAddrMem, leftReadAddrLU; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnLU, leftWriteByteEnMem; +wire leftWriteEnLU, leftWriteEnMem; + +wire[`PRECISION-1:0] topWriteData; +reg[`PRECISION-1:0] topWriteDataLU; +wire[`PRECISION-1:0] topReadData, topReadDataLU; +wire[`TOPSIZEWIDTH-1:0] topWriteAddr, topWriteAddrLU, topReadAddr, topReadAddrLU; +wire topWriteEn, topWriteEnLU; + +reg[`PRECISION-1:0] topReadDataReg0; +reg[`PRECISION-1:0] topWriteDataReg0; +reg[`PRECISION-1:0] topWriteDataReg1; +reg[`PRECISION-1:0] topWriteDataReg2; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg2; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg2; +reg topWriteEnReg0; +reg topWriteEnReg1; +reg topWriteEnReg2; +wire[`RAMWIDTH-1:0] rcWriteData; +wire leftWriteSel, curWriteSel, topSourceSel; +wire diagEn; +wire[`PEWIDTH-1:0] topWriteSel; + +wire MOSel; +wire MOEn; + +// control block +LUControl conBlock (clk, start, m, n, loop, mode, done, + curReadAddrLU, curWriteAddrLU, curWriteByteEnLU, curWriteEnLU, curWriteSel, + leftReadAddrLU, leftWriteAddrLU, leftWriteByteEnLU, leftWriteEnLU, leftWriteSel, + topReadAddrLU, topWriteAddrLU, topWriteEnLU, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +// fp_div unit +//floating point divider here +fpu_div rec(.clock(clk), .n(32'h3F800000), .d(diag), .div(recResult)); +// on-chip memory blocks that store the matrix to be LU factorized +// store current blocks data +ram currentBlock0 (curWriteByteEn0, clk, curWriteData0, curReadAddr0, curWriteAddr0, curWriteEn0, curReadData0 ); +ram1 currentBlock1 (curWriteByteEn1, clk, curWriteData1, curReadAddr1, curWriteAddr1, curWriteEn1, curReadData1 ); +// store left blocks data +ram2 leftBlock0(leftWriteByteEn0, clk, leftWriteData0, leftReadAddr0, leftWriteAddr0, leftWriteEn0, leftReadData0 ); + +ram3 leftBlock1(leftWriteByteEn1, clk, leftWriteData1, leftReadAddr1, leftWriteAddr1, leftWriteEn1, leftReadData1 ); + +// store top block data +top_ram topBlock(clk, topWriteData, topReadAddr, topWriteAddr, topWriteEn, topReadDataLU ); + +// processing elements that does the main computation of LU factorization +mult_add PE0 (clk, multA0, multOperand, addA0, multResult0, addResult0); +mult_add PE1 (clk, multA1, multOperand, addA1, multResult1, addResult1); +mult_add PE2 (clk, multA2, multOperand, addA2, multResult2, addResult2); +mult_add PE3 (clk, multA3, multOperand, addA3, multResult3, addResult3); +mult_add PE4 (clk, multA4, multOperand, addA4, multResult4, addResult4); +mult_add PE5 (clk, multA5, multOperand, addA5, multResult5, addResult5); +mult_add PE6 (clk, multA6, multOperand, addA6, multResult6, addResult6); +mult_add PE7 (clk, multA7, multOperand, addA7, multResult7, addResult7); +mult_add PE8 (clk, multA8, multOperand, addA8, multResult8, addResult8); +mult_add PE9 (clk, multA9, multOperand, addA9, multResult9, addResult9); +mult_add PE10 (clk, multA10, multOperand, addA10, multResult10, addResult10); +mult_add PE11 (clk, multA11, multOperand, addA11, multResult11, addResult11); +mult_add PE12 (clk, multA12, multOperand, addA12, multResult12, addResult12); +mult_add PE13 (clk, multA13, multOperand, addA13, multResult13, addResult13); +mult_add PE14 (clk, multA14, multOperand, addA14, multResult14, addResult14); +mult_add PE15 (clk, multA15, multOperand, addA15, multResult15, addResult15); +mult_add PE16 (clk, multA16, multOperand, addA16, multResult16, addResult16); +mult_add PE17 (clk, multA17, multOperand, addA17, multResult17, addResult17); +mult_add PE18 (clk, multA18, multOperand, addA18, multResult18, addResult18); +mult_add PE19 (clk, multA19, multOperand, addA19, multResult19, addResult19); +mult_add PE20 (clk, multA20, multOperand, addA20, multResult20, addResult20); +mult_add PE21 (clk, multA21, multOperand, addA21, multResult21, addResult21); +mult_add PE22 (clk, multA22, multOperand, addA22, multResult22, addResult22); +mult_add PE23 (clk, multA23, multOperand, addA23, multResult23, addResult23); +mult_add PE24 (clk, multA24, multOperand, addA24, multResult24, addResult24); +mult_add PE25 (clk, multA25, multOperand, addA25, multResult25, addResult25); +mult_add PE26 (clk, multA26, multOperand, addA26, multResult26, addResult26); +mult_add PE27 (clk, multA27, multOperand, addA27, multResult27, addResult27); +mult_add PE28 (clk, multA28, multOperand, addA28, multResult28, addResult28); +mult_add PE29 (clk, multA29, multOperand, addA29, multResult29, addResult29); +mult_add PE30 (clk, multA30, multOperand, addA30, multResult30, addResult30); +mult_add PE31 (clk, multA31, multOperand, addA31, multResult31, addResult31); +mult_add PE32 (clk, multA32, multOperand, addA32, multResult32, addResult32); +mult_add PE33 (clk, multA33, multOperand, addA33, multResult33, addResult33); +mult_add PE34 (clk, multA34, multOperand, addA34, multResult34, addResult34); +mult_add PE35 (clk, multA35, multOperand, addA35, multResult35, addResult35); +mult_add PE36 (clk, multA36, multOperand, addA36, multResult36, addResult36); +mult_add PE37 (clk, multA37, multOperand, addA37, multResult37, addResult37); +mult_add PE38 (clk, multA38, multOperand, addA38, multResult38, addResult38); +mult_add PE39 (clk, multA39, multOperand, addA39, multResult39, addResult39); +mult_add PE40 (clk, multA40, multOperand, addA40, multResult40, addResult40); +mult_add PE41 (clk, multA41, multOperand, addA41, multResult41, addResult41); +mult_add PE42 (clk, multA42, multOperand, addA42, multResult42, addResult42); +mult_add PE43 (clk, multA43, multOperand, addA43, multResult43, addResult43); +mult_add PE44 (clk, multA44, multOperand, addA44, multResult44, addResult44); +mult_add PE45 (clk, multA45, multOperand, addA45, multResult45, addResult45); +mult_add PE46 (clk, multA46, multOperand, addA46, multResult46, addResult46); +mult_add PE47 (clk, multA47, multOperand, addA47, multResult47, addResult47); +mult_add PE48 (clk, multA48, multOperand, addA48, multResult48, addResult48); +mult_add PE49 (clk, multA49, multOperand, addA49, multResult49, addResult49); +mult_add PE50 (clk, multA50, multOperand, addA50, multResult50, addResult50); +mult_add PE51 (clk, multA51, multOperand, addA51, multResult51, addResult51); +mult_add PE52 (clk, multA52, multOperand, addA52, multResult52, addResult52); +mult_add PE53 (clk, multA53, multOperand, addA53, multResult53, addResult53); +mult_add PE54 (clk, multA54, multOperand, addA54, multResult54, addResult54); +mult_add PE55 (clk, multA55, multOperand, addA55, multResult55, addResult55); +mult_add PE56 (clk, multA56, multOperand, addA56, multResult56, addResult56); +mult_add PE57 (clk, multA57, multOperand, addA57, multResult57, addResult57); +mult_add PE58 (clk, multA58, multOperand, addA58, multResult58, addResult58); +mult_add PE59 (clk, multA59, multOperand, addA59, multResult59, addResult59); +mult_add PE60 (clk, multA60, multOperand, addA60, multResult60, addResult60); +mult_add PE61 (clk, multA61, multOperand, addA61, multResult61, addResult61); +mult_add PE62 (clk, multA62, multOperand, addA62, multResult62, addResult62); +mult_add PE63 (clk, multA63, multOperand, addA63, multResult63, addResult63); + +// connect to ports of the left blocks +assign leftWriteDataLU = (leftWriteSel == 1'b0) ? curReadDataLU : rcWriteData; +always @ (posedge clk) +begin + if(leftMemSel == 1'b0) + begin + leftWriteData0Reg0 <= leftWriteDataMem; + leftWriteAddr0Reg0 <= leftWriteAddrMem; + leftWriteByteEn0Reg0 <= leftWriteByteEnMem; + leftWriteEn0Reg0 <= leftWriteEnMem; + leftWriteData1Reg0 <= leftWriteDataLU; + leftWriteAddr1Reg0 <= leftWriteAddrLU; + leftWriteByteEn1Reg0 <= leftWriteByteEnLU; + leftWriteEn1Reg0 <= leftWriteEnLU; + end + else + begin + leftWriteData0Reg0 <= leftWriteDataLU; + leftWriteAddr0Reg0 <= leftWriteAddrLU; + leftWriteByteEn0Reg0 <= leftWriteByteEnLU; + leftWriteEn0Reg0 <= leftWriteEnLU; + leftWriteData1Reg0 <= leftWriteDataMem; + leftWriteAddr1Reg0 <= leftWriteAddrMem; + leftWriteByteEn1Reg0 <= leftWriteByteEnMem; + leftWriteEn1Reg0 <= leftWriteEnMem; + end + leftReadAddr0Reg0 <= leftReadAddrLU; + leftReadAddr1Reg0 <= leftReadAddrLU; + leftWriteData0Reg1 <= leftWriteData0Reg0; + leftWriteAddr0Reg1 <= leftWriteAddr0Reg0; + leftReadAddr0Reg1 <= leftReadAddr0Reg0; + leftWriteByteEn0Reg1 <= leftWriteByteEn0Reg0; + leftWriteEn0Reg1 <= leftWriteEn0Reg0; + leftWriteData1Reg1 <= leftWriteData1Reg0; + leftWriteAddr1Reg1 <= leftWriteAddr1Reg0; + leftReadAddr1Reg1 <= leftReadAddr1Reg0; + leftWriteByteEn1Reg1 <= leftWriteByteEn1Reg0; + leftWriteEn1Reg1 <= leftWriteEn1Reg0; +end +assign leftWriteData0 = leftWriteData0Reg1; +assign leftWriteAddr0 = leftWriteAddr0Reg1; +assign leftReadAddr0 = leftReadAddr0Reg1; +assign leftWriteByteEn0 = leftWriteByteEn0Reg1; +assign leftWriteEn0 = leftWriteEn0Reg1; +assign leftWriteData1 = leftWriteData1Reg1; +assign leftWriteAddr1 = leftWriteAddr1Reg1; +assign leftReadAddr1 = leftReadAddr1Reg1; +assign leftWriteByteEn1 = leftWriteByteEn1Reg1; +assign leftWriteEn1 = leftWriteEn1Reg1; + +always @ (posedge clk) +begin + leftReadData0Reg0 <= leftReadData0; + leftReadData1Reg0 <= leftReadData1; +end +assign leftReadDataLU = (leftMemSel == 1'b0) ? leftReadData1Reg0 : leftReadData0Reg0; +// data feed to fp div unit +always @ (posedge clk) +begin + if (diagEn == 1'b1) + begin + diag <= topReadData; + end +end +// one of the inputs to the PE +always @ (posedge clk) +begin + if (start == 1'b1) + multOperand <= 0; + else if (MOEn == 1'b1) + begin + if (MOSel == 1'b0) + multOperand <= recResult; + else + multOperand <= topReadData; + end +end + +// connections to top block memory ports +always @ (topSourceSel or topWriteSel or curReadDataLU or addResult63 or addResult62 or addResult61 or addResult60 or addResult59 or addResult58 or addResult57 or addResult56 or addResult55 or addResult54 or addResult53 or addResult52 or addResult51 or addResult50 or addResult49 or addResult48 or addResult47 or addResult46 or addResult45 or addResult44 or addResult43 or addResult42 or addResult41 or addResult40 or addResult39 or addResult38 or addResult37 or addResult36 or addResult35 or addResult34 or addResult33 or addResult32 or addResult31 or addResult30 or addResult29 or addResult28 or addResult27 or addResult26 or addResult25 or addResult24 or addResult23 or addResult22 or addResult21 or addResult20 or addResult19 or addResult18 or addResult17 or addResult16 or addResult15 or addResult14 or addResult13 or addResult12 or addResult11 or addResult10 or addResult9 or addResult8 or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +begin + if (topSourceSel == 1'b0) + case (topWriteSel) + 0: + topWriteDataLU = curReadDataLU[2047:2016]; + 1: + topWriteDataLU = curReadDataLU[2015:1984]; + 2: + topWriteDataLU = curReadDataLU[1983:1952]; + 3: + topWriteDataLU = curReadDataLU[1951:1920]; + 4: + topWriteDataLU = curReadDataLU[1919:1888]; + 5: + topWriteDataLU = curReadDataLU[1887:1856]; + 6: + topWriteDataLU = curReadDataLU[1855:1824]; + 7: + topWriteDataLU = curReadDataLU[1823:1792]; + 8: + topWriteDataLU = curReadDataLU[1791:1760]; + 9: + topWriteDataLU = curReadDataLU[1759:1728]; + 10: + topWriteDataLU = curReadDataLU[1727:1696]; + 11: + topWriteDataLU = curReadDataLU[1695:1664]; + 12: + topWriteDataLU = curReadDataLU[1663:1632]; + 13: + topWriteDataLU = curReadDataLU[1631:1600]; + 14: + topWriteDataLU = curReadDataLU[1599:1568]; + 15: + topWriteDataLU = curReadDataLU[1567:1536]; + 16: + topWriteDataLU = curReadDataLU[1535:1504]; + 17: + topWriteDataLU = curReadDataLU[1503:1472]; + 18: + topWriteDataLU = curReadDataLU[1471:1440]; + 19: + topWriteDataLU = curReadDataLU[1439:1408]; + 20: + topWriteDataLU = curReadDataLU[1407:1376]; + 21: + topWriteDataLU = curReadDataLU[1375:1344]; + 22: + topWriteDataLU = curReadDataLU[1343:1312]; + 23: + topWriteDataLU = curReadDataLU[1311:1280]; + 24: + topWriteDataLU = curReadDataLU[1279:1248]; + 25: + topWriteDataLU = curReadDataLU[1247:1216]; + 26: + topWriteDataLU = curReadDataLU[1215:1184]; + 27: + topWriteDataLU = curReadDataLU[1183:1152]; + 28: + topWriteDataLU = curReadDataLU[1151:1120]; + 29: + topWriteDataLU = curReadDataLU[1119:1088]; + 30: + topWriteDataLU = curReadDataLU[1087:1056]; + 31: + topWriteDataLU = curReadDataLU[1055:1024]; + 32: + topWriteDataLU = curReadDataLU[1023:992]; + 33: + topWriteDataLU = curReadDataLU[991:960]; + 34: + topWriteDataLU = curReadDataLU[959:928]; + 35: + topWriteDataLU = curReadDataLU[927:896]; + 36: + topWriteDataLU = curReadDataLU[895:864]; + 37: + topWriteDataLU = curReadDataLU[863:832]; + 38: + topWriteDataLU = curReadDataLU[831:800]; + 39: + topWriteDataLU = curReadDataLU[799:768]; + 40: + topWriteDataLU = curReadDataLU[767:736]; + 41: + topWriteDataLU = curReadDataLU[735:704]; + 42: + topWriteDataLU = curReadDataLU[703:672]; + 43: + topWriteDataLU = curReadDataLU[671:640]; + 44: + topWriteDataLU = curReadDataLU[639:608]; + 45: + topWriteDataLU = curReadDataLU[607:576]; + 46: + topWriteDataLU = curReadDataLU[575:544]; + 47: + topWriteDataLU = curReadDataLU[543:512]; + 48: + topWriteDataLU = curReadDataLU[511:480]; + 49: + topWriteDataLU = curReadDataLU[479:448]; + 50: + topWriteDataLU = curReadDataLU[447:416]; + 51: + topWriteDataLU = curReadDataLU[415:384]; + 52: + topWriteDataLU = curReadDataLU[383:352]; + 53: + topWriteDataLU = curReadDataLU[351:320]; + 54: + topWriteDataLU = curReadDataLU[319:288]; + 55: + topWriteDataLU = curReadDataLU[287:256]; + 56: + topWriteDataLU = curReadDataLU[255:224]; + 57: + topWriteDataLU = curReadDataLU[223:192]; + 58: + topWriteDataLU = curReadDataLU[191:160]; + 59: + topWriteDataLU = curReadDataLU[159:128]; + 60: + topWriteDataLU = curReadDataLU[127:96]; + 61: + topWriteDataLU = curReadDataLU[95:64]; + 62: + topWriteDataLU = curReadDataLU[63:32]; + 63: + topWriteDataLU = curReadDataLU[31:0]; + default: + topWriteDataLU = curReadDataLU[`PRECISION-1:0]; + endcase + else + case (topWriteSel) + 0: + topWriteDataLU = addResult63; + 1: + topWriteDataLU = addResult62; + 2: + topWriteDataLU = addResult61; + 3: + topWriteDataLU = addResult60; + 4: + topWriteDataLU = addResult59; + 5: + topWriteDataLU = addResult58; + 6: + topWriteDataLU = addResult57; + 7: + topWriteDataLU = addResult56; + 8: + topWriteDataLU = addResult55; + 9: + topWriteDataLU = addResult54; + 10: + topWriteDataLU = addResult53; + 11: + topWriteDataLU = addResult52; + 12: + topWriteDataLU = addResult51; + 13: + topWriteDataLU = addResult50; + 14: + topWriteDataLU = addResult49; + 15: + topWriteDataLU = addResult48; + 16: + topWriteDataLU = addResult47; + 17: + topWriteDataLU = addResult46; + 18: + topWriteDataLU = addResult45; + 19: + topWriteDataLU = addResult44; + 20: + topWriteDataLU = addResult43; + 21: + topWriteDataLU = addResult42; + 22: + topWriteDataLU = addResult41; + 23: + topWriteDataLU = addResult40; + 24: + topWriteDataLU = addResult39; + 25: + topWriteDataLU = addResult38; + 26: + topWriteDataLU = addResult37; + 27: + topWriteDataLU = addResult36; + 28: + topWriteDataLU = addResult35; + 29: + topWriteDataLU = addResult34; + 30: + topWriteDataLU = addResult33; + 31: + topWriteDataLU = addResult32; + 32: + topWriteDataLU = addResult31; + 33: + topWriteDataLU = addResult30; + 34: + topWriteDataLU = addResult29; + 35: + topWriteDataLU = addResult28; + 36: + topWriteDataLU = addResult27; + 37: + topWriteDataLU = addResult26; + 38: + topWriteDataLU = addResult25; + 39: + topWriteDataLU = addResult24; + 40: + topWriteDataLU = addResult23; + 41: + topWriteDataLU = addResult22; + 42: + topWriteDataLU = addResult21; + 43: + topWriteDataLU = addResult20; + 44: + topWriteDataLU = addResult19; + 45: + topWriteDataLU = addResult18; + 46: + topWriteDataLU = addResult17; + 47: + topWriteDataLU = addResult16; + 48: + topWriteDataLU = addResult15; + 49: + topWriteDataLU = addResult14; + 50: + topWriteDataLU = addResult13; + 51: + topWriteDataLU = addResult12; + 52: + topWriteDataLU = addResult11; + 53: + topWriteDataLU = addResult10; + 54: + topWriteDataLU = addResult9; + 55: + topWriteDataLU = addResult8; + 56: + topWriteDataLU = addResult7; + 57: + topWriteDataLU = addResult6; + 58: + topWriteDataLU = addResult5; + 59: + topWriteDataLU = addResult4; + 60: + topWriteDataLU = addResult3; + 61: + topWriteDataLU = addResult2; + 62: + topWriteDataLU = addResult1; + 63: + topWriteDataLU = addResult0; + default: + topWriteDataLU = addResult0; + endcase +end + +always @ (posedge clk) +begin + topWriteDataReg0 <= topWriteDataLU; + topReadAddrReg0 <= topReadAddrLU; + topWriteAddrReg0 <= topWriteAddrLU; + topWriteEnReg0 <= topWriteEnLU; + topWriteDataReg1 <= topWriteDataReg0; + topReadAddrReg1 <= topReadAddrReg0; + topWriteAddrReg1 <= topWriteAddrReg0; + topWriteEnReg1 <= topWriteEnReg0; + topWriteDataReg2 <= topWriteDataReg1; + topReadAddrReg2 <= topReadAddrReg1; + topWriteAddrReg2 <= topWriteAddrReg1; + topWriteEnReg2 <= topWriteEnReg1; +end +assign topWriteData = topWriteDataReg2; +assign topReadAddr = topReadAddrReg2; +assign topWriteAddr = topWriteAddrReg2; +assign topWriteEn = topWriteEnReg2; +always @ (posedge clk) +begin + topReadDataReg0 <= topReadDataLU; +end +assign topReadData = topReadDataReg0; + +// connections to processing element +assign multA0 = leftReadDataLU[31:0]; +assign multA1 = leftReadDataLU[63:32]; +assign multA2 = leftReadDataLU[95:64]; +assign multA3 = leftReadDataLU[127:96]; +assign multA4 = leftReadDataLU[159:128]; +assign multA5 = leftReadDataLU[191:160]; +assign multA6 = leftReadDataLU[223:192]; +assign multA7 = leftReadDataLU[255:224]; +assign multA8 = leftReadDataLU[287:256]; +assign multA9 = leftReadDataLU[319:288]; +assign multA10 = leftReadDataLU[351:320]; +assign multA11 = leftReadDataLU[383:352]; +assign multA12 = leftReadDataLU[415:384]; +assign multA13 = leftReadDataLU[447:416]; +assign multA14 = leftReadDataLU[479:448]; +assign multA15 = leftReadDataLU[511:480]; +assign multA16 = leftReadDataLU[543:512]; +assign multA17 = leftReadDataLU[575:544]; +assign multA18 = leftReadDataLU[607:576]; +assign multA19 = leftReadDataLU[639:608]; +assign multA20 = leftReadDataLU[671:640]; +assign multA21 = leftReadDataLU[703:672]; +assign multA22 = leftReadDataLU[735:704]; +assign multA23 = leftReadDataLU[767:736]; +assign multA24 = leftReadDataLU[799:768]; +assign multA25 = leftReadDataLU[831:800]; +assign multA26 = leftReadDataLU[863:832]; +assign multA27 = leftReadDataLU[895:864]; +assign multA28 = leftReadDataLU[927:896]; +assign multA29 = leftReadDataLU[959:928]; +assign multA30 = leftReadDataLU[991:960]; +assign multA31 = leftReadDataLU[1023:992]; +assign multA32 = leftReadDataLU[1055:1024]; +assign multA33 = leftReadDataLU[1087:1056]; +assign multA34 = leftReadDataLU[1119:1088]; +assign multA35 = leftReadDataLU[1151:1120]; +assign multA36 = leftReadDataLU[1183:1152]; +assign multA37 = leftReadDataLU[1215:1184]; +assign multA38 = leftReadDataLU[1247:1216]; +assign multA39 = leftReadDataLU[1279:1248]; +assign multA40 = leftReadDataLU[1311:1280]; +assign multA41 = leftReadDataLU[1343:1312]; +assign multA42 = leftReadDataLU[1375:1344]; +assign multA43 = leftReadDataLU[1407:1376]; +assign multA44 = leftReadDataLU[1439:1408]; +assign multA45 = leftReadDataLU[1471:1440]; +assign multA46 = leftReadDataLU[1503:1472]; +assign multA47 = leftReadDataLU[1535:1504]; +assign multA48 = leftReadDataLU[1567:1536]; +assign multA49 = leftReadDataLU[1599:1568]; +assign multA50 = leftReadDataLU[1631:1600]; +assign multA51 = leftReadDataLU[1663:1632]; +assign multA52 = leftReadDataLU[1695:1664]; +assign multA53 = leftReadDataLU[1727:1696]; +assign multA54 = leftReadDataLU[1759:1728]; +assign multA55 = leftReadDataLU[1791:1760]; +assign multA56 = leftReadDataLU[1823:1792]; +assign multA57 = leftReadDataLU[1855:1824]; +assign multA58 = leftReadDataLU[1887:1856]; +assign multA59 = leftReadDataLU[1919:1888]; +assign multA60 = leftReadDataLU[1951:1920]; +assign multA61 = leftReadDataLU[1983:1952]; +assign multA62 = leftReadDataLU[2015:1984]; +assign multA63 = leftReadDataLU[2047:2016]; + +assign addA0 = curReadDataLU[31:0]; +assign addA1 = curReadDataLU[63:32]; +assign addA2 = curReadDataLU[95:64]; +assign addA3 = curReadDataLU[127:96]; +assign addA4 = curReadDataLU[159:128]; +assign addA5 = curReadDataLU[191:160]; +assign addA6 = curReadDataLU[223:192]; +assign addA7 = curReadDataLU[255:224]; +assign addA8 = curReadDataLU[287:256]; +assign addA9 = curReadDataLU[319:288]; +assign addA10 = curReadDataLU[351:320]; +assign addA11 = curReadDataLU[383:352]; +assign addA12 = curReadDataLU[415:384]; +assign addA13 = curReadDataLU[447:416]; +assign addA14 = curReadDataLU[479:448]; +assign addA15 = curReadDataLU[511:480]; +assign addA16 = curReadDataLU[543:512]; +assign addA17 = curReadDataLU[575:544]; +assign addA18 = curReadDataLU[607:576]; +assign addA19 = curReadDataLU[639:608]; +assign addA20 = curReadDataLU[671:640]; +assign addA21 = curReadDataLU[703:672]; +assign addA22 = curReadDataLU[735:704]; +assign addA23 = curReadDataLU[767:736]; +assign addA24 = curReadDataLU[799:768]; +assign addA25 = curReadDataLU[831:800]; +assign addA26 = curReadDataLU[863:832]; +assign addA27 = curReadDataLU[895:864]; +assign addA28 = curReadDataLU[927:896]; +assign addA29 = curReadDataLU[959:928]; +assign addA30 = curReadDataLU[991:960]; +assign addA31 = curReadDataLU[1023:992]; +assign addA32 = curReadDataLU[1055:1024]; +assign addA33 = curReadDataLU[1087:1056]; +assign addA34 = curReadDataLU[1119:1088]; +assign addA35 = curReadDataLU[1151:1120]; +assign addA36 = curReadDataLU[1183:1152]; +assign addA37 = curReadDataLU[1215:1184]; +assign addA38 = curReadDataLU[1247:1216]; +assign addA39 = curReadDataLU[1279:1248]; +assign addA40 = curReadDataLU[1311:1280]; +assign addA41 = curReadDataLU[1343:1312]; +assign addA42 = curReadDataLU[1375:1344]; +assign addA43 = curReadDataLU[1407:1376]; +assign addA44 = curReadDataLU[1439:1408]; +assign addA45 = curReadDataLU[1471:1440]; +assign addA46 = curReadDataLU[1503:1472]; +assign addA47 = curReadDataLU[1535:1504]; +assign addA48 = curReadDataLU[1567:1536]; +assign addA49 = curReadDataLU[1599:1568]; +assign addA50 = curReadDataLU[1631:1600]; +assign addA51 = curReadDataLU[1663:1632]; +assign addA52 = curReadDataLU[1695:1664]; +assign addA53 = curReadDataLU[1727:1696]; +assign addA54 = curReadDataLU[1759:1728]; +assign addA55 = curReadDataLU[1791:1760]; +assign addA56 = curReadDataLU[1823:1792]; +assign addA57 = curReadDataLU[1855:1824]; +assign addA58 = curReadDataLU[1887:1856]; +assign addA59 = curReadDataLU[1919:1888]; +assign addA60 = curReadDataLU[1951:1920]; +assign addA61 = curReadDataLU[1983:1952]; +assign addA62 = curReadDataLU[2015:1984]; +assign addA63 = curReadDataLU[2047:2016]; + +// connections to ports of the current blocks +assign rcWriteData[31:0] = (curWriteSel == 0) ? multResult0 : addResult0; +assign rcWriteData[63:32] = (curWriteSel == 0) ? multResult1 : addResult1; +assign rcWriteData[95:64] = (curWriteSel == 0) ? multResult2 : addResult2; +assign rcWriteData[127:96] = (curWriteSel == 0) ? multResult3 : addResult3; +assign rcWriteData[159:128] = (curWriteSel == 0) ? multResult4 : addResult4; +assign rcWriteData[191:160] = (curWriteSel == 0) ? multResult5 : addResult5; +assign rcWriteData[223:192] = (curWriteSel == 0) ? multResult6 : addResult6; +assign rcWriteData[255:224] = (curWriteSel == 0) ? multResult7 : addResult7; +assign rcWriteData[287:256] = (curWriteSel == 0) ? multResult8 : addResult8; +assign rcWriteData[319:288] = (curWriteSel == 0) ? multResult9 : addResult9; +assign rcWriteData[351:320] = (curWriteSel == 0) ? multResult10 : addResult10; +assign rcWriteData[383:352] = (curWriteSel == 0) ? multResult11 : addResult11; +assign rcWriteData[415:384] = (curWriteSel == 0) ? multResult12 : addResult12; +assign rcWriteData[447:416] = (curWriteSel == 0) ? multResult13 : addResult13; +assign rcWriteData[479:448] = (curWriteSel == 0) ? multResult14 : addResult14; +assign rcWriteData[511:480] = (curWriteSel == 0) ? multResult15 : addResult15; +assign rcWriteData[543:512] = (curWriteSel == 0) ? multResult16 : addResult16; +assign rcWriteData[575:544] = (curWriteSel == 0) ? multResult17 : addResult17; +assign rcWriteData[607:576] = (curWriteSel == 0) ? multResult18 : addResult18; +assign rcWriteData[639:608] = (curWriteSel == 0) ? multResult19 : addResult19; +assign rcWriteData[671:640] = (curWriteSel == 0) ? multResult20 : addResult20; +assign rcWriteData[703:672] = (curWriteSel == 0) ? multResult21 : addResult21; +assign rcWriteData[735:704] = (curWriteSel == 0) ? multResult22 : addResult22; +assign rcWriteData[767:736] = (curWriteSel == 0) ? multResult23 : addResult23; +assign rcWriteData[799:768] = (curWriteSel == 0) ? multResult24 : addResult24; +assign rcWriteData[831:800] = (curWriteSel == 0) ? multResult25 : addResult25; +assign rcWriteData[863:832] = (curWriteSel == 0) ? multResult26 : addResult26; +assign rcWriteData[895:864] = (curWriteSel == 0) ? multResult27 : addResult27; +assign rcWriteData[927:896] = (curWriteSel == 0) ? multResult28 : addResult28; +assign rcWriteData[959:928] = (curWriteSel == 0) ? multResult29 : addResult29; +assign rcWriteData[991:960] = (curWriteSel == 0) ? multResult30 : addResult30; +assign rcWriteData[1023:992] = (curWriteSel == 0) ? multResult31 : addResult31; +assign rcWriteData[1055:1024] = (curWriteSel == 0) ? multResult32 : addResult32; +assign rcWriteData[1087:1056] = (curWriteSel == 0) ? multResult33 : addResult33; +assign rcWriteData[1119:1088] = (curWriteSel == 0) ? multResult34 : addResult34; +assign rcWriteData[1151:1120] = (curWriteSel == 0) ? multResult35 : addResult35; +assign rcWriteData[1183:1152] = (curWriteSel == 0) ? multResult36 : addResult36; +assign rcWriteData[1215:1184] = (curWriteSel == 0) ? multResult37 : addResult37; +assign rcWriteData[1247:1216] = (curWriteSel == 0) ? multResult38 : addResult38; +assign rcWriteData[1279:1248] = (curWriteSel == 0) ? multResult39 : addResult39; +assign rcWriteData[1311:1280] = (curWriteSel == 0) ? multResult40 : addResult40; +assign rcWriteData[1343:1312] = (curWriteSel == 0) ? multResult41 : addResult41; +assign rcWriteData[1375:1344] = (curWriteSel == 0) ? multResult42 : addResult42; +assign rcWriteData[1407:1376] = (curWriteSel == 0) ? multResult43 : addResult43; +assign rcWriteData[1439:1408] = (curWriteSel == 0) ? multResult44 : addResult44; +assign rcWriteData[1471:1440] = (curWriteSel == 0) ? multResult45 : addResult45; +assign rcWriteData[1503:1472] = (curWriteSel == 0) ? multResult46 : addResult46; +assign rcWriteData[1535:1504] = (curWriteSel == 0) ? multResult47 : addResult47; +assign rcWriteData[1567:1536] = (curWriteSel == 0) ? multResult48 : addResult48; +assign rcWriteData[1599:1568] = (curWriteSel == 0) ? multResult49 : addResult49; +assign rcWriteData[1631:1600] = (curWriteSel == 0) ? multResult50 : addResult50; +assign rcWriteData[1663:1632] = (curWriteSel == 0) ? multResult51 : addResult51; +assign rcWriteData[1695:1664] = (curWriteSel == 0) ? multResult52 : addResult52; +assign rcWriteData[1727:1696] = (curWriteSel == 0) ? multResult53 : addResult53; +assign rcWriteData[1759:1728] = (curWriteSel == 0) ? multResult54 : addResult54; +assign rcWriteData[1791:1760] = (curWriteSel == 0) ? multResult55 : addResult55; +assign rcWriteData[1823:1792] = (curWriteSel == 0) ? multResult56 : addResult56; +assign rcWriteData[1855:1824] = (curWriteSel == 0) ? multResult57 : addResult57; +assign rcWriteData[1887:1856] = (curWriteSel == 0) ? multResult58 : addResult58; +assign rcWriteData[1919:1888] = (curWriteSel == 0) ? multResult59 : addResult59; +assign rcWriteData[1951:1920] = (curWriteSel == 0) ? multResult60 : addResult60; +assign rcWriteData[1983:1952] = (curWriteSel == 0) ? multResult61 : addResult61; +assign rcWriteData[2015:1984] = (curWriteSel == 0) ? multResult62 : addResult62; +assign rcWriteData[2047:2016] = (curWriteSel == 0) ? multResult63 : addResult63; +assign curWriteDataLU = rcWriteData; + +always @ (posedge clk) +begin + if(curMemSel == 1'b0) + begin + curWriteData0Reg0 <= curWriteDataMem; + curWriteAddr0Reg0 <= curWriteAddrMem; + curReadAddr0Reg0 <= curReadAddrMem; + curWriteByteEn0Reg0 <= curWriteByteEnMem; + curWriteEn0Reg0 <= curWriteEnMem; + curWriteData1Reg0 <= curWriteDataLU; + curWriteAddr1Reg0 <= curWriteAddrLU; + curReadAddr1Reg0 <= curReadAddrLU; + curWriteByteEn1Reg0 <= curWriteByteEnLU; + curWriteEn1Reg0 <= curWriteEnLU; + end + else + begin + curWriteData0Reg0 <= curWriteDataLU; + curWriteAddr0Reg0 <= curWriteAddrLU; + curReadAddr0Reg0 <= curReadAddrLU; + curWriteByteEn0Reg0 <= curWriteByteEnLU; + curWriteEn0Reg0 <= curWriteEnLU; + curWriteData1Reg0 <= curWriteDataMem; + curWriteAddr1Reg0 <= curWriteAddrMem; + curReadAddr1Reg0 <= curReadAddrMem; + curWriteByteEn1Reg0 <= curWriteByteEnMem; + curWriteEn1Reg0 <= curWriteEnMem; + end + curWriteData0Reg1 <= curWriteData0Reg0; + curWriteAddr0Reg1 <= curWriteAddr0Reg0; + curReadAddr0Reg1 <= curReadAddr0Reg0; + curWriteByteEn0Reg1 <= curWriteByteEn0Reg0; + curWriteEn0Reg1 <= curWriteEn0Reg0; + curWriteData1Reg1 <= curWriteData1Reg0; + curWriteAddr1Reg1 <= curWriteAddr1Reg0; + curReadAddr1Reg1 <= curReadAddr1Reg0; + curWriteByteEn1Reg1 <= curWriteByteEn1Reg0; + curWriteEn1Reg1 <= curWriteEn1Reg0; +end +assign curWriteData0 = curWriteData0Reg1; +assign curWriteAddr0 = curWriteAddr0Reg1; +assign curReadAddr0 = curReadAddr0Reg1; +assign curWriteByteEn0 = curWriteByteEn0Reg1; +assign curWriteEn0 = curWriteEn0Reg1; +assign curWriteData1 = curWriteData1Reg1; +assign curWriteAddr1 = curWriteAddr1Reg1; +assign curReadAddr1 = curReadAddr1Reg1; +assign curWriteByteEn1 = curWriteByteEn1Reg1; +assign curWriteEn1 = curWriteEn1Reg1; + +always @ (posedge clk) +begin + curReadData0Reg0 <= curReadData0; + curReadData1Reg0 <= curReadData1; +end +assign curReadDataMem = (curMemSel == 0) ? curReadData0Reg0 : curReadData1Reg0; +assign curReadDataLU = (curMemSel == 0) ? curReadData1Reg0 : curReadData0Reg0; +endmodule + +module LUControl (clk, start_in, m_in, n_in, loop_in, mode_in, done, + curReadAddr, curWriteAddr, curWriteByteEn, curWriteEn, curWriteSel, + leftReadAddr, leftWriteAddr, leftWriteByteEn, leftWriteEn, leftWriteSel, + topReadAddr, topWriteAddr, topWriteEn, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +input clk, start_in; +input[8-1:0] m_in, n_in, loop_in; +input[1:0] mode_in; +output done; + +output[256-1:0] curWriteByteEn; +output[8-1:0] curWriteAddr, curReadAddr; +output curWriteEn; + +output[256-1:0] leftWriteByteEn; +output[8-1:0] leftWriteAddr, leftReadAddr; +output leftWriteEn; + +output[14-1:0] topWriteAddr, topReadAddr; +output topWriteEn; + +output leftWriteSel, curWriteSel, topSourceSel, diagEn; +output[6-1:0] topWriteSel; + +output MOSel; +output MOEn; + +reg start; +reg[15:0]startDelay; +reg[8-1:0] m, n, stop, stop2, loop; +reg[1:0] mode; +reg[3:0] nextState, currentState; +reg[1:0] nextRowState, currentRowState; +reg startFetchRow, doneFetchRow, loadRow, writeRow; +reg updateCounter; + +reg[8-1:0] i1, j; +reg[14-1:0] nextTopIdx, nextTopIdx2, curTopIdx, nextTopIdxCounter; +reg[2-1:0] topIdx, topIdxCounter, mdivk; +reg[8-1:0] diagIdx, leftIdx, msIdx; +reg[6-1:0] imodk, i1modk; +reg[8-1:0] diagIdxCounter, leftIdxCounter, msIdxCounter, readRowCounter, topWriteCounter; +reg[256-1:0] byteEn, i1modkByteEn; + +reg done; + +reg[256-1:0] curWriteByteEn; +reg[8-1:0] curWriteAddr, curReadAddr; +reg curWriteEn; + +reg[256-1:0] leftWriteByteEn; +reg[8-1:0] leftWriteAddr, leftReadAddr; +reg leftWriteEn; + +reg[14-1:0] topWriteAddr, topReadAddr; +reg topWriteEn; + +reg leftWriteSel, curWriteSel, topSourceSel, diagEn; +reg[6-1:0] topWriteSel; + +reg MOSel; +reg MOEn; + +reg[8-1:0] counter; +reg[6-1:0] divCounter; + +reg[256-1:0]writeByteEnDelay0; +reg[256-1:0]writeByteEnDelay1; +reg[256-1:0]writeByteEnDelay2; +reg[256-1:0]writeByteEnDelay3; +reg[256-1:0]writeByteEnDelay4; +reg[256-1:0]writeByteEnDelay5; +reg[256-1:0]writeByteEnDelay6; +reg[256-1:0]writeByteEnDelay7; +reg[256-1:0]writeByteEnDelay8; +reg[256-1:0]writeByteEnDelay9; +reg[256-1:0]writeByteEnDelay10; +reg[256-1:0]writeByteEnDelay11; +reg[256-1:0]writeByteEnDelay12; +reg[256-1:0]writeByteEnDelay13; +reg[256-1:0]writeByteEnDelay14; +reg[256-1:0]writeByteEnDelay15; +reg[256-1:0]writeByteEnDelay16; +reg[256-1:0]writeByteEnDelay17; +reg[256-1:0]writeByteEnDelay18; +reg[256-1:0]writeByteEnDelay19; +reg[256-1:0]writeByteEnDelay20; +reg[256-1:0]writeByteEnDelay21; +reg[256-1:0]writeByteEnDelay22; +reg[256-1:0]writeByteEnDelay23; +reg[256-1:0]writeByteEnDelay24; +reg[256-1:0]writeByteEnDelay25; +reg[256-1:0]writeByteEnDelay26; +reg[256-1:0]writeByteEnDelay27; +reg[256-1:0]writeByteEnDelay28; +reg[256-1:0]writeByteEnDelay29; +reg[256-1:0]writeByteEnDelay30; +reg[256-1:0]writeByteEnDelay31; + +reg[8-1:0]curWriteAddrDelay0; +reg[8-1:0]curWriteAddrDelay1; +reg[8-1:0]curWriteAddrDelay2; +reg[8-1:0]curWriteAddrDelay3; +reg[8-1:0]curWriteAddrDelay4; +reg[8-1:0]curWriteAddrDelay5; +reg[8-1:0]curWriteAddrDelay6; +reg[8-1:0]curWriteAddrDelay7; +reg[8-1:0]curWriteAddrDelay8; +reg[8-1:0]curWriteAddrDelay9; +reg[8-1:0]curWriteAddrDelay10; +reg[8-1:0]curWriteAddrDelay11; +reg[8-1:0]curWriteAddrDelay12; +reg[8-1:0]curWriteAddrDelay13; +reg[8-1:0]curWriteAddrDelay14; +reg[8-1:0]curWriteAddrDelay15; +reg[8-1:0]curWriteAddrDelay16; +reg[8-1:0]curWriteAddrDelay17; +reg[8-1:0]curWriteAddrDelay18; +reg[8-1:0]curWriteAddrDelay19; +reg[8-1:0]curWriteAddrDelay20; +reg[8-1:0]curWriteAddrDelay21; +reg[8-1:0]curWriteAddrDelay22; +reg[8-1:0]curWriteAddrDelay23; +reg[8-1:0]curWriteAddrDelay24; +reg[8-1:0]curWriteAddrDelay25; +reg[8-1:0]curWriteAddrDelay26; +reg[8-1:0]curWriteAddrDelay27; +reg[8-1:0]curWriteAddrDelay28; +reg[8-1:0]curWriteAddrDelay29; +reg[8-1:0]curWriteAddrDelay30; +reg[8-1:0]curWriteAddrDelay31; + +reg[8-1:0]curReadAddrDelay0; +reg[8-1:0]curReadAddrDelay1; +reg[8-1:0]curReadAddrDelay2; +reg[8-1:0]curReadAddrDelay3; +reg[8-1:0]curReadAddrDelay4; +reg[8-1:0]curReadAddrDelay5; +reg[8-1:0]curReadAddrDelay6; +reg[8-1:0]curReadAddrDelay7; +reg[8-1:0]curReadAddrDelay8; +reg[8-1:0]curReadAddrDelay9; +reg[8-1:0]curReadAddrDelay10; +reg[8-1:0]curReadAddrDelay11; + +reg[32-1:0]leftWriteEnDelay; +reg[32-1:0]curWriteEnDelay; +reg[5-1:0]leftWriteSelDelay; +reg[16-1:0]curWriteSelDelay; +reg[8-1:0]leftReadAddrDelay0; +reg[14-1:0]topWriteAddrDelay0; +reg[14-1:0]topWriteAddrDelay1; +reg[14-1:0]topWriteAddrDelay2; +reg[14-1:0]topWriteAddrDelay3; +reg[14-1:0]topWriteAddrDelay4; +reg[14-1:0]topWriteAddrDelay5; +reg[14-1:0]topWriteAddrDelay6; +reg[14-1:0]topWriteAddrDelay7; +reg[14-1:0]topWriteAddrDelay8; +reg[14-1:0]topWriteAddrDelay9; +reg[14-1:0]topWriteAddrDelay10; +reg[14-1:0]topWriteAddrDelay11; +reg[14-1:0]topWriteAddrDelay12; +reg[14-1:0]topWriteAddrDelay13; +reg[14-1:0]topWriteAddrDelay14; +reg[14-1:0]topWriteAddrDelay15; +reg[14-1:0]topWriteAddrDelay16; +reg[14-1:0]topWriteAddrDelay17; +reg[14-1:0]topWriteAddrDelay18; +reg[14-1:0]topWriteAddrDelay19; +reg[14-1:0]topWriteAddrDelay20; +reg[14-1:0]topWriteAddrDelay21; +reg[14-1:0]topWriteAddrDelay22; +reg[14-1:0]topWriteAddrDelay23; +reg[14-1:0]topWriteAddrDelay24; +reg[14-1:0]topWriteAddrDelay25; +reg[14-1:0]topWriteAddrDelay26; +reg[14-1:0]topWriteAddrDelay27; +reg[14-1:0]topWriteAddrDelay28; +reg[14-1:0]topWriteAddrDelay29; +reg[14-1:0]topWriteAddrDelay30; +reg[14-1:0]topWriteAddrDelay31; + +reg [32-1:0]topWriteEnDelay; +reg [5-1:0]topSourceSelDelay; +reg[6-1:0]topWriteSelDelay0; +reg[6-1:0]topWriteSelDelay1; +reg[6-1:0]topWriteSelDelay2; +reg[6-1:0]topWriteSelDelay3; +reg[6-1:0]topWriteSelDelay4; +reg[6-1:0]topWriteSelDelay5; +reg[6-1:0]topWriteSelDelay6; +reg[6-1:0]topWriteSelDelay7; +reg[6-1:0]topWriteSelDelay8; +reg[6-1:0]topWriteSelDelay9; +reg[6-1:0]topWriteSelDelay10; +reg[6-1:0]topWriteSelDelay11; +reg[6-1:0]topWriteSelDelay12; +reg[6-1:0]topWriteSelDelay13; +reg[6-1:0]topWriteSelDelay14; +reg[6-1:0]topWriteSelDelay15; +reg[6-1:0]topWriteSelDelay16; +reg[6-1:0]topWriteSelDelay17; +reg[6-1:0]topWriteSelDelay18; +reg[6-1:0]topWriteSelDelay19; +reg[6-1:0]topWriteSelDelay20; +reg[6-1:0]topWriteSelDelay21; +reg[6-1:0]topWriteSelDelay22; +reg[6-1:0]topWriteSelDelay23; +reg[6-1:0]topWriteSelDelay24; +reg[6-1:0]topWriteSelDelay25; +reg[6-1:0]topWriteSelDelay26; +reg[6-1:0]topWriteSelDelay27; +reg[6-1:0]topWriteSelDelay28; +reg[6-1:0]topWriteSelDelay29; +reg[6-1:0]topWriteSelDelay30; +reg[6-1:0]topWriteSelDelay31; + +reg [6-1:0]diagEnDelay; +reg[6-1:0]MOEnDelay; +reg [8-1:0]waitCycles; + +// register store m, n and mdivk value +always @ (posedge clk) +begin + if (start_in == 1'b1) + begin + n <= n_in; + m <= m_in; + loop <= loop_in; + mode <= mode_in; + end + if (mode[0] == 1'b0 && m == loop) + stop <= loop; + else + stop <= loop+1'b1; + stop2 <= loop; + startDelay[0] <= start_in; + startDelay[1] <= startDelay[0]; + startDelay[2] <= startDelay[1]; + startDelay[3] <= startDelay[2]; + startDelay[4] <= startDelay[3]; + startDelay[5] <= startDelay[4]; + startDelay[6] <= startDelay[5]; + startDelay[7] <= startDelay[6]; + startDelay[8] <= startDelay[7]; + startDelay[9] <= startDelay[8]; + startDelay[10] <= startDelay[9]; + startDelay[11] <= startDelay[10]; + startDelay[12] <= startDelay[11]; + startDelay[13] <= startDelay[12]; + startDelay[14] <= startDelay[13]; + startDelay[15] <= startDelay[14]; + start <= startDelay[15]; + mdivk <= (m+64-1)>>6; +end + +// registers that store values that are used in FSM, dependent on i and/or j +always @ (posedge clk) +begin + if (start == 1'b1) + topIdx <= 2'b00; //offset1divk; + else if (currentState == `cINCRE_I && i1modk == 64-1 && mode[0] == 1'b0) + topIdx <= topIdx + 1'b1; + + if (start == 1'b1) + diagIdx <= 8'b00000000; + else if (currentState == `cSTORE_DIAG && mode == 2'b01) + diagIdx <= 2; else if (currentState == `cINCRE_I) + begin + if ((imodk == 64-1 && mode == 2'b00) || (i1modk == 64-1 && mode == 2'b01)) + diagIdx <= diagIdx + 2 + 1; + else + diagIdx <= diagIdx + 2; + end + + if (start == 1'b1) + leftIdx <= 8'b00000000; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 64-1 && mode[0] == 1'b0) + leftIdx <= leftIdx + 2 + 1; + else + leftIdx <= leftIdx + 2; + end + + if (start == 1'b1) + msIdx <= 8'b00000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + msIdx <= leftIdx + 2; + else + msIdx <= topIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + msIdx <= msIdx + 2; + + if (start == 1'b1) + imodk <= 6'b000000; + else if (currentState == `cINCRE_I) + begin + if (imodk == 64-1) + imodk <= 6'b000000; + else + imodk <= imodk + 1'b1; + end + + if (start == 1'b1) + i1modk <= 6'b000001; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 64-1) + i1modk <= 6'b000000; + else + i1modk <= i1modk + 1'b1; + end + + if (start == 1'b1) + nextTopIdx <= 14'b00000000000000; + else if (currentState == `cINCRE_I) + if (mode[1] == 0) + nextTopIdx <= nextTopIdx + n + 1; + else + nextTopIdx <= nextTopIdx + n; + nextTopIdx2 <= nextTopIdx + n + 1; + + if (start == 1'b1) + curTopIdx <= 14'b00000000000001; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + curTopIdx <= nextTopIdx+1; + else + curTopIdx <= nextTopIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + curTopIdx <= curTopIdx + 1; + + if (start == 1'b1) + i1 <= 8'b00000001; + else if (currentState == `cINCRE_I) + i1 <= i1 + 1; + + if (start == 1'b1) + j <= 8'b00000000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + j <= i1; + else + j <= 8'b00000000; + else if (currentRowState == `cLOAD_ROW_INC_J) + j <= j + 1; + +// compute cycles of delay in FSM + if (currentState == `cSTORE_MO) + waitCycles <= 32-1; + else if (currentState == `cINCRE_I) + begin + if (i1 == stop-1) + if (mode[1] == 1'b1) + waitCycles <= 32-1 + 6 - 3; + else + waitCycles <= waitCycles + 5 - 2; + else if (mode == 2'b01 && waitCycles < 32-1 - (16-1) - 4) + waitCycles <= 32-1 - (16-1) - 4; + else if (mode == 2'b10 && i1modk == 64-1) + waitCycles <= 32-1 + 6 - 3; + else if (mode == 2'b00) + waitCycles <= waitCycles + 6 ; + end +else if (waitCycles >8'b00000000) + waitCycles <= waitCycles - 1; + +end + +// determining next state of main FSM +always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +begin + case (currentState) + `cSETUP: + begin + if (start == 1'b1) + nextState = `cSTART; + else + nextState = `cSETUP; + updateCounter = 1'b1; + end + `cSTART: + begin + if (mode == 2'b00) + begin + if (m == 1 && n == 1) + nextState = `cDONE; + else + nextState = `cFETCH_COL; + end + else if (mode == 2'b01) + nextState = `cSTORE_DIAG; + else if (mode == 2'b10) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cUPDATE_J; + updateCounter = 1'b1; + end + `cSTART_FETCH_ROW: + begin + if (counter == 5+6-1) + begin + if (mode == 2'b00) + nextState = `cSTORE_DIAG; + else + nextState = `cUPDATE_J; + end + else + nextState = `cSTART_FETCH_ROW; + updateCounter = 1'b0; + end + `cFETCH_COL: + if (counter >= mdivk-1) + begin + if (mode == 2'b00 && counter < 5) + begin + nextState = `cWAIT_COL; + updateCounter = 1'b0; + end + else + begin + if (mode == 2'b00) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1'b1; + end + end + else + begin + nextState = `cFETCH_COL; + updateCounter = 1'b0; + end + `cWAIT_COL: + if (counter >= 5) + begin + if (mode == 0) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1; + end + else + begin + nextState = `cWAIT_COL; + updateCounter = 0; + end + `cSTORE_DIAG: + begin + if (mode == 0) + nextState = `cFIND_REC; + else + nextState = `cFETCH_COL; + updateCounter = 1; + end + `cFIND_REC: + if (divCounter == 56) + begin + if (mode == 0) + nextState = `cMULT_COL; + else + nextState = `cSTORE_DIAG2; + updateCounter = 1; + end + else + begin + nextState = `cFIND_REC; + updateCounter = 0; + end + `cSTORE_DIAG2: + begin + nextState = `cMULT_COL; + updateCounter = 1; + end + `cMULT_COL: + if (topIdxCounter == mdivk-1) + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + else + begin + nextState = `cMULT_COL; + updateCounter = 0; + end + `cUPDATE_J: + if ((mode[1] == 1 || counter >= 16-1) && doneFetchRow == 1) + begin + nextState = `cSTORE_MO; + updateCounter = 1; + end + else + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + `cSTORE_MO: + begin + if (j == stop2) + begin + if (counter == mdivk-1+5-2) + nextState = `cDONE; + else + nextState = `cSTORE_MO; + updateCounter = 0; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 1; + end + end + `cMULT_SUB: + if (topIdxCounter == mdivk-1) + begin + if (j == n-1) + nextState = `cINCRE_I; + else + nextState = `cMULT_SUB; + updateCounter = 1; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 0; + end + `cINCRE_I: + begin + nextState = `cWAIT; + updateCounter = 1; + end + `cWAIT: + if (waitCycles == 0) + begin + if (i1 == stop) + nextState = `cDONE; + else if (mode == 0) + nextState = `cSTORE_DIAG; + else if (mode == 1) + nextState = `cFIND_REC; + else + nextState = `cUPDATE_J; + updateCounter = 1; + end + else + begin + nextState = `cWAIT; + updateCounter = 0; + end + `cDONE: + begin + nextState = `cDONE; + updateCounter = 0; + end + default: + begin + nextState = `cSETUP; + updateCounter = 1; + end + endcase +end + +always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +begin + if (currentRowState == `cDONE_FETCH_ROW) + doneFetchRow = 1; + else + doneFetchRow = 0; + if((nextState == `cSTART_FETCH_ROW && currentState != `cSTART_FETCH_ROW && i1 == 1)) + startFetchRow = 1; + else + startFetchRow = 0; + if (currentState == `cMULT_SUB && topIdxCounter+2 == mdivk) + loadRow = 1; + else + loadRow = 0; + writeRow = (msIdxCounter == readRowCounter)&&(currentState==`cMULT_SUB)&&(j!=n)&&(mode[0] == 0); +end + +// second FSM that controls the control signals to temp_top block +always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +begin + case (currentRowState) + `cFETCH_ROW: + if (nextTopIdxCounter == n-1) + nextRowState = `cDONE_FETCH_ROW; + else + nextRowState = `cFETCH_ROW; + `cDONE_FETCH_ROW: + if (startFetchRow == 1) + nextRowState = `cFETCH_ROW; + else if (loadRow == 1 || (topIdx+1 == mdivk && nextState == `cMULT_SUB)) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + `cLOAD_ROW_INC_J: + if (topIdx+1 == mdivk && nextState == `cMULT_SUB) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + default: + nextRowState = `cDONE_FETCH_ROW; + endcase +end + +// address counters +always @ (posedge clk) +begin + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + topIdxCounter <= topIdx; + else + topIdxCounter <= topIdxCounter + 1; + + if (updateCounter == 1) + diagIdxCounter <= diagIdx; + else + diagIdxCounter <= diagIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + msIdxCounter <= msIdx; + else + msIdxCounter <= msIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + leftIdxCounter <= leftIdx; + else + leftIdxCounter <= leftIdxCounter + 1; + + if (currentState == `cFETCH_COL || currentState == `cSTORE_MO) + topWriteCounter <= i1; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + topWriteCounter <= topWriteCounter + 1; + + if (currentState == `cSTART) + nextTopIdxCounter <= nextTopIdx; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + nextTopIdxCounter <= nextTopIdx + n + 1; + else + nextTopIdxCounter <= nextTopIdx + n; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + nextTopIdxCounter <= nextTopIdxCounter + 1; + + if (currentState == `cSTART) + readRowCounter <= 0; //offsetdivk; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + readRowCounter <= leftIdx + 2; + else + readRowCounter <= topIdx; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + readRowCounter <= readRowCounter + 2; + + if (updateCounter == 1) + counter <= 0; + else + counter <= counter + 1; + + if (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2) + divCounter <= 0; + else if (divCounter < 56) + divCounter <= divCounter + 1; + + case (i1modk) + 6'b000000: begin + i1modkByteEn <= ~(256'b0) >> (6'b000000<<2'b10); + end + 6'b000001: begin + i1modkByteEn <= ~(256'b0) >> (6'b000001<<2'b10); + end + 6'b000010: begin + i1modkByteEn <= ~(256'b0) >> (6'b000010<<2'b10); + end + 6'b000011: begin + i1modkByteEn <= ~(256'b0) >> (6'b000011<<2'b10); + end + 6'b000100: begin + i1modkByteEn <= ~(256'b0) >> (6'b000100<<2'b10); + end + 6'b000101: begin + i1modkByteEn <= ~(256'b0) >> (6'b000101<<2'b10); + end + 6'b000110: begin + i1modkByteEn <= ~(256'b0) >> (6'b000110<<2'b10); + end + 6'b000111: begin + i1modkByteEn <= ~(256'b0) >> (6'b000111<<2'b10); + end + 6'b001000: begin + i1modkByteEn <= ~(256'b0) >> (6'b001000<<2'b10); + end + 6'b001001: begin + i1modkByteEn <= ~(256'b0) >> (6'b001001<<2'b10); + end + 6'b001010: begin + i1modkByteEn <= ~(256'b0) >> (6'b001010<<2'b10); + end + 6'b001011: begin + i1modkByteEn <= ~(256'b0) >> (6'b001011<<2'b10); + end + 6'b001100: begin + i1modkByteEn <= ~(256'b0) >> (6'b001100<<2'b10); + end + 6'b001101: begin + i1modkByteEn <= ~(256'b0) >> (6'b001101<<2'b10); + end + 6'b001110: begin + i1modkByteEn <= ~(256'b0) >> (6'b001110<<2'b10); + end + 6'b001111: begin + i1modkByteEn <= ~(256'b0) >> (6'b001111<<2'b10); + end + 6'b010000: begin + i1modkByteEn <= ~(256'b0) >> (6'b010000<<2'b10); + end + 6'b010001: begin + i1modkByteEn <= ~(256'b0) >> (6'b010001<<2'b10); + end + 6'b010010: begin + i1modkByteEn <= ~(256'b0) >> (6'b010010<<2'b10); + end + 6'b010011: begin + i1modkByteEn <= ~(256'b0) >> (6'b010011<<2'b10); + end + 6'b010100: begin + i1modkByteEn <= ~(256'b0) >> (6'b010100<<2'b10); + end + 6'b010101: begin + i1modkByteEn <= ~(256'b0) >> (6'b010101<<2'b10); + end + 6'b010110: begin + i1modkByteEn <= ~(256'b0) >> (6'b010110<<2'b10); + end + 6'b010111: begin + i1modkByteEn <= ~(256'b0) >> (6'b010111<<2'b10); + end + 6'b011000: begin + i1modkByteEn <= ~(256'b0) >> (6'b011000<<2'b10); + end + 6'b011001: begin + i1modkByteEn <= ~(256'b0) >> (6'b011001<<2'b10); + end + 6'b011010: begin + i1modkByteEn <= ~(256'b0) >> (6'b011010<<2'b10); + end + 6'b011011: begin + i1modkByteEn <= ~(256'b0) >> (6'b011011<<2'b10); + end + 6'b011100: begin + i1modkByteEn <= ~(256'b0) >> (6'b011100<<2'b10); + end + 6'b011101: begin + i1modkByteEn <= ~(256'b0) >> (6'b011101<<2'b10); + end + 6'b011110: begin + i1modkByteEn <= ~(256'b0) >> (6'b011110<<2'b10); + end + 6'b011111: begin + i1modkByteEn <= ~(256'b0) >> (6'b011111<<2'b10); + end + 6'b100000: begin + i1modkByteEn <= ~(256'b0) >> (6'b100000<<2'b10); + end + 6'b100001: begin + i1modkByteEn <= ~(256'b0) >> (6'b100001<<2'b10); + end + 6'b100010: begin + i1modkByteEn <= ~(256'b0) >> (6'b100010<<2'b10); + end + 6'b100011: begin + i1modkByteEn <= ~(256'b0) >> (6'b100011<<2'b10); + end + 6'b100100: begin + i1modkByteEn <= ~(256'b0) >> (6'b100100<<2'b10); + end + 6'b100101: begin + i1modkByteEn <= ~(256'b0) >> (6'b100101<<2'b10); + end + 6'b100110: begin + i1modkByteEn <= ~(256'b0) >> (6'b100110<<2'b10); + end + 6'b100111: begin + i1modkByteEn <= ~(256'b0) >> (6'b100111<<2'b10); + end + 6'b101000: begin + i1modkByteEn <= ~(256'b0) >> (6'b101000<<2'b10); + end + 6'b101001: begin + i1modkByteEn <= ~(256'b0) >> (6'b101001<<2'b10); + end + 6'b101010: begin + i1modkByteEn <= ~(256'b0) >> (6'b101010<<2'b10); + end + 6'b101011: begin + i1modkByteEn <= ~(256'b0) >> (6'b101011<<2'b10); + end + 6'b101100: begin + i1modkByteEn <= ~(256'b0) >> (6'b101100<<2'b10); + end + 6'b101101: begin + i1modkByteEn <= ~(256'b0) >> (6'b101101<<2'b10); + end + 6'b101110: begin + i1modkByteEn <= ~(256'b0) >> (6'b101110<<2'b10); + end + 6'b101111: begin + i1modkByteEn <= ~(256'b0) >> (6'b101111<<2'b10); + end + 6'b110000: begin + i1modkByteEn <= ~(256'b0) >> (6'b110000<<2'b10); + end + 6'b110001: begin + i1modkByteEn <= ~(256'b0) >> (6'b110001<<2'b10); + end + 6'b110010: begin + i1modkByteEn <= ~(256'b0) >> (6'b110010<<2'b10); + end + 6'b110011: begin + i1modkByteEn <= ~(256'b0) >> (6'b110011<<2'b10); + end + 6'b110100: begin + i1modkByteEn <= ~(256'b0) >> (6'b110100<<2'b10); + end + 6'b110101: begin + i1modkByteEn <= ~(256'b0) >> (6'b110101<<2'b10); + end + 6'b110110: begin + i1modkByteEn <= ~(256'b0) >> (6'b110110<<2'b10); + end + 6'b110111: begin + i1modkByteEn <= ~(256'b0) >> (6'b110111<<2'b10); + end + 6'b111000: begin + i1modkByteEn <= ~(256'b0) >> (6'b111000<<2'b10); + end + 6'b111001: begin + i1modkByteEn <= ~(256'b0) >> (6'b111001<<2'b10); + end + 6'b111010: begin + i1modkByteEn <= ~(256'b0) >> (6'b111010<<2'b10); + end + 6'b111011: begin + i1modkByteEn <= ~(256'b0) >> (6'b111011<<2'b10); + end + 6'b111100: begin + i1modkByteEn <= ~(256'b0) >> (6'b111100<<2'b10); + end + 6'b111101: begin + i1modkByteEn <= ~(256'b0) >> (6'b111101<<2'b10); + end + 6'b111110: begin + i1modkByteEn <= ~(256'b0) >> (6'b111110<<2'b10); + end + 6'b111111: begin + i1modkByteEn <= ~(256'b0) >> (6'b111111<<2'b10); + end + default: begin + i1modkByteEn <= ~(256'b0); + end + endcase +end + +// compute Byte Enable +always @ (posedge clk) +begin + if ((nextState == `cMULT_COL && currentState != `cMULT_COL) || (currentState == `cSTORE_MO) || currentRowState == `cLOAD_ROW_INC_J) + byteEn <= i1modkByteEn; + else + byteEn <= 256'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; +end + +// update FSM state register +always @ (posedge clk) +begin + if (start_in == 1'b1) + currentState <= `cSETUP; + else + currentState <= nextState; + if (start == 1'b1) + currentRowState <= `cDONE_FETCH_ROW; + else + currentRowState <= nextRowState; +end + +// delay register for control signals +// control signals are delayed to match latency of operations and/or memory access +always @ (posedge clk) +begin + curReadAddrDelay0 <= curReadAddrDelay1; + curReadAddrDelay1 <= curReadAddrDelay2; + curReadAddrDelay2 <= curReadAddrDelay3; + curReadAddrDelay3 <= curReadAddrDelay4; + curReadAddrDelay4 <= curReadAddrDelay5; + curReadAddrDelay5 <= curReadAddrDelay6; + curReadAddrDelay6 <= curReadAddrDelay7; + curReadAddrDelay7 <= curReadAddrDelay8; + curReadAddrDelay8 <= curReadAddrDelay9; + curReadAddrDelay9 <= curReadAddrDelay10; + curReadAddrDelay10 <= curReadAddrDelay11; + curReadAddrDelay11 <= msIdxCounter; + + curWriteAddrDelay0 <= curWriteAddrDelay1; + curWriteAddrDelay1 <= curWriteAddrDelay2; + curWriteAddrDelay2 <= curWriteAddrDelay3; + curWriteAddrDelay3 <= curWriteAddrDelay4; + if (currentState == `cFETCH_COL) + curWriteAddrDelay4 <= diagIdxCounter; + else + curWriteAddrDelay4 <= curWriteAddrDelay5; + curWriteAddrDelay5 <= curWriteAddrDelay6; + curWriteAddrDelay6 <= curWriteAddrDelay7; + curWriteAddrDelay7 <= curWriteAddrDelay8; + curWriteAddrDelay8 <= curWriteAddrDelay9; + curWriteAddrDelay9 <= curWriteAddrDelay10; + curWriteAddrDelay10 <= curWriteAddrDelay11; + curWriteAddrDelay11 <= curWriteAddrDelay12; + curWriteAddrDelay12 <= curWriteAddrDelay13; + curWriteAddrDelay13 <= curWriteAddrDelay14; + curWriteAddrDelay14 <= curWriteAddrDelay15; + if (currentState == `cMULT_COL) + curWriteAddrDelay15 <= leftIdxCounter; + else + curWriteAddrDelay15 <= curWriteAddrDelay16; + curWriteAddrDelay16 <= curWriteAddrDelay17; + curWriteAddrDelay17 <= curWriteAddrDelay18; + curWriteAddrDelay18 <= curWriteAddrDelay19; + curWriteAddrDelay19 <= curWriteAddrDelay20; + curWriteAddrDelay20 <= curWriteAddrDelay21; + curWriteAddrDelay21 <= curWriteAddrDelay22; + curWriteAddrDelay22 <= curWriteAddrDelay23; + curWriteAddrDelay23 <= curWriteAddrDelay24; + curWriteAddrDelay24 <= curWriteAddrDelay25; + curWriteAddrDelay25 <= curWriteAddrDelay26; + curWriteAddrDelay26 <= curWriteAddrDelay27; + curWriteAddrDelay27 <= curWriteAddrDelay28; + curWriteAddrDelay28 <= curWriteAddrDelay29; + curWriteAddrDelay29 <= curWriteAddrDelay30; + curWriteAddrDelay30 <= curWriteAddrDelay31; + curWriteAddrDelay31 <= msIdxCounter; + + writeByteEnDelay0 <= writeByteEnDelay1; + writeByteEnDelay1 <= writeByteEnDelay2; + writeByteEnDelay2 <= writeByteEnDelay3; + writeByteEnDelay3 <= writeByteEnDelay4; + if (mode[0] == 1'b1) + writeByteEnDelay4 <= ~0; + else if (currentState == `cFETCH_COL) + writeByteEnDelay4 <= byteEn; + else + writeByteEnDelay4 <= writeByteEnDelay5; + writeByteEnDelay5 <= writeByteEnDelay6; + writeByteEnDelay6 <= writeByteEnDelay7; + writeByteEnDelay7 <= writeByteEnDelay8; + writeByteEnDelay8 <= writeByteEnDelay9; + writeByteEnDelay9 <= writeByteEnDelay10; + writeByteEnDelay10 <= writeByteEnDelay11; + writeByteEnDelay11 <= writeByteEnDelay12; + writeByteEnDelay12 <= writeByteEnDelay13; + writeByteEnDelay13 <= writeByteEnDelay14; + writeByteEnDelay14 <= writeByteEnDelay15; + if (currentState == `cMULT_COL) + writeByteEnDelay15 <= byteEn; + else + writeByteEnDelay15 <= writeByteEnDelay16; + writeByteEnDelay16 <= writeByteEnDelay17; + writeByteEnDelay17 <= writeByteEnDelay18; + writeByteEnDelay18 <= writeByteEnDelay19; + writeByteEnDelay19 <= writeByteEnDelay20; + writeByteEnDelay20 <= writeByteEnDelay21; + writeByteEnDelay21 <= writeByteEnDelay22; + writeByteEnDelay22 <= writeByteEnDelay23; + writeByteEnDelay23 <= writeByteEnDelay24; + writeByteEnDelay24 <= writeByteEnDelay25; + writeByteEnDelay25 <= writeByteEnDelay26; + writeByteEnDelay26 <= writeByteEnDelay27; + writeByteEnDelay27 <= writeByteEnDelay28; + writeByteEnDelay28 <= writeByteEnDelay29; + writeByteEnDelay29 <= writeByteEnDelay30; + writeByteEnDelay30 <= writeByteEnDelay31; + writeByteEnDelay31 <= byteEn; + + curWriteSelDelay[0] <= curWriteSelDelay[1]; + curWriteSelDelay[1] <= curWriteSelDelay[2]; + curWriteSelDelay[2] <= curWriteSelDelay[3]; + curWriteSelDelay[3] <= curWriteSelDelay[4]; + curWriteSelDelay[4] <= curWriteSelDelay[5]; + curWriteSelDelay[5] <= curWriteSelDelay[6]; + curWriteSelDelay[6] <= curWriteSelDelay[7]; + curWriteSelDelay[7] <= curWriteSelDelay[8]; + curWriteSelDelay[8] <= curWriteSelDelay[9]; + curWriteSelDelay[9] <= curWriteSelDelay[10]; + curWriteSelDelay[10] <= curWriteSelDelay[11]; + curWriteSelDelay[11] <= curWriteSelDelay[12]; + curWriteSelDelay[12] <= curWriteSelDelay[13]; + curWriteSelDelay[13] <= curWriteSelDelay[14]; + curWriteSelDelay[14] <= curWriteSelDelay[15]; + if (currentState == `cMULT_COL) + curWriteSelDelay[15] <= 1'b0; + else + curWriteSelDelay[15] <= 1'b1; + + curWriteEnDelay[0] <= curWriteEnDelay[1]; + curWriteEnDelay[1] <= curWriteEnDelay[2]; + curWriteEnDelay[2] <= curWriteEnDelay[3]; + curWriteEnDelay[3] <= curWriteEnDelay[4]; + curWriteEnDelay[4] <= curWriteEnDelay[5]; + curWriteEnDelay[5] <= curWriteEnDelay[6]; + curWriteEnDelay[6] <= curWriteEnDelay[7]; + curWriteEnDelay[7] <= curWriteEnDelay[8]; + curWriteEnDelay[8] <= curWriteEnDelay[9]; + curWriteEnDelay[9] <= curWriteEnDelay[10]; + curWriteEnDelay[10] <= curWriteEnDelay[11]; + curWriteEnDelay[11] <= curWriteEnDelay[12]; + curWriteEnDelay[12] <= curWriteEnDelay[13]; + curWriteEnDelay[13] <= curWriteEnDelay[14]; + curWriteEnDelay[14] <= curWriteEnDelay[15]; + if (currentState == `cMULT_COL) + curWriteEnDelay[15] <= 1'b1; + else + curWriteEnDelay[15] <= curWriteEnDelay[16]; + curWriteEnDelay[16] <= curWriteEnDelay[17]; + curWriteEnDelay[17] <= curWriteEnDelay[18]; + curWriteEnDelay[18] <= curWriteEnDelay[19]; + curWriteEnDelay[19] <= curWriteEnDelay[20]; + curWriteEnDelay[20] <= curWriteEnDelay[21]; + curWriteEnDelay[21] <= curWriteEnDelay[22]; + curWriteEnDelay[22] <= curWriteEnDelay[23]; + curWriteEnDelay[23] <= curWriteEnDelay[24]; + curWriteEnDelay[24] <= curWriteEnDelay[25]; + curWriteEnDelay[25] <= curWriteEnDelay[26]; + curWriteEnDelay[26] <= curWriteEnDelay[27]; + curWriteEnDelay[27] <= curWriteEnDelay[28]; + curWriteEnDelay[28] <= curWriteEnDelay[29]; + curWriteEnDelay[29] <= curWriteEnDelay[30]; + curWriteEnDelay[30] <= curWriteEnDelay[31]; + if (currentState == `cMULT_SUB) + curWriteEnDelay[31] <= 1'b1; + else + curWriteEnDelay[31] <= 1'b0; + + leftWriteSelDelay[0] <= leftWriteSelDelay[1]; + leftWriteSelDelay[1] <= leftWriteSelDelay[2]; + leftWriteSelDelay[2] <= leftWriteSelDelay[3]; + leftWriteSelDelay[3] <= leftWriteSelDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteSelDelay[4] <= 1'b0; + else + leftWriteSelDelay[4] <= 1'b1; + + leftWriteEnDelay[0] <= leftWriteEnDelay[1]; + leftWriteEnDelay[1] <= leftWriteEnDelay[2]; + leftWriteEnDelay[2] <= leftWriteEnDelay[3]; + leftWriteEnDelay[3] <= leftWriteEnDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteEnDelay[4] <= 1'b1; + else + leftWriteEnDelay[4] <= leftWriteEnDelay[5]; + leftWriteEnDelay[5] <= leftWriteEnDelay[6]; + leftWriteEnDelay[6] <= leftWriteEnDelay[7]; + leftWriteEnDelay[7] <= leftWriteEnDelay[8]; + leftWriteEnDelay[8] <= leftWriteEnDelay[9]; + leftWriteEnDelay[9] <= leftWriteEnDelay[10]; + leftWriteEnDelay[10] <= leftWriteEnDelay[11]; + leftWriteEnDelay[11] <= leftWriteEnDelay[12]; + leftWriteEnDelay[12] <= leftWriteEnDelay[13]; + leftWriteEnDelay[13] <= leftWriteEnDelay[14]; + leftWriteEnDelay[14] <= leftWriteEnDelay[15]; + if (currentState == `cMULT_COL) + leftWriteEnDelay[15] <= 1'b1; + else + leftWriteEnDelay[15] <= leftWriteEnDelay[16]; + leftWriteEnDelay[16] <= leftWriteEnDelay[17]; + leftWriteEnDelay[17] <= leftWriteEnDelay[18]; + leftWriteEnDelay[18] <= leftWriteEnDelay[19]; + leftWriteEnDelay[19] <= leftWriteEnDelay[20]; + leftWriteEnDelay[20] <= leftWriteEnDelay[21]; + leftWriteEnDelay[21] <= leftWriteEnDelay[22]; + leftWriteEnDelay[22] <= leftWriteEnDelay[23]; + leftWriteEnDelay[23] <= leftWriteEnDelay[24]; + leftWriteEnDelay[24] <= leftWriteEnDelay[25]; + leftWriteEnDelay[25] <= leftWriteEnDelay[26]; + leftWriteEnDelay[26] <= leftWriteEnDelay[27]; + leftWriteEnDelay[27] <= leftWriteEnDelay[28]; + leftWriteEnDelay[28] <= leftWriteEnDelay[29]; + leftWriteEnDelay[29] <= leftWriteEnDelay[30]; + leftWriteEnDelay[30] <= leftWriteEnDelay[31]; + if (currentState == `cMULT_SUB && (mode == 0 || (mode == 1 && j == i1))) + leftWriteEnDelay[31] <= 1'b1; + else + leftWriteEnDelay[31] <= 1'b0; + + topWriteAddrDelay0 <= topWriteAddrDelay1; + topWriteAddrDelay1 <= topWriteAddrDelay2; + topWriteAddrDelay2 <= topWriteAddrDelay3; + topWriteAddrDelay3 <= topWriteAddrDelay4; + if (currentRowState == `cFETCH_ROW) + topWriteAddrDelay4 <= nextTopIdxCounter; + else + topWriteAddrDelay4 <= topWriteAddrDelay5; + topWriteAddrDelay5 <= topWriteAddrDelay6; + topWriteAddrDelay6 <= topWriteAddrDelay7; + topWriteAddrDelay7 <= topWriteAddrDelay8; + topWriteAddrDelay8 <= topWriteAddrDelay9; + topWriteAddrDelay9 <= topWriteAddrDelay10; + topWriteAddrDelay10 <= topWriteAddrDelay11; + topWriteAddrDelay11 <= topWriteAddrDelay12; + topWriteAddrDelay12 <= topWriteAddrDelay13; + topWriteAddrDelay13 <= topWriteAddrDelay14; + topWriteAddrDelay14 <= topWriteAddrDelay15; + topWriteAddrDelay15 <= topWriteAddrDelay16; + topWriteAddrDelay16 <= topWriteAddrDelay17; + topWriteAddrDelay17 <= topWriteAddrDelay18; + topWriteAddrDelay18 <= topWriteAddrDelay19; + topWriteAddrDelay19 <= topWriteAddrDelay20; + topWriteAddrDelay20 <= topWriteAddrDelay21; + topWriteAddrDelay21 <= topWriteAddrDelay22; + topWriteAddrDelay22 <= topWriteAddrDelay23; + topWriteAddrDelay23 <= topWriteAddrDelay24; + topWriteAddrDelay24 <= topWriteAddrDelay25; + topWriteAddrDelay25 <= topWriteAddrDelay26; + topWriteAddrDelay26 <= topWriteAddrDelay27; + topWriteAddrDelay27 <= topWriteAddrDelay28; + topWriteAddrDelay28 <= topWriteAddrDelay29; + topWriteAddrDelay29 <= topWriteAddrDelay30; + topWriteAddrDelay30 <= topWriteAddrDelay31; + topWriteAddrDelay31 <= nextTopIdxCounter; + + topWriteEnDelay[0] <= topWriteEnDelay[1]; + topWriteEnDelay[1] <= topWriteEnDelay[2]; + topWriteEnDelay[2] <= topWriteEnDelay[3]; + topWriteEnDelay[3] <= topWriteEnDelay[4]; + if (currentRowState == `cFETCH_ROW) + topWriteEnDelay[4] <= 1'b1; + else + topWriteEnDelay[4] <= topWriteEnDelay[5]; + topWriteEnDelay[5] <= topWriteEnDelay[6]; + topWriteEnDelay[6] <= topWriteEnDelay[7]; + topWriteEnDelay[7] <= topWriteEnDelay[8]; + topWriteEnDelay[8] <= topWriteEnDelay[9]; + topWriteEnDelay[9] <= topWriteEnDelay[10]; + topWriteEnDelay[10] <= topWriteEnDelay[11]; + topWriteEnDelay[11] <= topWriteEnDelay[12]; + topWriteEnDelay[12] <= topWriteEnDelay[13]; + topWriteEnDelay[13] <= topWriteEnDelay[14]; + topWriteEnDelay[14] <= topWriteEnDelay[15]; + topWriteEnDelay[15] <= topWriteEnDelay[16]; + topWriteEnDelay[16] <= topWriteEnDelay[17]; + topWriteEnDelay[17] <= topWriteEnDelay[18]; + topWriteEnDelay[18] <= topWriteEnDelay[19]; + topWriteEnDelay[19] <= topWriteEnDelay[20]; + topWriteEnDelay[20] <= topWriteEnDelay[21]; + topWriteEnDelay[21] <= topWriteEnDelay[22]; + topWriteEnDelay[22] <= topWriteEnDelay[23]; + topWriteEnDelay[23] <= topWriteEnDelay[24]; + topWriteEnDelay[24] <= topWriteEnDelay[25]; + topWriteEnDelay[25] <= topWriteEnDelay[26]; + topWriteEnDelay[26] <= topWriteEnDelay[27]; + topWriteEnDelay[27] <= topWriteEnDelay[28]; + topWriteEnDelay[28] <= topWriteEnDelay[29]; + topWriteEnDelay[29] <= topWriteEnDelay[30]; + topWriteEnDelay[30] <= topWriteEnDelay[31]; + topWriteEnDelay[31] <= writeRow; + + topWriteSelDelay0 <= topWriteSelDelay1; + topWriteSelDelay1 <= topWriteSelDelay2; + topWriteSelDelay2 <= topWriteSelDelay3; + topWriteSelDelay3 <= topWriteSelDelay4; + if (currentRowState == `cFETCH_ROW || currentState == `cUPDATE_J && i1 == 1) + topWriteSelDelay4 <= imodk; + else + topWriteSelDelay4 <= topWriteSelDelay5; + topWriteSelDelay5 <= topWriteSelDelay6; + topWriteSelDelay6 <= topWriteSelDelay7; + topWriteSelDelay7 <= topWriteSelDelay8; + topWriteSelDelay8 <= topWriteSelDelay9; + topWriteSelDelay9 <= topWriteSelDelay10; + topWriteSelDelay10 <= topWriteSelDelay11; + topWriteSelDelay11 <= topWriteSelDelay12; + topWriteSelDelay12 <= topWriteSelDelay13; + topWriteSelDelay13 <= topWriteSelDelay14; + topWriteSelDelay14 <= topWriteSelDelay15; + topWriteSelDelay15 <= topWriteSelDelay16; + topWriteSelDelay16 <= topWriteSelDelay17; + topWriteSelDelay17 <= topWriteSelDelay18; + topWriteSelDelay18 <= topWriteSelDelay19; + topWriteSelDelay19 <= topWriteSelDelay20; + topWriteSelDelay20 <= topWriteSelDelay21; + topWriteSelDelay21 <= topWriteSelDelay22; + topWriteSelDelay22 <= topWriteSelDelay23; + topWriteSelDelay23 <= topWriteSelDelay24; + topWriteSelDelay24 <= topWriteSelDelay25; + topWriteSelDelay25 <= topWriteSelDelay26; + topWriteSelDelay26 <= topWriteSelDelay27; + topWriteSelDelay27 <= topWriteSelDelay28; + topWriteSelDelay28 <= topWriteSelDelay29; + topWriteSelDelay29 <= topWriteSelDelay30; + topWriteSelDelay30 <= topWriteSelDelay31; + topWriteSelDelay31 <= i1modk; + + topSourceSelDelay[0] <= topSourceSelDelay[1]; + topSourceSelDelay[1] <= topSourceSelDelay[2]; + topSourceSelDelay[2] <= topSourceSelDelay[3]; + topSourceSelDelay[3] <= topSourceSelDelay[4]; + if (start == 1'b1) + topSourceSelDelay[4] <= 1'b0; + else if (currentState == `cSTORE_MO) + topSourceSelDelay[4] <= 1'b1; + + leftReadAddrDelay0 <= leftIdxCounter; + + + diagEnDelay[0] <= diagEnDelay[1]; + diagEnDelay[1] <= diagEnDelay[2]; + diagEnDelay[2] <= diagEnDelay[3]; + diagEnDelay[3] <= diagEnDelay[4]; + diagEnDelay[4] <= diagEnDelay[5]; + diagEnDelay[5] <= (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2); + + MOEnDelay[0] <= MOEnDelay[1]; + MOEnDelay[1] <= MOEnDelay[2]; + MOEnDelay[2] <= MOEnDelay[3]; + MOEnDelay[3] <= MOEnDelay[4]; + MOEnDelay[4] <= MOEnDelay[5]; + if (currentState == `cSTORE_MO || currentRowState == `cLOAD_ROW_INC_J) + MOEnDelay[5] <= 1'b1; + else + MOEnDelay[5] <= 1'b0; +end + +// output contorl signals +always @ (posedge clk) +begin + if (currentState == `cFETCH_COL) + curReadAddr <= diagIdxCounter; + else if (currentRowState == `cFETCH_ROW) + curReadAddr <= readRowCounter; + else + curReadAddr <= curReadAddrDelay0; + curWriteAddr <= curWriteAddrDelay0; + curWriteByteEn <= writeByteEnDelay0; + curWriteSel <= curWriteSelDelay; + curWriteEn <= curWriteEnDelay; + + if (currentState == `cMULT_COL) + leftReadAddr <= leftIdxCounter; + else + leftReadAddr <= leftReadAddrDelay0; + leftWriteAddr <= curWriteAddrDelay0; + leftWriteByteEn <= writeByteEnDelay0; + leftWriteSel <= leftWriteSelDelay; + leftWriteEn <= leftWriteEnDelay; + + if (currentState == `cSTORE_DIAG) + topReadAddr <= nextTopIdx; +else if (currentState == `cSTORE_DIAG2) + topReadAddr <= nextTopIdx2; + else + topReadAddr <= curTopIdx; + topWriteAddr <= topWriteAddrDelay0; + topWriteEn <= topWriteEnDelay; + topWriteSel <= topWriteSelDelay0; + topSourceSel <= topSourceSelDelay; + + MOSel <= ~(currentState == `cFIND_REC); +if (currentState == `cFIND_REC) + MOEn <= 1'b1; + else + MOEn <= MOEnDelay; + + diagEn <= diagEnDelay; + + if (currentState == `cDONE) + done <= 1'b1; + else + done <= 1'b0; +end + +endmodule + +module ram ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram1 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram2 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram3 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 2048'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 2048'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + + +module top_ram ( + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + //parameter TOPSIZE = 16384, TOPSIZEWIDTH = 14, TOPWIDTH = 32; + + input clk; + input [32-1:0] data; + input [14-1:0] rdaddress; + input [14-1:0] wraddress; + input wren; + output [32-1:0] q; + + wire [32-1:0] sub_wire0; + wire [32-1:0] q; + wire [32-1:0] junk_output; + assign q = sub_wire0 | dummy; + wire[32-1:0] dummy; + assign dummy = junk_output & 32'b0; + dual_port_ram inst2( + .clk (clk), + .we1(wren), + .we2(1'b0), + .data1(data), + .data2(data), + .out1(junk_output), + .out2(sub_wire0), + .addr1(wraddress), + .addr2(rdaddress)); + +endmodule + +module mult_add (clk, A, B, C, mult_result, add_result); +//parameter PRECISION = 32; +input clk; +input [32-1:0] A, B, C; +output [32-1:0] mult_result, add_result; +reg [32-1:0] mult_result; +reg [32-1:0] add_result; +wire [32-1:0] mult_comp_result; +reg [32-1:0] add_a, add_b; +wire [32-1:0] addition_result; +wire [31:0] dummy_wire; +assign dummy_wire = mult_comp_result>>2'b10; +//divsp MUL(.clk(clk), .rmode(2'b00), .fpu_op(3'b010), .opa(A), .opb(B), .ans(mult_comp_result) ); +wire [4:0]dummy_wire_2; +fpmul MUL(.clk(clk), .a(A), .b(B), .y_out(mult_comp_result), .control(2'b00), .flags(dummy_wire_2)); +fpu_add ADD(.clock(clk), .a1(C), .b1(dummy_wire), .sum(addition_result)); +always @ (posedge clk) +begin + add_result <= addition_result; + mult_result <= mult_comp_result[31:0]; +end +endmodule + + +//`define rFIFOINPUTWIDTH 64 +`define rFIFOSIZE 512 +`define rFIFOSIZEWIDTH 9 +`define rFIFOOUTPUTWIDTH 2048 +`define rFIFORSIZEWIDTH 4 + `define wFIFOINPUTWIDTH 13'b0100000000000 + `define wFIFOSIZE 6'b010000 + `define wFIFOSIZEWIDTH 4'b0100 + `define wFIFOOUTPUTWIDTH 8'b01000000 + `define wFIFORSIZEWIDTH 5'b01001 + //for addr_fifo +`define aFIFOSIZE 6'b010000 +`define aFIFOSIZEWIDTH 4'b0100 +`define aFIFOWIDTH 5'b01000 +//for memfifo +`define mFIFOSIZE 16 +`define mFIFOSIZEWIDTH 4 +//`define mFIFOWIDTH 28 + +`define BURSTLEN 3'b010 +`define BURSTWIDTH 3'b010 +`define DATAWIDTH 13'b0100000000000 +`define DATANUMBYTES 10'b0100000000 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define FIFOSIZE 6'b010000 +`define FIFOSIZEWIDTH 4'b0100 +`define RAMWIDTH 13'b0100000000000 +`define RAMNUMBYTES 10'b0100000000 +`define RAMSIZEWIDTH 5'b01000 +`define RATIO 7'b0100000 +`define RAMLAT 4'b0101 + +`define dIDLE 0 +`define dWRITE 1 +`define dREAD 2 + +module DataTransferUnit (clk, dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, + ram_read_addr, ram_read_data, ram_write_byte_en, ram_write_data, ram_write_addr, ram_write_en, + mem_rdata, mem_rdata_valid, mem_ready, mem_wdata_req, reset_n, + burst_begin, mem_local_addr, mem_be, mem_read_req, mem_size, mem_wdata, mem_write_req + ); + +output burst_begin; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +output [`MEMCONNUMBYTES-1: 0] mem_be; +output mem_read_req; +output [`BURSTWIDTH-1:0] mem_size; +output [`MEMCONWIDTH-1:0] mem_wdata; +output mem_write_req; +input clk; +input [`MEMCONWIDTH-1:0] mem_rdata; +input mem_rdata_valid; +input mem_ready; +input mem_wdata_req; +input reset_n; + +input dtu_write_req; +input dtu_read_req; +input [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +input [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +input [7:0] dtu_size; +output dtu_ack; +output dtu_done; + +output[`RAMWIDTH-1:0] ram_write_data; +input[`RAMWIDTH-1:0] ram_read_data; +output[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +output[`RAMNUMBYTES-1:0] ram_write_byte_en; +output ram_write_en; + +reg[`DDRSIZEWIDTH-1:0] mem_addr0; +reg[`DDRSIZEWIDTH-1:0] mem_addr1; +reg[`DDRSIZEWIDTH-1:0] mem_addr2; +reg[`DDRSIZEWIDTH-1:0] mem_addr3; +reg[`DDRSIZEWIDTH-1:0] mem_addr4; +reg[`DDRSIZEWIDTH-1:0] mem_addr5; + +reg [1:0] state; +wire [`DATAWIDTH-1:0] rdata, ram_write_dataw, ram_read_dataw; + +wire [`RAMSIZEWIDTH-1:0] rfifo_addr; +reg [`RAMLAT-1:0]fifo_write_reg; +reg [`RAMLAT-1:0]write_req_reg; +reg [`RAMLAT-1:0]read_req_reg; +reg [0:0]fifo_read_reg; +reg rdata_valid; +reg [1:0]test_complete_reg; +reg [`BURSTWIDTH-1:0] size_count0; +reg [`BURSTWIDTH-1:0] size_count1; +reg [`BURSTWIDTH-1:0] size_count2; +reg [`BURSTWIDTH-1:0] size_count3; +reg [`BURSTWIDTH-1:0] size_count4; + +reg [`RAMSIZEWIDTH-1:0] size; +reg [`RAMSIZEWIDTH-1:0]ram_addr0; +reg [`RAMSIZEWIDTH-1:0]ram_addr1; +reg [`RAMSIZEWIDTH-1:0]ram_addr2; +reg [`RAMSIZEWIDTH-1:0]ram_addr3; +reg [`RAMSIZEWIDTH-1:0]ram_addr4; + +reg [5:0] data_count; +reg ram_write_en_reg; + +wire read_req; +wire write_req; +wire [`FIFOSIZEWIDTH-1:0] wfifo_count; +wire rfull, wempty, rempty, rdcmd_empty, wrcmd_full, wrcmd_empty, rdata_empty; +wire [`DATAWIDTH-1:0] mem_data; +wire not_stall; +wire fifo_write, fifo_read; +wire rdata_req; +wire [`BURSTWIDTH+`DDRSIZEWIDTH+1:0] wrmem_cmd, rdmem_cmd; +wire mem_cmd_ready, mem_cmd_issue; + +// FIFOs to interact with off-chip memory +memcmd_fifo cmd_store( + //.aclr(~reset_n), + //.rdclk(phy_clk), + .clk(clk), + .data(wrmem_cmd), + .rdreq(mem_cmd_ready), + //.rdempty(rdcmd_empty), + .wrreq(mem_cmd_issue), + .full(wrcmd_full), + .empty(wrcmd_empty), + .q(rdmem_cmd) + ); + +wfifo wdata_store( + //.rdclk(phy_clk), + .clk(clk), + .data(mem_data), + .rdreq(mem_wdata_req), + .wrreq(fifo_write), + .empty(wempty), + .q(mem_wdata), + .usedw(wfifo_count) + ); + +addr_fifo raddress_store ( + .clk(clk), + .data(ram_addr3), + .wrreq(fifo_read), + .rdreq(rdata_req), + .empty(rempty), + .full(rfull), + .q(rfifo_addr) + ); + +rfifo rdata_store( + .clk(clk), + .data(mem_rdata), + .rdreq(rdata_req), + //.wrclk(phy_clk), + .wrreq(mem_rdata_valid), + .empty(rdata_empty), + .q(rdata) + ); + +assign mem_cmd_ready = (mem_ready == 1'b1);// && (rdcmd_empty == 0); +assign mem_cmd_issue = (wrcmd_full == 1'b0) && (write_req == 1 || read_req == 1'b1 || wrcmd_empty == 1'b1); +assign wrmem_cmd[27:26] = size_count0; +assign wrmem_cmd[`DDRSIZEWIDTH+1:2] = mem_addr0; +assign wrmem_cmd[1] = read_req; +assign wrmem_cmd[0] = write_req; +assign mem_write_req = rdmem_cmd[0];// && rdcmd_empty == 0; +assign mem_read_req = rdmem_cmd[1];// && rdcmd_empty == 0; +assign mem_local_addr = rdmem_cmd[`DDRSIZEWIDTH+1:2]; +assign burst_begin = 0; +assign mem_size = rdmem_cmd[`BURSTWIDTH+`DDRSIZEWIDTH+1:`DDRSIZEWIDTH+2]; +assign mem_be = ~0; +assign fifo_write = fifo_write_reg[0]; +assign write_req = (not_stall) ? write_req_reg[0] : 0; +assign read_req = (not_stall) ? read_req_reg[0] : 0; +assign fifo_read = (not_stall) ? fifo_read_reg[0] : 0; +assign not_stall = (wfifo_count < `FIFOSIZE-5) && (rfull == 0) && (wrcmd_full == 0); +assign dtu_ack = (state == `dIDLE); +assign dtu_done = (state == `dIDLE) && wempty && rempty; + +assign ram_write_dataw[63:0] = rdata[2047:1984]; +assign mem_data[63:0] = ram_read_dataw[2047:1984]; +assign ram_write_dataw[127:64] = rdata[1983:1920]; +assign mem_data[127:64] = ram_read_dataw[1983:1920]; +assign ram_write_dataw[191:128] = rdata[1919:1856]; +assign mem_data[191:128] = ram_read_dataw[1919:1856]; +assign ram_write_dataw[255:192] = rdata[1855:1792]; +assign mem_data[255:192] = ram_read_dataw[1855:1792]; +assign ram_write_dataw[319:256] = rdata[1791:1728]; +assign mem_data[319:256] = ram_read_dataw[1791:1728]; +assign ram_write_dataw[383:320] = rdata[1727:1664]; +assign mem_data[383:320] = ram_read_dataw[1727:1664]; +assign ram_write_dataw[447:384] = rdata[1663:1600]; +assign mem_data[447:384] = ram_read_dataw[1663:1600]; +assign ram_write_dataw[511:448] = rdata[1599:1536]; +assign mem_data[511:448] = ram_read_dataw[1599:1536]; +assign ram_write_dataw[575:512] = rdata[1535:1472]; +assign mem_data[575:512] = ram_read_dataw[1535:1472]; +assign ram_write_dataw[639:576] = rdata[1471:1408]; +assign mem_data[639:576] = ram_read_dataw[1471:1408]; +assign ram_write_dataw[703:640] = rdata[1407:1344]; +assign mem_data[703:640] = ram_read_dataw[1407:1344]; +assign ram_write_dataw[767:704] = rdata[1343:1280]; +assign mem_data[767:704] = ram_read_dataw[1343:1280]; +assign ram_write_dataw[831:768] = rdata[1279:1216]; +assign mem_data[831:768] = ram_read_dataw[1279:1216]; +assign ram_write_dataw[895:832] = rdata[1215:1152]; +assign mem_data[895:832] = ram_read_dataw[1215:1152]; +assign ram_write_dataw[959:896] = rdata[1151:1088]; +assign mem_data[959:896] = ram_read_dataw[1151:1088]; +assign ram_write_dataw[1023:960] = rdata[1087:1024]; +assign mem_data[1023:960] = ram_read_dataw[1087:1024]; +assign ram_write_dataw[1087:1024] = rdata[1023:960]; +assign mem_data[1087:1024] = ram_read_dataw[1023:960]; +assign ram_write_dataw[1151:1088] = rdata[959:896]; +assign mem_data[1151:1088] = ram_read_dataw[959:896]; +assign ram_write_dataw[1215:1152] = rdata[895:832]; +assign mem_data[1215:1152] = ram_read_dataw[895:832]; +assign ram_write_dataw[1279:1216] = rdata[831:768]; +assign mem_data[1279:1216] = ram_read_dataw[831:768]; +assign ram_write_dataw[1343:1280] = rdata[767:704]; +assign mem_data[1343:1280] = ram_read_dataw[767:704]; +assign ram_write_dataw[1407:1344] = rdata[703:640]; +assign mem_data[1407:1344] = ram_read_dataw[703:640]; +assign ram_write_dataw[1471:1408] = rdata[639:576]; +assign mem_data[1471:1408] = ram_read_dataw[639:576]; +assign ram_write_dataw[1535:1472] = rdata[575:512]; +assign mem_data[1535:1472] = ram_read_dataw[575:512]; +assign ram_write_dataw[1599:1536] = rdata[511:448]; +assign mem_data[1599:1536] = ram_read_dataw[511:448]; +assign ram_write_dataw[1663:1600] = rdata[447:384]; +assign mem_data[1663:1600] = ram_read_dataw[447:384]; +assign ram_write_dataw[1727:1664] = rdata[383:320]; +assign mem_data[1727:1664] = ram_read_dataw[383:320]; +assign ram_write_dataw[1791:1728] = rdata[319:256]; +assign mem_data[1791:1728] = ram_read_dataw[319:256]; +assign ram_write_dataw[1855:1792] = rdata[255:192]; +assign mem_data[1855:1792] = ram_read_dataw[255:192]; +assign ram_write_dataw[1919:1856] = rdata[191:128]; +assign mem_data[1919:1856] = ram_read_dataw[191:128]; +assign ram_write_dataw[1983:1920] = rdata[127:64]; +assign mem_data[1983:1920] = ram_read_dataw[127:64]; +assign ram_write_dataw[2047:1984] = rdata[63:0]; +assign mem_data[2047:1984] = ram_read_dataw[63:0]; +assign ram_write_data = ram_write_dataw[2047:0]; +assign ram_read_dataw[2047:0] = ram_read_data; +assign ram_write_addr = rfifo_addr; +assign ram_read_addr = ram_addr4; +assign ram_write_byte_en = ~0; +assign ram_write_en = ram_write_en_reg; +assign rdata_req = !rdata_empty; + +// FSM to produce off-chip memory commands +always @ (posedge clk) +begin + if (reset_n == 1'b0) + begin + state <= `dIDLE; + end + else + begin + case (state) + `dIDLE: + begin + if (dtu_write_req) + state <= `dWRITE; + else if (dtu_read_req) + state <= `dREAD; + else + state <= `dIDLE; + end + `dWRITE: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dWRITE; + end + `dREAD: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dREAD; + end + default: + begin + state <= `dIDLE; + end + endcase + end +end + +always @ (posedge clk) +begin + + if (reset_n == 0) + begin + size <= 0; + data_count <= 0; + size_count4 <= 1; + mem_addr5 <= 0; + ram_addr4 <= 0; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (state == `dIDLE) + begin + size <= dtu_size; + size_count4 <= `BURSTLEN; + mem_addr5 <= dtu_mem_addr; + ram_addr4 <= dtu_ram_addr; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= 1'b0; + fifo_read_reg[0] <= 1'b0; + read_req_reg[`RAMLAT-1] <= 1'b0; + data_count <= 0; + end + else if (data_count >= `BURSTLEN && not_stall) + begin + data_count <= data_count - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (size == 0 && data_count == 0 && not_stall==1'b1) + begin + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (size == 0 && not_stall==1'b1) + begin + size_count4 <= data_count[`BURSTWIDTH-1:0]; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (not_stall==1'b1) + begin + size <= size - 1; + data_count <= data_count + `RATIO - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + ram_addr4 <= ram_addr4+1; + fifo_write_reg[`RAMLAT-1] <= state == `dWRITE; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= state == `dREAD; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else + begin + fifo_write_reg[`RAMLAT-1] <= 0; + end +end + + +always @ (posedge clk) +begin + if (reset_n == 0) + begin + fifo_write_reg[0] <= 1'b0; + fifo_write_reg[1] <= 1'b0; + fifo_write_reg[2] <= 1'b0; + fifo_write_reg[3] <= 1'b0; + end + else + begin + fifo_write_reg[0] <= fifo_write_reg[1]; + fifo_write_reg[1] <= fifo_write_reg[2]; + fifo_write_reg[2] <= fifo_write_reg[3]; + fifo_write_reg[3] <= fifo_write_reg[4]; + end + + if (reset_n == 1'b0) + begin + mem_addr0 <= 0; + ram_addr0 <= 0; + size_count0 <= 1; + write_req_reg[0] <= 0; + read_req_reg[0] <= 0; + mem_addr1 <= 0; + ram_addr1 <= 0; + size_count1 <= 1; + write_req_reg[1] <= 0; + read_req_reg[1] <= 0; + mem_addr2 <= 0; + ram_addr2 <= 0; + size_count2 <= 1; + write_req_reg[2] <= 0; + read_req_reg[2] <= 0; + mem_addr3 <= 0; + ram_addr3 <= 0; + size_count3 <= 1; + write_req_reg[3] <= 0; + read_req_reg[3] <= 0; + mem_addr4 <= 0; + end + else if (not_stall) + begin + size_count0 <= size_count1; + mem_addr0 <= mem_addr1; + ram_addr0 <= ram_addr1; + write_req_reg[0] <= write_req_reg[1]; + read_req_reg[0] <= read_req_reg[1]; + size_count1 <= size_count2; + mem_addr1 <= mem_addr2; + ram_addr1 <= ram_addr2; + write_req_reg[1] <= write_req_reg[2]; + read_req_reg[1] <= read_req_reg[2]; + size_count2 <= size_count3; + mem_addr2 <= mem_addr3; + ram_addr2 <= ram_addr3; + write_req_reg[2] <= write_req_reg[3]; + read_req_reg[2] <= read_req_reg[3]; + size_count3 <= size_count4; + mem_addr3 <= mem_addr4; + ram_addr3 <= ram_addr4; + write_req_reg[3] <= write_req_reg[4]; + read_req_reg[3] <= read_req_reg[4]; + mem_addr4 <= mem_addr5; + end + + ram_write_en_reg <= rdata_req; +end + +endmodule + +module rfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q + ); + + + input clk; + input wrreq; + input rdreq; + input [`rFIFOINPUTWIDTH-1:0] data; + output empty; + output [`rFIFOOUTPUTWIDTH-1:0] q; + + reg [`rFIFORSIZEWIDTH-1:0] wr_pointer; + reg [`rFIFORSIZEWIDTH-1:0] rd_pointer; + reg [`rFIFORSIZEWIDTH:0] status_cnt; + reg [`rFIFOOUTPUTWIDTH-1:0] q ; + reg[4:0] counter; + wire [`rFIFOINPUTWIDTH-1:0] data_ram; +assign empty = (status_cnt == 10'b0000000000); +wire [`rFIFOINPUTWIDTH-1:0]junk_input; +wire [`rFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 64'b0000000000000000000000000000000000000000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q[`rFIFOINPUTWIDTH-1:0] <= data_ram; +else if (counter == 1) + q[127:64] <= data_ram; +else if (counter == 2) + q[191:128] <= data_ram; +else if (counter == 3) + q[255:192] <= data_ram; +else if (counter == 4) + q[319:256] <= data_ram; +else if (counter == 5) + q[383:320] <= data_ram; +else if (counter == 6) + q[447:384] <= data_ram; +else if (counter == 7) + q[511:448] <= data_ram; +else if (counter == 8) + q[575:512] <= data_ram; +else if (counter == 9) + q[639:576] <= data_ram; +else if (counter == 10) + q[703:640] <= data_ram; +else if (counter == 11) + q[767:704] <= data_ram; +else if (counter == 12) + q[831:768] <= data_ram; +else if (counter == 13) + q[895:832] <= data_ram; +else if (counter == 14) + q[959:896] <= data_ram; +else if (counter == 15) + q[1023:960] <= data_ram; +else if (counter == 16) + q[1087:1024] <= data_ram; +else if (counter == 17) + q[1151:1088] <= data_ram; +else if (counter == 18) + q[1215:1152] <= data_ram; +else if (counter == 19) + q[1279:1216] <= data_ram; +else if (counter == 20) + q[1343:1280] <= data_ram; +else if (counter == 21) + q[1407:1344] <= data_ram; +else if (counter == 22) + q[1471:1408] <= data_ram; +else if (counter == 23) + q[1535:1472] <= data_ram; +else if (counter == 24) + q[1599:1536] <= data_ram; +else if (counter == 25) + q[1663:1600] <= data_ram; +else if (counter == 26) + q[1727:1664] <= data_ram; +else if (counter == 27) + q[1791:1728] <= data_ram; +else if (counter == 28) + q[1855:1792] <= data_ram; +else if (counter == 29) + q[1919:1856] <= data_ram; +else if (counter == 30) + q[1983:1920] <= data_ram; +else if (counter == 31) + q[2047:1984] <= data_ram; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; +// Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module wfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q, + usedw + ); + + input clk; + input wrreq; + input rdreq; + input [`wFIFOINPUTWIDTH-1:0] data; + output empty; + output [`wFIFOOUTPUTWIDTH-1:0] q; + output [`wFIFOSIZEWIDTH-1:0] usedw; +//-----------Internal variables------------------- +reg [`wFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`wFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`wFIFOSIZEWIDTH:0] status_cnt; +reg [`wFIFOOUTPUTWIDTH-1:0] q ; +reg[4:0] counter; +wire [`wFIFOINPUTWIDTH-1:0] data_ram ; +assign empty = (status_cnt == 5'b00000); +wire [`wFIFOINPUTWIDTH-1:0]junk_input; +wire [`wFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 2048'b0; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q <= data_ram[63:0]; +else if(counter == 1) + q <= data_ram[127:64]; +else if(counter == 2) + q <= data_ram[191:128]; +else if(counter == 3) + q <= data_ram[255:192]; +else if(counter == 4) + q <= data_ram[319:256]; +else if(counter == 5) + q <= data_ram[383:320]; +else if(counter == 6) + q <= data_ram[447:384]; +else if(counter == 7) + q <= data_ram[511:448]; +else if(counter == 8) + q <= data_ram[575:512]; +else if(counter == 9) + q <= data_ram[639:576]; +else if(counter == 10) + q <= data_ram[703:640]; +else if(counter == 11) + q <= data_ram[767:704]; +else if(counter == 12) + q <= data_ram[831:768]; +else if(counter == 13) + q <= data_ram[895:832]; +else if(counter == 14) + q <= data_ram[959:896]; +else if(counter == 15) + q <= data_ram[1023:960]; +else if(counter == 16) + q <= data_ram[1087:1024]; +else if(counter == 17) + q <= data_ram[1151:1088]; +else if(counter == 18) + q <= data_ram[1215:1152]; +else if(counter == 19) + q <= data_ram[1279:1216]; +else if(counter == 20) + q <= data_ram[1343:1280]; +else if(counter == 21) + q <= data_ram[1407:1344]; +else if(counter == 22) + q <= data_ram[1471:1408]; +else if(counter == 23) + q <= data_ram[1535:1472]; +else if(counter == 24) + q <= data_ram[1599:1536]; +else if(counter == 25) + q <= data_ram[1663:1600]; +else if(counter == 26) + q <= data_ram[1727:1664]; +else if(counter == 27) + q <= data_ram[1791:1728]; +else if(counter == 28) + q <= data_ram[1855:1792]; +else if(counter == 29) + q <= data_ram[1919:1856]; +else if(counter == 30) + q <= data_ram[1983:1920]; +else if(counter == 31) + q <= data_ram[2047:1984]; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000 )) + status_cnt <= status_cnt + 1'b1; +end +assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module addr_fifo ( + clk, + data, + wrreq, + rdreq, + empty, + full, + q + ); + + input clk; + input [`aFIFOWIDTH-1:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [`aFIFOWIDTH-1:0] q; + +reg [`aFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`aFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`aFIFOSIZEWIDTH:0] status_cnt; +reg [`aFIFOWIDTH-1:0] q ; +wire [`aFIFOWIDTH-1:0] data_ram ; +assign full = (status_cnt == 5'b01111); +assign empty = (status_cnt == 5'b00000); +wire [`aFIFOWIDTH-1:0]junk_input; +wire [`aFIFOWIDTH-1:0]junk_output; +assign junk_input = 8'b00000000; +always @ (posedge clk) +begin //WRITE_POINTER +if (wrreq) +begin +wr_pointer <= wr_pointer + 1'b1; +end +end +always @ (posedge clk) +begin //READ_POINTER +if (rdreq) +begin +rd_pointer <= rd_pointer + 1'b1; +end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) begin +q <= data_ram; +end +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000)) + status_cnt <= status_cnt + 1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +module memcmd_fifo ( + clk, + data, + rdreq, + wrreq, + full, + empty, + q + ); + + input clk; + input [`mFIFOWIDTH-1:0] data; + input wrreq; + input rdreq; + output full; + output empty; + output [`mFIFOWIDTH-1:0] q; + + reg [`mFIFOSIZEWIDTH-1:0] wr_pointer; + reg [`mFIFOSIZEWIDTH-1:0] rd_pointer; + reg [`mFIFOSIZEWIDTH:0] status_cnt; + reg [`mFIFOWIDTH-1:0] q ; + wire [`mFIFOWIDTH-1:0] data_ram; + assign full = (status_cnt ==5'b01111); + assign empty = (status_cnt == 5'b00000); + wire [`mFIFOWIDTH-1:0]junk_input; + wire [`mFIFOWIDTH-1:0]junk_output; + assign junk_input = 28'b0000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end + end + always @ (posedge clk) + begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 1'b1; + end + end + always @ (posedge clk ) + begin //READ_DATA + if (rdreq) begin + q <= data_ram; + end + end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; + else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( + .we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable + .addr1 (wr_pointer) , // address_0 input + .addr2 (rd_pointer) , // address_q input + .data1 (data) , // data_0 bi-directional + .data2 (junk_input), // data_1 bi-directional + .clk(clk), + .out1 (data_ram), + .out2 (junk_output)); + + +endmodule + + +`define ZERO 8'b00000000 +`define ONE 8'b00000001 +`define TWO 8'b00000010 +`define THREE 8'b00000011 +`define FOUR 8'b00000100 +`define FIVE 8'b00000101 +`define SIX 8'b00000110 +`define SEVEN 8'b00000111 +`define EIGHT 8'b00001000 +`define NINE 8'b00001001 +`define TEN 8'b00001010 +`define ELEVEN 8'b00001011 +`define TWELVE 8'b00001100 +`define THIRTEEN 8'b00001101 +`define FOURTEEN 8'b00001110 +`define FIFTEEN 8'b00001111 +`define SIXTEEN 8'b00010000 +`define SEVENTEEN 8'b00010001 +`define EIGHTEEN 8'b00010010 +`define NINETEEN 8'b00010011 +`define TWENTY 8'b00010100 +`define TWENTYONE 8'b00010101 +`define TWENTYTWO 8'b00010110 +`define TWENTYTHREE 8'b00010111 +`define TWENTYFOUR 8'b00011000 + +module fpu_add (clock, a1, b1, sum); + input clock; + input [31:0]a1; + input [31:0]b1; + output [31:0]sum; + reg [31:0]sum; + + //Split up the numbers into exponents and mantissa. + reg [7:0]a_exp; + //reg [7:0]b_exp; + reg [23:0]a_man; + reg [23:0]b_man; + + reg [7:0]temp; + + reg [24:0]sum_man; + //reg [7:0]sum_exp; + + //introduce latency on inputs + reg [31:0]a; + reg [31:0]b; + + always @ (posedge clock) begin + a <= a1; + b <= b1; + end + + reg smaller; //smaller is 1 if a < b, 0 otherwise + + //Shift mantissa's to have the same exponent + always @ (a or b) begin + //a_exp = a[30:23]; + //b_exp = b[30:23]; + //a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]}; + + if (a[30:23] < b[30:23]) begin + temp = b[30:23] - a[30:23]; + //a_man = {1'b1, a[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + a_man = {1'b1, a[22:0]} >> `ONE; + end + `TWO: begin + a_man = {1'b1, a[22:0]} >> `TWO; + end + `THREE: begin + a_man = {1'b1, a[22:0]} >> `THREE; + end + `FOUR: begin + a_man = {1'b1, a[22:0]} >> `FOUR; + end + `FIVE: begin + a_man = {1'b1, a[22:0]} >> `FIVE; + end + `SIX: begin + a_man = {1'b1, a[22:0]} >> `SIX; + end + `SEVEN: begin + a_man = {1'b1, a[22:0]} >> `SEVEN; + end + `EIGHT: begin + a_man = {1'b1, a[22:0]} >> `EIGHT; + end + `NINE: begin + a_man = {1'b1, a[22:0]} >> `NINE; + end + `TEN: begin + a_man = {1'b1, a[22:0]} >> `TEN; + end + `ELEVEN: begin + a_man = {1'b1, a[22:0]} >> `ELEVEN; + end + `TWELVE: begin + a_man = {1'b1, a[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + a_man = {1'b1, a[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + a_man = {1'b1, a[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + a_man = {1'b1, a[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + a_man = {1'b1, a[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + a_man = {1'b1, a[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + a_man = {1'b1, a[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + a_man = {1'b1, a[22:0]} >> `NINETEEN; + end + `TWENTY: begin + a_man = {1'b1, a[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + endcase + + b_man = {1'b1, b[22:0]}; + a_exp = b[30:23]; + //b_exp = b[30:23]; + + end else if (a[30:23] > b[30:23]) begin + temp = a[30:23] - b[30:23]; + a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + b_man = {1'b1, b[22:0]} >> `ONE; + end + `TWO: begin + b_man = {1'b1, b[22:0]} >> `TWO; + end + `THREE: begin + b_man = {1'b1, b[22:0]} >> `THREE; + end + `FOUR: begin + b_man = {1'b1, b[22:0]} >> `FOUR; + end + `FIVE: begin + b_man = {1'b1, b[22:0]} >> `FIVE; + end + `SIX: begin + b_man = {1'b1, b[22:0]} >> `SIX; + end + `SEVEN: begin + b_man = {1'b1, b[22:0]} >> `SEVEN; + end + `EIGHT: begin + b_man = {1'b1, b[22:0]} >> `EIGHT; + end + `NINE: begin + b_man = {1'b1, b[22:0]} >> `NINE; + end + `TEN: begin + b_man = {1'b1, b[22:0]} >> `TEN; + end + `ELEVEN: begin + b_man = {1'b1, b[22:0]} >> `ELEVEN; + end + `TWELVE: begin + b_man = {1'b1, b[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + b_man = {1'b1, b[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + b_man = {1'b1, b[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + b_man = {1'b1, b[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + b_man = {1'b1, b[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + b_man = {1'b1, b[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + b_man = {1'b1, b[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + b_man = {1'b1, b[22:0]} >> `NINETEEN; + end + `TWENTY: begin + b_man = {1'b1, b[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + endcase + + a_exp = a[30:23]; + //b_exp = a[30:23]; + end else begin + temp = 8'b0; + a_man = {1'b1, a[22:0]}; + b_man = {1'b1, b[22:0]}; + a_exp = a[30:23]; + end + + end + + //Perform the addition operation + always @ (a_man or b_man or a or b) begin + if (a_man < b_man) begin + smaller = 1'b1; + end else begin + smaller = 1'b0; + end + + //both positive + if (~a[31] && ~b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b0; + end + + //both negative + else if (a[31] && b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b1; + end + + //a pos, b neg + else if (~a[31] && b[31]) begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b1; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b0; + end + end + + //a neg, b pos + else /*if (a[31] && ~b[31])*/ begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b0; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b1; + end + end + end + + //Store the number + // we already have the sign. + + always @ (sum_man or a_exp) begin + if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. + sum[22:0] = sum_man[23:1]; + sum[30:23] = a_exp + 8'b00000001; + + end else if (sum_man[23]) begin //do nothing + sum[22:0] = sum_man[22:0]; + sum[30:23] = a_exp; + + end else if (sum_man[22]) begin //shift << by 1, subtract 1 from exponent. + sum[22:0] = {sum_man[21:0], 1'b0}; + sum[30:23] = a_exp - 8'b00000001; + + end else if (sum_man[21]) begin //shift << by 2, subtract 2 from exponent. + sum[22:0] = {sum_man[20:0], 2'b0}; + sum[30:23] = a_exp - 8'b00000010; + + end else if (sum_man[20]) begin //shift << by 3, subtract 3 from exponent. + sum[22:0] = {sum_man[19:0], 3'b0}; + sum[30:23] = a_exp - 8'b00000011; + + end else if (sum_man[19]) begin //shift << by 4, subtract 4 from exponent. + sum[22:0] = {sum_man[18:0], 4'b0}; + sum[30:23] = a_exp - 8'b00000100; + + end else if (sum_man[18]) begin //shift << by 5, subtract 5 from exponent. + sum[22:0] = {sum_man[17:0], 5'b0}; + sum[30:23] = a_exp - 8'b00000101; + + end else if (sum_man[17]) begin //shift << by 6, subtract 6 from exponent. + sum[22:0] = {sum_man[16:0], 6'b0}; + sum[30:23] = a_exp - 8'b00000110; + + end else if (sum_man[16]) begin //shift << by 7, subtract 7 from exponent. + sum[22:0] = {sum_man[15:0], 7'b0}; + sum[30:23] = a_exp - 8'b00000111; + + end else if (sum_man[15]) begin //shift << by 8, subtract 8 from exponent. + sum[22:0] = {sum_man[14:0], 8'b0}; + sum[30:23] = a_exp - 8'b00001000; + + end else if (sum_man[14]) begin //shift << by 9, subtract 9 from exponent. + sum[22:0] = {sum_man[13:0], 9'b0}; + sum[30:23] = a_exp - 8'b00001001; + + end else if (sum_man[13]) begin //shift << by 10, subtract 10 from exponent. + sum[22:0] = {sum_man[12:0], 10'b0}; + sum[30:23] = a_exp - 8'b00001010; + + end else if (sum_man[12]) begin //shift << by 11, subtract 11 from exponent. + sum[22:0] = {sum_man[11:0], 11'b0}; + sum[30:23] = a_exp - 8'b00001011; + + end else if (sum_man[11]) begin //shift << by 12, subtract 12 from exponent. + sum[22:0] = {sum_man[10:0], 12'b0}; + sum[30:23] = a_exp - 8'b00001100; + + end else if (sum_man[10]) begin //shift << by 13, subtract 13 from exponent. + sum[22:0] = {sum_man[9:0], 13'b0}; + sum[30:23] = a_exp - 8'b00001101; + + end else if (sum_man[9]) begin //shift << by 14, subtract 14 from exponent. + sum[22:0] = {sum_man[8:0], 14'b0}; + sum[30:23] = a_exp - 8'b00001110; + + end else if (sum_man[8]) begin //shift << by 15, subtract 15 from exponent. + sum[22:0] = {sum_man[7:0], 15'b0}; + sum[30:23] = a_exp - 8'b00001111; + + end else if (sum_man[7]) begin //shift << by 16, subtract 16 from exponent. + sum[22:0] = {sum_man[6:0], 16'b0}; + sum[30:23] = a_exp - 8'b00010000; + + end else if (sum_man[6]) begin //shift << by 17, subtract 17 from exponent. + sum[22:0] = {sum_man[5:0], 17'b0}; + sum[30:23] = a_exp - 8'b00010001; + + end else if (sum_man[5]) begin //shift << by 18, subtract 18 from exponent. + sum[22:0] = {sum_man[4:0], 18'b0}; + sum[30:23] = a_exp - 8'b00010010; + + end else if (sum_man[4]) begin //shift << by 19, subtract 19 from exponent. + sum[22:0] = {sum_man[3:0], 19'b0}; + sum[30:23] = a_exp - 8'b00010011; + + end else if (sum_man[3]) begin //shift << by 20, subtract 20 from exponent. + sum[22:0] = {sum_man[2:0], 20'b0}; + sum[30:23] = a_exp - 8'b00010100; + + end else if (sum_man[2]) begin //shift << by 21, subtract 21 from exponent. + sum[22:0] = {sum_man[1:0], 21'b0}; + sum[30:23] = a_exp - 8'b00010101; + + end else if (sum_man[1]) begin //shift << by 22, subtract 22 from exponent. + sum[22:0] = {sum_man[0:0], 22'b0}; + sum[30:23] = a_exp - 8'b00010110; + + end else /*if (sum_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + sum[22:0] = 23'b0; + sum[30:23] = a_exp - 8'b00010111; + end + + end + +endmodule + +module fpu_div(clock, n, d, div); +//n = numerator +//d = denomenator +//div = result + input clock; + + input [31:0]n; + input [31:0]d; + output [31:0]div; + reg [31:0]div; + + //Store the mantissa and exponents separately. Introduce the latency of 1. + reg [7:0]n_exp; + reg [7:0]d_exp; + reg [23:0]n_man; + reg [23:0]d_man; + reg n_sign; + reg d_sign; + + wire [23:0]div_man; + reg [7:0]div_exp; + + always @ (posedge clock) begin + n_exp <= n[30:23]; + d_exp <= d[30:23]; + n_man <= {1'b1, n[22:0]}; + d_man <= {1'b1, d[22:0]}; + n_sign <= n[31]; + d_sign <= d[31]; + end + + //Find the exponent, store in div_exp. + always @ (n_exp or d_exp) begin + if (n_exp >= d_exp) begin + div_exp = 8'b01111111 + (n_exp - d_exp); + end else begin + div_exp = 8'b01111111 - (d_exp - n_exp); + end + end + + //Divide the mantissas, store in div_man. + div_24b divide(.numer(n_man), .denom(d_man), .res(div_man)); + + //Store the result. Shift exponents appropriately. Store sign. + //Sign + always @ (n_sign or d_sign) begin + div[31] = n_sign ^ d_sign; + end + + //Mantissa and Exponent + always @ (div_man or div_exp) begin + if (div_man[23]) begin //do nothing + div[22:0] = div_man[22:0]; + div[30:23] = div_exp; + + end else if (div_man[22]) begin //shift << by 1, subtract 1 from exponent. + div[22:0] = {div_man[21:0], 1'b0}; + div[30:23] = div_exp - 8'b00000001; + + end else if (div_man[21]) begin //shift << by 2, subtract 2 from exponent. + div[22:0] = {div_man[20:0], 2'b0}; + div[30:23] = div_exp - 8'b00000010; + + end else if (div_man[20]) begin //shift << by 3, subtract 3 from exponent. + div[22:0] = {div_man[19:0], 3'b0}; + div[30:23] = div_exp - 8'b00000011; + + end else if (div_man[19]) begin //shift << by 4, subtract 4 from exponent. + div[22:0] = {div_man[18:0], 4'b0}; + div[30:23] = div_exp - 8'b00000100; + + end else if (div_man[18]) begin //shift << by 5, subtract 5 from exponent. + div[22:0] = {div_man[17:0], 5'b0}; + div[30:23] = div_exp - 8'b00000101; + + end else if (div_man[17]) begin //shift << by 6, subtract 6 from exponent. + div[22:0] = {div_man[16:0], 6'b0}; + div[30:23] = div_exp - 8'b00000110; + + end else if (div_man[16]) begin //shift << by 7, subtract 7 from exponent. + div[22:0] = {div_man[15:0], 7'b0}; + div[30:23] = div_exp - 8'b00000111; + + end else if (div_man[15]) begin //shift << by 8, subtract 8 from exponent. + div[22:0] = {div_man[14:0], 8'b0}; + div[30:23] = div_exp - 8'b00001000; + + end else if (div_man[14]) begin //shift << by 9, subtract 9 from exponent. + div[22:0] = {div_man[13:0], 9'b0}; + div[30:23] = div_exp - 8'b00001001; + + end else if (div_man[13]) begin //shift << by 10, subtract 10 from exponent. + div[22:0] = {div_man[12:0], 10'b0}; + div[30:23] = div_exp - 8'b00001010; + + end else if (div_man[12]) begin //shift << by 11, subtract 11 from exponent. + div[22:0] = {div_man[11:0], 11'b0}; + div[30:23] = div_exp - 8'b00001011; + + end else if (div_man[11]) begin //shift << by 12, subtract 12 from exponent. + div[22:0] = {div_man[10:0], 12'b0}; + div[30:23] = div_exp - 8'b00001100; + + end else if (div_man[10]) begin //shift << by 13, subtract 13 from exponent. + div[22:0] = {div_man[9:0], 13'b0}; + div[30:23] = div_exp - 8'b00001101; + + end else if (div_man[9]) begin //shift << by 14, subtract 14 from exponent. + div[22:0] = {div_man[8:0], 14'b0}; + div[30:23] = div_exp - 8'b00001110; + + end else if (div_man[8]) begin //shift << by 15, subtract 15 from exponent. + div[22:0] = {div_man[7:0], 15'b0}; + div[30:23] = div_exp - 8'b00001111; + + end else if (div_man[7]) begin //shift << by 16, subtract 16 from exponent. + div[22:0] = {div_man[6:0], 16'b0}; + div[30:23] = div_exp - 8'b00010000; + + end else if (div_man[6]) begin //shift << by 17, subtract 17 from exponent. + div[22:0] = {div_man[5:0], 17'b0}; + div[30:23] = div_exp - 8'b00010001; + + end else if (div_man[5]) begin //shift << by 18, subtract 18 from exponent. + div[22:0] = {div_man[4:0], 18'b0}; + div[30:23] = div_exp - 8'b00010010; + + end else if (div_man[4]) begin //shift << by 19, subtract 19 from exponent. + div[22:0] = {div_man[3:0], 19'b0}; + div[30:23] = div_exp - 8'b00010011; + + end else if (div_man[3]) begin //shift << by 20, subtract 20 from exponent. + div[22:0] = {div_man[2:0], 20'b0}; + div[30:23] = div_exp - 8'b00010100; + + end else if (div_man[2]) begin //shift << by 21, subtract 21 from exponent. + div[22:0] = {div_man[1:0], 21'b0}; + div[30:23] = div_exp - 8'b00010101; + + end else if (div_man[1]) begin //shift << by 22, subtract 22 from exponent. + div[22:0] = {div_man[0:0], 22'b0}; + div[30:23] = div_exp - 8'b00010110; + + end else /*if (div_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + div[22:0] = 23'b0; + div[30:23] = div_exp - 8'b00010111; + end + + end + +endmodule + + + + + +module div_24b(numer, denom, res); + //input clock; + + input [23:0]numer; + input [23:0]denom; + output [23:0]res; + reg [23:0]res; + + //Pad with 23 zeros. + wire [46:0]denom_pad; + wire [46:0]numer23; + reg [46:0]numer22; + reg [46:0]numer21; + reg [46:0]numer20; + reg [46:0]numer19; + reg [46:0]numer18; + reg [46:0]numer17; + reg [46:0]numer16; + reg [46:0]numer15; + reg [46:0]numer14; + reg [46:0]numer13; + reg [46:0]numer12; + reg [46:0]numer11; + reg [46:0]numer10; + reg [46:0]numer9; + reg [46:0]numer8; + reg [46:0]numer7; + reg [46:0]numer6; + reg [46:0]numer5; + reg [46:0]numer4; + reg [46:0]numer3; + reg [46:0]numer2; + reg [46:0]numer1; + reg [46:0]numer0; + + //always @ (posedge clock) begin + assign denom_pad = {23'b0, denom}; + assign numer23 = {numer, 23'b0}; + // end + + //res[23] + always @ (denom_pad or numer23) begin + + if (denom_pad[23:0] <= numer23[46:23]) begin + res[23] = 1'b1; + numer22 = {numer23[46:23] - denom_pad[23:0], 23'b0}; + end else begin + res[23] = 1'b0; + numer22 = numer23; + end + + if (denom_pad[24:0] <= numer22[46:22]) begin + res[22] = 1'b1; + numer21 = {numer22[46:22] - denom_pad[24:0], 22'b0}; + end else begin + res[22] = 1'b0; + numer21 = numer22; + end + + if (denom_pad[25:0] <= numer21[46:21]) begin + res[21] = 1'b1; + numer20 = {numer21[46:21] - denom_pad[25:0], 21'b0}; + end else begin + res[21] = 1'b0; + numer20 = numer21; + end + + if (denom_pad[26:0] <= numer20[46:20]) begin + res[20] = 1'b1; + numer19 = {numer20[46:20] - denom_pad[26:0], 20'b0}; + end else begin + res[20] = 1'b0; + numer19 = numer20; + end + + if (denom_pad[27:0] <= numer19[46:19]) begin + res[19] = 1'b1; + numer18 = {numer19[46:19] - denom_pad[27:0], 19'b0}; + end else begin + res[19] = 1'b0; + numer18 = numer19; + end + + if (denom_pad[28:0] <= numer18[46:18]) begin + res[18] = 1'b1; + numer17 = {numer18[46:18] - denom_pad[28:0], 18'b0}; + end else begin + res[18] = 1'b0; + numer17 = numer18; + end + + if (denom_pad[29:0] <= numer17[46:17]) begin + res[17] = 1'b1; + numer16 = {numer17[46:17] - denom_pad[29:0], 17'b0}; + end else begin + res[17] = 1'b0; + numer16 = numer17; + end + + if (denom_pad[30:0] <= numer16[46:16]) begin + res[16] = 1'b1; + numer15 = {numer16[46:16] - denom_pad[30:0], 16'b0}; + end else begin + res[16] = 1'b0; + numer15 = numer16; + end + + if (denom_pad[31:0] <= numer15[46:15]) begin + res[15] = 1'b1; + numer14 = {numer15[46:15] - denom_pad[31:0], 15'b0}; + end else begin + res[15] = 1'b0; + numer14 = numer15; + end + + if (denom_pad[32:0] <= numer14[46:14]) begin + res[14] = 1'b1; + numer13 = {numer14[46:14] - denom_pad[32:0], 14'b0}; + end else begin + res[14] = 1'b0; + numer13 = numer14; + end + + if (denom_pad[33:0] <= numer13[46:13]) begin + res[13] = 1'b1; + numer12 = {numer13[46:13] - denom_pad[33:0], 13'b0}; + end else begin + res[13] = 1'b0; + numer12 = numer13; + end + + if (denom_pad[34:0] <= numer12[46:12]) begin + res[12] = 1'b1; + numer11 = {numer12[46:12] - denom_pad[34:0], 12'b0}; + end else begin + res[12] = 1'b0; + numer11 = numer12; + end + + if (denom_pad[35:0] <= numer11[46:11]) begin + res[11] = 1'b1; + numer10 = {numer11[46:11] - denom_pad[35:0], 11'b0}; + end else begin + res[11] = 1'b0; + numer10 = numer11; + end + + if (denom_pad[36:0] <= numer10[46:10]) begin + res[10] = 1'b1; + numer9 = {numer10[46:10] - denom_pad[36:0], 10'b0}; + end else begin + res[10] = 1'b0; + numer9 = numer10; + end + + if (denom_pad[37:0] <= numer9[46:9]) begin + res[9] = 1'b1; + numer8 = {numer9[46:9] - denom_pad[37:0], 9'b0}; + end else begin + res[9] = 1'b0; + numer8 = numer9; + end + + if (denom_pad[38:0] <= numer8[46:8]) begin + res[8] = 1'b1; + numer7 = {numer8[46:8] - denom_pad[38:0], 8'b0}; + end else begin + res[8] = 1'b0; + numer7 = numer8; + end + + if (denom_pad[39:0] <= numer7[46:7]) begin + res[7] = 1'b1; + numer6 = {numer7[46:7] - denom_pad[39:0], 7'b0}; + end else begin + res[7] = 1'b0; + numer6 = numer7; + end + + if (denom_pad[40:0] <= numer6[46:6]) begin + res[6] = 1'b1; + numer5 = {numer6[46:6] - denom_pad[40:0], 6'b0}; + end else begin + res[6] = 1'b0; + numer5 = numer6; + end + + if (denom_pad[41:0] <= numer5[46:5]) begin + res[5] = 1'b1; + numer4 = {numer5[46:5] - denom_pad[41:0], 5'b0}; + end else begin + res[5] = 1'b0; + numer4 = numer5; + end + + if (denom_pad[42:0] <= numer4[46:4]) begin + res[4] = 1'b1; + numer3 = {numer4[46:4] - denom_pad[42:0], 4'b0}; + end else begin + res[4] = 1'b0; + numer3 = numer4; + end + + if (denom_pad[43:0] <= numer3[46:3]) begin + res[3] = 1'b1; + numer2 = {numer3[46:3] - denom_pad[43:0], 3'b0}; + end else begin + res[3] = 1'b0; + numer2 = numer3; + end + + if (denom_pad[44:0] <= numer2[46:2]) begin + res[2] = 1'b1; + numer1 = {numer2[46:2] - denom_pad[44:0], 2'b0}; + end else begin + res[2] = 1'b0; + numer1 = numer2; + end + + if (denom_pad[45:0] <= numer1[46:1]) begin + res[1] = 1'b1; + numer0 = {numer1[46:1] - denom_pad[45:0], 1'b0}; + end else begin + res[1] = 1'b0; + numer0 = numer1; + end + + if (denom_pad <= numer0) begin + res[0] = 1'b1; + end else begin + res[0] = 1'b0; + end + + end + +endmodule + + +////////////////////////////////////////////// +// +// constants.v +// +// Version 1.3 +// Written 7/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 8/20/01 Mark_Phair@hmc.edu and Justin_Schauer@hmc.edu +// +// A set of constants for a parameterized floating point multiplier and adder. +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// FREE VARIABLES +////////////////////////////////////////////// + +// Widths of Fields +`define WEXP 8 +`define WSIG 23 +`define WFLAG 5 +`define WCONTROL 5 + +// output flag select (flags[x]) +`define DIVZERO 0 +`define INVALID 1 +`define INEXACT 2 +`define OVERFLOW 3 +`define UNDERFLOW 4 + +////////////////////////////////////////////// +// DEPENDENT VARIABLES +////////////////////////////////////////////// + +`define WIDTH 32 //(`WEXP + `WSIG + 1) +`define PRODWIDTH 48 //(2 * (`WSIG + 1)) +`define SHIFTWIDTH 96 //(2 * `PRODWIDTH)) +`define WPRENORM 24 // `WSIG + 1 +`define WEXPSUM 10 // `WEXP + 2 +`define BIAS 127 // (2^(`WEXP)) - 1 +`define WSIGMINUS1 22 // `WSIG - 1, used for rounding +`define WSHIFTAMT 5 // log2(`WSIG + 1) rounded up + +// for trapped over/underflow +`define UNDERBIAS 192 // 3 * 2 ^ (`WEXP -2) +`define OVERBIAS -192 // -`UNDERBIAS + +// specialized constants for fpadd +`define EXTRASIG 25 // `WSIG+2 this is the amount of precision needed so no + // subtraction errors occur +`define SHIFT 5 // # bits the max alignment shift will fit in (log2(`WSIG+2) + // rounded up to nearest int) +`define MAX_EXP 8'b11111110 // the maximum non-infinite exponent, + // `WEXP bits, the most significant + // `WEXP-1 bits are 1, the LSB is 0 +`define INF_EXP 8'b11111111 // Infinity exponent, `WEXP bits, all 1 +// Max significand, `WSIG bits, all 1 +`define MAX_SIG 23'b11111111111111111111111 +`define WEXP_0 8'b0 // Exponent equals `WEXP'b0 +`define WEXP_1 8'b1 // Exponent equals one `WEXP'b1 +`define WSIG_0 23'b0 // Significand equals zero `WSIG'b0 +`define WSIG_1 23'b1 // Significand equals one `WSIG'b1 +`define EXTRASIG_0 25'b0 // All result bits for adder zero `EXTRASIG'b0 + +// specialized constants for fpmul +`define MAXSHIFT 24 // `WSIG + 1 + +// GENERAL SPECIAL NUMBERS - Exp + Significand of special numbers +// plain NaN `WIDTH-1, all 1 +`define CONSTNAN {9'b111111111,22'b0} +// zero `WIDTH-1, all 0 +`define CONSTZERO 31'b0 +// infinity `WEXP all 1, `WSIG all 0 +`define CONSTINFINITY {8'b11111111, 23'b0} +// largest number maximum exponent(all 1's - 1) and maximum significand (all 1's) +`define CONSTLARGEST {`MAX_EXP, `MAX_SIG} +`define PRESHIFTZEROS 48'b0 // `PRODWIDTH'b0 + +////////////////////////////////////////////// +// +// fpmul.v +// +// Version 1.6 +// Written 07/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 08/20/01 Mark_Phair@hmc.edu +// +// A parameterized floating point multiplier. +// +// BLOCK DESCRIPTIONS +// +// preprocess - general processing, such as zero detection, computing sign, NaN +// +// prenorm - normalize denorms +// +// exponent - sum the exponents, check for tininess before rounding +// +// multiply - multiply the mantissae +// +// special - calculate special cases, such as NaN and infinities +// +// shift - shift the sig and exp if nesc. +// +// round - round product +// +// normalize - normalizes the result if appropriate (i.e. not a denormalized #) +// +// flag - general flag processing +// +// assemble - assemble results +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// Includes +////////////////////////////////////////////// + + + +////////////////////////////////////////////// +// fpmul module +////////////////////////////////////////////// + +module fpmul(clk, a, b, y_out, control, flags) ; + + input clk; + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-1:0] y_out; // floating-point product + reg [`WIDTH-1:0] y_out; + input [1:0] control; // control including rounding mode + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + //intermediate y_out + wire [`WIDTH-1:0]y; + + // internal signals + wire multsign; // sign of product + wire specialsign; // sign of special + + wire [`WSIG:0] norma; // normal-form mantissa a, 1 bit larger to hold leading 1 + wire [`WSIG:0] normb; // normal-form mantissa b, 1 bit larger to hold leading 1 + + wire [`WEXPSUM-1:0] expa, expb; // the two exponents, after prenormalization + wire [`WEXPSUM-1:0] expsum; // sum of exponents (two's complement) + wire [`WEXPSUM-1:0] shiftexp; // shifted exponent + wire [`WEXP-1:0] roundexp; // rounded, correct exponent + + wire [`PRODWIDTH-1:0] prod; // product of mantissae + wire [`PRODWIDTH-1:0] normalized; // Normalized product + wire [`SHIFTWIDTH-1:0] shiftprod; // shifted product + wire [`WSIG-1:0] roundprod; // rounded product + wire [`WIDTH-2:0] special; // special case exponent and product + + wire twoormore; // product is outside range [1,2) + wire zero; // zero detected + wire infinity; // infinity detected + wire aisnan; // NaN detected in A + wire bisnan; // NaN detected in B + wire aisdenorm; // Denormalized number detected in A + wire bisdenorm; // Denormalized number detected in B + wire specialcase; // This is a special case + wire specialsigncase; // Use the special case sign + wire roundoverflow; // overflow in rounding, need to add 1 to exponent + wire invalid; // invalid operation + wire overflow; // exponent result too high, standard overflow + wire inexact; // inexact flag + wire shiftloss; // lost digits due to a shift, result inaccurate + wire [1:0] roundmode; // rounding mode information extracted from control field + wire tiny; // Result is tiny (denormalized #) after multiplication + wire stilltiny; // Result is tiny (denormalized #) after rounding + wire denormround; // rounding occured only because the initial result was + // a denormalized number. This is used to determine + // underflow in cases of denormalized numbers rounding + // up to normalized numbers + + preprocess preprocesser(a, b, zero, aisnan, bisnan, + aisdenorm, bisdenorm, infinity, + control, roundmode, sign); + + special specialer(a, b, special, specialsign, zero, + aisnan, bisnan, + infinity, invalid, + specialcase, specialsigncase); + + prenorm prenormer(a[`WIDTH-2:0], b[`WIDTH-2:0], norma, normb, expa, expb, aisdenorm, bisdenorm); + + multiply_a multiplier(norma, normb, prod, twoormore); + + exponent exponenter(expa, expb, expsum, twoormore, tiny); + + normalize normalizer(prod, normalized, tiny, twoormore); + + shift shifter(normalized, expsum, shiftprod, + shiftexp, shiftloss); + + round rounder(shiftprod, shiftexp, shiftloss, + roundprod, roundexp, + roundmode, sign, tiny, inexact, + overflow, stilltiny, denormround); + + // *** To check for tininess before rounding, use tiny + // To check after rounding, use stilltiny + // *** for underflow detect: + // To check for inexact result use (inexact | (shiftloss & stilltiny)), + // To check for denormilization loss use (shiftloss & stilltiny) +// flag flager(invalid, overflow, inexact | shiftloss, +// shiftloss | inexact, +// /* tiny */ (stilltiny | (tiny & denormround)), +// specialcase, flags); + + //ODIN cannot have operations in module instantiations. + wire inexact_or_shiftloss; + assign inexact_or_shiftloss = inexact | shiftloss; + wire shiftloss_or_inexact; + assign shiftloss_or_inexact = shiftloss | inexact; + wire still_tiny_or_tiny_and_denormround; + assign still_tiny_or_tiny_and_denormround = stilltiny | (tiny & denormround); + + flag flager(invalid, overflow, inexact_or_shiftloss, + shiftloss_or_inexact, + /* tiny */ stilltiny_or_tiny_and_denormround, + specialcase, flags); + + + assemble assembler(roundprod, special, y, + sign, specialsign, roundexp, + specialcase, specialsigncase, + roundmode, flags[`OVERFLOW]); + + always @ (posedge clk) begin + y_out <= y; + end + +endmodule + + + + +module preprocess(a, b, zero, aisnan, bisnan, aisdenorm, bisdenorm, infinity, control, roundmode, sign); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output zero; // is there a zero? + //input [`WCONTROL-1:0] control; // control field + input [1:0] control; //the rest is unused, not necessary for ODIN. + output [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + output aisnan; // NaN detected in A + output bisnan; // NaN detected in B + output aisdenorm; // denormalized number detected in A + output bisdenorm; // denormalized number detected in B + output infinity; // infinity detected in A + output sign; // sign of product + + // internal signals + wire signa, signb; // sign of a and b + wire [`WEXP-1:0] expa, expb; // the exponents of a and b + wire [`WSIG-1:0] siga, sigb; // the significands of a and b + wire aexpfull; // the exponent of a is all 1's + wire bexpfull; // the exponent of b is all 1's + wire aexpzero; // the exponent of a is all 0's + wire bexpzero; // the exponent of b is all 0's + wire asigzero; // the significand of a is all 0's + wire bsigzero; // the significand of b is all 0's + + // Sign calculation + assign signa = a[`WIDTH-1]; + assign signb = b[`WIDTH-1]; + assign sign = signa ^ signb; + + // Significand calcuations + + assign siga = a[`WSIG-1:0]; + assign sigb = b[`WSIG-1:0]; + // Are the significands all 0's? + assign asigzero = ~|siga; + assign bsigzero = ~|sigb; + + // Exponent calculations + + assign expa = a[`WIDTH-2:`WIDTH-`WEXP-1]; + assign expb = b[`WIDTH-2:`WIDTH-`WEXP-1]; + // Are the exponents all 0's? + assign aexpzero = ~|expa; + assign bexpzero = ~|expb; + // Are the exponents all 1's? + assign aexpfull = &expa; + assign bexpfull = &expb; + + // General calculations + + // Zero Detect + assign zero = (aexpzero & asigzero) | (bexpzero & bsigzero); + + // NaN detect + assign aisnan = aexpfull & ~asigzero; + assign bisnan = bexpfull & ~bsigzero; + + // Infinity detect + assign infinity = (aexpfull & asigzero) | (bexpfull & bsigzero); + + // Denorm detect + assign aisdenorm = aexpzero & ~asigzero; + assign bisdenorm = bexpzero & ~bsigzero; + + // Round mode extraction + assign roundmode = control[1:0]; + +endmodule + +module special (a, b, special, specialsign, + zero, aisnan, bisnan, infinity, + invalid, specialcase, specialsigncase); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-2:0] special; // special case output, exp + sig + output specialsign; // the special-case sign + input zero; // is there a zero? + input aisnan; // NaN detected in A + input bisnan; // NaN detected in B + input infinity; // infinity detected + output invalid; // invalid operation + output specialcase; // this is a special case + output specialsigncase; // Use the special sign + + // internal signals + wire infandzero; // infinity and zero detected + wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input, + // and dont care if neither a nor b are NaNs + wire aishighernan; // a is the higher NaN + + assign infandzero = (infinity & zero); + + //#######SPECIAL ASSIGNMENT###### + // #######return higher NaN########## + // Use this block if you want to return the higher of two NaNs + + assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan)); + + assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0]; + + assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) : + (zero ? + (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)); + // #######return first NaN########## + // Use this block to return the first NaN encountered +// assign special = aisnan ? (a[`WIDTH-2:0]) : +// (bisnan ? (b[`WIDTH-2:0]) : +// (zero ? +// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY))); + //######END SPECIAL ASSIGNMENT####### + + assign specialcase = zero | aisnan | bisnan | infinity; + + assign invalid = infandzero; //*** need to include something about signaling NaNs here + + // dont need to check if b is NaN, if it defaults to that point, and b isnt NAN + // then it wont be used anyway + assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]); + + assign specialsigncase = infandzero | aisnan | bisnan; + +endmodule + +module prenorm(a, b, norma, normb, modexpa, modexpb, aisdenorm, bisdenorm); + + //input [`WIDTH-1:0] a, b; // the input floating point numbers + input [`WIDTH-2:0] a, b; //We don't need bit 31 here, unused in ODIN. + output [`WSIG:0] norma, normb; // the mantissae in normal form + output [`WEXPSUM-1:0] modexpa, modexpb; // the output exponents, larger to accomodate + // two's complement form + input aisdenorm; // a is a denormalized number + input bisdenorm; // b is a denormalized nubmer + + // internal signals + wire [`WEXPSUM-1:0] expa, expb; // exponents in two's complement form + // are negative if shifted for a + // denormalized number + wire [`SHIFT-1:0] shifta, shiftb; // the shift amounts + reg [`WSIG:0] shifteda, shiftedb; // the shifted significands, used to be wire, changed for ODIN. + + // pull out the exponents + assign expa = a[`WIDTH-2:`WIDTH-1-`WEXP]; + assign expb = b[`WIDTH-2:`WIDTH-1-`WEXP]; + + // when breaking appart for paramaterizing: + // ### RUN ./prenormshift.pl wsig_in ### +assign shifta = a[23 - 1] ? 1 : + a[23 - 2] ? 2 : + a[23 - 3] ? 3 : + a[23 - 4] ? 4 : + a[23 - 5] ? 5 : + a[23 - 6] ? 6 : + a[23 - 7] ? 7 : + a[23 - 8] ? 8 : + a[23 - 9] ? 9 : + a[23 - 10] ? 10 : + a[23 - 11] ? 11 : + a[23 - 12] ? 12 : + a[23 - 13] ? 13 : + a[23 - 14] ? 14 : + a[23 - 15] ? 15 : + a[23 - 16] ? 16 : + a[23 - 17] ? 17 : + a[23 - 18] ? 18 : + a[23 - 19] ? 19 : + a[23 - 20] ? 20 : + a[23 - 21] ? 21 : + a[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + +assign shiftb = b[23 - 1] ? 1 : + b[23 - 2] ? 2 : + b[23 - 3] ? 3 : + b[23 - 4] ? 4 : + b[23 - 5] ? 5 : + b[23 - 6] ? 6 : + b[23 - 7] ? 7 : + b[23 - 8] ? 8 : + b[23 - 9] ? 9 : + b[23 - 10] ? 10 : + b[23 - 11] ? 11 : + b[23 - 12] ? 12 : + b[23 - 13] ? 13 : + b[23 - 14] ? 14 : + b[23 - 15] ? 15 : + b[23 - 16] ? 16 : + b[23 - 17] ? 17 : + b[23 - 18] ? 18 : + b[23 - 19] ? 19 : + b[23 - 20] ? 20 : + b[23 - 21] ? 21 : + b[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + + + + // If number is a denorm, the exponent must be + // decremented by the shift amount + assign modexpa = aisdenorm ? 1 - shifta : expa; + assign modexpb = bisdenorm ? 1 - shiftb : expb; + + // If number is denorm, shift the significand the appropriate amount +// assign shifteda = a[`WSIG-1:0] << shifta; + //Must have constant shifts for ODIN + always @ (shifta or a) begin + case (shifta) + 5'b00001: begin + shifteda = a[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shifteda = a[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shifteda = a[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shifteda = a[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shifteda = a[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shifteda = a[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shifteda = a[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shifteda = a[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shifteda = a[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shifteda = a[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shifteda = a[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shifteda = a[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shifteda = a[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shifteda = a[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shifteda = a[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shifteda = a[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shifteda = a[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shifteda = a[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shifteda = a[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shifteda = a[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shifteda = a[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shifteda = a[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shifteda = a[`WSIG-1:0] << 5'b10111; + end + + default: begin //Won't be higher than 23. + shifteda = a[`WSIG-1:0]; + end + endcase + end + + assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; + + // assign shiftedb = b[`WSIG-1:0] << shiftb; + always @ (shiftb or b) begin + case (shiftb) + 5'b00001: begin + shiftedb = b[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shiftedb = b[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shiftedb = b[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shiftedb = b[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shiftedb = b[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shiftedb = b[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shiftedb = b[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shiftedb = b[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shiftedb = b[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shiftedb = b[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shiftedb = b[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shiftedb = b[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shiftedb = b[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shiftedb = b[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shiftedb = b[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shiftedb = b[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shiftedb = b[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shiftedb = b[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shiftedb = b[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shiftedb = b[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shiftedb = b[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shiftedb = b[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shiftedb = b[`WSIG-1:0] << 5'b10111; + end + + default: begin // Won't be higher than 23. + shiftedb = b[`WSIG-1:0]; + end + endcase + end + + + assign normb = bisdenorm ? shiftedb : {1'b1, b[`WSIG-1:0]}; + +endmodule + +module multiply_a (norma, normb, prod, twoormore); + + input [`WSIG:0] norma, normb; // normalized mantissae + + output [`PRODWIDTH-1:0] prod; // product of mantissae + output twoormore; // Product overflowed range [1,2) + + // multiplier array + // (*** need a more effecient multiplier, + // designware might work, though) + assign prod = norma * normb; + + // did the multiply overflow the range [1,2)? + assign twoormore = prod[`PRODWIDTH-1]; + +endmodule + + + +module exponent(expa, expb, expsum, twoormore, tiny); + + input [`WEXPSUM-1:0] expa, expb; // the input exponents in 2's complement form + // to accomodate denorms that have been + // prenormalized + input twoormore; // product is outside range [1,2) + + output [`WEXPSUM-1:0] expsum; // the sum of the exponents + output tiny; // Result is tiny (denormalized #) + + // Sum the exponents, subtract the bias + // and add 1 (twoormore) if multiply went out of [1,2) range + assign expsum = expa + expb - `BIAS + twoormore; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is in 2's-complement form, + // it is negative if the first bit is 1, and zero if + // all the bits are zero + assign tiny = ~|expsum[`WEXPSUM-2:0] | expsum[`WEXPSUM-1]; + + +endmodule + + + + +module normalize(prod, normalized, tiny, twoormore); + + // external signals + input [`PRODWIDTH-1:0] prod; // Product of multiplication + output [`PRODWIDTH-1:0] normalized; // Normalized product + input tiny; // Result is tiny (denormalized #) + input twoormore; // Product overflowed range [1,2) + + // normalize product if appropriate + // There are three possible cases here: + // 1) tiny and prod overfl. [1,2) -> take the whole prod, including the leading 1 + // 2) tiny or prod overfl. [1,2) -> dont take the first bit. its zero if its tiny, + // and it's the implied 1 if its not + // 3) neither tiny nor prod overfl.-> dont take the first 2 bits, the 2nd one is the + // implied 1 + assign normalized = (tiny & twoormore) ? prod[`PRODWIDTH-1:0] : + ((tiny ^ twoormore) ? {prod[`PRODWIDTH-2:0],1'b0} : + {prod[`PRODWIDTH-3:0],2'b0}); + +endmodule + +module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); + + // external signals + input [`PRODWIDTH-1:0] normalized; // normalized product of mantissae + input [`WEXPSUM-1:0] selectedexp; // sum of exponents + output [`SHIFTWIDTH-1:0] shiftprod; // shifted and normalized product + output [`WEXPSUM-1:0] shiftexp; // shifted exponent + output shiftloss; // loss of accuaracy due to shifting + + // internal signals + wire [`WEXPSUM-1:0] roundedexp; // selected exponent + 1 if rounding caused overflow +// wire negexp; // exponent is negative + wire [`WEXPSUM-1:0] shiftamt; // theoretical amount to shift product by + wire [`WSHIFTAMT-1:0] actualshiftamt; // actual amount to shift product by + wire tozero; // need more shifts than possible with width of significand + wire doshift; // only shift if value is nonnegative + wire [`SHIFTWIDTH-1:0] preshift; // value before shifting, with more room to ensure lossless shifting + reg [`SHIFTWIDTH-1:0] postshift; // value after shifting, with more room to ensure lossless shifting, used to be wire, changed for ODIN. + + // set up value for shifting + assign preshift = {normalized, `PRESHIFTZEROS}; + + // determine shift amount + assign shiftamt = -selectedexp; + + // make sure shift amount is nonnegative + // If the exponent is negative, the shift amount should + // come out positive, otherwise there shouldn't be any + // shifting to be done + assign doshift = ~shiftamt[`WEXPSUM-1]; + + // Determine if the result must be shifted more than + // will show up in the significand, even if it rounds up + assign tozero = doshift & (shiftamt > `MAXSHIFT); + + // If the shift is big enough to shift all the bits out of the final significand, + // then it stops being relevent how much it has been shifted. + assign actualshiftamt = tozero ? `MAXSHIFT : shiftamt[`WSHIFTAMT-1:0]; + + // shift significand + //assign postshift = preshift >> actualshiftamt; + //We can only have constant shifts for ODIN: + always @ (actualshiftamt or preshift) begin + case (actualshiftamt) + 5'b00001: begin + postshift = preshift >> 5'b00001; + end + + 5'b00010: begin + postshift = preshift >> 5'b00010; + end + + 5'b00011: begin + postshift = preshift >> 5'b00011; + end + + 5'b00100: begin + postshift = preshift >> 5'b00100; + end + + 5'b00101: begin + postshift = preshift >> 5'b00101; + end + + 5'b00110: begin + postshift = preshift >> 5'b00110; + end + + 5'b00111: begin + postshift = preshift >> 5'b00111; + end + + 5'b01000: begin + postshift = preshift >> 5'b01000; + end + + 5'b01001: begin + postshift = preshift >> 5'b01001; + end + + 5'b01010: begin + postshift = preshift >> 5'b01010; + end + + 5'b01011: begin + postshift = preshift >> 5'b01011; + end + + 5'b01100: begin + postshift = preshift >> 5'b01100; + end + + 5'b01101: begin + postshift = preshift >> 5'b01101; + end + + 5'b01110: begin + postshift = preshift >> 5'b01110; + end + + 5'b01111: begin + postshift = preshift >> 5'b01111; + end + + 5'b10000: begin + postshift = preshift >> 5'b10000; + end + + 5'b10001: begin + postshift = preshift >> 5'b10001; + end + + 5'b10010: begin + postshift = preshift >> 5'b10010; + end + + 5'b10011: begin + postshift = preshift >> 5'b10011; + end + + 5'b10100: begin + postshift = preshift >> 5'b10100; + end + + 5'b10101: begin + postshift = preshift >> 5'b10101; + end + + 5'b10110: begin + postshift = preshift >> 5'b10110; + end + + 5'b10111: begin + postshift = preshift >> 5'b10111; + end + + 5'b11000: begin + postshift = preshift >> 5'b11000; + end + + 5'b11001: begin + postshift = preshift >> 5'b11001; + end + + 5'b11010: begin + postshift = preshift >> 5'b11010; + end + + 5'b11011: begin + postshift = preshift >> 5'b11011; + end + + 5'b11100: begin + postshift = preshift >> 5'b11100; + end + + 5'b11101: begin + postshift = preshift >> 5'b11101; + end + + 5'b11110: begin + postshift = preshift >> 5'b11110; + end + + 5'b11111: begin + postshift = preshift >> 5'b11111; + end + + default: begin + postshift = preshift; + end + endcase + end + + + // assign appropriate significand + assign shiftprod = doshift ? postshift : preshift; + + // determine if any bits were lost from the shift + //assign shiftloss = tozero | (negexp & |postshift[`WSIG-1:0]); + assign shiftloss = tozero | (doshift & |postshift[`SHIFTWIDTH-`PRODWIDTH-1:0]); + + // assign appropriate exponent + assign shiftexp = doshift ? 0 : selectedexp; + +endmodule + + + +module round(shiftprod, shiftexp, shiftloss, roundprod, roundexp, roundmode, + sign, tiny, inexact, overflow, stilltiny, denormround); + + // external signals + input [`SHIFTWIDTH-1:0] shiftprod; // normalized and shifted product of mantissae + input [`WEXPSUM-1:0] shiftexp; // shifted exponent + input shiftloss; // bits were lost in the shifting process + output [`WSIG-1:0] roundprod; // rounded floating-point product + output [`WEXP-1:0] roundexp; // rounded exponent + input [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + input sign; // sign bit for rounding mode direction + input tiny; // denormalized number after rounding + output inexact; // rounding occured + output overflow; // overflow occured + output stilltiny; // Result is tiny (denormalized #) after rounding + output denormround; // result was rounded only because it was a denormalized number + + // internal signals + wire roundzero; // rounding towards zero + wire roundinf; // rounding towards infinity + wire stickybit; // there one or more 1 bits in the LS bits + wire denormsticky; // sticky bit if this weren't a denorm + wire [`WSIG-1:0] MSBits; // most significant bits + wire [`WSIG:0] MSBitsplus1; // most significant bits plus 1 + // for rounding purposes. needs to be one + // bit bigger for overflow + wire [1:0] roundbits; // bits used to compute rounding decision + wire rounddecision; // round up + wire roundoverflow; // rounding overflow occured + wire [`WEXPSUM-1:0] tempexp; // exponent after rounding + + //reduce round mode to three modes + // dont need round nearest, it is implied + // by roundzero and roundinf being false + //assign roundnearest = ~&roundmode; +// assign roundzero = &roundmode || (^roundmode && (roundmode[0] || sign)); + assign roundzero = (~roundmode[1] & roundmode[0]) | (roundmode[1] & (roundmode[0] ^ sign)); + assign roundinf = roundmode[1] & ~(sign ^ roundmode[0]); + + // pull out the most significant bits for the product + assign MSBits = shiftprod[`SHIFTWIDTH-1:`SHIFTWIDTH-`WSIG]; + + // add a 1 to the end of MSBits for round up + assign MSBitsplus1 = MSBits + 1; + + // pull out the last of the most significant bits + // and the first of the least significant bits + // to use for calculating the rounding decision + assign roundbits[1:0] = shiftprod[`SHIFTWIDTH-`WSIG:`SHIFTWIDTH-`WSIG-1]; + + // calculate the sticky bit. Are any of the least significant bits 1? + // also: was anything lost while shifting? + // *** Optimization: some of these bits are already checked from the shiftloss *** + // *** Optimization: stickybit can be calculated from denormsticky + // with only 1 more gate, instead of duplication of effort *** + assign stickybit = |shiftprod[`SHIFTWIDTH-`WSIG-2:0] | shiftloss; + assign denormsticky = |shiftprod[`SHIFTWIDTH-`WSIG-3:0] | shiftloss; + + // Compute rounding decision + assign rounddecision = ~roundzero & ( (roundbits[0] & (roundinf | roundbits[1])) + | (stickybit & (roundinf | roundbits[0])) + ); + + // Was this only rounded because it is a denorm? + assign denormround = tiny & rounddecision & ~denormsticky & roundbits[0]; + + // detect rounding overflow. it only overflows if: + // 1) the top bit of MSBitsplus1 is 1 + // 2) it decides to round up + assign roundoverflow = MSBitsplus1[`WSIG] & rounddecision; + + // assign significand (and postnormalize) + // rounddecision decides whether to use msbits+1 or msbits. + // if using msbits+1 and there is an rounding overflow (i.e. result=2), + // then should return 1 instead + assign roundprod = rounddecision ? + (roundoverflow ? 0 : + MSBitsplus1[`WSIG-1:0]) : + MSBits; + + // detect inexact + assign inexact = rounddecision | stickybit | roundbits[0]; + + // compensate for a rounding overflow + assign tempexp = roundoverflow + shiftexp; + + // check for overflow in exponent + // overflow occured if the number + // is too large to be represented, + // i.e. can't fit in `WEXP bits, or + // all `WEXP bits are 1's + assign overflow = &tempexp[`WEXP-1:0] | |tempexp[`WEXPSUM-1:`WEXP]; + + // two possible cases: + // 1) Overflow: then exponent doesnt matter, + // it will be changed to infinity anyway + // 2) not overflow: the leading bits will be 0 + assign roundexp = tempexp[`WEXP-1:0]; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is NOT in 2's-complement form, + // it is only less than one if its is zero, i.e. + // all the bits are 0 + assign stilltiny = ~|roundexp; + +endmodule + + +module flag (invalid, overflow, inexact, underflow, tiny, specialcase, flags); + + input invalid; // invalid operation + input overflow; // the result was too large + input inexact; // The result was rounded + input specialcase; // Using special result, shouldn't throw flags + input underflow; // Underflow detected + input tiny; // The result is tiny + + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + // flags + assign flags[`DIVZERO] = 1'b0; + assign flags[`INVALID] = invalid; + assign flags[`INEXACT] = ~specialcase & (inexact | underflow | overflow); + assign flags[`OVERFLOW] = ~specialcase & overflow; + assign flags[`UNDERFLOW] = tiny; //~specialcase & tiny & underflow & ~overflow; + +endmodule + +module assemble(roundprod, special, y, sign, specialsign, + shiftexp, specialcase, specialsigncase, + roundmode, overflow); + + // external signals + input [`WSIG-1:0] roundprod; // shifted, rounded and normalized + // product of mantissae + input [`WIDTH-2:0] special; // special case product + exponent + output [`WIDTH-1:0] y; // floating-point product + input sign; // sign of product (+ = 0, - = 1) + input specialsign; // special case sign + input [`WEXP-1:0] shiftexp; // shifted exponent + input specialcase; // this is a special case + input specialsigncase; // use the special case sign + input [1:0] roundmode; // rounding mode information extracted from control field + input overflow; // overflow detected + + // internal signals + wire [`WIDTH-2:0] rounded; // final product + exponent + wire [`WIDTH-2:0] overflowvalue; // product + exponent for overflow condition + wire undenormed; // the result was denormalized before rounding, but rounding + // caused it to become a small normalized number. + + // SET UP ROUNDED PRODUCT + EXPONENT + + // assign significand + assign rounded[`WSIG-1:0] = roundprod; + + // assign exponent + assign rounded[`WIDTH-2:`WIDTH-`WEXP-1] = shiftexp; + + // SET UP OVERFLOW CONDITION + assign overflowvalue[`WIDTH-2:0] = roundmode[1] ? + (sign ^ roundmode[0] ? `CONSTLARGEST : `CONSTINFINITY) : + (roundmode[0] ? `CONSTLARGEST: `CONSTINFINITY); + + // FINAL PRODUCT ASSIGN + + // assign sign + assign y[`WIDTH-1] = specialsigncase ? specialsign : sign; + + // assign product vs special vs overflowed + assign y[`WIDTH-2:0] = specialcase ? special[`WIDTH-2:0] : + (overflow ? overflowvalue[`WIDTH-2:0] : + rounded[`WIDTH-2:0]); + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v b/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v new file mode 100755 index 000000000..be2fb290c --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v @@ -0,0 +1,5001 @@ +//auto-generated top.v +//top level module of LU factorization +//by Wei Zhang + +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0101 +`define DDRWIDTH 7'b0100000 +`define DDRNUMDQS 4'b0100 +`define DDRSIZEWIDTH 6'b011000 +`define BURSTLEN 3'b010 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define RAMWIDTH 10'b0100000000 +`define RAMNUMBYTES 7'b0100000 +`define RAMSIZEWIDTH 4'b0101 +`define TOPWIDTH 7'b0100000 +`define rFIFOINPUTWIDTH 8'b01000000 +`define wFIFOINPUTWIDTH 10'b0100000000 +`define mFIFOWIDTH 6'b011100 +`define aFIFOWIDTH 4'b0101 + +module LU8PEEng (clk, //ref_clk, global_reset_n, + start, N, offset, done, + //mem_addr, mem_ba, mem_cas_n, mem_cke, mem_clk, mem_clk_n, mem_cs_n, +burst_begin, +mem_local_be, +mem_local_read_req, +mem_local_size, +mem_local_wdata, +mem_local_write_req, +mem_local_rdata, +mem_local_rdata_valid, +mem_local_ready, +mem_local_wdata_req, +reset_n, +mem_local_addr +//Cong: dummy output +//a_junk, +//w_junk, +//m_junk, +//r_junk, +//Cong:dummy output +//junk_r, +//junk_r1, +//junk_r2, +//junk_r3, +//junk_top + ); + +input start; +input[`NWIDTH-1:0] N; +input[`DDRSIZEWIDTH-1:0] offset; +output done; +input clk; + +output burst_begin; +output [`MEMCONNUMBYTES-1:0] mem_local_be; +output mem_local_read_req; +output [`BURSTLEN-1:0] mem_local_size; +output [`MEMCONWIDTH-1:0] mem_local_wdata; +output mem_local_write_req; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +input [`MEMCONWIDTH-1:0] mem_local_rdata; +input mem_local_rdata_valid; +input mem_local_ready; +input reset_n; +input mem_local_wdata_req; +wire[`BLOCKWIDTH-1:0] m, n, loop; +wire[1:0] mode; +wire comp_start, comp_done; +wire dtu_write_req, dtu_read_req, dtu_ack, dtu_done; +wire [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +wire [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +wire [`BLOCKWIDTH-1:0] dtu_size; +wire left_sel; + +wire[`RAMWIDTH-1:0] curWriteDataMem, curReadDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnMem; +wire curWriteEnMem; +wire[`RAMWIDTH-1:0] leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +wire leftWriteEnMem; +wire curMemSel, leftMemSel; + +wire burst_begin; +wire [`MEMCONNUMBYTES-1:0] mem_local_be; +wire mem_local_read_req; +wire [`BURSTLEN-1:0] mem_local_size; +wire [`MEMCONWIDTH-1:0] mem_local_wdata; +wire mem_local_write_req; +wire [`MEMCONWIDTH-1:0] mem_local_rdata; +wire mem_local_rdata_valid; +wire mem_local_ready; +wire mem_local_wdata_req; +wire reset_n; +wire [`DDRSIZEWIDTH-1:0] mem_local_addr; + +wire[`RAMWIDTH-1:0] ram_write_data, ram_read_data; +wire[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +wire[`RAMNUMBYTES-1:0] ram_write_byte_en; +wire ram_write_en; + +MarshallerController MC (clk, start, done, N, offset, + comp_start, m, n, loop, mode, comp_done, curMemSel, leftMemSel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + +// block that computes the LU factorization, with answer stored back into ram block +LU compBlock (clk, comp_start, m, n, loop, mode, comp_done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel); + +DataTransferUnit DTU (.clk(clk), .dtu_write_req(dtu_write_req), .dtu_read_req(dtu_read_req), .dtu_mem_addr(dtu_mem_addr), .dtu_ram_addr(dtu_ram_addr), .dtu_size(dtu_size), .dtu_ack(dtu_ack), .dtu_done(dtu_done), + .ram_read_addr(ram_read_addr), .ram_read_data(ram_read_data), .ram_write_byte_en(ram_write_byte_en), .ram_write_data(ram_write_data), .ram_write_addr(ram_write_addr), .ram_write_en(ram_write_en), + .mem_rdata(mem_local_rdata), .mem_rdata_valid(mem_local_rdata_valid), .mem_ready(mem_local_ready), .mem_wdata_req(mem_local_wdata_req), .reset_n(reset_n), + .burst_begin(burst_begin), .mem_local_addr(mem_local_addr), .mem_be(mem_local_be), .mem_read_req(mem_local_read_req), .mem_size(mem_local_size), + .mem_wdata(mem_local_wdata), .mem_write_req(mem_local_write_req) + //Cong: dummy output + ); + +assign curReadAddrMem = ram_read_addr; +assign curWriteByteEnMem = ram_write_byte_en; +assign curWriteDataMem = ram_write_data; +assign curWriteAddrMem = ram_write_addr; +assign curWriteEnMem = ram_write_en && (left_sel == 0); +assign leftWriteByteEnMem = ram_write_byte_en; +assign leftWriteDataMem = ram_write_data; +assign leftWriteAddrMem = ram_write_addr; +assign leftWriteEnMem = ram_write_en && (left_sel == 1); +assign ram_read_data = curReadDataMem; +endmodule +`define BLOCKM 6'b010000 +`define BLOCKN 6'b010000 +`define BLOCKMDIVK 3'b010 +`define MEMBLOCKM 5'b01000 +`define MEMBLOCKN 5'b01000 +`define NWIDTH 6'b010100 +`define BLOCKWIDTH 4'b0101 +`define DDRSIZEWIDTH 6'b011000 +`define RAMSIZEWIDTH 4'b0101 +`define START 1'b0 //0 +`define SETUP 2'b01 //1 +`define FIRST 3'b010 //2 +`define MODE0_SETUP 3'b011 //3 +`define MODE0_WAIT 4'b0100 //4 +`define MODE0 4'b0101 //5 +`define MODE1_SETUP 4'b0110 //6 +`define MODE1_WAIT 4'b0111 //7 +`define MODE1 5'b01000 //8 +`define MODE2_SETUP 5'b01001 //9 +`define MODE2_WAIT 5'b01010 //10 +`define MODE2 5'b01011 //11 +`define MODE3_SETUP 5'b01100 //12 +`define MODE3_WAIT 5'b01101 //13 +`define MODE3 5'b01110 //14 +`define STALL 5'b01111 //15 +`define STALL_WAIT 6'b010000 //16 +`define WAIT 6'b010001 //17 +`define FINAL_WRITE 6'b010010 //18 +`define FINAL_WAIT 6'b010011 //19 +`define IDLE 6'b010100 //20 +`define LAST_SETUP 6'b010101 //21 +`define LAST_SETUP_WAIT 6'b010110 //22 +`define LAST 6'b010111 //23 +`define LAST_WAIT 6'b011000 //24 +`define MEM_IDLE 1'b0 //0 +`define MEM_WRITE 2'b01 //1 +`define MEM_WRITE_WAIT 3'b010 //2 +`define MEM_CHECK_DONE 3'b011 //3 +`define MEM_READ 4'b0100 //4 +`define MEM_READ_WAIT 4'b0101 //5 +`define MEM_DONE 4'b0110 //6 +`define MEM_WAIT_DONE 4'b0111 //7 + +module MarshallerController (clk, start, done, input_N, offset, + comp_start, block_m, block_n, loop, mode, comp_done, cur_mem_sel, left_mem_sel, + dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, left_sel); + + +input clk; +input start; +output done; +input [`NWIDTH-1:0] input_N; +input [`DDRSIZEWIDTH-1:0] offset; + +// for computation section +output comp_start; +output [`BLOCKWIDTH-1:0] block_m, block_n, loop; +output [1:0] mode; +input comp_done; +output cur_mem_sel, left_mem_sel; + +// for data marshaller section +output dtu_write_req, dtu_read_req; +output [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +output [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +output [`BLOCKWIDTH-1:0] dtu_size; +input dtu_ack, dtu_done; +output left_sel; + +reg [4:0] cur_state, next_state; +reg [`NWIDTH-1:0] comp_N, N, mcount, ncount, Ndivk, mem_N; +reg [1:0] mode; +reg [`BLOCKWIDTH-1:0] block_m, block_n, loop, read_n; +reg [`BLOCKWIDTH-1:0] write_n, write_n_buf; +reg left_mem_sel, cur_mem_sel, no_left_switch; + +reg [3:0] cur_mem_state, next_mem_state; +reg [`RAMSIZEWIDTH-1:0] ram_addr; +reg [`DDRSIZEWIDTH-1:0] mem_addr; +reg [`DDRSIZEWIDTH-1:0] mem_base, mem_top, mem_write, mem_left, mem_cur; +reg [`DDRSIZEWIDTH-1:0] mem_write_buf; +reg [`BLOCKWIDTH-1:0] mem_count; +reg [1:0] mem_read; +reg [`BLOCKWIDTH-1:0] mem_write_size, mem_write_size_buf, mem_read_size; +wire mem_done; + +assign done = (cur_state == `IDLE); +assign dtu_ram_addr = ram_addr; +assign dtu_mem_addr = mem_addr; +assign dtu_size = (cur_mem_state == `MEM_WRITE) ? mem_write_size : mem_read_size; +assign comp_start = (cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)||(cur_state == `FIRST)||(cur_state == `LAST); +assign dtu_write_req = (cur_mem_state == `MEM_WRITE); +assign dtu_read_req = (cur_mem_state == `MEM_READ); +assign mem_done = (cur_mem_state == `MEM_DONE)&&(dtu_done == 1'b1); +assign left_sel = mem_read == 2'b01 && (cur_mem_state == `MEM_READ || cur_mem_state == `MEM_READ_WAIT || cur_mem_state == `MEM_WAIT_DONE); + +// FSM to produce memory instructions to DTU +always @ (posedge clk) +begin + case (cur_mem_state) + `MEM_IDLE: + begin + if (cur_state == `START) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_IDLE; + end + `MEM_DONE: + begin + if (cur_state == `MODE0 || cur_state == `MODE1 || cur_state == `MODE2 || + cur_state == `MODE3 || cur_state == `FINAL_WRITE || cur_state == `LAST_SETUP) + next_mem_state <= `MEM_WRITE; + else if (cur_state == `FIRST) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_DONE; + end + `MEM_WRITE: + begin + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WRITE_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == write_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_WRITE; + end + else + next_mem_state <= `MEM_WRITE_WAIT; + end + `MEM_WAIT_DONE: + begin + if (dtu_done == 1'b1) + next_mem_state <= `MEM_CHECK_DONE; + else + next_mem_state <= `MEM_WAIT_DONE; + end + `MEM_CHECK_DONE: + begin + if (mem_read == 2'b10) + next_mem_state <= `MEM_DONE; + else + next_mem_state <= `MEM_READ; + end + `MEM_READ: + begin + next_mem_state <= `MEM_READ_WAIT; + end + `MEM_READ_WAIT: + begin + if (dtu_ack == 1'b1) + begin + if (mem_count == read_n) + next_mem_state <= `MEM_WAIT_DONE; + else + next_mem_state <= `MEM_READ; + end + else + next_mem_state <= `MEM_READ_WAIT; + end + default: + next_mem_state <= `MEM_IDLE; + endcase +end + +always @ (posedge clk) +begin + if (cur_mem_state == `MEM_DONE || cur_mem_state == `MEM_IDLE) + begin + ram_addr <= 5'b0; + mem_addr <= mem_write; + if (next_state == `LAST_WAIT || next_state == `FINAL_WAIT || next_state == `STALL) + mem_read <= 2'b00; + else if (next_state == `MODE0_SETUP || next_state == `SETUP || cur_state == `MODE0 || next_state == `LAST_SETUP_WAIT) + mem_read <= 2'b01; + else + mem_read <= 2'b10; + mem_count <= 5'b0; + end + else if (cur_mem_state == `MEM_CHECK_DONE) + begin + if (mem_read == 2'b10) + begin + mem_addr <= mem_left; + read_n <= loop; + end + else + begin + mem_addr <= mem_cur; + read_n <= block_n; + end + mem_read <= mem_read - 2'b01; + mem_count <= 5'b0; + ram_addr <= 5'b0; + end + else if (cur_mem_state == `MEM_WRITE || cur_mem_state == `MEM_READ) + begin + ram_addr <= ram_addr + `BLOCKMDIVK; + mem_addr <= mem_addr + Ndivk; + mem_count <= mem_count + 2'b01; + end + +end + +// FSM to determine the block LU factorization algorithm +always @ (posedge clk) +begin + case (cur_state) + `START: + begin + next_state <= `SETUP; + end + `SETUP: + begin + next_state <= `WAIT; + end + `WAIT: + begin + if (mem_done == 1'b1) + next_state <= `FIRST; + else + next_state <= `WAIT; + + end + `FIRST: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + next_state <= `LAST_WAIT; + end + `MODE0_SETUP: + begin + next_state <= `MODE0_WAIT; + end + `MODE0_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE0; + else + next_state <= `MODE0_WAIT; + + end + `MODE0: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else + begin + next_state <= `LAST_WAIT; + end + end + `MODE1_SETUP: + begin + next_state <= `MODE1_WAIT; + end + `MODE1_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE1; + else + next_state <= `MODE1_WAIT; + + end + `MODE1: + begin + if (mcount < comp_N) + next_state <= `MODE1_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE2_SETUP: + begin + next_state <= `MODE2_WAIT; + end + `MODE2_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE2; + else + next_state <= `MODE2_WAIT; + end + `MODE2: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `MODE3_SETUP: + begin + next_state <= `MODE3_WAIT; + end + `MODE3_WAIT: + begin + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `MODE3; + else + next_state <= `MODE3_WAIT; + end + `MODE3: + begin + if (mcount < comp_N) + next_state <= `MODE3_SETUP; + else if (ncount < comp_N) + next_state <= `MODE2_SETUP; + else if (comp_N <= `BLOCKN + `BLOCKN) + next_state <= `STALL; + else + next_state <= `MODE0_SETUP; + end + `STALL: + next_state <= `STALL_WAIT; + `STALL_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST_SETUP; + else + next_state <= `STALL_WAIT; + `LAST_SETUP: + next_state <= `LAST_SETUP_WAIT; + `LAST_SETUP_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `LAST; + else + next_state <= `LAST_SETUP_WAIT; + `LAST: + next_state <= `LAST_WAIT; + `LAST_WAIT: + if (mem_done == 1'b1 && comp_done == 1'b1) + next_state <= `FINAL_WRITE; + else + next_state <= `LAST_WAIT; + `FINAL_WRITE: + next_state <= `FINAL_WAIT; + `FINAL_WAIT: + if (mem_done == 1'b1) + next_state <= `IDLE; + else + next_state <= `FINAL_WAIT; + `IDLE: + if (start) + next_state <= `SETUP; + else + next_state <= `IDLE; + default: + next_state <= `START; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + cur_state <= `START; + cur_mem_state <= `MEM_IDLE; + end + else + begin + cur_state <= next_state; + cur_mem_state <= next_mem_state; + end +end + +always @ (cur_state) +begin + case (cur_state) + `MODE1: + mode = 2'b01; + `MODE2: + mode = 2'b10; + `MODE3: + mode = 2'b11; + default: + mode = 2'b00; + endcase +end + +always @ (posedge clk) +begin + if (start) + begin + comp_N <= input_N; + N <= input_N; + end + else if (next_state == `MODE0) + begin + comp_N <= comp_N - `BLOCKN; + end + + Ndivk <= ((N+`BLOCKM-1)>>4)<<3; + mem_N <= Ndivk<<4; + + if (start) + begin + mem_base <= offset; + mem_top <= offset; + mem_left <= offset; + mem_cur <= offset; + end + else if (cur_state == `MODE0_SETUP) + begin + mem_base <= mem_base + mem_N+`MEMBLOCKN; + mem_top <= mem_base + mem_N+`MEMBLOCKN; + mem_cur <= mem_base + mem_N+`MEMBLOCKN; + mem_left <= mem_base + mem_N+`MEMBLOCKN; + end + else if (cur_state == `MODE1_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + end + else if (cur_state == `MODE3_SETUP) + begin + mem_cur <= mem_cur + `MEMBLOCKM; + mem_left <= mem_left + `MEMBLOCKM; + end + else if (cur_state == `MODE2_SETUP) + begin + mem_cur <= mem_top + mem_N; + mem_top <= mem_top + mem_N; + mem_left <= mem_base; + end + + if (cur_state == `SETUP) + begin + mem_write <= 24'b0; + mem_write_buf <= 24'b0; + mem_write_size <= `BLOCKMDIVK; + mem_write_size_buf <= `BLOCKMDIVK; + write_n <= block_n; + write_n_buf <= block_n; + end + else if (cur_mem_state == `MEM_CHECK_DONE && mem_read == 0) + begin + mem_write <= mem_write_buf; + mem_write_buf <= mem_cur; + mem_write_size <= mem_write_size_buf; + mem_write_size_buf <= mem_read_size; + write_n <= write_n_buf; + write_n_buf <= block_n; + end + + mem_read_size <= `BLOCKMDIVK; + + if (start) begin + loop <= `BLOCKN; + end else if (next_state == `LAST) begin + loop <= comp_N[8:0] - `BLOCKN; + end + + if (cur_state == `MODE0_SETUP || cur_state == `MODE2_SETUP || start) begin + mcount <= `BLOCKM; + end else if (cur_state == `MODE1_SETUP || cur_state == `MODE3_SETUP) begin + mcount <= mcount+`BLOCKM; + end + + if (cur_state == `MODE0_SETUP || start) begin + ncount <= `BLOCKN; + end else if (cur_state == `MODE2_SETUP) begin + ncount <= ncount+`BLOCKN; + end + + if (mcount < comp_N) begin + block_m <= `BLOCKM; + end else begin + block_m <= comp_N - mcount + `BLOCKM; + end + + if (ncount < comp_N) begin + block_n <= `BLOCKN; + end else begin + block_n <= comp_N - ncount + `BLOCKN; + end + + if (start) begin + cur_mem_sel <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)||(cur_state == `LAST)) begin + cur_mem_sel <= !cur_mem_sel; + end + + if (start) begin + no_left_switch <= 1'b0; + end else if ((cur_state == `MODE0)||(cur_state == `FIRST)) begin + no_left_switch <= 1'b1; + end else if ((cur_state == `MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP)) begin + no_left_switch <= 1'b0; + end + + if (start) begin + left_mem_sel <= 1'b0; + end else if (((cur_state == `MODE0)||(cur_state ==`MODE1)||(cur_state == `MODE2)||(cur_state == `MODE3)|| + (cur_state == `FIRST)||(cur_state == `FINAL_WRITE)||(cur_state == `LAST_SETUP))&&(no_left_switch == 1'b0)) begin + left_mem_sel <= !left_mem_sel; + end +end + +endmodule + + +//topoutputdelay = 1 +//auto-generated LU.v +//datapath for computating LU factorization +//by Wei Zhang + +`define rRAMSIZEWIDTH 5 +`define cSETUP 4'b0000 +`define cSTART 4'b0001 +`define cFETCH_COL 4'b0010 +`define cWAIT_COL 4'b0011 +`define cFIND_REC 4'b0100 +`define cMULT_COL 4'b0101 +`define cUPDATE_J 4'b0110 +`define cSTORE_MO 4'b0111 +`define cMULT_SUB 4'b1000 +`define cINCRE_I 4'b1001 +`define cWAIT 4'b1010 +`define cDONE 4'b1011 +`define cSTORE_DIAG 4'b1100 +`define cSTORE_DIAG2 4'b1101 +`define cSTART_FETCH_ROW 4'b1110 +`define cROW_WAIT 2'b00 +`define cFETCH_ROW 2'b01 +`define cDONE_FETCH_ROW 2'b10 +`define cLOAD_ROW_INC_J 2'b11 + +`define PRECISION 7'b0100000 +`define NUMPE 5'b01000 +`define PEWIDTH 3'b011 +`define BLOCKWIDTH 4'b0101 +`define RAMWIDTH 10'b0100000000 +`define RAMNUMBYTES 7'b0100000 +`define RAMSIZEWIDTH 4'b0101 +`define TOPSIZEWIDTH 5'b01000 +`define TOPINPUTDELAY 3'b011 +`define TOPOUTPUTDELAY 2'b01 +`define MEMINPUTDELAY 3'b010 +`define MEMOUTPUTDELAY 2'b01 +`define TOPWIDTH 7'b0100000 + +module LU (clk, start, m, n, loop, mode, done, + curReadAddrMem, curReadDataMem, curWriteByteEnMem, curWriteDataMem, curWriteAddrMem, curWriteEnMem, curMemSel, + leftWriteByteEnMem, leftWriteDataMem, leftWriteAddrMem, leftWriteEnMem, leftMemSel +); + + +input clk, start; +input[`BLOCKWIDTH-1:0] m, n, loop; +input[1:0] mode; +output done; +wire[`RAMWIDTH-1:0] curWriteData0, curWriteData1; +wire[`RAMSIZEWIDTH-1:0] curWriteAddr0, curReadAddr0, curWriteAddr1, curReadAddr1; +wire[`RAMWIDTH-1:0] curReadData0, curReadData1; +wire[`RAMNUMBYTES-1:0] curWriteByteEn0, curWriteByteEn1; +wire curWriteEn0, curWriteEn1; + +input[`RAMWIDTH-1:0] curWriteDataMem; +output[`RAMWIDTH-1:0] curReadDataMem; +input[`RAMSIZEWIDTH-1:0] curWriteAddrMem, curReadAddrMem; +input[`RAMNUMBYTES-1:0] curWriteByteEnMem; +input curWriteEnMem; +input[`RAMWIDTH-1:0] leftWriteDataMem; +input[`RAMSIZEWIDTH-1:0] leftWriteAddrMem; +input[`RAMNUMBYTES-1:0] leftWriteByteEnMem; +input leftWriteEnMem; +input leftMemSel, curMemSel; + +wire[`RAMWIDTH-1:0] curReadDataLU, curReadDataMem; +wire[`RAMWIDTH-1:0] curWriteDataLU, curWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] curWriteAddrLU, curWriteAddrMem, curReadAddrLU, curReadAddrMem; +wire[`RAMNUMBYTES-1:0] curWriteByteEnLU, curWriteByteEnMem; +wire curWriteEnLU, curWriteEnMem; + +reg[`RAMWIDTH-1:0] curReadData0Reg0; +reg[`RAMWIDTH-1:0] curReadData1Reg0; +reg[`RAMWIDTH-1:0] leftReadData0Reg0; +reg[`RAMWIDTH-1:0] leftReadData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg0; +reg[`RAMWIDTH-1:0] curWriteData0Reg1; +reg[`RAMWIDTH-1:0] curWriteData1Reg0; +reg[`RAMWIDTH-1:0] curWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] curReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] curWriteByteEn1Reg1; +reg curWriteEn0Reg0; +reg curWriteEn0Reg1; +reg curWriteEn1Reg0; +reg curWriteEn1Reg1; +reg[`RAMWIDTH-1:0] leftWriteData0Reg0; +reg[`RAMWIDTH-1:0] leftWriteData0Reg1; +reg[`RAMWIDTH-1:0] leftWriteData1Reg0; +reg[`RAMWIDTH-1:0] leftWriteData1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr0Reg1; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftWriteAddr1Reg1; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg0; +reg[`RAMSIZEWIDTH-1:0] leftReadAddr1Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn0Reg1; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg0; +reg[`RAMNUMBYTES-1:0] leftWriteByteEn1Reg1; +reg leftWriteEn0Reg0; +reg leftWriteEn0Reg1; +reg leftWriteEn1Reg0; +reg leftWriteEn1Reg1; + +reg[`PRECISION-1:0] multOperand; +reg[`PRECISION-1:0] diag; +wire[`PRECISION-1:0] recResult; +wire[`PRECISION-1:0] multA0; +wire[`PRECISION-1:0] multA1; +wire[`PRECISION-1:0] multA2; +wire[`PRECISION-1:0] multA3; +wire[`PRECISION-1:0] multA4; +wire[`PRECISION-1:0] multA5; +wire[`PRECISION-1:0] multA6; +wire[`PRECISION-1:0] multA7; +wire[`PRECISION-1:0] multResult0; +wire[`PRECISION-1:0] multResult1; +wire[`PRECISION-1:0] multResult2; +wire[`PRECISION-1:0] multResult3; +wire[`PRECISION-1:0] multResult4; +wire[`PRECISION-1:0] multResult5; +wire[`PRECISION-1:0] multResult6; +wire[`PRECISION-1:0] multResult7; +wire[`PRECISION-1:0] addA0; +wire[`PRECISION-1:0] addA1; +wire[`PRECISION-1:0] addA2; +wire[`PRECISION-1:0] addA3; +wire[`PRECISION-1:0] addA4; +wire[`PRECISION-1:0] addA5; +wire[`PRECISION-1:0] addA6; +wire[`PRECISION-1:0] addA7; +wire[`PRECISION-1:0] addResult0; +wire[`PRECISION-1:0] addResult1; +wire[`PRECISION-1:0] addResult2; +wire[`PRECISION-1:0] addResult3; +wire[`PRECISION-1:0] addResult4; +wire[`PRECISION-1:0] addResult5; +wire[`PRECISION-1:0] addResult6; +wire[`PRECISION-1:0] addResult7; +wire[`RAMWIDTH-1:0] leftReadData0, leftReadData1, leftWriteData0, leftWriteData1; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddr0, leftWriteAddr1, leftReadAddr0, leftReadAddr1; +wire[`RAMNUMBYTES-1:0] leftWriteByteEn0, leftWriteByteEn1; +wire leftWriteEn0, leftWriteEn1; +wire[`RAMWIDTH-1:0] leftReadDataLU, leftWriteDataLU, leftWriteDataMem; +wire[`RAMSIZEWIDTH-1:0] leftWriteAddrLU, leftWriteAddrMem, leftReadAddrLU; +wire[`RAMNUMBYTES-1:0] leftWriteByteEnLU, leftWriteByteEnMem; +wire leftWriteEnLU, leftWriteEnMem; + +wire[`PRECISION-1:0] topWriteData; +reg[`PRECISION-1:0] topWriteDataLU; +wire[`PRECISION-1:0] topReadData, topReadDataLU; +wire[`TOPSIZEWIDTH-1:0] topWriteAddr, topWriteAddrLU, topReadAddr, topReadAddrLU; +wire topWriteEn, topWriteEnLU; + +reg[`PRECISION-1:0] topReadDataReg0; +reg[`PRECISION-1:0] topWriteDataReg0; +reg[`PRECISION-1:0] topWriteDataReg1; +reg[`PRECISION-1:0] topWriteDataReg2; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topWriteAddrReg2; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg0; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg1; +reg[`TOPSIZEWIDTH-1:0] topReadAddrReg2; +reg topWriteEnReg0; +reg topWriteEnReg1; +reg topWriteEnReg2; +wire[`RAMWIDTH-1:0] rcWriteData; +wire leftWriteSel, curWriteSel, topSourceSel; +wire diagEn; +wire[`PEWIDTH-1:0] topWriteSel; + +wire MOSel; +wire MOEn; + +// control block +LUControl conBlock (clk, start, m, n, loop, mode, done, + curReadAddrLU, curWriteAddrLU, curWriteByteEnLU, curWriteEnLU, curWriteSel, + leftReadAddrLU, leftWriteAddrLU, leftWriteByteEnLU, leftWriteEnLU, leftWriteSel, + topReadAddrLU, topWriteAddrLU, topWriteEnLU, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +// fp_div unit +//floating point divider here +fpu_div rec(.clock(clk), .n(32'h3F800000), .d(diag), .div(recResult)); +// on-chip memory blocks that store the matrix to be LU factorized +// store current blocks data +ram currentBlock0 (curWriteByteEn0, clk, curWriteData0, curReadAddr0, curWriteAddr0, curWriteEn0, curReadData0 ); +ram1 currentBlock1 (curWriteByteEn1, clk, curWriteData1, curReadAddr1, curWriteAddr1, curWriteEn1, curReadData1 ); +// store left blocks data +ram2 leftBlock0(leftWriteByteEn0, clk, leftWriteData0, leftReadAddr0, leftWriteAddr0, leftWriteEn0, leftReadData0 ); + +ram3 leftBlock1(leftWriteByteEn1, clk, leftWriteData1, leftReadAddr1, leftWriteAddr1, leftWriteEn1, leftReadData1 ); + +// store top block data +top_ram topBlock(clk, topWriteData, topReadAddr, topWriteAddr, topWriteEn, topReadDataLU ); + +// processing elements that does the main computation of LU factorization +mult_add PE0 (clk, multA0, multOperand, addA0, multResult0, addResult0); +mult_add PE1 (clk, multA1, multOperand, addA1, multResult1, addResult1); +mult_add PE2 (clk, multA2, multOperand, addA2, multResult2, addResult2); +mult_add PE3 (clk, multA3, multOperand, addA3, multResult3, addResult3); +mult_add PE4 (clk, multA4, multOperand, addA4, multResult4, addResult4); +mult_add PE5 (clk, multA5, multOperand, addA5, multResult5, addResult5); +mult_add PE6 (clk, multA6, multOperand, addA6, multResult6, addResult6); +mult_add PE7 (clk, multA7, multOperand, addA7, multResult7, addResult7); + +// connect to ports of the left blocks +assign leftWriteDataLU = (leftWriteSel == 1'b0) ? curReadDataLU : rcWriteData; +always @ (posedge clk) +begin + if(leftMemSel == 1'b0) + begin + leftWriteData0Reg0 <= leftWriteDataMem; + leftWriteAddr0Reg0 <= leftWriteAddrMem; + leftWriteByteEn0Reg0 <= leftWriteByteEnMem; + leftWriteEn0Reg0 <= leftWriteEnMem; + leftWriteData1Reg0 <= leftWriteDataLU; + leftWriteAddr1Reg0 <= leftWriteAddrLU; + leftWriteByteEn1Reg0 <= leftWriteByteEnLU; + leftWriteEn1Reg0 <= leftWriteEnLU; + end + else + begin + leftWriteData0Reg0 <= leftWriteDataLU; + leftWriteAddr0Reg0 <= leftWriteAddrLU; + leftWriteByteEn0Reg0 <= leftWriteByteEnLU; + leftWriteEn0Reg0 <= leftWriteEnLU; + leftWriteData1Reg0 <= leftWriteDataMem; + leftWriteAddr1Reg0 <= leftWriteAddrMem; + leftWriteByteEn1Reg0 <= leftWriteByteEnMem; + leftWriteEn1Reg0 <= leftWriteEnMem; + end + leftReadAddr0Reg0 <= leftReadAddrLU; + leftReadAddr1Reg0 <= leftReadAddrLU; + leftWriteData0Reg1 <= leftWriteData0Reg0; + leftWriteAddr0Reg1 <= leftWriteAddr0Reg0; + leftReadAddr0Reg1 <= leftReadAddr0Reg0; + leftWriteByteEn0Reg1 <= leftWriteByteEn0Reg0; + leftWriteEn0Reg1 <= leftWriteEn0Reg0; + leftWriteData1Reg1 <= leftWriteData1Reg0; + leftWriteAddr1Reg1 <= leftWriteAddr1Reg0; + leftReadAddr1Reg1 <= leftReadAddr1Reg0; + leftWriteByteEn1Reg1 <= leftWriteByteEn1Reg0; + leftWriteEn1Reg1 <= leftWriteEn1Reg0; +end +assign leftWriteData0 = leftWriteData0Reg1; +assign leftWriteAddr0 = leftWriteAddr0Reg1; +assign leftReadAddr0 = leftReadAddr0Reg1; +assign leftWriteByteEn0 = leftWriteByteEn0Reg1; +assign leftWriteEn0 = leftWriteEn0Reg1; +assign leftWriteData1 = leftWriteData1Reg1; +assign leftWriteAddr1 = leftWriteAddr1Reg1; +assign leftReadAddr1 = leftReadAddr1Reg1; +assign leftWriteByteEn1 = leftWriteByteEn1Reg1; +assign leftWriteEn1 = leftWriteEn1Reg1; + +always @ (posedge clk) +begin + leftReadData0Reg0 <= leftReadData0; + leftReadData1Reg0 <= leftReadData1; +end +assign leftReadDataLU = (leftMemSel == 1'b0) ? leftReadData1Reg0 : leftReadData0Reg0; +// data feed to fp div unit +always @ (posedge clk) +begin + if (diagEn == 1'b1) + begin + diag <= topReadData; + end +end +// one of the inputs to the PE +always @ (posedge clk) +begin + if (start == 1'b1) + multOperand <= 0; + else if (MOEn == 1'b1) + begin + if (MOSel == 1'b0) + multOperand <= recResult; + else + multOperand <= topReadData; + end +end + +// connections to top block memory ports +always @ (topSourceSel or topWriteSel or curReadDataLU or addResult7 or addResult6 or addResult5 or addResult4 or addResult3 or addResult2 or addResult1 or addResult0) +begin + if (topSourceSel == 1'b0) + case (topWriteSel) + 0: + topWriteDataLU = curReadDataLU[255:224]; + 1: + topWriteDataLU = curReadDataLU[223:192]; + 2: + topWriteDataLU = curReadDataLU[191:160]; + 3: + topWriteDataLU = curReadDataLU[159:128]; + 4: + topWriteDataLU = curReadDataLU[127:96]; + 5: + topWriteDataLU = curReadDataLU[95:64]; + 6: + topWriteDataLU = curReadDataLU[63:32]; + 7: + topWriteDataLU = curReadDataLU[31:0]; + default: + topWriteDataLU = curReadDataLU[`PRECISION-1:0]; + endcase + else + case (topWriteSel) + 0: + topWriteDataLU = addResult7; + 1: + topWriteDataLU = addResult6; + 2: + topWriteDataLU = addResult5; + 3: + topWriteDataLU = addResult4; + 4: + topWriteDataLU = addResult3; + 5: + topWriteDataLU = addResult2; + 6: + topWriteDataLU = addResult1; + 7: + topWriteDataLU = addResult0; + default: + topWriteDataLU = addResult0; + endcase +end + +always @ (posedge clk) +begin + topWriteDataReg0 <= topWriteDataLU; + topReadAddrReg0 <= topReadAddrLU; + topWriteAddrReg0 <= topWriteAddrLU; + topWriteEnReg0 <= topWriteEnLU; + topWriteDataReg1 <= topWriteDataReg0; + topReadAddrReg1 <= topReadAddrReg0; + topWriteAddrReg1 <= topWriteAddrReg0; + topWriteEnReg1 <= topWriteEnReg0; + topWriteDataReg2 <= topWriteDataReg1; + topReadAddrReg2 <= topReadAddrReg1; + topWriteAddrReg2 <= topWriteAddrReg1; + topWriteEnReg2 <= topWriteEnReg1; +end +assign topWriteData = topWriteDataReg2; +assign topReadAddr = topReadAddrReg2; +assign topWriteAddr = topWriteAddrReg2; +assign topWriteEn = topWriteEnReg2; +always @ (posedge clk) +begin + topReadDataReg0 <= topReadDataLU; +end +assign topReadData = topReadDataReg0; + +// connections to processing element +assign multA0 = leftReadDataLU[31:0]; +assign multA1 = leftReadDataLU[63:32]; +assign multA2 = leftReadDataLU[95:64]; +assign multA3 = leftReadDataLU[127:96]; +assign multA4 = leftReadDataLU[159:128]; +assign multA5 = leftReadDataLU[191:160]; +assign multA6 = leftReadDataLU[223:192]; +assign multA7 = leftReadDataLU[255:224]; + +assign addA0 = curReadDataLU[31:0]; +assign addA1 = curReadDataLU[63:32]; +assign addA2 = curReadDataLU[95:64]; +assign addA3 = curReadDataLU[127:96]; +assign addA4 = curReadDataLU[159:128]; +assign addA5 = curReadDataLU[191:160]; +assign addA6 = curReadDataLU[223:192]; +assign addA7 = curReadDataLU[255:224]; + +// connections to ports of the current blocks +assign rcWriteData[31:0] = (curWriteSel == 0) ? multResult0 : addResult0; +assign rcWriteData[63:32] = (curWriteSel == 0) ? multResult1 : addResult1; +assign rcWriteData[95:64] = (curWriteSel == 0) ? multResult2 : addResult2; +assign rcWriteData[127:96] = (curWriteSel == 0) ? multResult3 : addResult3; +assign rcWriteData[159:128] = (curWriteSel == 0) ? multResult4 : addResult4; +assign rcWriteData[191:160] = (curWriteSel == 0) ? multResult5 : addResult5; +assign rcWriteData[223:192] = (curWriteSel == 0) ? multResult6 : addResult6; +assign rcWriteData[255:224] = (curWriteSel == 0) ? multResult7 : addResult7; +assign curWriteDataLU = rcWriteData; + +always @ (posedge clk) +begin + if(curMemSel == 1'b0) + begin + curWriteData0Reg0 <= curWriteDataMem; + curWriteAddr0Reg0 <= curWriteAddrMem; + curReadAddr0Reg0 <= curReadAddrMem; + curWriteByteEn0Reg0 <= curWriteByteEnMem; + curWriteEn0Reg0 <= curWriteEnMem; + curWriteData1Reg0 <= curWriteDataLU; + curWriteAddr1Reg0 <= curWriteAddrLU; + curReadAddr1Reg0 <= curReadAddrLU; + curWriteByteEn1Reg0 <= curWriteByteEnLU; + curWriteEn1Reg0 <= curWriteEnLU; + end + else + begin + curWriteData0Reg0 <= curWriteDataLU; + curWriteAddr0Reg0 <= curWriteAddrLU; + curReadAddr0Reg0 <= curReadAddrLU; + curWriteByteEn0Reg0 <= curWriteByteEnLU; + curWriteEn0Reg0 <= curWriteEnLU; + curWriteData1Reg0 <= curWriteDataMem; + curWriteAddr1Reg0 <= curWriteAddrMem; + curReadAddr1Reg0 <= curReadAddrMem; + curWriteByteEn1Reg0 <= curWriteByteEnMem; + curWriteEn1Reg0 <= curWriteEnMem; + end + curWriteData0Reg1 <= curWriteData0Reg0; + curWriteAddr0Reg1 <= curWriteAddr0Reg0; + curReadAddr0Reg1 <= curReadAddr0Reg0; + curWriteByteEn0Reg1 <= curWriteByteEn0Reg0; + curWriteEn0Reg1 <= curWriteEn0Reg0; + curWriteData1Reg1 <= curWriteData1Reg0; + curWriteAddr1Reg1 <= curWriteAddr1Reg0; + curReadAddr1Reg1 <= curReadAddr1Reg0; + curWriteByteEn1Reg1 <= curWriteByteEn1Reg0; + curWriteEn1Reg1 <= curWriteEn1Reg0; +end +assign curWriteData0 = curWriteData0Reg1; +assign curWriteAddr0 = curWriteAddr0Reg1; +assign curReadAddr0 = curReadAddr0Reg1; +assign curWriteByteEn0 = curWriteByteEn0Reg1; +assign curWriteEn0 = curWriteEn0Reg1; +assign curWriteData1 = curWriteData1Reg1; +assign curWriteAddr1 = curWriteAddr1Reg1; +assign curReadAddr1 = curReadAddr1Reg1; +assign curWriteByteEn1 = curWriteByteEn1Reg1; +assign curWriteEn1 = curWriteEn1Reg1; + +always @ (posedge clk) +begin + curReadData0Reg0 <= curReadData0; + curReadData1Reg0 <= curReadData1; +end +assign curReadDataMem = (curMemSel == 0) ? curReadData0Reg0 : curReadData1Reg0; +assign curReadDataLU = (curMemSel == 0) ? curReadData1Reg0 : curReadData0Reg0; +endmodule + +module LUControl (clk, start_in, m_in, n_in, loop_in, mode_in, done, + curReadAddr, curWriteAddr, curWriteByteEn, curWriteEn, curWriteSel, + leftReadAddr, leftWriteAddr, leftWriteByteEn, leftWriteEn, leftWriteSel, + topReadAddr, topWriteAddr, topWriteEn, topWriteSel, topSourceSel, diagEn, MOSel, MOEn); + +input clk, start_in; +input[5-1:0] m_in, n_in, loop_in; +input[1:0] mode_in; +output done; + +output[32-1:0] curWriteByteEn; +output[5-1:0] curWriteAddr, curReadAddr; +output curWriteEn; + +output[32-1:0] leftWriteByteEn; +output[5-1:0] leftWriteAddr, leftReadAddr; +output leftWriteEn; + +output[8-1:0] topWriteAddr, topReadAddr; +output topWriteEn; + +output leftWriteSel, curWriteSel, topSourceSel, diagEn; +output[3-1:0] topWriteSel; + +output MOSel; +output MOEn; + +reg start; +reg[15:0]startDelay; +reg[5-1:0] m, n, stop, stop2, loop; +reg[1:0] mode; +reg[3:0] nextState, currentState; +reg[1:0] nextRowState, currentRowState; +reg startFetchRow, doneFetchRow, loadRow, writeRow; +reg updateCounter; + +reg[5-1:0] i1, j; +reg[8-1:0] nextTopIdx, nextTopIdx2, curTopIdx, nextTopIdxCounter; +reg[2-1:0] topIdx, topIdxCounter, mdivk; +reg[5-1:0] diagIdx, leftIdx, msIdx; +reg[3-1:0] imodk, i1modk; +reg[5-1:0] diagIdxCounter, leftIdxCounter, msIdxCounter, readRowCounter, topWriteCounter; +reg[32-1:0] byteEn, i1modkByteEn; + +reg done; + +reg[32-1:0] curWriteByteEn; +reg[5-1:0] curWriteAddr, curReadAddr; +reg curWriteEn; + +reg[32-1:0] leftWriteByteEn; +reg[5-1:0] leftWriteAddr, leftReadAddr; +reg leftWriteEn; + +reg[8-1:0] topWriteAddr, topReadAddr; +reg topWriteEn; + +reg leftWriteSel, curWriteSel, topSourceSel, diagEn; +reg[3-1:0] topWriteSel; + +reg MOSel; +reg MOEn; + +reg[5-1:0] counter; +reg[6-1:0] divCounter; + +reg[32-1:0]writeByteEnDelay0; +reg[32-1:0]writeByteEnDelay1; +reg[32-1:0]writeByteEnDelay2; +reg[32-1:0]writeByteEnDelay3; +reg[32-1:0]writeByteEnDelay4; +reg[32-1:0]writeByteEnDelay5; +reg[32-1:0]writeByteEnDelay6; +reg[32-1:0]writeByteEnDelay7; +reg[32-1:0]writeByteEnDelay8; +reg[32-1:0]writeByteEnDelay9; +reg[32-1:0]writeByteEnDelay10; +reg[32-1:0]writeByteEnDelay11; +reg[32-1:0]writeByteEnDelay12; +reg[32-1:0]writeByteEnDelay13; +reg[32-1:0]writeByteEnDelay14; +reg[32-1:0]writeByteEnDelay15; +reg[32-1:0]writeByteEnDelay16; +reg[32-1:0]writeByteEnDelay17; +reg[32-1:0]writeByteEnDelay18; +reg[32-1:0]writeByteEnDelay19; +reg[32-1:0]writeByteEnDelay20; +reg[32-1:0]writeByteEnDelay21; +reg[32-1:0]writeByteEnDelay22; +reg[32-1:0]writeByteEnDelay23; +reg[32-1:0]writeByteEnDelay24; +reg[32-1:0]writeByteEnDelay25; +reg[32-1:0]writeByteEnDelay26; +reg[32-1:0]writeByteEnDelay27; +reg[32-1:0]writeByteEnDelay28; +reg[32-1:0]writeByteEnDelay29; +reg[32-1:0]writeByteEnDelay30; +reg[32-1:0]writeByteEnDelay31; + +reg[5-1:0]curWriteAddrDelay0; +reg[5-1:0]curWriteAddrDelay1; +reg[5-1:0]curWriteAddrDelay2; +reg[5-1:0]curWriteAddrDelay3; +reg[5-1:0]curWriteAddrDelay4; +reg[5-1:0]curWriteAddrDelay5; +reg[5-1:0]curWriteAddrDelay6; +reg[5-1:0]curWriteAddrDelay7; +reg[5-1:0]curWriteAddrDelay8; +reg[5-1:0]curWriteAddrDelay9; +reg[5-1:0]curWriteAddrDelay10; +reg[5-1:0]curWriteAddrDelay11; +reg[5-1:0]curWriteAddrDelay12; +reg[5-1:0]curWriteAddrDelay13; +reg[5-1:0]curWriteAddrDelay14; +reg[5-1:0]curWriteAddrDelay15; +reg[5-1:0]curWriteAddrDelay16; +reg[5-1:0]curWriteAddrDelay17; +reg[5-1:0]curWriteAddrDelay18; +reg[5-1:0]curWriteAddrDelay19; +reg[5-1:0]curWriteAddrDelay20; +reg[5-1:0]curWriteAddrDelay21; +reg[5-1:0]curWriteAddrDelay22; +reg[5-1:0]curWriteAddrDelay23; +reg[5-1:0]curWriteAddrDelay24; +reg[5-1:0]curWriteAddrDelay25; +reg[5-1:0]curWriteAddrDelay26; +reg[5-1:0]curWriteAddrDelay27; +reg[5-1:0]curWriteAddrDelay28; +reg[5-1:0]curWriteAddrDelay29; +reg[5-1:0]curWriteAddrDelay30; +reg[5-1:0]curWriteAddrDelay31; + +reg[5-1:0]curReadAddrDelay0; +reg[5-1:0]curReadAddrDelay1; +reg[5-1:0]curReadAddrDelay2; +reg[5-1:0]curReadAddrDelay3; +reg[5-1:0]curReadAddrDelay4; +reg[5-1:0]curReadAddrDelay5; +reg[5-1:0]curReadAddrDelay6; +reg[5-1:0]curReadAddrDelay7; +reg[5-1:0]curReadAddrDelay8; +reg[5-1:0]curReadAddrDelay9; +reg[5-1:0]curReadAddrDelay10; +reg[5-1:0]curReadAddrDelay11; + +reg[32-1:0]leftWriteEnDelay; +reg[32-1:0]curWriteEnDelay; +reg[5-1:0]leftWriteSelDelay; +reg[16-1:0]curWriteSelDelay; +reg[5-1:0]leftReadAddrDelay0; +reg[8-1:0]topWriteAddrDelay0; +reg[8-1:0]topWriteAddrDelay1; +reg[8-1:0]topWriteAddrDelay2; +reg[8-1:0]topWriteAddrDelay3; +reg[8-1:0]topWriteAddrDelay4; +reg[8-1:0]topWriteAddrDelay5; +reg[8-1:0]topWriteAddrDelay6; +reg[8-1:0]topWriteAddrDelay7; +reg[8-1:0]topWriteAddrDelay8; +reg[8-1:0]topWriteAddrDelay9; +reg[8-1:0]topWriteAddrDelay10; +reg[8-1:0]topWriteAddrDelay11; +reg[8-1:0]topWriteAddrDelay12; +reg[8-1:0]topWriteAddrDelay13; +reg[8-1:0]topWriteAddrDelay14; +reg[8-1:0]topWriteAddrDelay15; +reg[8-1:0]topWriteAddrDelay16; +reg[8-1:0]topWriteAddrDelay17; +reg[8-1:0]topWriteAddrDelay18; +reg[8-1:0]topWriteAddrDelay19; +reg[8-1:0]topWriteAddrDelay20; +reg[8-1:0]topWriteAddrDelay21; +reg[8-1:0]topWriteAddrDelay22; +reg[8-1:0]topWriteAddrDelay23; +reg[8-1:0]topWriteAddrDelay24; +reg[8-1:0]topWriteAddrDelay25; +reg[8-1:0]topWriteAddrDelay26; +reg[8-1:0]topWriteAddrDelay27; +reg[8-1:0]topWriteAddrDelay28; +reg[8-1:0]topWriteAddrDelay29; +reg[8-1:0]topWriteAddrDelay30; +reg[8-1:0]topWriteAddrDelay31; + +reg [32-1:0]topWriteEnDelay; +reg [5-1:0]topSourceSelDelay; +reg[3-1:0]topWriteSelDelay0; +reg[3-1:0]topWriteSelDelay1; +reg[3-1:0]topWriteSelDelay2; +reg[3-1:0]topWriteSelDelay3; +reg[3-1:0]topWriteSelDelay4; +reg[3-1:0]topWriteSelDelay5; +reg[3-1:0]topWriteSelDelay6; +reg[3-1:0]topWriteSelDelay7; +reg[3-1:0]topWriteSelDelay8; +reg[3-1:0]topWriteSelDelay9; +reg[3-1:0]topWriteSelDelay10; +reg[3-1:0]topWriteSelDelay11; +reg[3-1:0]topWriteSelDelay12; +reg[3-1:0]topWriteSelDelay13; +reg[3-1:0]topWriteSelDelay14; +reg[3-1:0]topWriteSelDelay15; +reg[3-1:0]topWriteSelDelay16; +reg[3-1:0]topWriteSelDelay17; +reg[3-1:0]topWriteSelDelay18; +reg[3-1:0]topWriteSelDelay19; +reg[3-1:0]topWriteSelDelay20; +reg[3-1:0]topWriteSelDelay21; +reg[3-1:0]topWriteSelDelay22; +reg[3-1:0]topWriteSelDelay23; +reg[3-1:0]topWriteSelDelay24; +reg[3-1:0]topWriteSelDelay25; +reg[3-1:0]topWriteSelDelay26; +reg[3-1:0]topWriteSelDelay27; +reg[3-1:0]topWriteSelDelay28; +reg[3-1:0]topWriteSelDelay29; +reg[3-1:0]topWriteSelDelay30; +reg[3-1:0]topWriteSelDelay31; + +reg [6-1:0]diagEnDelay; +reg[6-1:0]MOEnDelay; +reg [5-1:0]waitCycles; + +// register store m, n and mdivk value +always @ (posedge clk) +begin + if (start_in == 1'b1) + begin + n <= n_in; + m <= m_in; + loop <= loop_in; + mode <= mode_in; + end + if (mode[0] == 1'b0 && m == loop) + stop <= loop; + else + stop <= loop+1'b1; + stop2 <= loop; + startDelay[0] <= start_in; + startDelay[1] <= startDelay[0]; + startDelay[2] <= startDelay[1]; + startDelay[3] <= startDelay[2]; + startDelay[4] <= startDelay[3]; + startDelay[5] <= startDelay[4]; + startDelay[6] <= startDelay[5]; + startDelay[7] <= startDelay[6]; + startDelay[8] <= startDelay[7]; + startDelay[9] <= startDelay[8]; + startDelay[10] <= startDelay[9]; + startDelay[11] <= startDelay[10]; + startDelay[12] <= startDelay[11]; + startDelay[13] <= startDelay[12]; + startDelay[14] <= startDelay[13]; + startDelay[15] <= startDelay[14]; + start <= startDelay[15]; + mdivk <= (m+8-1)>>3; +end + +// registers that store values that are used in FSM, dependent on i and/or j +always @ (posedge clk) +begin + if (start == 1'b1) + topIdx <= 2'b00; //offset1divk; + else if (currentState == `cINCRE_I && i1modk == 8-1 && mode[0] == 1'b0) + topIdx <= topIdx + 1'b1; + + if (start == 1'b1) + diagIdx <= 5'b00000; + else if (currentState == `cSTORE_DIAG && mode == 2'b01) + diagIdx <= 2; else if (currentState == `cINCRE_I) + begin + if ((imodk == 8-1 && mode == 2'b00) || (i1modk == 8-1 && mode == 2'b01)) + diagIdx <= diagIdx + 2 + 1; + else + diagIdx <= diagIdx + 2; + end + + if (start == 1'b1) + leftIdx <= 5'b00000; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 8-1 && mode[0] == 1'b0) + leftIdx <= leftIdx + 2 + 1; + else + leftIdx <= leftIdx + 2; + end + + if (start == 1'b1) + msIdx <= 5'b00000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + msIdx <= leftIdx + 2; + else + msIdx <= topIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + msIdx <= msIdx + 2; + + if (start == 1'b1) + imodk <= 3'b000; + else if (currentState == `cINCRE_I) + begin + if (imodk == 8-1) + imodk <= 3'b000; + else + imodk <= imodk + 1'b1; + end + + if (start == 1'b1) + i1modk <= 3'b001; + else if (currentState == `cINCRE_I) + begin + if (i1modk == 8-1) + i1modk <= 3'b000; + else + i1modk <= i1modk + 1'b1; + end + + if (start == 1'b1) + nextTopIdx <= 8'b00000000; + else if (currentState == `cINCRE_I) + if (mode[1] == 0) + nextTopIdx <= nextTopIdx + n + 1; + else + nextTopIdx <= nextTopIdx + n; + nextTopIdx2 <= nextTopIdx + n + 1; + + if (start == 1'b1) + curTopIdx <= 8'b00000001; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + curTopIdx <= nextTopIdx+1; + else + curTopIdx <= nextTopIdx; + else if (nextRowState == `cLOAD_ROW_INC_J) + curTopIdx <= curTopIdx + 1; + + if (start == 1'b1) + i1 <= 5'b00001; + else if (currentState == `cINCRE_I) + i1 <= i1 + 1; + + if (start == 1'b1) + j <= 5'b00000; + else if (currentState == `cUPDATE_J) + if (mode[1] == 1'b0) + j <= i1; + else + j <= 5'b00000; + else if (currentRowState == `cLOAD_ROW_INC_J) + j <= j + 1; + +// compute cycles of delay in FSM + if (currentState == `cSTORE_MO) + waitCycles <= 32-1; + else if (currentState == `cINCRE_I) + begin + if (i1 == stop-1) + if (mode[1] == 1'b1) + waitCycles <= 32-1 + 6 - 3; + else + waitCycles <= waitCycles + 5 - 2; + else if (mode == 2'b01 && waitCycles < 32-1 - (16-1) - 4) + waitCycles <= 32-1 - (16-1) - 4; + else if (mode == 2'b10 && i1modk == 8-1) + waitCycles <= 32-1 + 6 - 3; + else if (mode == 2'b00) + waitCycles <= waitCycles + 6 ; + end +else if (waitCycles >5'b00000) + waitCycles <= waitCycles - 1; + +end + +// determining next state of main FSM +always @ (currentState or start or mode or m or n or counter or mdivk or topIdxCounter or doneFetchRow or divCounter or j or stop2 or waitCycles or stop or i1) +begin + case (currentState) + `cSETUP: + begin + if (start == 1'b1) + nextState = `cSTART; + else + nextState = `cSETUP; + updateCounter = 1'b1; + end + `cSTART: + begin + if (mode == 2'b00) + begin + if (m == 1 && n == 1) + nextState = `cDONE; + else + nextState = `cFETCH_COL; + end + else if (mode == 2'b01) + nextState = `cSTORE_DIAG; + else if (mode == 2'b10) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cUPDATE_J; + updateCounter = 1'b1; + end + `cSTART_FETCH_ROW: + begin + if (counter == 5+6-1) + begin + if (mode == 2'b00) + nextState = `cSTORE_DIAG; + else + nextState = `cUPDATE_J; + end + else + nextState = `cSTART_FETCH_ROW; + updateCounter = 1'b0; + end + `cFETCH_COL: + if (counter >= mdivk-1) + begin + if (mode == 2'b00 && counter < 5) + begin + nextState = `cWAIT_COL; + updateCounter = 1'b0; + end + else + begin + if (mode == 2'b00) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1'b1; + end + end + else + begin + nextState = `cFETCH_COL; + updateCounter = 1'b0; + end + `cWAIT_COL: + if (counter >= 5) + begin + if (mode == 0) + nextState = `cSTART_FETCH_ROW; + else + nextState = `cFIND_REC; + updateCounter = 1; + end + else + begin + nextState = `cWAIT_COL; + updateCounter = 0; + end + `cSTORE_DIAG: + begin + if (mode == 0) + nextState = `cFIND_REC; + else + nextState = `cFETCH_COL; + updateCounter = 1; + end + `cFIND_REC: + if (divCounter == 56) + begin + if (mode == 0) + nextState = `cMULT_COL; + else + nextState = `cSTORE_DIAG2; + updateCounter = 1; + end + else + begin + nextState = `cFIND_REC; + updateCounter = 0; + end + `cSTORE_DIAG2: + begin + nextState = `cMULT_COL; + updateCounter = 1; + end + `cMULT_COL: + if (topIdxCounter == mdivk-1) + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + else + begin + nextState = `cMULT_COL; + updateCounter = 0; + end + `cUPDATE_J: + if ((mode[1] == 1 || counter >= 16-1) && doneFetchRow == 1) + begin + nextState = `cSTORE_MO; + updateCounter = 1; + end + else + begin + nextState = `cUPDATE_J; + updateCounter = 0; + end + `cSTORE_MO: + begin + if (j == stop2) + begin + if (counter == mdivk-1+5-2) + nextState = `cDONE; + else + nextState = `cSTORE_MO; + updateCounter = 0; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 1; + end + end + `cMULT_SUB: + if (topIdxCounter == mdivk-1) + begin + if (j == n-1) + nextState = `cINCRE_I; + else + nextState = `cMULT_SUB; + updateCounter = 1; + end + else + begin + nextState = `cMULT_SUB; + updateCounter = 0; + end + `cINCRE_I: + begin + nextState = `cWAIT; + updateCounter = 1; + end + `cWAIT: + if (waitCycles == 0) + begin + if (i1 == stop) + nextState = `cDONE; + else if (mode == 0) + nextState = `cSTORE_DIAG; + else if (mode == 1) + nextState = `cFIND_REC; + else + nextState = `cUPDATE_J; + updateCounter = 1; + end + else + begin + nextState = `cWAIT; + updateCounter = 0; + end + `cDONE: + begin + nextState = `cDONE; + updateCounter = 0; + end + default: + begin + nextState = `cSETUP; + updateCounter = 1; + end + endcase +end + +always @ (currentRowState or currentState or nextState or i1 or topIdxCounter or mdivk or msIdxCounter or readRowCounter or j or n or mode) +begin + if (currentRowState == `cDONE_FETCH_ROW) + doneFetchRow = 1; + else + doneFetchRow = 0; + if((nextState == `cSTART_FETCH_ROW && currentState != `cSTART_FETCH_ROW && i1 == 1)) + startFetchRow = 1; + else + startFetchRow = 0; + if (currentState == `cMULT_SUB && topIdxCounter+2 == mdivk) + loadRow = 1; + else + loadRow = 0; + writeRow = (msIdxCounter == readRowCounter)&&(currentState==`cMULT_SUB)&&(j!=n)&&(mode[0] == 0); +end + +// second FSM that controls the control signals to temp_top block +always @ (currentRowState or nextTopIdxCounter or n or startFetchRow or loadRow or topIdx or mdivk or nextState) +begin + case (currentRowState) + `cFETCH_ROW: + if (nextTopIdxCounter == n-1) + nextRowState = `cDONE_FETCH_ROW; + else + nextRowState = `cFETCH_ROW; + `cDONE_FETCH_ROW: + if (startFetchRow == 1) + nextRowState = `cFETCH_ROW; + else if (loadRow == 1 || (topIdx+1 == mdivk && nextState == `cMULT_SUB)) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + `cLOAD_ROW_INC_J: + if (topIdx+1 == mdivk && nextState == `cMULT_SUB) + nextRowState = `cLOAD_ROW_INC_J; + else + nextRowState = `cDONE_FETCH_ROW; + default: + nextRowState = `cDONE_FETCH_ROW; + endcase +end + +// address counters +always @ (posedge clk) +begin + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + topIdxCounter <= topIdx; + else + topIdxCounter <= topIdxCounter + 1; + + if (updateCounter == 1) + diagIdxCounter <= diagIdx; + else + diagIdxCounter <= diagIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + msIdxCounter <= msIdx; + else + msIdxCounter <= msIdxCounter + 1; + + if (updateCounter == 1 || currentRowState == `cLOAD_ROW_INC_J) + leftIdxCounter <= leftIdx; + else + leftIdxCounter <= leftIdxCounter + 1; + + if (currentState == `cFETCH_COL || currentState == `cSTORE_MO) + topWriteCounter <= i1; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + topWriteCounter <= topWriteCounter + 1; + + if (currentState == `cSTART) + nextTopIdxCounter <= nextTopIdx; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + nextTopIdxCounter <= nextTopIdx + n + 1; + else + nextTopIdxCounter <= nextTopIdx + n; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + nextTopIdxCounter <= nextTopIdxCounter + 1; + + if (currentState == `cSTART) + readRowCounter <= 0; //offsetdivk; + else if (currentState == `cSTORE_MO) + if (mode[1] == 0) + readRowCounter <= leftIdx + 2; + else + readRowCounter <= topIdx; + else if (writeRow == 1 || currentRowState == `cFETCH_ROW) + readRowCounter <= readRowCounter + 2; + + if (updateCounter == 1) + counter <= 0; + else + counter <= counter + 1; + + if (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2) + divCounter <= 0; + else if (divCounter < 56) + divCounter <= divCounter + 1; + + case (i1modk) + 3'b000: begin + i1modkByteEn <= ~(32'b0) >> (3'b000<<2'b10); + end + 3'b001: begin + i1modkByteEn <= ~(32'b0) >> (3'b001<<2'b10); + end + 3'b010: begin + i1modkByteEn <= ~(32'b0) >> (3'b010<<2'b10); + end + 3'b011: begin + i1modkByteEn <= ~(32'b0) >> (3'b011<<2'b10); + end + 3'b100: begin + i1modkByteEn <= ~(32'b0) >> (3'b100<<2'b10); + end + 3'b101: begin + i1modkByteEn <= ~(32'b0) >> (3'b101<<2'b10); + end + 3'b110: begin + i1modkByteEn <= ~(32'b0) >> (3'b110<<2'b10); + end + 3'b111: begin + i1modkByteEn <= ~(32'b0) >> (3'b111<<2'b10); + end + default: begin + i1modkByteEn <= ~(32'b0); + end + endcase +end + +// compute Byte Enable +always @ (posedge clk) +begin + if ((nextState == `cMULT_COL && currentState != `cMULT_COL) || (currentState == `cSTORE_MO) || currentRowState == `cLOAD_ROW_INC_J) + byteEn <= i1modkByteEn; + else + byteEn <= 32'b11111111111111111111111111111111; +end + +// update FSM state register +always @ (posedge clk) +begin + if (start_in == 1'b1) + currentState <= `cSETUP; + else + currentState <= nextState; + if (start == 1'b1) + currentRowState <= `cDONE_FETCH_ROW; + else + currentRowState <= nextRowState; +end + +// delay register for control signals +// control signals are delayed to match latency of operations and/or memory access +always @ (posedge clk) +begin + curReadAddrDelay0 <= curReadAddrDelay1; + curReadAddrDelay1 <= curReadAddrDelay2; + curReadAddrDelay2 <= curReadAddrDelay3; + curReadAddrDelay3 <= curReadAddrDelay4; + curReadAddrDelay4 <= curReadAddrDelay5; + curReadAddrDelay5 <= curReadAddrDelay6; + curReadAddrDelay6 <= curReadAddrDelay7; + curReadAddrDelay7 <= curReadAddrDelay8; + curReadAddrDelay8 <= curReadAddrDelay9; + curReadAddrDelay9 <= curReadAddrDelay10; + curReadAddrDelay10 <= curReadAddrDelay11; + curReadAddrDelay11 <= msIdxCounter; + + curWriteAddrDelay0 <= curWriteAddrDelay1; + curWriteAddrDelay1 <= curWriteAddrDelay2; + curWriteAddrDelay2 <= curWriteAddrDelay3; + curWriteAddrDelay3 <= curWriteAddrDelay4; + if (currentState == `cFETCH_COL) + curWriteAddrDelay4 <= diagIdxCounter; + else + curWriteAddrDelay4 <= curWriteAddrDelay5; + curWriteAddrDelay5 <= curWriteAddrDelay6; + curWriteAddrDelay6 <= curWriteAddrDelay7; + curWriteAddrDelay7 <= curWriteAddrDelay8; + curWriteAddrDelay8 <= curWriteAddrDelay9; + curWriteAddrDelay9 <= curWriteAddrDelay10; + curWriteAddrDelay10 <= curWriteAddrDelay11; + curWriteAddrDelay11 <= curWriteAddrDelay12; + curWriteAddrDelay12 <= curWriteAddrDelay13; + curWriteAddrDelay13 <= curWriteAddrDelay14; + curWriteAddrDelay14 <= curWriteAddrDelay15; + if (currentState == `cMULT_COL) + curWriteAddrDelay15 <= leftIdxCounter; + else + curWriteAddrDelay15 <= curWriteAddrDelay16; + curWriteAddrDelay16 <= curWriteAddrDelay17; + curWriteAddrDelay17 <= curWriteAddrDelay18; + curWriteAddrDelay18 <= curWriteAddrDelay19; + curWriteAddrDelay19 <= curWriteAddrDelay20; + curWriteAddrDelay20 <= curWriteAddrDelay21; + curWriteAddrDelay21 <= curWriteAddrDelay22; + curWriteAddrDelay22 <= curWriteAddrDelay23; + curWriteAddrDelay23 <= curWriteAddrDelay24; + curWriteAddrDelay24 <= curWriteAddrDelay25; + curWriteAddrDelay25 <= curWriteAddrDelay26; + curWriteAddrDelay26 <= curWriteAddrDelay27; + curWriteAddrDelay27 <= curWriteAddrDelay28; + curWriteAddrDelay28 <= curWriteAddrDelay29; + curWriteAddrDelay29 <= curWriteAddrDelay30; + curWriteAddrDelay30 <= curWriteAddrDelay31; + curWriteAddrDelay31 <= msIdxCounter; + + writeByteEnDelay0 <= writeByteEnDelay1; + writeByteEnDelay1 <= writeByteEnDelay2; + writeByteEnDelay2 <= writeByteEnDelay3; + writeByteEnDelay3 <= writeByteEnDelay4; + if (mode[0] == 1'b1) + writeByteEnDelay4 <= ~0; + else if (currentState == `cFETCH_COL) + writeByteEnDelay4 <= byteEn; + else + writeByteEnDelay4 <= writeByteEnDelay5; + writeByteEnDelay5 <= writeByteEnDelay6; + writeByteEnDelay6 <= writeByteEnDelay7; + writeByteEnDelay7 <= writeByteEnDelay8; + writeByteEnDelay8 <= writeByteEnDelay9; + writeByteEnDelay9 <= writeByteEnDelay10; + writeByteEnDelay10 <= writeByteEnDelay11; + writeByteEnDelay11 <= writeByteEnDelay12; + writeByteEnDelay12 <= writeByteEnDelay13; + writeByteEnDelay13 <= writeByteEnDelay14; + writeByteEnDelay14 <= writeByteEnDelay15; + if (currentState == `cMULT_COL) + writeByteEnDelay15 <= byteEn; + else + writeByteEnDelay15 <= writeByteEnDelay16; + writeByteEnDelay16 <= writeByteEnDelay17; + writeByteEnDelay17 <= writeByteEnDelay18; + writeByteEnDelay18 <= writeByteEnDelay19; + writeByteEnDelay19 <= writeByteEnDelay20; + writeByteEnDelay20 <= writeByteEnDelay21; + writeByteEnDelay21 <= writeByteEnDelay22; + writeByteEnDelay22 <= writeByteEnDelay23; + writeByteEnDelay23 <= writeByteEnDelay24; + writeByteEnDelay24 <= writeByteEnDelay25; + writeByteEnDelay25 <= writeByteEnDelay26; + writeByteEnDelay26 <= writeByteEnDelay27; + writeByteEnDelay27 <= writeByteEnDelay28; + writeByteEnDelay28 <= writeByteEnDelay29; + writeByteEnDelay29 <= writeByteEnDelay30; + writeByteEnDelay30 <= writeByteEnDelay31; + writeByteEnDelay31 <= byteEn; + + curWriteSelDelay[0] <= curWriteSelDelay[1]; + curWriteSelDelay[1] <= curWriteSelDelay[2]; + curWriteSelDelay[2] <= curWriteSelDelay[3]; + curWriteSelDelay[3] <= curWriteSelDelay[4]; + curWriteSelDelay[4] <= curWriteSelDelay[5]; + curWriteSelDelay[5] <= curWriteSelDelay[6]; + curWriteSelDelay[6] <= curWriteSelDelay[7]; + curWriteSelDelay[7] <= curWriteSelDelay[8]; + curWriteSelDelay[8] <= curWriteSelDelay[9]; + curWriteSelDelay[9] <= curWriteSelDelay[10]; + curWriteSelDelay[10] <= curWriteSelDelay[11]; + curWriteSelDelay[11] <= curWriteSelDelay[12]; + curWriteSelDelay[12] <= curWriteSelDelay[13]; + curWriteSelDelay[13] <= curWriteSelDelay[14]; + curWriteSelDelay[14] <= curWriteSelDelay[15]; + if (currentState == `cMULT_COL) + curWriteSelDelay[15] <= 1'b0; + else + curWriteSelDelay[15] <= 1'b1; + + curWriteEnDelay[0] <= curWriteEnDelay[1]; + curWriteEnDelay[1] <= curWriteEnDelay[2]; + curWriteEnDelay[2] <= curWriteEnDelay[3]; + curWriteEnDelay[3] <= curWriteEnDelay[4]; + curWriteEnDelay[4] <= curWriteEnDelay[5]; + curWriteEnDelay[5] <= curWriteEnDelay[6]; + curWriteEnDelay[6] <= curWriteEnDelay[7]; + curWriteEnDelay[7] <= curWriteEnDelay[8]; + curWriteEnDelay[8] <= curWriteEnDelay[9]; + curWriteEnDelay[9] <= curWriteEnDelay[10]; + curWriteEnDelay[10] <= curWriteEnDelay[11]; + curWriteEnDelay[11] <= curWriteEnDelay[12]; + curWriteEnDelay[12] <= curWriteEnDelay[13]; + curWriteEnDelay[13] <= curWriteEnDelay[14]; + curWriteEnDelay[14] <= curWriteEnDelay[15]; + if (currentState == `cMULT_COL) + curWriteEnDelay[15] <= 1'b1; + else + curWriteEnDelay[15] <= curWriteEnDelay[16]; + curWriteEnDelay[16] <= curWriteEnDelay[17]; + curWriteEnDelay[17] <= curWriteEnDelay[18]; + curWriteEnDelay[18] <= curWriteEnDelay[19]; + curWriteEnDelay[19] <= curWriteEnDelay[20]; + curWriteEnDelay[20] <= curWriteEnDelay[21]; + curWriteEnDelay[21] <= curWriteEnDelay[22]; + curWriteEnDelay[22] <= curWriteEnDelay[23]; + curWriteEnDelay[23] <= curWriteEnDelay[24]; + curWriteEnDelay[24] <= curWriteEnDelay[25]; + curWriteEnDelay[25] <= curWriteEnDelay[26]; + curWriteEnDelay[26] <= curWriteEnDelay[27]; + curWriteEnDelay[27] <= curWriteEnDelay[28]; + curWriteEnDelay[28] <= curWriteEnDelay[29]; + curWriteEnDelay[29] <= curWriteEnDelay[30]; + curWriteEnDelay[30] <= curWriteEnDelay[31]; + if (currentState == `cMULT_SUB) + curWriteEnDelay[31] <= 1'b1; + else + curWriteEnDelay[31] <= 1'b0; + + leftWriteSelDelay[0] <= leftWriteSelDelay[1]; + leftWriteSelDelay[1] <= leftWriteSelDelay[2]; + leftWriteSelDelay[2] <= leftWriteSelDelay[3]; + leftWriteSelDelay[3] <= leftWriteSelDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteSelDelay[4] <= 1'b0; + else + leftWriteSelDelay[4] <= 1'b1; + + leftWriteEnDelay[0] <= leftWriteEnDelay[1]; + leftWriteEnDelay[1] <= leftWriteEnDelay[2]; + leftWriteEnDelay[2] <= leftWriteEnDelay[3]; + leftWriteEnDelay[3] <= leftWriteEnDelay[4]; + if (currentState == `cFETCH_COL) + leftWriteEnDelay[4] <= 1'b1; + else + leftWriteEnDelay[4] <= leftWriteEnDelay[5]; + leftWriteEnDelay[5] <= leftWriteEnDelay[6]; + leftWriteEnDelay[6] <= leftWriteEnDelay[7]; + leftWriteEnDelay[7] <= leftWriteEnDelay[8]; + leftWriteEnDelay[8] <= leftWriteEnDelay[9]; + leftWriteEnDelay[9] <= leftWriteEnDelay[10]; + leftWriteEnDelay[10] <= leftWriteEnDelay[11]; + leftWriteEnDelay[11] <= leftWriteEnDelay[12]; + leftWriteEnDelay[12] <= leftWriteEnDelay[13]; + leftWriteEnDelay[13] <= leftWriteEnDelay[14]; + leftWriteEnDelay[14] <= leftWriteEnDelay[15]; + if (currentState == `cMULT_COL) + leftWriteEnDelay[15] <= 1'b1; + else + leftWriteEnDelay[15] <= leftWriteEnDelay[16]; + leftWriteEnDelay[16] <= leftWriteEnDelay[17]; + leftWriteEnDelay[17] <= leftWriteEnDelay[18]; + leftWriteEnDelay[18] <= leftWriteEnDelay[19]; + leftWriteEnDelay[19] <= leftWriteEnDelay[20]; + leftWriteEnDelay[20] <= leftWriteEnDelay[21]; + leftWriteEnDelay[21] <= leftWriteEnDelay[22]; + leftWriteEnDelay[22] <= leftWriteEnDelay[23]; + leftWriteEnDelay[23] <= leftWriteEnDelay[24]; + leftWriteEnDelay[24] <= leftWriteEnDelay[25]; + leftWriteEnDelay[25] <= leftWriteEnDelay[26]; + leftWriteEnDelay[26] <= leftWriteEnDelay[27]; + leftWriteEnDelay[27] <= leftWriteEnDelay[28]; + leftWriteEnDelay[28] <= leftWriteEnDelay[29]; + leftWriteEnDelay[29] <= leftWriteEnDelay[30]; + leftWriteEnDelay[30] <= leftWriteEnDelay[31]; + if (currentState == `cMULT_SUB && (mode == 0 || (mode == 1 && j == i1))) + leftWriteEnDelay[31] <= 1'b1; + else + leftWriteEnDelay[31] <= 1'b0; + + topWriteAddrDelay0 <= topWriteAddrDelay1; + topWriteAddrDelay1 <= topWriteAddrDelay2; + topWriteAddrDelay2 <= topWriteAddrDelay3; + topWriteAddrDelay3 <= topWriteAddrDelay4; + if (currentRowState == `cFETCH_ROW) + topWriteAddrDelay4 <= nextTopIdxCounter; + else + topWriteAddrDelay4 <= topWriteAddrDelay5; + topWriteAddrDelay5 <= topWriteAddrDelay6; + topWriteAddrDelay6 <= topWriteAddrDelay7; + topWriteAddrDelay7 <= topWriteAddrDelay8; + topWriteAddrDelay8 <= topWriteAddrDelay9; + topWriteAddrDelay9 <= topWriteAddrDelay10; + topWriteAddrDelay10 <= topWriteAddrDelay11; + topWriteAddrDelay11 <= topWriteAddrDelay12; + topWriteAddrDelay12 <= topWriteAddrDelay13; + topWriteAddrDelay13 <= topWriteAddrDelay14; + topWriteAddrDelay14 <= topWriteAddrDelay15; + topWriteAddrDelay15 <= topWriteAddrDelay16; + topWriteAddrDelay16 <= topWriteAddrDelay17; + topWriteAddrDelay17 <= topWriteAddrDelay18; + topWriteAddrDelay18 <= topWriteAddrDelay19; + topWriteAddrDelay19 <= topWriteAddrDelay20; + topWriteAddrDelay20 <= topWriteAddrDelay21; + topWriteAddrDelay21 <= topWriteAddrDelay22; + topWriteAddrDelay22 <= topWriteAddrDelay23; + topWriteAddrDelay23 <= topWriteAddrDelay24; + topWriteAddrDelay24 <= topWriteAddrDelay25; + topWriteAddrDelay25 <= topWriteAddrDelay26; + topWriteAddrDelay26 <= topWriteAddrDelay27; + topWriteAddrDelay27 <= topWriteAddrDelay28; + topWriteAddrDelay28 <= topWriteAddrDelay29; + topWriteAddrDelay29 <= topWriteAddrDelay30; + topWriteAddrDelay30 <= topWriteAddrDelay31; + topWriteAddrDelay31 <= nextTopIdxCounter; + + topWriteEnDelay[0] <= topWriteEnDelay[1]; + topWriteEnDelay[1] <= topWriteEnDelay[2]; + topWriteEnDelay[2] <= topWriteEnDelay[3]; + topWriteEnDelay[3] <= topWriteEnDelay[4]; + if (currentRowState == `cFETCH_ROW) + topWriteEnDelay[4] <= 1'b1; + else + topWriteEnDelay[4] <= topWriteEnDelay[5]; + topWriteEnDelay[5] <= topWriteEnDelay[6]; + topWriteEnDelay[6] <= topWriteEnDelay[7]; + topWriteEnDelay[7] <= topWriteEnDelay[8]; + topWriteEnDelay[8] <= topWriteEnDelay[9]; + topWriteEnDelay[9] <= topWriteEnDelay[10]; + topWriteEnDelay[10] <= topWriteEnDelay[11]; + topWriteEnDelay[11] <= topWriteEnDelay[12]; + topWriteEnDelay[12] <= topWriteEnDelay[13]; + topWriteEnDelay[13] <= topWriteEnDelay[14]; + topWriteEnDelay[14] <= topWriteEnDelay[15]; + topWriteEnDelay[15] <= topWriteEnDelay[16]; + topWriteEnDelay[16] <= topWriteEnDelay[17]; + topWriteEnDelay[17] <= topWriteEnDelay[18]; + topWriteEnDelay[18] <= topWriteEnDelay[19]; + topWriteEnDelay[19] <= topWriteEnDelay[20]; + topWriteEnDelay[20] <= topWriteEnDelay[21]; + topWriteEnDelay[21] <= topWriteEnDelay[22]; + topWriteEnDelay[22] <= topWriteEnDelay[23]; + topWriteEnDelay[23] <= topWriteEnDelay[24]; + topWriteEnDelay[24] <= topWriteEnDelay[25]; + topWriteEnDelay[25] <= topWriteEnDelay[26]; + topWriteEnDelay[26] <= topWriteEnDelay[27]; + topWriteEnDelay[27] <= topWriteEnDelay[28]; + topWriteEnDelay[28] <= topWriteEnDelay[29]; + topWriteEnDelay[29] <= topWriteEnDelay[30]; + topWriteEnDelay[30] <= topWriteEnDelay[31]; + topWriteEnDelay[31] <= writeRow; + + topWriteSelDelay0 <= topWriteSelDelay1; + topWriteSelDelay1 <= topWriteSelDelay2; + topWriteSelDelay2 <= topWriteSelDelay3; + topWriteSelDelay3 <= topWriteSelDelay4; + if (currentRowState == `cFETCH_ROW || currentState == `cUPDATE_J && i1 == 1) + topWriteSelDelay4 <= imodk; + else + topWriteSelDelay4 <= topWriteSelDelay5; + topWriteSelDelay5 <= topWriteSelDelay6; + topWriteSelDelay6 <= topWriteSelDelay7; + topWriteSelDelay7 <= topWriteSelDelay8; + topWriteSelDelay8 <= topWriteSelDelay9; + topWriteSelDelay9 <= topWriteSelDelay10; + topWriteSelDelay10 <= topWriteSelDelay11; + topWriteSelDelay11 <= topWriteSelDelay12; + topWriteSelDelay12 <= topWriteSelDelay13; + topWriteSelDelay13 <= topWriteSelDelay14; + topWriteSelDelay14 <= topWriteSelDelay15; + topWriteSelDelay15 <= topWriteSelDelay16; + topWriteSelDelay16 <= topWriteSelDelay17; + topWriteSelDelay17 <= topWriteSelDelay18; + topWriteSelDelay18 <= topWriteSelDelay19; + topWriteSelDelay19 <= topWriteSelDelay20; + topWriteSelDelay20 <= topWriteSelDelay21; + topWriteSelDelay21 <= topWriteSelDelay22; + topWriteSelDelay22 <= topWriteSelDelay23; + topWriteSelDelay23 <= topWriteSelDelay24; + topWriteSelDelay24 <= topWriteSelDelay25; + topWriteSelDelay25 <= topWriteSelDelay26; + topWriteSelDelay26 <= topWriteSelDelay27; + topWriteSelDelay27 <= topWriteSelDelay28; + topWriteSelDelay28 <= topWriteSelDelay29; + topWriteSelDelay29 <= topWriteSelDelay30; + topWriteSelDelay30 <= topWriteSelDelay31; + topWriteSelDelay31 <= i1modk; + + topSourceSelDelay[0] <= topSourceSelDelay[1]; + topSourceSelDelay[1] <= topSourceSelDelay[2]; + topSourceSelDelay[2] <= topSourceSelDelay[3]; + topSourceSelDelay[3] <= topSourceSelDelay[4]; + if (start == 1'b1) + topSourceSelDelay[4] <= 1'b0; + else if (currentState == `cSTORE_MO) + topSourceSelDelay[4] <= 1'b1; + + leftReadAddrDelay0 <= leftIdxCounter; + + + diagEnDelay[0] <= diagEnDelay[1]; + diagEnDelay[1] <= diagEnDelay[2]; + diagEnDelay[2] <= diagEnDelay[3]; + diagEnDelay[3] <= diagEnDelay[4]; + diagEnDelay[4] <= diagEnDelay[5]; + diagEnDelay[5] <= (currentState == `cSTORE_DIAG || currentState == `cSTORE_DIAG2); + + MOEnDelay[0] <= MOEnDelay[1]; + MOEnDelay[1] <= MOEnDelay[2]; + MOEnDelay[2] <= MOEnDelay[3]; + MOEnDelay[3] <= MOEnDelay[4]; + MOEnDelay[4] <= MOEnDelay[5]; + if (currentState == `cSTORE_MO || currentRowState == `cLOAD_ROW_INC_J) + MOEnDelay[5] <= 1'b1; + else + MOEnDelay[5] <= 1'b0; +end + +// output contorl signals +always @ (posedge clk) +begin + if (currentState == `cFETCH_COL) + curReadAddr <= diagIdxCounter; + else if (currentRowState == `cFETCH_ROW) + curReadAddr <= readRowCounter; + else + curReadAddr <= curReadAddrDelay0; + curWriteAddr <= curWriteAddrDelay0; + curWriteByteEn <= writeByteEnDelay0; + curWriteSel <= curWriteSelDelay; + curWriteEn <= curWriteEnDelay; + + if (currentState == `cMULT_COL) + leftReadAddr <= leftIdxCounter; + else + leftReadAddr <= leftReadAddrDelay0; + leftWriteAddr <= curWriteAddrDelay0; + leftWriteByteEn <= writeByteEnDelay0; + leftWriteSel <= leftWriteSelDelay; + leftWriteEn <= leftWriteEnDelay; + + if (currentState == `cSTORE_DIAG) + topReadAddr <= nextTopIdx; +else if (currentState == `cSTORE_DIAG2) + topReadAddr <= nextTopIdx2; + else + topReadAddr <= curTopIdx; + topWriteAddr <= topWriteAddrDelay0; + topWriteEn <= topWriteEnDelay; + topWriteSel <= topWriteSelDelay0; + topSourceSel <= topSourceSelDelay; + + MOSel <= ~(currentState == `cFIND_REC); +if (currentState == `cFIND_REC) + MOEn <= 1'b1; + else + MOEn <= MOEnDelay; + + diagEn <= diagEnDelay; + + if (currentState == `cDONE) + done <= 1'b1; + else + done <= 1'b0; +end + +endmodule + +module ram ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram1 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram2 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + +module ram3 ( + byteena_a, + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + input [`RAMNUMBYTES-1:0] byteena_a; + input clk; + input [`RAMWIDTH-1:0] data; + input [`rRAMSIZEWIDTH-1:0] rdaddress; + input [`rRAMSIZEWIDTH-1:0] wraddress; + input wren; + output [`RAMWIDTH-1:0] q; + wire [`RAMWIDTH-1:0] value_out; + wire [`RAMWIDTH-1:0] subwire; + assign q = subwire | dummy; + wire [`RAMWIDTH-1:0] uselessdata; + assign uselessdata = 256'b0; +wire j; +assign j = |byteena_a; + wire [`RAMWIDTH-1:0]dummy; + assign dummy = value_out & 256'b0; +dual_port_ram inst1( +.clk (clk), +.we1(wren), +.we2(1'b0), +.data1(data), +.data2(uselessdata), +.out1(value_out), +.out2(subwire), +.addr1(wraddress), +.addr2(rdaddress)); + + +endmodule + + +module top_ram ( + clk, + data, + rdaddress, + wraddress, + wren, + q + ); + + //parameter TOPSIZE = 256, TOPSIZEWIDTH = 8, TOPWIDTH = 32; + + input clk; + input [32-1:0] data; + input [8-1:0] rdaddress; + input [8-1:0] wraddress; + input wren; + output [32-1:0] q; + + wire [32-1:0] sub_wire0; + wire [32-1:0] q; + wire [32-1:0] junk_output; + assign q = sub_wire0 | dummy; + wire[32-1:0] dummy; + assign dummy = junk_output & 32'b0; + dual_port_ram inst2( + .clk (clk), + .we1(wren), + .we2(1'b0), + .data1(data), + .data2(data), + .out1(junk_output), + .out2(sub_wire0), + .addr1(wraddress), + .addr2(rdaddress)); + +endmodule + +module mult_add (clk, A, B, C, mult_result, add_result); +//parameter PRECISION = 32; +input clk; +input [32-1:0] A, B, C; +output [32-1:0] mult_result, add_result; +reg [32-1:0] mult_result; +reg [32-1:0] add_result; +wire [32-1:0] mult_comp_result; +reg [32-1:0] add_a, add_b; +wire [32-1:0] addition_result; +wire [31:0] dummy_wire; +assign dummy_wire = mult_comp_result>>2'b10; +//divsp MUL(.clk(clk), .rmode(2'b00), .fpu_op(3'b010), .opa(A), .opb(B), .ans(mult_comp_result) ); +wire [4:0]dummy_wire_2; +fpmul MUL(.clk(clk), .a(A), .b(B), .y_out(mult_comp_result), .control(2'b00), .flags(dummy_wire_2)); +fpu_add ADD(.clock(clk), .a1(C), .b1(dummy_wire), .sum(addition_result)); +always @ (posedge clk) +begin + add_result <= addition_result; + mult_result <= mult_comp_result[31:0]; +end +endmodule + + +//`define rFIFOINPUTWIDTH 64 +`define rFIFOSIZE 64 +`define rFIFOSIZEWIDTH 6 +`define rFIFOOUTPUTWIDTH 256 +`define rFIFORSIZEWIDTH 4 + `define wFIFOINPUTWIDTH 10'b0100000000 + `define wFIFOSIZE 6'b010000 + `define wFIFOSIZEWIDTH 4'b0100 + `define wFIFOOUTPUTWIDTH 8'b01000000 + `define wFIFORSIZEWIDTH 4'b0110 + //for addr_fifo +`define aFIFOSIZE 6'b010000 +`define aFIFOSIZEWIDTH 4'b0100 +`define aFIFOWIDTH 4'b0101 +//for memfifo +`define mFIFOSIZE 16 +`define mFIFOSIZEWIDTH 4 +//`define mFIFOWIDTH 28 + +`define BURSTLEN 3'b010 +`define BURSTWIDTH 3'b010 +`define DATAWIDTH 10'b0100000000 +`define DATANUMBYTES 7'b0100000 +`define MEMCONWIDTH 8'b01000000 +`define MEMCONNUMBYTES 5'b01000 +`define DDRSIZEWIDTH 6'b011000 +`define FIFOSIZE 6'b010000 +`define FIFOSIZEWIDTH 4'b0100 +`define RAMWIDTH 10'b0100000000 +`define RAMNUMBYTES 7'b0100000 +`define RAMSIZEWIDTH 4'b0101 +`define RATIO 4'b0100 +`define RAMLAT 4'b0101 + +`define dIDLE 0 +`define dWRITE 1 +`define dREAD 2 + +module DataTransferUnit (clk, dtu_write_req, dtu_read_req, dtu_mem_addr, dtu_ram_addr, dtu_size, dtu_ack, dtu_done, + ram_read_addr, ram_read_data, ram_write_byte_en, ram_write_data, ram_write_addr, ram_write_en, + mem_rdata, mem_rdata_valid, mem_ready, mem_wdata_req, reset_n, + burst_begin, mem_local_addr, mem_be, mem_read_req, mem_size, mem_wdata, mem_write_req + ); + +output burst_begin; +output [`DDRSIZEWIDTH-1:0] mem_local_addr; +output [`MEMCONNUMBYTES-1: 0] mem_be; +output mem_read_req; +output [`BURSTWIDTH-1:0] mem_size; +output [`MEMCONWIDTH-1:0] mem_wdata; +output mem_write_req; +input clk; +input [`MEMCONWIDTH-1:0] mem_rdata; +input mem_rdata_valid; +input mem_ready; +input mem_wdata_req; +input reset_n; + +input dtu_write_req; +input dtu_read_req; +input [`DDRSIZEWIDTH-1:0] dtu_mem_addr; +input [`RAMSIZEWIDTH-1:0] dtu_ram_addr; +input [4:0] dtu_size; +output dtu_ack; +output dtu_done; + +output[`RAMWIDTH-1:0] ram_write_data; +input[`RAMWIDTH-1:0] ram_read_data; +output[`RAMSIZEWIDTH-1:0] ram_write_addr, ram_read_addr; +output[`RAMNUMBYTES-1:0] ram_write_byte_en; +output ram_write_en; + +reg[`DDRSIZEWIDTH-1:0] mem_addr0; +reg[`DDRSIZEWIDTH-1:0] mem_addr1; +reg[`DDRSIZEWIDTH-1:0] mem_addr2; +reg[`DDRSIZEWIDTH-1:0] mem_addr3; +reg[`DDRSIZEWIDTH-1:0] mem_addr4; +reg[`DDRSIZEWIDTH-1:0] mem_addr5; + +reg [1:0] state; +wire [`DATAWIDTH-1:0] rdata, ram_write_dataw, ram_read_dataw; + +wire [`RAMSIZEWIDTH-1:0] rfifo_addr; +reg [`RAMLAT-1:0]fifo_write_reg; +reg [`RAMLAT-1:0]write_req_reg; +reg [`RAMLAT-1:0]read_req_reg; +reg [0:0]fifo_read_reg; +reg rdata_valid; +reg [1:0]test_complete_reg; +reg [`BURSTWIDTH-1:0] size_count0; +reg [`BURSTWIDTH-1:0] size_count1; +reg [`BURSTWIDTH-1:0] size_count2; +reg [`BURSTWIDTH-1:0] size_count3; +reg [`BURSTWIDTH-1:0] size_count4; + +reg [`RAMSIZEWIDTH-1:0] size; +reg [`RAMSIZEWIDTH-1:0]ram_addr0; +reg [`RAMSIZEWIDTH-1:0]ram_addr1; +reg [`RAMSIZEWIDTH-1:0]ram_addr2; +reg [`RAMSIZEWIDTH-1:0]ram_addr3; +reg [`RAMSIZEWIDTH-1:0]ram_addr4; + +reg [2:0] data_count; +reg ram_write_en_reg; + +wire read_req; +wire write_req; +wire [`FIFOSIZEWIDTH-1:0] wfifo_count; +wire rfull, wempty, rempty, rdcmd_empty, wrcmd_full, wrcmd_empty, rdata_empty; +wire [`DATAWIDTH-1:0] mem_data; +wire not_stall; +wire fifo_write, fifo_read; +wire rdata_req; +wire [`BURSTWIDTH+`DDRSIZEWIDTH+1:0] wrmem_cmd, rdmem_cmd; +wire mem_cmd_ready, mem_cmd_issue; + +// FIFOs to interact with off-chip memory +memcmd_fifo cmd_store( + //.aclr(~reset_n), + //.rdclk(phy_clk), + .clk(clk), + .data(wrmem_cmd), + .rdreq(mem_cmd_ready), + //.rdempty(rdcmd_empty), + .wrreq(mem_cmd_issue), + .full(wrcmd_full), + .empty(wrcmd_empty), + .q(rdmem_cmd) + ); + +wfifo wdata_store( + //.rdclk(phy_clk), + .clk(clk), + .data(mem_data), + .rdreq(mem_wdata_req), + .wrreq(fifo_write), + .empty(wempty), + .q(mem_wdata), + .usedw(wfifo_count) + ); + +addr_fifo raddress_store ( + .clk(clk), + .data(ram_addr3), + .wrreq(fifo_read), + .rdreq(rdata_req), + .empty(rempty), + .full(rfull), + .q(rfifo_addr) + ); + +rfifo rdata_store( + .clk(clk), + .data(mem_rdata), + .rdreq(rdata_req), + //.wrclk(phy_clk), + .wrreq(mem_rdata_valid), + .empty(rdata_empty), + .q(rdata) + ); + +assign mem_cmd_ready = (mem_ready == 1'b1);// && (rdcmd_empty == 0); +assign mem_cmd_issue = (wrcmd_full == 1'b0) && (write_req == 1 || read_req == 1'b1 || wrcmd_empty == 1'b1); +assign wrmem_cmd[27:26] = size_count0; +assign wrmem_cmd[`DDRSIZEWIDTH+1:2] = mem_addr0; +assign wrmem_cmd[1] = read_req; +assign wrmem_cmd[0] = write_req; +assign mem_write_req = rdmem_cmd[0];// && rdcmd_empty == 0; +assign mem_read_req = rdmem_cmd[1];// && rdcmd_empty == 0; +assign mem_local_addr = rdmem_cmd[`DDRSIZEWIDTH+1:2]; +assign burst_begin = 0; +assign mem_size = rdmem_cmd[`BURSTWIDTH+`DDRSIZEWIDTH+1:`DDRSIZEWIDTH+2]; +assign mem_be = ~0; +assign fifo_write = fifo_write_reg[0]; +assign write_req = (not_stall) ? write_req_reg[0] : 0; +assign read_req = (not_stall) ? read_req_reg[0] : 0; +assign fifo_read = (not_stall) ? fifo_read_reg[0] : 0; +assign not_stall = (wfifo_count < `FIFOSIZE-5) && (rfull == 0) && (wrcmd_full == 0); +assign dtu_ack = (state == `dIDLE); +assign dtu_done = (state == `dIDLE) && wempty && rempty; + +assign ram_write_dataw[63:0] = rdata[255:192]; +assign mem_data[63:0] = ram_read_dataw[255:192]; +assign ram_write_dataw[127:64] = rdata[191:128]; +assign mem_data[127:64] = ram_read_dataw[191:128]; +assign ram_write_dataw[191:128] = rdata[127:64]; +assign mem_data[191:128] = ram_read_dataw[127:64]; +assign ram_write_dataw[255:192] = rdata[63:0]; +assign mem_data[255:192] = ram_read_dataw[63:0]; +assign ram_write_data = ram_write_dataw[255:0]; +assign ram_read_dataw[255:0] = ram_read_data; +assign ram_write_addr = rfifo_addr; +assign ram_read_addr = ram_addr4; +assign ram_write_byte_en = ~0; +assign ram_write_en = ram_write_en_reg; +assign rdata_req = !rdata_empty; + +// FSM to produce off-chip memory commands +always @ (posedge clk) +begin + if (reset_n == 1'b0) + begin + state <= `dIDLE; + end + else + begin + case (state) + `dIDLE: + begin + if (dtu_write_req) + state <= `dWRITE; + else if (dtu_read_req) + state <= `dREAD; + else + state <= `dIDLE; + end + `dWRITE: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dWRITE; + end + `dREAD: + begin + if (not_stall && size == 0 && data_count < `BURSTLEN) + state <= `dIDLE; + else + state <= `dREAD; + end + default: + begin + state <= `dIDLE; + end + endcase + end +end + +always @ (posedge clk) +begin + + if (reset_n == 0) + begin + size <= 0; + data_count <= 0; + size_count4 <= 1; + mem_addr5 <= 0; + ram_addr4 <= 0; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (state == `dIDLE) + begin + size <= dtu_size; + size_count4 <= `BURSTLEN; + mem_addr5 <= dtu_mem_addr; + ram_addr4 <= dtu_ram_addr; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= 1'b0; + fifo_read_reg[0] <= 1'b0; + read_req_reg[`RAMLAT-1] <= 1'b0; + data_count <= 0; + end + else if (data_count >= `BURSTLEN && not_stall) + begin + data_count <= data_count - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + fifo_write_reg[`RAMLAT-1] <= 1'b0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (size == 0 && data_count == 0 && not_stall==1'b1) + begin + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= 0; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= 0; + end + else if (size == 0 && not_stall==1'b1) + begin + size_count4 <= data_count[`BURSTWIDTH-1:0]; + fifo_write_reg[`RAMLAT-1] <= 0; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= 0; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else if (not_stall==1'b1) + begin + size <= size - 1; + data_count <= data_count + `RATIO - `BURSTLEN; + mem_addr5 <= mem_addr5 + `BURSTLEN; + ram_addr4 <= ram_addr4+1; + fifo_write_reg[`RAMLAT-1] <= state == `dWRITE; + write_req_reg[`RAMLAT-1] <= state == `dWRITE; + fifo_read_reg[0] <= state == `dREAD; + read_req_reg[`RAMLAT-1] <= state == `dREAD; + end + else + begin + fifo_write_reg[`RAMLAT-1] <= 0; + end +end + + +always @ (posedge clk) +begin + if (reset_n == 0) + begin + fifo_write_reg[0] <= 1'b0; + fifo_write_reg[1] <= 1'b0; + fifo_write_reg[2] <= 1'b0; + fifo_write_reg[3] <= 1'b0; + end + else + begin + fifo_write_reg[0] <= fifo_write_reg[1]; + fifo_write_reg[1] <= fifo_write_reg[2]; + fifo_write_reg[2] <= fifo_write_reg[3]; + fifo_write_reg[3] <= fifo_write_reg[4]; + end + + if (reset_n == 1'b0) + begin + mem_addr0 <= 0; + ram_addr0 <= 0; + size_count0 <= 1; + write_req_reg[0] <= 0; + read_req_reg[0] <= 0; + mem_addr1 <= 0; + ram_addr1 <= 0; + size_count1 <= 1; + write_req_reg[1] <= 0; + read_req_reg[1] <= 0; + mem_addr2 <= 0; + ram_addr2 <= 0; + size_count2 <= 1; + write_req_reg[2] <= 0; + read_req_reg[2] <= 0; + mem_addr3 <= 0; + ram_addr3 <= 0; + size_count3 <= 1; + write_req_reg[3] <= 0; + read_req_reg[3] <= 0; + mem_addr4 <= 0; + end + else if (not_stall) + begin + size_count0 <= size_count1; + mem_addr0 <= mem_addr1; + ram_addr0 <= ram_addr1; + write_req_reg[0] <= write_req_reg[1]; + read_req_reg[0] <= read_req_reg[1]; + size_count1 <= size_count2; + mem_addr1 <= mem_addr2; + ram_addr1 <= ram_addr2; + write_req_reg[1] <= write_req_reg[2]; + read_req_reg[1] <= read_req_reg[2]; + size_count2 <= size_count3; + mem_addr2 <= mem_addr3; + ram_addr2 <= ram_addr3; + write_req_reg[2] <= write_req_reg[3]; + read_req_reg[2] <= read_req_reg[3]; + size_count3 <= size_count4; + mem_addr3 <= mem_addr4; + ram_addr3 <= ram_addr4; + write_req_reg[3] <= write_req_reg[4]; + read_req_reg[3] <= read_req_reg[4]; + mem_addr4 <= mem_addr5; + end + + ram_write_en_reg <= rdata_req; +end + +endmodule + +module rfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q + ); + + + input clk; + input wrreq; + input rdreq; + input [`rFIFOINPUTWIDTH-1:0] data; + output empty; + output [`rFIFOOUTPUTWIDTH-1:0] q; + + reg [`rFIFORSIZEWIDTH-1:0] wr_pointer; + reg [`rFIFORSIZEWIDTH-1:0] rd_pointer; + reg [`rFIFORSIZEWIDTH:0] status_cnt; + reg [`rFIFOOUTPUTWIDTH-1:0] q ; + reg[1:0] counter; + wire [`rFIFOINPUTWIDTH-1:0] data_ram; +assign empty = (status_cnt == 7'b0000000); +wire [`rFIFOINPUTWIDTH-1:0]junk_input; +wire [`rFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 64'b0000000000000000000000000000000000000000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q[`rFIFOINPUTWIDTH-1:0] <= data_ram; +else if (counter == 1) + q[127:64] <= data_ram; +else if (counter == 2) + q[191:128] <= data_ram; +else if (counter == 3) + q[255:192] <= data_ram; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; +// Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 64 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module wfifo ( + clk, + data, + rdreq, + wrreq, + empty, + q, + usedw + ); + + input clk; + input wrreq; + input rdreq; + input [`wFIFOINPUTWIDTH-1:0] data; + output empty; + output [`wFIFOOUTPUTWIDTH-1:0] q; + output [`wFIFOSIZEWIDTH-1:0] usedw; +//-----------Internal variables------------------- +reg [`wFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`wFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`wFIFOSIZEWIDTH:0] status_cnt; +reg [`wFIFOOUTPUTWIDTH-1:0] q ; +reg[1:0] counter; +wire [`wFIFOINPUTWIDTH-1:0] data_ram ; +assign empty = (status_cnt == 5'b00000); +wire [`wFIFOINPUTWIDTH-1:0]junk_input; +wire [`wFIFOINPUTWIDTH-1:0]junk_output; +assign junk_input = 256'b0; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end +end +always @ (posedge clk) +begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 2'b01; + end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) + counter <= 0; +else + counter <= counter + 2'b01; +if(counter == 0) + q <= data_ram[63:0]; +else if(counter == 1) + q <= data_ram[127:64]; +else if(counter == 2) + q <= data_ram[191:128]; +else if(counter == 3) + q <= data_ram[255:192]; +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000 )) + status_cnt <= status_cnt + 1'b1; +end +assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0]; + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +// synopsys translate_off +//`timescale 1 ps / 1 ps +// synopsys translate_on +module addr_fifo ( + clk, + data, + wrreq, + rdreq, + empty, + full, + q + ); + + input clk; + input [`aFIFOWIDTH-1:0] data; + input rdreq; + input wrreq; + output empty; + output full; + output [`aFIFOWIDTH-1:0] q; + +reg [`aFIFOSIZEWIDTH-1:0] wr_pointer; +reg [`aFIFOSIZEWIDTH-1:0] rd_pointer; +reg [`aFIFOSIZEWIDTH:0] status_cnt; +reg [`aFIFOWIDTH-1:0] q ; +wire [`aFIFOWIDTH-1:0] data_ram ; +assign full = (status_cnt == 5'b01111); +assign empty = (status_cnt == 5'b00000); +wire [`aFIFOWIDTH-1:0]junk_input; +wire [`aFIFOWIDTH-1:0]junk_output; +assign junk_input = 5'b00000; +always @ (posedge clk) +begin //WRITE_POINTER +if (wrreq) +begin +wr_pointer <= wr_pointer + 1'b1; +end +end +always @ (posedge clk) +begin //READ_POINTER +if (rdreq) +begin +rd_pointer <= rd_pointer + 1'b1; +end +end +always @ (posedge clk ) +begin //READ_DATA +if (rdreq) begin +q <= data_ram; +end +end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 5'b00000)) + status_cnt <= status_cnt - 1'b1; + // Write but no read. + else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000)) + status_cnt <= status_cnt + 1; +end + dual_port_ram ram_addr( +.we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable +.addr1 (wr_pointer) , // address_0 input +.addr2 (rd_pointer) , // address_q input +.data1 (data) , // data_0 bi-directional +.data2 (junk_input), // data_1 bi-directional +.clk(clk), +.out1 (data_ram), +.out2 (junk_output) + ); + + +endmodule + +module memcmd_fifo ( + clk, + data, + rdreq, + wrreq, + full, + empty, + q + ); + + input clk; + input [`mFIFOWIDTH-1:0] data; + input wrreq; + input rdreq; + output full; + output empty; + output [`mFIFOWIDTH-1:0] q; + + reg [`mFIFOSIZEWIDTH-1:0] wr_pointer; + reg [`mFIFOSIZEWIDTH-1:0] rd_pointer; + reg [`mFIFOSIZEWIDTH:0] status_cnt; + reg [`mFIFOWIDTH-1:0] q ; + wire [`mFIFOWIDTH-1:0] data_ram; + assign full = (status_cnt ==5'b01111); + assign empty = (status_cnt == 5'b00000); + wire [`mFIFOWIDTH-1:0]junk_input; + wire [`mFIFOWIDTH-1:0]junk_output; + assign junk_input = 28'b0000000000000000000000000000; + always @ (posedge clk) + begin //WRITE_POINTER + if (wrreq) + begin + wr_pointer <= wr_pointer + 1'b1; + end + end + always @ (posedge clk) + begin //READ_POINTER + if (rdreq) + begin + rd_pointer <= rd_pointer + 1'b1; + end + end + always @ (posedge clk ) + begin //READ_DATA + if (rdreq) begin + q <= data_ram; + end + end +always @ (posedge clk ) +begin // : STATUS_COUNTER + if ((rdreq) && (!wrreq) && (status_cnt != 0)) + status_cnt <= status_cnt - 1'b1; + else if ((wrreq) && (!rdreq) && (status_cnt != 16 )) + status_cnt <= status_cnt + 1'b1; +end + dual_port_ram ram_addr( + .we1 (wrreq) , // write enable + .we2 (rdreq) , // Read enable + .addr1 (wr_pointer) , // address_0 input + .addr2 (rd_pointer) , // address_q input + .data1 (data) , // data_0 bi-directional + .data2 (junk_input), // data_1 bi-directional + .clk(clk), + .out1 (data_ram), + .out2 (junk_output)); + + +endmodule + + +`define ZERO 8'b00000000 +`define ONE 8'b00000001 +`define TWO 8'b00000010 +`define THREE 8'b00000011 +`define FOUR 8'b00000100 +`define FIVE 8'b00000101 +`define SIX 8'b00000110 +`define SEVEN 8'b00000111 +`define EIGHT 8'b00001000 +`define NINE 8'b00001001 +`define TEN 8'b00001010 +`define ELEVEN 8'b00001011 +`define TWELVE 8'b00001100 +`define THIRTEEN 8'b00001101 +`define FOURTEEN 8'b00001110 +`define FIFTEEN 8'b00001111 +`define SIXTEEN 8'b00010000 +`define SEVENTEEN 8'b00010001 +`define EIGHTEEN 8'b00010010 +`define NINETEEN 8'b00010011 +`define TWENTY 8'b00010100 +`define TWENTYONE 8'b00010101 +`define TWENTYTWO 8'b00010110 +`define TWENTYTHREE 8'b00010111 +`define TWENTYFOUR 8'b00011000 + +module fpu_add (clock, a1, b1, sum); + input clock; + input [31:0]a1; + input [31:0]b1; + output [31:0]sum; + reg [31:0]sum; + + //Split up the numbers into exponents and mantissa. + reg [7:0]a_exp; + //reg [7:0]b_exp; + reg [23:0]a_man; + reg [23:0]b_man; + + reg [7:0]temp; + + reg [24:0]sum_man; + //reg [7:0]sum_exp; + + //introduce latency on inputs + reg [31:0]a; + reg [31:0]b; + + always @ (posedge clock) begin + a <= a1; + b <= b1; + end + + reg smaller; //smaller is 1 if a < b, 0 otherwise + + //Shift mantissa's to have the same exponent + always @ (a or b) begin + //a_exp = a[30:23]; + //b_exp = b[30:23]; + //a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]}; + + if (a[30:23] < b[30:23]) begin + temp = b[30:23] - a[30:23]; + //a_man = {1'b1, a[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + a_man = {1'b1, a[22:0]} >> `ONE; + end + `TWO: begin + a_man = {1'b1, a[22:0]} >> `TWO; + end + `THREE: begin + a_man = {1'b1, a[22:0]} >> `THREE; + end + `FOUR: begin + a_man = {1'b1, a[22:0]} >> `FOUR; + end + `FIVE: begin + a_man = {1'b1, a[22:0]} >> `FIVE; + end + `SIX: begin + a_man = {1'b1, a[22:0]} >> `SIX; + end + `SEVEN: begin + a_man = {1'b1, a[22:0]} >> `SEVEN; + end + `EIGHT: begin + a_man = {1'b1, a[22:0]} >> `EIGHT; + end + `NINE: begin + a_man = {1'b1, a[22:0]} >> `NINE; + end + `TEN: begin + a_man = {1'b1, a[22:0]} >> `TEN; + end + `ELEVEN: begin + a_man = {1'b1, a[22:0]} >> `ELEVEN; + end + `TWELVE: begin + a_man = {1'b1, a[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + a_man = {1'b1, a[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + a_man = {1'b1, a[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + a_man = {1'b1, a[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + a_man = {1'b1, a[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + a_man = {1'b1, a[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + a_man = {1'b1, a[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + a_man = {1'b1, a[22:0]} >> `NINETEEN; + end + `TWENTY: begin + a_man = {1'b1, a[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + a_man = {1'b1, a[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + a_man = {1'b1, a[22:0]} >> `TWENTYFOUR; + end + endcase + + b_man = {1'b1, b[22:0]}; + a_exp = b[30:23]; + //b_exp = b[30:23]; + + end else if (a[30:23] > b[30:23]) begin + temp = a[30:23] - b[30:23]; + a_man = {1'b1, a[22:0]}; + //b_man = {1'b1, b[22:0]} >> temp; //Expand into case statement, as below. + case (temp) + `ONE: begin + b_man = {1'b1, b[22:0]} >> `ONE; + end + `TWO: begin + b_man = {1'b1, b[22:0]} >> `TWO; + end + `THREE: begin + b_man = {1'b1, b[22:0]} >> `THREE; + end + `FOUR: begin + b_man = {1'b1, b[22:0]} >> `FOUR; + end + `FIVE: begin + b_man = {1'b1, b[22:0]} >> `FIVE; + end + `SIX: begin + b_man = {1'b1, b[22:0]} >> `SIX; + end + `SEVEN: begin + b_man = {1'b1, b[22:0]} >> `SEVEN; + end + `EIGHT: begin + b_man = {1'b1, b[22:0]} >> `EIGHT; + end + `NINE: begin + b_man = {1'b1, b[22:0]} >> `NINE; + end + `TEN: begin + b_man = {1'b1, b[22:0]} >> `TEN; + end + `ELEVEN: begin + b_man = {1'b1, b[22:0]} >> `ELEVEN; + end + `TWELVE: begin + b_man = {1'b1, b[22:0]} >> `TWELVE; + end + `THIRTEEN: begin + b_man = {1'b1, b[22:0]} >> `THIRTEEN; + end + `FOURTEEN: begin + b_man = {1'b1, b[22:0]} >> `FOURTEEN; + end + `FIFTEEN: begin + b_man = {1'b1, b[22:0]} >> `FIFTEEN; + end + `SIXTEEN: begin + b_man = {1'b1, b[22:0]} >> `SIXTEEN; + end + `SEVENTEEN: begin + b_man = {1'b1, b[22:0]} >> `SEVENTEEN; + end + `EIGHTEEN: begin + b_man = {1'b1, b[22:0]} >> `EIGHTEEN; + end + `NINETEEN: begin + b_man = {1'b1, b[22:0]} >> `NINETEEN; + end + `TWENTY: begin + b_man = {1'b1, b[22:0]} >> `TWENTY; + end + `TWENTYONE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYONE; + end + `TWENTYTWO: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTWO; + end + `TWENTYTHREE: begin + b_man = {1'b1, b[22:0]} >> `TWENTYTHREE; + end + `TWENTYFOUR: begin + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + default: begin //More than twenty-four, shift by twenty-four. It is a boundary case. + b_man = {1'b1, b[22:0]} >> `TWENTYFOUR; + end + endcase + + a_exp = a[30:23]; + //b_exp = a[30:23]; + end else begin + temp = 8'b0; + a_man = {1'b1, a[22:0]}; + b_man = {1'b1, b[22:0]}; + a_exp = a[30:23]; + end + + end + + //Perform the addition operation + always @ (a_man or b_man or a or b) begin + if (a_man < b_man) begin + smaller = 1'b1; + end else begin + smaller = 1'b0; + end + + //both positive + if (~a[31] && ~b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b0; + end + + //both negative + else if (a[31] && b[31]) begin + sum_man = a_man + b_man; + sum[31] = 1'b1; + end + + //a pos, b neg + else if (~a[31] && b[31]) begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b1; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b0; + end + end + + //a neg, b pos + else /*if (a[31] && ~b[31])*/ begin + if (smaller) begin //a < b + sum_man = b_man - a_man; + sum[31] = 1'b0; + end else begin + sum_man = a_man - b_man; + sum[31] = 1'b1; + end + end + end + + //Store the number + // we already have the sign. + + always @ (sum_man or a_exp) begin + if (sum_man[24])begin //shif sum >> by 1, add 1 to the exponent. + sum[22:0] = sum_man[23:1]; + sum[30:23] = a_exp + 8'b00000001; + + end else if (sum_man[23]) begin //do nothing + sum[22:0] = sum_man[22:0]; + sum[30:23] = a_exp; + + end else if (sum_man[22]) begin //shift << by 1, subtract 1 from exponent. + sum[22:0] = {sum_man[21:0], 1'b0}; + sum[30:23] = a_exp - 8'b00000001; + + end else if (sum_man[21]) begin //shift << by 2, subtract 2 from exponent. + sum[22:0] = {sum_man[20:0], 2'b0}; + sum[30:23] = a_exp - 8'b00000010; + + end else if (sum_man[20]) begin //shift << by 3, subtract 3 from exponent. + sum[22:0] = {sum_man[19:0], 3'b0}; + sum[30:23] = a_exp - 8'b00000011; + + end else if (sum_man[19]) begin //shift << by 4, subtract 4 from exponent. + sum[22:0] = {sum_man[18:0], 4'b0}; + sum[30:23] = a_exp - 8'b00000100; + + end else if (sum_man[18]) begin //shift << by 5, subtract 5 from exponent. + sum[22:0] = {sum_man[17:0], 5'b0}; + sum[30:23] = a_exp - 8'b00000101; + + end else if (sum_man[17]) begin //shift << by 6, subtract 6 from exponent. + sum[22:0] = {sum_man[16:0], 6'b0}; + sum[30:23] = a_exp - 8'b00000110; + + end else if (sum_man[16]) begin //shift << by 7, subtract 7 from exponent. + sum[22:0] = {sum_man[15:0], 7'b0}; + sum[30:23] = a_exp - 8'b00000111; + + end else if (sum_man[15]) begin //shift << by 8, subtract 8 from exponent. + sum[22:0] = {sum_man[14:0], 8'b0}; + sum[30:23] = a_exp - 8'b00001000; + + end else if (sum_man[14]) begin //shift << by 9, subtract 9 from exponent. + sum[22:0] = {sum_man[13:0], 9'b0}; + sum[30:23] = a_exp - 8'b00001001; + + end else if (sum_man[13]) begin //shift << by 10, subtract 10 from exponent. + sum[22:0] = {sum_man[12:0], 10'b0}; + sum[30:23] = a_exp - 8'b00001010; + + end else if (sum_man[12]) begin //shift << by 11, subtract 11 from exponent. + sum[22:0] = {sum_man[11:0], 11'b0}; + sum[30:23] = a_exp - 8'b00001011; + + end else if (sum_man[11]) begin //shift << by 12, subtract 12 from exponent. + sum[22:0] = {sum_man[10:0], 12'b0}; + sum[30:23] = a_exp - 8'b00001100; + + end else if (sum_man[10]) begin //shift << by 13, subtract 13 from exponent. + sum[22:0] = {sum_man[9:0], 13'b0}; + sum[30:23] = a_exp - 8'b00001101; + + end else if (sum_man[9]) begin //shift << by 14, subtract 14 from exponent. + sum[22:0] = {sum_man[8:0], 14'b0}; + sum[30:23] = a_exp - 8'b00001110; + + end else if (sum_man[8]) begin //shift << by 15, subtract 15 from exponent. + sum[22:0] = {sum_man[7:0], 15'b0}; + sum[30:23] = a_exp - 8'b00001111; + + end else if (sum_man[7]) begin //shift << by 16, subtract 16 from exponent. + sum[22:0] = {sum_man[6:0], 16'b0}; + sum[30:23] = a_exp - 8'b00010000; + + end else if (sum_man[6]) begin //shift << by 17, subtract 17 from exponent. + sum[22:0] = {sum_man[5:0], 17'b0}; + sum[30:23] = a_exp - 8'b00010001; + + end else if (sum_man[5]) begin //shift << by 18, subtract 18 from exponent. + sum[22:0] = {sum_man[4:0], 18'b0}; + sum[30:23] = a_exp - 8'b00010010; + + end else if (sum_man[4]) begin //shift << by 19, subtract 19 from exponent. + sum[22:0] = {sum_man[3:0], 19'b0}; + sum[30:23] = a_exp - 8'b00010011; + + end else if (sum_man[3]) begin //shift << by 20, subtract 20 from exponent. + sum[22:0] = {sum_man[2:0], 20'b0}; + sum[30:23] = a_exp - 8'b00010100; + + end else if (sum_man[2]) begin //shift << by 21, subtract 21 from exponent. + sum[22:0] = {sum_man[1:0], 21'b0}; + sum[30:23] = a_exp - 8'b00010101; + + end else if (sum_man[1]) begin //shift << by 22, subtract 22 from exponent. + sum[22:0] = {sum_man[0:0], 22'b0}; + sum[30:23] = a_exp - 8'b00010110; + + end else /*if (sum_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + sum[22:0] = 23'b0; + sum[30:23] = a_exp - 8'b00010111; + end + + end + +endmodule + +module fpu_div(clock, n, d, div); +//n = numerator +//d = denomenator +//div = result + input clock; + + input [31:0]n; + input [31:0]d; + output [31:0]div; + reg [31:0]div; + + //Store the mantissa and exponents separately. Introduce the latency of 1. + reg [7:0]n_exp; + reg [7:0]d_exp; + reg [23:0]n_man; + reg [23:0]d_man; + reg n_sign; + reg d_sign; + + wire [23:0]div_man; + reg [7:0]div_exp; + + always @ (posedge clock) begin + n_exp <= n[30:23]; + d_exp <= d[30:23]; + n_man <= {1'b1, n[22:0]}; + d_man <= {1'b1, d[22:0]}; + n_sign <= n[31]; + d_sign <= d[31]; + end + + //Find the exponent, store in div_exp. + always @ (n_exp or d_exp) begin + if (n_exp >= d_exp) begin + div_exp = 8'b01111111 + (n_exp - d_exp); + end else begin + div_exp = 8'b01111111 - (d_exp - n_exp); + end + end + + //Divide the mantissas, store in div_man. + div_24b divide(.numer(n_man), .denom(d_man), .res(div_man)); + + //Store the result. Shift exponents appropriately. Store sign. + //Sign + always @ (n_sign or d_sign) begin + div[31] = n_sign ^ d_sign; + end + + //Mantissa and Exponent + always @ (div_man or div_exp) begin + if (div_man[23]) begin //do nothing + div[22:0] = div_man[22:0]; + div[30:23] = div_exp; + + end else if (div_man[22]) begin //shift << by 1, subtract 1 from exponent. + div[22:0] = {div_man[21:0], 1'b0}; + div[30:23] = div_exp - 8'b00000001; + + end else if (div_man[21]) begin //shift << by 2, subtract 2 from exponent. + div[22:0] = {div_man[20:0], 2'b0}; + div[30:23] = div_exp - 8'b00000010; + + end else if (div_man[20]) begin //shift << by 3, subtract 3 from exponent. + div[22:0] = {div_man[19:0], 3'b0}; + div[30:23] = div_exp - 8'b00000011; + + end else if (div_man[19]) begin //shift << by 4, subtract 4 from exponent. + div[22:0] = {div_man[18:0], 4'b0}; + div[30:23] = div_exp - 8'b00000100; + + end else if (div_man[18]) begin //shift << by 5, subtract 5 from exponent. + div[22:0] = {div_man[17:0], 5'b0}; + div[30:23] = div_exp - 8'b00000101; + + end else if (div_man[17]) begin //shift << by 6, subtract 6 from exponent. + div[22:0] = {div_man[16:0], 6'b0}; + div[30:23] = div_exp - 8'b00000110; + + end else if (div_man[16]) begin //shift << by 7, subtract 7 from exponent. + div[22:0] = {div_man[15:0], 7'b0}; + div[30:23] = div_exp - 8'b00000111; + + end else if (div_man[15]) begin //shift << by 8, subtract 8 from exponent. + div[22:0] = {div_man[14:0], 8'b0}; + div[30:23] = div_exp - 8'b00001000; + + end else if (div_man[14]) begin //shift << by 9, subtract 9 from exponent. + div[22:0] = {div_man[13:0], 9'b0}; + div[30:23] = div_exp - 8'b00001001; + + end else if (div_man[13]) begin //shift << by 10, subtract 10 from exponent. + div[22:0] = {div_man[12:0], 10'b0}; + div[30:23] = div_exp - 8'b00001010; + + end else if (div_man[12]) begin //shift << by 11, subtract 11 from exponent. + div[22:0] = {div_man[11:0], 11'b0}; + div[30:23] = div_exp - 8'b00001011; + + end else if (div_man[11]) begin //shift << by 12, subtract 12 from exponent. + div[22:0] = {div_man[10:0], 12'b0}; + div[30:23] = div_exp - 8'b00001100; + + end else if (div_man[10]) begin //shift << by 13, subtract 13 from exponent. + div[22:0] = {div_man[9:0], 13'b0}; + div[30:23] = div_exp - 8'b00001101; + + end else if (div_man[9]) begin //shift << by 14, subtract 14 from exponent. + div[22:0] = {div_man[8:0], 14'b0}; + div[30:23] = div_exp - 8'b00001110; + + end else if (div_man[8]) begin //shift << by 15, subtract 15 from exponent. + div[22:0] = {div_man[7:0], 15'b0}; + div[30:23] = div_exp - 8'b00001111; + + end else if (div_man[7]) begin //shift << by 16, subtract 16 from exponent. + div[22:0] = {div_man[6:0], 16'b0}; + div[30:23] = div_exp - 8'b00010000; + + end else if (div_man[6]) begin //shift << by 17, subtract 17 from exponent. + div[22:0] = {div_man[5:0], 17'b0}; + div[30:23] = div_exp - 8'b00010001; + + end else if (div_man[5]) begin //shift << by 18, subtract 18 from exponent. + div[22:0] = {div_man[4:0], 18'b0}; + div[30:23] = div_exp - 8'b00010010; + + end else if (div_man[4]) begin //shift << by 19, subtract 19 from exponent. + div[22:0] = {div_man[3:0], 19'b0}; + div[30:23] = div_exp - 8'b00010011; + + end else if (div_man[3]) begin //shift << by 20, subtract 20 from exponent. + div[22:0] = {div_man[2:0], 20'b0}; + div[30:23] = div_exp - 8'b00010100; + + end else if (div_man[2]) begin //shift << by 21, subtract 21 from exponent. + div[22:0] = {div_man[1:0], 21'b0}; + div[30:23] = div_exp - 8'b00010101; + + end else if (div_man[1]) begin //shift << by 22, subtract 22 from exponent. + div[22:0] = {div_man[0:0], 22'b0}; + div[30:23] = div_exp - 8'b00010110; + + end else /*if (div_man[0])*/ begin //shift << by 23, subtract 23 from exponent. + div[22:0] = 23'b0; + div[30:23] = div_exp - 8'b00010111; + end + + end + +endmodule + + + + + +module div_24b(numer, denom, res); + //input clock; + + input [23:0]numer; + input [23:0]denom; + output [23:0]res; + reg [23:0]res; + + //Pad with 23 zeros. + wire [46:0]denom_pad; + wire [46:0]numer23; + reg [46:0]numer22; + reg [46:0]numer21; + reg [46:0]numer20; + reg [46:0]numer19; + reg [46:0]numer18; + reg [46:0]numer17; + reg [46:0]numer16; + reg [46:0]numer15; + reg [46:0]numer14; + reg [46:0]numer13; + reg [46:0]numer12; + reg [46:0]numer11; + reg [46:0]numer10; + reg [46:0]numer9; + reg [46:0]numer8; + reg [46:0]numer7; + reg [46:0]numer6; + reg [46:0]numer5; + reg [46:0]numer4; + reg [46:0]numer3; + reg [46:0]numer2; + reg [46:0]numer1; + reg [46:0]numer0; + + //always @ (posedge clock) begin + assign denom_pad = {23'b0, denom}; + assign numer23 = {numer, 23'b0}; + // end + + //res[23] + always @ (denom_pad or numer23) begin + + if (denom_pad[23:0] <= numer23[46:23]) begin + res[23] = 1'b1; + numer22 = {numer23[46:23] - denom_pad[23:0], 23'b0}; + end else begin + res[23] = 1'b0; + numer22 = numer23; + end + + if (denom_pad[24:0] <= numer22[46:22]) begin + res[22] = 1'b1; + numer21 = {numer22[46:22] - denom_pad[24:0], 22'b0}; + end else begin + res[22] = 1'b0; + numer21 = numer22; + end + + if (denom_pad[25:0] <= numer21[46:21]) begin + res[21] = 1'b1; + numer20 = {numer21[46:21] - denom_pad[25:0], 21'b0}; + end else begin + res[21] = 1'b0; + numer20 = numer21; + end + + if (denom_pad[26:0] <= numer20[46:20]) begin + res[20] = 1'b1; + numer19 = {numer20[46:20] - denom_pad[26:0], 20'b0}; + end else begin + res[20] = 1'b0; + numer19 = numer20; + end + + if (denom_pad[27:0] <= numer19[46:19]) begin + res[19] = 1'b1; + numer18 = {numer19[46:19] - denom_pad[27:0], 19'b0}; + end else begin + res[19] = 1'b0; + numer18 = numer19; + end + + if (denom_pad[28:0] <= numer18[46:18]) begin + res[18] = 1'b1; + numer17 = {numer18[46:18] - denom_pad[28:0], 18'b0}; + end else begin + res[18] = 1'b0; + numer17 = numer18; + end + + if (denom_pad[29:0] <= numer17[46:17]) begin + res[17] = 1'b1; + numer16 = {numer17[46:17] - denom_pad[29:0], 17'b0}; + end else begin + res[17] = 1'b0; + numer16 = numer17; + end + + if (denom_pad[30:0] <= numer16[46:16]) begin + res[16] = 1'b1; + numer15 = {numer16[46:16] - denom_pad[30:0], 16'b0}; + end else begin + res[16] = 1'b0; + numer15 = numer16; + end + + if (denom_pad[31:0] <= numer15[46:15]) begin + res[15] = 1'b1; + numer14 = {numer15[46:15] - denom_pad[31:0], 15'b0}; + end else begin + res[15] = 1'b0; + numer14 = numer15; + end + + if (denom_pad[32:0] <= numer14[46:14]) begin + res[14] = 1'b1; + numer13 = {numer14[46:14] - denom_pad[32:0], 14'b0}; + end else begin + res[14] = 1'b0; + numer13 = numer14; + end + + if (denom_pad[33:0] <= numer13[46:13]) begin + res[13] = 1'b1; + numer12 = {numer13[46:13] - denom_pad[33:0], 13'b0}; + end else begin + res[13] = 1'b0; + numer12 = numer13; + end + + if (denom_pad[34:0] <= numer12[46:12]) begin + res[12] = 1'b1; + numer11 = {numer12[46:12] - denom_pad[34:0], 12'b0}; + end else begin + res[12] = 1'b0; + numer11 = numer12; + end + + if (denom_pad[35:0] <= numer11[46:11]) begin + res[11] = 1'b1; + numer10 = {numer11[46:11] - denom_pad[35:0], 11'b0}; + end else begin + res[11] = 1'b0; + numer10 = numer11; + end + + if (denom_pad[36:0] <= numer10[46:10]) begin + res[10] = 1'b1; + numer9 = {numer10[46:10] - denom_pad[36:0], 10'b0}; + end else begin + res[10] = 1'b0; + numer9 = numer10; + end + + if (denom_pad[37:0] <= numer9[46:9]) begin + res[9] = 1'b1; + numer8 = {numer9[46:9] - denom_pad[37:0], 9'b0}; + end else begin + res[9] = 1'b0; + numer8 = numer9; + end + + if (denom_pad[38:0] <= numer8[46:8]) begin + res[8] = 1'b1; + numer7 = {numer8[46:8] - denom_pad[38:0], 8'b0}; + end else begin + res[8] = 1'b0; + numer7 = numer8; + end + + if (denom_pad[39:0] <= numer7[46:7]) begin + res[7] = 1'b1; + numer6 = {numer7[46:7] - denom_pad[39:0], 7'b0}; + end else begin + res[7] = 1'b0; + numer6 = numer7; + end + + if (denom_pad[40:0] <= numer6[46:6]) begin + res[6] = 1'b1; + numer5 = {numer6[46:6] - denom_pad[40:0], 6'b0}; + end else begin + res[6] = 1'b0; + numer5 = numer6; + end + + if (denom_pad[41:0] <= numer5[46:5]) begin + res[5] = 1'b1; + numer4 = {numer5[46:5] - denom_pad[41:0], 5'b0}; + end else begin + res[5] = 1'b0; + numer4 = numer5; + end + + if (denom_pad[42:0] <= numer4[46:4]) begin + res[4] = 1'b1; + numer3 = {numer4[46:4] - denom_pad[42:0], 4'b0}; + end else begin + res[4] = 1'b0; + numer3 = numer4; + end + + if (denom_pad[43:0] <= numer3[46:3]) begin + res[3] = 1'b1; + numer2 = {numer3[46:3] - denom_pad[43:0], 3'b0}; + end else begin + res[3] = 1'b0; + numer2 = numer3; + end + + if (denom_pad[44:0] <= numer2[46:2]) begin + res[2] = 1'b1; + numer1 = {numer2[46:2] - denom_pad[44:0], 2'b0}; + end else begin + res[2] = 1'b0; + numer1 = numer2; + end + + if (denom_pad[45:0] <= numer1[46:1]) begin + res[1] = 1'b1; + numer0 = {numer1[46:1] - denom_pad[45:0], 1'b0}; + end else begin + res[1] = 1'b0; + numer0 = numer1; + end + + if (denom_pad <= numer0) begin + res[0] = 1'b1; + end else begin + res[0] = 1'b0; + end + + end + +endmodule + + +////////////////////////////////////////////// +// +// constants.v +// +// Version 1.3 +// Written 7/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 8/20/01 Mark_Phair@hmc.edu and Justin_Schauer@hmc.edu +// +// A set of constants for a parameterized floating point multiplier and adder. +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// FREE VARIABLES +////////////////////////////////////////////// + +// Widths of Fields +`define WEXP 8 +`define WSIG 23 +`define WFLAG 5 +`define WCONTROL 5 + +// output flag select (flags[x]) +`define DIVZERO 0 +`define INVALID 1 +`define INEXACT 2 +`define OVERFLOW 3 +`define UNDERFLOW 4 + +////////////////////////////////////////////// +// DEPENDENT VARIABLES +////////////////////////////////////////////// + +`define WIDTH 32 //(`WEXP + `WSIG + 1) +`define PRODWIDTH 48 //(2 * (`WSIG + 1)) +`define SHIFTWIDTH 96 //(2 * `PRODWIDTH)) +`define WPRENORM 24 // `WSIG + 1 +`define WEXPSUM 10 // `WEXP + 2 +`define BIAS 127 // (2^(`WEXP)) - 1 +`define WSIGMINUS1 22 // `WSIG - 1, used for rounding +`define WSHIFTAMT 5 // log2(`WSIG + 1) rounded up + +// for trapped over/underflow +`define UNDERBIAS 192 // 3 * 2 ^ (`WEXP -2) +`define OVERBIAS -192 // -`UNDERBIAS + +// specialized constants for fpadd +`define EXTRASIG 25 // `WSIG+2 this is the amount of precision needed so no + // subtraction errors occur +`define SHIFT 5 // # bits the max alignment shift will fit in (log2(`WSIG+2) + // rounded up to nearest int) +`define MAX_EXP 8'b11111110 // the maximum non-infinite exponent, + // `WEXP bits, the most significant + // `WEXP-1 bits are 1, the LSB is 0 +`define INF_EXP 8'b11111111 // Infinity exponent, `WEXP bits, all 1 +// Max significand, `WSIG bits, all 1 +`define MAX_SIG 23'b11111111111111111111111 +`define WEXP_0 8'b0 // Exponent equals `WEXP'b0 +`define WEXP_1 8'b1 // Exponent equals one `WEXP'b1 +`define WSIG_0 23'b0 // Significand equals zero `WSIG'b0 +`define WSIG_1 23'b1 // Significand equals one `WSIG'b1 +`define EXTRASIG_0 25'b0 // All result bits for adder zero `EXTRASIG'b0 + +// specialized constants for fpmul +`define MAXSHIFT 24 // `WSIG + 1 + +// GENERAL SPECIAL NUMBERS - Exp + Significand of special numbers +// plain NaN `WIDTH-1, all 1 +`define CONSTNAN {9'b111111111,22'b0} +// zero `WIDTH-1, all 0 +`define CONSTZERO 31'b0 +// infinity `WEXP all 1, `WSIG all 0 +`define CONSTINFINITY {8'b11111111, 23'b0} +// largest number maximum exponent(all 1's - 1) and maximum significand (all 1's) +`define CONSTLARGEST {`MAX_EXP, `MAX_SIG} +`define PRESHIFTZEROS 48'b0 // `PRODWIDTH'b0 + +////////////////////////////////////////////// +// +// fpmul.v +// +// Version 1.6 +// Written 07/11/01 David_Harris@hmc.edu & Mark_Phair@hmc.edu +// Modifed 08/20/01 Mark_Phair@hmc.edu +// +// A parameterized floating point multiplier. +// +// BLOCK DESCRIPTIONS +// +// preprocess - general processing, such as zero detection, computing sign, NaN +// +// prenorm - normalize denorms +// +// exponent - sum the exponents, check for tininess before rounding +// +// multiply - multiply the mantissae +// +// special - calculate special cases, such as NaN and infinities +// +// shift - shift the sig and exp if nesc. +// +// round - round product +// +// normalize - normalizes the result if appropriate (i.e. not a denormalized #) +// +// flag - general flag processing +// +// assemble - assemble results +// +////////////////////////////////////////////// + +////////////////////////////////////////////// +// Includes +////////////////////////////////////////////// + + + +////////////////////////////////////////////// +// fpmul module +////////////////////////////////////////////// + +module fpmul(clk, a, b, y_out, control, flags) ; + + input clk; + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-1:0] y_out; // floating-point product + reg [`WIDTH-1:0] y_out; + input [1:0] control; // control including rounding mode + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + //intermediate y_out + wire [`WIDTH-1:0]y; + + // internal signals + wire multsign; // sign of product + wire specialsign; // sign of special + + wire [`WSIG:0] norma; // normal-form mantissa a, 1 bit larger to hold leading 1 + wire [`WSIG:0] normb; // normal-form mantissa b, 1 bit larger to hold leading 1 + + wire [`WEXPSUM-1:0] expa, expb; // the two exponents, after prenormalization + wire [`WEXPSUM-1:0] expsum; // sum of exponents (two's complement) + wire [`WEXPSUM-1:0] shiftexp; // shifted exponent + wire [`WEXP-1:0] roundexp; // rounded, correct exponent + + wire [`PRODWIDTH-1:0] prod; // product of mantissae + wire [`PRODWIDTH-1:0] normalized; // Normalized product + wire [`SHIFTWIDTH-1:0] shiftprod; // shifted product + wire [`WSIG-1:0] roundprod; // rounded product + wire [`WIDTH-2:0] special; // special case exponent and product + + wire twoormore; // product is outside range [1,2) + wire zero; // zero detected + wire infinity; // infinity detected + wire aisnan; // NaN detected in A + wire bisnan; // NaN detected in B + wire aisdenorm; // Denormalized number detected in A + wire bisdenorm; // Denormalized number detected in B + wire specialcase; // This is a special case + wire specialsigncase; // Use the special case sign + wire roundoverflow; // overflow in rounding, need to add 1 to exponent + wire invalid; // invalid operation + wire overflow; // exponent result too high, standard overflow + wire inexact; // inexact flag + wire shiftloss; // lost digits due to a shift, result inaccurate + wire [1:0] roundmode; // rounding mode information extracted from control field + wire tiny; // Result is tiny (denormalized #) after multiplication + wire stilltiny; // Result is tiny (denormalized #) after rounding + wire denormround; // rounding occured only because the initial result was + // a denormalized number. This is used to determine + // underflow in cases of denormalized numbers rounding + // up to normalized numbers + + preprocess preprocesser(a, b, zero, aisnan, bisnan, + aisdenorm, bisdenorm, infinity, + control, roundmode, sign); + + special specialer(a, b, special, specialsign, zero, + aisnan, bisnan, + infinity, invalid, + specialcase, specialsigncase); + + prenorm prenormer(a[`WIDTH-2:0], b[`WIDTH-2:0], norma, normb, expa, expb, aisdenorm, bisdenorm); + + multiply_a multiplier(norma, normb, prod, twoormore); + + exponent exponenter(expa, expb, expsum, twoormore, tiny); + + normalize normalizer(prod, normalized, tiny, twoormore); + + shift shifter(normalized, expsum, shiftprod, + shiftexp, shiftloss); + + round rounder(shiftprod, shiftexp, shiftloss, + roundprod, roundexp, + roundmode, sign, tiny, inexact, + overflow, stilltiny, denormround); + + // *** To check for tininess before rounding, use tiny + // To check after rounding, use stilltiny + // *** for underflow detect: + // To check for inexact result use (inexact | (shiftloss & stilltiny)), + // To check for denormilization loss use (shiftloss & stilltiny) +// flag flager(invalid, overflow, inexact | shiftloss, +// shiftloss | inexact, +// /* tiny */ (stilltiny | (tiny & denormround)), +// specialcase, flags); + + //ODIN cannot have operations in module instantiations. + wire inexact_or_shiftloss; + assign inexact_or_shiftloss = inexact | shiftloss; + wire shiftloss_or_inexact; + assign shiftloss_or_inexact = shiftloss | inexact; + wire still_tiny_or_tiny_and_denormround; + assign still_tiny_or_tiny_and_denormround = stilltiny | (tiny & denormround); + + flag flager(invalid, overflow, inexact_or_shiftloss, + shiftloss_or_inexact, + /* tiny */ stilltiny_or_tiny_and_denormround, + specialcase, flags); + + + assemble assembler(roundprod, special, y, + sign, specialsign, roundexp, + specialcase, specialsigncase, + roundmode, flags[`OVERFLOW]); + + always @ (posedge clk) begin + y_out <= y; + end + +endmodule + + + + +module preprocess(a, b, zero, aisnan, bisnan, aisdenorm, bisdenorm, infinity, control, roundmode, sign); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output zero; // is there a zero? + //input [`WCONTROL-1:0] control; // control field + input [1:0] control; //the rest is unused, not necessary for ODIN. + output [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + output aisnan; // NaN detected in A + output bisnan; // NaN detected in B + output aisdenorm; // denormalized number detected in A + output bisdenorm; // denormalized number detected in B + output infinity; // infinity detected in A + output sign; // sign of product + + // internal signals + wire signa, signb; // sign of a and b + wire [`WEXP-1:0] expa, expb; // the exponents of a and b + wire [`WSIG-1:0] siga, sigb; // the significands of a and b + wire aexpfull; // the exponent of a is all 1's + wire bexpfull; // the exponent of b is all 1's + wire aexpzero; // the exponent of a is all 0's + wire bexpzero; // the exponent of b is all 0's + wire asigzero; // the significand of a is all 0's + wire bsigzero; // the significand of b is all 0's + + // Sign calculation + assign signa = a[`WIDTH-1]; + assign signb = b[`WIDTH-1]; + assign sign = signa ^ signb; + + // Significand calcuations + + assign siga = a[`WSIG-1:0]; + assign sigb = b[`WSIG-1:0]; + // Are the significands all 0's? + assign asigzero = ~|siga; + assign bsigzero = ~|sigb; + + // Exponent calculations + + assign expa = a[`WIDTH-2:`WIDTH-`WEXP-1]; + assign expb = b[`WIDTH-2:`WIDTH-`WEXP-1]; + // Are the exponents all 0's? + assign aexpzero = ~|expa; + assign bexpzero = ~|expb; + // Are the exponents all 1's? + assign aexpfull = &expa; + assign bexpfull = &expb; + + // General calculations + + // Zero Detect + assign zero = (aexpzero & asigzero) | (bexpzero & bsigzero); + + // NaN detect + assign aisnan = aexpfull & ~asigzero; + assign bisnan = bexpfull & ~bsigzero; + + // Infinity detect + assign infinity = (aexpfull & asigzero) | (bexpfull & bsigzero); + + // Denorm detect + assign aisdenorm = aexpzero & ~asigzero; + assign bisdenorm = bexpzero & ~bsigzero; + + // Round mode extraction + assign roundmode = control[1:0]; + +endmodule + +module special (a, b, special, specialsign, + zero, aisnan, bisnan, infinity, + invalid, specialcase, specialsigncase); + + // external signals + input [`WIDTH-1:0] a, b; // floating-point inputs + output [`WIDTH-2:0] special; // special case output, exp + sig + output specialsign; // the special-case sign + input zero; // is there a zero? + input aisnan; // NaN detected in A + input bisnan; // NaN detected in B + input infinity; // infinity detected + output invalid; // invalid operation + output specialcase; // this is a special case + output specialsigncase; // Use the special sign + + // internal signals + wire infandzero; // infinity and zero detected + wire [`WIDTH-2:0] highernan; // holds inputed NaN, the higher if two are input, + // and dont care if neither a nor b are NaNs + wire aishighernan; // a is the higher NaN + + assign infandzero = (infinity & zero); + + //#######SPECIAL ASSIGNMENT###### + // #######return higher NaN########## + // Use this block if you want to return the higher of two NaNs + + assign aishighernan = (aisnan & ((a[`WSIG-1:0] >= b[`WSIG-1:0]) | ~bisnan)); + + assign highernan[`WIDTH-2:0] = aishighernan ? a[`WIDTH-2:0] : b[`WIDTH-2:0]; + + assign special[`WIDTH-2:0] = (aisnan | bisnan) ? (highernan[`WIDTH-2:0]) : + (zero ? + (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY)); + // #######return first NaN########## + // Use this block to return the first NaN encountered +// assign special = aisnan ? (a[`WIDTH-2:0]) : +// (bisnan ? (b[`WIDTH-2:0]) : +// (zero ? +// (infinity ? (`CONSTNAN) : (`CONSTZERO)) : (`CONSTINFINITY))); + //######END SPECIAL ASSIGNMENT####### + + assign specialcase = zero | aisnan | bisnan | infinity; + + assign invalid = infandzero; //*** need to include something about signaling NaNs here + + // dont need to check if b is NaN, if it defaults to that point, and b isnt NAN + // then it wont be used anyway + assign specialsign = infandzero ? (1'b1) : (aishighernan ? a[`WIDTH-1] : b[`WIDTH-1]); + + assign specialsigncase = infandzero | aisnan | bisnan; + +endmodule + +module prenorm(a, b, norma, normb, modexpa, modexpb, aisdenorm, bisdenorm); + + //input [`WIDTH-1:0] a, b; // the input floating point numbers + input [`WIDTH-2:0] a, b; //We don't need bit 31 here, unused in ODIN. + output [`WSIG:0] norma, normb; // the mantissae in normal form + output [`WEXPSUM-1:0] modexpa, modexpb; // the output exponents, larger to accomodate + // two's complement form + input aisdenorm; // a is a denormalized number + input bisdenorm; // b is a denormalized nubmer + + // internal signals + wire [`WEXPSUM-1:0] expa, expb; // exponents in two's complement form + // are negative if shifted for a + // denormalized number + wire [`SHIFT-1:0] shifta, shiftb; // the shift amounts + reg [`WSIG:0] shifteda, shiftedb; // the shifted significands, used to be wire, changed for ODIN. + + // pull out the exponents + assign expa = a[`WIDTH-2:`WIDTH-1-`WEXP]; + assign expb = b[`WIDTH-2:`WIDTH-1-`WEXP]; + + // when breaking appart for paramaterizing: + // ### RUN ./prenormshift.pl wsig_in ### +assign shifta = a[23 - 1] ? 1 : + a[23 - 2] ? 2 : + a[23 - 3] ? 3 : + a[23 - 4] ? 4 : + a[23 - 5] ? 5 : + a[23 - 6] ? 6 : + a[23 - 7] ? 7 : + a[23 - 8] ? 8 : + a[23 - 9] ? 9 : + a[23 - 10] ? 10 : + a[23 - 11] ? 11 : + a[23 - 12] ? 12 : + a[23 - 13] ? 13 : + a[23 - 14] ? 14 : + a[23 - 15] ? 15 : + a[23 - 16] ? 16 : + a[23 - 17] ? 17 : + a[23 - 18] ? 18 : + a[23 - 19] ? 19 : + a[23 - 20] ? 20 : + a[23 - 21] ? 21 : + a[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + +assign shiftb = b[23 - 1] ? 1 : + b[23 - 2] ? 2 : + b[23 - 3] ? 3 : + b[23 - 4] ? 4 : + b[23 - 5] ? 5 : + b[23 - 6] ? 6 : + b[23 - 7] ? 7 : + b[23 - 8] ? 8 : + b[23 - 9] ? 9 : + b[23 - 10] ? 10 : + b[23 - 11] ? 11 : + b[23 - 12] ? 12 : + b[23 - 13] ? 13 : + b[23 - 14] ? 14 : + b[23 - 15] ? 15 : + b[23 - 16] ? 16 : + b[23 - 17] ? 17 : + b[23 - 18] ? 18 : + b[23 - 19] ? 19 : + b[23 - 20] ? 20 : + b[23 - 21] ? 21 : + b[23 - 22] ? 22 : + 23; // dont need to check last bit +// if the second to last isn't 1, then the last one must be + + + + // If number is a denorm, the exponent must be + // decremented by the shift amount + assign modexpa = aisdenorm ? 1 - shifta : expa; + assign modexpb = bisdenorm ? 1 - shiftb : expb; + + // If number is denorm, shift the significand the appropriate amount +// assign shifteda = a[`WSIG-1:0] << shifta; + //Must have constant shifts for ODIN + always @ (shifta or a) begin + case (shifta) + 5'b00001: begin + shifteda = a[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shifteda = a[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shifteda = a[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shifteda = a[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shifteda = a[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shifteda = a[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shifteda = a[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shifteda = a[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shifteda = a[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shifteda = a[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shifteda = a[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shifteda = a[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shifteda = a[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shifteda = a[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shifteda = a[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shifteda = a[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shifteda = a[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shifteda = a[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shifteda = a[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shifteda = a[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shifteda = a[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shifteda = a[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shifteda = a[`WSIG-1:0] << 5'b10111; + end + + default: begin //Won't be higher than 23. + shifteda = a[`WSIG-1:0]; + end + endcase + end + + assign norma = aisdenorm ? shifteda : {1'b1, a[`WSIG-1:0]}; + + // assign shiftedb = b[`WSIG-1:0] << shiftb; + always @ (shiftb or b) begin + case (shiftb) + 5'b00001: begin + shiftedb = b[`WSIG-1:0] << 5'b00001; + end + + 5'b00010: begin + shiftedb = b[`WSIG-1:0] << 5'b00010; + end + + 5'b00011: begin + shiftedb = b[`WSIG-1:0] << 5'b00011; + end + + 5'b00100: begin + shiftedb = b[`WSIG-1:0] << 5'b00100; + end + + 5'b00101: begin + shiftedb = b[`WSIG-1:0] << 5'b00101; + end + + 5'b00110: begin + shiftedb = b[`WSIG-1:0] << 5'b00110; + end + + 5'b00111: begin + shiftedb = b[`WSIG-1:0] << 5'b00111; + end + + 5'b01000: begin + shiftedb = b[`WSIG-1:0] << 5'b01000; + end + + 5'b01001: begin + shiftedb = b[`WSIG-1:0] << 5'b01001; + end + + 5'b01010: begin + shiftedb = b[`WSIG-1:0] << 5'b01010; + end + + 5'b01011: begin + shiftedb = b[`WSIG-1:0] << 5'b01011; + end + + 5'b01100: begin + shiftedb = b[`WSIG-1:0] << 5'b01100; + end + + 5'b01101: begin + shiftedb = b[`WSIG-1:0] << 5'b01101; + end + + 5'b01110: begin + shiftedb = b[`WSIG-1:0] << 5'b01110; + end + + 5'b01111: begin + shiftedb = b[`WSIG-1:0] << 5'b01111; + end + + 5'b10000: begin + shiftedb = b[`WSIG-1:0] << 5'b10000; + end + + 5'b10001: begin + shiftedb = b[`WSIG-1:0] << 5'b10001; + end + + 5'b10010: begin + shiftedb = b[`WSIG-1:0] << 5'b10010; + end + + 5'b10011: begin + shiftedb = b[`WSIG-1:0] << 5'b10011; + end + + 5'b10100: begin + shiftedb = b[`WSIG-1:0] << 5'b10100; + end + + 5'b10101: begin + shiftedb = b[`WSIG-1:0] << 5'b10101; + end + + 5'b10110: begin + shiftedb = b[`WSIG-1:0] << 5'b10110; + end + + 5'b10111: begin + shiftedb = b[`WSIG-1:0] << 5'b10111; + end + + default: begin // Won't be higher than 23. + shiftedb = b[`WSIG-1:0]; + end + endcase + end + + + assign normb = bisdenorm ? shiftedb : {1'b1, b[`WSIG-1:0]}; + +endmodule + +module multiply_a (norma, normb, prod, twoormore); + + input [`WSIG:0] norma, normb; // normalized mantissae + + output [`PRODWIDTH-1:0] prod; // product of mantissae + output twoormore; // Product overflowed range [1,2) + + // multiplier array + // (*** need a more effecient multiplier, + // designware might work, though) + assign prod = norma * normb; + + // did the multiply overflow the range [1,2)? + assign twoormore = prod[`PRODWIDTH-1]; + +endmodule + + + +module exponent(expa, expb, expsum, twoormore, tiny); + + input [`WEXPSUM-1:0] expa, expb; // the input exponents in 2's complement form + // to accomodate denorms that have been + // prenormalized + input twoormore; // product is outside range [1,2) + + output [`WEXPSUM-1:0] expsum; // the sum of the exponents + output tiny; // Result is tiny (denormalized #) + + // Sum the exponents, subtract the bias + // and add 1 (twoormore) if multiply went out of [1,2) range + assign expsum = expa + expb - `BIAS + twoormore; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is in 2's-complement form, + // it is negative if the first bit is 1, and zero if + // all the bits are zero + assign tiny = ~|expsum[`WEXPSUM-2:0] | expsum[`WEXPSUM-1]; + + +endmodule + + + + +module normalize(prod, normalized, tiny, twoormore); + + // external signals + input [`PRODWIDTH-1:0] prod; // Product of multiplication + output [`PRODWIDTH-1:0] normalized; // Normalized product + input tiny; // Result is tiny (denormalized #) + input twoormore; // Product overflowed range [1,2) + + // normalize product if appropriate + // There are three possible cases here: + // 1) tiny and prod overfl. [1,2) -> take the whole prod, including the leading 1 + // 2) tiny or prod overfl. [1,2) -> dont take the first bit. its zero if its tiny, + // and it's the implied 1 if its not + // 3) neither tiny nor prod overfl.-> dont take the first 2 bits, the 2nd one is the + // implied 1 + assign normalized = (tiny & twoormore) ? prod[`PRODWIDTH-1:0] : + ((tiny ^ twoormore) ? {prod[`PRODWIDTH-2:0],1'b0} : + {prod[`PRODWIDTH-3:0],2'b0}); + +endmodule + +module shift(normalized, selectedexp, shiftprod, shiftexp, shiftloss); + + // external signals + input [`PRODWIDTH-1:0] normalized; // normalized product of mantissae + input [`WEXPSUM-1:0] selectedexp; // sum of exponents + output [`SHIFTWIDTH-1:0] shiftprod; // shifted and normalized product + output [`WEXPSUM-1:0] shiftexp; // shifted exponent + output shiftloss; // loss of accuaracy due to shifting + + // internal signals + wire [`WEXPSUM-1:0] roundedexp; // selected exponent + 1 if rounding caused overflow +// wire negexp; // exponent is negative + wire [`WEXPSUM-1:0] shiftamt; // theoretical amount to shift product by + wire [`WSHIFTAMT-1:0] actualshiftamt; // actual amount to shift product by + wire tozero; // need more shifts than possible with width of significand + wire doshift; // only shift if value is nonnegative + wire [`SHIFTWIDTH-1:0] preshift; // value before shifting, with more room to ensure lossless shifting + reg [`SHIFTWIDTH-1:0] postshift; // value after shifting, with more room to ensure lossless shifting, used to be wire, changed for ODIN. + + // set up value for shifting + assign preshift = {normalized, `PRESHIFTZEROS}; + + // determine shift amount + assign shiftamt = -selectedexp; + + // make sure shift amount is nonnegative + // If the exponent is negative, the shift amount should + // come out positive, otherwise there shouldn't be any + // shifting to be done + assign doshift = ~shiftamt[`WEXPSUM-1]; + + // Determine if the result must be shifted more than + // will show up in the significand, even if it rounds up + assign tozero = doshift & (shiftamt > `MAXSHIFT); + + // If the shift is big enough to shift all the bits out of the final significand, + // then it stops being relevent how much it has been shifted. + assign actualshiftamt = tozero ? `MAXSHIFT : shiftamt[`WSHIFTAMT-1:0]; + + // shift significand + //assign postshift = preshift >> actualshiftamt; + //We can only have constant shifts for ODIN: + always @ (actualshiftamt or preshift) begin + case (actualshiftamt) + 5'b00001: begin + postshift = preshift >> 5'b00001; + end + + 5'b00010: begin + postshift = preshift >> 5'b00010; + end + + 5'b00011: begin + postshift = preshift >> 5'b00011; + end + + 5'b00100: begin + postshift = preshift >> 5'b00100; + end + + 5'b00101: begin + postshift = preshift >> 5'b00101; + end + + 5'b00110: begin + postshift = preshift >> 5'b00110; + end + + 5'b00111: begin + postshift = preshift >> 5'b00111; + end + + 5'b01000: begin + postshift = preshift >> 5'b01000; + end + + 5'b01001: begin + postshift = preshift >> 5'b01001; + end + + 5'b01010: begin + postshift = preshift >> 5'b01010; + end + + 5'b01011: begin + postshift = preshift >> 5'b01011; + end + + 5'b01100: begin + postshift = preshift >> 5'b01100; + end + + 5'b01101: begin + postshift = preshift >> 5'b01101; + end + + 5'b01110: begin + postshift = preshift >> 5'b01110; + end + + 5'b01111: begin + postshift = preshift >> 5'b01111; + end + + 5'b10000: begin + postshift = preshift >> 5'b10000; + end + + 5'b10001: begin + postshift = preshift >> 5'b10001; + end + + 5'b10010: begin + postshift = preshift >> 5'b10010; + end + + 5'b10011: begin + postshift = preshift >> 5'b10011; + end + + 5'b10100: begin + postshift = preshift >> 5'b10100; + end + + 5'b10101: begin + postshift = preshift >> 5'b10101; + end + + 5'b10110: begin + postshift = preshift >> 5'b10110; + end + + 5'b10111: begin + postshift = preshift >> 5'b10111; + end + + 5'b11000: begin + postshift = preshift >> 5'b11000; + end + + 5'b11001: begin + postshift = preshift >> 5'b11001; + end + + 5'b11010: begin + postshift = preshift >> 5'b11010; + end + + 5'b11011: begin + postshift = preshift >> 5'b11011; + end + + 5'b11100: begin + postshift = preshift >> 5'b11100; + end + + 5'b11101: begin + postshift = preshift >> 5'b11101; + end + + 5'b11110: begin + postshift = preshift >> 5'b11110; + end + + 5'b11111: begin + postshift = preshift >> 5'b11111; + end + + default: begin + postshift = preshift; + end + endcase + end + + + // assign appropriate significand + assign shiftprod = doshift ? postshift : preshift; + + // determine if any bits were lost from the shift + //assign shiftloss = tozero | (negexp & |postshift[`WSIG-1:0]); + assign shiftloss = tozero | (doshift & |postshift[`SHIFTWIDTH-`PRODWIDTH-1:0]); + + // assign appropriate exponent + assign shiftexp = doshift ? 0 : selectedexp; + +endmodule + + + +module round(shiftprod, shiftexp, shiftloss, roundprod, roundexp, roundmode, + sign, tiny, inexact, overflow, stilltiny, denormround); + + // external signals + input [`SHIFTWIDTH-1:0] shiftprod; // normalized and shifted product of mantissae + input [`WEXPSUM-1:0] shiftexp; // shifted exponent + input shiftloss; // bits were lost in the shifting process + output [`WSIG-1:0] roundprod; // rounded floating-point product + output [`WEXP-1:0] roundexp; // rounded exponent + input [1:0] roundmode; // 00 = RN; 01 = RZ; 10 = RP; 11 = RM + input sign; // sign bit for rounding mode direction + input tiny; // denormalized number after rounding + output inexact; // rounding occured + output overflow; // overflow occured + output stilltiny; // Result is tiny (denormalized #) after rounding + output denormround; // result was rounded only because it was a denormalized number + + // internal signals + wire roundzero; // rounding towards zero + wire roundinf; // rounding towards infinity + wire stickybit; // there one or more 1 bits in the LS bits + wire denormsticky; // sticky bit if this weren't a denorm + wire [`WSIG-1:0] MSBits; // most significant bits + wire [`WSIG:0] MSBitsplus1; // most significant bits plus 1 + // for rounding purposes. needs to be one + // bit bigger for overflow + wire [1:0] roundbits; // bits used to compute rounding decision + wire rounddecision; // round up + wire roundoverflow; // rounding overflow occured + wire [`WEXPSUM-1:0] tempexp; // exponent after rounding + + //reduce round mode to three modes + // dont need round nearest, it is implied + // by roundzero and roundinf being false + //assign roundnearest = ~&roundmode; +// assign roundzero = &roundmode || (^roundmode && (roundmode[0] || sign)); + assign roundzero = (~roundmode[1] & roundmode[0]) | (roundmode[1] & (roundmode[0] ^ sign)); + assign roundinf = roundmode[1] & ~(sign ^ roundmode[0]); + + // pull out the most significant bits for the product + assign MSBits = shiftprod[`SHIFTWIDTH-1:`SHIFTWIDTH-`WSIG]; + + // add a 1 to the end of MSBits for round up + assign MSBitsplus1 = MSBits + 1; + + // pull out the last of the most significant bits + // and the first of the least significant bits + // to use for calculating the rounding decision + assign roundbits[1:0] = shiftprod[`SHIFTWIDTH-`WSIG:`SHIFTWIDTH-`WSIG-1]; + + // calculate the sticky bit. Are any of the least significant bits 1? + // also: was anything lost while shifting? + // *** Optimization: some of these bits are already checked from the shiftloss *** + // *** Optimization: stickybit can be calculated from denormsticky + // with only 1 more gate, instead of duplication of effort *** + assign stickybit = |shiftprod[`SHIFTWIDTH-`WSIG-2:0] | shiftloss; + assign denormsticky = |shiftprod[`SHIFTWIDTH-`WSIG-3:0] | shiftloss; + + // Compute rounding decision + assign rounddecision = ~roundzero & ( (roundbits[0] & (roundinf | roundbits[1])) + | (stickybit & (roundinf | roundbits[0])) + ); + + // Was this only rounded because it is a denorm? + assign denormround = tiny & rounddecision & ~denormsticky & roundbits[0]; + + // detect rounding overflow. it only overflows if: + // 1) the top bit of MSBitsplus1 is 1 + // 2) it decides to round up + assign roundoverflow = MSBitsplus1[`WSIG] & rounddecision; + + // assign significand (and postnormalize) + // rounddecision decides whether to use msbits+1 or msbits. + // if using msbits+1 and there is an rounding overflow (i.e. result=2), + // then should return 1 instead + assign roundprod = rounddecision ? + (roundoverflow ? 0 : + MSBitsplus1[`WSIG-1:0]) : + MSBits; + + // detect inexact + assign inexact = rounddecision | stickybit | roundbits[0]; + + // compensate for a rounding overflow + assign tempexp = roundoverflow + shiftexp; + + // check for overflow in exponent + // overflow occured if the number + // is too large to be represented, + // i.e. can't fit in `WEXP bits, or + // all `WEXP bits are 1's + assign overflow = &tempexp[`WEXP-1:0] | |tempexp[`WEXPSUM-1:`WEXP]; + + // two possible cases: + // 1) Overflow: then exponent doesnt matter, + // it will be changed to infinity anyway + // 2) not overflow: the leading bits will be 0 + assign roundexp = tempexp[`WEXP-1:0]; + + // The result is tiny if the exponent is less than 1. + // Because the exponent sum is NOT in 2's-complement form, + // it is only less than one if its is zero, i.e. + // all the bits are 0 + assign stilltiny = ~|roundexp; + +endmodule + + +module flag (invalid, overflow, inexact, underflow, tiny, specialcase, flags); + + input invalid; // invalid operation + input overflow; // the result was too large + input inexact; // The result was rounded + input specialcase; // Using special result, shouldn't throw flags + input underflow; // Underflow detected + input tiny; // The result is tiny + + output [`WFLAG-1:0] flags; // DIVZERO, INVALID, INEXACT, + // OVERFLOW, UNDERFLOW (defined in constant.v) + + // flags + assign flags[`DIVZERO] = 1'b0; + assign flags[`INVALID] = invalid; + assign flags[`INEXACT] = ~specialcase & (inexact | underflow | overflow); + assign flags[`OVERFLOW] = ~specialcase & overflow; + assign flags[`UNDERFLOW] = tiny; //~specialcase & tiny & underflow & ~overflow; + +endmodule + +module assemble(roundprod, special, y, sign, specialsign, + shiftexp, specialcase, specialsigncase, + roundmode, overflow); + + // external signals + input [`WSIG-1:0] roundprod; // shifted, rounded and normalized + // product of mantissae + input [`WIDTH-2:0] special; // special case product + exponent + output [`WIDTH-1:0] y; // floating-point product + input sign; // sign of product (+ = 0, - = 1) + input specialsign; // special case sign + input [`WEXP-1:0] shiftexp; // shifted exponent + input specialcase; // this is a special case + input specialsigncase; // use the special case sign + input [1:0] roundmode; // rounding mode information extracted from control field + input overflow; // overflow detected + + // internal signals + wire [`WIDTH-2:0] rounded; // final product + exponent + wire [`WIDTH-2:0] overflowvalue; // product + exponent for overflow condition + wire undenormed; // the result was denormalized before rounding, but rounding + // caused it to become a small normalized number. + + // SET UP ROUNDED PRODUCT + EXPONENT + + // assign significand + assign rounded[`WSIG-1:0] = roundprod; + + // assign exponent + assign rounded[`WIDTH-2:`WIDTH-`WEXP-1] = shiftexp; + + // SET UP OVERFLOW CONDITION + assign overflowvalue[`WIDTH-2:0] = roundmode[1] ? + (sign ^ roundmode[0] ? `CONSTLARGEST : `CONSTINFINITY) : + (roundmode[0] ? `CONSTLARGEST: `CONSTINFINITY); + + // FINAL PRODUCT ASSIGN + + // assign sign + assign y[`WIDTH-1] = specialsigncase ? specialsign : sign; + + // assign product vs special vs overflowed + assign y[`WIDTH-2:0] = specialcase ? special[`WIDTH-2:0] : + (overflow ? overflowvalue[`WIDTH-2:0] : + rounded[`WIDTH-2:0]); + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v b/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v new file mode 100644 index 000000000..c290fc893 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v @@ -0,0 +1,8210 @@ + + +module single_port_ram_21_8( + clk, + data, + we, + addr, + out + ); +`define ADDR_WIDTH_21_8 8 +`define DATA_WIDTH_21_8 21 + + input clk; + input [`DATA_WIDTH_21_8-1:0] data; + input we; + input [`ADDR_WIDTH_21_8-1:0] addr; + + + output [`DATA_WIDTH_21_8-1:0] out; + reg [`DATA_WIDTH_21_8-1:0] out; + + reg [`DATA_WIDTH_21_8-1:0] RAM[255:0]; + + always @ (posedge clk) + begin + if (we) + begin + RAM[addr] <= data; + out <= RAM[addr]; + end + end + +endmodule + + + +module single_port_ram_128_8( + clk, + data, + we, + addr, + out + ); +`define ADDR_WIDTH_128_8 8 +`define DATA_WIDTH_128_8 128 + + input clk; + input [`DATA_WIDTH_128_8-1:0] data; + input we; + input [`ADDR_WIDTH_128_8-1:0] addr; + + + output [`DATA_WIDTH_128_8-1:0] out; + reg [`DATA_WIDTH_128_8-1:0] out; + + reg [`DATA_WIDTH_128_8-1:0] RAM[255:0]; + + always @ (posedge clk) + begin + if (we) + begin + RAM[addr] <= data; + out <= RAM[addr]; + end + end + +endmodule + + + +module a25_icache + + + ( + i_clk, + i_core_stall, + o_stall, + + i_select, + i_address, + i_address_nxt, + i_cache_enable, + i_cache_flush, + o_read_data, + + o_wb_req, + i_wb_read_data, + i_wb_ready + ); + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + +`ifndef _A25_CONFIG_DEFINES +`define _A25_CONFIG_DEFINES + + + +`define A25_ICACHE_WAYS 4 +`define A25_DCACHE_WAYS 4 + +`endif + +parameter CACHE_LINES = 256; + +// This cannot be changed without some major surgeory on +// this module +parameter CACHE_WORDS_PER_LINE = 4; + + +parameter WAYS = `A25_ICACHE_WAYS; + + +parameter CACHE_ADDR_WIDTH = 8; // = 8 +parameter WORD_SEL_WIDTH = 2; // = 2 +parameter TAG_ADDR_WIDTH = 20; // = 20 +parameter TAG_WIDTH = 21; // = 21, including Valid flag +parameter CACHE_LINE_WIDTH = 128; // = 128 +parameter TAG_ADDR32_LSB = 12; // = 12 +parameter CACHE_ADDR32_MSB = 11; // = 11 +parameter CACHE_ADDR32_LSB = 4; // = 4 +parameter WORD_SEL_MSB = 3; // = 3 +parameter WORD_SEL_LSB = 2; // = 2 +// --------------------------------------------------------- + + +input i_clk; +input i_core_stall; +output o_stall; + +// Read / Write requests from core +input i_select; +input [31:0] i_address; // registered address from execute +input [31:0] i_address_nxt; // un-registered version of address from execute stage +input i_cache_enable; // from co-processor 15 configuration register +input i_cache_flush; // from co-processor 15 register + +output [127:0] o_read_data; + +// WB Read Request +output o_wb_req; // Read Request +input [127:0] i_wb_read_data; +input i_wb_ready; + + +// One-hot encoded +localparam C_INIT = 0, + C_CORE = 1, + C_FILL = 2, + C_INVA = 3, + C_STATES = 4; + +localparam [3:0] CS_INIT = 4'd0, + CS_IDLE = 4'd1, + CS_FILL0 = 4'd2, + CS_FILL1 = 4'd3, + CS_FILL2 = 4'd4, + CS_FILL3 = 4'd5, + CS_FILL4 = 4'd6, + CS_FILL_COMPLETE = 4'd7, + CS_TURN_AROUND = 4'd8, + CS_WRITE_HIT1 = 4'd9, + CS_EX_DELETE = 4'd10; + +//reg o_wb_req; //jing+ +//reg o_stall; //jing+ +//reg [127:0] o_read_data; //jing+ + +reg [3:0] c_state = 4'd1 ; // c_state = CS_IDLE +reg [C_STATES-1:0] source_sel = 4'b10; //1'd1 << C_CORE +reg [CACHE_ADDR_WIDTH:0] init_count = 9'd0; + +wire [TAG_WIDTH-1:0] tag_rdata_way0; +wire [TAG_WIDTH-1:0] tag_rdata_way1; +wire [TAG_WIDTH-1:0] tag_rdata_way2; +wire [TAG_WIDTH-1:0] tag_rdata_way3; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way0; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way1; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way2; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way3; +wire [WAYS-1:0] data_wenable_way; +wire [WAYS-1:0] data_hit_way; +wire [WAYS-1:0] tag_wenable_way; +reg [WAYS-1:0] select_way = 4'd0; +wire [WAYS-1:0] next_way; +reg [WAYS-1:0] valid_bits_r = 4'd0; + +reg [3:0] random_num = 4'hf; + +wire [CACHE_ADDR_WIDTH-1:0] tag_address; +wire [TAG_WIDTH-1:0] tag_wdata; +wire tag_wenable; + +wire [CACHE_ADDR_WIDTH-1:0] data_address; +wire [31:0] write_data_word; + +wire idle_hit; +reg read_miss; //jing +wire read_miss_fill; +wire invalid_read; +wire fill_state; + +reg [31:0] miss_address = 32'd0; +wire [CACHE_LINE_WIDTH-1:0] hit_rdata; + +wire cache_busy_stall; +wire read_stall; + +wire enable; +wire [CACHE_ADDR_WIDTH-1:0] address; +wire [31:0] address_c; +reg [31:0] address_r = 32'd0; + +reg [31:0] wb_address = 32'd0; +wire wb_hit; //jing - add wire -> reg +wire read_buf_hit; //jing - add wire -> reg +reg [127:0] read_buf_data_r; +reg [31:0] read_buf_addr_r; +reg read_buf_valid_r; +//genvar i; + +// ====================================== +// Address to use for cache access +// ====================================== +// If currently stalled then the address for the next +// cycle will be the same as it is in the current cycle +// +assign address_c = i_core_stall ? i_address : + i_address_nxt; + +assign address = address_c[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB]; + + +// ====================================== +// Outputs +// ====================================== +assign o_read_data = wb_hit ? i_wb_read_data : + read_buf_hit ? read_buf_data_r : + hit_rdata ; + + +// Don't allow the cache to stall the wb i/f for an exclusive access +// The cache needs a couple of cycles to flush a potential copy of the exclusive +// address, but the wb can do the access in parallel. So there is no +// stall in the state CS_EX_DELETE, even though the cache is out of action. +// This works fine as long as the wb is stalling the core +//assign o_stall = read_stall || cache_busy_stall; +always @ ( posedge i_clk ) + o_stall <= read_stall || cache_busy_stall; + +assign o_wb_req = read_miss && c_state == CS_IDLE; + + +// ====================================== +// Read Buffer +// ====================================== +always@(posedge i_clk) + if ( i_cache_flush ) + read_buf_valid_r <= 1'd0; + else if (i_wb_ready && c_state == CS_FILL3) + begin + read_buf_data_r <= i_wb_read_data; + read_buf_addr_r <= miss_address; + read_buf_valid_r <= 1'd1; + end + else if (o_wb_req) + read_buf_valid_r <= 1'd0; + + +assign read_buf_hit = read_buf_valid_r && i_address[31:4] == read_buf_addr_r[31:4]; + +// ====================================== +// Cache State Machine +// ====================================== + +// Little State Machine to Flush Tag RAMS +always @ ( posedge i_clk ) + if ( i_cache_flush ) + begin + c_state <= CS_INIT; + source_sel <= 4'd1; //1'd1 << C_INIT + init_count <= 9'd0; + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display("Cache Flush"); + `endif + end + else + case ( c_state ) + CS_INIT : + if ( init_count < CACHE_LINES ) + begin + init_count <= init_count + 1'd1; + source_sel <= 4'b1; //1'd1 << C_INIT + end + else + begin + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + CS_IDLE : + begin + source_sel <= 4'b10; //1'd1 << C_CORE + + if ( read_miss ) + c_state <= CS_FILL3; + end + + + CS_FILL3 : + begin + // Pick a way to write the cache update into + // Either pick one of the invalid caches, or if all are valid, then pick + // one randomly + select_way <= next_way; + random_num <= {random_num[2], random_num[1], random_num[0], + random_num[3]^random_num[2]}; + + // third read of burst of 4 + // wb read request asserted, wait for ack + if ( i_wb_ready ) + begin + c_state <= CS_FILL_COMPLETE; + end + end + + + // Write the read fetch data in this cycle + CS_FILL_COMPLETE : + begin + // Back to normal cache operations, but + // use physical address for first read as + // address moved before the stall was asserted for the read_miss + // However don't use it if its a non-cached address! + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + + // Ignore the tag read data in this cycle + // Wait 1 cycle to pre-read the cache and return to normal operation + CS_TURN_AROUND : + begin + c_state <= CS_IDLE; + end + + endcase + + +// ====================================== +// Miss Address +// ====================================== +always @ ( posedge i_clk ) + if ( c_state == CS_IDLE ) + miss_address <= i_address; + + +always @ ( posedge i_clk ) + address_r <= address_c; + +assign invalid_read = address_r != i_address; + + +always @(posedge i_clk) + if ( o_wb_req ) + wb_address <= i_address; + else if ( i_wb_ready && fill_state ) + wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0}; + +assign fill_state = c_state == CS_FILL3; +assign wb_hit = i_address == wb_address && i_wb_ready && fill_state; + +assign tag_address = read_miss_fill ? miss_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0] : + address ; + + +assign data_address = read_miss_fill ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + address ; + + +assign tag_wdata = read_miss_fill ? {1'd1, miss_address[31:12]} : // [31:TAG_ADDR32_LSB] + 21'd0 ; // {TAG_WIDTH{1'd0}} TAG_WIDTH =21 + + +assign read_miss_fill = c_state == CS_FILL3 && i_wb_ready; + + + +assign tag_wenable = read_miss_fill ? 1'd1 : + source_sel[C_INVA] ? 1'd1 : + source_sel[C_FILL] ? 1'd1 : + source_sel[C_INIT] ? 1'd1 : + source_sel[C_CORE] ? 1'd0 : + 1'd0 ; + + +assign enable = i_select && i_cache_enable; + +assign idle_hit = |data_hit_way; + +assign read_miss = enable && !idle_hit && !invalid_read; + +assign read_stall = (i_select && i_cache_enable) && !(|data_hit_way) && !wb_hit && !read_buf_hit; +//assign read_stall = enable && !idle_hit && !wb_hit && !read_buf_hit; + +assign cache_busy_stall = (c_state == CS_TURN_AROUND && enable && !read_buf_hit) || c_state == CS_INIT; + + +// ====================================== +// Instantiate RAMS +// ====================================== + +//generate +// for ( i=0; i reg +reg cache_stall; //jing- add wire -> reg +//reg o_fetch_stall; //jing+ +wire [127:0] cache_read_data128; +wire [31:0] cache_read_data; +wire sel_cache; +wire uncached_instruction_read; +wire address_cachable; +wire icache_wb_req; +wire wait_wb; +reg wb_req_r = 1'd0; +wire [31:0] wb_rdata32; + + + +// e.g. 24 for 32MBytes, 26 for 128MBytes +localparam MAIN_MSB = 26; + +// e.g. 13 for 4k words +localparam BOOT_MSB = 13; + +localparam MAIN_BASE = 32'h00000000; /* Main Memory */ +localparam BOOT_BASE = 32'h00000000; /* Cachable Boot Memory */ +localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */ +localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */ +localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */ +localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */ +localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */ +localparam HIBOOT_BASE = 32'h28000000; /* Uncachable Boot Memory */ +localparam TEST_BASE = 16'hf000; /* Test Module */ + + +assign address_cachable = ( + ( i_iaddress >= 32'h00000000 && i_iaddress < 32'h7fff) + || ( + (i_iaddress >= MAIN_BASE && i_iaddress < (MAIN_BASE + 32'hfffffff)) + && !( (i_iaddress >= BOOT_BASE && i_iaddress < (BOOT_BASE + 32'h7fff)) + ||(i_iaddress[31:14] == HIBOOT_BASE>>(14))) + ) + ) + && ((i_iaddress[25:21] == 5'b00000) ? i_cacheable_area[0] : + (i_iaddress[25:21] == 5'b00001) ? i_cacheable_area[1] : + (i_iaddress[25:21] == 5'b00010) ? i_cacheable_area[2] : + (i_iaddress[25:21] == 5'b00011) ? i_cacheable_area[3] : + (i_iaddress[25:21] == 5'b00100) ? i_cacheable_area[4] : + (i_iaddress[25:21] == 5'b00101) ? i_cacheable_area[5] : + (i_iaddress[25:21] == 5'b00110) ? i_cacheable_area[6] : + (i_iaddress[25:21] == 5'b00111) ? i_cacheable_area[7] : + (i_iaddress[25:21] == 5'b01000) ? i_cacheable_area[8] : + (i_iaddress[25:21] == 5'b01001) ? i_cacheable_area[9] : + (i_iaddress[25:21] == 5'b01010) ? i_cacheable_area[10] : + (i_iaddress[25:21] == 5'b01011) ? i_cacheable_area[11] : + (i_iaddress[25:21] == 5'b01100) ? i_cacheable_area[12] : + (i_iaddress[25:21] == 5'b01101) ? i_cacheable_area[13] : + (i_iaddress[25:21] == 5'b01110) ? i_cacheable_area[14] : + (i_iaddress[25:21] == 5'b01111) ? i_cacheable_area[15] : + (i_iaddress[25:21] == 5'b10000) ? i_cacheable_area[16] : + (i_iaddress[25:21] == 5'b10001) ? i_cacheable_area[17] : + (i_iaddress[25:21] == 5'b10010) ? i_cacheable_area[18] : + (i_iaddress[25:21] == 5'b10011) ? i_cacheable_area[19] : + (i_iaddress[25:21] == 5'b10100) ? i_cacheable_area[20] : + (i_iaddress[25:21] == 5'b10101) ? i_cacheable_area[21] : + (i_iaddress[25:21] == 5'b10110) ? i_cacheable_area[22] : + (i_iaddress[25:21] == 5'b10111) ? i_cacheable_area[23] : + (i_iaddress[25:21] == 5'b11000) ? i_cacheable_area[24] : + (i_iaddress[25:21] == 5'b11001) ? i_cacheable_area[25] : + (i_iaddress[25:21] == 5'b11010) ? i_cacheable_area[26] : + (i_iaddress[25:21] == 5'b11011) ? i_cacheable_area[27] : + (i_iaddress[25:21] == 5'b11100) ? i_cacheable_area[28] : + (i_iaddress[25:21] == 5'b11101) ? i_cacheable_area[29] : + (i_iaddress[25:21] == 5'b11110) ? i_cacheable_area[30] : + i_cacheable_area[31] ); + +//i_cacheable_area[i_iaddress[25:21]]; + +assign sel_cache = address_cachable && i_iaddress_valid && i_cache_enable; + +// Don't start wishbone transfers when the cache is stalling the core +// The cache stalls the core during its initialization sequence +assign uncached_instruction_read = !sel_cache && i_iaddress_valid && !cache_stall; + +// Return read data either from the wishbone bus or the cache +assign cache_read_data = i_iaddress[3:2] == 2'd0 ? cache_read_data128[ 31: 0] : + i_iaddress[3:2] == 2'd1 ? cache_read_data128[ 63:32] : + i_iaddress[3:2] == 2'd2 ? cache_read_data128[ 95:64] : + cache_read_data128[127:96] ; + +assign wb_rdata32 = i_iaddress[3:2] == 2'd0 ? i_wb_read_data[ 31: 0] : + i_iaddress[3:2] == 2'd1 ? i_wb_read_data[ 63:32] : + i_iaddress[3:2] == 2'd2 ? i_wb_read_data[ 95:64] : + i_wb_read_data[127:96] ; + +assign o_fetch_instruction = sel_cache ? cache_read_data : + uncached_instruction_read ? wb_rdata32 : + 32'hffeeddcc ; + +// Stall the instruction decode and execute stages of the core +// when the fetch stage needs more than 1 cycle to return the requested +// read data + +assign o_fetch_stall = !i_system_rdy || wait_wb || cache_stall; + +assign o_wb_address = i_iaddress; +assign o_wb_req = icache_wb_req || uncached_instruction_read; + +assign wait_wb = (o_wb_req || wb_req_r) && !i_wb_ready; + +always @(posedge i_clk) + wb_req_r <= o_wb_req && !i_wb_ready; + +assign core_stall = o_fetch_stall || i_mem_stall || i_exec_stall || i_conflict; + +// ====================================== +// L1 Instruction Cache +// ====================================== +a25_icache u_cache ( + .i_clk ( i_clk ), + .i_core_stall ( core_stall ), + .o_stall ( cache_stall ), + + .i_select ( sel_cache ), + .i_address ( i_iaddress ), + .i_address_nxt ( i_iaddress_nxt ), + .i_cache_enable ( i_cache_enable ), + .i_cache_flush ( i_cache_flush ), + .o_read_data ( cache_read_data128 ), + + .o_wb_req ( icache_wb_req ), + .i_wb_read_data ( i_wb_read_data ), + .i_wb_ready ( i_wb_ready ) +); + + +endmodule + + + + +module a25_decode( + i_clk, + i_fetch_instruction, + i_core_stall, + i_irq, + i_firq, + i_dabt, + i_iabt, + i_adex, + i_execute_iaddress, + // i_execute_daddress, + i_abt_status, + i_execute_status_bits, + i_multiply_done, + + + o_imm32, + o_imm_shift_amount, + o_shift_imm_zero, + o_condition, + o_decode_exclusive, + o_decode_iaccess, + o_decode_daccess, + o_status_bits_mode, + o_status_bits_irq_mask, + o_status_bits_firq_mask, + + o_rm_sel, + o_rs_sel, + o_load_rd, + + o_rn_sel, + o_barrel_shift_amount_sel, + o_barrel_shift_data_sel, + o_barrel_shift_function, + o_alu_function, + o_multiply_function, + o_interrupt_vector_sel, + o_iaddress_sel, + o_daddress_sel, + o_pc_sel, + o_byte_enable_sel, + o_status_bits_sel, + o_reg_write_sel, + o_user_mode_regs_store_nxt, + o_firq_not_user_mode, + + o_write_data_wen, + o_base_address_wen, + + o_pc_wen, + o_reg_bank_wen, + o_status_bits_flags_wen, + o_status_bits_mode_wen, + o_status_bits_irq_mask_wen, + o_status_bits_firq_mask_wen, + + o_copro_opcode1, + o_copro_opcode2, + o_copro_crn, + o_copro_crm, + o_copro_num, + o_copro_operation, + + o_copro_write_data_wen, + o_iabt_trigger, + o_iabt_address, + o_iabt_status, + o_dabt_trigger, + o_dabt_address, + o_dabt_status, + o_conflict, + o_rn_use_read, + o_rm_use_read, + o_rs_use_read, + o_rd_use_read +); + +/************************* IO Declarations *********************/ +input i_clk; +input [31:0] i_fetch_instruction; +input i_core_stall; // stall all stages of the Amber core at the same time +input i_irq; // interrupt request +input i_firq; // Fast interrupt request +input i_dabt; // data abort interrupt request +input i_iabt; // instruction pre-fetch abort flag +input i_adex; // Address Exception +input [31:0] i_execute_iaddress; // Registered instruction address output by execute stage +//input [31:0] i_execute_daddress; // Registered instruction address output by execute stage +input [7:0] i_abt_status; // Abort status +input [31:0] i_execute_status_bits; // current status bits values in execute stage +input i_multiply_done; // multiply unit is nearly done + + +// -------------------------------------------------- +// Control signals to execute stage +// -------------------------------------------------- +output [31:0] o_imm32; +output [4:0] o_imm_shift_amount; +output o_shift_imm_zero; +output [3:0] o_condition; // 4'he = al +output o_decode_exclusive; // exclusive access request ( swap instruction ) +output o_decode_iaccess; // Indicates an instruction access +output o_decode_daccess; // Indicates a data access +output [1:0] o_status_bits_mode; // SVC +output o_status_bits_irq_mask; +output o_status_bits_firq_mask; + +output [3:0] o_rm_sel; +output [3:0] o_rs_sel; +output [7:0] o_load_rd; // [7] load flags with PC + // [6] load status bits with PC + // [5] Write into User Mode register + // [4] zero-extend load + // [3:0] destination register, Rd +output [3:0] o_rn_sel; +output [1:0] o_barrel_shift_amount_sel; +output [1:0] o_barrel_shift_data_sel; +output [1:0] o_barrel_shift_function; +output [8:0] o_alu_function; +output [1:0] o_multiply_function; +output [2:0] o_interrupt_vector_sel; +output [3:0] o_iaddress_sel; +output [3:0] o_daddress_sel; +output [2:0] o_pc_sel; +output [1:0] o_byte_enable_sel; // byte, halfword or word write +output [2:0] o_status_bits_sel; +output [2:0] o_reg_write_sel; +output o_user_mode_regs_store_nxt; +output o_firq_not_user_mode; + +output o_write_data_wen; +output o_base_address_wen; // save ldm base address register + // in case of data abort +output o_pc_wen; +output [14:0] o_reg_bank_wen; +output o_status_bits_flags_wen; +output o_status_bits_mode_wen; +output o_status_bits_irq_mask_wen; +output o_status_bits_firq_mask_wen; + +// -------------------------------------------------- +// Co-Processor interface +// -------------------------------------------------- +output [2:0] o_copro_opcode1; +output [2:0] o_copro_opcode2; +output [3:0] o_copro_crn; +output [3:0] o_copro_crm; +output [3:0] o_copro_num; +output [1:0] o_copro_operation; // 0 = no operation, + // 1 = Move to Amber Core Register from Coprocessor + // 2 = Move to Coprocessor from Amber Core Register +output o_copro_write_data_wen; +output o_iabt_trigger; +output [31:0] o_iabt_address; +output [7:0] o_iabt_status; +output o_dabt_trigger; +output [31:0] o_dabt_address; +output [7:0] o_dabt_status; +output o_conflict; +output o_rn_use_read; +output o_rm_use_read; +output o_rs_use_read; +output o_rd_use_read; + + + + +/*********************** Signal Declarations *******************/ + +reg [31:0] o_imm32 = 32'd0; +reg [4:0] o_imm_shift_amount = 5'd0; +reg o_shift_imm_zero = 1'd0; +reg [3:0] o_condition = 4'he; // 4'he = al +reg o_decode_exclusive = 1'd0; // exclusive access request ( swap instruction ) +reg o_decode_iaccess = 1'd1; // Indicates an instruction access +reg o_decode_daccess = 1'd0; // Indicates a data access +reg [1:0] o_status_bits_mode = 2'b11; // SVC +reg o_status_bits_irq_mask = 1'd1; +reg o_status_bits_firq_mask = 1'd1; + +reg [3:0] o_rm_sel = 4'd0; +reg [3:0] o_rs_sel = 4'd0; +reg [7:0] o_load_rd = 8'd0; // [7] load flags with PC + +reg [3:0] o_rn_sel = 4'd0; +reg [1:0] o_barrel_shift_amount_sel = 2'd0; +reg [1:0] o_barrel_shift_data_sel = 2'd0; +reg [1:0] o_barrel_shift_function = 2'd0; +reg [8:0] o_alu_function = 9'd0; +reg [1:0] o_multiply_function = 2'd0; +reg [2:0] o_interrupt_vector_sel = 3'd0; +reg [3:0] o_iaddress_sel = 4'd2; +reg [3:0] o_daddress_sel = 4'd2; +reg [2:0] o_pc_sel = 3'd2; +reg [1:0] o_byte_enable_sel = 2'd0; // byte, halfword or word write +reg [2:0] o_status_bits_sel = 3'd0; +reg [2:0] o_reg_write_sel; +reg o_user_mode_regs_store_nxt; +reg o_firq_not_user_mode; + +reg o_write_data_wen = 1'd0; +reg o_base_address_wen = 1'd0; // save ldm base address register + // in case of data abort +reg o_pc_wen = 1'd1; +reg [14:0] o_reg_bank_wen = 15'd0; +reg o_status_bits_flags_wen = 1'd0; +reg o_status_bits_mode_wen = 1'd0; +reg o_status_bits_irq_mask_wen = 1'd0; +reg o_status_bits_firq_mask_wen = 1'd0; + +// -------------------------------------------------- +// Co-Processor interface +// -------------------------------------------------- +reg [2:0] o_copro_opcode1 = 3'd0; +reg [2:0] o_copro_opcode2 = 3'd0; +reg [3:0] o_copro_crn = 4'd0; +reg [3:0] o_copro_crm = 4'd0; +reg [3:0] o_copro_num = 4'd0; +reg [1:0] o_copro_operation = 2'd0; // 0 = no operation, + // 1 = Move to Amber Core Register from Coprocessor + // 2 = Move to Coprocessor from Amber Core Register +reg o_copro_write_data_wen = 1'd0; +reg o_rn_use_read; +reg o_rm_use_read; +reg o_rs_use_read; +reg o_rd_use_read; + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + + +localparam [4:0] RST_WAIT1 = 5'd0, + RST_WAIT2 = 5'd1, + INT_WAIT1 = 5'd2, + INT_WAIT2 = 5'd3, + EXECUTE = 5'd4, + PRE_FETCH_EXEC = 5'd5, // Execute the Pre-Fetched Instruction + MEM_WAIT1 = 5'd6, // conditionally decode current instruction, in case + // previous instruction does not execute in S2 + MEM_WAIT2 = 5'd7, + PC_STALL1 = 5'd8, // Program Counter altered + // conditionally decude current instruction, in case + // previous instruction does not execute in S2 + PC_STALL2 = 5'd9, + MTRANS_EXEC1 = 5'd10, + MTRANS_EXEC2 = 5'd11, + MTRANS_ABORT = 5'd12, + MULT_PROC1 = 5'd13, // first cycle, save pre fetch instruction + MULT_PROC2 = 5'd14, // do multiplication + MULT_STORE = 5'd15, // save RdLo + MULT_ACCUMU = 5'd16, // Accumulate add lower 32 bits + SWAP_WRITE = 5'd17, + SWAP_WAIT1 = 5'd18, + SWAP_WAIT2 = 5'd19, + COPRO_WAIT = 5'd20; + + +// ======================================================== +// Internal signals +// ======================================================== +wire [31:0] instruction; +wire [3:0] type; // regop, mem access etc. +wire instruction_iabt; // abort flag, follows the instruction +wire instruction_adex; // address exception flag, follows the instruction +wire [31:0] instruction_address; // instruction virtual address, follows + // the instruction +wire [7:0] instruction_iabt_status; // abort status, follows the instruction +wire [1:0] instruction_sel; +wire [3:0] opcode; +wire [7:0] imm8; +wire [31:0] offset12; +wire [31:0] offset24; +wire [4:0] shift_imm; + +wire opcode_compare; +wire mem_op; +wire load_op; +wire store_op; +wire write_pc; +wire current_write_pc; +reg load_pc_nxt; +reg load_pc_r = 1'd0; +wire immediate_shift_op; +wire rds_use_rs; +wire branch; +wire mem_op_pre_indexed; +wire mem_op_post_indexed; + +// Flop inputs +wire [31:0] imm32_nxt; +wire [4:0] imm_shift_amount_nxt; +wire shift_imm_zero_nxt; +wire [3:0] condition_nxt; +reg decode_exclusive_nxt; +reg decode_iaccess_nxt; +reg decode_daccess_nxt; + +reg [1:0] barrel_shift_function_nxt; +wire [8:0] alu_function_nxt; +reg [1:0] multiply_function_nxt; +reg [1:0] status_bits_mode_nxt; +reg status_bits_irq_mask_nxt; +reg status_bits_firq_mask_nxt; + +wire [3:0] rm_sel_nxt; +wire [3:0] rs_sel_nxt; + +wire [3:0] rn_sel_nxt; +reg [1:0] barrel_shift_amount_sel_nxt; +reg [1:0] barrel_shift_data_sel_nxt; +reg [3:0] iaddress_sel_nxt; +reg [3:0] daddress_sel_nxt; +reg [2:0] pc_sel_nxt; +reg [1:0] byte_enable_sel_nxt; +reg [2:0] status_bits_sel_nxt; +reg [2:0] reg_write_sel_nxt; +wire firq_not_user_mode_nxt; + +// ALU Function signals +reg alu_swap_sel_nxt; +reg alu_not_sel_nxt; +reg [1:0] alu_cin_sel_nxt; +reg alu_cout_sel_nxt; +reg [3:0] alu_out_sel_nxt; + +reg write_data_wen_nxt; +reg copro_write_data_wen_nxt; +reg base_address_wen_nxt; +reg pc_wen_nxt; +reg [14:0] reg_bank_wen_nxt; +reg status_bits_flags_wen_nxt; +reg status_bits_mode_wen_nxt; +reg status_bits_irq_mask_wen_nxt; +reg status_bits_firq_mask_wen_nxt; + +reg saved_current_instruction_wen; // saved load instruction +reg pre_fetch_instruction_wen; // pre-fetch instruction + +reg [4:0] control_state = 5'd0; //RST_WAIT1 +reg [4:0] control_state_nxt; + + +wire dabt; +reg dabt_reg = 1'd0; +reg dabt_reg_d1; +reg iabt_reg = 1'd0; +reg adex_reg = 1'd0; +reg [31:0] fetch_address_r = 32'd0; +reg [7:0] abt_status_reg = 8'd0; +reg [31:0] fetch_instruction_r = 32'd0; +reg [3:0] fetch_instruction_type_r = 4'd0; +reg [31:0] saved_current_instruction = 32'd0; +reg [3:0] saved_current_instruction_type = 4'd0; +reg saved_current_instruction_iabt = 1'd0; // access abort flag +reg saved_current_instruction_adex = 1'd0; // address exception +reg [31:0] saved_current_instruction_address = 32'd0; // virtual address of abort instruction +reg [7:0] saved_current_instruction_iabt_status = 8'd0; // status of abort instruction +reg [31:0] pre_fetch_instruction = 32'd0; +reg [3:0] pre_fetch_instruction_type = 4'd0; +reg pre_fetch_instruction_iabt = 1'd0; // access abort flag +reg pre_fetch_instruction_adex = 1'd0; // address exception +reg [31:0] pre_fetch_instruction_address = 32'd0; // virtual address of abort instruction +reg [7:0] pre_fetch_instruction_iabt_status = 8'd0; // status of abort instruction +reg [31:0] hold_instruction = 32'd0; +reg [3:0] hold_instruction_type = 4'd0; +reg hold_instruction_iabt = 1'd0; // access abort flag +reg hold_instruction_adex = 1'd0; // address exception +reg [31:0] hold_instruction_address = 32'd0; // virtual address of abort instruction +reg [7:0] hold_instruction_iabt_status = 8'd0; // status of abort instruction + +wire instruction_valid; +wire instruction_execute; +reg instruction_execute_r = 1'd0; + +reg [3:0] mtrans_reg1; // the current register being accessed as part of stm/ldm +reg [3:0] mtrans_reg2; // the next register being accessed as part of stm/ldm +reg [31:0] mtrans_instruction_nxt; +wire [15:0] mtrans_reg2_mask; + +wire [31:0] mtrans_base_reg_change; +wire [4:0] mtrans_num_registers; +wire use_saved_current_instruction; +wire use_hold_instruction; +wire use_pre_fetch_instruction; +wire interrupt; +wire interrupt_or_conflict; +wire [1:0] interrupt_mode; +wire [2:0] next_interrupt; +reg irq = 1'd0; +reg firq = 1'd0; +wire firq_request; +wire irq_request; +wire swi_request; +wire und_request; +wire dabt_request; +reg [1:0] copro_operation_nxt; +reg restore_base_address = 1'd0; +reg restore_base_address_nxt; + +wire regop_set_flags; + +wire [7:0] load_rd_nxt; +wire load_rd_byte; +wire ldm_user_mode; +wire ldm_status_bits; +wire ldm_flags; +wire [6:0] load_rd_d1_nxt; +reg [6:0] load_rd_d1 = 7'd0; // MSB is the valid bit + +wire rn_valid; +wire rm_valid; +wire rs_valid; +wire rd_valid; +wire stm_valid; +wire rn_conflict1; +wire rn_conflict2; +wire rm_conflict1; +wire rm_conflict2; +wire rs_conflict1; +wire rs_conflict2; +wire rd_conflict1; +wire rd_conflict2; +wire stm_conflict1a; +wire stm_conflict1b; +wire stm_conflict2a; +wire stm_conflict2b; +wire conflict1; // Register conflict1 with ldr operation +wire conflict2; // Register conflict1 with ldr operation +wire conflict; // Register conflict1 with ldr operation +reg conflict_r = 1'd0; +reg rn_conflict1_r = 1'd0; +reg rm_conflict1_r = 1'd0; +reg rs_conflict1_r = 1'd0; +reg rd_conflict1_r = 1'd0; +wire [11:0] i_fetch; + +// ======================================================== +// Instruction Abort and Data Abort outputs +// ======================================================== + + +assign o_iabt_trigger = instruction_iabt && o_status_bits_mode == SVC && control_state == INT_WAIT1; +assign o_iabt_address = instruction_address; +assign o_iabt_status = instruction_iabt_status; + +assign o_dabt_trigger = dabt_reg && !dabt_reg_d1; +assign o_dabt_address = fetch_address_r; +assign o_dabt_status = abt_status_reg; + + +// ======================================================== +// Instruction Decode +// ======================================================== + +// for instructions that take more than one cycle +// the instruction is saved in the 'saved_mem_instruction' +// register and then that register is used for the rest of +// the execution of the instruction. +// But if the instruction does not execute because of the +// condition, then need to select the next instruction to +// decode +assign use_saved_current_instruction = instruction_execute && + ( control_state == MEM_WAIT1 || + control_state == MEM_WAIT2 || + control_state == MTRANS_EXEC1 || + control_state == MTRANS_EXEC2 || + control_state == MTRANS_ABORT || + control_state == MULT_PROC1 || + control_state == MULT_PROC2 || + control_state == MULT_ACCUMU || + control_state == MULT_STORE || + control_state == INT_WAIT1 || + control_state == INT_WAIT2 || + control_state == SWAP_WRITE || + control_state == SWAP_WAIT1 || + control_state == SWAP_WAIT2 || + control_state == COPRO_WAIT ); + +assign use_hold_instruction = conflict_r; + +assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC; + + +assign instruction_sel = use_hold_instruction ? 2'd3 : // hold_instruction + use_saved_current_instruction ? 2'd1 : // saved_current_instruction + use_pre_fetch_instruction ? 2'd2 : // pre_fetch_instruction + 2'd0 ; // fetch_instruction_r + +assign instruction = instruction_sel == 2'd0 ? fetch_instruction_r : + instruction_sel == 2'd1 ? saved_current_instruction : + instruction_sel == 2'd3 ? hold_instruction : + pre_fetch_instruction ; + +assign type = instruction_sel == 2'd0 ? fetch_instruction_type_r : + instruction_sel == 2'd1 ? saved_current_instruction_type : + instruction_sel == 2'd3 ? hold_instruction_type : + pre_fetch_instruction_type ; + +// abort flag +assign instruction_iabt = instruction_sel == 2'd0 ? iabt_reg : + instruction_sel == 2'd1 ? saved_current_instruction_iabt : + instruction_sel == 2'd3 ? hold_instruction_iabt : + pre_fetch_instruction_iabt ; + +assign instruction_address = instruction_sel == 2'd0 ? fetch_address_r : + instruction_sel == 2'd1 ? saved_current_instruction_address : + instruction_sel == 2'd3 ? hold_instruction_address : + pre_fetch_instruction_address ; + +assign instruction_iabt_status = instruction_sel == 2'd0 ? abt_status_reg : + instruction_sel == 2'd1 ? saved_current_instruction_iabt_status : + instruction_sel == 2'd3 ? hold_instruction_iabt_status : + pre_fetch_instruction_iabt_status ; + +// instruction address exception +assign instruction_adex = instruction_sel == 2'd0 ? adex_reg : + instruction_sel == 2'd1 ? saved_current_instruction_adex : + instruction_sel == 2'd3 ? hold_instruction_adex : + pre_fetch_instruction_adex ; + + +// ======================================================== +// Fixed fields within the instruction +// ======================================================== + +assign opcode = instruction[24:21]; +assign condition_nxt = instruction[31:28]; + +assign rm_sel_nxt = instruction[3:0]; +assign rn_sel_nxt = branch ? 4'd15 : instruction[19:16]; // Use PC to calculate branch destination +assign rs_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory + type == MTRANS ? mtrans_reg1 : + branch ? 4'd15 : // Update the PC + rds_use_rs ? instruction[11:8] : + instruction[15:12] ; + +// Load from memory into registers +assign ldm_user_mode = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010; +assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22]; +assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR; +assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22]; +assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt}; + + + // MSB indicates valid dirty target register +assign load_rd_d1_nxt = {o_decode_daccess && !o_write_data_wen, o_load_rd[3:0]}; +assign shift_imm = instruction[11:7]; +assign offset12 = { 20'h0, instruction[11:0]}; +assign offset24 = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend +assign imm8 = instruction[7:0]; + +assign immediate_shift_op = instruction[25]; +assign rds_use_rs = (type == REGOP && !instruction[25] && instruction[4]) || + (type == MULT && + (control_state == MULT_PROC1 || + control_state == MULT_PROC2 || +// instruction_valid && !interrupt )) ; +// remove the '!conflict' term from the interrupt logic used here +// to break a combinational loop + (instruction_valid && !interrupt_or_conflict))) ; + + +assign branch = type == BRANCH; +assign opcode_compare = opcode == CMP || opcode == CMN || opcode == TEQ || opcode == TST ; +assign mem_op = type == TRANS; +assign load_op = mem_op && instruction[20]; +assign store_op = mem_op && !instruction[20]; +assign write_pc = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_r || load_pc_nxt; +assign current_write_pc = (pc_wen_nxt && pc_sel_nxt != 3'd0) || load_pc_nxt; +assign regop_set_flags = type == REGOP && instruction[20]; + +assign mem_op_pre_indexed = instruction[24] && instruction[21]; +assign mem_op_post_indexed = !instruction[24]; + +assign imm32_nxt = // add 0 to Rm + type == MULT ? { 32'd0 } : //MULT = 4'h1, + + // 4 x number of registers + type == MTRANS ? { mtrans_base_reg_change } : //MTRANS = 4'h4 + type == BRANCH ? { offset24 } : //BRANCH = 4'h5 + type == TRANS ? { offset12 } : //TRANS = 4'h3 + instruction[11:8] == 4'h0 ? { 24'd0, imm8[7:0] } : + instruction[11:8] == 4'h1 ? { imm8[1:0], 24'd0, imm8[7:2] } : + instruction[11:8] == 4'h2 ? { imm8[3:0], 24'd0, imm8[7:4] } : + instruction[11:8] == 4'h3 ? { imm8[5:0], 24'd0, imm8[7:6] } : + instruction[11:8] == 4'h4 ? { imm8[7:0], 24'd0 } : + instruction[11:8] == 4'h5 ? { 2'd0, imm8[7:0], 22'd0 } : + instruction[11:8] == 4'h6 ? { 4'd0, imm8[7:0], 20'd0 } : + instruction[11:8] == 4'h7 ? { 6'd0, imm8[7:0], 18'd0 } : + instruction[11:8] == 4'h8 ? { 8'd0, imm8[7:0], 16'd0 } : + instruction[11:8] == 4'h9 ? { 10'd0, imm8[7:0], 14'd0 } : + instruction[11:8] == 4'ha ? { 12'd0, imm8[7:0], 12'd0 } : + instruction[11:8] == 4'hb ? { 14'd0, imm8[7:0], 10'd0 } : + instruction[11:8] == 4'hc ? { 16'd0, imm8[7:0], 8'd0 } : + instruction[11:8] == 4'hd ? { 18'd0, imm8[7:0], 6'd0 } : + instruction[11:8] == 4'he ? { 20'd0, imm8[7:0], 4'd0 } : + { 22'd0, imm8[7:0],2'd0 } ; + + +assign imm_shift_amount_nxt = shift_imm ; + + // This signal is encoded in the decode stage because + // it is on the critical path in the execute stage +assign shift_imm_zero_nxt = imm_shift_amount_nxt == 5'd0 && // immediate amount = 0 + barrel_shift_amount_sel_nxt == 2'd2; // shift immediate amount + +assign alu_function_nxt = { alu_swap_sel_nxt, + alu_not_sel_nxt, + alu_cin_sel_nxt, + alu_cout_sel_nxt, + alu_out_sel_nxt }; + +// ======================================================== +// Register Conflict Detection +// ======================================================== +assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS; +assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op); +assign rs_valid = rds_use_rs; +assign rd_valid = (type == TRANS && store_op) || (type == REGOP || type == SWAP); +assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction + + +assign rn_conflict1 = instruction_execute && rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] ); +assign rn_conflict2 = instruction_execute_r && rn_valid && ( load_rd_d1 [4] && rn_sel_nxt == load_rd_d1 [3:0] ); +assign rm_conflict1 = instruction_execute && rm_valid && ( load_rd_d1_nxt[4] && rm_sel_nxt == load_rd_d1_nxt[3:0] ); +assign rm_conflict2 = instruction_execute_r && rm_valid && ( load_rd_d1 [4] && rm_sel_nxt == load_rd_d1 [3:0] ); +assign rs_conflict1 = instruction_execute && rs_valid && ( load_rd_d1_nxt[4] && rs_sel_nxt == load_rd_d1_nxt[3:0] ); +assign rs_conflict2 = instruction_execute_r && rs_valid && ( load_rd_d1 [4] && rs_sel_nxt == load_rd_d1 [3:0] ); +assign rd_conflict1 = instruction_execute && rd_valid && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] ); +assign rd_conflict2 = instruction_execute_r && rd_valid && ( load_rd_d1 [4] && instruction[15:12] == load_rd_d1 [3:0] ); + +assign stm_conflict1a = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1 == load_rd_d1_nxt[3:0] ); +assign stm_conflict1b = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2 == load_rd_d1_nxt[3:0] ); +assign stm_conflict2a = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg1 == load_rd_d1 [3:0] ); +assign stm_conflict2b = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg2 == load_rd_d1 [3:0] ); + +assign conflict1 = instruction_valid && + (rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 || + stm_conflict1a || stm_conflict1b); + +assign conflict2 = instruction_valid && (stm_conflict2a || stm_conflict2b); + +assign conflict = conflict1 || conflict2; + + +always @( posedge i_clk ) + if ( !i_core_stall ) + begin + conflict_r <= conflict; + instruction_execute_r <= instruction_execute; + rn_conflict1_r <= rn_conflict1 && instruction_execute; + rm_conflict1_r <= rm_conflict1 && instruction_execute; + rs_conflict1_r <= rs_conflict1 && instruction_execute; + rd_conflict1_r <= rd_conflict1 && instruction_execute; + o_rn_use_read <= instruction_valid && ( rn_conflict1_r || rn_conflict2 ); + o_rm_use_read <= instruction_valid && ( rm_conflict1_r || rm_conflict2 ); + o_rs_use_read <= instruction_valid && ( rs_conflict1_r || rs_conflict2 ); + o_rd_use_read <= instruction_valid && ( rd_conflict1_r || rd_conflict2 ); + end + +assign o_conflict = conflict; + + +// ======================================================== +// MTRANS Operations +// ======================================================== + + // Bit 15 = r15 + // Bit 0 = r0 + // In ldm and stm instructions r0 is loaded or stored first +always @* + + if (instruction[0] == 1'b1) mtrans_reg1 = 4'h0; + else if (instruction[1:0] == 2'b10) mtrans_reg1 = 4'h1; + else if (instruction[2:0] == 3'b100) mtrans_reg1 = 4'h2; + else if (instruction[3:0] == 4'b1000) mtrans_reg1 = 4'h3; + else if (instruction[4:0] == 5'b10000) mtrans_reg1 = 4'h4; + else if (instruction[5:0] == 6'b100000) mtrans_reg1 = 4'h5; + else if (instruction[6:0] == 7'b1000000) mtrans_reg1 = 4'h6; + else if (instruction[7:0] == 8'b10000000) mtrans_reg1 = 4'h7; + else if (instruction[8:0] == 9'b100000000) mtrans_reg1 = 4'h8; + else if (instruction[9:0] == 10'b1000000000) mtrans_reg1 = 4'h9; + else if (instruction[10:0] == 11'b10000000000) mtrans_reg1 = 4'ha; + else if (instruction[11:0] == 12'b100000000000) mtrans_reg1 = 4'hb; + else if (instruction[12:0] == 13'b1000000000000) mtrans_reg1 = 4'hc; + else if (instruction[13:0] == 14'b10000000000000) mtrans_reg1 = 4'hd; + else if (instruction[14:0] == 15'b100000000000000) mtrans_reg1 = 4'he; + else mtrans_reg1 = 4'hf; + +// casez ( instruction[15:0] ) +// 16'b???????????????1 : mtrans_reg1 = 4'h0 ; +// 16'b??????????????10 : mtrans_reg1 = 4'h1 ; +// 16'b?????????????100 : mtrans_reg1 = 4'h2 ; +// 16'b????????????1000 : mtrans_reg1 = 4'h3 ; +// 16'b???????????10000 : mtrans_reg1 = 4'h4 ; +// 16'b??????????100000 : mtrans_reg1 = 4'h5 ; +// 16'b?????????1000000 : mtrans_reg1 = 4'h6 ; +// 16'b????????10000000 : mtrans_reg1 = 4'h7 ; +// 16'b???????100000000 : mtrans_reg1 = 4'h8 ; +// 16'b??????1000000000 : mtrans_reg1 = 4'h9 ; +// 16'b?????10000000000 : mtrans_reg1 = 4'ha ; +// 16'b????100000000000 : mtrans_reg1 = 4'hb ; +// 16'b???1000000000000 : mtrans_reg1 = 4'hc ; +// 16'b??10000000000000 : mtrans_reg1 = 4'hd ; +// 16'b?100000000000000 : mtrans_reg1 = 4'he ; +// default : mtrans_reg1 = 4'hf ; +// endcase + + + +//assign mtrans_reg2_mask = 1'd1< 4'd2 )) + decode_iaccess_nxt = 1'd0; + + else if ( control_state == MTRANS_EXEC2 && ( mtrans_num_registers > 4'd2 )) + decode_iaccess_nxt = 1'd0; + + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + decode_iaccess_nxt = 1'd0; + + else + decode_iaccess_nxt = 1'd1; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == CORTRANS && !und_request ) + begin + if ( instruction[20] ) + copro_operation_nxt = 2'd1; + else + copro_operation_nxt = 2'd0; + end + else + copro_operation_nxt = 2'd0; + end + + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && !instruction[20]) + copro_operation_nxt = 2'd2; + + else + copro_operation_nxt = 2'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && (load_op && instruction[15:12] == 4'd15)) + saved_current_instruction_wen = 1'd1; + else if ( type == MTRANS ) + saved_current_instruction_wen = 1'd1; + else if ( type == MULT ) + saved_current_instruction_wen = 1'd1; + else if ( type == SWAP ) + saved_current_instruction_wen = 1'd1; + else if ( type == CORTRANS && !und_request ) + saved_current_instruction_wen = 1'd1; + else + saved_current_instruction_wen = 1'd0; + end + + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + saved_current_instruction_wen = 1'd1; + + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute &&( instruction[20] && mtrans_reg1 == 4'd15 )) + saved_current_instruction_wen = 1'd1; + + else if ( control_state == MTRANS_EXEC2 && ( instruction[20] && mtrans_reg1 == 4'd15 )) + saved_current_instruction_wen = 1'd1; + + else + saved_current_instruction_wen = 1'd0; + end + +always @* + begin + if ( control_state == MEM_WAIT1 && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == MTRANS_EXEC1 && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == MULT_PROC1 && instruction_execute && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict ) + pre_fetch_instruction_wen = 1'd1; + else + pre_fetch_instruction_wen = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == MTRANS) + // restore_base_address_nxt <= instruction[20] && + // (instruction[15:0] & (1'd1 << instruction[19:16])); + restore_base_address_nxt = instruction[20] && + (instruction[15:0] & ( + instruction[19:16] == 4'h1 ? 16'b10: + instruction[19:16] == 4'h2 ? 16'b100: + instruction[19:16] == 4'h3 ? 16'b1000: + instruction[19:16] == 4'h4 ? 16'b10000: + instruction[19:16] == 4'h5 ? 16'b100000: + instruction[19:16] == 4'h6 ? 16'b1000000: + instruction[19:16] == 4'h7 ? 16'b10000000: + instruction[19:16] == 4'h8 ? 16'b100000000: + instruction[19:16] == 4'h9 ? 16'b1000000000: + instruction[19:16] == 4'ha ? 16'b10000000000: + instruction[19:16] == 4'hb ? 16'b100000000000: + instruction[19:16] == 4'hc ? 16'b1000000000000: + instruction[19:16] == 4'hd ? 16'b10000000000000: + instruction[19:16] == 4'he ? 16'b100000000000000: + instruction[19:16] == 4'hf ? 16'b1000000000000000: + 16'b1)); + else + restore_base_address_nxt = restore_base_address; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP ) + begin + if ( !immediate_shift_op && instruction[4] ) + barrel_shift_amount_sel_nxt = 2'd1; + else if ( !immediate_shift_op && !instruction[4] ) + barrel_shift_amount_sel_nxt = 2'd2; + else + barrel_shift_amount_sel_nxt = 2'd0; + end + else if ( mem_op && ( type == TRANS && instruction[25] && shift_imm != 5'd0 ) ) + barrel_shift_amount_sel_nxt = 2'd2; + else + barrel_shift_amount_sel_nxt = 2'd0; + end + else + barrel_shift_amount_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if(type == REGOP && !immediate_shift_op) + barrel_shift_data_sel_nxt = 2'd2; + + else if (mem_op && instruction[25] && type == TRANS) + barrel_shift_data_sel_nxt = 2'd2; + else if ( type == SWAP ) + barrel_shift_data_sel_nxt = 2'd2; + else + barrel_shift_data_sel_nxt = 2'd0; + end + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + barrel_shift_data_sel_nxt = 2'd2; + else + barrel_shift_data_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP && !immediate_shift_op) + barrel_shift_function_nxt = instruction[6:5]; + else if ( mem_op && type == TRANS && instruction[25] && shift_imm != 5'd0 ) + barrel_shift_function_nxt = instruction[6:5]; + else + barrel_shift_function_nxt = 2'd0; + end + else + barrel_shift_function_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == MULT) + begin + multiply_function_nxt[0] = 1'd1; + if( instruction[21] ) + multiply_function_nxt[1] = 1'd1; + else + multiply_function_nxt[1] = 1'd0; + end + else if ( control_state == MULT_PROC1 && instruction_execute && !conflict ) + multiply_function_nxt = o_multiply_function; + else if ( control_state == MULT_PROC2 ) + multiply_function_nxt = o_multiply_function; + else if ( control_state == MULT_STORE ) + multiply_function_nxt = o_multiply_function; + else if ( control_state == MULT_ACCUMU ) + multiply_function_nxt = o_multiply_function; + else + multiply_function_nxt = 2'd0; + end + + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP && !opcode_compare && instruction[15:12] == 4'd15) + iaddress_sel_nxt = 4'd1; + else if ( type == BRANCH ) + iaddress_sel_nxt = 4'd1; + else if ( type == MTRANS && mtrans_num_registers > 4'd1) + iaddress_sel_nxt = 4'd3; + else if ( type == CORTRANS && !und_request ) + iaddress_sel_nxt = 4'd3; + else if ( type == SWI || und_request ) + iaddress_sel_nxt = 4'd2; + else + iaddress_sel_nxt = 4'd0; + + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + iaddress_sel_nxt = 4'd2; + + else if ( control_state == MEM_WAIT1 && !conflict &&instruction_execute) + iaddress_sel_nxt = 4'd3; + + else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || + ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + + iaddress_sel_nxt = 4'd3; + + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && mtrans_num_registers != 4'd1) + + iaddress_sel_nxt = 4'd3; + + else if ( control_state == MTRANS_EXEC2 && mtrans_num_registers > 4'd1) + iaddress_sel_nxt = 4'd3; + else if ( control_state == MULT_PROC2 ) + iaddress_sel_nxt = 4'd3; + else if ( control_state == MULT_ACCUMU ) + iaddress_sel_nxt = 4'd3; + else if ( control_state == SWAP_WAIT1 && instruction_execute) + iaddress_sel_nxt = 4'd3; + else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15) + iaddress_sel_nxt = 4'd3; + else + iaddress_sel_nxt = 4'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op ) + begin + if ( mem_op_post_indexed ) + daddress_sel_nxt = 4'd4; // Rn + else + daddress_sel_nxt = 4'd1; // alu out + end + else if ( type == MTRANS ) + if ( instruction[23] ) + begin + if ( instruction[24] ) // increment before + daddress_sel_nxt = 4'd7; // Rn + 4 + else + daddress_sel_nxt = 4'd4; // Rn + end + else + begin + if ( !instruction[24] ) // decrement after + daddress_sel_nxt = 4'd6; // alu out + 4 + else + daddress_sel_nxt = 4'd1; // alu out + end + else if ( type == SWAP ) + daddress_sel_nxt = 4'd4; + else + daddress_sel_nxt = 4'd0; + end + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute ) + daddress_sel_nxt = 4'd5; + else if ( control_state == MTRANS_EXEC2 ) + daddress_sel_nxt = 4'd5; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + daddress_sel_nxt = 4'd4; + else + daddress_sel_nxt = 4'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP && !opcode_compare && instruction[15:12] == 4'd15 ) + pc_sel_nxt = 3'd1; + else if ( mem_op && (mem_op_pre_indexed || mem_op_post_indexed) && rn_sel_nxt == 4'd15 ) + pc_sel_nxt = 3'd1; + else if ( type == BRANCH ) + pc_sel_nxt = 3'd1; + else if ( type == SWI || und_request ) + pc_sel_nxt = 3'd2; + else + pc_sel_nxt = 3'd0; + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + pc_sel_nxt = 3'd2; + else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || + ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + pc_sel_nxt = 3'd3; + + else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15 ) + + pc_sel_nxt = 3'd3; + else + pc_sel_nxt = 3'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && ( load_op && instruction[15:12] == 4'd15 )) + load_pc_nxt = 1'd1; + else if ( type == MTRANS && ( instruction[20] && mtrans_reg1 == 4'd15 )) + load_pc_nxt = 1'd1; + else + load_pc_nxt = 1'd0; + end + else if ( control_state == MEM_WAIT1 && !conflict && instruction_execute) + load_pc_nxt = load_pc_r; + else if ( control_state == MEM_WAIT2 && !dabt && (( type == TRANS && instruction[15:12] == 4'd15 ) || + ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ))) + load_pc_nxt = load_pc_r; + + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && ( instruction[20] && mtrans_reg1 == 4'd15 )) + load_pc_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC2 && ( instruction[20] && mtrans_reg1 == 4'd15 )) + load_pc_nxt = 1'd1; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + load_pc_nxt = load_pc_r; + else if ( control_state == SWAP_WAIT1 && !dabt && instruction[15:12] == 4'd15 ) + load_pc_nxt = load_pc_r; + else + load_pc_nxt = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && store_op && type == TRANS && instruction[22] ) + byte_enable_sel_nxt = 2'd1; + else + byte_enable_sel_nxt = 2'd0; + end + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict && instruction[22]) + byte_enable_sel_nxt = 2'd1; + else + byte_enable_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && regop_set_flags && instruction[15:12] == 4'd15) + status_bits_sel_nxt = 3'd1; + else if ( control_state == MULT_STORE && instruction[20]) + status_bits_sel_nxt = 3'd4; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] && instruction[15:12] == 4'd15 ) + status_bits_sel_nxt = 3'd3; + else + status_bits_sel_nxt = 3'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == BRANCH && instruction[24] ) + reg_write_sel_nxt = 3'd1; + else if ( type == SWI || und_request ) + reg_write_sel_nxt = 3'd1; + else + reg_write_sel_nxt = 3'd0; + + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + begin + if ( next_interrupt == 3'd4 ) + reg_write_sel_nxt = 3'd7; + else + reg_write_sel_nxt = 3'd1; + end + else if ( control_state == MTRANS_ABORT && restore_base_address ) + reg_write_sel_nxt = 3'd6; + else if ( control_state == MULT_STORE ) + reg_write_sel_nxt = 3'd2; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20]) + reg_write_sel_nxt = 3'd5; + else + reg_write_sel_nxt = 3'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == MTRANS && instruction[22:20] == 3'b100 ) + o_user_mode_regs_store_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && instruction[22:20] == 3'b100 ) + o_user_mode_regs_store_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC2 && instruction[22:20] == 3'b100 ) + o_user_mode_regs_store_nxt = 1'd1; + else + o_user_mode_regs_store_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == REGOP ) + begin + if ( opcode == RSB ) + alu_swap_sel_nxt = 1'd1; + else if ( opcode == RSC ) + alu_swap_sel_nxt = 1'd1; + else + alu_swap_sel_nxt = 1'd0; + end + else + alu_swap_sel_nxt = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP ) + begin + if ( opcode == SUB || opcode == CMP ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == SBC ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == RSB ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == RSC ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == BIC ) + alu_not_sel_nxt = 1'd1; + else if ( opcode == MVN ) + alu_not_sel_nxt = 1'd1; + else + alu_not_sel_nxt = 1'd0; + end + else if ( mem_op && !instruction[23]) + alu_not_sel_nxt = 1'd1; + else if ( type == MTRANS && !instruction[23]) + alu_not_sel_nxt = 1'd1; + else + alu_not_sel_nxt = 1'd0; + end + else + alu_not_sel_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP ) + begin + if ( opcode == ADC ) + alu_cin_sel_nxt = 2'd2; + else if ( opcode == SUB || opcode == CMP ) + alu_cin_sel_nxt = 2'd1; + else if ( opcode == SBC ) + alu_cin_sel_nxt = 2'd2; + else if ( opcode == RSB ) + alu_cin_sel_nxt = 2'd1; + else if ( opcode == RSC ) + alu_cin_sel_nxt = 2'd2; + else + alu_cin_sel_nxt = 2'd0; + end + else if ( mem_op && !instruction[23]) + alu_cin_sel_nxt = 2'd1; + else if ( type == MTRANS && !instruction[23]) + alu_cin_sel_nxt = 2'd1; + else + alu_cin_sel_nxt = 2'd0; + end + else + alu_cin_sel_nxt = 2'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && type == REGOP ) + begin + if ( opcode == AND || opcode == TST ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == EOR || opcode == TEQ ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == ORR ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == BIC ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == MOV ) + alu_cout_sel_nxt = 1'd1; + else if ( opcode == MVN ) + alu_cout_sel_nxt = 1'd1; + else + alu_cout_sel_nxt = 1'd0; + end + else + alu_cout_sel_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if( type == REGOP ) + begin + if ( opcode == ADD || opcode == CMN ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == ADC ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == SUB || opcode == CMP ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == SBC ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == RSB ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == RSC ) + alu_out_sel_nxt = 4'd1; + else if ( opcode == AND || opcode == TST ) + alu_out_sel_nxt = 4'd8; + else if ( opcode == EOR || opcode == TEQ ) + alu_out_sel_nxt = 4'd6; + else if ( opcode == ORR ) + alu_out_sel_nxt = 4'd7; + else if ( opcode == BIC ) + alu_out_sel_nxt = 4'd8; + else + alu_out_sel_nxt = 4'd0; + end + else if ( mem_op ) + alu_out_sel_nxt = 4'd1; + else if ( type == BRANCH ) + alu_out_sel_nxt = 4'd1; + else if ( type == MTRANS ) + alu_out_sel_nxt = 4'd1; + else + alu_out_sel_nxt = 4'd0; + end + else + alu_out_sel_nxt = 4'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op && store_op ) + write_data_wen_nxt = 1'd1; + else if ( type == MTRANS && !instruction[20] ) + write_data_wen_nxt = 1'd1; + else + write_data_wen_nxt = 1'd0; + end + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute && !instruction[20] ) + write_data_wen_nxt = 1'd1; + else if ( control_state == MTRANS_EXEC2 && !instruction[20] ) + write_data_wen_nxt = 1'd1; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict ) + write_data_wen_nxt = 1'd1; + else + write_data_wen_nxt = 1'd0; + end + +always @* + begin + if(instruction_valid && !interrupt && !conflict && (type == CORTRANS && !und_request) && ! instruction[20]) + copro_write_data_wen_nxt = 1'd1; + else + copro_write_data_wen_nxt = 1'd0; + end + +always @* + begin + if(instruction_valid && !interrupt && !conflict && type == MTRANS) + base_address_wen_nxt = 1'd1; + else + base_address_wen_nxt = 1'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( mem_op &&(load_op && instruction[15:12] == 4'd15) ) + pc_wen_nxt = 1'd0; + else if ( type == MTRANS ) + begin + if ( mtrans_num_registers > 4'd1 ) + pc_wen_nxt = 1'd0; + else if ( instruction[20] && mtrans_reg1 == 4'd15 ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( type == MULT ) + pc_wen_nxt = 1'd0; + else if ( type == SWAP ) + pc_wen_nxt = 1'd0; + else if ( type == CORTRANS && !und_request ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( control_state == MEM_WAIT1 && !conflict && instruction_execute) + pc_wen_nxt = 1'd0; + else if ( control_state == MEM_WAIT2 && !dabt) + pc_wen_nxt = 1'd0; + else if ( control_state == MTRANS_EXEC1 && !conflict && instruction_execute ) + begin + if ( mtrans_num_registers != 4'd1 ) + pc_wen_nxt = 1'd0; + else if ( instruction[20] && mtrans_reg1 == 4'd15 ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( control_state == MTRANS_EXEC2 ) + begin + if ( mtrans_num_registers > 4'd1 ) + pc_wen_nxt = 1'd0; + else if ( instruction[20] && mtrans_reg1 == 4'd15 ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + else if ( control_state == MULT_PROC1 && instruction_execute && !conflict ) + pc_wen_nxt = 1'd0; + else if ( control_state == MULT_PROC2 ) + pc_wen_nxt = 1'd0; + else if ( control_state == MULT_ACCUMU ) + pc_wen_nxt = 1'd0; + else if ( control_state == SWAP_WRITE && instruction_execute && !conflict && instruction_execute) + pc_wen_nxt = 1'd0; + else if ( control_state == SWAP_WAIT1 &&instruction_execute ) + pc_wen_nxt = 1'd0; + else + pc_wen_nxt = 1'd1; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict ) + begin + if ( type == REGOP && !opcode_compare && instruction[15:12] != 4'd15) + //reg_bank_wen_nxt = decode (instruction[15:12]); + reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: + instruction[15:12] == 4'h1 ? 15'h0002: + instruction[15:12] == 4'h2 ? 15'h0004: + instruction[15:12] == 4'h3 ? 15'h0008: + instruction[15:12] == 4'h4 ? 15'h0010: + instruction[15:12] == 4'h5 ? 15'h0020: + instruction[15:12] == 4'h6 ? 15'h0040: + instruction[15:12] == 4'h7 ? 15'h0080: + instruction[15:12] == 4'h8 ? 15'h0100: + instruction[15:12] == 4'h9 ? 15'h0200: + instruction[15:12] == 4'ha ? 15'h0400: + instruction[15:12] == 4'hb ? 15'h0800: + instruction[15:12] == 4'hc ? 15'h1000: + instruction[15:12] == 4'hd ? 15'h2000: + instruction[15:12] == 4'he ? 15'h4000: + 15'h0000; + else if ( mem_op && ( mem_op_pre_indexed || mem_op_post_indexed ) && rn_sel_nxt != 4'd15) + // reg_bank_wen_nxt = decode ( rn_sel_nxt ); + reg_bank_wen_nxt = rn_sel_nxt == 4'h0 ? 15'h0001: + rn_sel_nxt == 4'h1 ? 15'h0002: + rn_sel_nxt == 4'h2 ? 15'h0004: + rn_sel_nxt == 4'h3 ? 15'h0008: + rn_sel_nxt == 4'h4 ? 15'h0010: + rn_sel_nxt == 4'h5 ? 15'h0020: + rn_sel_nxt == 4'h6 ? 15'h0040: + rn_sel_nxt == 4'h7 ? 15'h0080: + rn_sel_nxt == 4'h8 ? 15'h0100: + rn_sel_nxt == 4'h9 ? 15'h0200: + rn_sel_nxt == 4'ha ? 15'h0400: + rn_sel_nxt == 4'hb ? 15'h0800: + rn_sel_nxt == 4'hc ? 15'h1000: + rn_sel_nxt == 4'hd ? 15'h2000: + rn_sel_nxt == 4'he ? 15'h4000: + 15'h0000; + else if ( type == BRANCH && instruction[24]) + //reg_bank_wen_nxt = decode (4'd14); + reg_bank_wen_nxt = 15'h4000; + else if ( type == MTRANS && instruction[21] ) + //reg_bank_wen_nxt = decode (rn_sel_nxt); + reg_bank_wen_nxt = rn_sel_nxt == 4'h0 ? 15'h0001: + rn_sel_nxt == 4'h1 ? 15'h0002: + rn_sel_nxt == 4'h2 ? 15'h0004: + rn_sel_nxt == 4'h3 ? 15'h0008: + rn_sel_nxt == 4'h4 ? 15'h0010: + rn_sel_nxt == 4'h5 ? 15'h0020: + rn_sel_nxt == 4'h6 ? 15'h0040: + rn_sel_nxt == 4'h7 ? 15'h0080: + rn_sel_nxt == 4'h8 ? 15'h0100: + rn_sel_nxt == 4'h9 ? 15'h0200: + rn_sel_nxt == 4'ha ? 15'h0400: + rn_sel_nxt == 4'hb ? 15'h0800: + rn_sel_nxt == 4'hc ? 15'h1000: + rn_sel_nxt == 4'hd ? 15'h2000: + rn_sel_nxt == 4'he ? 15'h4000: + 15'h0000; + else if ( type == SWI || und_request ) + //reg_bank_wen_nxt = decode (4'd14); + reg_bank_wen_nxt = 15'h4000; + else + reg_bank_wen_nxt = 15'h0; + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + //reg_bank_wen_nxt = decode (4'd14); + reg_bank_wen_nxt = 15'h4000; + else if ( control_state == MTRANS_ABORT && restore_base_address) + //reg_bank_wen_nxt = decode ( instruction[19:16] ); + reg_bank_wen_nxt = instruction[19:16] == 4'h0 ? 15'h0001: + instruction[19:16] == 4'h1 ? 15'h0002: + instruction[19:16] == 4'h2 ? 15'h0004: + instruction[19:16] == 4'h3 ? 15'h0008: + instruction[19:16] == 4'h4 ? 15'h0010: + instruction[19:16] == 4'h5 ? 15'h0020: + instruction[19:16] == 4'h6 ? 15'h0040: + instruction[19:16] == 4'h7 ? 15'h0080: + instruction[19:16] == 4'h8 ? 15'h0100: + instruction[19:16] == 4'h9 ? 15'h0200: + instruction[19:16] == 4'ha ? 15'h0400: + instruction[19:16] == 4'hb ? 15'h0800: + instruction[19:16] == 4'hc ? 15'h1000: + instruction[19:16] == 4'hd ? 15'h2000: + instruction[19:16] == 4'he ? 15'h4000: + 15'h0000; + else if ( control_state == MULT_STORE ) + begin + if ( type == MULT ) + //reg_bank_wen_nxt = decode ( instruction[19:16] ); + reg_bank_wen_nxt = instruction[19:16] == 4'h0 ? 15'h0001: + instruction[19:16] == 4'h1 ? 15'h0002: + instruction[19:16] == 4'h2 ? 15'h0004: + instruction[19:16] == 4'h3 ? 15'h0008: + instruction[19:16] == 4'h4 ? 15'h0010: + instruction[19:16] == 4'h5 ? 15'h0020: + instruction[19:16] == 4'h6 ? 15'h0040: + instruction[19:16] == 4'h7 ? 15'h0080: + instruction[19:16] == 4'h8 ? 15'h0100: + instruction[19:16] == 4'h9 ? 15'h0200: + instruction[19:16] == 4'ha ? 15'h0400: + instruction[19:16] == 4'hb ? 15'h0800: + instruction[19:16] == 4'hc ? 15'h1000: + instruction[19:16] == 4'hd ? 15'h2000: + instruction[19:16] == 4'he ? 15'h4000: + 15'h0000; + else + //reg_bank_wen_nxt = decode (instruction[15:12]); + reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: + instruction[15:12] == 4'h1 ? 15'h0002: + instruction[15:12] == 4'h2 ? 15'h0004: + instruction[15:12] == 4'h3 ? 15'h0008: + instruction[15:12] == 4'h4 ? 15'h0010: + instruction[15:12] == 4'h5 ? 15'h0020: + instruction[15:12] == 4'h6 ? 15'h0040: + instruction[15:12] == 4'h7 ? 15'h0080: + instruction[15:12] == 4'h8 ? 15'h0100: + instruction[15:12] == 4'h9 ? 15'h0200: + instruction[15:12] == 4'ha ? 15'h0400: + instruction[15:12] == 4'hb ? 15'h0800: + instruction[15:12] == 4'hc ? 15'h1000: + instruction[15:12] == 4'hd ? 15'h2000: + instruction[15:12] == 4'he ? 15'h4000: + 15'h0000; + end + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] && instruction[15:12] != 4'd15) + //reg_bank_wen_nxt = decode (instruction[15:12]); + reg_bank_wen_nxt = instruction[15:12] == 4'h0 ? 15'h0001: + instruction[15:12] == 4'h1 ? 15'h0002: + instruction[15:12] == 4'h2 ? 15'h0004: + instruction[15:12] == 4'h3 ? 15'h0008: + instruction[15:12] == 4'h4 ? 15'h0010: + instruction[15:12] == 4'h5 ? 15'h0020: + instruction[15:12] == 4'h6 ? 15'h0040: + instruction[15:12] == 4'h7 ? 15'h0080: + instruction[15:12] == 4'h8 ? 15'h0100: + instruction[15:12] == 4'h9 ? 15'h0200: + instruction[15:12] == 4'ha ? 15'h0400: + instruction[15:12] == 4'hb ? 15'h0800: + instruction[15:12] == 4'hc ? 15'h1000: + instruction[15:12] == 4'hd ? 15'h2000: + instruction[15:12] == 4'he ? 15'h4000: + 15'h0000; + else + reg_bank_wen_nxt = 15'd0; + end + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && regop_set_flags) + status_bits_flags_wen_nxt = 1'd1; + else if ( control_state == MULT_STORE && instruction[20]) + status_bits_flags_wen_nxt = 1'd1; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] && instruction[15:12] == 4'd15) + status_bits_flags_wen_nxt = 1'd1; + else + status_bits_flags_wen_nxt = 1'd0; + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict) + begin + if ( type == SWI || und_request ) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + else if ( regop_set_flags && instruction[15:12] == 4'd15 && (i_execute_status_bits[1:0] != USR) ) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + else + begin + status_bits_mode_wen_nxt = 1'd0; + status_bits_irq_mask_wen_nxt = 1'd0; + end + end + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 ) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] + && instruction[15:12] == 4'd15 && i_execute_status_bits[1:0] != USR) + begin + status_bits_mode_wen_nxt = 1'd1; + status_bits_irq_mask_wen_nxt = 1'd1; + end + else + begin + status_bits_mode_wen_nxt = 1'd0; + status_bits_irq_mask_wen_nxt = 1'd0; + end + end + + +always @* + begin + if ( instruction_valid && !interrupt && !conflict && regop_set_flags + && instruction[15:12] == 4'd15 && i_execute_status_bits[1:0] != USR) + status_bits_firq_mask_wen_nxt = 1'd1; + else if ( instruction_valid && interrupt && next_interrupt != 3'd6 && next_interrupt == 3'd2 ) + status_bits_firq_mask_wen_nxt = 1'd1; + else if ( control_state == COPRO_WAIT && instruction_execute && !conflict && instruction[20] + && instruction[15:12] == 4'd15 && i_execute_status_bits[1:0] != USR) + status_bits_firq_mask_wen_nxt = 1'd1; + else + status_bits_firq_mask_wen_nxt = 1'd0; + end + + + +// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq +// This pre-encodes the firq_s3 signal thats used in u_register_bank +// assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ; + +assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ; + + +// ======================================================== +// Next State Logic +// ======================================================== + +// this replicates the current value of the execute signal in the execute stage +//assign instruction_execute = conditional_execute ( o_condition, i_execute_status_bits[31:28] ); +assign instruction_execute = ( o_condition == AL ) || + ( o_condition == EQ && i_execute_status_bits[30] ) || + ( o_condition == NE && !i_execute_status_bits[30] ) || + ( o_condition == CS && i_execute_status_bits[29] ) || + ( o_condition == CC && !i_execute_status_bits[29] ) || + ( o_condition == MI && i_execute_status_bits[31] ) || + ( o_condition == PL && !i_execute_status_bits[31] ) || + ( o_condition == VS && i_execute_status_bits[28] ) || + ( o_condition == VC && !i_execute_status_bits[28] ) || + ( o_condition == HI && i_execute_status_bits[29] && !i_execute_status_bits[30] ) || + ( o_condition == LS && (!i_execute_status_bits[29] || i_execute_status_bits[30]) ) || + + ( o_condition == GE && i_execute_status_bits[31] == i_execute_status_bits[28] ) || + ( o_condition == LT && i_execute_status_bits[31] != i_execute_status_bits[28] ) || + + ( o_condition == GT && !i_execute_status_bits[30] && i_execute_status_bits[31] == i_execute_status_bits[28] ) || + ( o_condition == LE && (i_execute_status_bits[30] || i_execute_status_bits[31] != i_execute_status_bits[28]) ) ; + + +// First state of executing a new instruction +// Its complex because of conditional execution of multi-cycle instructions +assign instruction_valid = ((control_state == EXECUTE || control_state == PRE_FETCH_EXEC) || + // when last instruction was multi-cycle instruction but did not execute + // because condition was false then act like you're in the execute state + (!instruction_execute && (control_state == PC_STALL1 || + control_state == MEM_WAIT1 || + control_state == COPRO_WAIT || + control_state == SWAP_WRITE || + control_state == MULT_PROC1 || + control_state == MTRANS_EXEC1 ) )); + + + +always @* + begin + // default is to hold the current state +// control_state_nxt <= control_state; + + // Note: The order is important here + + if ( instruction_valid ) + begin + + if ( interrupt && !conflict ) + control_state_nxt = INT_WAIT1; + else + begin + if ( type == MTRANS && instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC + control_state_nxt = MEM_WAIT1; + + else if ( type == MTRANS && !conflict && mtrans_num_registers != 5'd0 && mtrans_num_registers != 5'd1 ) + control_state_nxt = MTRANS_EXEC1; + + else if ( type == MULT && !conflict ) + control_state_nxt = MULT_PROC1; + + else if ( type == SWAP && !conflict ) + control_state_nxt = SWAP_WRITE; + + else if ( type == CORTRANS && !und_request && !conflict ) + control_state_nxt = COPRO_WAIT; + else + begin + if ( load_op && instruction[15:12] == 4'd15 ) + control_state_nxt = MEM_WAIT1; + else + begin + if( current_write_pc ) + control_state_nxt = PC_STALL1; + else + control_state_nxt = EXECUTE; + end + end + end + + end + + else + begin + if ( control_state == RST_WAIT1 ) control_state_nxt = RST_WAIT2; + else if ( control_state == RST_WAIT2 ) control_state_nxt = EXECUTE; + else if ( control_state == INT_WAIT1 ) control_state_nxt = INT_WAIT2; + else if ( control_state == INT_WAIT2 ) control_state_nxt = EXECUTE; + else if ( control_state == COPRO_WAIT ) control_state_nxt = PRE_FETCH_EXEC; + else if ( control_state == PC_STALL1 ) control_state_nxt = PC_STALL2; + else if ( control_state == PC_STALL2 ) control_state_nxt = EXECUTE; + else if ( control_state == SWAP_WRITE ) control_state_nxt = SWAP_WAIT1; + else if ( control_state == SWAP_WAIT1 ) control_state_nxt = SWAP_WAIT2; + else if ( control_state == MULT_STORE ) control_state_nxt = PRE_FETCH_EXEC; + else if ( control_state == MTRANS_ABORT ) control_state_nxt = PRE_FETCH_EXEC; + + else if ( control_state == MEM_WAIT1 ) control_state_nxt = MEM_WAIT2; + + else if ( control_state == MEM_WAIT2 || control_state == SWAP_WAIT2 ) + begin + if ( write_pc ) // writing to the PC!! + control_state_nxt = PC_STALL1; + else + control_state_nxt = PRE_FETCH_EXEC; + end + + else if ( control_state == MTRANS_EXEC1 ) + begin + if ( mtrans_instruction_nxt[15:0] != 16'd0 ) + control_state_nxt = MTRANS_EXEC2; + else // if the register list holds a single register + begin + if ( dabt ) // data abort + control_state_nxt = MTRANS_ABORT; + else if ( write_pc ) // writing to the PC!! + control_state_nxt = MEM_WAIT1; + else + control_state_nxt = PRE_FETCH_EXEC; + end + + end + + // Stay in State MTRANS_EXEC2 until the full list of registers to + // load or store has been processed + + else if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5'd1 ) + begin + if ( dabt ) // data abort + control_state_nxt = MTRANS_ABORT; + else if ( write_pc ) // writing to the PC!! + control_state_nxt = MEM_WAIT1; + else + control_state_nxt = PRE_FETCH_EXEC; + end + + + else if ( control_state == MULT_PROC1 ) + begin + if (!instruction_execute) + control_state_nxt = PRE_FETCH_EXEC; + else + control_state_nxt = MULT_PROC2; + end + + else if ( control_state == MULT_PROC2 ) + begin + if ( i_multiply_done ) + begin + if ( o_multiply_function[1] ) // Accumulate ? + control_state_nxt = MULT_ACCUMU; + else + control_state_nxt = MULT_STORE; + end + else + control_state_nxt = control_state; + end + + + else if ( control_state == MULT_ACCUMU ) + begin + control_state_nxt = MULT_STORE; + end + + + else //jing + control_state_nxt = control_state; + end + + end + + +assign i_fetch = {i_fetch_instruction[27:20], i_fetch_instruction[7:4]}; //jing +// ======================================================== +// Register Update +// ======================================================== +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + if (!conflict) + begin + fetch_instruction_r <= i_fetch_instruction; +// fetch_instruction_type_r <= instruction_type(i_fetch_instruction); + + fetch_instruction_type_r <= + ( +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]}[11:6] == 12'b00010?001001 ? SWAP: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b000000??1001 ? MULT: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]}[11:10] = 12'b00?????????? ? REGOP: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b01?????????? ? TRANS: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b100????????? ? MTRANS: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b101????????? ? BRANCH: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b110????????? ? CODTRANS: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b1110???????0 ? COREGOP: +// {i_fetch_instruction[27:20], i_fetch_instruction[7:4]} = 12'b1110???????1 ? CORTRANS: +// SWI + + (i_fetch[11:7] == 5'b00010 && i_fetch[5:0] == 6'b001001)? SWAP: + (i_fetch[11:6] == 6'b000000 && i_fetch[3:0] == 4'b1001 )? MULT: + i_fetch[11:10] == 2'b00 ? REGOP: + i_fetch[11:10] == 2'b01 ? TRANS: + i_fetch[11:9] == 3'b100 ? MTRANS: + i_fetch[11:9] == 3'b101 ? BRANCH: + i_fetch[11:9] == 3'b110 ? CODTRANS: + (i_fetch[11:8] == 4'b1110 && i_fetch[0] == 1'b0 )? COREGOP: + (i_fetch[11:8] == 4'b1110 && i_fetch[0] == 1'b1 )? CORTRANS: + SWI); + + fetch_address_r <= i_execute_iaddress; + iabt_reg <= i_iabt; + adex_reg <= i_adex; + abt_status_reg <= i_abt_status; + end + + o_status_bits_mode <= status_bits_mode_nxt; + o_status_bits_irq_mask <= status_bits_irq_mask_nxt; + o_status_bits_firq_mask <= status_bits_firq_mask_nxt; + o_imm32 <= imm32_nxt; + o_imm_shift_amount <= imm_shift_amount_nxt; + o_shift_imm_zero <= shift_imm_zero_nxt; + + // when have an interrupt, execute the interrupt operation + // unconditionally in the execute stage + // ensures that status_bits register gets updated correctly + // Likewise when in middle of multi-cycle instructions + // execute them unconditionally + o_condition <= instruction_valid && !interrupt ? condition_nxt : AL; + o_decode_exclusive <= decode_exclusive_nxt; + o_decode_iaccess <= decode_iaccess_nxt; + o_decode_daccess <= decode_daccess_nxt; + + o_rm_sel <= rm_sel_nxt; + o_rs_sel <= rs_sel_nxt; + o_load_rd <= load_rd_nxt; + load_rd_d1 <= load_rd_d1_nxt; + load_pc_r <= load_pc_nxt; + o_rn_sel <= rn_sel_nxt; + o_barrel_shift_amount_sel <= barrel_shift_amount_sel_nxt; + o_barrel_shift_data_sel <= barrel_shift_data_sel_nxt; + o_barrel_shift_function <= barrel_shift_function_nxt; + o_alu_function <= alu_function_nxt; + o_multiply_function <= multiply_function_nxt; + o_interrupt_vector_sel <= next_interrupt; + o_iaddress_sel <= iaddress_sel_nxt; + o_daddress_sel <= daddress_sel_nxt; + o_pc_sel <= pc_sel_nxt; + o_byte_enable_sel <= byte_enable_sel_nxt; + o_status_bits_sel <= status_bits_sel_nxt; + o_reg_write_sel <= reg_write_sel_nxt; + o_firq_not_user_mode <= firq_not_user_mode_nxt; + o_write_data_wen <= write_data_wen_nxt; + o_base_address_wen <= base_address_wen_nxt; + o_pc_wen <= pc_wen_nxt; + o_reg_bank_wen <= reg_bank_wen_nxt; + o_status_bits_flags_wen <= status_bits_flags_wen_nxt; + o_status_bits_mode_wen <= status_bits_mode_wen_nxt; + o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt; + o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt; + + o_copro_opcode1 <= instruction[23:21]; + o_copro_opcode2 <= instruction[7:5]; + o_copro_crn <= instruction[19:16]; + o_copro_crm <= instruction[3:0]; + o_copro_num <= instruction[11:8]; + o_copro_operation <= copro_operation_nxt; + o_copro_write_data_wen <= copro_write_data_wen_nxt; + restore_base_address <= restore_base_address_nxt; + control_state <= control_state_nxt; + end + + + +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + // sometimes this is a pre-fetch instruction + // e.g. two ldr instructions in a row. The second ldr will be saved + // to the pre-fetch instruction register + // then when its decoded, a copy is saved to the saved_current_instruction + // register + if ( type == MTRANS ) + begin + saved_current_instruction <= mtrans_instruction_nxt; + saved_current_instruction_type <= type; + saved_current_instruction_iabt <= instruction_iabt; + saved_current_instruction_adex <= instruction_adex; + saved_current_instruction_address <= instruction_address; + saved_current_instruction_iabt_status <= instruction_iabt_status; + end + else if ( saved_current_instruction_wen ) + begin + saved_current_instruction <= instruction; + saved_current_instruction_type <= type; + saved_current_instruction_iabt <= instruction_iabt; + saved_current_instruction_adex <= instruction_adex; + saved_current_instruction_address <= instruction_address; + saved_current_instruction_iabt_status <= instruction_iabt_status; + end + + if ( pre_fetch_instruction_wen ) + begin + pre_fetch_instruction <= fetch_instruction_r; + pre_fetch_instruction_type <= fetch_instruction_type_r; + pre_fetch_instruction_iabt <= iabt_reg; + pre_fetch_instruction_adex <= adex_reg; + pre_fetch_instruction_address <= fetch_address_r; + pre_fetch_instruction_iabt_status <= abt_status_reg; + end + + + // TODO possible to use saved_current_instruction instead and save some regs? + hold_instruction <= instruction; + hold_instruction_type <= type; + hold_instruction_iabt <= instruction_iabt; + hold_instruction_adex <= instruction_adex; + hold_instruction_address <= instruction_address; + hold_instruction_iabt_status <= instruction_iabt_status; + end + + + +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + irq <= i_irq; + firq <= i_firq; + + if ( control_state == INT_WAIT1 && o_status_bits_mode == SVC ) + begin + dabt_reg <= 1'd0; + end + else + begin + dabt_reg <= dabt_reg || i_dabt; + end + + dabt_reg_d1 <= dabt_reg; + end + +assign dabt = dabt_reg || i_dabt; + + +// ======================================================== +// Decompiler for debugging core - not synthesizable +// ======================================================== +//synopsys translate_off + +//`include "a25/debug_functions.v" + +/*a25_decompile u_decompile ( + .i_clk ( i_clk ), + .i_core_stall ( i_core_stall ), + .i_instruction ( instruction ), + .i_instruction_valid ( instruction_valid &&!conflict ), + .i_instruction_execute ( instruction_execute ), + .i_instruction_address ( instruction_address ), + .i_interrupt ( {3{interrupt}} & next_interrupt ), + .i_interrupt_state ( control_state == INT_WAIT2 ), + .i_instruction_undefined ( und_request ), + .i_pc_sel ( o_pc_sel ), + .i_pc_wen ( o_pc_wen ) +); +*/ + +wire [(15*8)-1:0] xCONTROL_STATE; +wire [(15*8)-1:0] xMODE; +wire [( 8*8)-1:0] xTYPE; + +assign xCONTROL_STATE = + control_state == RST_WAIT1 ? "RST_WAIT1" : + control_state == RST_WAIT2 ? "RST_WAIT2" : + + + control_state == INT_WAIT1 ? "INT_WAIT1" : + control_state == INT_WAIT2 ? "INT_WAIT2" : + control_state == EXECUTE ? "EXECUTE" : + control_state == PRE_FETCH_EXEC ? "PRE_FETCH_EXEC" : + control_state == MEM_WAIT1 ? "MEM_WAIT1" : + control_state == MEM_WAIT2 ? "MEM_WAIT2" : + control_state == PC_STALL1 ? "PC_STALL1" : + control_state == PC_STALL2 ? "PC_STALL2" : + control_state == MTRANS_EXEC1 ? "MTRANS_EXEC1" : + control_state == MTRANS_EXEC2 ? "MTRANS_EXEC2" : + control_state == MTRANS_ABORT ? "MTRANS_ABORT" : + control_state == MULT_PROC1 ? "MULT_PROC1" : + control_state == MULT_PROC2 ? "MULT_PROC2" : + control_state == MULT_STORE ? "MULT_STORE" : + control_state == MULT_ACCUMU ? "MULT_ACCUMU" : + control_state == SWAP_WRITE ? "SWAP_WRITE" : + control_state == SWAP_WAIT1 ? "SWAP_WAIT1" : + control_state == SWAP_WAIT2 ? "SWAP_WAIT2" : + "COPRO_WAIT" ; + +//assign xMODE = mode_name ( o_status_bits_mode ); + +//assign xMODE = o_status_bits_mode == USR ? "User " : +// o_status_bits_mode == SVC ? "Supervisor " : +// o_status_bits_mode == IRQ ? "Interrupt " : +// "Fast_Interrupt" ; + +assign xTYPE = + type == REGOP ? "REGOP" : + type == MULT ? "MULT" : + type == SWAP ? "SWAP" : + type == TRANS ? "TRANS" : + type == MTRANS ? "MTRANS" : + type == BRANCH ? "BRANCH" : + type == CODTRANS ? "CODTRANS" : + type == COREGOP ? "COREGOP" : + type == CORTRANS ? "CORTRANS" : + "SWI" ; + + +/*always @( posedge i_clk ) + if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx))) + begin + `TB_ERROR_MESSAGE + $display("Instruction with x's =%08h", instruction); + end +*/ +//synopsys translate_on + +endmodule + + + +module a25_shifter_quick +( + +i_in, +i_carry_in, +i_shift_amount, +i_shift_imm_zero, +i_function, + +o_out, +o_carry_out + +); + +input [31:0] i_in; +input i_carry_in; +input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant +input i_shift_imm_zero; // high when immediate shift value of zero selected +input [1:0] i_function; + +output [31:0] o_out; +output o_carry_out; + +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + + // MSB is carry out +wire [32:0] lsl_out; +wire [32:0] lsr_out; +wire [32:0] asr_out; +wire [32:0] ror_out; + + +// Logical shift right zero is redundant as it is the same as logical shift left zero, so +// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow +// lsr #32 to be specified. + +// lsl #0 is a special case, where the shifter carry out is the old value of the status flags +// C flag. The contents of Rm are used directly as the second operand. + + // only gives the correct result if the shift value is < 4 + assign lsl_out = i_shift_imm_zero ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 2'd1 ? {i_in[31], i_in[30: 0], 1'd0} : + i_shift_amount == 2'd2 ? {i_in[30], i_in[29: 0], 2'd0} : + {i_in[29], i_in[28: 0], 3'd0} ; // 3 + +// The form of the shift field which might be expected to correspond to LSR #0 is used +// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. + + // only gives the correct result if the shift value is < 4 + assign lsr_out = i_shift_imm_zero ? {i_in[31], 32'd0 } : + i_shift_amount[1:0] == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount[1:0] == 2'd1 ? {i_in[ 0], 1'd0, i_in[31: 1]} : + i_shift_amount[1:0] == 2'd2 ? {i_in[ 1], 2'd0, i_in[31: 2]} : + {i_in[ 2], 3'd0, i_in[31: 3]} ; // 3 + +// The form of the shift field which might be expected to give ASR #0 is used to encode +// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is +// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to +// the value of bit 31 of Rm. + + // only gives the correct result if the shift value is < 4 + assign asr_out = i_shift_imm_zero ? {i_in[31], {32{i_in[31]}} } : + i_shift_amount[1:0] == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount[1:0] == 2'd1 ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} : + i_shift_amount[1:0] == 2'd2 ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} : + {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} ; // 3 + + // only gives the correct result if the shift value is < 4 + assign ror_out = i_shift_imm_zero ? {i_in[ 0], i_carry_in, i_in[31: 1]} : // RXR, (ROR w/ imm 0) + i_shift_amount[1:0] == 2'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount[1:0] == 2'd1 ? {i_in[ 0], i_in[ 0], i_in[31: 1]} : + i_shift_amount[1:0] == 2'd2 ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} : + {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} ; // 3 + +assign {o_carry_out, o_out} = i_function == LSL ? lsl_out : + i_function == LSR ? lsr_out : + i_function == ASR ? asr_out : + ror_out ; + +endmodule + + + +module a25_shifter_full +( + +i_in, +i_carry_in, +i_shift_amount, +i_shift_imm_zero, +i_function, + +o_out, +o_carry_out + +); + +input [31:0] i_in; +input i_carry_in; +input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant +input i_shift_imm_zero; // high when immediate shift value of zero selected +input [1:0] i_function; + +output [31:0] o_out; +output o_carry_out; + +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + + + // MSB is carry out +wire [32:0] lsl_out; +wire [32:0] lsr_out; +wire [32:0] asr_out; +wire [32:0] ror_out; + + +// Logical shift right zero is redundant as it is the same as logical shift left zero, so +// the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow +// lsr #32 to be specified. + +// lsl #0 is a special case, where the shifter carry out is the old value of the status flags +// C flag. The contents of Rm are used directly as the second operand. + + assign lsl_out = i_shift_imm_zero ? {i_carry_in, i_in } : // fall through case + + i_shift_amount == 8'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 8'd1 ? {i_in[31], i_in[30: 0], 1'd0} : + i_shift_amount == 8'd2 ? {i_in[30], i_in[29: 0], 2'd0} : + i_shift_amount == 8'd3 ? {i_in[29], i_in[28: 0], 3'd0} : + i_shift_amount == 8'd4 ? {i_in[28], i_in[27: 0], 4'd0} : + i_shift_amount == 8'd5 ? {i_in[27], i_in[26: 0], 5'd0} : + i_shift_amount == 8'd6 ? {i_in[26], i_in[25: 0], 6'd0} : + i_shift_amount == 8'd7 ? {i_in[25], i_in[24: 0], 7'd0} : + i_shift_amount == 8'd8 ? {i_in[24], i_in[23: 0], 8'd0} : + i_shift_amount == 8'd9 ? {i_in[23], i_in[22: 0], 9'd0} : + i_shift_amount == 8'd10 ? {i_in[22], i_in[21: 0], 10'd0} : + i_shift_amount == 8'd11 ? {i_in[21], i_in[20: 0], 11'd0} : + + i_shift_amount == 8'd12 ? {i_in[20], i_in[19: 0], 12'd0} : + i_shift_amount == 8'd13 ? {i_in[19], i_in[18: 0], 13'd0} : + i_shift_amount == 8'd14 ? {i_in[18], i_in[17: 0], 14'd0} : + i_shift_amount == 8'd15 ? {i_in[17], i_in[16: 0], 15'd0} : + i_shift_amount == 8'd16 ? {i_in[16], i_in[15: 0], 16'd0} : + i_shift_amount == 8'd17 ? {i_in[15], i_in[14: 0], 17'd0} : + i_shift_amount == 8'd18 ? {i_in[14], i_in[13: 0], 18'd0} : + i_shift_amount == 8'd19 ? {i_in[13], i_in[12: 0], 19'd0} : + i_shift_amount == 8'd20 ? {i_in[12], i_in[11: 0], 20'd0} : + i_shift_amount == 8'd21 ? {i_in[11], i_in[10: 0], 21'd0} : + + i_shift_amount == 8'd22 ? {i_in[10], i_in[ 9: 0], 22'd0} : + i_shift_amount == 8'd23 ? {i_in[ 9], i_in[ 8: 0], 23'd0} : + i_shift_amount == 8'd24 ? {i_in[ 8], i_in[ 7: 0], 24'd0} : + i_shift_amount == 8'd25 ? {i_in[ 7], i_in[ 6: 0], 25'd0} : + i_shift_amount == 8'd26 ? {i_in[ 6], i_in[ 5: 0], 26'd0} : + i_shift_amount == 8'd27 ? {i_in[ 5], i_in[ 4: 0], 27'd0} : + i_shift_amount == 8'd28 ? {i_in[ 4], i_in[ 3: 0], 28'd0} : + i_shift_amount == 8'd29 ? {i_in[ 3], i_in[ 2: 0], 29'd0} : + i_shift_amount == 8'd30 ? {i_in[ 2], i_in[ 1: 0], 30'd0} : + i_shift_amount == 8'd31 ? {i_in[ 1], i_in[ 0: 0], 31'd0} : + i_shift_amount == 8'd32 ? {i_in[ 0], 32'd0 } : // 32 + {1'd0, 32'd0 } ; // > 32 + + +// The form of the shift field which might be expected to correspond to LSR #0 is used +// to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output. + + // carry out, < -------- out ----------> + assign lsr_out = i_shift_imm_zero ? {i_in[31], 32'd0 } : + i_shift_amount == 8'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 8'd1 ? {i_in[ 0], 1'd0, i_in[31: 1]} : + i_shift_amount == 8'd2 ? {i_in[ 1], 2'd0, i_in[31: 2]} : + i_shift_amount == 8'd3 ? {i_in[ 2], 3'd0, i_in[31: 3]} : + i_shift_amount == 8'd4 ? {i_in[ 3], 4'd0, i_in[31: 4]} : + i_shift_amount == 8'd5 ? {i_in[ 4], 5'd0, i_in[31: 5]} : + i_shift_amount == 8'd6 ? {i_in[ 5], 6'd0, i_in[31: 6]} : + i_shift_amount == 8'd7 ? {i_in[ 6], 7'd0, i_in[31: 7]} : + i_shift_amount == 8'd8 ? {i_in[ 7], 8'd0, i_in[31: 8]} : + i_shift_amount == 8'd9 ? {i_in[ 8], 9'd0, i_in[31: 9]} : + + i_shift_amount == 8'd10 ? {i_in[ 9], 10'd0, i_in[31:10]} : + i_shift_amount == 8'd11 ? {i_in[10], 11'd0, i_in[31:11]} : + i_shift_amount == 8'd12 ? {i_in[11], 12'd0, i_in[31:12]} : + i_shift_amount == 8'd13 ? {i_in[12], 13'd0, i_in[31:13]} : + i_shift_amount == 8'd14 ? {i_in[13], 14'd0, i_in[31:14]} : + i_shift_amount == 8'd15 ? {i_in[14], 15'd0, i_in[31:15]} : + i_shift_amount == 8'd16 ? {i_in[15], 16'd0, i_in[31:16]} : + i_shift_amount == 8'd17 ? {i_in[16], 17'd0, i_in[31:17]} : + i_shift_amount == 8'd18 ? {i_in[17], 18'd0, i_in[31:18]} : + i_shift_amount == 8'd19 ? {i_in[18], 19'd0, i_in[31:19]} : + + i_shift_amount == 8'd20 ? {i_in[19], 20'd0, i_in[31:20]} : + i_shift_amount == 8'd21 ? {i_in[20], 21'd0, i_in[31:21]} : + i_shift_amount == 8'd22 ? {i_in[21], 22'd0, i_in[31:22]} : + i_shift_amount == 8'd23 ? {i_in[22], 23'd0, i_in[31:23]} : + i_shift_amount == 8'd24 ? {i_in[23], 24'd0, i_in[31:24]} : + i_shift_amount == 8'd25 ? {i_in[24], 25'd0, i_in[31:25]} : + i_shift_amount == 8'd26 ? {i_in[25], 26'd0, i_in[31:26]} : + i_shift_amount == 8'd27 ? {i_in[26], 27'd0, i_in[31:27]} : + i_shift_amount == 8'd28 ? {i_in[27], 28'd0, i_in[31:28]} : + i_shift_amount == 8'd29 ? {i_in[28], 29'd0, i_in[31:29]} : + + i_shift_amount == 8'd30 ? {i_in[29], 30'd0, i_in[31:30]} : + i_shift_amount == 8'd31 ? {i_in[30], 31'd0, i_in[31 ]} : + i_shift_amount == 8'd32 ? {i_in[31], 32'd0 } : + {1'd0, 32'd0 } ; // > 32 + +// The form of the shift field which might be expected to give ASR #0 is used to encode +// ASR #32. Bit 31 of Rm is again used as the carry output, and each bit of operand 2 is +// also equal to bit 31 of Rm. The result is therefore all ones or all zeros, according to +// the value of bit 31 of Rm. + + // carry out, < -------- out ----------> + assign asr_out = i_shift_imm_zero ? {i_in[31], {32{i_in[31]}} } : + i_shift_amount == 8'd0 ? {i_carry_in, i_in } : // fall through case + i_shift_amount == 8'd1 ? {i_in[ 0], { 2{i_in[31]}}, i_in[30: 1]} : + i_shift_amount == 8'd2 ? {i_in[ 1], { 3{i_in[31]}}, i_in[30: 2]} : + i_shift_amount == 8'd3 ? {i_in[ 2], { 4{i_in[31]}}, i_in[30: 3]} : + i_shift_amount == 8'd4 ? {i_in[ 3], { 5{i_in[31]}}, i_in[30: 4]} : + i_shift_amount == 8'd5 ? {i_in[ 4], { 6{i_in[31]}}, i_in[30: 5]} : + i_shift_amount == 8'd6 ? {i_in[ 5], { 7{i_in[31]}}, i_in[30: 6]} : + i_shift_amount == 8'd7 ? {i_in[ 6], { 8{i_in[31]}}, i_in[30: 7]} : + i_shift_amount == 8'd8 ? {i_in[ 7], { 9{i_in[31]}}, i_in[30: 8]} : + i_shift_amount == 8'd9 ? {i_in[ 8], {10{i_in[31]}}, i_in[30: 9]} : + + i_shift_amount == 8'd10 ? {i_in[ 9], {11{i_in[31]}}, i_in[30:10]} : + i_shift_amount == 8'd11 ? {i_in[10], {12{i_in[31]}}, i_in[30:11]} : + i_shift_amount == 8'd12 ? {i_in[11], {13{i_in[31]}}, i_in[30:12]} : + i_shift_amount == 8'd13 ? {i_in[12], {14{i_in[31]}}, i_in[30:13]} : + i_shift_amount == 8'd14 ? {i_in[13], {15{i_in[31]}}, i_in[30:14]} : + i_shift_amount == 8'd15 ? {i_in[14], {16{i_in[31]}}, i_in[30:15]} : + i_shift_amount == 8'd16 ? {i_in[15], {17{i_in[31]}}, i_in[30:16]} : + i_shift_amount == 8'd17 ? {i_in[16], {18{i_in[31]}}, i_in[30:17]} : + i_shift_amount == 8'd18 ? {i_in[17], {19{i_in[31]}}, i_in[30:18]} : + i_shift_amount == 8'd19 ? {i_in[18], {20{i_in[31]}}, i_in[30:19]} : + + i_shift_amount == 8'd20 ? {i_in[19], {21{i_in[31]}}, i_in[30:20]} : + i_shift_amount == 8'd21 ? {i_in[20], {22{i_in[31]}}, i_in[30:21]} : + i_shift_amount == 8'd22 ? {i_in[21], {23{i_in[31]}}, i_in[30:22]} : + i_shift_amount == 8'd23 ? {i_in[22], {24{i_in[31]}}, i_in[30:23]} : + i_shift_amount == 8'd24 ? {i_in[23], {25{i_in[31]}}, i_in[30:24]} : + i_shift_amount == 8'd25 ? {i_in[24], {26{i_in[31]}}, i_in[30:25]} : + i_shift_amount == 8'd26 ? {i_in[25], {27{i_in[31]}}, i_in[30:26]} : + i_shift_amount == 8'd27 ? {i_in[26], {28{i_in[31]}}, i_in[30:27]} : + i_shift_amount == 8'd28 ? {i_in[27], {29{i_in[31]}}, i_in[30:28]} : + i_shift_amount == 8'd29 ? {i_in[28], {30{i_in[31]}}, i_in[30:29]} : + i_shift_amount == 8'd30 ? {i_in[29], {31{i_in[31]}}, i_in[30 ]} : + i_shift_amount == 8'd31 ? {i_in[30], {32{i_in[31]}} } : + {i_in[31], {32{i_in[31]}} } ; // >= 32 + + + // carry out, < ------- out ---------> + assign ror_out = i_shift_imm_zero ? {i_in[ 0], i_carry_in, i_in[31: 1]} : // RXR, (ROR w/ imm 0) + + i_shift_amount[7:0] == 8'd0 ? {i_carry_in, i_in } : // fall through case + + i_shift_amount[4:0] == 5'd0 ? {i_in[31], i_in } : // Rs > 31 + i_shift_amount[4:0] == 5'd1 ? {i_in[ 0], i_in[ 0], i_in[31: 1]} : + i_shift_amount[4:0] == 5'd2 ? {i_in[ 1], i_in[ 1: 0], i_in[31: 2]} : + i_shift_amount[4:0] == 5'd3 ? {i_in[ 2], i_in[ 2: 0], i_in[31: 3]} : + i_shift_amount[4:0] == 5'd4 ? {i_in[ 3], i_in[ 3: 0], i_in[31: 4]} : + i_shift_amount[4:0] == 5'd5 ? {i_in[ 4], i_in[ 4: 0], i_in[31: 5]} : + i_shift_amount[4:0] == 5'd6 ? {i_in[ 5], i_in[ 5: 0], i_in[31: 6]} : + i_shift_amount[4:0] == 5'd7 ? {i_in[ 6], i_in[ 6: 0], i_in[31: 7]} : + i_shift_amount[4:0] == 5'd8 ? {i_in[ 7], i_in[ 7: 0], i_in[31: 8]} : + i_shift_amount[4:0] == 5'd9 ? {i_in[ 8], i_in[ 8: 0], i_in[31: 9]} : + + i_shift_amount[4:0] == 5'd10 ? {i_in[ 9], i_in[ 9: 0], i_in[31:10]} : + i_shift_amount[4:0] == 5'd11 ? {i_in[10], i_in[10: 0], i_in[31:11]} : + i_shift_amount[4:0] == 5'd12 ? {i_in[11], i_in[11: 0], i_in[31:12]} : + i_shift_amount[4:0] == 5'd13 ? {i_in[12], i_in[12: 0], i_in[31:13]} : + i_shift_amount[4:0] == 5'd14 ? {i_in[13], i_in[13: 0], i_in[31:14]} : + i_shift_amount[4:0] == 5'd15 ? {i_in[14], i_in[14: 0], i_in[31:15]} : + i_shift_amount[4:0] == 5'd16 ? {i_in[15], i_in[15: 0], i_in[31:16]} : + i_shift_amount[4:0] == 5'd17 ? {i_in[16], i_in[16: 0], i_in[31:17]} : + i_shift_amount[4:0] == 5'd18 ? {i_in[17], i_in[17: 0], i_in[31:18]} : + i_shift_amount[4:0] == 5'd19 ? {i_in[18], i_in[18: 0], i_in[31:19]} : + + i_shift_amount[4:0] == 5'd20 ? {i_in[19], i_in[19: 0], i_in[31:20]} : + i_shift_amount[4:0] == 5'd21 ? {i_in[20], i_in[20: 0], i_in[31:21]} : + i_shift_amount[4:0] == 5'd22 ? {i_in[21], i_in[21: 0], i_in[31:22]} : + i_shift_amount[4:0] == 5'd23 ? {i_in[22], i_in[22: 0], i_in[31:23]} : + i_shift_amount[4:0] == 5'd24 ? {i_in[23], i_in[23: 0], i_in[31:24]} : + i_shift_amount[4:0] == 5'd25 ? {i_in[24], i_in[24: 0], i_in[31:25]} : + i_shift_amount[4:0] == 5'd26 ? {i_in[25], i_in[25: 0], i_in[31:26]} : + i_shift_amount[4:0] == 5'd27 ? {i_in[26], i_in[26: 0], i_in[31:27]} : + i_shift_amount[4:0] == 5'd28 ? {i_in[27], i_in[27: 0], i_in[31:28]} : + i_shift_amount[4:0] == 5'd29 ? {i_in[28], i_in[28: 0], i_in[31:29]} : + + i_shift_amount[4:0] == 5'd30 ? {i_in[29], i_in[29: 0], i_in[31:30]} : + {i_in[30], i_in[30: 0], i_in[31:31]} ; + +assign {o_carry_out, o_out} = i_function == LSL ? lsl_out : + i_function == LSR ? lsr_out : + i_function == ASR ? asr_out : + ror_out ; + +endmodule + + +module a25_barrel_shift ( + + i_clk, + i_in, + i_carry_in, + i_shift_amount, + i_shift_imm_zero, + i_function, + + o_out, + o_carry_out, + o_stall + +); + +/************************* IO Declarations *********************/ +input i_clk; +input [31:0] i_in; +input i_carry_in; +input [7:0] i_shift_amount; // uses 8 LSBs of Rs, or a 5 bit immediate constant +input i_shift_imm_zero; // high when immediate shift value of zero selected +input [1:0] i_function; + +output [31:0] o_out; +output o_carry_out; +output o_stall; + +/************************* IO Declarations *********************/ +wire [31:0] quick_out; +wire quick_carry_out; +wire [31:0] full_out; +wire full_carry_out; +reg [31:0] full_out_r = 32'd0; +reg full_carry_out_r = 1'd0; +reg use_quick_r = 1'd1; + + +assign o_stall = (|i_shift_amount[7:2]) & use_quick_r; +assign o_out = use_quick_r ? quick_out : full_out_r; +assign o_carry_out = use_quick_r ? quick_carry_out : full_carry_out_r; + + +// Capture the result from the full barrel shifter in case the +// quick shifter gives the wrong value +always @(posedge i_clk) + begin + full_out_r <= full_out; + full_carry_out_r <= full_carry_out; + use_quick_r <= !o_stall; + end + +// Full barrel shifter +a25_shifter_full u_shifter_full ( + .i_in ( i_in ), + .i_carry_in ( i_carry_in ), + .i_shift_amount ( i_shift_amount ), + .i_shift_imm_zero ( i_shift_imm_zero ), + .i_function ( i_function ), + .o_out ( full_out ), + .o_carry_out ( full_carry_out ) +); + + + +// Quick barrel shifter +a25_shifter_quick u_shifter_quick ( + .i_in ( i_in ), + .i_carry_in ( i_carry_in ), + .i_shift_amount ( i_shift_amount ), + .i_shift_imm_zero ( i_shift_imm_zero ), + .i_function ( i_function ), + .o_out ( quick_out ), + .o_carry_out ( quick_carry_out ) +); + +endmodule + + + + + +module a25_register_bank ( + + i_clk, + i_core_stall, + i_mem_stall, + + i_mode_idec, + + i_mode_exec, + + i_mode_rds_exec, + + i_firq_not_user_mode, + i_rm_sel, + i_rs_sel, + i_rn_sel, + + i_pc_wen, + i_reg_bank_wen, + + i_pc, + i_reg, + + i_wb_read_data, + i_wb_read_data_valid, + i_wb_read_data_rd, + i_wb_mode, + + i_status_bits_flags, + i_status_bits_irq_mask, + i_status_bits_firq_mask, + + o_rm, + o_rs, + o_rd, + o_rn, + o_pc + + ); + +//`include "a25/a25_localparams.v" +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + +//`include "a25/a25_functions.v" + +input i_clk; +input i_core_stall; +input i_mem_stall; + +input [1:0] i_mode_idec; // user, supervisor, irq_idec, firq_idec etc. + // Used for register writes +input [1:0] i_mode_exec; // 1 periods delayed from i_mode_idec + // Used for register reads +input [3:0] i_mode_rds_exec; // Use one-hot version specifically for rds, + // includes i_user_mode_regs_store +input i_firq_not_user_mode; +input [3:0] i_rm_sel; +input [3:0] i_rs_sel; +input [3:0] i_rn_sel; + +input i_pc_wen; +input [14:0] i_reg_bank_wen; + +input [23:0] i_pc; // program counter [25:2] +input [31:0] i_reg; + +input [31:0] i_wb_read_data; +input i_wb_read_data_valid; +input [3:0] i_wb_read_data_rd; +input [1:0] i_wb_mode; + +input [3:0] i_status_bits_flags; +input i_status_bits_irq_mask; +input i_status_bits_firq_mask; + +output [31:0] o_rm; +output [31:0] o_rs; +output [31:0] o_rd; +output [31:0] o_rn; +output [31:0] o_pc; + +reg [31:0] o_rs; // +reg [31:0] o_rd; // + +// User Mode Registers +reg [31:0] r0 = 32'hdeadbeef; +reg [31:0] r1 = 32'hdeadbeef; +reg [31:0] r2 = 32'hdeadbeef; +reg [31:0] r3 = 32'hdeadbeef; +reg [31:0] r4 = 32'hdeadbeef; +reg [31:0] r5 = 32'hdeadbeef; +reg [31:0] r6 = 32'hdeadbeef; +reg [31:0] r7 = 32'hdeadbeef; +reg [31:0] r8 = 32'hdeadbeef; +reg [31:0] r9 = 32'hdeadbeef; +reg [31:0] r10 = 32'hdeadbeef; +reg [31:0] r11 = 32'hdeadbeef; +reg [31:0] r12 = 32'hdeadbeef; +reg [31:0] r13 = 32'hdeadbeef; +reg [31:0] r14 = 32'hdeadbeef; +reg [23:0] r15 = 24'hc0ffee; + +wire [31:0] r0_out; +wire [31:0] r1_out; +wire [31:0] r2_out; +wire [31:0] r3_out; +wire [31:0] r4_out; +wire [31:0] r5_out; +wire [31:0] r6_out; +wire [31:0] r7_out; +wire [31:0] r8_out; +wire [31:0] r9_out; +wire [31:0] r10_out; +wire [31:0] r11_out; +wire [31:0] r12_out; +wire [31:0] r13_out; +wire [31:0] r14_out; +wire [31:0] r15_out_rm; +wire [31:0] r15_out_rm_nxt; +wire [31:0] r15_out_rn; + +wire [31:0] r8_rds; +wire [31:0] r9_rds; +wire [31:0] r10_rds; +wire [31:0] r11_rds; +wire [31:0] r12_rds; +wire [31:0] r13_rds; +wire [31:0] r14_rds; + +// Supervisor Mode Registers +reg [31:0] r13_svc = 32'hdeadbeef; +reg [31:0] r14_svc = 32'hdeadbeef; + +// Interrupt Mode Registers +reg [31:0] r13_irq = 32'hdeadbeef; +reg [31:0] r14_irq = 32'hdeadbeef; + +// Fast Interrupt Mode Registers +reg [31:0] r8_firq = 32'hdeadbeef; +reg [31:0] r9_firq = 32'hdeadbeef; +reg [31:0] r10_firq = 32'hdeadbeef; +reg [31:0] r11_firq = 32'hdeadbeef; +reg [31:0] r12_firq = 32'hdeadbeef; +reg [31:0] r13_firq = 32'hdeadbeef; +reg [31:0] r14_firq = 32'hdeadbeef; + +wire usr_exec; +wire svc_exec; +wire irq_exec; +wire firq_exec; + +wire usr_idec; +wire svc_idec; +wire irq_idec; +wire firq_idec; +wire [14:0] read_data_wen; +wire [14:0] reg_bank_wen_c; +wire pc_wen_c; +wire pc_dmem_wen; + +reg [14:0] decode; //jingjing + + + // Write Enables from execute stage +assign usr_idec = i_mode_idec == USR; +assign svc_idec = i_mode_idec == SVC; +assign irq_idec = i_mode_idec == IRQ; + +// pre-encoded in decode stage to speed up long path +assign firq_idec = i_firq_not_user_mode; + + // Read Enables from stage 1 (fetch) +assign usr_exec = i_mode_exec == USR; +assign svc_exec = i_mode_exec == SVC; +assign irq_exec = i_mode_exec == IRQ; +assign firq_exec = i_mode_exec == FIRQ; + +always @* +case(i_wb_read_data_rd) + 4'h0 : decode = 15'h0001 ; + 4'h1 : decode = 15'h0002 ; + 4'h2 : decode = 15'h0004 ; + 4'h3 : decode = 15'h0008 ; + 4'h4 : decode = 15'h0010 ; + 4'h5 : decode = 15'h0020 ; + 4'h6 : decode = 15'h0040 ; + 4'h7 : decode = 15'h0080 ; + 4'h8 : decode = 15'h0100 ; + 4'h9 : decode = 15'h0200 ; + 4'ha : decode = 15'h0400 ; + 4'hb : decode = 15'h0800 ; + 4'hc : decode = 15'h1000 ; + 4'hd : decode = 15'h2000 ; + 4'he : decode = 15'h4000 ; + default: decode = 15'h0000 ; +endcase + + +/* i_wb_read_data_rd == 4'h0 ? 15'h0001 : + i_wb_read_data_rd == 4'h1 ? 15'h0002 : + i_wb_read_data_rd == 4'h2 ? 15'h0004 : + i_wb_read_data_rd == 4'h3 ? 15'h0008 : + i_wb_read_data_rd == 4'h4 ? 15'h0010 : + i_wb_read_data_rd == 4'h5 ? 15'h0020 : + + i_wb_read_data_rd == 4'h6 ? 15'h0040 : + i_wb_read_data_rd == 4'h7 ? 15'h0080 : + i_wb_read_data_rd == 4'h8 ? 15'h0100 : + i_wb_read_data_rd == 4'h9 ? 15'h0200 : + i_wb_read_data_rd == 4'ha ? 15'h0400 : + i_wb_read_data_rd == 4'hb ? 15'h0800 : + i_wb_read_data_rd == 4'hc ? 15'h1000 : + i_wb_read_data_rd == 4'hd ? 15'h2000 : + i_wb_read_data_rd == 4'he ? 15'h4000 : + default: 15'h0000 ; +*/ +//& decode (i_wb_read_data_rd); +assign read_data_wen = {15{i_wb_read_data_valid & ~i_mem_stall}} + & decode; + + + +assign reg_bank_wen_c = {15{~i_core_stall}} & i_reg_bank_wen; +assign pc_wen_c = ~i_core_stall & i_pc_wen; +assign pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_read_data_rd == 4'd15; + + +// ======================================================== +// Register Update +// ======================================================== + + +always @ ( posedge i_clk ) + begin + // these registers are used in all modes + r0 <= reg_bank_wen_c[0 ] ? i_reg : read_data_wen[0 ] ? i_wb_read_data : r0; + r1 <= reg_bank_wen_c[1 ] ? i_reg : read_data_wen[1 ] ? i_wb_read_data : r1; + r2 <= reg_bank_wen_c[2 ] ? i_reg : read_data_wen[2 ] ? i_wb_read_data : r2; + r3 <= reg_bank_wen_c[3 ] ? i_reg : read_data_wen[3 ] ? i_wb_read_data : r3; + r4 <= reg_bank_wen_c[4 ] ? i_reg : read_data_wen[4 ] ? i_wb_read_data : r4; + r5 <= reg_bank_wen_c[5 ] ? i_reg : read_data_wen[5 ] ? i_wb_read_data : r5; + r6 <= reg_bank_wen_c[6 ] ? i_reg : read_data_wen[6 ] ? i_wb_read_data : r6; + r7 <= reg_bank_wen_c[7 ] ? i_reg : read_data_wen[7 ] ? i_wb_read_data : r7; + + // these registers are used in all modes, except fast irq + r8 <= reg_bank_wen_c[8 ] && !firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode != FIRQ ? i_wb_read_data : r8; + r9 <= reg_bank_wen_c[9 ] && !firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode != FIRQ ? i_wb_read_data : r9; + r10 <= reg_bank_wen_c[10] && !firq_idec ? i_reg : read_data_wen[10] && i_wb_mode != FIRQ ? i_wb_read_data : r10; + r11 <= reg_bank_wen_c[11] && !firq_idec ? i_reg : read_data_wen[11] && i_wb_mode != FIRQ ? i_wb_read_data : r11; + r12 <= reg_bank_wen_c[12] && !firq_idec ? i_reg : read_data_wen[12] && i_wb_mode != FIRQ ? i_wb_read_data : r12; + + // these registers are used in fast irq mode + r8_firq <= reg_bank_wen_c[8 ] && firq_idec ? i_reg : read_data_wen[8 ] && i_wb_mode == FIRQ ? i_wb_read_data : r8_firq; + r9_firq <= reg_bank_wen_c[9 ] && firq_idec ? i_reg : read_data_wen[9 ] && i_wb_mode == FIRQ ? i_wb_read_data : r9_firq; + r10_firq <= reg_bank_wen_c[10] && firq_idec ? i_reg : read_data_wen[10] && i_wb_mode == FIRQ ? i_wb_read_data : r10_firq; + r11_firq <= reg_bank_wen_c[11] && firq_idec ? i_reg : read_data_wen[11] && i_wb_mode == FIRQ ? i_wb_read_data : r11_firq; + r12_firq <= reg_bank_wen_c[12] && firq_idec ? i_reg : read_data_wen[12] && i_wb_mode == FIRQ ? i_wb_read_data : r12_firq; + + // these registers are used in user mode + r13 <= reg_bank_wen_c[13] && usr_idec ? i_reg : read_data_wen[13] && i_wb_mode == USR ? i_wb_read_data : r13; + r14 <= reg_bank_wen_c[14] && usr_idec ? i_reg : read_data_wen[14] && i_wb_mode == USR ? i_wb_read_data : r14; + + // these registers are used in supervisor mode + r13_svc <= reg_bank_wen_c[13] && svc_idec ? i_reg : read_data_wen[13] && i_wb_mode == SVC ? i_wb_read_data : r13_svc; + r14_svc <= reg_bank_wen_c[14] && svc_idec ? i_reg : read_data_wen[14] && i_wb_mode == SVC ? i_wb_read_data : r14_svc; + + // these registers are used in irq mode + r13_irq <= reg_bank_wen_c[13] && irq_idec ? i_reg : read_data_wen[13] && i_wb_mode == IRQ ? i_wb_read_data : r13_irq; + r14_irq <= (reg_bank_wen_c[14] && irq_idec) ? i_reg : read_data_wen[14] && i_wb_mode == IRQ ? i_wb_read_data : r14_irq; + + // these registers are used in fast irq mode + r13_firq <= reg_bank_wen_c[13] && firq_idec ? i_reg : read_data_wen[13] && i_wb_mode == FIRQ ? i_wb_read_data : r13_firq; + r14_firq <= reg_bank_wen_c[14] && firq_idec ? i_reg : read_data_wen[14] && i_wb_mode == FIRQ ? i_wb_read_data : r14_firq; + + // these registers are used in all modes + r15 <= pc_wen_c ? i_pc : pc_dmem_wen ? i_wb_read_data[25:2] : r15; + + end + + +// ======================================================== +// Register Read based on Mode +// ======================================================== +assign r0_out = r0; +assign r1_out = r1; +assign r2_out = r2; +assign r3_out = r3; +assign r4_out = r4; +assign r5_out = r5; +assign r6_out = r6; +assign r7_out = r7; + +assign r8_out = firq_exec ? r8_firq : r8; +assign r9_out = firq_exec ? r9_firq : r9; +assign r10_out = firq_exec ? r10_firq : r10; +assign r11_out = firq_exec ? r11_firq : r11; +assign r12_out = firq_exec ? r12_firq : r12; + +assign r13_out = usr_exec ? r13 : + svc_exec ? r13_svc : + irq_exec ? r13_irq : + r13_firq ; + +assign r14_out = usr_exec ? r14 : + svc_exec ? r14_svc : + irq_exec ? r14_irq : + r14_firq ; + + +assign r15_out_rm = { i_status_bits_flags, + i_status_bits_irq_mask, + i_status_bits_firq_mask, + r15, + i_mode_exec}; + +assign r15_out_rm_nxt = { i_status_bits_flags, + i_status_bits_irq_mask, + i_status_bits_firq_mask, + i_pc, + i_mode_exec}; + +assign r15_out_rn = {6'd0, r15, 2'd0}; + + +// rds outputs +assign r8_rds = i_mode_rds_exec[OH_FIRQ] ? r8_firq : r8; +assign r9_rds = i_mode_rds_exec[OH_FIRQ] ? r9_firq : r9; +assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10; +assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11; +assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12; + +assign r13_rds = i_mode_rds_exec[OH_USR] ? r13 : + i_mode_rds_exec[OH_SVC] ? r13_svc : + i_mode_rds_exec[OH_IRQ] ? r13_irq : + r13_firq ; + +assign r14_rds = i_mode_rds_exec[OH_USR] ? r14 : + i_mode_rds_exec[OH_SVC] ? r14_svc : + i_mode_rds_exec[OH_IRQ] ? r14_irq : + r14_firq ; + + +// ======================================================== +// Program Counter out +// ======================================================== +assign o_pc = r15_out_rn; + +// ======================================================== +// Rm Selector +// ======================================================== +assign o_rm = i_rm_sel == 4'd0 ? r0_out : + i_rm_sel == 4'd1 ? r1_out : + i_rm_sel == 4'd2 ? r2_out : + i_rm_sel == 4'd3 ? r3_out : + i_rm_sel == 4'd4 ? r4_out : + i_rm_sel == 4'd5 ? r5_out : + i_rm_sel == 4'd6 ? r6_out : + i_rm_sel == 4'd7 ? r7_out : + i_rm_sel == 4'd8 ? r8_out : + i_rm_sel == 4'd9 ? r9_out : + i_rm_sel == 4'd10 ? r10_out : + i_rm_sel == 4'd11 ? r11_out : + i_rm_sel == 4'd12 ? r12_out : + i_rm_sel == 4'd13 ? r13_out : + i_rm_sel == 4'd14 ? r14_out : + r15_out_rm ; + + +// ======================================================== +// Rds Selector +// ======================================================== +always @* + case ( i_rs_sel ) + 4'd0 : o_rs = r0_out ; + 4'd1 : o_rs = r1_out ; + 4'd2 : o_rs = r2_out ; + 4'd3 : o_rs = r3_out ; + 4'd4 : o_rs = r4_out ; + 4'd5 : o_rs = r5_out ; + 4'd6 : o_rs = r6_out ; + 4'd7 : o_rs = r7_out ; + 4'd8 : o_rs = r8_rds ; + 4'd9 : o_rs = r9_rds ; + 4'd10 : o_rs = r10_rds ; + 4'd11 : o_rs = r11_rds ; + 4'd12 : o_rs = r12_rds ; + 4'd13 : o_rs = r13_rds ; + 4'd14 : o_rs = r14_rds ; + default: o_rs = r15_out_rn ; + endcase + + + +// ======================================================== +// Rd Selector +// ======================================================== + +always @* + case ( i_rs_sel ) + 4'd0 : o_rd = r0_out ; + 4'd1 : o_rd = r1_out ; + 4'd2 : o_rd = r2_out ; + 4'd3 : o_rd = r3_out ; + 4'd4 : o_rd = r4_out ; + 4'd5 : o_rd = r5_out ; + 4'd6 : o_rd = r6_out ; + 4'd7 : o_rd = r7_out ; + 4'd8 : o_rd = r8_rds ; + 4'd9 : o_rd = r9_rds ; + 4'd10 : o_rd = r10_rds ; + 4'd11 : o_rd = r11_rds ; + 4'd12 : o_rd = r12_rds ; + 4'd13 : o_rd = r13_rds ; + 4'd14 : o_rd = r14_rds ; + default: o_rd = r15_out_rm_nxt ; + endcase + + +// ======================================================== +// Rn Selector +// ======================================================== +assign o_rn = i_rn_sel == 4'd0 ? r0_out : + i_rn_sel == 4'd1 ? r1_out : + i_rn_sel == 4'd2 ? r2_out : + i_rn_sel == 4'd3 ? r3_out : + i_rn_sel == 4'd4 ? r4_out : + i_rn_sel == 4'd5 ? r5_out : + i_rn_sel == 4'd6 ? r6_out : + i_rn_sel == 4'd7 ? r7_out : + i_rn_sel == 4'd8 ? r8_out : + i_rn_sel == 4'd9 ? r9_out : + i_rn_sel == 4'd10 ? r10_out : + i_rn_sel == 4'd11 ? r11_out : + i_rn_sel == 4'd12 ? r12_out : + i_rn_sel == 4'd13 ? r13_out : + i_rn_sel == 4'd14 ? r14_out : + r15_out_rn ; + + +endmodule + + +module a25_multiply ( + i_clk, + i_core_stall, + + i_a_in, + i_b_in, + i_function, + i_execute, + + o_out, + o_flags, + o_done + ); + +input i_clk; +input i_core_stall; + +input [31:0] i_a_in; // Rds +input [31:0] i_b_in; // Rm +input [1:0] i_function; +input i_execute; + +output [31:0] o_out; +output [1:0] o_flags; // [1] = N, [0] = Z +output o_done; // goes high 2 cycles before completion + +reg o_done = 1'd0; +wire enable; +wire accumulate; +wire [33:0] multiplier; +wire [33:0] multiplier_bar; +wire [33:0] sum; +wire [33:0] sum34_b; + +reg [5:0] count = 6'd0; +reg [5:0] count_nxt; +reg [67:0] product = 68'd0; +reg [67:0] product_nxt; +reg [1:0] flags_nxt; +wire [32:0] sum_acc1; // the MSB is the carry out for the upper 32 bit addition + + +assign enable = i_function[0]; +assign accumulate = i_function[1]; + +assign multiplier = { 2'd0, i_a_in} ; +assign multiplier_bar = ~{ 2'd0, i_a_in} + 34'd1 ; + +assign sum34_b = product[1:0] == 2'b01 ? multiplier : + product[1:0] == 2'b10 ? multiplier_bar : + 34'd0 ; + + + // ----------------------------------- + // 34-bit adder - booth multiplication + // ----------------------------------- + assign sum = product[67:34] + sum34_b; + + // ------------------------------------ + // 33-bit adder - accumulate operations + // ------------------------------------ + assign sum_acc1 = {1'd0, product[32:1]} + {1'd0, i_a_in}; + + // assign count_nxt = count; + +always @* + begin + + + // update Negative and Zero flags + // Use registered value of product so this adds an extra cycle + // but this avoids having the 64-bit zero comparator on the + // main adder path + flags_nxt = { product[32], product[32:1] == 32'd0 }; + + + if ( count == 6'd0 ) + product_nxt = {33'd0, 1'd0, i_b_in, 1'd0 } ; + else if ( count <= 6'd33 ) + product_nxt = { sum[33], sum, product[33:1]} ; + else if ( count == 6'd34 && accumulate ) + begin + // Note that bit 0 is not part of the product. It is used during the booth + // multiplication algorithm + product_nxt = { product[64:33], sum_acc1[31:0], 1'd0}; // Accumulate + end + else + product_nxt = product; + + + // Multiplication state counter + if (count == 6'd0) // start + count_nxt = enable ? 6'd1 : 6'd0; + else if ((count == 6'd34 && !accumulate) || // MUL + (count == 6'd35 && accumulate) ) // MLA + count_nxt = 6'd0; + else + count_nxt = count + 1'd1; + end + + +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + count <= i_execute ? count_nxt : count; + product <= i_execute ? product_nxt : product; + o_done <= i_execute ? count == 6'd31 : o_done; + end + +// Outputs +assign o_out = product[32:1]; +assign o_flags = flags_nxt; + +endmodule + + + + +module a25_alu ( + + i_a_in, + i_b_in, + i_barrel_shift_carry, + i_status_bits_carry, + i_function, + o_out, + o_flags +); + +/************************* IO Declarations *********************/ +input [31:0] i_a_in; +input [31:0] i_b_in; +input i_barrel_shift_carry; +input i_status_bits_carry; +input [8:0] i_function; + +output [31:0] o_out; +output [3:0] o_flags; + +/*********************** Signal Declarations *******************/ +wire [31:0] a; +wire [31:0] b; +wire [31:0] b_not; +wire [31:0] and_out; +wire [31:0] or_out; +wire [31:0] xor_out; +wire [31:0] sign_ex8_out; +wire [31:0] sign_ex_16_out; +wire [31:0] zero_ex8_out; +wire [31:0] zero_ex_16_out; +wire [32:0] fadder_out; +wire swap_sel; +wire not_sel; +wire [1:0] cin_sel; +wire cout_sel; +wire [3:0] out_sel; +wire carry_in; +wire carry_out; +wire overflow_out; +wire fadder_carry_out; + +assign { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function; + + +assign a = (swap_sel ) ? i_b_in : i_a_in ; + +// ======================================================== +// B Select +// ======================================================== +assign b = (swap_sel ) ? i_a_in : i_b_in ; + +// ======================================================== +// Not Select +// ======================================================== +assign b_not = (not_sel ) ? ~b : b ; + +// ======================================================== +// Cin Select +// ======================================================== +assign carry_in = (cin_sel==2'd0 ) ? 1'd0 : + (cin_sel==2'd1 ) ? 1'd1 : + i_status_bits_carry ; // add with carry + +// ======================================================== +// Cout Select +// ======================================================== +assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out : + i_barrel_shift_carry ; + +// For non-addition/subtractions that incorporate a shift +// operation, C is set to the last bit +// shifted out of the value by the shifter. + + +// ======================================================== +// Overflow out +// ======================================================== +// Only assert the overflow flag when using the adder +assign overflow_out = out_sel == 4'd1 && + // overflow if adding two positive numbers and get a negative number + ( (!a[31] && !b_not[31] && fadder_out[31]) || + // or adding two negative numbers and get a positive number + (a[31] && b_not[31] && !fadder_out[31]) ); + + +// ======================================================== +// ALU Operations +// ======================================================== + + +assign fadder_out = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in}; + + +assign fadder_carry_out = fadder_out[32]; +assign and_out = a & b_not; +assign or_out = a | b_not; +assign xor_out = a ^ b_not; +assign zero_ex8_out = {24'd0, b_not[7:0]}; +assign zero_ex_16_out = {16'd0, b_not[15:0]}; +assign sign_ex8_out = {{24{b_not[7]}}, b_not[7:0]}; +assign sign_ex_16_out = {{16{b_not[15]}}, b_not[15:0]}; + +// ======================================================== +// Out Select +// ======================================================== +assign o_out = out_sel == 4'd0 ? b_not : + out_sel == 4'd1 ? fadder_out[31:0] : + out_sel == 4'd2 ? zero_ex_16_out : + out_sel == 4'd3 ? zero_ex8_out : + out_sel == 4'd4 ? sign_ex_16_out : + out_sel == 4'd5 ? sign_ex8_out : + out_sel == 4'd6 ? xor_out : + out_sel == 4'd7 ? or_out : + and_out ; + +assign o_flags = { o_out[31], // negative + |o_out == 1'd0, // zero + carry_out, // carry + overflow_out // overflow + }; + + +endmodule + + +module a25_execute ( + +i_clk, +i_core_stall, +i_mem_stall, +o_exec_stall, + +i_wb_read_data, +i_wb_read_data_valid, +i_wb_load_rd, + +i_copro_read_data, +i_decode_iaccess, +i_decode_daccess, +i_decode_load_rd, + +o_copro_write_data, +o_write_data, +o_iaddress, +o_iaddress_nxt, + +o_iaddress_valid, +o_daddress, +o_daddress_nxt, + +o_daddress_valid, +o_adex, +o_priviledged, +o_exclusive, +o_write_enable, +o_byte_enable, +o_exec_load_rd, +o_status_bits, +o_multiply_done, + +i_status_bits_mode, +i_status_bits_irq_mask, +i_status_bits_firq_mask, +i_imm32, +i_imm_shift_amount, +i_shift_imm_zero, +i_condition, +i_decode_exclusive, + +i_rm_sel, +i_rs_sel, +i_rn_sel, +i_barrel_shift_amount_sel, +i_barrel_shift_data_sel, +i_barrel_shift_function, +i_alu_function, +i_multiply_function, +i_interrupt_vector_sel, +i_iaddress_sel, +i_daddress_sel, +i_pc_sel, +i_byte_enable_sel, +i_status_bits_sel, +i_reg_write_sel, +i_user_mode_regs_store_nxt, +i_firq_not_user_mode, + +i_write_data_wen, +i_base_address_wen, +i_pc_wen, +i_reg_bank_wen, +i_status_bits_flags_wen, +i_status_bits_mode_wen, +i_status_bits_irq_mask_wen, +i_status_bits_firq_mask_wen, +i_copro_write_data_wen, +i_conflict, +i_rn_use_read, +i_rm_use_read, +i_rs_use_read, +i_rd_use_read +); + + +//`include "a25/a25_localparams.v" + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 6'b0, //0 + OH_IRQ = 6'b1, //1 + OH_FIRQ = 6'b10, //2 + OH_SVC = 6'b11; //3 + + +//`include "a25/a25_functions.v" + +input i_clk; +input i_core_stall; // stall all stages of the Amber core at the same time +input i_mem_stall; // data memory access stalls +output o_exec_stall; // stall the core pipeline + +input [31:0] i_wb_read_data; // data reads +input i_wb_read_data_valid; // read data is valid +input [10:0] i_wb_load_rd; // Rd for data reads + +input [31:0] i_copro_read_data; // From Co-Processor, to either Register + // or Memory +input i_decode_iaccess; // Indicates an instruction access +input i_decode_daccess; // Indicates a data access +input [7:0] i_decode_load_rd; // The destination register for a load instruction + +output [31:0] o_copro_write_data; +output [31:0] o_write_data; +output [31:0] o_iaddress; +output [31:0] o_iaddress_nxt; // un-registered version of address to the + // cache rams address ports +output o_iaddress_valid; // High when instruction address is valid +output [31:0] o_daddress; // Address to data cache +output [31:0] o_daddress_nxt; // un-registered version of address to the + // cache rams address ports +output o_daddress_valid; // High when data address is valid +output o_adex; // Address Exception +output o_priviledged; // Priviledged access +output o_exclusive; // swap access +output o_write_enable; +output [3:0] o_byte_enable; +output [8:0] o_exec_load_rd; // The destination register for a load instruction +output [31:0] o_status_bits; // Full PC will all status bits, but PC part zero'ed out +output o_multiply_done; + + +// -------------------------------------------------- +// Control signals from Instruction Decode stage +// -------------------------------------------------- +input [1:0] i_status_bits_mode; +input i_status_bits_irq_mask; +input i_status_bits_firq_mask; +input [31:0] i_imm32; +input [4:0] i_imm_shift_amount; +input i_shift_imm_zero; +input [3:0] i_condition; +input i_decode_exclusive; // swap access + +input [3:0] i_rm_sel; +input [3:0] i_rs_sel; +input [3:0] i_rn_sel; +input [1:0] i_barrel_shift_amount_sel; +input [1:0] i_barrel_shift_data_sel; +input [1:0] i_barrel_shift_function; +input [8:0] i_alu_function; +input [1:0] i_multiply_function; +input [2:0] i_interrupt_vector_sel; +input [3:0] i_iaddress_sel; +input [3:0] i_daddress_sel; +input [2:0] i_pc_sel; +input [1:0] i_byte_enable_sel; +input [2:0] i_status_bits_sel; +input [2:0] i_reg_write_sel; +input i_user_mode_regs_store_nxt; +input i_firq_not_user_mode; + +input i_write_data_wen; +input i_base_address_wen; // save LDM base address register, + // in case of data abort +input i_pc_wen; +input [14:0] i_reg_bank_wen; +input i_status_bits_flags_wen; +input i_status_bits_mode_wen; +input i_status_bits_irq_mask_wen; +input i_status_bits_firq_mask_wen; +input i_copro_write_data_wen; +input i_conflict; +input i_rn_use_read; +input i_rm_use_read; +input i_rs_use_read; +input i_rd_use_read; + + + +reg [31:0] o_copro_write_data = 32'd0; +reg [31:0] o_write_data = 32'd0; +reg [31:0] o_iaddress = 32'hdeaddead; + +reg o_iaddress_valid = 1'd0; // High when instruction address is valid +reg [31:0] o_daddress = 32'h0; // Address to data cache + +reg o_daddress_valid = 1'd0; // High when data address is valid +reg o_adex = 1'd0; // Address Exception +reg o_priviledged = 1'd0; // Priviledged access +reg o_exclusive = 1'd0; // swap access +reg o_write_enable = 1'd0; +reg [3:0] o_byte_enable = 4'd0; +reg [8:0] o_exec_load_rd = 9'd0; // The destination register for a load instruction + + +// ======================================================== +// Internal signals +// ======================================================== +wire [31:0] write_data_nxt; +wire [3:0] byte_enable_nxt; +wire [31:0] pc_plus4; +wire [31:0] pc_minus4; +wire [31:0] daddress_plus4; +wire [31:0] alu_plus4; +wire [31:0] rn_plus4; +wire [31:0] alu_out; +wire [3:0] alu_flags; +wire [31:0] rm; +wire [31:0] rs; +wire [31:0] rd; +wire [31:0] rn; +wire [31:0] reg_bank_rn; +wire [31:0] reg_bank_rm; +wire [31:0] reg_bank_rs; +wire [31:0] reg_bank_rd; +wire [31:0] pc; +wire [31:0] pc_nxt; +wire [31:0] interrupt_vector; +wire [7:0] shift_amount; +wire [31:0] barrel_shift_in; +wire [31:0] barrel_shift_out; +wire barrel_shift_carry; +wire barrel_shift_stall; + +wire [3:0] status_bits_flags_nxt; +reg [3:0] status_bits_flags = 4'd0; +wire [1:0] status_bits_mode_nxt; +reg [1:0] status_bits_mode = 2'b11; //SVC = 2'b11 + // one-hot encoded rs select +wire [3:0] status_bits_mode_rds_oh_nxt; + +//reg [3:0] status_bits_mode_rds_oh = 1'd1 << OH_SVC; +reg [3:0] status_bits_mode_rds_oh = 4'b1000; +wire status_bits_mode_rds_oh_update; +wire status_bits_irq_mask_nxt; +reg status_bits_irq_mask = 1'd1; +wire status_bits_firq_mask_nxt; +reg status_bits_firq_mask = 1'd1; +wire [8:0] exec_load_rd_nxt; + +wire execute; // high when condition execution is true +wire [31:0] reg_write_nxt; +wire pc_wen; +wire [14:0] reg_bank_wen; +wire [31:0] multiply_out; +wire [1:0] multiply_flags; +reg [31:0] base_address = 32'd0; // Saves base address during LDM instruction in + // case of data abort +wire [31:0] read_data_filtered1; +wire [31:0] read_data_filtered; +wire [31:0] read_data_filtered_c; +reg [31:0] read_data_filtered_r = 32'd0; +reg [3:0] load_rd_r = 4'd0; +wire [3:0] load_rd_c; + +wire write_enable_nxt; +wire daddress_valid_nxt; +wire iaddress_valid_nxt; +wire priviledged_nxt; +wire priviledged_update; +wire iaddress_update; +wire daddress_update; +wire base_address_update; +wire write_data_update; +wire copro_write_data_update; +wire byte_enable_update; +wire exec_load_rd_update; +wire write_enable_update; +wire exclusive_update; +wire status_bits_flags_update; +wire status_bits_mode_update; +wire status_bits_irq_mask_update; +wire status_bits_firq_mask_update; + +wire [31:0] alu_out_pc_filtered; +wire adex_nxt; +wire [31:0] save_int_pc; +wire [31:0] save_int_pc_m4; +wire ldm_flags; +wire ldm_status_bits; + + +// ======================================================== +// Status Bits in PC register +// ======================================================== +wire [1:0] status_bits_mode_out; +wire [3:0] pc_dmem_wen; //jing + + +assign status_bits_mode_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && !ldm_status_bits) ? + alu_out[1:0] : status_bits_mode ; + +assign o_status_bits = { status_bits_flags, // 31:28 + status_bits_irq_mask, // 7 27 + status_bits_firq_mask, // 6 26 + 24'd0, // 25:2 + status_bits_mode_out }; // 1:0 = mode + + +// ======================================================== +// Status Bits Select +// ======================================================== +assign ldm_flags = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[8]; +assign ldm_status_bits = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[7]; + + +assign status_bits_flags_nxt = ldm_flags ? read_data_filtered[31:28] : + i_status_bits_sel == 3'd0 ? alu_flags : + i_status_bits_sel == 3'd1 ? alu_out [31:28] : + i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] : + // 4 = update status_bits_flags after a multiply operation + { multiply_flags, status_bits_flags[1:0] } ; + +assign status_bits_mode_nxt = ldm_status_bits ? read_data_filtered [1:0] : + i_status_bits_sel == 3'd0 ? i_status_bits_mode : + i_status_bits_sel == 3'd1 ? alu_out [1:0] : + i_copro_read_data [1:0] ; + + +// Used for the Rds output of register_bank - this special version of +// status_bits_mode speeds up the critical path from status_bits_mode through the +// register_bank, barrel_shifter and alu. It moves a mux needed for the +// i_user_mode_regs_store_nxt signal back into the previous stage - +// so its really part of the decode stage even though the logic is right here +// In addition the signal is one-hot encoded to further speed up the logic + +//assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR : +// status_bits_mode_update ? oh_status_bits_mode(status_bits_mode_nxt) : +// oh_status_bits_mode(status_bits_mode) ; + + +assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 4'b0001 : //1'd1 << OH_USR + status_bits_mode_update ? ( status_bits_mode_nxt == SVC ? 4'b1000 : //1'd1 << OH_SVC + status_bits_mode_nxt == IRQ ? 4'b0010 : //1'd1 << OH_IRQ + status_bits_mode_nxt == FIRQ ? 4'b0100 : //1'd1 << OH_FIRQ + 4'b0001 ): //1'd1 << OH_USR + + ( status_bits_mode == SVC ? 4'b1000 : //1'd1 << OH_SVC + status_bits_mode == IRQ ? 4'b0010 : //1'd1 << OH_IRQ + status_bits_mode == FIRQ ? 4'b0100 : //1'd1 << OH_FIRQ + 4'b0001 ); //1'd1 << OH_USR + +assign status_bits_irq_mask_nxt = ldm_status_bits ? read_data_filtered [27] : + i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask : + i_status_bits_sel == 3'd1 ? alu_out [27] : + i_copro_read_data [27] ; + +assign status_bits_firq_mask_nxt = ldm_status_bits ? read_data_filtered [26] : + i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask : + i_status_bits_sel == 3'd1 ? alu_out [26] : + i_copro_read_data [26] ; +// ======================================================== +// Adders +// ======================================================== +assign pc_plus4 = pc + 32'd4; +assign pc_minus4 = pc - 32'd4; +assign daddress_plus4 = o_daddress + 32'd4; +assign alu_plus4 = alu_out + 32'd4; +assign rn_plus4 = rn + 32'd4; + +// ======================================================== +// Barrel Shift Amount Select +// ======================================================== +// An immediate shift value of 0 is translated into 32 +assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 : + i_barrel_shift_amount_sel == 2'd1 ? rs[7:0] : + {3'd0, i_imm_shift_amount } ; + + +// ======================================================== +// Barrel Shift Data Select +// ======================================================== +assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32 : rm ; + + +// ======================================================== +// Interrupt vector Select +// ======================================================== + +assign interrupt_vector = // Reset vector + (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 : + // Data abort interrupt vector + (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 : + // Fast interrupt vector + (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c : + // Regular interrupt vector + (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 : + // Prefetch abort interrupt vector + (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c : + // Undefined instruction interrupt vector + (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 : + // Software (SWI) interrupt vector + (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 : + // Default is the address exception interrupt + 32'h00000014 ; + + +// ======================================================== +// Address Select +// ======================================================== + +assign pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[3:0] == 4'd15; +//always @( posedge i_clk ) +// pc_dmem_wen = i_wb_read_data_valid & ~i_mem_stall & i_wb_load_rd[3:0] == 4'd15; + +// If rd is the pc, then seperate the address bits from the status bits for +// generating the next address to fetch +//assign alu_out_pc_filtered = pc_wen && i_pc_sel == 3'd1 ? pcf(alu_out) : alu_out; + +assign alu_out_pc_filtered = pc_wen && i_pc_sel == 3'd1 ? {6'd0, alu_out[25:2], 2'd0} : alu_out; + +// if current instruction does not execute because it does not meet the condition +// then address advances to next instruction +assign o_iaddress_nxt = (pc_dmem_wen) ? {6'd0, read_data_filtered[25:2], 2'd0} : + (!execute) ? pc_plus4 : + (i_iaddress_sel == 4'd0) ? pc_plus4 : + (i_iaddress_sel == 4'd1) ? alu_out_pc_filtered : + (i_iaddress_sel == 4'd2) ? interrupt_vector : + pc ; + +// if current instruction does not execute because it does not meet the condition +// then address advances to next instruction +assign o_daddress_nxt = (i_daddress_sel == 4'd1) ? alu_out_pc_filtered : + (i_daddress_sel == 4'd2) ? interrupt_vector : + (i_daddress_sel == 4'd4) ? rn : + (i_daddress_sel == 4'd5) ? daddress_plus4 : // MTRANS address incrementer + (i_daddress_sel == 4'd6) ? alu_plus4 : // MTRANS decrement after + rn_plus4 ; // MTRANS increment before + +// Data accesses use 32-bit address space, but instruction +// accesses are restricted to 26 bit space +assign adex_nxt = |o_iaddress_nxt[31:26] && i_decode_iaccess; + + +// ======================================================== +// Filter Read Data +// ======================================================== +// mem_load_rd[10:9]-> shift ROR bytes +// mem_load_rd[8] -> load flags with PC +// mem_load_rd[7] -> load status bits with PC +// mem_load_rd[6:5] -> Write into this Mode registers +// mem_load_rd[4] -> zero_extend byte +// mem_load_rd[3:0] -> Destination Register +assign read_data_filtered1 = i_wb_load_rd[10:9] == 2'd0 ? i_wb_read_data : + i_wb_load_rd[10:9] == 2'd1 ? {i_wb_read_data[7:0], i_wb_read_data[31:8]} : + i_wb_load_rd[10:9] == 2'd2 ? {i_wb_read_data[15:0], i_wb_read_data[31:16]} : + {i_wb_read_data[23:0], i_wb_read_data[31:24]} ; + +assign read_data_filtered = i_wb_load_rd[4] ? {24'd0, read_data_filtered1[7:0]} : read_data_filtered1 ; + + +// ======================================================== +// Program Counter Select +// ======================================================== +// If current instruction does not execute because it does not meet the condition +// then PC advances to next instruction +assign pc_nxt = (!execute) ? pc_plus4 : + i_pc_sel == 3'd0 ? pc_plus4 : + i_pc_sel == 3'd1 ? alu_out : + i_pc_sel == 3'd2 ? interrupt_vector : + i_pc_sel == 3'd3 ? {6'd0, read_data_filtered[25:2], 2'd0} : + pc_minus4 ; + + +// ======================================================== +// Register Write Select +// ======================================================== + +assign save_int_pc = { status_bits_flags, + status_bits_irq_mask, + status_bits_firq_mask, + pc[25:2], + status_bits_mode }; + + +assign save_int_pc_m4 = { status_bits_flags, + status_bits_irq_mask, + status_bits_firq_mask, + pc_minus4[25:2], + status_bits_mode }; + + +assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out : + // save pc to lr on an interrupt + i_reg_write_sel == 3'd1 ? save_int_pc_m4 : + // to update Rd at the end of Multiplication + i_reg_write_sel == 3'd2 ? multiply_out : + i_reg_write_sel == 3'd3 ? o_status_bits : + i_reg_write_sel == 3'd5 ? i_copro_read_data : // mrc + i_reg_write_sel == 3'd6 ? base_address : + save_int_pc ; + + +// ======================================================== +// Byte Enable Select +// ======================================================== +assign byte_enable_nxt = i_byte_enable_sel == 2'd0 ? 4'b1111 : // word write + i_byte_enable_sel == 2'd2 ? // halfword write + ( o_daddress_nxt[1] == 1'd0 ? 4'b0011 : + 4'b1100 ) : + + o_daddress_nxt[1:0] == 2'd0 ? 4'b0001 : // byte write + o_daddress_nxt[1:0] == 2'd1 ? 4'b0010 : + o_daddress_nxt[1:0] == 2'd2 ? 4'b0100 : + 4'b1000 ; + + +// ======================================================== +// Write Data Select +// ======================================================== +assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd : + {rd[7:0],rd[7:0],rd[7:0],rd[7:0]} ; + + +// ======================================================== +// Conditional Execution +// ======================================================== +//assign execute = conditional_execute ( i_condition, status_bits_flags ); + +assign execute = ( i_condition == AL ) || + ( i_condition == EQ && status_bits_flags[2] ) || + ( i_condition == NE && !status_bits_flags[2] ) || + ( i_condition == CS && status_bits_flags[1] ) || + ( i_condition == CC && !status_bits_flags[1] ) || + ( i_condition == MI && status_bits_flags[3] ) || + ( i_condition == PL && !status_bits_flags[3] ) || + ( i_condition == VS && status_bits_flags[0] ) || + ( i_condition == VC && !status_bits_flags[0] ) || + ( i_condition == HI && status_bits_flags[1] && !status_bits_flags[2] ) || + ( i_condition == LS && (!status_bits_flags[1] || status_bits_flags[2]) ) || + ( i_condition == GE && status_bits_flags[3] == status_bits_flags[0] ) || + ( i_condition == LT && status_bits_flags[3] != status_bits_flags[0] ) || + ( i_condition == GT && !status_bits_flags[2] && status_bits_flags[3] == status_bits_flags[0] ) || + ( i_condition == LE && (status_bits_flags[2] || status_bits_flags[3] != status_bits_flags[0])) ; + + +// allow the PC to increment to the next instruction when current +// instruction does not execute +assign pc_wen = (i_pc_wen || !execute) && !i_conflict; + +// only update register bank if current instruction executes +//assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen}; + assign reg_bank_wen = execute ==1'd1? {15'b111111111111111 & i_reg_bank_wen} : + {15'b0 & i_reg_bank_wen}; + +// ======================================================== +// Priviledged output flag +// ======================================================== +// Need to look at status_bits_mode_nxt so switch to priviledged mode +// at the same time as assert interrupt vector address + +assign priviledged_nxt = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ; + + +// ======================================================== +// Write Enable +// ======================================================== +// This must be de-asserted when execute is fault + +assign write_enable_nxt = execute && i_write_data_wen; + + +// ======================================================== +// Address Valid +// ======================================================== +assign daddress_valid_nxt = execute && i_decode_daccess && !i_core_stall; + +// For some multi-cycle instructions, the stream of instrution +// reads can be paused. However if the instruction does not execute +// then the read stream must not be interrupted. +assign iaddress_valid_nxt = i_decode_iaccess || !execute; + +// ======================================================== +// Use read value from data memory instead of from register +// ======================================================== +assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn; +assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm; +assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs; +assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd; + + +always@( posedge i_clk ) + if ( i_wb_read_data_valid ) + begin + read_data_filtered_r <= read_data_filtered; + load_rd_r <= i_wb_load_rd[3:0]; + end + +assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r; +assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r; + + +// ======================================================== +// Set mode for the destination registers of a mem read +// ======================================================== +// The mode is either user mode, or the current mode +assign exec_load_rd_nxt = { i_decode_load_rd[7:6], + i_decode_load_rd[5] ? USR : status_bits_mode, // 1 bit -> 2 bits + i_decode_load_rd[4:0] }; + + +// ======================================================== +// Register Update +// ======================================================== +assign o_exec_stall = barrel_shift_stall; + +assign daddress_update = !i_core_stall; +assign exec_load_rd_update = !i_core_stall && execute; +assign priviledged_update = !i_core_stall; +assign exclusive_update = !i_core_stall && execute; +assign write_enable_update = !i_core_stall; +assign write_data_update = !i_core_stall && execute && i_write_data_wen; +assign byte_enable_update = !i_core_stall && execute && i_write_data_wen; + +assign iaddress_update = pc_dmem_wen || (!i_core_stall && !i_conflict); +assign copro_write_data_update = !i_core_stall && execute && i_copro_write_data_wen; + +assign base_address_update = !i_core_stall && execute && i_base_address_wen; +assign status_bits_flags_update = ldm_flags || (!i_core_stall && execute && i_status_bits_flags_wen); +assign status_bits_mode_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_mode_wen); +assign status_bits_mode_rds_oh_update = !i_core_stall; +assign status_bits_irq_mask_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_irq_mask_wen); +assign status_bits_firq_mask_update = ldm_status_bits || (!i_core_stall && execute && i_status_bits_firq_mask_wen); + + +always @( posedge i_clk ) + begin + o_daddress <= daddress_update ? o_daddress_nxt : o_daddress; + o_daddress_valid <= daddress_update ? daddress_valid_nxt : o_daddress_valid; + o_exec_load_rd <= exec_load_rd_update ? exec_load_rd_nxt : o_exec_load_rd; + o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged; + o_exclusive <= exclusive_update ? i_decode_exclusive : o_exclusive; + o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable; + o_write_data <= write_data_update ? write_data_nxt : o_write_data; + o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable; + o_iaddress <= iaddress_update ? o_iaddress_nxt : o_iaddress; + o_iaddress_valid <= iaddress_update ? iaddress_valid_nxt : o_iaddress_valid; + o_adex <= iaddress_update ? adex_nxt : o_adex; + o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data; + + base_address <= base_address_update ? rn : base_address; + + status_bits_flags <= status_bits_flags_update ? status_bits_flags_nxt : status_bits_flags; + status_bits_mode <= status_bits_mode_update ? status_bits_mode_nxt : status_bits_mode; + status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh; + status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask; + status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask; + end + + +// ======================================================== +// Instantiate Barrel Shift +// ======================================================== +a25_barrel_shift u_barrel_shift ( + .i_clk ( i_clk ), + .i_in ( barrel_shift_in ), + .i_carry_in ( status_bits_flags[1] ), + .i_shift_amount ( shift_amount ), + .i_shift_imm_zero ( i_shift_imm_zero ), + .i_function ( i_barrel_shift_function ), + + .o_out ( barrel_shift_out ), + .o_carry_out ( barrel_shift_carry ), + .o_stall ( barrel_shift_stall ) +); + + +// ======================================================== +// Instantiate ALU +// ======================================================== +a25_alu u_alu ( + .i_a_in ( rn ), + .i_b_in ( barrel_shift_out ), + .i_barrel_shift_carry ( barrel_shift_carry ), + .i_status_bits_carry ( status_bits_flags[1] ), + .i_function ( i_alu_function ), + + .o_out ( alu_out ), + .o_flags ( alu_flags ) +); + + +// ======================================================== +// Instantiate Booth 64-bit Multiplier-Accumulator +// ======================================================== +a25_multiply u_multiply ( + .i_clk ( i_clk ), + .i_core_stall ( i_core_stall ), + .i_a_in ( rs ), + .i_b_in ( rm ), + .i_function ( i_multiply_function ), + .i_execute ( execute ), + .o_out ( multiply_out ), + .o_flags ( multiply_flags ), // [1] = N, [0] = Z + .o_done ( o_multiply_done ) +); + + +// ======================================================== +// Instantiate Register Bank +// ======================================================== +a25_register_bank u_register_bank( + .i_clk ( i_clk ), + .i_core_stall ( i_core_stall ), + .i_mem_stall ( i_mem_stall ), + .i_mode_idec ( i_status_bits_mode ), + .i_mode_exec ( status_bits_mode ), + .i_mode_rds_exec ( status_bits_mode_rds_oh ), + + // pre-encoded in decode stage to speed up long path + .i_firq_not_user_mode ( i_firq_not_user_mode ), + .i_rm_sel ( i_rm_sel ), + .i_rs_sel ( i_rs_sel ), + .i_rn_sel ( i_rn_sel ), + .i_pc_wen ( pc_wen ), + .i_reg_bank_wen ( reg_bank_wen ), + .i_pc ( pc_nxt[25:2] ), + .i_reg ( reg_write_nxt ), + + + + .i_wb_read_data ( read_data_filtered ), + .i_wb_read_data_valid ( i_wb_read_data_valid ), + .i_wb_read_data_rd ( i_wb_load_rd[3:0] ), + .i_wb_mode ( i_wb_load_rd[6:5] ), + + .i_status_bits_flags ( status_bits_flags ), + .i_status_bits_irq_mask ( status_bits_irq_mask ), + .i_status_bits_firq_mask ( status_bits_firq_mask ), + + + + // use one-hot version for speed, combine with i_user_mode_regs_store + + + .o_rm ( reg_bank_rm ), + .o_rs ( reg_bank_rs ), + .o_rd ( reg_bank_rd ), + .o_rn ( reg_bank_rn ), + .o_pc ( pc ) +); + + + +// ======================================================== +// Debug - non-synthesizable code +// ======================================================== +//synopsys translate_off + +wire [(2*8)-1:0] xCONDITION; +wire [(4*8)-1:0] xMODE; + +assign xCONDITION = i_condition == EQ ? "EQ" : + i_condition == NE ? "NE" : + i_condition == CS ? "CS" : + i_condition == CC ? "CC" : + i_condition == MI ? "MI" : + i_condition == PL ? "PL" : + i_condition == VS ? "VS" : + i_condition == VC ? "VC" : + i_condition == HI ? "HI" : + i_condition == LS ? "LS" : + i_condition == GE ? "GE" : + i_condition == LT ? "LT" : + i_condition == GT ? "GT" : + i_condition == LE ? "LE" : + i_condition == AL ? "AL" : + "NV " ; + +assign xMODE = status_bits_mode == SVC ? "SVC" : + status_bits_mode == IRQ ? "IRQ" : + status_bits_mode == FIRQ ? "FIRQ" : + "USR" ; + + +//synopsys translate_on + +endmodule + + +module a25_dcache + + ( + i_clk, + i_request, + i_exclusive, + i_write_data, + i_write_enable, + i_address, + i_address_nxt, + i_byte_enable, + i_cache_enable, + i_cache_flush, + i_fetch_stall, + i_exec_stall, + i_wb_cached_rdata, + i_wb_cached_ready, + + o_read_data, + o_stall, + o_wb_cached_req + ); + + + +`ifndef _A25_CONFIG_DEFINES +`define _A25_CONFIG_DEFINES + +// Cache Ways +// Changing this parameter is the recommended +// way to change the Amber cache size; 2, 3, 4 and 8 ways are supported. +// +// 2 ways -> 8KB cache +// 3 ways -> 12KB cache +// 4 ways -> 16KB cache +// 8 ways -> 32KB cache +// +// e.g. if both caches have 8 ways, the total is 32KB icache + 32KB dcache = 64KB + +`define A25_ICACHE_WAYS 4 +`define A25_DCACHE_WAYS 4 + + +// -------------------------------------------------------------------- +// Debug switches +// -------------------------------------------------------------------- + +// Enable the decompiler. The default output file is amber.dis +//`define A25_DECOMPILE + +// Co-processor 15 debug. Registers in here control the cache +//`define A25_COPRO15_DEBUG + +// Cache debug +//`define A25_CACHE_DEBUG + +// -------------------------------------------------------------------- + + +// -------------------------------------------------------------------- +// File Names +// -------------------------------------------------------------------- +//`ifndef A25_DECOMPILE_FILE +// `define A25_DECOMPILE_FILE "amber.dis" +//`endif + +`endif +// --------------------------------------------------------- +// Cache Configuration + +// Limited to Linux 4k page sizes -> 256 lines +parameter CACHE_LINES = 256; + +// This cannot be changed without some major surgeory on +// this module +parameter CACHE_WORDS_PER_LINE = 4; + +// Changing this parameter is the recommended +// way to change the overall cache size; 2, 4 and 8 ways are supported. +// 2 ways -> 8KB cache +// 4 ways -> 16KB cache +// 8 ways -> 32KB cache +parameter WAYS = `A25_DCACHE_WAYS; //4 + +// derived configuration parameters +//parameter CACHE_ADDR_WIDTH = log2 ( CACHE_LINES ); // = 8 +//parameter WORD_SEL_WIDTH = log2 ( CACHE_WORDS_PER_LINE ); // = 2 +//parameter TAG_ADDR_WIDTH = 32 - CACHE_ADDR_WIDTH - WORD_SEL_WIDTH - 2; // = 20 +//parameter TAG_WIDTH = TAG_ADDR_WIDTH + 1; // = 21, including Valid flag +//parameter CACHE_LINE_WIDTH = CACHE_WORDS_PER_LINE * 32; // = 128 +//parameter TAG_ADDR32_LSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2; // = 12 +//parameter CACHE_ADDR32_MSB = CACHE_ADDR_WIDTH + WORD_SEL_WIDTH + 2 - 1; // = 11 +//parameter CACHE_ADDR32_LSB = WORD_SEL_WIDTH + 2; // = 4 +//parameter WORD_SEL_MSB = WORD_SEL_WIDTH + 2 - 1; // = 3 +//parameter WORD_SEL_LSB = 2; // = 2 +// --------------------------------------------------------- + +parameter CACHE_ADDR_WIDTH = 8; // = 8 +parameter WORD_SEL_WIDTH = 2; // = 2 +parameter TAG_ADDR_WIDTH = 20; // = 20 +parameter TAG_WIDTH = 21; // = 21, including Valid flag +parameter CACHE_LINE_WIDTH = 128; // = 128 +parameter TAG_ADDR32_LSB = 12; // = 12 +parameter CACHE_ADDR32_MSB = 11; // = 11 +parameter CACHE_ADDR32_LSB = 4; // = 4 +parameter WORD_SEL_MSB = 3; // = 3 +parameter WORD_SEL_LSB = 2; // = 2 + + +input i_clk; // Read / Write requests from core +input i_request; +input i_exclusive; // exclusive access, part of swap instruction +input [31:0] i_write_data; +input i_write_enable; // write request from execute stage +input [31:0] i_address; // registered address from execute +input [31:0] i_address_nxt; // un-registered version of address from execute stage +input [3:0] i_byte_enable; +input i_cache_enable; // from co-processor 15 configuration register +input i_cache_flush; // from co-processor 15 register + +output [31:0] o_read_data; +input i_fetch_stall; +input i_exec_stall; +output o_stall; + +// WB Read Request +output o_wb_cached_req; // Read Request +input [127:0] i_wb_cached_rdata; // wb bus +input i_wb_cached_ready; // wb_stb && !wb_ack + +////////////////////////////////////////////////////////////////// +// // +// Parameters file for Amber 25 Core // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Holds general parameters that are used is several core // +// modules // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2011 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + + +// Instruction Types +localparam [3:0] REGOP = 4'h0, // Data processing + MULT = 4'h1, // Multiply + SWAP = 4'h2, // Single Data Swap + TRANS = 4'h3, // Single data transfer + MTRANS = 4'h4, // Multi-word data transfer + BRANCH = 4'h5, // Branch + CODTRANS = 4'h6, // Co-processor data transfer + COREGOP = 4'h7, // Co-processor data operation + CORTRANS = 4'h8, // Co-processor register transfer + SWI = 4'h9; // software interrupt + + +// Opcodes +localparam [3:0] AND = 4'h0, // Logical AND + EOR = 4'h1, // Logical Exclusive OR + SUB = 4'h2, // Subtract + RSB = 4'h3, // Reverse Subtract + ADD = 4'h4, // Add + ADC = 4'h5, // Add with Carry + SBC = 4'h6, // Subtract with Carry + RSC = 4'h7, // Reverse Subtract with Carry + TST = 4'h8, // Test (using AND operator) + TEQ = 4'h9, // Test Equivalence (using EOR operator) + CMP = 4'ha, // Compare (using Subtract operator) + CMN = 4'hb, // Compare Negated + ORR = 4'hc, // Logical OR + MOV = 4'hd, // Move + BIC = 4'he, // Bit Clear (using AND & NOT operators) + MVN = 4'hf; // Move NOT + +// Condition Encoding +localparam [3:0] EQ = 4'h0, // Equal / Z set + NE = 4'h1, // Not equal / Z clear + CS = 4'h2, // Carry set / C set + CC = 4'h3, // Carry clear / C clear + MI = 4'h4, // Minus / N set + PL = 4'h5, // Plus / N clear + VS = 4'h6, // Overflow / V set + VC = 4'h7, // No overflow / V clear + HI = 4'h8, // Unsigned higher / C set and Z clear + LS = 4'h9, // Unsigned lower + // or same / C clear or Z set + GE = 4'ha, // Signed greater + // than or equal / N == V + LT = 4'hb, // Signed less than / N != V + GT = 4'hc, // Signed greater + // than / Z == 0, N == V + LE = 4'hd, // Signed less than + // or equal / Z == 1, N != V + AL = 4'he, // Always + NV = 4'hf; // Never + +// Any instruction with a condition field of 0b1111 is UNPREDICTABLE. + +// Shift Types +localparam [1:0] LSL = 2'h0, + LSR = 2'h1, + ASR = 2'h2, + RRX = 2'h3, + ROR = 2'h3; + +// Modes +localparam [1:0] SVC = 2'b11, // Supervisor + IRQ = 2'b10, // Interrupt + FIRQ = 2'b01, // Fast Interrupt + USR = 2'b00; // User + +// One-Hot Mode encodings +localparam [5:0] OH_USR = 0, + OH_IRQ = 1, + OH_FIRQ = 2, + OH_SVC = 3; + + +// One-hot encoded +localparam C_INIT = 0, + C_CORE = 1, + C_FILL = 2, + C_INVA = 3, + C_STATES = 4; + +localparam [3:0] CS_INIT = 4'd0, + CS_IDLE = 4'd1, + CS_FILL = 4'd2, + CS_FILL_COMPLETE = 4'd3, + CS_TURN_AROUND = 4'd4, + CS_WRITE_HIT = 4'd5, + CS_WRITE_HIT_WAIT_WB = 4'd6, + CS_WRITE_MISS_WAIT_WB = 4'd7, + CS_EX_DELETE = 4'd8; + + +reg [3:0] c_state = CS_IDLE; +//reg [C_STATES-1:0] source_sel = 4'd1 << C_CORE; +reg [C_STATES-1:0] source_sel = 4'b10; +reg [CACHE_ADDR_WIDTH:0] init_count = 9'd0; + +wire [TAG_WIDTH-1:0] tag_rdata_way0; +wire [TAG_WIDTH-1:0] tag_rdata_way1; +wire [TAG_WIDTH-1:0] tag_rdata_way2; +wire [TAG_WIDTH-1:0] tag_rdata_way3; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way0; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way1; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way2; +wire [CACHE_LINE_WIDTH-1:0] data_rdata_way3; +wire [WAYS-1:0] data_wenable_way; +wire [WAYS-1:0] data_hit_way; +reg [WAYS-1:0] data_hit_way_r = 4'd0; +wire [WAYS-1:0] tag_wenable_way; +reg [WAYS-1:0] select_way = 4'd0; +wire [WAYS-1:0] next_way; +reg [WAYS-1:0] valid_bits_r = 4'd0; + +reg [3:0] random_num = 4'hf; + +wire [CACHE_ADDR_WIDTH-1:0] tag_address; +wire [TAG_WIDTH-1:0] tag_wdata; +wire tag_wenable; + +wire [CACHE_LINE_WIDTH-1:0] read_miss_wdata; +wire [CACHE_LINE_WIDTH-1:0] write_hit_wdata; +reg [CACHE_LINE_WIDTH-1:0] data_wdata_r = 128'd0; +wire [CACHE_LINE_WIDTH-1:0] consecutive_write_wdata; +wire [CACHE_LINE_WIDTH-1:0] data_wdata; +wire [CACHE_ADDR_WIDTH-1:0] data_address; +wire [31:0] write_data_word; + +wire idle_hit; +wire read_miss; +wire write_miss; +wire write_hit; +wire consecutive_write; +wire fill_state; + +reg [31:0] miss_address = 32'd0; +wire [CACHE_LINE_WIDTH-1:0] hit_rdata; + +wire read_stall; +wire write_stall; +wire cache_busy_stall; +wire core_stall; +wire write_state; + +wire request_pulse; +wire request_hold; +reg request_r = 1'd0; +wire [CACHE_ADDR_WIDTH-1:0] address; +reg [CACHE_LINE_WIDTH-1:0] wb_rdata_burst = 128'd0; + +wire exclusive_access; +wire ex_read_hit; +reg ex_read_hit_r = 1'd0; +reg [WAYS-1:0] ex_read_hit_way = 4'd0; +reg [CACHE_ADDR_WIDTH-1:0] ex_read_address; +wire ex_read_hit_clear; +wire ex_read_cache_busy; + +reg [31:0] wb_address = 32'd0; +//wire rbuf_hit = 1'd0; +wire wb_hit; +wire [127:0] read_data128; +//genvar i; + + +// ====================================== +// Address to use for cache access +// ====================================== +// If currently stalled then the address for the next +// cycle will be the same as it is in the current cycle +// +assign core_stall = i_fetch_stall || i_exec_stall || o_stall; + +assign address = core_stall ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + i_address_nxt[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] ; + +// ====================================== +// Outputs +// ====================================== + +assign read_data128 = wb_hit ? i_wb_cached_rdata : hit_rdata; + +assign o_read_data = i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd0 ? read_data128 [31:0] : + i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd1 ? read_data128 [63:32] : + i_address[WORD_SEL_MSB:WORD_SEL_LSB] == 2'd2 ? read_data128 [95:64] : + read_data128 [127:96] ; + +// Don't allow the cache to stall the wb i/f for an exclusive access +// The cache needs a couple of cycles to flush a potential copy of the exclusive +// address, but the wb can do the access in parallel. So there is no +// stall in the state CS_EX_DELETE, even though the cache is out of action. +// This works fine as long as the wb is stalling the core +assign o_stall = request_hold && ( read_stall || write_stall || cache_busy_stall || ex_read_cache_busy ); + +assign o_wb_cached_req = ( (read_miss || write_miss || write_hit) && c_state == CS_IDLE ) || consecutive_write; + + +// ====================================== +// Cache State Machine +// ====================================== + +// Little State Machine to Flush Tag RAMS +always @ ( posedge i_clk ) + if ( i_cache_flush ) + begin + c_state <= CS_INIT; + source_sel <= 4'b1; //1'd1 << C_INIT + init_count <= 9'd0; + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display("Cache Flush"); + `endif + end + else + case ( c_state ) + CS_INIT : + if ( init_count < CACHE_LINES ) + begin + init_count <= init_count + 1'd1; + source_sel <= 4'b1; //1'd1 << C_INIT + end + else + begin + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + CS_IDLE : + begin + if ( ex_read_hit || ex_read_hit_r ) + begin + select_way <= data_hit_way | ex_read_hit_way; + c_state <= CS_EX_DELETE; + source_sel <= 4'b1000; //1'd1 << C_INVA + end + else if ( read_miss ) + begin + c_state <= CS_FILL; + source_sel <= 4'b10; //1'd1 << C_CORE + end + else if ( write_hit ) + begin + source_sel <= 4'b10; //1'd1 << C_CORE + if ( i_wb_cached_ready ) + c_state <= CS_WRITE_HIT; + + else + c_state <= CS_WRITE_HIT_WAIT_WB; + end + else if ( write_miss && !i_wb_cached_ready ) + begin + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_WRITE_MISS_WAIT_WB; + end + end + + + CS_FILL : + // third read of burst of 4 + // wb read request asserted, wait for ack + if ( i_wb_cached_ready ) + begin + c_state <= CS_FILL_COMPLETE; + source_sel <= 4'b100; //1'd1 << C_FILL + + // Pick a way to write the cache update into + // Either pick one of the invalid caches, or if all are valid, then pick + // one randomly + + select_way <= next_way; + random_num <= {random_num[2], random_num[1], random_num[0], + random_num[3]^random_num[2]}; + end + + + // Write the read fetch data in this cycle + CS_FILL_COMPLETE : + begin + // Back to normal cache operations, but + // use physical address for first read as + // address moved before the stall was asserted for the read_miss + // However don't use it if its a non-cached address! + source_sel <= 4'b10; //1'd1 << C_CORE + c_state <= CS_TURN_AROUND; + end + + + // Ignore the tag read data in this cycle + // Wait 1 cycle to pre-read the cache and return to normal operation + CS_TURN_AROUND : + begin + c_state <= CS_IDLE; + end + + + // Flush the entry matching an exclusive access + CS_EX_DELETE: + begin + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display("Cache deleted Locked entry"); + `endif + c_state <= CS_TURN_AROUND; + source_sel <= 4'b10; //1'd1 << C_CORE + end + + + CS_WRITE_HIT: + if ( !consecutive_write ) + c_state <= CS_IDLE; + + + CS_WRITE_HIT_WAIT_WB: + // wait for an ack on the wb bus to complete the write + if ( i_wb_cached_ready ) + c_state <= CS_IDLE; + + + CS_WRITE_MISS_WAIT_WB: + // wait for an ack on the wb bus to complete the write + if ( i_wb_cached_ready ) + c_state <= CS_IDLE; + + endcase + + +// ====================================== +// Capture WB Block Read - burst of 4 words +// ====================================== +always @ ( posedge i_clk ) + if ( i_wb_cached_ready ) + wb_rdata_burst <= i_wb_cached_rdata; + + + +// ====================================== +// Miss Address +// ====================================== +always @ ( posedge i_clk ) + if ( o_wb_cached_req || write_hit ) + miss_address <= i_address; + +always @ ( posedge i_clk ) + if ( write_hit ) + begin + data_hit_way_r <= data_hit_way; + end + +always @ ( posedge i_clk ) + if ( write_hit || consecutive_write ) + begin + data_wdata_r <= data_wdata; + end + +assign consecutive_write = miss_address[31:4] == i_address[31:4] && + i_write_enable && + c_state == CS_WRITE_HIT && + request_pulse; + + +always @(posedge i_clk) + if ( o_wb_cached_req ) + wb_address <= i_address; + else if ( i_wb_cached_ready && fill_state ) + wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0}; + +assign fill_state = c_state == CS_FILL ; +assign wb_hit = i_address == wb_address && i_wb_cached_ready && fill_state; + + +// ====================================== +// Hold Requests +// ====================================== +always @(posedge i_clk) + request_r <= (request_pulse || request_r) && o_stall; + +assign request_hold = request_pulse || request_r; + + +// ====================================== +// Remember Read-Modify-Write Hit +// ====================================== +assign ex_read_hit_clear = c_state == CS_EX_DELETE; + +always @ ( posedge i_clk ) + if ( ex_read_hit_clear ) + begin + ex_read_hit_r <= 1'd0; + ex_read_hit_way <= 4'd0; + end + else if ( ex_read_hit ) + begin + + `ifdef A25_CACHE_DEBUG + `TB_DEBUG_MESSAGE + $display ("Exclusive access cache hit address 0x%08h", i_address); + `endif + + ex_read_hit_r <= 1'd1; + ex_read_hit_way <= data_hit_way; + end + else if ( c_state == CS_FILL_COMPLETE && ex_read_hit_r ) + ex_read_hit_way <= select_way; + + +always @ (posedge i_clk) + if ( ex_read_hit ) + ex_read_address <= i_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB]; + + +assign tag_address = source_sel[C_FILL] ? miss_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_INVA] ? ex_read_address : + source_sel[C_INIT] ? init_count[CACHE_ADDR_WIDTH-1:0] : + source_sel[C_CORE] ? address : + {CACHE_ADDR_WIDTH{1'd0}} ; + + +assign data_address = consecutive_write ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + write_hit ? i_address [CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_FILL] ? miss_address[CACHE_ADDR32_MSB:CACHE_ADDR32_LSB] : + source_sel[C_CORE] ? address : + {CACHE_ADDR_WIDTH{1'd0}} ; + + +assign tag_wdata = source_sel[C_FILL] ? {1'd1, miss_address[31:12]} : // [31:TAG_ADDR32_LSB] + {TAG_WIDTH{1'd0}} ; + + + // Data comes in off the WB bus in wrap4 with the missed data word first +assign data_wdata = write_hit && c_state == CS_IDLE ? write_hit_wdata : + consecutive_write ? consecutive_write_wdata : + read_miss_wdata ; + +assign read_miss_wdata = wb_rdata_burst; + + +assign write_hit_wdata = i_address[3:2] == 2'd0 ? {hit_rdata[127:32], write_data_word } : + i_address[3:2] == 2'd1 ? {hit_rdata[127:64], write_data_word, hit_rdata[31:0] } : + i_address[3:2] == 2'd2 ? {hit_rdata[127:96], write_data_word, hit_rdata[63:0] } : + { write_data_word, hit_rdata[95:0] } ; +wire [31:0] con_read_data_word; +wire [31:0] con_write_data_word; + +assign consecutive_write_wdata = + i_address[3:2] == 2'd0 ? {data_wdata_r[127:32], con_write_data_word } : + i_address[3:2] == 2'd1 ? {data_wdata_r[127:64], con_write_data_word, data_wdata_r[31:0] } : + i_address[3:2] == 2'd2 ? {data_wdata_r[127:96], con_write_data_word, data_wdata_r[63:0] } : + { con_write_data_word, data_wdata_r[95:0] } ; +assign con_read_data_word = + i_address[3:2] == 2'd0 ? data_wdata_r[ 31: 0] : + i_address[3:2] == 2'd1 ? data_wdata_r[ 63: 32] : + i_address[3:2] == 2'd2 ? data_wdata_r[ 95: 64] : + data_wdata_r[127: 96] ; + + +assign con_write_data_word = + i_byte_enable == 4'b0001 ? { con_read_data_word[31: 8], i_write_data[ 7: 0] } : + i_byte_enable == 4'b0010 ? { con_read_data_word[31:16], i_write_data[15: 8], con_read_data_word[ 7:0]} : + i_byte_enable == 4'b0100 ? { con_read_data_word[31:24], i_write_data[23:16], con_read_data_word[15:0]} : + i_byte_enable == 4'b1000 ? { i_write_data[31:24], con_read_data_word[23:0]} : + i_byte_enable == 4'b0011 ? { con_read_data_word[31:16], i_write_data[15: 0] } : + i_byte_enable == 4'b1100 ? { i_write_data[31:16], con_read_data_word[15:0]} : + i_write_data ; + + + + +// Use Byte Enables +assign write_data_word = i_byte_enable == 4'b0001 ? { o_read_data[31: 8], i_write_data[ 7: 0] } : + i_byte_enable == 4'b0010 ? { o_read_data[31:16], i_write_data[15: 8], o_read_data[ 7:0]} : + i_byte_enable == 4'b0100 ? { o_read_data[31:24], i_write_data[23:16], o_read_data[15:0]} : + i_byte_enable == 4'b1000 ? { i_write_data[31:24], o_read_data[23:0]} : + i_byte_enable == 4'b0011 ? { o_read_data[31:16], i_write_data[15: 0] } : + i_byte_enable == 4'b1100 ? { i_write_data[31:16], o_read_data[15:0]} : + i_write_data ; + + +assign tag_wenable = source_sel[C_INVA] ? 1'd1 : + source_sel[C_FILL] ? 1'd1 : + source_sel[C_INIT] ? 1'd1 : + source_sel[C_CORE] ? 1'd0 : + 1'd0 ; + + +assign request_pulse = i_request && i_cache_enable; + +assign exclusive_access = i_exclusive && i_cache_enable; + + +//always@(posedge i_clk) +// idle_hit <= |data_hit_way; + +assign idle_hit = |data_hit_way; + +assign write_hit = request_hold && i_write_enable && idle_hit; + +assign write_miss = request_hold && i_write_enable && !idle_hit && !consecutive_write; + +assign read_miss = request_hold && !idle_hit && !i_write_enable; + + // Exclusive read idle_hit +assign ex_read_hit = exclusive_access && !i_write_enable && idle_hit; + + // Added to fix rare swap bug which occurs when the cache starts + // a fill just as the swap instruction starts to execute. The cache + // fails to check for a read idle_hit on the swap read cycle. + // This signal stalls the core in that case until after the + // fill has completed. +assign ex_read_cache_busy = exclusive_access && !i_write_enable && c_state != CS_IDLE; + + // Need to stall for a write miss to wait for the current wb + // read miss access to complete. Also for a write idle_hit, need + // to stall for 1 cycle while the data cache is being written to +assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT || + c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB; + +assign write_stall = (write_miss && !(i_wb_cached_ready && write_state)) || (write_hit && !i_wb_cached_ready); + +//assign read_stall = request_hold && !idle_hit && !rbuf_hit && !wb_hit && !i_write_enable; + +assign read_stall = request_hold && !idle_hit && !wb_hit && !i_write_enable; + +assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT || +// (fill_state && !rbuf_hit && !wb_hit) || + (fill_state && !wb_hit) || + (c_state == CS_WRITE_HIT && !consecutive_write); + + +// ====================================== +// Instantiate RAMS +// ====================================== + +//generate +// for ( i=0; i 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else if ( WAYS == 3 ) begin : check_hit_3ways + + always @( posedge i_clk ) + if ( (data_hit_way[0] + data_hit_way[1] + data_hit_way[2] ) > 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else if ( WAYS == 4 ) begin : check_hit_4ways + + always @( posedge i_clk ) + if ( (data_hit_way[0] + data_hit_way[1] + + data_hit_way[2] + data_hit_way[3] ) > 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else if ( WAYS == 8 ) begin : check_hit_8ways + + always @( posedge i_clk ) + if ( (data_hit_way[0] + data_hit_way[1] + + data_hit_way[2] + data_hit_way[3] + + data_hit_way[4] + data_hit_way[5] + + data_hit_way[6] + data_hit_way[7] ) > 4'd1 ) + begin + `TB_ERROR_MESSAGE + $display("Hit in more than one cache ways!"); + end + +end +else begin : check_hit_nways + + initial + begin + ` + $display("Unsupported number of ways %0d", WAYS); + $display("Set A25_DCACHE_WAYS in a25_config_defines.v to either 2,3,4 or 8"); + end + +end +endgenerate +*/ + +//synopsys translate_on + +endmodule + + + +module a25_mem( + i_clk, + i_fetch_stall, + i_exec_stall, + o_mem_stall, + + i_daddress, + i_daddress_valid, + i_daddress_nxt, + i_write_data, + i_write_enable, + i_exclusive, + i_byte_enable, + i_exec_load_rd, + i_cache_enable, + i_cache_flush, + i_cacheable_area, + + o_mem_read_data, + o_mem_read_data_valid, + o_mem_load_rd, + + o_wb_cached_req, + o_wb_uncached_req, + o_wb_write, + o_wb_byte_enable, + o_wb_write_data, + o_wb_address, + i_wb_uncached_rdata, + i_wb_cached_rdata, + i_wb_cached_ready, + i_wb_uncached_ready + ); + + + +input i_clk; +input i_fetch_stall; // Fetch stage asserting stall +input i_exec_stall; // Execute stage asserting stall +output o_mem_stall; // Mem stage asserting stall + +input [31:0] i_daddress; +input i_daddress_valid; +input [31:0] i_daddress_nxt; // un-registered version of address to the cache rams +input [31:0] i_write_data; +input i_write_enable; +input i_exclusive; // high for read part of swap access +input [3:0] i_byte_enable; +input [8:0] i_exec_load_rd; // The destination register for a load instruction +input i_cache_enable; // cache enable +input i_cache_flush; // cache flush +input [31:0] i_cacheable_area; // each bit corresponds to 2MB address space + +output [31:0] o_mem_read_data; +output o_mem_read_data_valid; +output [10:0] o_mem_load_rd; // The destination register for a load instruction + +// Wishbone accesses +output o_wb_cached_req; // Cached Request +output o_wb_uncached_req; // Unached Request +output o_wb_write; // Read=0, Write=1 +output [15:0] o_wb_byte_enable; // byte eable +output [127:0] o_wb_write_data; +output [31:0] o_wb_address; // wb bus +input [127:0] i_wb_uncached_rdata; // wb bus +input [127:0] i_wb_cached_rdata; // wb bus +input i_wb_cached_ready; // wishbone access complete and read data valid +input i_wb_uncached_ready; // wishbone access complete and read data valid + +wire [31:0] cache_read_data; +wire address_cachable; +wire sel_cache_p; +wire sel_cache; +wire cached_wb_req; +wire uncached_data_access; +wire uncached_data_access_p; +wire cache_stall; +wire uncached_wb_wait; +reg uncached_wb_req_r = 1'd0; +reg uncached_wb_stop_r = 1'd0; +reg cached_wb_stop_r = 1'd0; +wire daddress_valid_p; // pulse +reg [31:0] mem_read_data_r = 32'd0; +reg mem_read_data_valid_r = 1'd0; +reg [10:0] mem_load_rd_r = 11'd0; +wire [10:0] mem_load_rd_c; +wire [31:0] mem_read_data_c; +wire mem_read_data_valid_c; +reg mem_stall_r = 1'd0; +wire use_mem_reg; +reg fetch_only_stall_r = 1'd0; +wire fetch_only_stall; +wire void_output; +wire wb_stop; +reg daddress_valid_stop_r = 1'd0; +wire [31:0] wb_rdata32; + +// ====================================== +// Memory Decode +// ====================================== + +//assign address_cachable = in_cachable_mem( i_daddress ) && i_cacheable_area[i_daddress[25:21]]; +//in_cachable_mem = in_loboot_mem ( address ) || in_main_mem ( address ) ; + + +// e.g. 24 for 32MBytes, 26 for 128MBytes +localparam MAIN_MSB = 26; + +// e.g. 13 for 4k words +localparam BOOT_MSB = 13; + +localparam MAIN_BASE = 32'h00000000; /* Main Memory */ +localparam BOOT_BASE = 32'h00000000; /* Cachable Boot Memory */ +localparam AMBER_TM_BASE = 16'h1300; /* Timers Module */ +localparam AMBER_IC_BASE = 16'h1400; /* Interrupt Controller */ +localparam AMBER_UART0_BASE = 16'h1600; /* UART 0 */ +localparam AMBER_UART1_BASE = 16'h1700; /* UART 1 */ +localparam ETHMAC_BASE = 16'h2000; /* Ethernet MAC */ +localparam HIBOOT_BASE = 32'h28000000; /* Uncachable Boot Memory */ +localparam TEST_BASE = 16'hf000; /* Test Module */ + + + +//function in_loboot_mem; +// input [31:0] address; +//begin +//in_loboot_mem = (address >= BOOT_BASE && +// address < (BOOT_BASE + 2**(BOOT_MSB+1)-1)); +//end +//endfunction + + +//function in_hiboot_mem; +// input [31:0] address; +//begin +//in_hiboot_mem = (address[31:BOOT_MSB+1] == HIBOOT_BASE[31:BOOT_MSB+1]); +// = (address[31:14] == HIBOOT_BASE>>(BOOT_MSB+1)); fixed + +//end +//endfunction + + +//function in_boot_mem; +// input [31:0] address; +//begin +//in_boot_mem = in_loboot_mem(address) || in_hiboot_mem(address); +//end +//endfunction + + +//function in_main_mem; +// input [31:0] address; +//begin +//in_main_mem = (address >= MAIN_BASE && +// address < (MAIN_BASE + 2**(MAIN_MSB+1)-1)) && +// !in_boot_mem ( address ); +//end +//endfunction + + +// UART 0 address space +//function in_uart0; +// input [31:0] address; +//begin +// in_uart0 = address [31:16] == AMBER_UART0_BASE; +//end +//endfunction + + +// UART 1 address space +//function in_uart1; +// input [31:0] address; +//begin +// in_uart1 = address [31:16] == AMBER_UART1_BASE; +//end +//endfunction + + +// Interrupt Controller address space +//function in_ic; +// input [31:0] address; +//begin +// in_ic = address [31:16] == AMBER_IC_BASE; +//end +//endfunction + + +// Timer Module address space +//function in_tm; +// input [31:0] address; +//begin +// in_tm = address [31:16] == AMBER_TM_BASE; +//end +//endfunction + + +// Test module +//function in_test; +// input [31:0] address; +//begin +// in_test = address [31:16] == TEST_BASE; +//end +//endfunction + + +// Ethernet MAC +//function in_ethmac; +// input [31:0] address; +//begin +// in_ethmac = address [31:16] == ETHMAC_BASE; +//end +//endfunction + + +// Used in fetch.v and l2cache.v to allow accesses to these addresses +// to be cached +//function in_cachable_mem; +// input [31:0] address; +//begin +// in_cachable_mem = in_loboot_mem ( address ) || +// in_main_mem ( address ) ; +//end +//endfunction + + + +assign address_cachable = ( + (i_daddress >= BOOT_BASE && i_daddress < (BOOT_BASE + 32'h7fff)) // in_loboot_mem ( address ) + || ( + (i_daddress >= MAIN_BASE && i_daddress < (MAIN_BASE + 32'hfffffff)) + && !( (i_daddress >= BOOT_BASE && i_daddress < (BOOT_BASE + 32'h7fff)) + ||(i_daddress[31:14] == HIBOOT_BASE>>(14))) + ) + ) + && ((i_daddress[25:21] == 5'b00000) ? i_cacheable_area[0] : + (i_daddress[25:21] == 5'b00001) ? i_cacheable_area[1] : + (i_daddress[25:21] == 5'b00010) ? i_cacheable_area[2] : + (i_daddress[25:21] == 5'b00011) ? i_cacheable_area[3] : + (i_daddress[25:21] == 5'b00100) ? i_cacheable_area[4] : + (i_daddress[25:21] == 5'b00101) ? i_cacheable_area[5] : + (i_daddress[25:21] == 5'b00110) ? i_cacheable_area[6] : + (i_daddress[25:21] == 5'b00111) ? i_cacheable_area[7] : + (i_daddress[25:21] == 5'b01000) ? i_cacheable_area[8] : + (i_daddress[25:21] == 5'b01001) ? i_cacheable_area[9] : + (i_daddress[25:21] == 5'b01010) ? i_cacheable_area[10] : + (i_daddress[25:21] == 5'b01011) ? i_cacheable_area[11] : + (i_daddress[25:21] == 5'b01100) ? i_cacheable_area[12] : + (i_daddress[25:21] == 5'b01101) ? i_cacheable_area[13] : + (i_daddress[25:21] == 5'b01110) ? i_cacheable_area[14] : + (i_daddress[25:21] == 5'b01111) ? i_cacheable_area[15] : + (i_daddress[25:21] == 5'b10000) ? i_cacheable_area[16] : + (i_daddress[25:21] == 5'b10001) ? i_cacheable_area[17] : + (i_daddress[25:21] == 5'b10010) ? i_cacheable_area[18] : + (i_daddress[25:21] == 5'b10011) ? i_cacheable_area[19] : + (i_daddress[25:21] == 5'b10100) ? i_cacheable_area[20] : + (i_daddress[25:21] == 5'b10101) ? i_cacheable_area[21] : + (i_daddress[25:21] == 5'b10110) ? i_cacheable_area[22] : + (i_daddress[25:21] == 5'b10111) ? i_cacheable_area[23] : + (i_daddress[25:21] == 5'b11000) ? i_cacheable_area[24] : + (i_daddress[25:21] == 5'b11001) ? i_cacheable_area[25] : + (i_daddress[25:21] == 5'b11010) ? i_cacheable_area[26] : + (i_daddress[25:21] == 5'b11011) ? i_cacheable_area[27] : + (i_daddress[25:21] == 5'b11100) ? i_cacheable_area[28] : + (i_daddress[25:21] == 5'b11101) ? i_cacheable_area[29] : + (i_daddress[25:21] == 5'b11110) ? i_cacheable_area[30] : + i_cacheable_area[31] ); + +//i_cacheable_area[i_daddress[25:21]]; +assign sel_cache_p = daddress_valid_p && address_cachable && i_cache_enable && !i_exclusive; +assign sel_cache = i_daddress_valid && address_cachable && i_cache_enable && !i_exclusive; +assign uncached_data_access = i_daddress_valid && !sel_cache && !cache_stall; +assign uncached_data_access_p = daddress_valid_p && !sel_cache; + +assign use_mem_reg = wb_stop && !mem_stall_r; +assign o_mem_read_data = use_mem_reg ? mem_read_data_r : mem_read_data_c; +assign o_mem_load_rd = use_mem_reg ? mem_load_rd_r : mem_load_rd_c; +assign o_mem_read_data_valid = !void_output && (use_mem_reg ? mem_read_data_valid_r : mem_read_data_valid_c); + + +// Return read data either from the wishbone bus or the cache +assign wb_rdata32 = i_daddress[3:2] == 2'd0 ? i_wb_uncached_rdata[ 31: 0] : + i_daddress[3:2] == 2'd1 ? i_wb_uncached_rdata[ 63:32] : + i_daddress[3:2] == 2'd2 ? i_wb_uncached_rdata[ 95:64] : + i_wb_uncached_rdata[127:96] ; + +assign mem_read_data_c = sel_cache ? cache_read_data : + uncached_data_access ? wb_rdata32 : + 32'h76543210 ; + +assign mem_load_rd_c = {i_daddress[1:0], i_exec_load_rd}; +assign mem_read_data_valid_c = i_daddress_valid && !i_write_enable && !o_mem_stall; + +assign o_mem_stall = uncached_wb_wait || cache_stall; + +// Request wishbone access +assign o_wb_byte_enable = i_daddress[3:2] == 2'd0 ? {12'd0, i_byte_enable } : + i_daddress[3:2] == 2'd1 ? { 8'd0, i_byte_enable, 4'd0} : + i_daddress[3:2] == 2'd2 ? { 4'd0, i_byte_enable, 8'd0} : + { i_byte_enable, 12'd0} ; + +assign o_wb_write = i_write_enable; +assign o_wb_address = {i_daddress[31:2], 2'd0}; +assign o_wb_write_data = {4{i_write_data}}; +assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req; +assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p; + +assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready; + +always @( posedge i_clk ) + begin + uncached_wb_req_r <= (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready; + end + +assign fetch_only_stall = i_fetch_stall && !o_mem_stall; + +always @( posedge i_clk ) + fetch_only_stall_r <= fetch_only_stall; + +assign void_output = (fetch_only_stall_r && fetch_only_stall) || (fetch_only_stall_r && mem_read_data_valid_r); + + +// pulse this signal +assign daddress_valid_p = i_daddress_valid && !daddress_valid_stop_r; + +always @( posedge i_clk ) + begin + uncached_wb_stop_r <= (uncached_wb_stop_r || (uncached_data_access_p&&!cache_stall)) && (i_fetch_stall || o_mem_stall); + cached_wb_stop_r <= (cached_wb_stop_r || cached_wb_req) && (i_fetch_stall || o_mem_stall); + daddress_valid_stop_r <= (daddress_valid_stop_r || daddress_valid_p) && (i_fetch_stall || o_mem_stall); + // hold this until the mem access completes + mem_stall_r <= o_mem_stall; + end + + +assign wb_stop = uncached_wb_stop_r || cached_wb_stop_r; + +always @( posedge i_clk ) + if ( !wb_stop || o_mem_stall ) + begin + mem_read_data_r <= mem_read_data_c; + mem_load_rd_r <= mem_load_rd_c; + mem_read_data_valid_r <= mem_read_data_valid_c; + end + + +// ====================================== +// L1 Data Cache +// ====================================== +a25_dcache u_dcache ( + .i_clk ( i_clk ), + .i_request ( sel_cache_p ), + .i_exclusive ( i_exclusive ), + .i_write_data ( i_write_data ), + .i_write_enable ( i_write_enable ), + .i_address ( i_daddress ), + .i_address_nxt ( i_daddress_nxt ), + .i_byte_enable ( i_byte_enable ), + .i_cache_enable ( i_cache_enable ), + .i_cache_flush ( i_cache_flush ), + .i_fetch_stall ( i_fetch_stall ), + .i_exec_stall ( i_exec_stall ), + .i_wb_cached_rdata ( i_wb_cached_rdata ), + .i_wb_cached_ready ( i_wb_cached_ready ), + + .o_read_data ( cache_read_data ), + .o_stall ( cache_stall ), + .o_wb_cached_req ( cached_wb_req ) + +); + + + +endmodule + + + + +module a25_write_back( + i_clk, + i_mem_stall, + + i_mem_read_data, + i_mem_read_data_valid, + i_mem_load_rd, + + o_wb_read_data, + o_wb_read_data_valid, + o_wb_load_rd, + + i_daddress, +// i_daddress_valid + ); + +input i_clk; +input i_mem_stall; // Mem stage asserting stall + +input [31:0] i_mem_read_data; // data reads +input i_mem_read_data_valid; // read data is valid +input [10:0] i_mem_load_rd; // Rd for data reads + +output [31:0] o_wb_read_data; // data reads +output o_wb_read_data_valid; // read data is valid +output [10:0] o_wb_load_rd; // Rd for data reads + +input [31:0] i_daddress; +//input i_daddress_valid; + +reg [31:0] mem_read_data_r = 32'd0; // Register read data from Data Cache +reg mem_read_data_valid_r = 1'd0; // Register read data from Data Cache +reg [10:0] mem_load_rd_r = 11'd0; // Register the Rd value for loads + +assign o_wb_read_data = mem_read_data_r; +assign o_wb_read_data_valid = mem_read_data_valid_r; +assign o_wb_load_rd = mem_load_rd_r; + + +always @( posedge i_clk ) + if ( !i_mem_stall ) + begin + mem_read_data_r <= i_mem_read_data; + mem_read_data_valid_r <= i_mem_read_data_valid; + mem_load_rd_r <= i_mem_load_rd; + end + + +// Used by a25_decompile.v, so simulation only +//synopsys translate_off +reg [31:0] daddress_r = 32'd0; // Register read data from Data Cache +always @( posedge i_clk ) + if ( !i_mem_stall ) + daddress_r <= i_daddress; +//synopsys translate_on + +endmodule + + + + module a25_wishbone_buf ( + i_clk, + +// Core side + i_req, + i_write, + i_wdata, + i_be, + i_addr, + o_rdata, + o_ack, + +// Wishbone side + o_valid, + i_accepted, + o_write, + o_wdata, + o_be, + o_addr, + i_rdata, + i_rdata_valid + ); + +input i_clk; + +// Core side +input i_req; +input i_write; +input [127:0] i_wdata; +input [15:0] i_be; +input [31:0] i_addr; +output [127:0] o_rdata; +output o_ack; + +// Wishbone side +output o_valid; +input i_accepted; +output o_write; +output [127:0] o_wdata; +output [15:0] o_be; +output [31:0] o_addr; +input [127:0] i_rdata; +input i_rdata_valid; + +// ---------------------------------------------------- +// Signals +// ---------------------------------------------------- +reg [1:0] wbuf_used_r = 2'd0; +//reg [31:0] wbuf_addr_r [1:0]; +reg [31:0] wbuf_addr_r0; +reg [31:0] wbuf_addr_r1; +//reg [127:0] wbuf_wdata_r [1:0]; +reg [127:0] wbuf_wdata_r0; +reg [127:0] wbuf_wdata_r1; +//reg [15:0] wbuf_be_r [1:0]; +reg [15:0] wbuf_be_r0; +reg [15:0] wbuf_be_r1; +reg [1:0] wbuf_write_r = 2'd0; +reg wbuf_wp_r = 1'd0; // write buf write pointer +reg wbuf_rp_r = 1'd0; // write buf read pointer +reg busy_reading_r = 1'd0; +reg wait_rdata_valid_r = 1'd0; +wire in_wreq; +reg ack_owed_r = 1'd0; +reg push; //wire to reg +reg pop; //wire to reg + +// ---------------------------------------------------- +// Access Buffer +// ---------------------------------------------------- +assign in_wreq = i_req && i_write; +assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted)); +assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0; + +always @(posedge i_clk) + if (push && pop) + wbuf_used_r <= wbuf_used_r; + else if (push) + wbuf_used_r <= wbuf_used_r + 1'd1; + else if (pop) + wbuf_used_r <= wbuf_used_r - 1'd1; + +always @(posedge i_clk) + if (push && in_wreq && !o_ack) + ack_owed_r <= 1'd1; + else if (!i_req && o_ack) + ack_owed_r <= 1'd0; + +always @(posedge i_clk) + if (push) + begin + if ( wbuf_wp_r == 1'd0) + begin + wbuf_wdata_r0 <= i_wdata; + wbuf_addr_r0 <= i_addr; + wbuf_be_r0 <= i_write ? i_be : 16'hffff; + wbuf_write_r [0] <= i_write; + end + + + else if ( wbuf_wp_r == 1'd1) + begin + wbuf_wdata_r1 <= i_wdata; + wbuf_addr_r1 <= i_addr; + wbuf_be_r1 <= i_write ? i_be : 16'hffff; + wbuf_write_r [1] <= i_write; + end + + wbuf_wp_r <= !wbuf_wp_r; + end + +always @(posedge i_clk) + if (pop) + wbuf_rp_r <= !wbuf_rp_r; + + +// ---------------------------------------------------- +// Output logic +// ---------------------------------------------------- +//assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata; +assign o_wdata = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_wdata_r0 : wbuf_wdata_r1 ) : i_wdata; + +//assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write; +assign o_write = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_write_r[0] : wbuf_write_r[1]) : i_write; + +//assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr; +assign o_addr = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_addr_r0 : wbuf_addr_r1 ) : i_addr; + +//assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff; +assign o_be = wbuf_used_r != 2'd0 ? (wbuf_rp_r == 1'd0 ? wbuf_be_r0 : wbuf_be_r1) : i_write ? i_be : 16'hffff; + +assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop); + +assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r; + +assign o_rdata = i_rdata; + + +always@(posedge i_clk) + if (o_valid && !o_write) + busy_reading_r <= 1'd1; + else if (i_rdata_valid) + busy_reading_r <= 1'd0; + +always@(posedge i_clk) + if (o_valid && !o_write && i_accepted) + wait_rdata_valid_r <= 1'd1; + else if (i_rdata_valid) + wait_rdata_valid_r <= 1'd0; +endmodule + + + +module a25_wishbone( + i_clk, + + i_port0_req, + o_port0_ack, + i_port0_write, + i_port0_wdata, + i_port0_be, + i_port0_addr, + o_port0_rdata, + + i_port1_req, + o_port1_ack, + i_port1_write, + i_port1_wdata, + i_port1_be, + i_port1_addr, + o_port1_rdata, + + i_port2_req, + o_port2_ack, + i_port2_write, + i_port2_wdata, + i_port2_be, + i_port2_addr, + o_port2_rdata, + + + o_wb_adr, + o_wb_sel, + o_wb_we, + o_wb_dat, + o_wb_cyc, + o_wb_stb, + i_wb_dat, + i_wb_ack +// i_wb_err + ); + + +// ---------------------------------------------------- +// Parameters +// ---------------------------------------------------- +localparam WBUF = 3; + +input i_clk; + + +// Port 0 - dcache uncached +input i_port0_req; +output o_port0_ack; +input i_port0_write; +input [127:0] i_port0_wdata; +input [15:0] i_port0_be; +input [31:0] i_port0_addr; +output [127:0] o_port0_rdata; + +// Port 1 - dcache cached +input i_port1_req; +output o_port1_ack; +input i_port1_write; +input [127:0] i_port1_wdata; +input [15:0] i_port1_be; +input [31:0] i_port1_addr; +output [127:0] o_port1_rdata; + +// Port 2 - instruction cache accesses, read only +input i_port2_req; +output o_port2_ack; +input i_port2_write; +input [127:0] i_port2_wdata; +input [15:0] i_port2_be; +input [31:0] i_port2_addr; +output [127:0] o_port2_rdata; + + +// 128-bit Wishbone Bus +output [31:0] o_wb_adr; +output [15:0] o_wb_sel; +output o_wb_we; +output [127:0] o_wb_dat; +output o_wb_cyc; +output o_wb_stb; +input [127:0] i_wb_dat; +input i_wb_ack; +//input i_wb_err; + +// ---------------------------------------------------- +// Signals +// ---------------------------------------------------- + +reg o_wb_adr = 32'd0; +reg o_wb_sel = 16'd0; +reg o_wb_we = 1'd0; +reg o_wb_dat = 128'd0; +reg o_wb_cyc = 1'd0; +reg o_wb_stb = 1'd0; +wire [WBUF-1:0] wbuf_valid; +wire [WBUF-1:0] wbuf_accepted; +wire [WBUF-1:0] wbuf_write; +//wire [127:0] wbuf_wdata [WBUF-1:0]; +//wire [15:0] wbuf_be [WBUF-1:0]; +//wire [31:0] wbuf_addr [WBUF-1:0]; +wire [127:0] wbuf_wdata0; +wire [127:0] wbuf_wdata1; +wire [127:0] wbuf_wdata2; +wire [15:0] wbuf_be0; +wire [15:0] wbuf_be1; +wire [15:0] wbuf_be2; +wire [31:0] wbuf_addr0; +wire [31:0] wbuf_addr1; +wire [31:0] wbuf_addr2; +wire [WBUF-1:0] wbuf_rdata_valid; +wire new_access; +reg [WBUF-1:0] serving_port = 3'd0; + + +// ---------------------------------------------------- +// Instantiate the write buffers +// ---------------------------------------------------- + +a25_wishbone_buf u_wishbone_buf_p0 ( + .i_clk ( i_clk ), + + .i_req ( i_port0_req ), + .i_write ( i_port0_write ), + .i_wdata ( i_port0_wdata ), + .i_be ( i_port0_be ), + .i_addr ( i_port0_addr ), + .o_rdata ( o_port0_rdata ), + .o_ack ( o_port0_ack ), + + .o_valid ( wbuf_valid [0] ), + .i_accepted ( wbuf_accepted [0] ), + .o_write ( wbuf_write [0] ), + .o_wdata ( wbuf_wdata0 ), + .o_be ( wbuf_be0 ), + .o_addr ( wbuf_addr0 ), + .i_rdata ( i_wb_dat ), + .i_rdata_valid ( wbuf_rdata_valid [0] ) + ); + + +a25_wishbone_buf u_wishbone_buf_p1 ( + .i_clk ( i_clk ), + + .i_req ( i_port1_req ), + .i_write ( i_port1_write ), + .i_wdata ( i_port1_wdata ), + .i_be ( i_port1_be ), + .i_addr ( i_port1_addr ), + .o_rdata ( o_port1_rdata ), + .o_ack ( o_port1_ack ), + + .o_valid ( wbuf_valid [1] ), + .i_accepted ( wbuf_accepted [1] ), + .o_write ( wbuf_write [1] ), + .o_wdata ( wbuf_wdata1 ), + .o_be ( wbuf_be1 ), + .o_addr ( wbuf_addr1 ), + .i_rdata ( i_wb_dat ), + .i_rdata_valid ( wbuf_rdata_valid [1] ) + ); + + +a25_wishbone_buf u_wishbone_buf_p2 ( + .i_clk ( i_clk ), + + .i_req ( i_port2_req ), + .i_write ( i_port2_write ), + .i_wdata ( i_port2_wdata ), + .i_be ( i_port2_be ), + .i_addr ( i_port2_addr ), + .o_rdata ( o_port2_rdata ), + .o_ack ( o_port2_ack ), + + .o_valid ( wbuf_valid [2] ), + .i_accepted ( wbuf_accepted [2] ), + .o_write ( wbuf_write [2] ), + .o_wdata ( wbuf_wdata2 ), + .o_be ( wbuf_be2 ), + .o_addr ( wbuf_addr2 ), + .i_rdata ( i_wb_dat ), + .i_rdata_valid ( wbuf_rdata_valid [2] ) + ); + + +assign new_access = !o_wb_stb || i_wb_ack; + +assign wbuf_accepted[0] = new_access && wbuf_valid[0]; +assign wbuf_accepted[1] = new_access && !wbuf_valid[0] && wbuf_valid[1]; +assign wbuf_accepted[2] = new_access && !wbuf_valid[0] && !wbuf_valid[1] && wbuf_valid[2]; + +//always @(posedge i_clk) +// begin + +// wbuf_accepted[0] <= new_access && wbuf_valid[0]; + +// wbuf_accepted[1] <= new_access && !wbuf_valid[0] && wbuf_valid[1]; + +// wbuf_accepted[2] <= new_access && !wbuf_valid[0] && !wbuf_valid[1] && wbuf_valid[2]; + +// end + + +always @(posedge i_clk) + begin + if (new_access) + begin + if (wbuf_valid[0]) + begin + o_wb_adr <= wbuf_addr0; + o_wb_sel <= wbuf_be0; + o_wb_we <= wbuf_write[0]; + o_wb_dat <= wbuf_wdata0; + o_wb_cyc <= 1'd1; + o_wb_stb <= 1'd1; + serving_port <= 3'b001; + end + else if (wbuf_valid[1]) + begin + // o_wb_adr <= wbuf_addr [1]; + // o_wb_sel <= wbuf_be [1]; + // o_wb_we <= wbuf_write[1]; + // o_wb_dat <= wbuf_wdata[1]; + o_wb_adr <= wbuf_addr1; + o_wb_sel <= wbuf_be1; + o_wb_we <= wbuf_write[1]; + o_wb_dat <= wbuf_wdata1; + o_wb_cyc <= 1'd1; + o_wb_stb <= 1'd1; + serving_port <= 3'b010; + end + else if (wbuf_valid[2]) + begin + // o_wb_adr <= wbuf_addr [2]; + // o_wb_sel <= wbuf_be [2]; + // o_wb_we <= wbuf_write[2]; + // o_wb_dat <= wbuf_wdata[2]; + o_wb_adr <= wbuf_addr2; + o_wb_sel <= wbuf_be2; + o_wb_we <= wbuf_write[2]; + o_wb_dat <= wbuf_wdata2; + o_wb_cyc <= 1'd1; + o_wb_stb <= 1'd1; + serving_port <= 3'b100; + end + else + begin + o_wb_cyc <= 1'd0; + o_wb_stb <= 1'd0; + + // Don't need to change these values because they are ignored + // when stb is low, but it makes for a cleaner waveform, at the expense of a few gates + o_wb_we <= 1'd0; + o_wb_adr <= 32'd0; + o_wb_dat <= 128'd0; + + serving_port <= 3'b000; + end + end + end + + +assign {wbuf_rdata_valid[2], wbuf_rdata_valid[1], wbuf_rdata_valid[0]} = {3{i_wb_ack & ~ o_wb_we}} & serving_port; + + +endmodule + + + + + + +module a25_coprocessor( + i_clk, + i_core_stall, +// i_copro_opcode1, +// i_copro_opcode2, + i_copro_crn, +// i_copro_crm, +// i_copro_num, + i_copro_operation, + i_copro_write_data, + i_fault, + i_fault_status, + i_fault_address, + o_copro_read_data, + o_cache_enable, + o_cache_flush, + o_cacheable_area + ); + +/************************* IO Declarations *********************/ +input i_clk; +input i_core_stall; // stall all stages of the Amber core at the same time +//input [2:0] i_copro_opcode1; +//input [2:0] i_copro_opcode2; +input [3:0] i_copro_crn; // Register Number +//input [3:0] i_copro_crm; +//input [3:0] i_copro_num; +input [1:0] i_copro_operation; +input [31:0] i_copro_write_data; + +input i_fault; // high to latch the fault address and status +input [7:0] i_fault_status; +input [31:0] i_fault_address; // the address that caused the fault + +output [31:0] o_copro_read_data; +output o_cache_enable; +output o_cache_flush; +output [31:0] o_cacheable_area; + +/*********************** Signal Declarations *******************/ +reg [31:0] o_copro_read_data; +// Bit 0 - Cache on(1)/off +// Bit 1 - Shared (1) or seperate User/Supervisor address space +// Bit 2 - address monitor mode(1) +reg [2:0] cache_control = 3'b000; + +// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable +// Bit 1 - next 2MB region etc. +reg [31:0] cacheable_area = 32'h0; + +// Marks memory regions as read only so writes are ignored by the cache +// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable +// Bit 1 - next 2MB region etc. +reg [31:0] updateable_area = 32'h0; + +// Accesses to a region with a flag set in this register cause the +// cache to flush +// Bit 0 - 2MB memory from 0 to 0x01fffff +// Bit 1 - next 2MB region etc. +reg [31:0] disruptive_area = 32'h0; + + +reg [7:0] fault_status = 8'd0; +reg [31:0] fault_address = 32'b0; // the address that caused the fault + +wire copro15_reg1_write; + + +// --------------------------- +// Outputs +// --------------------------- +assign o_cache_enable = cache_control[0]; +assign o_cache_flush = copro15_reg1_write; +assign o_cacheable_area = cacheable_area; + +// --------------------------- +// Capture an access fault address and status +// --------------------------- +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + if ( i_fault ) + begin + + fault_status <= i_fault_status; + fault_address <= i_fault_address; + end + end + + +// --------------------------- +// Register Writes +// --------------------------- +always @ ( posedge i_clk ) + if ( !i_core_stall ) + begin + if ( i_copro_operation == 2'd2 ) + case ( i_copro_crn ) + 4'd2: cache_control <= i_copro_write_data[2:0]; + 4'd3: cacheable_area <= i_copro_write_data[31:0]; + 4'd4: updateable_area <= i_copro_write_data[31:0]; + 4'd5: disruptive_area <= i_copro_write_data[31:0]; + default: cache_control <=cache_control; + endcase + end + +// Flush the cache +assign copro15_reg1_write = !i_core_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1; + + +// --------------------------- +// Register Reads +// --------------------------- +always @ ( posedge i_clk ) + if ( !i_core_stall ) + case ( i_copro_crn ) + // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision + 4'd0: o_copro_read_data <= 32'h41560300; + 4'd2: o_copro_read_data <= {29'd0, cache_control}; + 4'd3: o_copro_read_data <= cacheable_area; + 4'd4: o_copro_read_data <= updateable_area; + 4'd5: o_copro_read_data <= disruptive_area; + 4'd6: o_copro_read_data <= {24'd0, fault_status }; + 4'd7: o_copro_read_data <= fault_address; + default: o_copro_read_data <= 32'd0; + endcase + + +endmodule + + + + + + module arm_core( + i_clk, + i_irq, + i_firq, + i_system_rdy, + i_wb_dat, + i_wb_ack, + i_wb_err, + + +//decode + +//coprocessor +// cache_enable, // Enabel the cache +// cache_flush, // Flush the cache +// cacheable_area, +//execute + +//wishbone + + +//write_back + + + + o_wb_adr, + o_wb_sel, + o_wb_we, + o_wb_dat, + o_wb_cyc, + o_wb_stb + ); + +input i_clk; + +input i_irq; // Interrupt request, active high +input i_firq; // Fast Interrupt request, active high + +input i_system_rdy; // Amber is stalled when this is low + +// Wishbone Master I/F +output [31:0] o_wb_adr; +output [15:0] o_wb_sel; +output o_wb_we; +input [127:0] i_wb_dat; +output [127:0] o_wb_dat; +output o_wb_cyc; +output o_wb_stb; +input i_wb_ack; //Used to terminate read and write accesses +input i_wb_err; + + +//decode + + +//coprocessor + +//input cache_enable; // Enabel the cache +//input cache_flush; // Flush the cache +//input [31:0] cacheable_area; + +//execute + + +//wishbone + + +//write_back + + + +wire [31:0] execute_iaddress; +wire execute_iaddress_valid; +wire [31:0] execute_iaddress_nxt; // un-registered version of execute_address + // to the instruction cache rams +wire [31:0] execute_daddress; +wire execute_daddress_valid; +wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress + // to the data cache rams +wire [31:0] write_data; +wire write_enable; +wire [31:0] fetch_instruction; +wire decode_exclusive; +wire decode_iaccess; +wire decode_daccess; +wire [3:0] byte_enable; +wire exclusive; // swap access +wire cache_enable; // Enabel the cache +wire cache_flush; // Flush the cache +wire [31:0] cacheable_area; + +wire fetch_stall; +wire mem_stall; +wire exec_stall; +wire core_stall; + +wire [1:0] status_bits_mode; +wire status_bits_irq_mask; +wire status_bits_firq_mask; +wire status_bits_flags_wen; +wire status_bits_mode_wen; +wire status_bits_irq_mask_wen; +wire status_bits_firq_mask_wen; +wire [31:0] execute_status_bits; + +wire [31:0] imm32; +wire [4:0] imm_shift_amount; +wire shift_imm_zero; +wire [3:0] condition; + +wire [3:0] rm_sel; +wire [3:0] rs_sel; +wire [7:0] decode_load_rd; +wire [8:0] exec_load_rd; +wire [3:0] rn_sel; +wire [1:0] barrel_shift_amount_sel; +wire [1:0] barrel_shift_data_sel; +wire [1:0] barrel_shift_function; +wire [8:0] alu_function; +wire [1:0] multiply_function; +wire [2:0] interrupt_vector_sel; +wire [3:0] iaddress_sel; +wire [3:0] daddress_sel; +wire [2:0] pc_sel; +wire [1:0] byte_enable_sel; +wire [2:0] status_bits_sel; +wire [2:0] reg_write_sel; +wire user_mode_regs_store_nxt; +wire firq_not_user_mode; + +wire write_data_wen; +wire copro_write_data_wen; +wire base_address_wen; +wire pc_wen; +wire [14:0] reg_bank_wen; + +wire [2:0] copro_opcode1; +wire [2:0] copro_opcode2; +wire [3:0] copro_crn; +wire [3:0] copro_crm; +wire [3:0] copro_num; +wire [1:0] copro_operation; +wire [31:0] copro_read_data; +wire [31:0] copro_write_data; +wire multiply_done; + +wire decode_fault; +wire iabt_trigger; +wire dabt_trigger; + +wire [7:0] decode_fault_status; +wire [7:0] iabt_fault_status; +wire [7:0] dabt_fault_status; + +wire [31:0] decode_fault_address; +wire [31:0] iabt_fault_address; +wire [31:0] dabt_fault_address; + +wire adex; + +wire [31:0] mem_read_data; +wire mem_read_data_valid; +wire [10:0] mem_load_rd; + +wire [31:0] wb_read_data; +wire wb_read_data_valid; +wire [10:0] wb_load_rd; + +wire dcache_wb_cached_req; +wire dcache_wb_uncached_req; +wire dcache_wb_write; +wire [15:0] dcache_wb_byte_enable; +wire [31:0] dcache_wb_address; +wire [127:0] dcache_wb_cached_rdata; +wire [127:0] dcache_wb_write_data; +wire dcache_wb_cached_ready; +wire dcache_wb_uncached_ready; +wire [31:0] icache_wb_address; +wire icache_wb_req; +wire [31:0] icache_wb_adr; +wire [127:0] icache_wb_read_data; +wire icache_wb_ready; + +wire conflict; +wire rn_use_read; +wire rm_use_read; +wire rs_use_read; +wire rd_use_read; +//jing+ +wire priviledged; +wire [127:0] port0_rdata; + +// data abort has priority +assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status; +assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address; +assign decode_fault = dabt_trigger | iabt_trigger; + +assign core_stall = fetch_stall || mem_stall || exec_stall; + + +// ====================================== +// Fetch Stage +// ====================================== +a25_fetch u_fetch ( + .i_clk ( i_clk ), + .i_mem_stall ( mem_stall ), + .i_exec_stall ( exec_stall ), + .i_conflict ( conflict ), + .o_fetch_stall ( fetch_stall ), + .i_system_rdy ( i_system_rdy ), + + // .i_iaddress ( {execute_iaddress[31:2], 2'd0} ), + .i_iaddress ( execute_iaddress ), + .i_iaddress_valid ( execute_iaddress_valid ), + .i_iaddress_nxt ( execute_iaddress_nxt ), + .o_fetch_instruction ( fetch_instruction ), + .i_cache_enable ( cache_enable ), + .i_cache_flush ( cache_flush ), + .i_cacheable_area ( cacheable_area ), + + .o_wb_req ( icache_wb_req ), + .o_wb_address ( icache_wb_address ), + .i_wb_read_data ( icache_wb_read_data ), + .i_wb_ready ( icache_wb_ready ) +); + + +// ====================================== +// Decode Stage +// ====================================== +a25_decode u_decode ( + .i_clk ( i_clk ), + .i_fetch_instruction ( fetch_instruction ), + .i_core_stall ( core_stall ), + .i_irq ( i_irq ), + .i_firq ( i_firq ), + .i_dabt ( 1'd0 ), + .i_iabt ( 1'd0 ), + .i_adex ( adex ), + + // Instruction fetch or data read signals + + .i_execute_iaddress ( execute_iaddress ), + // .i_execute_daddress ( execute_daddress ), + .i_abt_status ( 8'd0 ), + .i_execute_status_bits ( execute_status_bits ), + .i_multiply_done ( multiply_done ), + + .o_imm32 ( imm32 ), + .o_imm_shift_amount ( imm_shift_amount ), + .o_shift_imm_zero ( shift_imm_zero ), + .o_condition ( condition ), + .o_decode_exclusive ( decode_exclusive ), + .o_decode_iaccess ( decode_iaccess ), + .o_decode_daccess ( decode_daccess ), + .o_status_bits_mode ( status_bits_mode ), + .o_status_bits_irq_mask ( status_bits_irq_mask ), + .o_status_bits_firq_mask ( status_bits_firq_mask ), + + .o_rm_sel ( rm_sel ), + .o_rs_sel ( rs_sel ), + .o_load_rd ( decode_load_rd ), + + .o_rn_sel ( rn_sel ), + .o_barrel_shift_amount_sel ( barrel_shift_amount_sel ), + .o_barrel_shift_data_sel ( barrel_shift_data_sel ), + .o_barrel_shift_function ( barrel_shift_function ), + .o_alu_function ( alu_function ), + .o_multiply_function ( multiply_function ), + .o_interrupt_vector_sel ( interrupt_vector_sel ), + .o_iaddress_sel ( iaddress_sel ), + .o_daddress_sel ( daddress_sel ), + .o_pc_sel ( pc_sel ), + .o_byte_enable_sel ( byte_enable_sel ), + .o_status_bits_sel ( status_bits_sel ), + .o_reg_write_sel ( reg_write_sel ), + .o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), + .o_firq_not_user_mode ( firq_not_user_mode ), + .o_write_data_wen ( write_data_wen ), + .o_base_address_wen ( base_address_wen ), + .o_pc_wen ( pc_wen ), + .o_reg_bank_wen ( reg_bank_wen ), + .o_status_bits_flags_wen ( status_bits_flags_wen ), + .o_status_bits_mode_wen ( status_bits_mode_wen ), + .o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ), + .o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ), + + .o_copro_opcode1 ( copro_opcode1 ), + .o_copro_opcode2 ( copro_opcode2 ), + .o_copro_crn ( copro_crn ), + .o_copro_crm ( copro_crm ), + .o_copro_num ( copro_num ), + .o_copro_operation ( copro_operation ), + .o_copro_write_data_wen ( copro_write_data_wen ), + + .o_iabt_trigger ( iabt_trigger ), + .o_iabt_address ( iabt_fault_address ), + .o_iabt_status ( iabt_fault_status ), + .o_dabt_trigger ( dabt_trigger ), + .o_dabt_address ( dabt_fault_address ), + .o_dabt_status ( dabt_fault_status ), + + .o_conflict ( conflict ), + .o_rn_use_read ( rn_use_read ), + .o_rm_use_read ( rm_use_read ), + .o_rs_use_read ( rs_use_read ), + .o_rd_use_read ( rd_use_read ) +); + +// ====================================== +// Execute Stage +// ====================================== +a25_execute u_execute ( + .i_clk ( i_clk ), + .i_core_stall ( core_stall ), + .i_mem_stall ( mem_stall ), + .o_exec_stall ( exec_stall ), + + .i_wb_read_data ( wb_read_data ), + .i_wb_read_data_valid ( wb_read_data_valid ), + .i_wb_load_rd ( wb_load_rd ), + + .i_copro_read_data ( copro_read_data ), + .i_decode_iaccess ( decode_iaccess ), + .i_decode_daccess ( decode_daccess ), + .i_decode_load_rd ( decode_load_rd ), + .o_copro_write_data ( copro_write_data ), + .o_write_data ( write_data ), + .o_iaddress ( execute_iaddress ), + .o_iaddress_nxt ( execute_iaddress_nxt ), + .o_iaddress_valid ( execute_iaddress_valid ), + .o_daddress ( execute_daddress ), + .o_daddress_nxt ( execute_daddress_nxt ), + .o_daddress_valid ( execute_daddress_valid ), + + .o_adex ( adex ), + .o_priviledged ( priviledged ), + .o_exclusive ( exclusive ), + .o_write_enable ( write_enable ), + .o_byte_enable ( byte_enable ), + .o_exec_load_rd ( exec_load_rd ), + .o_status_bits ( execute_status_bits ), + .o_multiply_done ( multiply_done ), + + .i_status_bits_mode ( status_bits_mode ), + .i_status_bits_irq_mask ( status_bits_irq_mask ), + .i_status_bits_firq_mask ( status_bits_firq_mask ), + .i_imm32 ( imm32 ), + .i_imm_shift_amount ( imm_shift_amount ), + .i_shift_imm_zero ( shift_imm_zero ), + .i_condition ( condition ), + .i_decode_exclusive ( decode_exclusive ), + + .i_rm_sel ( rm_sel ), + .i_rs_sel ( rs_sel ), + + .i_rn_sel ( rn_sel ), + .i_barrel_shift_amount_sel ( barrel_shift_amount_sel ), + .i_barrel_shift_data_sel ( barrel_shift_data_sel ), + .i_barrel_shift_function ( barrel_shift_function ), + .i_alu_function ( alu_function ), + .i_multiply_function ( multiply_function ), + .i_interrupt_vector_sel ( interrupt_vector_sel ), + .i_iaddress_sel ( iaddress_sel ), + .i_daddress_sel ( daddress_sel ), + .i_pc_sel ( pc_sel ), + .i_byte_enable_sel ( byte_enable_sel ), + .i_status_bits_sel ( status_bits_sel ), + .i_reg_write_sel ( reg_write_sel ), + .i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), + .i_firq_not_user_mode ( firq_not_user_mode ), + .i_write_data_wen ( write_data_wen ), + .i_base_address_wen ( base_address_wen ), + .i_pc_wen ( pc_wen ), + .i_reg_bank_wen ( reg_bank_wen ), + .i_status_bits_flags_wen ( status_bits_flags_wen ), + .i_status_bits_mode_wen ( status_bits_mode_wen ), + .i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ), + .i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ), + .i_copro_write_data_wen ( copro_write_data_wen ), + .i_conflict ( conflict ), + .i_rn_use_read ( rn_use_read ), + .i_rm_use_read ( rm_use_read ), + .i_rs_use_read ( rs_use_read ), + .i_rd_use_read ( rd_use_read ) +); + + + +// ====================================== +// Memory access stage with data cache +// ====================================== +a25_mem u_mem ( + .i_clk ( i_clk ), + .i_fetch_stall ( fetch_stall ), + .i_exec_stall ( exec_stall ), + .o_mem_stall ( mem_stall ), + + .i_daddress ( execute_daddress ), + .i_daddress_valid ( execute_daddress_valid ), + .i_daddress_nxt ( execute_daddress_nxt ), + .i_write_data ( write_data ), + .i_write_enable ( write_enable ), + .i_exclusive ( exclusive ), + .i_byte_enable ( byte_enable ), + .i_exec_load_rd ( exec_load_rd ), + .i_cache_enable ( cache_enable ), + .i_cache_flush ( cache_flush ), + .i_cacheable_area ( cacheable_area ), + + .o_mem_read_data ( mem_read_data ), + .o_mem_read_data_valid ( mem_read_data_valid ), + .o_mem_load_rd ( mem_load_rd ), + + .o_wb_cached_req ( dcache_wb_cached_req ), + .o_wb_uncached_req ( dcache_wb_uncached_req ), + .o_wb_write ( dcache_wb_write ), + .o_wb_byte_enable ( dcache_wb_byte_enable ), + .o_wb_write_data ( dcache_wb_write_data ), + .o_wb_address ( dcache_wb_address ), + .i_wb_uncached_rdata ( dcache_wb_cached_rdata ), + .i_wb_cached_rdata ( dcache_wb_cached_rdata ), + .i_wb_cached_ready ( dcache_wb_cached_ready ), + .i_wb_uncached_ready ( dcache_wb_uncached_ready ) + +); + +// ====================================== +// Write back stage with data cache +// ====================================== +a25_write_back u_write_back ( + .i_clk ( i_clk ), + .i_mem_stall ( mem_stall ), + + .i_mem_read_data ( mem_read_data ), + .i_mem_read_data_valid ( mem_read_data_valid ), + .i_mem_load_rd ( mem_load_rd ), + + .o_wb_read_data ( wb_read_data ), + .o_wb_read_data_valid ( wb_read_data_valid ), + .o_wb_load_rd ( wb_load_rd ), + .i_daddress ( execute_daddress ) +// .i_daddress_valid ( execute_daddress_valid ) +); + + +// ====================================== +// Wishbone Master I/F +// ====================================== +a25_wishbone u_wishbone ( + // CPU Side + .i_clk ( i_clk ), + + // Port 0 - dcache uncached + .i_port0_req ( dcache_wb_uncached_req ), + .o_port0_ack ( dcache_wb_uncached_ready ), + .i_port0_write ( dcache_wb_write ), + .i_port0_wdata ( dcache_wb_write_data ), + .i_port0_be ( dcache_wb_byte_enable ), + .i_port0_addr ( dcache_wb_address ), + .o_port0_rdata ( port0_rdata ), //output [127:0] o_port0_rdata + + // Port 1 - dcache cached + .i_port1_req ( dcache_wb_cached_req ), + .o_port1_ack ( dcache_wb_cached_ready ), + .i_port1_write ( dcache_wb_write ), + .i_port1_wdata ( dcache_wb_write_data ), + .i_port1_be ( dcache_wb_byte_enable ), + .i_port1_addr ( dcache_wb_address ), + .o_port1_rdata ( dcache_wb_cached_rdata ), + + // Port 2 - instruction cache accesses, read only + .i_port2_req ( icache_wb_req ), + .o_port2_ack ( icache_wb_ready ), + .i_port2_write ( 1'd0 ), + .i_port2_wdata ( 128'd0 ), + .i_port2_be ( 16'd0 ), + .i_port2_addr ( icache_wb_address ), + .o_port2_rdata ( icache_wb_read_data ), + + // Wishbone + .o_wb_adr ( o_wb_adr ), + .o_wb_sel ( o_wb_sel ), + .o_wb_we ( o_wb_we ), + .o_wb_dat ( o_wb_dat ), + .o_wb_cyc ( o_wb_cyc ), + .o_wb_stb ( o_wb_stb ), + .i_wb_dat ( i_wb_dat ), + .i_wb_ack ( i_wb_ack ) +// .i_wb_err ( i_wb_err ) +); + +// ====================================== +// Co-Processor #15 +// ====================================== +a25_coprocessor u_coprocessor ( + .i_clk ( i_clk ), + .i_core_stall ( core_stall ), + +// .i_copro_opcode1 ( copro_opcode1 ), +// .i_copro_opcode2 ( copro_opcode2 ), + .i_copro_crn ( copro_crn ), +// .i_copro_crm ( copro_crm ), +// .i_copro_num ( copro_num ), + .i_copro_operation ( copro_operation ), + .i_copro_write_data ( copro_write_data ), + + .i_fault ( decode_fault ), + .i_fault_status ( decode_fault_status ), + .i_fault_address ( decode_fault_address ), + + .o_copro_read_data ( copro_read_data ), + .o_cache_enable ( cache_enable ), + .o_cache_flush ( cache_flush ), + .o_cacheable_area ( cacheable_area ) +); + + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/bgm.v b/openfpga_flow/benchmarks/vtr_benchmark/bgm.v new file mode 100755 index 000000000..dbb32256a --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/bgm.v @@ -0,0 +1,2659 @@ +// DEFINES +`define BITS 32 // Bit width of the operands +`define NumPath 34 + +module bgm(clock, + reset, + sigma_a, + sigma_b, + sigma_c, + Fn, + dw_x, + dw_y, + dw_z, + dt, + Fn_out +); + +// SIGNAL DECLARATIONS +input clock; +input reset; + +input [`BITS-1:0] sigma_a; +input [`BITS-1:0] sigma_b; +input [`BITS-1:0] sigma_c; +input [`BITS-1:0] Fn; +input [`BITS-1:0] dw_x; +input [`BITS-1:0] dw_y; +input [`BITS-1:0] dw_z; +input [`BITS-1:0] dt; + +output [`BITS-1:0] Fn_out; + +wire [`BITS-1:0] x0; +wire [`BITS-1:0] x1; +wire [`BITS-1:0] x2; +wire [`BITS-1:0] x3; +wire [`BITS-1:0] x4; +wire [`BITS-1:0] x5; +wire [`BITS-1:0] x6; +wire [`BITS-1:0] x7; +wire [`BITS-1:0] x8; +wire [`BITS-1:0] x9; +wire [`BITS-1:0] x10; + +wire [`BITS-1:0] a0; +wire [`BITS-1:0] a1; +wire [`BITS-1:0] a2; +wire [`BITS-1:0] a3; +wire [`BITS-1:0] a4; +wire [`BITS-1:0] a5; +wire [`BITS-1:0] a6; +wire [`BITS-1:0] a7; +wire [`BITS-1:0] a8; + +wire [`BITS-1:0] Fn_out; +wire [`BITS-1:0] Fn_delay_chain; +wire [`BITS-1:0] Fn_delay_chain_delay5; + +wire [`BITS-1:0] dw_x_delay; +wire [`BITS-1:0] dw_y_delay; +wire [`BITS-1:0] dw_z_delay; +wire [`BITS-1:0] sigma_a_delay; +wire [`BITS-1:0] sigma_b_delay; +wire [`BITS-1:0] sigma_c_delay; + +wire [`BITS-1:0] fifo_out1; +wire [`BITS-1:0] fifo_out2; +wire [`BITS-1:0] fifo_out3; + +wire [`BITS-1:0] a4_delay5; +/* +delay44 delay_u1(clock, dw_x, dw_x_delay); +delay44 delay_u2(clock, dw_y, dw_y_delay); +delay44 delay_u3(clock, dw_z, dw_z_delay); +delay44 delay_u4(clock, sigma_a, sigma_a_delay); +delay44 delay_u5(clock, sigma_b, sigma_b_delay); +delay44 delay_u6(clock, sigma_c, sigma_c_delay); + +fifo fifo_1(clock, a0, fifo_out1); +fifo fifo_2(clock, a1, fifo_out2); +fifo fifo_3(clock, a2, fifo_out3); +*/ + +delay5 delay_u1(clock, dw_x, dw_x_delay); +delay5 delay_u2(clock, dw_y, dw_y_delay); +delay5 delay_u3(clock, dw_z, dw_z_delay); +delay5 delay_u4(clock, sigma_a, sigma_a_delay); +delay5 delay_u5(clock, sigma_b, sigma_b_delay); +delay5 delay_u6(clock, sigma_c, sigma_c_delay); + +delay5 fifo_1(clock, a0, fifo_out1); +delay5 fifo_2(clock, a1, fifo_out2); +delay5 fifo_3(clock, a2, fifo_out3); + + + +//assign x0 = Fn * sigma_a; +wire [7:0] x0_control; +fpu_mul x0_mul +( + .clk(clock), + .opa(Fn), + .opb(sigma_a), + .out(x0), + .control(x0_control) +); + +//assign x1 = Fn * sigma_b; +wire [7:0] x1_control; +fpu_mul x1_mul +( + .clk(clock), + .opa(Fn), + .opb(sigma_b), + .out(x1), + .control(x1_control) +); + + +//assign x2 = Fn * sigma_c; +wire [7:0] x2_control; +fpu_mul x2_mul +( + .clk(clock), + .opa(Fn), + .opb(sigma_c), + .out(x2), + .control(x2_control) +); + +//assign a0 = x0 + fifo_out1; +wire [7:0] a0_control; +fpu_add a0_add +( + .clk(clock), + .opa(x0), + .opb(fifo_out1), + .out(a0), + .control(a0_control) +); + + +//assign a1 = x1 + fifo_out2; +wire [7:0] a1_control; +fpu_add a1_add +( + .clk(clock), + .opa(x1), + .opb(fifo_out2), + .out(a1), + .control(a1_control) +); + +//assign a2 = x2 + fifo_out3; +wire [7:0] a2_control; +fpu_add a2_add +( + .clk(clock), + .opa(x2), + .opb(fifo_out3), + .out(a2), + .control(a2_control) +); + +//assign x3 = dw_x_delay * sigma_a_delay; +wire [7:0] x3_control; +fpu_mul x3_mul +( + .clk(clock), + .opa(dw_x_delay), + .opb(sigma_a_delay), + .out(x3), + .control(x3_control) +); + + +//assign x4 = a0 * sigma_a_delay; +wire [7:0] x4_control; +fpu_mul x4_mul +( + .clk(clock), + .opa(a0), + .opb(sigma_a_delay), + .out(x4), + .control(x4_control) +); + + +//assign x5 = dw_y_delay * sigma_b_delay; +wire [7:0] x5_control; +fpu_mul x5_mul +( + .clk(clock), + .opa(dw_y_delay), + .opb(sigma_b_delay), + .out(x5), + .control(x5_control) +); + +//assign x6 = a1 * sigma_b_delay; +wire [7:0] x6_control; +fpu_mul x6_mul +( + .clk(clock), + .opa(a1), + .opb(sigma_b_delay), + .out(x6), + .control(x6_control) +); + +//assign x7 = dw_z_delay * sigma_c_delay; +wire [7:0] x7_control; +fpu_mul x7_mul +( + .clk(clock), + .opa(dw_z_delay), + .opb(sigma_c_delay), + .out(x7), + .control(x7_control) +); + +//assign x8 = a2 * sigma_c_delay; +wire [7:0] x8_control; +fpu_mul x8_mul +( + .clk(clock), + .opa(a2), + .opb(sigma_c_delay), + .out(x8), + .control(x8_control) +); + +//assign a3 = x3 + x5; +wire [7:0] a3_control; +fpu_add a3_add +( + .clk(clock), + .opa(x3), + .opb(x5), + .out(a3), + .control(a3_control) +); + +//assign a4 = a3 + x7; +wire [7:0] a4_control; +fpu_add a4_add +( + .clk(clock), + .opa(a3), + .opb(x7), + .out(a4), + .control(a4_control) +); + + +//assign a5 = x4 + x6; +wire [7:0] a5_control; +fpu_add a5_add +( + .clk(clock), + .opa(x4), + .opb(x6), + .out(a5), + .control(a5_control) +); + +//assign a6 = a5 + x8; +wire [7:0] a6_control; +fpu_add a6_add +( + .clk(clock), + .opa(a5), + .opb(x8), + .out(a6), + .control(a6_control) +); + +delay5 delay_a5(clock, a4, a4_delay5); + +//assign x9 = dt * a6; +wire [7:0] x9_control; +fpu_mul x9_mul +( + .clk(clock), + .opa(dt), + .opb(a6), + .out(x9), + .control(x9_control) +); + +//assign a7 = a4_delay5 + x9; +wire [7:0] a7_control; +fpu_add a7_add +( + .clk(clock), + .opa(a4_delay5), + .opb(x9), + .out(a7), + .control(a7_control) +); + + +//delay_chain delay_Fn(clock, Fn, Fn_delay_chain); +delay5 delay_Fn(clock, Fn, Fn_delay_chain); +delay5 delay_Fn_delay5(clock, Fn_delay_chain, Fn_delay_chain_delay5); + +//assign x10 = a7 * Fn_delay_chain; +wire [7:0] x10_control; +fpu_mul x10_mul +( + .clk(clock), + .opa(a7), + .opb(Fn_delay_chain), + .out(x10), + .control(x10_control) +); + +//assign a8 = Fn_delay_chain_delay5 + x10; +wire [7:0] a8_control; +fpu_add a8_add +( + .clk(clock), + .opa(Fn_delay_chain_delay5), + .opb(x10), + .out(a8), + .control(a8_control) +); + +assign Fn_out = a8; + + +endmodule + + + +/* +module fifo(clock, fifo_in, fifo_out); + input clock; + input [`BITS-1:0] fifo_in; + output [`BITS-1:0] fifo_out; + wire [`BITS-1:0] fifo_out; + + reg [`BITS-1:0] freg1; + + reg [`BITS-1:0] freg2; + reg [`BITS-1:0] freg3; + reg [`BITS-1:0] freg4; + reg [`BITS-1:0] freg5; + reg [`BITS-1:0] freg6; + reg [`BITS-1:0] freg7; + reg [`BITS-1:0] freg8; + reg [`BITS-1:0] freg9; + reg [`BITS-1:0] freg10; + reg [`BITS-1:0] freg11; + reg [`BITS-1:0] freg12; + reg [`BITS-1:0] freg13; + reg [`BITS-1:0] freg14; + reg [`BITS-1:0] freg15; + reg [`BITS-1:0] freg16; + reg [`BITS-1:0] freg17; + reg [`BITS-1:0] freg18; + reg [`BITS-1:0] freg19; + reg [`BITS-1:0] freg20; + reg [`BITS-1:0] freg21; + reg [`BITS-1:0] freg22; + reg [`BITS-1:0] freg23; + reg [`BITS-1:0] freg24; + reg [`BITS-1:0] freg25; + reg [`BITS-1:0] freg26; + reg [`BITS-1:0] freg27; + reg [`BITS-1:0] freg28; + reg [`BITS-1:0] freg29; + reg [`BITS-1:0] freg30; + reg [`BITS-1:0] freg31; + reg [`BITS-1:0] freg32; + reg [`BITS-1:0] freg33; + reg [`BITS-1:0] freg34; + + assign fifo_out = freg34; + + always @(posedge clock) + begin + freg1 <= fifo_in; + + freg2 <= freg1; + freg3 <= freg2; + freg4 <= freg3; + freg5 <= freg4; + freg6 <= freg5; + freg7 <= freg6; + freg8 <= freg7; + freg9 <= freg8; + freg10 <= freg9; + freg11 <= freg10; + freg12 <= freg11; + freg13 <= freg12; + freg14 <= freg13; + freg15 <= freg14; + freg16 <= freg15; + freg17 <= freg16; + freg18 <= freg17; + freg19 <= freg18; + freg20 <= freg19; + freg21 <= freg20; + freg22 <= freg21; + freg23 <= freg22; + freg24 <= freg23; + freg25 <= freg24; + freg26 <= freg25; + freg27 <= freg26; + freg28 <= freg27; + freg29 <= freg28; + freg30 <= freg29; + freg31 <= freg30; + freg32 <= freg31; + freg33 <= freg32; + freg34 <= freg33; + + end +endmodule +*/ + +module delay5 (clock, d5_delay_in, d5_delay_out); + input clock; + input [`BITS-1:0] d5_delay_in; + output [`BITS-1:0] d5_delay_out; + + //FIFO delay + reg [`BITS-1:0] d5_reg1; +/* + reg [`BITS-1:0] d5_reg2; + reg [`BITS-1:0] d5_reg3; + reg [`BITS-1:0] d5_reg4; + reg [`BITS-1:0] d5_reg5; + reg [`BITS-1:0] d5_reg6; +*/ + + assign d5_delay_out = d5_reg1; + + always @(posedge clock) + begin + d5_reg1 <= d5_delay_in; +/* + d5_reg2 <= d5_reg1; + d5_reg3 <= d5_reg2; + d5_reg4 <= d5_reg3; + d5_reg5 <= d5_reg4; + d5_reg6 <= d5_reg5; +*/ + end +endmodule + +/* +module delay44 (clock, delay_in, delay_out); + input clock; + input [`BITS-1:0] delay_in; + output [`BITS-1:0] delay_out; +// wire [`BITS-1:0] delay_out; + + //FIFO delay + wire [`BITS-1:0] fifo_out; + + //multiplier delay + wire [`BITS-1:0] delay5_dout1; + + //adder delay + wire [`BITS-1:0] delay5_dout2; + + fifo fifo_delay(clock, delay_in , fifo_out); + delay5 delay_d1(clock, fifo_out, delay5_dout1); + delay5 delay_d2(clock, delay5_dout1, delay5_dout2); + + assign delay_out = delay5_dout2; +// always @(posedge clock) +// begin +// fifo_out <= delay_in; +// delay5_dout1 <= fifo_out; +// delay5_dout2 <= delay5_dout1; +// end + +endmodule +*/ + +/* +module delay_chain (clock, delay_in, delay_out); + input clock; + input [`BITS-1:0] delay_in; + output [`BITS-1:0] delay_out; +// wire [`BITS-1:0] delay_out; + + wire [`BITS-1:0] delay44_out; + wire [`BITS-1:0] delay5_out1; + wire [`BITS-1:0] delay5_out2; + wire [`BITS-1:0] delay5_out3; + wire [`BITS-1:0] delay5_out4; + + delay44 delay_c1(clock, delay_in, delay44_out); + delay5 delay_c2(clock, delay44_out, delay5_out1); + delay5 delay_c3(clock, delay5_out1, delay5_out2); + delay5 delay_c4(clock, delay5_out2, delay5_out3); + delay5 delay_c5(clock, delay5_out3, delay5_out4); + + assign delay_out = delay5_out4; +endmodule +*/ + + +module fpu_mul( +clk, +//rmode, +opa, opb, out, +control +/* +inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero +*/ +); +input clk; +//input [1:0] rmode; +input [31:0] opa, opb; +output [31:0] out; +output [7:0] control; +/* +output inf, snan, qnan; +output ine; +output overflow, underflow; +output zero; +output div_by_zero; +*/ + + + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires +// +reg [2:0] fpu_op; +reg zero; +reg [31:0] opa_r, opb_r; // Input operand registers +reg [31:0] out; // Output register +reg div_by_zero; // Divide by zero output register +wire signa, signb; // alias to opX sign +wire sign_fasu; // sign output +wire [26:0] fracta, fractb; // Fraction Outputs from EQU block +wire [7:0] exp_fasu; // Exponent output from EQU block +reg [7:0] exp_r; // Exponent output (registerd) +wire [26:0] fract_out_d; // fraction output +wire co; // carry output +reg [27:0] fract_out_q; // fraction output (registerd) +wire [30:0] out_d; // Intermediate final result output +wire overflow_d, underflow_d;// Overflow/Underflow Indicators +reg overflow, underflow; // Output registers for Overflow & Underflow +reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN +reg ine; // Output Registers for INE +reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode + rmode_r3; +reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration + fpu_op_r3; +wire mul_inf, div_inf; +wire mul_00, div_00; +/* +parameter INF = 31'h7f800000; +parameter QNAN = 31'h7fc00001; +parameter SNAN = 31'h7f800001; + +*/ +wire [1:0] rmode; +assign rmode = 2'b00; + +wire [30:0] INF; +assign INF = 31'h7f800000; +wire [30:0] QNAN; +assign QNAN = 31'h7fc00001; +wire [30:0] SNAN; +assign SNAN = 31'h7f800001; + +// start output_reg +reg [31:0] out_o1; +reg inf_o1, snan_o1, qnan_o1; +reg ine_o1; +reg overflow_o1, underflow_o1; +reg zero_o1; +reg div_by_zero_o1; +// end output_reg + +wire [7:0] contorl; +assign control = {inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero}; + +//////////////////////////////////////////////////////////////////////// +// +// Input Registers +// + +always @(posedge clk) begin + fpu_op[2:0] <= 3'b010; +end + +always @(posedge clk) + opa_r <= opa; + +always @(posedge clk) + opb_r <= opb; + +always @(posedge clk) + rmode_r1 <= rmode; + +always @(posedge clk) + rmode_r2 <= rmode_r1; + +always @(posedge clk) + rmode_r3 <= rmode_r2; + +always @(posedge clk) + fpu_op_r1 <= fpu_op; + +always @(posedge clk) + fpu_op_r2 <= fpu_op_r1; + +always @(posedge clk) + fpu_op_r3 <= fpu_op_r2; + +//////////////////////////////////////////////////////////////////////// +// +// Exceptions block +// +wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan; +wire opa_00, opb_00; +wire opa_inf, opb_inf; +wire opa_dn, opb_dn; + +except u0( .clk(clk), + .opa(opa_r[30:0]), .opb(opb_r[30:0]), + .inf(inf_d), .ind(ind_d), + .qnan(qnan_d), .snan(snan_d), + .opa_nan(opa_nan), .opb_nan(opb_nan), + .opa_00(opa_00), .opb_00(opb_00), + .opa_inf(opa_inf), .opb_inf(opb_inf), + .opa_dn(opa_dn), .opb_dn(opb_dn) + ); + +//////////////////////////////////////////////////////////////////////// +// +// Pre-Normalize block +// - Adjusts the numbers to equal exponents and sorts them +// - determine result sign +// - determine actual operation to perform (add or sub) +// + +wire nan_sign_d, result_zero_sign_d; +reg sign_fasu_r; +wire [7:0] exp_mul; +wire sign_mul; +reg sign_mul_r; +wire [23:0] fracta_mul, fractb_mul; +wire inf_mul; +reg inf_mul_r; +wire [1:0] exp_ovf; +reg [1:0] exp_ovf_r; +wire sign_exe; +reg sign_exe_r; +wire [2:0] underflow_fmul_d; + +pre_norm_fmul u2( + .clk(clk), + .fpu_op(fpu_op_r1), + .opa(opa_r), .opb(opb_r), + .fracta(fracta_mul), + .fractb(fractb_mul), + .exp_out(exp_mul), // FMUL exponent output (registered) + .sign(sign_mul), // FMUL sign output (registered) + .sign_exe(sign_exe), // FMUL exception sign output (registered) + .inf(inf_mul), // FMUL inf output (registered) + .exp_ovf(exp_ovf), // FMUL exponnent overflow output (registered) + .underflow(underflow_fmul_d) + ); + +always @(posedge clk) + sign_mul_r <= sign_mul; + +always @(posedge clk) + sign_exe_r <= sign_exe; + +always @(posedge clk) + inf_mul_r <= inf_mul; + +always @(posedge clk) + exp_ovf_r <= exp_ovf; + + +//////////////////////////////////////////////////////////////////////// +// +// Mul +// +wire [47:0] prod; + +mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod)); + + +//////////////////////////////////////////////////////////////////////// +// +// Normalize Result +// +wire ine_d; +reg [47:0] fract_denorm; +wire [47:0] fract_div; +wire sign_d; +reg sign; +reg [30:0] opa_r1; +reg [47:0] fract_i2f; +reg opas_r1, opas_r2; +wire f2i_out_sign; + +always @(posedge clk) // Exponent must be once cycle delayed + exp_r <= exp_mul; + +always @(posedge clk) + opa_r1 <= opa_r[30:0]; + +//always @(fpu_op_r3 or prod) +always @(prod) + fract_denorm = prod; + +always @(posedge clk) + opas_r1 <= opa_r[31]; + +always @(posedge clk) + opas_r2 <= opas_r1; + +assign sign_d = sign_mul; + +always @(posedge clk) + sign <= (rmode_r2==2'h3) ? !sign_d : sign_d; + +wire or_result; +assign or_result = mul_00 | div_00; +post_norm u4( +//.clk(clk), // System Clock + .fpu_op(fpu_op_r3), // Floating Point Operation + .opas(opas_r2), // OPA Sign + .sign(sign), // Sign of the result + .rmode(rmode_r3), // Rounding mode + .fract_in(fract_denorm), // Fraction Input + .exp_in(exp_r), // Exponent Input + .exp_ovf(exp_ovf_r), // Exponent Overflow + .opa_dn(opa_dn), // Operand A Denormalized + .opb_dn(opb_dn), // Operand A Denormalized + .rem_00(1'b0), // Diveide Remainder is zero + .div_opa_ldz(5'b00000), // Divide opa leading zeros count +// .output_zero(mul_00 | div_00), // Force output to Zero + .output_zero(or_result), // Force output to Zero + .out(out_d), // Normalized output (un-registered) + .ine(ine_d), // Result Inexact output (un-registered) + .overflow(overflow_d), // Overflow output (un-registered) + .underflow(underflow_d), // Underflow output (un-registered) + .f2i_out_sign(f2i_out_sign) // F2I Output Sign + ); + +//////////////////////////////////////////////////////////////////////// +// +// FPU Outputs +// +wire [30:0] out_fixed; +wire output_zero_fasu; +wire output_zero_fdiv; +wire output_zero_fmul; +reg inf_mul2; +wire overflow_fasu; +wire overflow_fmul; +wire overflow_fdiv; +wire inf_fmul; +wire sign_mul_final; +wire out_d_00; +wire sign_div_final; +wire ine_mul, ine_mula, ine_div, ine_fasu; +wire underflow_fasu, underflow_fmul, underflow_fdiv; +wire underflow_fmul1; +reg [2:0] underflow_fmul_r; +reg opa_nan_r; + + + +always @(posedge clk) + inf_mul2 <= exp_mul == 8'hff; + + +// Force pre-set values for non numerical output +assign mul_inf = (fpu_op_r3==3'b010) & (inf_mul_r | inf_mul2) & (rmode_r3==2'h0); +assign div_inf = (fpu_op_r3==3'b011) & (opb_00 | opa_inf); + +assign mul_00 = (fpu_op_r3==3'b010) & (opa_00 | opb_00); +assign div_00 = (fpu_op_r3==3'b011) & (opa_00 | opb_inf); + +assign out_fixed = + ( (qnan_d | snan_d) | + (opa_inf & opb_00)| + (opb_inf & opa_00 ) + ) ? QNAN : INF; + +always @(posedge clk) + out_o1[30:0] <= (mul_inf | div_inf | inf_d | snan_d | qnan_d) ? out_fixed : out_d; + +assign out_d_00 = !(|out_d); + +assign sign_mul_final = (sign_exe_r & ((opa_00 & opb_inf) | (opb_00 & opa_inf))) ? !sign_mul_r : sign_mul_r; + +assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00); + +always @(posedge clk) +// out_o1[31] <= !(snan_d | qnan_d) ? sign_mul_final : nan_sign_d ; + out_o1[31] <= !(snan_d | qnan_d) & sign_mul_final; + +// Exception Outputs +assign ine_mula = ((inf_mul_r | inf_mul2 | opa_inf | opb_inf) & (rmode_r3==2'h1) & + !((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3[1]); + +assign ine_mul = (ine_mula | ine_d | inf_fmul | out_d_00 | overflow_d | underflow_d) & + !opa_00 & !opb_00 & !(snan_d | qnan_d | inf_d); + +always @(posedge clk) + ine_o1 <= ine_mul; + + +assign overflow_fmul = !inf_d & (inf_mul_r | inf_mul2 | overflow_d) & !(snan_d | qnan_d); + +always @(posedge clk) + overflow_o1 <= overflow_fmul; + +always @(posedge clk) + underflow_fmul_r <= underflow_fmul_d; + +wire out_d_compare1; +assign out_d_compare1 = (out_d[30:23]==8'b0); + +wire out_d_compare2; +assign out_d_compare2 = (out_d[22:0]==23'b0); +/* +assign underflow_fmul1 = underflow_fmul_r[0] | + (underflow_fmul_r[1] & underflow_d ) | + ((opa_dn | opb_dn) & out_d_00 & (prod!=0) & sign) | + (underflow_fmul_r[2] & ((out_d[30:23]==8'b0) | (out_d[22:0]==23'b0))); +*/ +assign underflow_fmul1 = underflow_fmul_r[0] | + (underflow_fmul_r[1] & underflow_d ) | + ((opa_dn | opb_dn) & out_d_00 & (prod!=48'b0) & sign) | + (underflow_fmul_r[2] & (out_d_compare1 | out_d_compare2)); + + +assign underflow_fmul = underflow_fmul1 & !(snan_d | qnan_d | inf_mul_r); +/* +always @(posedge clk) +begin + underflow_o1 <= 1'b0; + snan_o1 <= 1'b0; + qnan_o1 <= 1'b0; + inf_fmul <= 1'b0; + inf_o1 <= 1'b0; + zero_o1 <= 1'b0; + opa_nan_r <= 1'b0; + div_by_zero_o1 <= 1'b0; +end +assign output_zero_fmul = 1'b0; +*/ + + +always @(posedge clk) + underflow_o1 <= underflow_fmul; + +always @(posedge clk) + snan_o1 <= snan_d; + +// Status Outputs +always @(posedge clk) + qnan_o1 <= ( snan_d | qnan_d | + (((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010) + ); + +assign inf_fmul = (((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_inf) & + !((opa_inf & opb_00) | (opb_inf & opa_00 )) & + fpu_op_r3==3'b010; + +always @(posedge clk) +/* + inf_o1 <= fpu_op_r3[2] ? 1'b0 : + (!(qnan_d | snan_d) & + ( ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) | inf_fmul) + ); +*/ + inf_o1 <= !fpu_op_r3[2] & (!(qnan_d | snan_d) & + ( ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) | inf_fmul) + ); + +assign output_zero_fmul = (out_d_00 | opa_00 | opb_00) & + !(inf_mul_r | inf_mul2 | opa_inf | opb_inf | snan_d | qnan_d) & + !(opa_inf & opb_00) & !(opb_inf & opa_00); + +always @(posedge clk) + zero_o1 <= output_zero_fmul; + +always @(posedge clk) + opa_nan_r <= (!opa_nan) & (fpu_op_r2==3'b011) ; + +always @(posedge clk) + div_by_zero_o1 <= opa_nan_r & !opa_00 & !opa_inf & opb_00; + + +// output register +always @(posedge clk) +begin + qnan <= qnan_o1; + out <= out_o1; + inf <= inf_o1; + snan <= snan_o1; + //qnan <= qnan_o1; + ine <= ine_o1; + overflow <= overflow_o1; + underflow <= underflow_o1; + zero <= zero_o1; + div_by_zero <= div_by_zero_o1; +end +endmodule + + +//--------------------------------------------------------------------------------- +module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan, + opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn); +input clk; +input [30:0] opa, opb; +output inf, ind, qnan, snan, opa_nan, opb_nan; +output opa_00, opb_00; +output opa_inf, opb_inf; +output opa_dn; +output opb_dn; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +wire [7:0] expa, expb; // alias to opX exponent +wire [22:0] fracta, fractb; // alias to opX fraction +reg expa_ff, infa_f_r, qnan_r_a, snan_r_a; +reg expb_ff, infb_f_r, qnan_r_b, snan_r_b; +reg inf, ind, qnan, snan; // Output registers +reg opa_nan, opb_nan; +reg expa_00, expb_00, fracta_00, fractb_00; +reg opa_00, opb_00; +reg opa_inf, opb_inf; +reg opa_dn, opb_dn; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign expa = opa[30:23]; +assign expb = opb[30:23]; +assign fracta = opa[22:0]; +assign fractb = opb[22:0]; + +//////////////////////////////////////////////////////////////////////// +// +// Determine if any of the input operators is a INF or NAN or any other special number +// + +always @(posedge clk) + expa_ff <= &expa; + +always @(posedge clk) + expb_ff <= &expb; + +always @(posedge clk) + infa_f_r <= !(|fracta); + +always @(posedge clk) + infb_f_r <= !(|fractb); + +always @(posedge clk) + qnan_r_a <= fracta[22]; + +always @(posedge clk) + snan_r_a <= !fracta[22] & |fracta[21:0]; + +always @(posedge clk) + qnan_r_b <= fractb[22]; + +always @(posedge clk) + snan_r_b <= !fractb[22] & |fractb[21:0]; + +always @(posedge clk) + ind <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r); + +always @(posedge clk) + inf <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r); + +always @(posedge clk) + qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b); + +always @(posedge clk) + snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b); + +always @(posedge clk) + opa_nan <= &expa & (|fracta[22:0]); + +always @(posedge clk) + opb_nan <= &expb & (|fractb[22:0]); + +always @(posedge clk) + opa_inf <= (expa_ff & infa_f_r); + +always @(posedge clk) + opb_inf <= (expb_ff & infb_f_r); + +always @(posedge clk) + expa_00 <= !(|expa); + +always @(posedge clk) + expb_00 <= !(|expb); + +always @(posedge clk) + fracta_00 <= !(|fracta); + +always @(posedge clk) + fractb_00 <= !(|fractb); + +always @(posedge clk) + opa_00 <= expa_00 & fracta_00; + +always @(posedge clk) + opb_00 <= expb_00 & fractb_00; + +always @(posedge clk) + opa_dn <= expa_00; + +always @(posedge clk) + opb_dn <= expb_00; + +endmodule + + + + +//--------------------------------------------------------------------------------- +module pre_norm_fmul(clk, fpu_op, opa, opb, fracta, fractb, exp_out, sign, + sign_exe, inf, exp_ovf, underflow); +input clk; +input [2:0] fpu_op; +input [31:0] opa, opb; +output [23:0] fracta, fractb; +output [7:0] exp_out; +output sign, sign_exe; +output inf; +output [1:0] exp_ovf; +output [2:0] underflow; + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +reg [7:0] exp_out; +wire signa, signb; +reg sign, sign_d; +reg sign_exe; +reg inf; +wire [1:0] exp_ovf_d; +reg [1:0] exp_ovf; +wire [7:0] expa, expb; +wire [7:0] exp_tmp1, exp_tmp2; +wire co1, co2; +wire expa_dn, expb_dn; +wire [7:0] exp_out_a; +wire opa_00, opb_00, fracta_00, fractb_00; +wire [7:0] exp_tmp3, exp_tmp4, exp_tmp5; +wire [2:0] underflow_d; +reg [2:0] underflow; +wire op_div; +wire [7:0] exp_out_mul, exp_out_div; + +assign op_div = (fpu_op == 3'b011); +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// +assign signa = opa[31]; +assign signb = opb[31]; +assign expa = opa[30:23]; +assign expb = opb[30:23]; + +//////////////////////////////////////////////////////////////////////// +// +// Calculate Exponenet +// + +assign expa_dn = !(|expa); +assign expb_dn = !(|expb); +assign opa_00 = !(|opa[30:0]); +assign opb_00 = !(|opb[30:0]); +assign fracta_00 = !(|opa[22:0]); +assign fractb_00 = !(|opb[22:0]); + +assign fracta[22:0] = opa[22:0]; +assign fractb[22:0] = opb[22:0]; +assign fracta[23:23] = !expa_dn; +assign fractb[23:23] = !expb_dn; +//assign fracta = {!expa_dn,opa[22:0]}; // Recover hidden bit +//assign fractb = {!expb_dn,opb[22:0]}; // Recover hidden bit + +assign {co1,exp_tmp1} = op_div ? ({1'b0,expa[7:0]} - {1'b0,expb[7:0]}) : ({1'b0,expa[7:0]} + {1'b0,expb[7:0]}); +assign {co2,exp_tmp2} = op_div ? ({co1,exp_tmp1} + 9'h07f) : ({co1,exp_tmp1} - 9'h07f); +assign exp_tmp3 = exp_tmp2 + 8'h01; +assign exp_tmp4 = 8'h7f - exp_tmp1; +assign exp_tmp5 = op_div ? (exp_tmp4+8'h01) : (exp_tmp4-8'h01); + + +always@(posedge clk) + exp_out <= op_div ? exp_out_div : exp_out_mul; + +assign exp_out_div = (expa_dn | expb_dn) ? (co2 ? exp_tmp5 : exp_tmp3 ) : co2 ? exp_tmp4 : exp_tmp2; +assign exp_out_mul = exp_ovf_d[1] ? exp_out_a : (expa_dn | expb_dn) ? exp_tmp3 : exp_tmp2; +assign exp_out_a = (expa_dn | expb_dn) ? exp_tmp5 : exp_tmp4; +assign exp_ovf_d[0] = op_div ? (expa[7] & !expb[7]) : (co2 & expa[7] & expb[7]); +assign exp_ovf_d[1] = op_div ? co2 : ((!expa[7] & !expb[7] & exp_tmp2[7]) | co2); + +always @(posedge clk) + exp_ovf <= exp_ovf_d; + +assign underflow_d[0] = (exp_tmp1 < 8'h7f) & !co1 & !(opa_00 | opb_00 | expa_dn | expb_dn); +assign underflow_d[1] = ((expa[7] | expb[7]) & !opa_00 & !opb_00) | + (expa_dn & !fracta_00) | (expb_dn & !fractb_00); +assign underflow_d[2] = !opa_00 & !opb_00 & (exp_tmp1 == 8'h7f); + +always @(posedge clk) + underflow <= underflow_d; + +always @(posedge clk) + inf <= op_div ? (expb_dn & !expa[7]) : ({co1,exp_tmp1} > 9'h17e) ; + + +//////////////////////////////////////////////////////////////////////// +// +// Determine sign for the output +// + +// sign: 0=Posetive Number; 1=Negative Number +always @(signa or signb) + case({signa, signb}) // synopsys full_case parallel_case + 2'b00: sign_d = 0; + 2'b01: sign_d = 1; + 2'b10: sign_d = 1; + 2'b11: sign_d = 0; + endcase + +always @(posedge clk) + sign <= sign_d; + +always @(posedge clk) + sign_exe <= signa & signb; + +endmodule + +//---------------------------------------------------------------------------- +//////////////////////////////////////////////////////////////////////// +// +// Multiply +// + +module mul_r2(clk, opa, opb, prod); +input clk; +input [23:0] opa, opb; +output [47:0] prod; + +reg [47:0] prod1, prod; + +always @(posedge clk) + prod1 <= opa * opb; + +always @(posedge clk) + prod <= prod1; + +endmodule + + + +//---------------------------------------------------------------------------- + + +module post_norm( fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf, + opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out, + ine, overflow, underflow, f2i_out_sign); + input [2:0] fpu_op; + input opas; + input sign; + input [1:0] rmode; + input [47:0] fract_in; + input [7:0] exp_in; + input [1:0] exp_ovf; + input opa_dn, opb_dn; + input rem_00; + input [4:0] div_opa_ldz; + input output_zero; + output [30:0] out; + output ine; + output overflow, underflow; + output f2i_out_sign; + + //////////////////////////////////////////////////////////////////////// + // + // Local Wires and registers + // + + wire [22:0] fract_out; + wire [7:0] exp_out; + wire [30:0] out; + wire exp_out1_co, overflow, underflow; + wire [22:0] fract_out_final; + reg [22:0] fract_out_rnd; + wire [8:0] exp_next_mi; + wire dn; + wire exp_rnd_adj; + wire [7:0] exp_out_final; + reg [7:0] exp_out_rnd; + wire op_dn; + + wire op_mul; + wire op_div; + wire op_i2f; + wire op_f2i; + + + //reg [5:0] fi_ldz; + wire [5:0] fi_ldz; + + wire g, r, s; + wire round, round2, round2a, round2_fasu, round2_fmul; + wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a; + wire [22:0] fract_out_rnd0, fract_out_rnd1, fract_out_rnd2, fract_out_rnd2a; + wire exp_rnd_adj0, exp_rnd_adj2a; + wire r_sign; + wire ovf0, ovf1; + wire [23:0] fract_out_pl1; + wire [7:0] exp_out_pl1, exp_out_mi1; + wire exp_out_00, exp_out_fe, exp_out_ff, exp_in_00, exp_in_ff; + wire exp_out_final_ff, fract_out_7fffff; + wire [24:0] fract_trunc; + wire [7:0] exp_out1; + wire grs_sel; + wire fract_out_00, fract_in_00; + wire shft_co; + wire [8:0] exp_in_pl1, exp_in_mi1; + wire [47:0] fract_in_shftr; + wire [47:0] fract_in_shftl; + + // for block shifter + wire [47:0] fract_in_shftr_1; + wire [47:0] fract_in_shftl_1; + // end for block shifter + + wire [7:0] exp_div; + wire [7:0] shft2; + wire [7:0] exp_out1_mi1; + wire div_dn; + wire div_nr; + wire grs_sel_div; + + wire div_inf; + wire [6:0] fi_ldz_2a; + wire [7:0] fi_ldz_2; + wire [7:0] div_shft1, div_shft2, div_shft3, div_shft4; + wire div_shft1_co; + wire [8:0] div_exp1; + wire [7:0] div_exp2, div_exp3; + wire left_right, lr_mul, lr_div; + wire [7:0] shift_right, shftr_mul, shftr_div; + wire [7:0] shift_left, shftl_mul, shftl_div; + wire [7:0] fasu_shift; + wire [7:0] exp_fix_div; + + wire [7:0] exp_fix_diva, exp_fix_divb; + wire [5:0] fi_ldz_mi1; + wire [5:0] fi_ldz_mi22; + wire exp_zero; + wire [6:0] ldz_all; + wire [7:0] ldz_dif; + + wire [8:0] div_scht1a; + wire [7:0] f2i_shft; + wire [55:0] exp_f2i_1; + wire f2i_zero, f2i_max; + wire [7:0] f2i_emin; + wire [7:0] conv_shft; + wire [7:0] exp_i2f, exp_f2i, conv_exp; + wire round2_f2i; + + + assign op_mul = fpu_op[2:0]==3'b010; + assign op_div = fpu_op[2:0]==3'b011; + assign op_i2f = fpu_op[2:0]==3'b100; + assign op_f2i = fpu_op[2:0]==3'b101; + assign op_dn = opa_dn | opb_dn; + + pri_encoder u6( + .fract_in (fract_in), + .fi_ldz (fi_ldz) + ); + + // --------------------------------------------------------------------- + // Normalize + + wire exp_in_80; + wire rmode_00, rmode_01, rmode_10, rmode_11; + + // Misc common signals + assign exp_in_ff = &exp_in; + assign exp_in_00 = !(|exp_in); + assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]); + assign exp_out_ff = &exp_out; + assign exp_out_00 = !(|exp_out); + assign exp_out_fe = &exp_out[7:1] & !exp_out[0]; + assign exp_out_final_ff = &exp_out_final; + + assign fract_out_7fffff = &fract_out; + assign fract_out_00 = !(|fract_out); + assign fract_in_00 = !(|fract_in); + + assign rmode_00 = (rmode==2'b00); + assign rmode_01 = (rmode==2'b01); + assign rmode_10 = (rmode==2'b10); + assign rmode_11 = (rmode==2'b11); + + // Fasu Output will be denormalized ... + assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) ); + + // --------------------------------------------------------------------- + // Fraction Normalization + wire[7:0] f2i_emax; + assign f2i_emax = 8'h9d; + //parameter f2i_emax = 8'h9d; + + // Incremented fraction for rounding + assign fract_out_pl1 = {1'b0, fract_out} + 24'h000001; + + // Special Signals for f2i + assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f; + assign f2i_zero = (!opas & (exp_inf2i_emax)) | (opas & (exp_inf2i_emax)) | (opas & (exp_in8'h16); + + assign f2i_shft = exp_in-8'h7d; + + // Select shifting direction + assign left_right = op_div ? lr_div : op_mul ? lr_mul :1'b1; + + assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1'b1 : + (op_dn & exp_ovf[1]) ? 1'b0 : + (op_dn & div_shft1_co) ? 1'b0 : + (op_dn & exp_out_00) ? 1'b1 : + (!op_dn & exp_out_00 & !exp_ovf[1]) ? 1'b1 : + exp_ovf[1] ? 1'b0 : + 1'b1; + assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1'b1 : + ( exp_ovf[1] | exp_in_00 ) ? 1'b0 : + 1'b1; + + // Select Left and Right shift value + assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h02 : exp_in_pl1[7:0]) : {2'h0, fi_ldz}; + assign shift_right = op_div ? shftr_div : shftr_mul; + + assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz}; + + assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift; + + assign shftl_mul = (shft_co | + (!exp_ovf[1] & exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz}; + + assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] : + (!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] : + {2'h0, fi_ldz}; + assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 : + (op_dn & div_shft1_co) ? div_shft4 : div_shft2; + // Do the actual shifting + //assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0]; + //assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<>shift_right[5:0]; + + + b_left_shifter u7( + .shift_in (fract_in), + .shift_value (shift_left[5:0]), + .shift_out (fract_in_shftl_1) + ); + + assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 48'b0 : fract_in_shftl_1; // fract_in<f2i_emax) ? 1'b0 : opas) : + ((exp_inf2i_emax) ? 1'b1 : opas); + + assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 8'h00) : (8'h9e-{2'b0, fi_ldz}); + + //assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<8'hfe) )) ? div_exp2 : + (opa_dn | (exp_in_00 & !exp_ovf[1]) ) ? 8'h00 : + exp_out1_mi1; + + assign div_inf = opb_dn & !opa_dn & (div_exp1[7:0] < 8'h7f); + + // --------------------------------------------------------------------- + // Round + + // Extract rounding (GRS) bits + assign grs_sel_div = op_div & (exp_ovf[1] | div_dn | exp_out1_co | exp_out_00); + + assign g = grs_sel_div ? fract_out[0] : fract_out[0]; + assign r = grs_sel_div ? (fract_trunc[24] & !div_nr) : fract_trunc[24]; + assign s = grs_sel_div ? |fract_trunc[24:0] : (|fract_trunc[23:0] | (fract_trunc[24] & op_div)); + + // Round to nearest even + assign round = (g & r) | (r & s) ; + assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out}; + assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out; + assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i; + + // round to zero + assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out; + assign exp_fix_div = (fi_ldz>6'd22) ? exp_fix_diva : exp_fix_divb; + assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) : (exp_out_ff & !op_f2i) ? exp_in : exp_out; + assign ovf1 = exp_out_ff & !dn; + + // round to +inf (UP) and -inf (DOWN) + assign r_sign = sign; + + assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff); + assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a)); + + assign round2_fmul = !r_sign & + ( + (exp_ovf[1] & !fract_in_00 & + ( ((!exp_out1_co | op_dn) & (r | s | (!rem_00 & op_div) )) | fract_out_00 | (!op_dn & !op_div)) + ) | + ( + (r | s | (!rem_00 & op_div)) & ( + (!exp_ovf[1] & (exp_in_80 | !exp_ovf[0])) | op_div | + ( exp_ovf[1] & !exp_ovf[0] & exp_out1_co) + ) + ) + ); + + //assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc)); + wire temp_fract_in; + assign temp_fract_in = |fract_in[23:0]; + assign round2_f2i = rmode_10 & (( temp_fract_in & !opas & (exp_in<8'h80 )) | (|fract_trunc)); + + assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu; + + assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out}; + assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out; + + assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a; + assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a; + + + // Choose rounding mode + + always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2) + case(rmode) // synopsys full_case parallel_case + 2'b00: exp_out_rnd = exp_out_rnd0; + 2'b01: exp_out_rnd = exp_out_rnd1; + 2'b10: exp_out_rnd = exp_out_rnd2; + 2'b11: exp_out_rnd = exp_out_rnd2; + endcase + + always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2) + case (rmode) // synopsys full_case parallel_case + 2'b00: fract_out_rnd = fract_out_rnd0; + 2'b01: fract_out_rnd = fract_out_rnd1; + 2'b10: fract_out_rnd = fract_out_rnd2; + 2'b11: fract_out_rnd = fract_out_rnd2; + endcase + + // --------------------------------------------------------------------- + // Final Output Mux + // Fix Output for denormalized and special numbers + wire max_num, inf_out; + + assign max_num = ( !rmode_00 & (op_mul | op_div ) & ( + ( exp_ovf[1] & exp_ovf[0]) | + (!exp_ovf[1] & !exp_ovf[0] & exp_in_ff & (fi_ldz_2<8'd24) & (exp_out!=8'hfe) ) + ) + ) | + + ( op_div & ( + ( rmode_01 & ( div_inf | + (exp_out_ff & !exp_ovf[1] ) | + (exp_ovf[1] & exp_ovf[0] ) + ) + ) | + + ( rmode[1] & !exp_ovf[1] & ( + ( exp_ovf[0] & exp_in_ff & r_sign & fract_in[47] + ) | + + ( r_sign & ( + (fract_in[47] & div_inf) | + (exp_in[7] & !exp_out_rnd[7] & !exp_in_80 & exp_out!=8'h7f ) | + (exp_in[7] & exp_out_rnd[7] & r_sign & exp_out_ff & op_dn & + div_exp1>9'h0fe ) + ) + ) | + + ( exp_in_00 & r_sign & ( + div_inf | + (r_sign & exp_out_ff & fi_ldz_2<8'h18) + ) + ) + ) + ) + ) + ); + + + assign inf_out = (rmode[1] & (op_mul | op_div) & !r_sign & ( (exp_in_ff & !op_div) | + (exp_ovf[1] & exp_ovf[0] & (exp_in_00 | exp_in[7]) ) + ) + ) | (div_inf & op_div & ( + rmode_00 | + (rmode[1] & !exp_in_ff & !exp_ovf[1] & !exp_ovf[0] & !r_sign ) | + (rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign) + ) + ) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 8'd24) & (exp_out_rnd!=8'hfe) ); + + assign fract_out_final = (inf_out | ovf0 | output_zero ) ? 23'h000000 : + (max_num | (f2i_max & op_f2i) ) ? 23'h7fffff : + fract_out_rnd; + + assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero ) ? 8'h00 : + ((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff : + max_num ? 8'hfe : + exp_out_rnd; + + + // --------------------------------------------------------------------- + // Pack Result + + assign out = {exp_out_final, fract_out_final}; + + // --------------------------------------------------------------------- + // Exceptions + wire underflow_fmul; + wire overflow_fdiv; + wire undeflow_div; + + wire z; + assign z = shft_co | ( exp_ovf[1] | exp_in_00) | + (!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00)); + + assign underflow_fmul = ( (|fract_trunc) & z & !exp_in_ff ) | + (fract_out_00 & !fract_in_00 & exp_ovf[1]); + + + assign undeflow_div = !(exp_ovf[1] & exp_ovf[0] & rmode_00) & !inf_out & !max_num & exp_out_final!=8'hff & ( + + ((|fract_trunc) & !opb_dn & ( + ( op_dn & !exp_ovf[1] & exp_ovf[0]) | + ( op_dn & exp_ovf[1]) | + ( op_dn & div_shft1_co) | + exp_out_00 | + exp_ovf[1] + ) + + ) | + + ( exp_ovf[1] & !exp_ovf[0] & ( + ( op_dn & exp_in>8'h16 & fi_ldz<6'd23) | + ( op_dn & exp_in<8'd23 & fi_ldz<6'd23 & !rem_00) | + ( !op_dn & (exp_in[7]==exp_div[7]) & !rem_00) | + ( !op_dn & exp_in_00 & (exp_div[7:1]==7'h7f) ) | + ( !op_dn & exp_in<8'h7f & exp_in>8'h20 ) + ) + ) | + + (!exp_ovf[1] & !exp_ovf[0] & ( + ( op_dn & fi_ldz<6'd23 & exp_out_00) | + ( exp_in_00 & !rem_00) | + ( !op_dn & ldz_all<7'd23 & exp_in==8'h01 & exp_out_00 & !rem_00) + ) + ) + + ); + + assign underflow = op_div ? undeflow_div : op_mul ? underflow_fmul : (!fract_in[47] & exp_out1_co) & !dn; + + assign overflow_fdiv = inf_out | + (!rmode_00 & max_num) | + (exp_in[7] & op_dn & exp_out_ff) | + (exp_ovf[0] & (exp_ovf[1] | exp_out_ff) ); + + assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1); + + wire f2i_ine; + assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) | + (|fract_trunc) | + (f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) | + (f2i_max & rmode_11 & (exp_in<8'h80)); + + + + assign ine = op_f2i ? f2i_ine : + op_i2f ? (|fract_trunc) : + ((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00)); +endmodule + +//------------------------------------------------------------------------------------- + +module pri_encoder ( fract_in, fi_ldz ); + +input [47:0] fract_in; +output [5:0] fi_ldz; +reg [5:0] fi_ldz_r0; + +assign fi_ldz = fi_ldz_r0; + +always @(fract_in) +begin + if (fract_in[47:47] == 1'b1) + fi_ldz_r0 = 6'd1; + else if (fract_in[47:46] == 2'b01) + fi_ldz_r0 = 6'd2; + else if (fract_in[47:45] == 3'b001) + fi_ldz_r0 = 6'd3; + else if (fract_in[47:44] == 4'b0001) + fi_ldz_r0 = 6'd4; + else if (fract_in[47:43] == 5'b00001) + fi_ldz_r0 = 6'd5; + else if (fract_in[47:42] == 6'b000001) + fi_ldz_r0 = 6'd6; + else if (fract_in[47:41] == 7'b0000001) + fi_ldz_r0 = 6'd7; + else if (fract_in[47:40] == 8'b00000001) + fi_ldz_r0 = 6'd8; + else if (fract_in[47:39] == 9'b000000001) + fi_ldz_r0 = 6'd9; + else if (fract_in[47:38] == 10'b0000000001) + fi_ldz_r0 = 6'd10; + else if (fract_in[47:37] == 11'b00000000001) + fi_ldz_r0 = 6'd11; + else if (fract_in[47:36] == 12'b000000000001) + fi_ldz_r0 = 6'd12; + else if (fract_in[47:35] == 13'b0000000000001) + fi_ldz_r0 = 6'd13; + else if (fract_in[47:34] == 14'b00000000000001) + fi_ldz_r0 = 6'd14; + else if (fract_in[47:33] == 15'b000000000000001) + fi_ldz_r0 = 6'd15; + else if (fract_in[47:32] == 16'b0000000000000001) + fi_ldz_r0 = 6'd16; + else if (fract_in[47:31] == 17'b00000000000000001) + fi_ldz_r0 = 6'd17; + else if (fract_in[47:30] == 18'b000000000000000001) + fi_ldz_r0 = 6'd18; + else if (fract_in[47:29] == 19'b0000000000000000001) + fi_ldz_r0 = 6'd19; + else if (fract_in[47:28] == 20'b00000000000000000001) + fi_ldz_r0 = 6'd20; + else if (fract_in[47:27] == 21'b000000000000000000001) + fi_ldz_r0 = 6'd21; + else if (fract_in[47:26] == 22'b0000000000000000000001) + fi_ldz_r0 = 6'd22; + else if (fract_in[47:25] == 23'b00000000000000000000001) + fi_ldz_r0 = 6'd23; + else if (fract_in[47:24] == 24'b000000000000000000000001) + fi_ldz_r0 = 6'd24; + else if (fract_in[47:23] == 25'b0000000000000000000000001) + fi_ldz_r0 = 6'd25; + else if (fract_in[47:22] == 26'b00000000000000000000000001) + fi_ldz_r0 = 6'd26; + else if (fract_in[47:21] == 27'b000000000000000000000000001) + fi_ldz_r0 = 6'd27; + else if (fract_in[47:20] == 28'b0000000000000000000000000001) + fi_ldz_r0 = 6'd28; + else if (fract_in[47:19] == 29'b00000000000000000000000000001) + fi_ldz_r0 = 6'd29; + else if (fract_in[47:18] == 30'b000000000000000000000000000001) + fi_ldz_r0 = 6'd30; + else if (fract_in[47:17] == 31'b0000000000000000000000000000001) + fi_ldz_r0 = 6'd31; + else if (fract_in[47:16] == 32'b00000000000000000000000000000001) + fi_ldz_r0 = 6'd32; + else if (fract_in[47:15] == 33'b000000000000000000000000000000001) + fi_ldz_r0 = 6'd33; + else if (fract_in[47:14] == 34'b0000000000000000000000000000000001) + fi_ldz_r0 = 6'd34; + else if (fract_in[47:13] == 35'b00000000000000000000000000000000001) + fi_ldz_r0 = 6'd35; + else if (fract_in[47:12] == 36'b000000000000000000000000000000000001) + fi_ldz_r0 = 6'd36; + else if (fract_in[47:11] == 37'b0000000000000000000000000000000000001) + fi_ldz_r0 = 6'd37; + else if (fract_in[47:10] == 38'b00000000000000000000000000000000000001) + fi_ldz_r0 = 6'd38; + else if (fract_in[47:9] == 39'b000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd39; + else if (fract_in[47:8] == 40'b0000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd40; + else if (fract_in[47:7] == 41'b00000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd41; + else if (fract_in[47:6] == 42'b000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd42; + else if (fract_in[47:5] == 43'b0000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd43; + else if (fract_in[47:4] == 44'b00000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd44; + else if (fract_in[47:3] == 45'b000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd45; + else if (fract_in[47:2] == 46'b0000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd46; + else if (fract_in[47:1] == 47'b00000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd47; + else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000001) + fi_ldz_r0 = 6'd48; + else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000000) + fi_ldz_r0 = 6'd48; +end + +endmodule + + +module b_right_shifter ( + shift_in, + shift_value, + shift_out +); + +input [47:0] shift_in; +input [5:0] shift_value; +output [47:0] shift_out; +reg [47:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 6'b000000: shift_out = shift_in; + 6'b000001: shift_out = shift_in >> 1; + 6'b000010: shift_out = shift_in >> 2; + 6'b000011: shift_out = shift_in >> 3; + 6'b000100: shift_out = shift_in >> 4; + 6'b000101: shift_out = shift_in >> 5; + 6'b000110: shift_out = shift_in >> 6; + 6'b000111: shift_out = shift_in >> 7; + 6'b001000: shift_out = shift_in >> 8; + 6'b001001: shift_out = shift_in >> 9; + 6'b001010: shift_out = shift_in >> 10; + 6'b001011: shift_out = shift_in >> 11; + 6'b001100: shift_out = shift_in >> 12; + 6'b001101: shift_out = shift_in >> 13; + 6'b001110: shift_out = shift_in >> 14; + 6'b001111: shift_out = shift_in >> 15; + 6'b010000: shift_out = shift_in >> 16; + 6'b010001: shift_out = shift_in >> 17; + 6'b010010: shift_out = shift_in >> 18; + 6'b010011: shift_out = shift_in >> 19; + 6'b010100: shift_out = shift_in >> 20; + 6'b010101: shift_out = shift_in >> 21; + 6'b010110: shift_out = shift_in >> 22; + 6'b010111: shift_out = shift_in >> 23; + 6'b011000: shift_out = shift_in >> 24; + 6'b011001: shift_out = shift_in >> 25; + 6'b011010: shift_out = shift_in >> 26; + 6'b011011: shift_out = shift_in >> 27; + 6'b011100: shift_out = shift_in >> 28; + 6'b011101: shift_out = shift_in >> 29; + 6'b011110: shift_out = shift_in >> 30; + 6'b011111: shift_out = shift_in >> 31; + 6'b100000: shift_out = shift_in >> 32; + 6'b100001: shift_out = shift_in >> 33; + 6'b100010: shift_out = shift_in >> 34; + 6'b100011: shift_out = shift_in >> 35; + 6'b100100: shift_out = shift_in >> 36; + 6'b100101: shift_out = shift_in >> 37; + 6'b100110: shift_out = shift_in >> 38; + 6'b100111: shift_out = shift_in >> 39; + 6'b101000: shift_out = shift_in >> 40; + 6'b101001: shift_out = shift_in >> 41; + 6'b101010: shift_out = shift_in >> 42; + 6'b101011: shift_out = shift_in >> 43; + 6'b101100: shift_out = shift_in >> 44; + 6'b101101: shift_out = shift_in >> 45; + 6'b101110: shift_out = shift_in >> 46; + 6'b101111: shift_out = shift_in >> 47; + 6'b110000: shift_out = shift_in >> 48; + + endcase +end + +//assign shift_out = shift_in >> shift_value; + +endmodule + +module b_left_shifter ( + shift_in, + shift_value, + shift_out +); + +input [47:0] shift_in; +input [5:0] shift_value; +output [47:0] shift_out; +reg [47:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 6'b000000: shift_out = shift_in; + 6'b000001: shift_out = shift_in << 1; + 6'b000010: shift_out = shift_in << 2; + 6'b000011: shift_out = shift_in << 3; + 6'b000100: shift_out = shift_in << 4; + 6'b000101: shift_out = shift_in << 5; + 6'b000110: shift_out = shift_in << 6; + 6'b000111: shift_out = shift_in << 7; + 6'b001000: shift_out = shift_in << 8; + 6'b001001: shift_out = shift_in << 9; + 6'b001010: shift_out = shift_in << 10; + 6'b001011: shift_out = shift_in << 11; + 6'b001100: shift_out = shift_in << 12; + 6'b001101: shift_out = shift_in << 13; + 6'b001110: shift_out = shift_in << 14; + 6'b001111: shift_out = shift_in << 15; + 6'b010000: shift_out = shift_in << 16; + 6'b010001: shift_out = shift_in << 17; + 6'b010010: shift_out = shift_in << 18; + 6'b010011: shift_out = shift_in << 19; + 6'b010100: shift_out = shift_in << 20; + 6'b010101: shift_out = shift_in << 21; + 6'b010110: shift_out = shift_in << 22; + 6'b010111: shift_out = shift_in << 23; + 6'b011000: shift_out = shift_in << 24; + 6'b011001: shift_out = shift_in << 25; + 6'b011010: shift_out = shift_in << 26; + 6'b011011: shift_out = shift_in << 27; + 6'b011100: shift_out = shift_in << 28; + 6'b011101: shift_out = shift_in << 29; + 6'b011110: shift_out = shift_in << 30; + 6'b011111: shift_out = shift_in << 31; + 6'b100000: shift_out = shift_in << 32; + 6'b100001: shift_out = shift_in << 33; + 6'b100010: shift_out = shift_in << 34; + 6'b100011: shift_out = shift_in << 35; + 6'b100100: shift_out = shift_in << 36; + 6'b100101: shift_out = shift_in << 37; + 6'b100110: shift_out = shift_in << 38; + 6'b100111: shift_out = shift_in << 39; + 6'b101000: shift_out = shift_in << 40; + 6'b101001: shift_out = shift_in << 41; + 6'b101010: shift_out = shift_in << 42; + 6'b101011: shift_out = shift_in << 43; + 6'b101100: shift_out = shift_in << 44; + 6'b101101: shift_out = shift_in << 45; + 6'b101110: shift_out = shift_in << 46; + 6'b101111: shift_out = shift_in << 47; + 6'b110000: shift_out = shift_in << 48; + + endcase +end + +endmodule + + +module b_left_shifter_new ( + shift_in, + shift_value, + shift_out +); + +input [55:0] shift_in; +input [5:0] shift_value; +output [55:0] shift_out; +reg [55:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 6'b000000: shift_out = shift_in; + 6'b000001: shift_out = shift_in << 1; + 6'b000010: shift_out = shift_in << 2; + 6'b000011: shift_out = shift_in << 3; + 6'b000100: shift_out = shift_in << 4; + 6'b000101: shift_out = shift_in << 5; + 6'b000110: shift_out = shift_in << 6; + 6'b000111: shift_out = shift_in << 7; + 6'b001000: shift_out = shift_in << 8; + 6'b001001: shift_out = shift_in << 9; + 6'b001010: shift_out = shift_in << 10; + 6'b001011: shift_out = shift_in << 11; + 6'b001100: shift_out = shift_in << 12; + 6'b001101: shift_out = shift_in << 13; + 6'b001110: shift_out = shift_in << 14; + 6'b001111: shift_out = shift_in << 15; + 6'b010000: shift_out = shift_in << 16; + 6'b010001: shift_out = shift_in << 17; + 6'b010010: shift_out = shift_in << 18; + 6'b010011: shift_out = shift_in << 19; + 6'b010100: shift_out = shift_in << 20; + 6'b010101: shift_out = shift_in << 21; + 6'b010110: shift_out = shift_in << 22; + 6'b010111: shift_out = shift_in << 23; + 6'b011000: shift_out = shift_in << 24; + 6'b011001: shift_out = shift_in << 25; + 6'b011010: shift_out = shift_in << 26; + 6'b011011: shift_out = shift_in << 27; + 6'b011100: shift_out = shift_in << 28; + 6'b011101: shift_out = shift_in << 29; + 6'b011110: shift_out = shift_in << 30; + 6'b011111: shift_out = shift_in << 31; + 6'b100000: shift_out = shift_in << 32; + 6'b100001: shift_out = shift_in << 33; + 6'b100010: shift_out = shift_in << 34; + 6'b100011: shift_out = shift_in << 35; + 6'b100100: shift_out = shift_in << 36; + 6'b100101: shift_out = shift_in << 37; + 6'b100110: shift_out = shift_in << 38; + 6'b100111: shift_out = shift_in << 39; + 6'b101000: shift_out = shift_in << 40; + 6'b101001: shift_out = shift_in << 41; + 6'b101010: shift_out = shift_in << 42; + 6'b101011: shift_out = shift_in << 43; + 6'b101100: shift_out = shift_in << 44; + 6'b101101: shift_out = shift_in << 45; + 6'b101110: shift_out = shift_in << 46; + 6'b101111: shift_out = shift_in << 47; + 6'b110000: shift_out = shift_in << 48; + 6'b110001: shift_out = shift_in << 49; + 6'b110010: shift_out = shift_in << 50; + 6'b110011: shift_out = shift_in << 51; + 6'b110100: shift_out = shift_in << 52; + 6'b110101: shift_out = shift_in << 53; + 6'b110110: shift_out = shift_in << 54; + 6'b110111: shift_out = shift_in << 55; + 6'b111000: shift_out = shift_in << 56; + endcase +end + +endmodule + +module fpu_add( clk, +//rmode, +opa, opb, out, +control +//inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero +); + input clk; + //input [1:0] rmode; + //input [2:0] fpu_op; + input [31:0] opa, opb; + output [31:0] out; + /* + output inf, snan, qnan; + output ine; + output overflow, underflow; + output zero; + output div_by_zero; + */ + output [7:0] control; + /* + parameter INF = 31'h7f800000; + parameter QNAN = 31'h7fc00001; + parameter SNAN = 31'h7f800001; + + */ + + wire [30:0] INF; + assign INF = 31'h7f800000; + wire [30:0] QNAN; + assign QNAN = 31'h7fc00001; + wire [30:0] SNAN; + assign SNAN = 31'h7f800001; + + //////////////////////////////////////////////////////////////////////// + // + // Local Wires + // + reg [2:0] fpu_op; + reg zero; + reg [31:0] opa_r, opb_r; // Input operand registers + reg [31:0] out; // Output register + reg div_by_zero; // Divide by zero output register + // wire signa, signb; // alias to opX sign + wire sign_fasu; // sign output + wire [26:0] fracta, fractb; // Fraction Outputs from EQU block + wire [7:0] exp_fasu; // Exponent output from EQU block + reg [7:0] exp_r; // Exponent output (registerd) + wire [26:0] fract_out_d; // fraction output + // wire co; // carry output + reg [27:0] fract_out_q; // fraction output (registerd) + wire [30:0] out_d; // Intermediate final result output + wire overflow_d, underflow_d;// Overflow/Underflow Indicators + reg overflow, underflow; // Output registers for Overflow & Underflow + reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN + reg ine; // Output Registers for INE + reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode + rmode_r3; + reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration + fpu_op_r3; + // wire mul_inf, div_inf; + // wire mul_00, div_00; + + + // start output_reg + reg [31:0] out_o1; + reg inf_o1, snan_o1, qnan_o1; + reg ine_o1; + reg overflow_o1, underflow_o1; + reg zero_o1; + reg div_by_zero_o1; + // end output_reg + wire [7:0] contorl; + assign control = {inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero}; + wire [1:0] rmode; + assign rmode= 2'b00; + + + always@(posedge clk) + begin + fpu_op[2:0] <= 3'b000; + end + //////////////////////////////////////////////////////////////////////// + // + // Input Registers + // + + always @(posedge clk) + opa_r <= opa; + + always @(posedge clk) + opb_r <= opb; + + always @(posedge clk) + rmode_r1 <= rmode; + + always @(posedge clk) + rmode_r2 <= rmode_r1; + + always @(posedge clk) + rmode_r3 <= rmode_r2; + + always @(posedge clk) + fpu_op_r1 <= fpu_op; + + always @(posedge clk) + fpu_op_r2 <= fpu_op_r1; + + always @(posedge clk) + fpu_op_r3 <= fpu_op_r2; + + //////////////////////////////////////////////////////////////////////// + // + // Exceptions block + // + wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan; + wire opa_00, opb_00; + wire opa_inf, opb_inf; + wire opa_dn, opb_dn; + + except u0( .clk(clk), + .opa(opa_r), .opb(opb_r), + .inf(inf_d), .ind(ind_d), + .qnan(qnan_d), .snan(snan_d), + .opa_nan(opa_nan), .opb_nan(opb_nan), + .opa_00(opa_00), .opb_00(opb_00), + .opa_inf(opa_inf), .opb_inf(opb_inf), + .opa_dn(opa_dn), .opb_dn(opb_dn) + ); + + //////////////////////////////////////////////////////////////////////// + // + // Pre-Normalize block + // - Adjusts the numbers to equal exponents and sorts them + // - determine result sign + // - determine actual operation to perform (add or sub) + // + + wire nan_sign_d, result_zero_sign_d; + reg sign_fasu_r; + wire fasu_op; + + wire add_input; + assign add_input=!fpu_op_r1[0]; + pre_norm u1(.clk(clk), // System Clock + .rmode(rmode_r2), // Roundin Mode + // .add(!fpu_op_r1[0]), // Add/Sub Input + .add(add_input), + .opa(opa_r), .opb(opb_r), // Registered OP Inputs + .opa_nan(opa_nan), // OpA is a NAN indicator + .opb_nan(opb_nan), // OpB is a NAN indicator + .fracta_out(fracta), // Equalized and sorted fraction + .fractb_out(fractb), // outputs (Registered) + .exp_dn_out(exp_fasu), // Selected exponent output (registered); + .sign(sign_fasu), // Encoded output Sign (registered) + .nan_sign(nan_sign_d), // Output Sign for NANs (registered) + .result_zero_sign(result_zero_sign_d), // Output Sign for zero result (registered) + .fasu_op(fasu_op) // Actual fasu operation output (registered) + ); + + always @(posedge clk) + sign_fasu_r <= sign_fasu; + + wire co_d; + //////////////////////////////////////////////////////////////////////// + // + // Add/Sub + // + + add_sub27 u3( + .add(fasu_op), // Add/Sub + .opa(fracta), // Fraction A input + .opb(fractb), // Fraction B Input + .sum(fract_out_d), // SUM output + .co(co_d) ); // Carry Output + + always @(posedge clk) + fract_out_q <= {co_d, fract_out_d}; + + + //////////////////////////////////////////////////////////////////////// + // + // Normalize Result + // + wire ine_d; + //reg [47:0] fract_denorm; + wire [47:0] fract_denorm; + + wire sign_d; + reg sign; + reg [30:0] opa_r1; + reg [47:0] fract_i2f; + reg opas_r1, opas_r2; + wire f2i_out_sign; + + always @(posedge clk) // Exponent must be once cycle delayed + exp_r <= exp_fasu; + + + always @(posedge clk) + opa_r1 <= opa_r[30:0]; + + //always @(fpu_op_r3 or fract_out_q) + assign fract_denorm = {fract_out_q, 20'h0}; + + + always @(posedge clk) + opas_r1 <= opa_r[31]; + + always @(posedge clk) + opas_r2 <= opas_r1; + + assign sign_d = sign_fasu; + + always @(posedge clk) + sign <= (rmode_r2==2'h3) ? !sign_d : sign_d; + + post_norm u4( + //.clk(clk), // System Clock + .fpu_op(fpu_op_r3), // Floating Point Operation + .opas(opas_r2), // OPA Sign + .sign(sign), // Sign of the result + .rmode(rmode_r3), // Rounding mode + .fract_in(fract_denorm), // Fraction Input + .exp_in(exp_r), // Exponent Input + .exp_ovf(2'b00), // Exponent Overflow + .opa_dn(opa_dn), // Operand A Denormalized + .opb_dn(opb_dn), // Operand A Denormalized + .rem_00(1'b0), // Diveide Remainder is zero + .div_opa_ldz(5'b00000), // Divide opa leading zeros count + .output_zero(1'b0), // Force output to Zero + .out(out_d), // Normalized output (un-registered) + .ine(ine_d), // Result Inexact output (un-registered) + .overflow(overflow_d), // Overflow output (un-registered) + .underflow(underflow_d), // Underflow output (un-registered) + .f2i_out_sign(f2i_out_sign) // F2I Output Sign + ); + + //////////////////////////////////////////////////////////////////////// + // + // FPU Outputs + // + reg fasu_op_r1, fasu_op_r2; + wire [30:0] out_fixed; + wire output_zero_fasu; + wire overflow_fasu; + wire out_d_00; + wire ine_fasu; + wire underflow_fasu; + reg opa_nan_r; + + + always @(posedge clk) + fasu_op_r1 <= fasu_op; + + always @(posedge clk) + fasu_op_r2 <= fasu_op_r1; + + + // Force pre-set values for non numerical output + + assign out_fixed = ( (qnan_d | snan_d) | + (ind_d & !fasu_op_r2) ) ? QNAN : INF; + + always @(posedge clk) + out_o1[30:0] <= (inf_d | snan_d | qnan_d) ? out_fixed : out_d; + + + assign out_d_00 = !(|out_d); + + always @(posedge clk) + out_o1[31] <= (snan_d | qnan_d | ind_d) ? nan_sign_d : + output_zero_fasu ? result_zero_sign_d : + sign_fasu_r; + + assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d); + + always @(posedge clk) + ine_o1 <= ine_fasu ; + + + assign overflow_fasu = overflow_d & !(snan_d | qnan_d | inf_d); + + always @(posedge clk) + overflow_o1 <= overflow_fasu ; + + assign underflow_fasu = underflow_d & !(inf_d | snan_d | qnan_d); + + always @(posedge clk) + underflow_o1 <= underflow_fasu ; + + always @(posedge clk) + snan_o1 <= snan_d; + + + + // Status Outputs + always @(posedge clk) + qnan_o1 <= ( snan_d | qnan_d | (ind_d & !fasu_op_r2) ); + + always @(posedge clk) + inf_o1 <= (!(qnan_d | snan_d) & (( (&out_d[30:23]) & !(|out_d[22:0] ) ) | (inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) )); + + assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d); + + always @(posedge clk) + zero_o1 <= output_zero_fasu ; + + always @(posedge clk) + opa_nan_r <= !opa_nan & fpu_op_r2==3'b011; + + always @(posedge clk) + div_by_zero_o1 <= 1'b0; + + // output register + always @(posedge clk) + begin + qnan <= qnan_o1; + out <= out_o1; + inf <= inf_o1; + snan <= snan_o1; + //qnan <= qnan_o1; + ine <= ine_o1; + overflow <= overflow_o1; + underflow <= underflow_o1; + zero <= zero_o1; + div_by_zero <= div_by_zero_o1; + end + +endmodule + + + + +//--------------------------------------------------------------------------------- +module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out, + fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign, + fasu_op); +input clk; +input [1:0] rmode; +input add; +input [31:0] opa, opb; +input opa_nan, opb_nan; +output [26:0] fracta_out, fractb_out; +output [7:0] exp_dn_out; +output sign; +output nan_sign, result_zero_sign; +output fasu_op; // Operation Output + +//////////////////////////////////////////////////////////////////////// +// +// Local Wires and registers +// + +wire signa, signb; // alias to opX sign +wire [7:0] expa, expb; // alias to opX exponent +wire [22:0] fracta, fractb; // alias to opX fraction +wire expa_lt_expb; // expa is larger than expb indicator +wire fractb_lt_fracta; // fractb is larger than fracta indicator +reg [7:0] exp_dn_out; // de normalized exponent output +wire [7:0] exp_small, exp_large; +wire [7:0] exp_diff; // Numeric difference of the two exponents +wire [22:0] adj_op; // Fraction adjustment: input +wire [26:0] adj_op_tmp; +wire [26:0] adj_op_out; // Fraction adjustment: output +wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing +wire [26:0] fracta_s, fractb_s; // Fraction Sorting out +reg [26:0] fracta_out, fractb_out; // Fraction Output +reg sign, sign_d; // Sign Output +reg add_d; // operation (add/sub) +reg fasu_op; // operation (add/sub) register +wire expa_dn, expb_dn; +reg sticky; +reg result_zero_sign; +reg add_r, signa_r, signb_r; +wire [4:0] exp_diff_sft; +wire exp_lt_27; +wire op_dn; +wire [26:0] adj_op_out_sft; +reg fracta_lt_fractb, fracta_eq_fractb; +wire nan_sign1; +reg nan_sign; + +//////////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign signa = opa[31]; +assign signb = opb[31]; +assign expa = opa[30:23]; +assign expb = opb[30:23]; +assign fracta = opa[22:0]; +assign fractb = opb[22:0]; + +//////////////////////////////////////////////////////////////////////// +// +// Pre-Normalize exponents (and fractions) +// + +assign expa_lt_expb = expa > expb; // expa is larger than expb + +// --------------------------------------------------------------------- +// Normalize + +assign expa_dn = !(|expa); // opa denormalized +assign expb_dn = !(|expb); // opb denormalized + +// --------------------------------------------------------------------- +// Calculate the difference between the smaller and larger exponent + +wire [7:0] exp_diff1, exp_diff1a, exp_diff2; + +assign exp_small = expa_lt_expb ? expb : expa; +assign exp_large = expa_lt_expb ? expa : expb; +assign exp_diff1 = exp_large - exp_small; +assign exp_diff1a = exp_diff1-8'h01; +assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1; +assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2; + +always @(posedge clk) // If numbers are equal we should return zero + exp_dn_out <= (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large; + +// --------------------------------------------------------------------- +// Adjust the smaller fraction + + +assign op_dn = expa_lt_expb ? expb_dn : expa_dn; +assign adj_op = expa_lt_expb ? fractb : fracta; +wire temp1; +assign temp1 = ~op_dn; +//assign adj_op_tmp[26:0] = {~op_dn, adj_op, 3'b000}; // recover hidden bit (op_dn) +assign adj_op_tmp[26:0] = {temp1, adj_op, 3'b000}; // recover hidden bit (op_dn) + +// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right +assign exp_lt_27 = exp_diff > 8'd27; +assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0]; + +//assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft; +b_right_shifter_new u7( + .shift_in(adj_op_tmp), + .shift_value(exp_diff_sft), + .shift_out(adj_op_out_sft) +); + +wire temp2; +assign temp2 = adj_op_out_sft[0] | sticky; +//assign adj_op_out[26:0] = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky }; +assign adj_op_out[26:0] = {adj_op_out_sft[26:1], temp2 }; + + +// --------------------------------------------------------------------- +// Get truncated portion (sticky bit) + +always @(exp_diff_sft or adj_op_tmp) + case(exp_diff_sft) // synopsys full_case parallel_case + 5'd00: sticky = 1'h0; + 5'd01: sticky = adj_op_tmp[0]; + 5'd02: sticky = |adj_op_tmp[01:0]; + 5'd03: sticky = |adj_op_tmp[02:0]; + 5'd04: sticky = |adj_op_tmp[03:0]; + 5'd05: sticky = |adj_op_tmp[04:0]; + 5'd06: sticky = |adj_op_tmp[05:0]; + 5'd07: sticky = |adj_op_tmp[06:0]; + 5'd08: sticky = |adj_op_tmp[07:0]; + 5'd09: sticky = |adj_op_tmp[08:0]; + 5'd10: sticky = |adj_op_tmp[09:0]; + 5'd11: sticky = |adj_op_tmp[10:0]; + 5'd12: sticky = |adj_op_tmp[11:0]; + 5'd13: sticky = |adj_op_tmp[12:0]; + 5'd14: sticky = |adj_op_tmp[13:0]; + 5'd15: sticky = |adj_op_tmp[14:0]; + 5'd16: sticky = |adj_op_tmp[15:0]; + 5'd17: sticky = |adj_op_tmp[16:0]; + 5'd18: sticky = |adj_op_tmp[17:0]; + 5'd19: sticky = |adj_op_tmp[18:0]; + 5'd20: sticky = |adj_op_tmp[19:0]; + 5'd21: sticky = |adj_op_tmp[20:0]; + 5'd22: sticky = |adj_op_tmp[21:0]; + 5'd23: sticky = |adj_op_tmp[22:0]; + 5'd24: sticky = |adj_op_tmp[23:0]; + 5'd25: sticky = |adj_op_tmp[24:0]; + 5'd26: sticky = |adj_op_tmp[25:0]; + 5'd27: sticky = |adj_op_tmp[26:0]; + endcase + +// --------------------------------------------------------------------- +// Select operands for add/sub (recover hidden bit) + +assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out; +assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0}; + +// --------------------------------------------------------------------- +// Sort operands (for sub only) + +assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta +assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n; +assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n; + +always @(posedge clk) + fracta_out <= fracta_s; + +always @(posedge clk) + fractb_out <= fractb_s; + +// --------------------------------------------------------------------- +// Determine sign for the output + +// sign: 0=Positive Number; 1=Negative Number +always @(signa or signb or add or fractb_lt_fracta) + case({signa, signb, add}) // synopsys full_case parallel_case + + // Add + 3'b001: sign_d = 0; + 3'b011: sign_d = fractb_lt_fracta; + 3'b101: sign_d = !fractb_lt_fracta; + 3'b111: sign_d = 1; + + // Sub + 3'b000: sign_d = fractb_lt_fracta; + 3'b010: sign_d = 0; + 3'b100: sign_d = 1; + 3'b110: sign_d = !fractb_lt_fracta; + endcase + +always @(posedge clk) + sign <= sign_d; + +// Fix sign for ZERO result +always @(posedge clk) + signa_r <= signa; + +always @(posedge clk) + signb_r <= signb; + +always @(posedge clk) + add_r <= add; + +always @(posedge clk) + result_zero_sign <= ( add_r & signa_r & signb_r) | + (!add_r & signa_r & !signb_r) | + ( add_r & (signa_r | signb_r) & (rmode==3)) | + (!add_r & (signa_r == signb_r) & (rmode==3)); + +// Fix sign for NAN result +always @(posedge clk) + fracta_lt_fractb <= fracta < fractb; + +always @(posedge clk) + fracta_eq_fractb <= fracta == fractb; + +assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r; + +always @(posedge clk) + nan_sign <= (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r; + +//////////////////////////////////////////////////////////////////////// +// +// Decode Add/Sub operation +// + +// add: 1=Add; 0=Subtract +always @(signa or signb or add) + case({signa, signb, add}) // synopsys full_case parallel_case + + // Add + 3'b001: add_d = 1; + 3'b011: add_d = 0; + 3'b101: add_d = 0; + 3'b111: add_d = 1; + + // Sub + 3'b000: add_d = 0; + 3'b010: add_d = 1; + 3'b100: add_d = 1; + 3'b110: add_d = 0; + endcase + +always @(posedge clk) + fasu_op <= add_d; + +endmodule + +module b_right_shifter_new ( + shift_in, + shift_value, + shift_out +); + +input [26:0] shift_in; +input [4:0] shift_value; +output [26:0] shift_out; +reg [26:0] shift_out; + +always @(shift_value) +begin + case (shift_value) + 5'b00000: shift_out = shift_in; + 5'b00001: shift_out = shift_in >> 1; + 5'b00010: shift_out = shift_in >> 2; + 5'b00011: shift_out = shift_in >> 3; + 5'b00100: shift_out = shift_in >> 4; + 5'b00101: shift_out = shift_in >> 5; + 5'b00110: shift_out = shift_in >> 6; + 5'b00111: shift_out = shift_in >> 7; + 5'b01000: shift_out = shift_in >> 8; + 5'b01001: shift_out = shift_in >> 9; + 5'b01010: shift_out = shift_in >> 10; + 5'b01011: shift_out = shift_in >> 11; + 5'b01100: shift_out = shift_in >> 12; + 5'b01101: shift_out = shift_in >> 13; + 5'b01110: shift_out = shift_in >> 14; + 5'b01111: shift_out = shift_in >> 15; + 5'b10000: shift_out = shift_in >> 16; + 5'b10001: shift_out = shift_in >> 17; + 5'b10010: shift_out = shift_in >> 18; + 5'b10011: shift_out = shift_in >> 19; + 5'b10100: shift_out = shift_in >> 20; + 5'b10101: shift_out = shift_in >> 21; + 5'b10110: shift_out = shift_in >> 22; + 5'b10111: shift_out = shift_in >> 23; + 5'b11000: shift_out = shift_in >> 24; + 5'b11001: shift_out = shift_in >> 25; + 5'b11010: shift_out = shift_in >> 26; + 5'b11011: shift_out = shift_in >> 27; + endcase +end + + +endmodule + +//---------------------------------------------------------------------------- + + + +//////////////////////////////////////////////////////////////////////// +// +// Add/Sub +// + +module add_sub27(add, opa, opb, sum, co); +input add; +input [26:0] opa, opb; +output [26:0] sum; +output co; + + + +assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb}); + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v b/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v new file mode 100755 index 000000000..e7b836533 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v @@ -0,0 +1,1617 @@ +//************************************************************************** +// author: Alexander Bochem +// date: 07.05.2010 +//************************************************************************** +//input: RLE encoded pixel data +//output: blob attributes merged with bounding box criteria +// +//description: +// - read RLE encoded pixel data from input fifo +// - merge Runs based on bounding box criteria +// - write Blobs attributes to output fifo +//************************************************************************** +//change: 13.05.2010 +// condition checks in state CHECK_PIXEL implemented to merge adjacent +// runs into BLOB containers +// +// 15.05.2010 +// included BLOB_RANGE and CONT_RANGE for adjacency check +// eliminates multiple detection of BLOBs +// +// 26.05.2010 +// extended to detect up to six BLOBs +// +// 27.05.2010 +// add average X and Y edge to output for +// threshold adjustment +// +// 29.05.2010 +// include collecting data for center of mass method in RLE merging process +// change module name to RLE_BlobMerging +// +// 31.05.2010 +// include computation for center of mass +//************************************************************************** + +`define LSB_X 1'b0 +`define MSB_X 4'b1010 +`define LSB_Y 4'b1011 +`define MSB_Y 5'b10101 +`define LSB_RunLength 5'b10110 +`define MSB_RunLength 5'b11111 +`define LSB_RunSumValues 6'b100000 +`define MSB_RunSumValues 6'b11111 +`define LSB_RunSumXpositions 7'b1000000 +`define MSB_RunSumXpositions 7'b1011111 +`define LSB_RunSumYpositions 7'b1100000 +`define MSB_RunSumYpositions 7'b1111111 +`define LSB_EOFflag 1'b0 +`define MSB_EOFflag 5'b11111 +`define CONT_RANGE 5'b01010 +`define BLOB_RANGE 5'b01010 + + +`define FALSE 1'b0 +`define TRUE 1'b1 +`define INIT 5'b00000 +`define IDLE 5'b00001 +`define CHECK_CONDITIONS 5'b00010 +`define WRITE_FIFO 5'b00011 +`define WAIT_FIFO 5'b00100 +`define COMPUTE_CENTER 5'b00101 +`define VALIDATE_CHECK_ADJACENT_CONTAINER 5'b00110 +`define READ_FIFO 5'b00111 +`define CONFIG_WRITE 5'b01000 +`define WRITE_WAIT 5'b01001 +`define SELECT_EMPTY_CONTAINER 5'b01010 +`define CHECK_ADJACENT_CONTAINTER 5'b01011 +`define CHECK_CONT_ADJACENCY 5'b01100 +`define MERGE_CONTAINER 5'b01101 +`define WRITE_BLOB_0 4'b0000 +`define WRITE_BLOB_1 4'b0001 +`define WRITE_BLOB_2 4'b0010 +`define WRITE_BLOB_3 4'b0011 +`define WRITE_BLOB_4 4'b0100 +`define WRITE_BLOB_5 4'b0101 +`define EOF 32'b00000000000000000000000000000000 +`define MERGE_CONT_1_2 5'b01110 +`define MERGE_CONT_1_3 5'b01111 +`define MERGE_CONT_1_4 5'b10000 +`define MERGE_CONT_1_5 5'b10001 +`define MERGE_CONT_2_3 5'b10010 +`define MERGE_CONT_2_4 5'b10011 +`define MERGE_CONT_2_5 5'b10100 +`define MERGE_CONT_3_4 5'b10101 +`define MERGE_CONT_3_5 5'b10110 +`define MERGE_CONT_4_5 5'b10111 +`define MERGE_CONT_1_6 5'b11000 +`define MERGE_CONT_2_6 5'b11001 +`define MERGE_CONT_3_6 5'b11010 +`define MERGE_CONT_4_6 5'b11011 +`define MERGE_CONT_5_6 5'b11100 + + + +module RLE_BlobMerging(clk, +//iCOMclock, + iReset, + iReadFifoEmpty, + iReadFifoData, + iWriteFifoFull, + oReadFifoRequest, + oWriteBlobData, + oWriteRequest, + oAvgSizeXaxis, + oAvgSizeYaxis +); + + input clk; //module clock + //input iCOMclock; //clock for COM sub-module + input iReset; //module reset signal + input iReadFifoEmpty; //fifo empty signal from input fifo + input [127:0]iReadFifoData; //data bus from input fifo [32b y-w., 32b x-w., 32 pixel-w.,10b length, 11b Y, 11b X] + input iWriteFifoFull; //fifo full signal from output fifo + + output oReadFifoRequest; //read request to input fifo + output [75:0]oWriteBlobData; //data bus to output fifo [10b index, 11b bb y, 11b bb x, 11b com y, 11b com x, 11b len y, 11b len x] + output oWriteRequest; //write request to output fifo + output [10:0] oAvgSizeXaxis; //average size of X axis for detected BLOBs + output [10:0] oAvgSizeYaxis; //average size of Y axis for detected BLOBs + + reg oReadFifoRequest; //read request to input fifo + reg [75:0]oWriteBlobData; //data bus to output fifo [10b index, 11b bb y, 11b bb x, 11b com y, 11b com x, 11b len y, 11b len x] + reg oWriteRequest; //write request to output fifo + reg [10:0] oAvgSizeXaxis; //average size of X axis for detected BLOBs + reg [10:0] oAvgSizeYaxis; //average size of Y axis for detected BLOBs + +/* +parameter LSB_X=0, MSB_X=10; //start and end bit for x coordiante +parameter LSB_Y=11, MSB_Y=21; //start and end bit for y coordiante +parameter LSB_RunLength=22, MSB_RunLength=31; //start and end bit for RUN length +parameter LSB_RunSumValues=32, MSB_RunSumValues=63; +parameter LSB_RunSumXpositions=64, MSB_RunSumXpositions=95; +parameter LSB_RunSumYpositions=96, MSB_RunSumYpositions=127; +parameter LSB_EOFflag=0, MSB_EOFflag=31;//start and end bit for EOF flag +parameter CONT_RANGE = 5'd10; +parameter BLOB_RANGE = 5'd10; +parameter MIN_X=11'd0, MAX_X=11'd640, MIN_Y=11'd0, MAX_Y=11'd480; +parameter COM_DELAY_TIME=3'd5; +*/ + +//internal registers +reg [17:0] checkResult; //each flage represents one result of conditional checks +reg [9:0] run_length; //temporary store the length of a detected run +reg [10:0] run_start_x; //temporary store starting X position of run +reg [10:0] run_start_y; //temporary store starting Y position of run +reg [31:0] run_sum_x_positions; //temporary store weighted sum of x positions in run +reg [31:0] run_sum_y_positions; //temporary store weighted sum of y postions in run +reg [31:0] run_sum_values; //temporary store sum of weights in run +reg [3:0] write_result_pointer; +reg [4:0] state; +reg RunAdded; +reg [14:0] ContainerAdjacentResult; +reg [3:0] countDetectedBlobs; +reg [10:0] avgSizeXaxis; +reg [10:0] avgSizeYaxis; +reg enableCOMcomputation; //flag enables sub-modules for center point computation with COM +reg [3:0] delayCounterCOM; //counts up to COM_DELAY_TIME to allow sub-module finish computation + +//BLOB containers +//CONTAINER 1 +reg[10:0] blob1minX, blob1minY, blob1maxX, blob1maxY; //bounding box attributes +reg [10:0] blob1X_bb_center, blob1Y_bb_center; //center points for bounding box attributes +reg [35:0] blob1X_com_center, blob1Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_1; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_1; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_1; //number of pixels belonging to BLOB +reg blob1empty; //flag information if container is empty + +//CONTAINER 2 +reg[10:0] blob2minX, blob2minY, blob2maxX, blob2maxY; //bounding box attributes +reg [10:0] blob2X_bb_center, blob2Y_bb_center; //center points for bounding box attributes +reg [35:0] blob2X_com_center, blob2Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_2; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_2; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_2; //number of pixels belonging to BLOB +reg blob2empty; //flag information if container is empty + +//CONTAINER 3 +reg[10:0] blob3minX, blob3minY, blob3maxX, blob3maxY; //bounding box attributes +reg [10:0] blob3X_bb_center, blob3Y_bb_center; //center points for bounding box attributes +reg [35:0] blob3X_com_center, blob3Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_3; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_3; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_3; //number of pixels belonging to BLOB +reg blob3empty; //flag information if container is empty + +//CONTAINER 4 +reg[10:0] blob4minX, blob4minY, blob4maxX, blob4maxY; //bounding box attributes +reg [10:0] blob4X_bb_center, blob4Y_bb_center; //center points for bounding box attributes +reg [35:0] blob4X_com_center, blob4Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_4; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_4; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_4; //number of pixels belonging to BLOB +reg blob4empty; //flag information if container is empty + +//CONTAINER 5 +reg[10:0] blob5minX, blob5minY, blob5maxX, blob5maxY; //bounding box attributes +reg [10:0] blob5X_bb_center, blob5Y_bb_center; //center points for bounding box attributes +reg [35:0] blob5X_com_center, blob5Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_5; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_5; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_5; //number of pixels belonging to BLOB +reg blob5empty; //flag information if container is empty + +//CONTAINER 6 +reg[10:0] blob6minX, blob6minY, blob6maxX, blob6maxY; //bounding box attributes +reg [10:0] blob6X_bb_center, blob6Y_bb_center; //center points for bounding box attributes +reg [35:0] blob6X_com_center, blob6Y_com_center; //center points for center of mass attributes +reg [35:0] sumBLOB_Xpositions_6; //summed X positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Ypositions_6; //summed Y positions of all pixels belonging to BLOB, weightend by pixel value +reg [35:0] sumBLOB_Pixels_6; //number of pixels belonging to BLOB +reg blob6empty; //flag information if container is empty + +//divider varaible + +//reg [49:0]divider_res_x; +wire [10:0]divider_res_x; +//reg [49:0]divider_rem_x; +wire [10:0]divider_rem_x; + +wire [10:0]divider_res_y; +//reg [49:0]divider_res_y; +wire [10:0]divider_rem_y; +//reg [49:0]divider_rem_y; + +wire [10:0] ex_avgSizeXaxis; +//reg [49:0] ex_avgSizeXaxis; +assign ex_avgSizeXaxis = avgSizeXaxis; + +wire [10:0]ex_avgSizeYaxis; +//reg [49:0]ex_avgSizeYaxis; +assign ex_avgSizeYaxis = avgSizeYaxis; + + +wire [3:0]ex_countDetectedBlobs; +//reg [49:0]ex_countDetectedBlobs; +assign ex_countDetectedBlobs = countDetectedBlobs; +//implement the divider +divider inst_x ( + .opa(ex_avgSizeXaxis), + .opb(ex_countDetectedBlobs), + .quo(divider_res_x), + .rem(divider_rem_x)); + +divider inst_y ( + .opa(ex_avgSizeYaxis), + .opb(ex_countDetectedBlobs), + .quo(divider_res_y), + .rem(divider_rem_y)); + +//read RLE encoded pixel data from input fifo and merge adjacent runs to blobs +//compute blobs center points, on EOF flag +//store center points to output fifo, if EOF flag is read from Fifo +always@(posedge clk) begin + + //reset internal registers on reset signal + if(iReset) begin + state <= `INIT; + end + else begin + //module state machine + case(state) + + //intialize internal register + `INIT: begin + checkResult <= 18'b000000000000000000; + run_length <= 10'b0000000000; + run_start_x <= 11'b00000000000; + run_start_y <= 11'b00000000000; + + RunAdded <= `FALSE; + + //set defaults for CONTAINER 1 + blob1maxX <= 11'b00000000000; + blob1minX <= 11'b00000000000; + blob1maxY <= 11'b00000000000; + blob1minY <= 11'b00000000000; +// sumBLOB_Xpositions_1=0; +// sumBLOB_Ypositions_1=0; +// sumBLOB_Pixels_1=0; + blob1empty <= `TRUE; + + //set defaults for CONTAINER 2 + blob2maxX <= 11'b00000000000; + blob2minX <= 11'b00000000000; + blob2maxY <= 11'b00000000000; + blob2minY <= 11'b00000000000; +// sumBLOB_Xpositions_2=0; +// sumBLOB_Ypositions_2=0; +// sumBLOB_Pixels_2=0; + blob2empty <= `TRUE; + + //set defaults for CONTAINER 3 + blob3maxX <= 11'b00000000000; + blob3minX <= 11'b00000000000; + blob3maxY <= 11'b00000000000; + blob3minY <= 11'b00000000000; +// sumBLOB_Xpositions_3=0; +// sumBLOB_Ypositions_3=0; +// sumBLOB_Pixels_3=0; + blob3empty <= `TRUE; + + //set defaults for CONTAINER 4 + blob4maxX <= 11'b00000000000; + blob4minX <= 11'b00000000000; + blob4maxY <= 11'b00000000000; + blob4minY <= 11'b00000000000; +// sumBLOB_Xpositions_4=0; +// sumBLOB_Ypositions_4=0; +// sumBLOB_Pixels_4=0; + blob4empty <= `TRUE; + + + //set defaults for CONTAINER 5 + blob5maxX <= 11'b00000000000; + blob5minX <= 11'b00000000000; + blob5maxY <= 11'b00000000000; + blob5minY <= 11'b00000000000; +// sumBLOB_Xpositions_5=0; +// sumBLOB_Ypositions_5=0; +// sumBLOB_Pixels_5=0; + blob5empty <= `TRUE; + + //set defaults for CONTAINER 6 + blob6maxX <= 11'b00000000000; + blob6minX <= 11'b00000000000; + blob6maxY <= 11'b00000000000; + blob6minY <= 11'b00000000000; +// sumBLOB_Xpositions_6<=0; +// sumBLOB_Ypositions_6<=0; +// sumBLOB_Pixels_6<=0; + blob6empty <= `TRUE; + + + blob1X_com_center <= 35'b00000000000000000000000000000000000; + blob1Y_com_center <= 35'b00000000000000000000000000000000000; + blob2X_com_center <= 35'b00000000000000000000000000000000000; + blob2Y_com_center <= 35'b00000000000000000000000000000000000; + blob3X_com_center <= 35'b00000000000000000000000000000000000; + blob3Y_com_center <= 35'b00000000000000000000000000000000000; + blob4X_com_center <= 35'b00000000000000000000000000000000000; + blob4Y_com_center <= 35'b00000000000000000000000000000000000; + blob5X_com_center <= 35'b00000000000000000000000000000000000; + blob5Y_com_center <= 35'b00000000000000000000000000000000000; + blob6X_com_center <= 35'b00000000000000000000000000000000000; + blob6Y_com_center <= 35'b00000000000000000000000000000000000; + //blob4X_com_center + //blob4X_com_center + + + avgSizeXaxis<=11'b00000000000; + avgSizeYaxis<=11'b00000000000; + countDetectedBlobs<=4'b0000; + enableCOMcomputation<=`FALSE; + + state <= `IDLE; + end + + //read run data from input fifo + `IDLE: begin + if(!iReadFifoEmpty) begin + oReadFifoRequest <= `TRUE; + state <= `READ_FIFO; + end + else begin + state <= `IDLE; + end + end + + //receive data from input fifo + `READ_FIFO: begin + oReadFifoRequest <= `FALSE; + + //check for EOF flag + if(iReadFifoData[`MSB_EOFflag:`LSB_EOFflag]==`EOF)begin + write_result_pointer<=4'b0000; + + //start center point computation for COM + enableCOMcomputation<=`TRUE; + delayCounterCOM<=4'b0000; //reset delay time counter + + state <= `COMPUTE_CENTER; + end + else begin + run_length <= iReadFifoData[31:22]; + run_start_x <= iReadFifoData[10:0]; + run_start_y <= iReadFifoData[21:11]; + run_sum_x_positions <= iReadFifoData[95:64]; + run_sum_y_positions <= iReadFifoData[127:96]; + run_sum_values <= iReadFifoData[63:32]; + checkResult <= 18'b000000000000000000; + RunAdded <= `FALSE; + state <= `CHECK_CONDITIONS; + end + end + + //perform condition checks + `CHECK_CONDITIONS: begin + + //check which BLOB containers are empty + checkResult[0] <= blob1empty; + checkResult[3] <= blob2empty; + checkResult[6] <= blob3empty; + checkResult[9] <= blob4empty; + checkResult[12] <= blob5empty; + checkResult[15] <= blob6empty; + + + //check if run is adjacent on X values to blob 1 container + if( (((run_start_x+`BLOB_RANGE) >= blob1minX) & (run_start_x <= (blob1maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob1minX) & ((run_start_x+run_length) <= (blob1maxX+`BLOB_RANGE)) ) begin + checkResult[1] <= `TRUE; + end + //check if run is adjacent on X values to blob 2 container +// if( ((run_start_x+`BLOB_RANGE) >= blob2minX) & (run_start_x <= blob2maxX) & +// ((run_start_x+run_length) >= blob2minX) & ((run_start_x+run_length) <= (blob2maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob2minX) & (run_start_x <= (blob2maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob2minX) & ((run_start_x+run_length) <= (blob2maxX+`BLOB_RANGE)) ) begin + checkResult[4] <= `TRUE; + end + //check if run is adjacent on X values to blob 3 container +// if( ((run_start_x+`BLOB_RANGE) >= blob3minX) & (run_start_x <= blob3maxX) & +// ((run_start_x+run_length) >= blob3minX) & ((run_start_x+run_length) <= (blob3maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob3minX) & (run_start_x <= (blob3maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob3minX) & ((run_start_x+run_length) <= (blob3maxX+`BLOB_RANGE)) ) begin + checkResult[7] <= `TRUE; + end + //check if run is adjacent on X values to blob 4 container +// if( ((run_start_x+`BLOB_RANGE) >= blob4minX) & (run_start_x <= blob4maxX) & +// ((run_start_x+run_length) >= blob4minX) & ((run_start_x+run_length) <= (blob4maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob4minX) & (run_start_x <= (blob4maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob4minX) & ((run_start_x+run_length) <= (blob4maxX+`BLOB_RANGE)) ) begin + checkResult[10] <= `TRUE; + end + //check if run is adjacent on X values to blob 5 container +// if( ((run_start_x+`BLOB_RANGE) >= blob5minX) & (run_start_x <= blob5maxX) & +// ((run_start_x+run_length) >= blob5minX) & ((run_start_x+run_length) <= (blob5maxX+`BLOB_RANGE)) ) begin + if( (((run_start_x+`BLOB_RANGE) >= blob5minX) & (run_start_x <= (blob5maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob5minX) & ((run_start_x+run_length) <= (blob5maxX+`BLOB_RANGE)) ) begin + checkResult[13] <= `TRUE; + end + + //check if run is adjacent on X values to blob 6 container + if( (((run_start_x+`BLOB_RANGE) >= blob6minX) & (run_start_x <= (blob6maxX+`BLOB_RANGE))) || + ((run_start_x+run_length+`BLOB_RANGE) >= blob6minX) & ((run_start_x+run_length) <= (blob6maxX+`BLOB_RANGE)) ) begin + checkResult[16] <= `TRUE; + end + + //check if run is adjacent on Y values to blob 1 container + if( (run_start_y == (blob1maxY +1)) || (run_start_y == blob1maxY) ) begin + checkResult[2] <= `TRUE; + end + //check if run is adjacent on Y values to blob 2 container + if( (run_start_y == (blob2maxY +1)) || (run_start_y == blob2maxY) ) begin + checkResult[5] <= `TRUE; + end + //check if run is adjacent on Y values to blob 3 container + if( (run_start_y == (blob3maxY +1)) || (run_start_y == blob3maxY) ) begin + checkResult[8] <= `TRUE; + end + //check if run is adjacent on Y values to blob 4 container + if( (run_start_y == (blob4maxY +1)) || (run_start_y == blob4maxY) ) begin + checkResult[11] <= `TRUE; + end + //check if run is adjacent on Y values to blob 5 container + if( (run_start_y == (blob5maxY +1)) || (run_start_y == blob5maxY) ) begin + checkResult[14] <= `TRUE; + end + //check if run is adjacent on Y values to blob 5 container + if( (run_start_y == (blob6maxY +1)) || (run_start_y == blob6maxY) ) begin + checkResult[17] <= `TRUE; + end + + state <= `CHECK_ADJACENT_CONTAINTER; + end + + //validate results from condition check for adjacency + `CHECK_ADJACENT_CONTAINTER: begin + + if( + ((~checkResult[0])&checkResult[1]&checkResult[2]) + || ((~checkResult[3])&checkResult[4]&checkResult[5]) + || ((~checkResult[6])&checkResult[7]&checkResult[8]) + || ((~checkResult[9])&checkResult[10]&checkResult[11]) + || ((~checkResult[12])&checkResult[13]&checkResult[14]) + || ((~checkResult[15])&checkResult[16]&checkResult[17]) + ) + begin + RunAdded <= `TRUE; + end + + //run adjacent to container 1 + if( (~checkResult[0])&checkResult[1]&checkResult[2] ) + begin + if(run_start_x < blob1minX) blob1minX <= run_start_x; + if((run_start_x+run_length) > blob1maxX) blob1maxX <= (run_start_x+run_length); + if(blob1maxY < run_start_y) blob1maxY <= run_start_y; + end + + //run adjacent to container 2 + if( (~checkResult[3])&checkResult[4]&checkResult[5] ) + begin + if(run_start_x < blob2minX) blob2minX <= run_start_x; + if((run_start_x+run_length) > blob2maxX) blob2maxX <= (run_start_x+run_length); + if(blob2maxY < run_start_y) blob2maxY <= run_start_y; + end + + //run adjacent to container 3 + if( (~checkResult[6])&checkResult[7]&checkResult[8] ) + begin + if(run_start_x < blob3minX) blob3minX <= run_start_x; + if((run_start_x+run_length) > blob3maxX) blob3maxX <= (run_start_x+run_length); + if(blob3maxY < run_start_y) blob3maxY <= run_start_y; + end + + //run adjacent to container 4 + if( (~checkResult[9])&checkResult[10]&checkResult[11] ) + begin + if(run_start_x < blob4minX) blob4minX <= run_start_x; + if((run_start_x+run_length) > blob4maxX) blob4maxX <= (run_start_x+run_length); + if(blob4maxY < run_start_y) blob4maxY <= run_start_y; + end + + //run adjacent to container 5 + if( (~checkResult[12])&checkResult[13]&checkResult[14] ) + begin + if(run_start_x < blob5minX) blob5minX <= run_start_x; + if((run_start_x+run_length) > blob5maxX) blob5maxX <= (run_start_x+run_length); + if(blob5maxY < run_start_y) blob5maxY <= run_start_y; + end + + //run adjacent to container 6 + if( (~checkResult[15])&checkResult[16]&checkResult[17] ) + begin + if(run_start_x < blob6minX) blob6minX <= run_start_x; + if((run_start_x+run_length) > blob6maxX) blob6maxX <= (run_start_x+run_length); + if(blob6maxY < run_start_y) blob6maxY <= run_start_y; + end + + //read next run from input fifo + state <= `VALIDATE_CHECK_ADJACENT_CONTAINER; + end + + //check if run could be added to container + `VALIDATE_CHECK_ADJACENT_CONTAINER: begin + //if run has been added, continue with next run + if(RunAdded) begin + state <= `CHECK_CONT_ADJACENCY; + end + //if run not adjacent, put into empty container + else begin + state <= `SELECT_EMPTY_CONTAINER; + end + end + + //if run was not adjacent, add to new container + `SELECT_EMPTY_CONTAINER: begin + + //first cont empty + if( checkResult[0] ) begin + blob1minX <= run_start_x; + blob1maxX <= run_start_x+run_length; + blob1minY <= run_start_y; + blob1maxY <= run_start_y; + +// sumBLOB_Xpositions_1<=run_sum_x_positions; +// sumBLOB_Ypositions_1<=run_sum_y_positions; +// sumBLOB_Pixels_1<=run_sum_values; + + blob1empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 2 is empty + //second cont empty + else if( checkResult[3]) begin + blob2minX <= run_start_x; + blob2maxX <= run_start_x+run_length; + blob2minY <= run_start_y; + blob2maxY <= run_start_y; + +// sumBLOB_Xpositions_2<=run_sum_x_positions; +// sumBLOB_Ypositions_2<=run_sum_y_positions; +// sumBLOB_Pixels_2<=run_sum_values; + + blob2empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 3 is empty + //third cont empty + if( checkResult[6]) begin + blob3minX <= run_start_x; + blob3maxX <= run_start_x+run_length; + blob3minY <= run_start_y; + blob3maxY <= run_start_y; + +// sumBLOB_Xpositions_3<=run_sum_x_positions; +// sumBLOB_Ypositions_3<=run_sum_y_positions; +// sumBLOB_Pixels_3<=run_sum_values; + + blob3empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 4 is empty + //fourth cont empty + else if( checkResult[9])begin + blob4minX <= run_start_x; + blob4maxX <= run_start_x+run_length; + blob4minY <= run_start_y; + blob4maxY <= run_start_y; + +// sumBLOB_Xpositions_4<=run_sum_x_positions; +// sumBLOB_Ypositions_4<=run_sum_y_positions; +// sumBLOB_Pixels_4<=run_sum_values; + + blob4empty<=`FALSE; + end + + //run not adjacent to existing blobs and container 5 is empty + //fifth cont empty + else if( checkResult[12]) begin + blob5minX <= run_start_x; + blob5maxX <= run_start_x+run_length; + blob5minY <= run_start_y; + blob5maxY <= run_start_y; + +// sumBLOB_Xpositions_5<=run_sum_x_positions; +// sumBLOB_Ypositions_5<=run_sum_y_positions; +// sumBLOB_Pixels_5<=run_sum_values; + + blob5empty<=`FALSE; + end + + else if( checkResult[15]) begin + blob6minX <= run_start_x; + blob6maxX <= run_start_x+run_length; + blob6minY <= run_start_y; + blob6maxY <= run_start_y; + +// sumBLOB_Xpositions_6<=run_sum_x_positions; +// sumBLOB_Ypositions_6<=run_sum_y_positions; +// sumBLOB_Pixels_6<=run_sum_values; + + blob6empty<=`FALSE; + end + + state <= `CHECK_CONT_ADJACENCY; + end + + //compute center points for non-empty containers + //center point computation with BB and COM + `COMPUTE_CENTER: begin + //compute center point for blob in Container 1 + blob1X_bb_center <= ((blob1minX + blob1maxX)>>1'b1); + blob1Y_bb_center <= ((blob1minY + blob1maxY)>>1'b1); + //compute center point for blob in Container 2 + blob2X_bb_center <= ((blob2minX + blob2maxX)>>1'b1); + blob2Y_bb_center <= ((blob2minY + blob2maxY)>>1'b1); + //compute center point for blob in Container 3 + blob3X_bb_center <= ((blob3minX + blob3maxX)>>1'b1); + blob3Y_bb_center <= ((blob3minY + blob3maxY)>>1'b1); + //compute center point for blob in Container 4 + blob4X_bb_center <= ((blob4minX + blob4maxX)>>1'b1); + blob4Y_bb_center <= ((blob4minY + blob4maxY)>>1'b1); + //compute center point for blob in Container 5 + blob5X_bb_center <= ((blob5minX + blob5maxX)>>1'b1); + blob5Y_bb_center <= ((blob5minY + blob5maxY)>>1'b1); + //compute center point for blob in Container 6 + blob6X_bb_center <= ((blob6minX + blob6maxX)>>1'b1); + blob6Y_bb_center <= ((blob6minY + blob6maxY)>>1'b1); + + //increase delay time counter for COM computation + //delayCounterCOM<=delayCounterCOM+3'd1; + + state<=`CONFIG_WRITE; + end + + `CONFIG_WRITE: begin + //increase delay time counter for COM computation + //delayCounterCOM<=delayCounterCOM+3'd1; + + //if(delayCounterCOM > COM_DELAY_TIME) begin + //selector for write progress + case(write_result_pointer) + + `WRITE_BLOB_0: begin + //if(blob1empty==`FALSE && blob1Y > 1) begin + if(blob1empty==`FALSE) begin + //oWriteBlobData={10'd1, blob1Y, blob1X,(blob1maxY-blob1minY),(blob1maxX-blob1minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob1Y_bb_center; + oWriteBlobData[31:21]<=blob1X_bb_center; + oWriteBlobData[42:32]<=blob1Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob1X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob1maxY-blob1minY); + oWriteBlobData[75:65]<=(blob1maxX-blob1minX); + avgSizeYaxis<=(blob1maxY-blob1minY); + avgSizeXaxis<=(blob1maxX-blob1minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_1: begin + //if(blob2empty==`FALSE && blob2Y > 1) begin + if(blob2empty==`FALSE) begin + //oWriteBlobData={10'd2, blob2Y, blob2X,(blob2maxY-blob2minY),(blob2maxX-blob2minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob2Y_bb_center; + oWriteBlobData[31:21]<=blob2X_bb_center; + oWriteBlobData[42:32]<=blob2Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob2X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob2maxY-blob2minY); + oWriteBlobData[75:65]<=(blob2maxX-blob2minX); + avgSizeYaxis<=avgSizeYaxis+(blob2maxY-blob2minY); + avgSizeXaxis<=avgSizeXaxis+(blob2maxX-blob2minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+4'b0001; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_2: begin + //if(blob3empty==`FALSE && blob3Y > 1) begin + if(blob3empty==`FALSE) begin + //oWriteBlobData={10'd3, blob3Y, blob3X,(blob3maxY-blob3minY),(blob3maxX-blob3minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob3Y_bb_center; + oWriteBlobData[31:21]<=blob3X_bb_center; + oWriteBlobData[42:32]<=blob3Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob3X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob3maxY-blob3minY); + oWriteBlobData[75:65]<=(blob3maxX-blob3minX); + avgSizeYaxis<=avgSizeYaxis+(blob3maxY-blob3minY); + avgSizeXaxis<=avgSizeXaxis+(blob3maxX-blob3minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+4'b0001; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_3: begin + //if(blob4empty==`FALSE && blob4Y > 1) begin + if(blob4empty==`FALSE) begin + //oWriteBlobData={10'd4, blob4Y, blob4X,(blob4maxY-blob4minY),(blob4maxX-blob4minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob4Y_bb_center; + oWriteBlobData[31:21]<=blob4X_bb_center; + oWriteBlobData[42:32]<=blob4Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob4X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob4maxY-blob4minY); + oWriteBlobData[75:65]<=(blob4maxX-blob4minX); + avgSizeYaxis<=avgSizeYaxis+(blob4maxY-blob4minY); + avgSizeXaxis<=avgSizeXaxis+(blob4maxX-blob4minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_4: begin + //if(blob5empty==`FALSE && blob5Y > 1) begin + if(blob5empty==`FALSE) begin + //oWriteBlobData={10'd5, blob5Y, blob5X,(blob5maxY-blob5minY),(blob5maxX-blob5minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob5Y_bb_center; + oWriteBlobData[31:21]<=blob5X_bb_center; + oWriteBlobData[42:32]<=blob5Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob5X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob5maxY-blob5minY); + oWriteBlobData[75:65]<=(blob5maxX-blob5minX); + avgSizeYaxis<=avgSizeYaxis+(blob5maxY-blob5minY); + avgSizeXaxis<=avgSizeXaxis+(blob5maxX-blob5minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + `WRITE_BLOB_5: begin + //if(blob6empty==`FALSE && blob6Y > 1) begin + if(blob6empty==`FALSE) begin + //oWriteBlobData={10'd6, blob6Y, blob6X,(blob6maxY-blob6minY),(blob6maxX-blob6minX)}; + oWriteBlobData[9:0]<=10'b0000000001; + oWriteBlobData[20:10]<=blob6Y_bb_center; + oWriteBlobData[31:21]<=blob6X_bb_center; + oWriteBlobData[42:32]<=blob6Y_com_center[10:0]; + oWriteBlobData[53:43]<=blob6X_com_center[10:0]; + oWriteBlobData[64:54]<=(blob6maxY-blob6minY); + oWriteBlobData[75:65]<=(blob6maxX-blob6minX); + + avgSizeYaxis<=avgSizeYaxis+(blob6maxY-blob6minY); + avgSizeXaxis<=avgSizeXaxis+(blob6maxX-blob6minX); + countDetectedBlobs<=countDetectedBlobs+1'b1; + state<=`WRITE_FIFO; + end + else begin + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + end + + default: begin + oAvgSizeXaxis<=divider_res_x; + oAvgSizeYaxis<=divider_res_y; + //oWriteBlobData<=32'h00000000; + oWriteBlobData<=0; + state<=`INIT;//continue processing pixel from new frame + end + //NO DEFAULT(DIVIDER, CONG) + endcase + //end + //end + + end + + + + `WRITE_FIFO: begin + if(!iWriteFifoFull) begin + oWriteRequest<=`TRUE; + state<=`WRITE_WAIT; + end + end + + `WRITE_WAIT: begin + oWriteRequest<=`FALSE; + write_result_pointer<=write_result_pointer+1'b1; + state<=`CONFIG_WRITE; + end + + `CHECK_CONT_ADJACENCY: begin +//MERGE TO CONTAINER 1 + if(blob2empty==`FALSE && blob1empty==`FALSE) begin + if( ((blob2minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob2maxY) < `CONT_RANGE)) begin + + if( ((blob2minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob2maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[0]<=`TRUE; + end + end + end + if(blob3empty==`FALSE && blob1empty==`FALSE) begin + //check adjacency on Y axis + if( ((blob3minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob3minY) < `CONT_RANGE) || + ((blob3minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob3minY) < `CONT_RANGE) || + ((blob3maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob3maxY) < `CONT_RANGE) || + ((blob3maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob3maxY) < `CONT_RANGE)) begin + + if( ((blob3minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob3minX) < `CONT_RANGE) || + ((blob3minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob3minX) < `CONT_RANGE) || + ((blob3maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob3maxX) < `CONT_RANGE) || + ((blob3maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob3maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[1]<=`TRUE; + end + end + end + if(blob4empty==`FALSE && blob1empty==`FALSE) begin + //check adjacency on Y axis + //Merge Container 1 and 4 if adjacent + //check adjacency on Y axis + if( ((blob4minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[2]<=`TRUE; + end + end + end + if(blob5empty==`FALSE && blob1empty==`FALSE) begin + if( ((blob5minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob5minY) < `CONT_RANGE) || + ((blob5minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob5minY) < `CONT_RANGE) || + ((blob5maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob5maxY) < `CONT_RANGE) || + ((blob5maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob5maxY) < `CONT_RANGE)) begin + + if( ((blob5minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob5minX) < `CONT_RANGE) || + ((blob5minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob5minX) < `CONT_RANGE) || + ((blob5maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob5maxX) < `CONT_RANGE) || + ((blob5maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob5maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[3]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob1empty==`FALSE) begin + if( ((blob6minY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob6minY) < `CONT_RANGE) || + ((blob6minY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob6minY) < `CONT_RANGE) || + ((blob6maxY-blob1minY) < `CONT_RANGE) || ((blob1minY-blob6maxY) < `CONT_RANGE) || + ((blob6maxY-blob1maxY) < `CONT_RANGE) || ((blob1maxY-blob6maxY) < `CONT_RANGE)) begin + + if( ((blob6minX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob6minX) < `CONT_RANGE) || + ((blob6minX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob6minX) < `CONT_RANGE) || + ((blob6maxX-blob1minX) < `CONT_RANGE) || ((blob1minX-blob6maxX) < `CONT_RANGE) || + ((blob6maxX-blob1maxX) < `CONT_RANGE) || ((blob1maxX-blob6maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[10]<=`TRUE; + end + end + end + +//MERGE TO CONTAINER 2 + if(blob3empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[4]<=`TRUE; + end + end + end + if(blob4empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob4minY) < `CONT_RANGE) || ((blob4minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob4maxY) < `CONT_RANGE) || ((blob4maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob4minY) < `CONT_RANGE) || ((blob4minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob4maxY) < `CONT_RANGE) || ((blob4maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob4minX) < `CONT_RANGE) || ((blob4minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob4maxX) < `CONT_RANGE) || ((blob4maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob4minX) < `CONT_RANGE) || ((blob4minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob4maxX) < `CONT_RANGE) || ((blob4maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[5]<=`TRUE; + end + end + end + if(blob5empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[6]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob2empty==`FALSE) begin + if( ((blob2minY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob2minY) < `CONT_RANGE) || + ((blob2minY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob2minY) < `CONT_RANGE) || + ((blob2maxY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob2maxY) < `CONT_RANGE) || + ((blob2maxY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob2maxY) < `CONT_RANGE) )begin + + if( ((blob2minX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob2minX) < `CONT_RANGE) || + ((blob2minX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob2minX) < `CONT_RANGE) || + ((blob2maxX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob2maxX) < `CONT_RANGE) || + ((blob2maxX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob2maxX) < `CONT_RANGE) )begin + ContainerAdjacentResult[11]<=`TRUE; + end + end + end + +//MERGE CONTAINER 3 + if(blob4empty==`FALSE && blob3empty==`FALSE) begin + if( ((blob4minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[7]<=`TRUE; + end + end + end + if(blob5empty==`FALSE && blob3empty==`FALSE) begin + if( ((blob5minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob5minY) < `CONT_RANGE) || + ((blob5minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob5minY) < `CONT_RANGE) || + ((blob5maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob5maxY) < `CONT_RANGE) || + ((blob5maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob5maxY) < `CONT_RANGE)) begin + + if( ((blob5minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob5minX) < `CONT_RANGE) || + ((blob5minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob5minX) < `CONT_RANGE) || + ((blob5maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob5maxX) < `CONT_RANGE) || + ((blob5maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob5maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[8]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob3empty==`FALSE) begin + if( ((blob6minY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob6minY) < `CONT_RANGE) || + ((blob6minY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob6minY) < `CONT_RANGE) || + ((blob6maxY-blob3minY) < `CONT_RANGE) || ((blob3minY-blob6maxY) < `CONT_RANGE) || + ((blob6maxY-blob3maxY) < `CONT_RANGE) || ((blob3maxY-blob6maxY) < `CONT_RANGE)) begin + + if( ((blob6minX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob6minX) < `CONT_RANGE) || + ((blob6minX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob6minX) < `CONT_RANGE) || + ((blob6maxX-blob3minX) < `CONT_RANGE) || ((blob3minX-blob6maxX) < `CONT_RANGE) || + ((blob6maxX-blob3maxX) < `CONT_RANGE) || ((blob3maxX-blob6maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[12]<=`TRUE; + end + end + end + +//MERGE CONTAINER 4 + if(blob5empty==`FALSE && blob4empty==`FALSE) begin + if( ((blob4minY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob5minY) < `CONT_RANGE) || ((blob5minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob5maxY) < `CONT_RANGE) || ((blob5maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob5minX) < `CONT_RANGE) || ((blob5minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob5maxX) < `CONT_RANGE) || ((blob5maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[9]<=`TRUE; + end + end + end + if(blob6empty==`FALSE && blob4empty==`FALSE) begin + if( ((blob4minY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob4minY) < `CONT_RANGE) || + ((blob4minY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob4minY) < `CONT_RANGE) || + ((blob4maxY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob4maxY) < `CONT_RANGE) || + ((blob4maxY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob4maxY) < `CONT_RANGE)) begin + + if( ((blob4minX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob4minX) < `CONT_RANGE) || + ((blob4minX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob4minX) < `CONT_RANGE) || + ((blob4maxX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob4maxX) < `CONT_RANGE) || + ((blob4maxX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob4maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[13]<=`TRUE; + end + end + end +//MERGE CONTAINER 5 + if(blob6empty==`FALSE && blob5empty==`FALSE) begin + if( ((blob5minY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob5minY) < `CONT_RANGE) || + ((blob5minY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob5minY) < `CONT_RANGE) || + ((blob5maxY-blob6minY) < `CONT_RANGE) || ((blob6minY-blob5maxY) < `CONT_RANGE) || + ((blob5maxY-blob6maxY) < `CONT_RANGE) || ((blob6maxY-blob5maxY) < `CONT_RANGE)) begin + + if( ((blob5minX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob5minX) < `CONT_RANGE) || + ((blob5minX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob5minX) < `CONT_RANGE) || + ((blob5maxX-blob6minX) < `CONT_RANGE) || ((blob6minX-blob5maxX) < `CONT_RANGE) || + ((blob5maxX-blob6maxX) < `CONT_RANGE) || ((blob6maxX-blob5maxX) < `CONT_RANGE)) begin + ContainerAdjacentResult[14]<=`TRUE; + end + end + end + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONTAINER: begin + if(ContainerAdjacentResult>0) begin + + if(ContainerAdjacentResult[14]==1'b1) begin + state<= `MERGE_CONT_5_6; + end + else if(ContainerAdjacentResult[13]==1'b1) begin + state<= `MERGE_CONT_4_6; + end + else if(ContainerAdjacentResult[9]==1'b1) begin + state<= `MERGE_CONT_4_5; + end + else if(ContainerAdjacentResult[12]==1'b1) begin + state<= `MERGE_CONT_3_6; + end + else if(ContainerAdjacentResult[8]==1'b1) begin + state<= `MERGE_CONT_3_5; + end + else if(ContainerAdjacentResult[7]==1'b1) begin + state<= `MERGE_CONT_3_4; + end + else if(ContainerAdjacentResult[11]==1'b1) begin + state<= `MERGE_CONT_2_6; + end + else if(ContainerAdjacentResult[6]==1'b1) begin + state<= `MERGE_CONT_2_5; + end + else if(ContainerAdjacentResult[5]==1'b1) begin + state<= `MERGE_CONT_2_4; + end + else if(ContainerAdjacentResult[4]==1'b1) begin + state<= `MERGE_CONT_2_3; + end + else if(ContainerAdjacentResult[10]==1'b1) begin + state<= `MERGE_CONT_1_6; + end + else if(ContainerAdjacentResult[3]==1'b1) begin + state<= `MERGE_CONT_1_5; + end + else if(ContainerAdjacentResult[2]==1'b1) begin + state<= `MERGE_CONT_1_4; + end + else if(ContainerAdjacentResult[1]==1'b1) begin + state<= `MERGE_CONT_1_3; + end + else if(ContainerAdjacentResult[0]==1'b1) begin + state<= `MERGE_CONT_1_2; + end + + + end + else begin + state<=`IDLE; + end + end + + `MERGE_CONT_1_2: begin + if(blob2maxX > blob1maxX) blob1maxX <= blob2maxX; + if(blob2maxY > blob1maxY) blob1maxY <= blob2maxY; + if(blob2minX < blob1minX) blob1minX <= blob2minX; + if(blob2minY < blob1minY) blob1minY <= blob2minY; + ContainerAdjacentResult[0]<=`FALSE; + blob2empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_3: begin + if(blob3maxX > blob1maxX) blob1maxX <= blob3maxX; + if(blob3maxY > blob1maxY) blob1maxY <= blob3maxY; + if(blob3minX < blob1minX) blob1minX <= blob3minX; + if(blob3minY < blob1minY) blob1minY <= blob3minY; + ContainerAdjacentResult[1]<=`FALSE; + blob3empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_4: begin + if(blob4maxX > blob1maxX) blob1maxX <= blob4maxX; + if(blob4maxY > blob1maxY) blob1maxY <= blob4maxY; + if(blob4minX < blob1minX) blob1minX <= blob4minX; + if(blob4minY < blob1minY) blob1minY <= blob4minY; + ContainerAdjacentResult[2]<=`FALSE; + blob4empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_5: begin + if(blob5maxX > blob1maxX) blob1maxX <= blob5maxX; + if(blob5maxY > blob1maxY) blob1maxY <= blob5maxY; + if(blob5minX < blob1minX) blob1minX <= blob5minX; + if(blob5minY < blob1minY) blob1minY <= blob5minY; + ContainerAdjacentResult[3]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_1_6: begin + if(blob6maxX > blob1maxX) blob1maxX <= blob6maxX; + if(blob6maxY > blob1maxY) blob1maxY <= blob6maxY; + if(blob6minX < blob1minX) blob1minX <= blob6minX; + if(blob6minY < blob1minY) blob1minY <= blob6minY; + ContainerAdjacentResult[10]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_3: begin + if(blob3maxX > blob2maxX) blob2maxX <= blob3maxX; + if(blob3maxY > blob2maxY) blob2maxY <= blob3maxY; + if(blob3minX < blob2minX) blob2minX <= blob3minX; + if(blob3minY < blob2minY) blob2minY <= blob3minY; + ContainerAdjacentResult[4]<=`FALSE; + blob3empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_4: begin + if(blob4maxX > blob2maxX) blob2maxX <= blob4maxX; + if(blob4maxY > blob2maxY) blob2maxY <= blob4maxY; + if(blob4minX < blob2minX) blob2minX <= blob4minX; + if(blob4minY < blob2minY) blob2minY <= blob4minY; + ContainerAdjacentResult[5]<=`FALSE; + blob4empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_5: begin + if(blob5maxX > blob2maxX) blob2maxX <= blob5maxX; + if(blob5maxY > blob2maxY) blob2maxY <= blob5maxY; + if(blob5minX < blob2minX) blob2minX <= blob5minX; + if(blob5minY < blob2minY) blob2minY <= blob5minY; + ContainerAdjacentResult[6]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_2_6: begin + if(blob6maxX > blob2maxX) blob2maxX <= blob6maxX; + if(blob6maxY > blob2maxY) blob2maxY <= blob6maxY; + if(blob6minX < blob2minX) blob2minX <= blob6minX; + if(blob6minY < blob2minY) blob2minY <= blob6minY; + ContainerAdjacentResult[11]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_3_4: begin + if(blob4maxX > blob3maxX) blob3maxX <= blob4maxX; + if(blob4maxY > blob3maxY) blob3maxY <= blob4maxY; + if(blob4minX < blob3minX) blob3minX <= blob4minX; + if(blob4minY < blob3minY) blob3minY <= blob4minY; + ContainerAdjacentResult[7]<=`FALSE; + blob4empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_3_5: begin + if(blob5maxX > blob3maxX) blob3maxX <= blob5maxX; + if(blob5maxY > blob3maxY) blob3maxY <= blob5maxY; + if(blob5minX < blob3minX) blob3minX <= blob5minX; + if(blob5minY < blob3minY) blob3minY <= blob5minY; + ContainerAdjacentResult[8]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_3_6: begin + if(blob6maxX > blob3maxX) blob3maxX <= blob6maxX; + if(blob6maxY > blob3maxY) blob3maxY <= blob6maxY; + if(blob6minX < blob3minX) blob3minX <= blob6minX; + if(blob6minY < blob3minY) blob3minY <= blob6minY; + ContainerAdjacentResult[12]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_4_5: begin + if(blob5maxX > blob4maxX) blob4maxX <= blob5maxX; + if(blob5maxY > blob4maxY) blob4maxY <= blob5maxY; + if(blob5minX < blob4minX) blob4minX <= blob5minX; + if(blob5minY < blob4minY) blob4minY <= blob5minY; + ContainerAdjacentResult[9]<=`FALSE; + blob5empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_4_6: begin + if(blob6maxX > blob4maxX) blob4maxX <= blob6maxX; + if(blob6maxY > blob4maxY) blob4maxY <= blob6maxY; + if(blob6minX < blob4minX) blob4minX <= blob6minX; + if(blob6minY < blob4minY) blob4minY <= blob6minY; + ContainerAdjacentResult[13]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + `MERGE_CONT_5_6: begin + if(blob6maxX > blob5maxX) blob5maxX <= blob6maxX; + if(blob6maxY > blob5maxY) blob5maxY <= blob6maxY; + if(blob6minX < blob5minX) blob5minX <= blob6minX; + if(blob6minY < blob5minY) blob5minY <= blob6minY; + ContainerAdjacentResult[14]<=`FALSE; + blob6empty<=`TRUE; + + state<= `MERGE_CONTAINER; + end + + endcase + end +end + + +//perform center of mass computation +//delay of 1 clock tick +//CenterOfMass BlobCenterComputation1( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_1), +// .inSumPosX(sumBLOB_Xpositions_1), +// .inSumPosY(sumBLOB_Ypositions_1), +// .outBlobXcenter(blob1X_com_center), +// .outBlobYcenter(blob1Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation2( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_2), +// .inSumPosX(sumBLOB_Xpositions_2), +// .inSumPosY(sumBLOB_Ypositions_2), +// .outBlobXcenter(blob2X_com_center), +// .outBlobYcenter(blob2Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation3( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_3), +// .inSumPosX(sumBLOB_Xpositions_3), +// .inSumPosY(sumBLOB_Ypositions_3), +// .outBlobXcenter(blob3X_com_center), +// .outBlobYcenter(blob3Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation4( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_4), +// .inSumPosX(sumBLOB_Xpositions_4), +// .inSumPosY(sumBLOB_Ypositions_4), +// .outBlobXcenter(blob4X_com_center), +// .outBlobYcenter(blob4Y_com_center)); +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation5( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_5), +// .inSumPosX(sumBLOB_Xpositions_5), +// .inSumPosY(sumBLOB_Ypositions_5), +// .outBlobXcenter(blob5X_com_center), +// .outBlobYcenter(blob5Y_com_center)); +// +// +////perform center of mass computation +////delay of 1 clock tick +//CenterOfMass BlobCenterComputation6( +// .iCLK(iCOMclock), +// .iEnable(enableCOMcomputation), +// .inSumPixels(sumBLOB_Pixels_6), +// .inSumPosX(sumBLOB_Xpositions_6), +// .inSumPosY(sumBLOB_Ypositions_6), +// .outBlobXcenter(blob6X_com_center), +// .outBlobYcenter(blob6Y_com_center)); + +endmodule + + +module divider(//clk, + opa, opb, quo, rem + //testy , testy2, testy_diff, dividend_test + ); + input [10:0] opa; + input [3:0] opb; + output [10:0] quo, rem; + //input clk; +//output [49:0] testy; +//output [49:0] testy2; +//output [49:0] testy_diff; +//output [49:0] dividend_test; + + +//assign testy_diff = diff27; +//assign testy = quotient26; +//assign testy2 = divider_copy26; +//assign dividend_test = dividend_copy26; + + + + reg [10:0] quo, rem; + +// """"""""| +// 1011 | <---- dividend_copy +// -0011 | <---- divider_copy +// """"""""| 0 Difference is negative: copy dividend and put 0 in quotient. +// 1011 | <---- dividend_copy +// -0011 | <---- divider_copy +// """"""""| 00 Difference is negative: copy dividend and put 0 in quotient. +// 1011 | <---- dividend_copy +// -0011 | <---- divider_copy +// """"""""| 001 Difference is positive: use difference and put 1 in quotient. +// quotient (numbers above) + + reg [10:0] quotient0; + reg [10:0] dividend_copy0, diff0; + reg [10:0] divider_copy0; + wire [10:0] remainder0; + + reg [10:0] quotient1; + reg [10:0] dividend_copy1, diff1; + reg [10:0] divider_copy1; + wire [10:0] remainder1; + + reg [10:0] quotient2; + reg [10:0] dividend_copy2, diff2; + reg [10:0] divider_copy2; + wire [10:0] remainder2; + + reg [10:0] quotient3; + reg [10:0] dividend_copy3, diff3; + reg [10:0] divider_copy3; + wire [10:0] remainder3; + + reg [10:0] quotient4; + reg [10:0] dividend_copy4, diff4; + reg [10:0] divider_copy4; + wire [10:0] remainder4; + + reg [10:0] quotient5; + reg [10:0] dividend_copy5, diff5; + reg [10:0] divider_copy5; + wire [10:0] remainder5; + + reg [10:0] quotient6; + reg [10:0] dividend_copy6, diff6; + reg [10:0] divider_copy6; + wire [10:0] remainder6; + + reg [10:0] quotient7; + reg [10:0] dividend_copy7, diff7; + reg [10:0] divider_copy7; + wire [10:0] remainder7; + + reg [10:0] quotient8; + reg [10:0] dividend_copy8, diff8; + reg [10:0] divider_copy8; + wire [10:0] remainder8; + +always @ (opa or opb) +begin +//stage initial + quotient0 = 11'b00000000000; + dividend_copy0 = opa; + divider_copy0 = {opb,7'b0000000}; + + //stage1 + diff1 = dividend_copy0 - divider_copy0; + quotient1 [10:1] = quotient0[9:0] ; + if (!diff1[10]) // if diff1[10] == 0 (diff is positive, use difference ) + begin + dividend_copy1 = diff1; + quotient1[0] = 1'b1; + end +else // diff was negative, use old dividend +begin +dividend_copy1 = dividend_copy0; + quotient1[0] = 1'b0; + +end + divider_copy1 = (divider_copy0 >> 1); +//stage2 + diff2 = dividend_copy1 - divider_copy1; + quotient2[10:1] = quotient1 [9:0] ; + if (!diff2[10]) + begin + dividend_copy2 = diff2; + quotient2[0] = 1'b1; + end + else +begin +dividend_copy2 = dividend_copy1; + quotient2[0] = 1'b0; + +end + divider_copy2 = divider_copy1 >> 1; + + //stage3 + diff3 = dividend_copy2 - divider_copy2; + quotient3[10:1] = quotient2 [9:0] ; + if (!diff3[10]) + begin + dividend_copy3 = diff3; + quotient3[0] = 1'b1; + end + else +begin +dividend_copy3 = dividend_copy2; + quotient3[0] = 1'b0; + +end + divider_copy3 = divider_copy2 >> 1; + + //stage4 + diff4 = dividend_copy3 - divider_copy3; + quotient4[10:1] = quotient3 [9:0] ; + if (!diff4[10]) + begin + dividend_copy4 = diff4; + quotient4[0] = 1'b1; + end + else +begin +dividend_copy4 = dividend_copy3; + quotient4[0] = 1'b0; + +end + divider_copy4 = divider_copy3 >> 1; + //stage5 + diff5 = dividend_copy4 - divider_copy4; + quotient5[10:1] = quotient4 [9:0] ; + if (!diff5[10]) + begin + dividend_copy5 = diff5; + quotient5[0] = 1'b1; + end + else +begin +dividend_copy5 = dividend_copy4; + quotient5[0] = 1'b0; + +end + divider_copy5 = divider_copy4 >> 1; + //stage6 + diff6 = dividend_copy5 - divider_copy5; + quotient6[10:1] = quotient5 [9:0] ; + if (!diff6[10]) + begin + dividend_copy6 = diff6; + quotient6[0] = 1'b1; + end + else +begin +dividend_copy6 = dividend_copy5; + quotient6[0] = 1'b0; + +end + divider_copy6 = divider_copy5>> 1; + + //stage7 + diff7 = dividend_copy6 - divider_copy6; + quotient7[10:1] = quotient6 [9:0] ; + if (!diff7[10]) + begin + dividend_copy7 = diff7; + quotient7[0] = 1'b1; + end + else +begin +dividend_copy7 = dividend_copy6; + quotient7[0] = 1'b0; + +end + divider_copy7 = divider_copy6>> 1; + //stage8 + diff8 = dividend_copy7 - divider_copy7; + quotient8[10:1] = quotient7 [9:0] ; + if (!diff8[10]) + begin + dividend_copy8 = diff8; + quotient8[0] = 1'b1; + end + else +begin +dividend_copy8 = dividend_copy7; + quotient8[0] = 1'b0; + +end + divider_copy8 = divider_copy7>> 1; + +quo = quotient8; +rem = dividend_copy8; + +end + + //integer i; + + /* +always @(opa,opb) +begin + for (i=-1; i<8; i=i+1) +begin +if (i==-1) +begin + // initialization +quotient = 10'd0; +dividend_copy = opa; +divider_copy = {opb,7'd0}; +end +else +begin +diff = dividend_copy - divider_copy; +quotient = quotient ; + +if( !diff[10] ) +begin +dividend_copy = diff; +quotient[0] = 1'd1; +end +divider_copy = divider_copy >> 1; +end +end +end +*/ + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v b/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v new file mode 100755 index 000000000..a749b99d0 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v @@ -0,0 +1,2820 @@ + module paj_boundtop_hierarchy_no_mem (triIDvalid, triID, wanttriID, raydata, rayaddr, raywe, resultready, resultdata, globalreset, want_braddr, braddr_ready, braddrin, want_brdata, brdata_ready, brdatain, want_addr2, addr2_ready, addr2in, want_data2, data2_ready, data2in, pglobalreset, tm3_clk_v0, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource, input1); + + + output triIDvalid; + wire triIDvalid; + output[15:0] triID; + wire[15:0] triID; + input wanttriID; + output[31:0] raydata; + wire[31:0] raydata; + output[3:0] rayaddr; + wire[3:0] rayaddr; + output[2:0] raywe; + wire[2:0] raywe; + input resultready; + input[31:0] resultdata; + output globalreset; + wire globalreset; + output want_braddr; + wire want_braddr; + input braddr_ready; + input[9:0] braddrin; + output want_brdata; + wire want_brdata; + input brdata_ready; + input[31:0] brdatain; + output want_addr2; + wire want_addr2; + input addr2_ready; + input[17:0] addr2in; + output want_data2; + wire want_data2; + input data2_ready; + input[63:0] data2in; + input pglobalreset; + input tm3_clk_v0; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + wire[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + wire[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + wire[1:0] tm3_sram_oe; + output tm3_sram_adsp; + wire tm3_sram_adsp; + input[1:0] raygroup01; + input raygroupvalid01; + output busy01; + wire busy01; + input[1:0] raygroup10; + input raygroupvalid10; + output busy10; + wire busy10; + input[31:0] rgData; + input[3:0] rgAddr; + input[2:0] rgWE; + input rgAddrValid; + output rgDone; + wire rgDone; + output[31:0] rgResultData; + wire[31:0] rgResultData; + output rgResultReady; + wire rgResultReady; + output[1:0] rgResultSource; + wire[1:0] rgResultSource; + input input1; + wire raygroupwe; + wire raygroupwe01; + wire raygroupwe10; + wire[1:0] raygroupout; + wire[1:0] raygroupout01; + wire[1:0] raygroupout10; + wire[1:0] raygroupid; + wire[1:0] raygroupid01; + wire[1:0] raygroupid10; + reg[1:0] oldresultid; + wire[1:0] resultid; + wire[31:0] t1i; + wire[31:0] t2i; + wire[31:0] t3i; + wire[15:0] u1i; + wire[15:0] u2i; + wire[15:0] u3i; + wire[15:0] v1i; + wire[15:0] v2i; + wire[15:0] v3i; + wire[15:0] id1i; + wire[15:0] id2i; + wire[15:0] id3i; + wire hit1i; + wire hit2i; + wire hit3i; + wire newresult; + wire write; + reg reset; + wire reset01; + wire reset10; + wire[103:0] peekdata; + reg[103:0] peeklatch; + wire commit01; + wire commit10; + wire[1:0] baseaddress01; + wire[1:0] baseaddress10; + wire[1:0] done; + wire cntreset; + wire cntreset01; + wire cntreset10; + wire passCTS01; + wire passCTS10; + wire triIDvalid01; + wire triIDvalid10; + wire[15:0] triID01; + wire[15:0] triID10; + reg[9:0] boundNodeID; + wire[9:0] BoundNodeID01; + wire[9:0] BoundNodeID10; + wire enablenear; + wire enablenear01; + wire enablenear10; + wire ack01; + wire ack10; + wire empty01; + wire dataready01; + wire empty10; + wire dataready10; + wire lhreset01; + wire lhreset10; + wire[9:0] boundnodeIDout01; + wire[9:0] boundnodeIDout10; + wire[1:0] level01; + wire[1:0] level10; + wire[2:0] hitmask01; + wire[2:0] hitmask10; + // Offset Block Ram Read Signals + wire[9:0] ostaddr; + wire[9:0] addrind01; + wire[9:0] addrind10; + wire ostaddrvalid; + wire addrindvalid01; + wire addrindvalid10; + wire ostdatavalid; + wire[31:0] ostdata; + // Tri List Ram Read Signals + wire[17:0] tladdr; + wire[17:0] tladdr01; + wire[17:0] tladdr10; + wire tladdrvalid; + wire tladdrvalid01; + wire tladdrvalid10; + wire tldatavalid; +wire[63:0] tldata; + // Final Result Signals + wire[31:0] t1_01; + wire[31:0] t2_01; + wire[31:0] t3_01; + wire[31:0] t1_10; + wire[31:0] t2_10; + wire[31:0] t3_10; + wire[15:0] v1_01; + wire[15:0] v2_01; + wire[15:0] v3_01; + wire[15:0] v1_10; + wire[15:0] v2_10; + wire[15:0] v3_10; + wire[15:0] u1_01; + wire[15:0] u2_01; + wire[15:0] u3_01; + wire[15:0] u1_10; + wire[15:0] u2_10; + wire[15:0] u3_10; + wire[15:0] id1_01; + wire[15:0] id2_01; + wire[15:0] id3_01; + wire[15:0] id1_10; + wire[15:0] id2_10; + wire[15:0] id3_10; + wire hit1_01; + wire hit2_01; + wire hit3_01; + wire hit1_10; + wire hit2_10; + wire hit3_10; + wire bcvalid01; + wire bcvalid10; + wire[2:0] peekoffset1a; + wire[2:0] peekoffset1b; + wire[2:0] peekoffset0a; + wire[2:0] peekoffset0b; + wire[2:0] peekoffset2a; + wire[2:0] peekoffset2b; + wire[4:0] peekaddressa; + wire[4:0] peekaddressb; + wire doutput; + wire dack; + wire[4:0] state01; + wire[4:0] state10; + wire[2:0] junk1; + wire[2:0] junk1b; + wire junk2; + wire junk2a; + wire[1:0] junk3; + wire[1:0] junk4; + wire[13:0] debugcount01; + wire[13:0] debugcount10; + wire[1:0] debugsubcount01; + wire[1:0] debugsubcount10; + wire[2:0] statesram; + + onlyonecycle oc (input1, doutput, pglobalreset, tm3_clk_v0); + // Real Stuff Starts Here + assign ostaddr = addrind01 | addrind10 ; + assign ostaddrvalid = addrindvalid01 | addrindvalid10 ; + + vblockramcontroller offsettable(want_braddr, braddr_ready, braddrin, want_brdata, brdata_ready, brdatain, ostaddr, ostaddrvalid, ostdata, ostdatavalid, pglobalreset, tm3_clk_v0); + assign tladdr = tladdr01 | tladdr10 ; + assign tladdrvalid = tladdrvalid01 | tladdrvalid10 ; + sramcontroller trilist (want_addr2, addr2_ready, addr2in, want_data2, data2_ready, data2in, tladdr, tladdrvalid, tldata, tldatavalid, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, pglobalreset, tm3_clk_v0, statesram); + resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); + rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); + boundcontroller boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01); + boundcontroller boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01); + resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); + +assign raygroupout = raygroupout01 | raygroupout10 ; + assign raygroupwe = raygroupwe01 | raygroupwe10 ; + assign raygroupid = raygroupid01 | raygroupid10 ; + assign triIDvalid = triIDvalid01 | triIDvalid10 ; + assign enablenear = enablenear01 | enablenear10 ; + assign triID = triID01 | triID10 ; + assign cntreset = cntreset01 | cntreset10 ; + + // reset <= reset01 or reset10; + always @(BoundNodeID01 or BoundNodeID10 or resultid) + begin + if (resultid == 2'b01) + begin + boundNodeID = BoundNodeID01 ; + end + else if (resultid == 2'b10) + begin + boundNodeID = BoundNodeID10 ; + end + else + begin + boundNodeID = 10'b0000000000 ; + end + end + assign write = ((newresult == 1'b1) & (resultid != 0) & ((hit1i == 1'b1) | (hit2i == 1'b1) | (hit3i == 1'b1))) ? 1'b1 : 1'b0 ; + + sortedstack st(t1i, {hit3i, hit2i, hit1i, boundNodeID}, write, reset, peekdata, pglobalreset, tm3_clk_v0); + assign commit01 = (done == 2'b01) ? 1'b1 : 1'b0 ; + assign commit10 = (done == 2'b10) ? 1'b1 : 1'b0 ; + assign dack = doutput | ack01 ; + listhandler lh01 (peeklatch, commit01, hitmask01, dack, boundnodeIDout01, level01, empty01, dataready01, lhreset01, pglobalreset, tm3_clk_v0, peekoffset0a, peekoffset1a, peekoffset2a, junk2a, junk4); + listhandler lh02 (peeklatch, commit10, hitmask10, ack10, boundnodeIDout10, level10, empty10, dataready10, lhreset10, pglobalreset, tm3_clk_v0, junk1, junk1b, peekoffset2b, junk2, junk3); + + always @(posedge tm3_clk_v0) + begin + if (pglobalreset == 1'b1) + begin + peeklatch <= 0; + reset <= 1'b0 ; + oldresultid <= 2'b00 ; + end + else + begin + oldresultid <= resultid ; + // The reset is only for debugging + if (resultid != oldresultid) + begin + reset <= 1'b1 ; + end + else + begin + reset <= 1'b0 ; + end + if (done != 0) + begin + peeklatch <= peekdata ; + end + end + end + + resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0); + endmodule + + + + + + + + + + + + + + +module resulttransmit (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + input valid01; + input valid10; + input[15:0] id01a; + input[15:0] id01b; + input[15:0] id01c; + input[15:0] id10a; + input[15:0] id10b; + input[15:0] id10c; + input hit01a; + input hit01b; + + input hit01c; + input hit10a; + input hit10b; + input hit10c; + input[15:0] u01a; + input[15:0] u01b; + input[15:0] u01c; + input[15:0] v01a; + input[15:0] v01b; + input[15:0] v01c; + input[15:0] u10a; + input[15:0] u10b; + + input[15:0] u10c; + input[15:0] v10a; + input[15:0] v10b; + input[15:0] v10c; + output[31:0] rgResultData; + reg[31:0] rgResultData; + output rgResultReady; + reg rgResultReady; + output[1:0] rgResultSource; + reg[1:0] rgResultSource; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + + reg hit01al; + reg hit01bl; + reg hit01cl; + reg hit10al; + reg hit10bl; + reg hit10cl; + reg pending01; + reg pending10; + reg valid01d; + reg valid10d; + +reg[31:0] temp_rgResultData; + reg temp_rgResultReady; + reg[1:0] temp_rgResultSource; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + pending01 <= 1'b0 ; + pending10 <= 1'b0 ; + rgResultData <= 32'b00000000000000000000000000000000 ; + rgResultSource <= 2'b00 ; + + rgResultReady <= 1'b0 ; + end + else + begin + valid01d <= valid01 ; + valid10d <= valid10 ; + if (valid01 == 1'b1) + begin + pending01 <= 1'b1 ; + end + if (valid01d == 1'b1) + begin + hit01al <= hit01a ; + hit01bl <= hit01b ; + hit01cl <= hit01c ; + end + if (valid10 == 1'b1) + begin + pending10 <= 1'b1 ; + end + if (valid10d == 1'b1) + begin + hit10al <= hit10a ; + hit10bl <= hit10b ; + hit10cl <= hit10c ; + end + state <= next_state ; + + rgResultData <= temp_rgResultData; + rgResultReady <= temp_rgResultReady; + rgResultSource <= temp_rgResultSource; + end + end + + always @(state or pending01 or pending10) + begin + case (state) + 0 : + begin + if (pending01 == 1'b1) + begin + next_state = 1 ; + end + else if (pending10 == 1'b1) + begin + next_state = 5 ; + end + else + + begin + next_state = 0 ; + end + end + 1 : + begin + next_state = 2 ; + temp_rgResultData = {id01a, id01b} ; + temp_rgResultReady = 1'b1 ; + temp_rgResultSource = 2'b01 ; + end + 2 : + begin + next_state = 3 ; + temp_rgResultData = {13'b0000000000000, hit01al, hit01bl, hit01cl, id01c} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + + 3 : + begin + next_state = 4 ; + temp_rgResultData = {8'b00000000, u01a[15:8], u01b[15:8], u01c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + 4 : + begin + next_state = 0 ; + temp_rgResultData = {8'b00000000, v01a[15:8], v01b[15:8], v01c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b01 ; + end + 5 : + begin + next_state = 6 ; + temp_rgResultData = {id10a, id10b} ; + temp_rgResultReady = 1'b1 ; + temp_rgResultSource = 2'b10 ; + end + 6 : + begin + next_state = 7 ; + temp_rgResultData = {13'b0000000000000, hit10al, hit10bl, hit10cl, id10c} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + 7 : + begin + next_state = 8 ; + temp_rgResultData = {8'b00000000, u10a[15:8], u10b[15:8], u10c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + 8 : + begin + next_state = 0 ; + temp_rgResultData = {8'b00000000, v10a[15:8], v10b[15:8], v10c[15:8]} ; + temp_rgResultReady = 1'b0 ; + temp_rgResultSource = 2'b10 ; + end + default: + begin + temp_rgResultReady = u01a || u01b || u01c || v01a || v01b || v01c || u10a || u10b || u10c || v10a || v10b || v10c; + end + endcase + end + endmodule + + + + + + + + + + + + + + + + + + + + + + + + + +module boundcontroller (raygroupout, raygroupwe, raygroupid, enablenear, raygroup, validraygroup, busy, triIDvalid, triID, wanttriID, l0reset, baseaddress, newdata, boundNodeIDout, resultID, hitmask, ldataready, lempty, llevel, lboundNodeID, lack, lhreset, addrind, addrindvalid, dataind, dataindvalid, tladdr, tladdrvalid, tldata, tldatavalid, t1in, t2in, t3in, u1in, u2in, u3in, v1in, v2in, v3in, id1in, id2in, id3in, hit1in, hit2in, hit3in, t1, t2, t3, u1, u2, u3, v1, v2, v3, id1, id2, id3, hit1, hit2, hit3, bcvalid, done, resetcnt, passCTSout, passCTSin, globalreset, clk, statepeek, debugsubcount, debugcount); + + output[1:0] raygroupout; + wire[1:0] raygroupout; + output raygroupwe; + reg raygroupwe; + output[1:0] raygroupid; + reg[1:0] raygroupid; + output enablenear; + reg enablenear; + input[1:0] raygroup; + input validraygroup; + output busy; + reg busy; + reg temp_busy; + output triIDvalid; + reg triIDvalid; + output[15:0] triID; + reg[15:0] triID; + input wanttriID; + output l0reset; + reg l0reset; + output[1:0] baseaddress; + reg[1:0] baseaddress; + input newdata; + output[9:0] boundNodeIDout; + reg[9:0] boundNodeIDout; + input[1:0] resultID; + output[2:0] hitmask; + reg[2:0] hitmask; + input ldataready; + input lempty; + input[1:0] llevel; + input[9:0] lboundNodeID; + output lack; + reg lack; + output lhreset; + reg lhreset; + output[9:0] addrind; + reg[9:0] addrind; + output addrindvalid; + reg addrindvalid; + input[31:0] dataind; + input dataindvalid; + output[17:0] tladdr; + reg[17:0] tladdr; + output tladdrvalid; + reg tladdrvalid; + input[63:0] tldata; + input tldatavalid; + input[31:0] t1in; + input[31:0] t2in; + input[31:0] t3in; + input[15:0] u1in; + input[15:0] u2in; + input[15:0] u3in; + input[15:0] v1in; + input[15:0] v2in; + input[15:0] v3in; + input[15:0] id1in; + input[15:0] id2in; + input[15:0] id3in; + input hit1in; + input hit2in; + input hit3in; + output[31:0] t1; + reg[31:0] t1; + output[31:0] t2; + reg[31:0] t2; + output[31:0] t3; + reg[31:0] t3; + output[15:0] u1; + reg[15:0] u1; + output[15:0] u2; + reg[15:0] u2; + output[15:0] u3; + reg[15:0] u3; + output[15:0] v1; + reg[15:0] v1; + output[15:0] v2; + reg[15:0] v2; + output[15:0] v3; + reg[15:0] v3; + output[15:0] id1; + reg[15:0] id1; + output[15:0] id2; + reg[15:0] id2; + output[15:0] id3; + reg[15:0] id3; + output hit1; + reg hit1; + output hit2; + reg hit2; + output hit3; + reg hit3; + output bcvalid; + reg bcvalid; + input[1:0] done; + output resetcnt; + reg resetcnt; + output passCTSout; + reg passCTSout; + input passCTSin; + input globalreset; + input clk; + output[4:0] statepeek; + reg[4:0] statepeek; + output[1:0] debugsubcount; + wire[1:0] debugsubcount; + output[13:0] debugcount; + wire[13:0] debugcount; + + reg[4:0] state; + reg[4:0] next_state; + reg cts; + reg[11:0] addr; + reg[11:0] startAddr; + reg[2:0] resetcount; + reg[1:0] raygroupoutl; + // Leaf Node Signals + reg[13:0] count; + reg[63:0] triDatalatch; + reg[1:0] subcount; + reg[1:0] maskcount; + + reg[4:0] temp_statepeek; + reg [1:0]temp_raygroupoutl ; + reg temp_cts ; + reg temp_passCTSout ; + reg [2:0]temp_resetcount ; + reg temp_l0reset ; + reg [11:0]temp_addr ; + reg [11:0]temp_startAddr ; + reg [9:0]temp_boundNodeIDout ; + reg [1:0]temp_baseaddress ; + reg [2:0]temp_hitmask ; + reg temp_hit1 ; + reg temp_hit2 ; + reg temp_hit3 ; + reg temp_triIDvalid ; + reg [15:0]temp_triID ; + reg temp_lack ; + reg [9:0]temp_addrind ; + reg temp_addrindvalid ; + reg temp_tladdrvalid ; + reg [17:0]temp_tladdr ; + reg [13:0]temp_count ; + reg [1:0]temp_subcount ; + reg [1:0]temp_maskcount ; + reg [63:0]temp_triDatalatch ; + reg [31:0]temp_t1 ; + reg [15:0]temp_u1 ; + reg [15:0]temp_v1 ; + reg [15:0]temp_id1 ; + reg [31:0]temp_t2 ; + reg [15:0]temp_u2 ; + reg [15:0]temp_v2 ; + reg [15:0]temp_id2 ; + reg [31:0]temp_t3 ; + reg [15:0]temp_u3 ; + reg [15:0]temp_v3 ; + reg [15:0]temp_id3 ; + + assign debugsubcount = subcount ; + assign debugcount = count ; + assign raygroupout = (cts == 1'b1 & state != 8 & state != 19 & state != 1) ? raygroupoutl : 2'b00 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + raygroupoutl <= 0; + cts <= 1'b0 ; + passCTSout <= 1'b0 ; + addr <= 0; + startAddr <= 0; + boundNodeIDout <= 0; + resetcount <= 0; + hitmask <= 1; + lack <= 1'b0 ; + baseaddress <= 0; + l0reset <= 1'b0 ; + resetcnt <= 1'b0 ; + triIDvalid <= 1'b0 ; + triID <= 0; + addrind <= 0; + addrindvalid <= 1'b0 ; + tladdrvalid <= 1'b0 ; + tladdr <= 0; + triDatalatch <= 0; + maskcount <= 0; + subcount <= 0; + count <= 0; + hit1 <= 1'b0 ; + hit2 <= 1'b0 ; + hit3 <= 1'b0 ; + t1 <= 0; + t2 <= 0; + t3 <= 0; + u1 <= 0; + u2 <= 0; + u3 <= 0; + v1 <= 0; + v2 <= 0; + v3 <= 0; + id1 <= 0; + id2 <= 0; + id3 <= 0; + busy <= 1'b0 ; + end + else + begin + state <= next_state ; + busy <= temp_busy; + if ((done == 2'b00) | (state == 15 & newdata == 1'b1 & resultID == 2'b00)) + begin + resetcnt <= 1'b1 ; + end + else + begin + resetcnt <= 1'b0 ; + end + + statepeek <= temp_statepeek; + raygroupoutl <= temp_raygroupoutl ; + cts <= temp_cts ; + passCTSout <= temp_passCTSout ; + resetcount <= temp_resetcount ; + l0reset <= temp_l0reset ; + addr <= temp_addr ; + startAddr <= temp_startAddr ; + boundNodeIDout <= temp_boundNodeIDout ; + baseaddress <= temp_baseaddress ; + hitmask <= temp_hitmask ; + hit1 <= temp_hit1 ; + hit2 <= temp_hit2 ; + hit3 <= temp_hit3 ; + triIDvalid <= temp_triIDvalid ; + triID <= temp_triID ; + lack <= temp_lack ; + addrind <= temp_addrind ; + addrindvalid <= temp_addrindvalid ; + tladdr <= temp_tladdr ; + tladdrvalid <= temp_tladdrvalid ; + count <= temp_count ; + subcount <= temp_subcount ; + maskcount <= temp_maskcount ; + triDatalatch <= temp_triDatalatch ; + t1 <= temp_t1 ; + u1 <= temp_u1 ; + v1 <= temp_v1 ; + id1 <= temp_id1 ; + t2 <= temp_t2 ; + u2 <= temp_u2 ; + v2 <= temp_v2 ; + id2 <= temp_id2 ; + t3 <= temp_t3 ; + u3 <= temp_u3 ; + v3 <= temp_v3 ; + id3 <= temp_id3 ; + end + end + + + + always @* + begin + case (state) + 0 : + begin + raygroupid = 0; + enablenear = 1'b0 ; + raygroupwe = 1'b0 ; + bcvalid = 1'b0 ; + + lhreset = 1'b1 ; + if (validraygroup == 1'b1 & cts == 1'b1) + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + else if (validraygroup == 1'b1 & cts == 1'b0) + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + else if (validraygroup == 1'b0 & passCTSin == 1'b1 & cts == 1'b1) + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + else + begin + next_state = 0 ; + temp_busy = 1'b0 ; + end + + temp_statepeek = 5'b00001 ; + // + temp_raygroupoutl = raygroup ; + if (validraygroup == 1'b1 & cts == 1'b0) + begin + temp_cts = 1'b1 ; + temp_passCTSout = 1'b1 ; + end + else if (validraygroup == 1'b0 & cts == 1'b1 & passCTSin == 1'b1) + begin + temp_cts = 1'b0 ; + temp_passCTSout = 1'b1 ; + end + + end + 1 : + begin + if ((passCTSin == cts) & (cts == 1'b1)) + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + else if (passCTSin == cts) + begin + next_state = 0 ; + temp_busy = 1'b0 ; + end + else + begin + next_state = 1 ; + temp_busy = 1'b0 ; + end + + temp_statepeek = 5'b00010 ; + // + if (passCTSin == cts) + begin + temp_passCTSout = 1'b0 ; + end + + end + 2 : + begin + if (wanttriID == 1'b1) + begin + next_state = 3 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 2 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b00011 ; + // + temp_resetcount = 3'b100 ; + temp_l0reset = 1'b1 ; + temp_addr = 0; + temp_startAddr = 0; + temp_boundNodeIDout = 0; + temp_baseaddress = 0; + temp_hitmask = 1; + temp_hit1 = 1'b0 ; + temp_hit2 = 1'b0 ; + temp_hit3 = 1'b0 ; + end + 3 : + begin + if ((addr - startAddr >= 1) & (addr - startAddr != 49)) + begin + raygroupid = 2'b00 ; + end + next_state = 4 ; + temp_busy = 1'b1 ; + if (resetcount == 5) + begin + raygroupwe = 1'b1 ; + end + enablenear = 1'b1 ; + temp_statepeek = 5'b00100 ; + // + if ((addr - startAddr != 48) & (addr - startAddr != 49)) + begin + temp_triIDvalid = 1'b1 ; + end + temp_triID = {4'b0000, addr} ; + end + 4 : + begin + if (addr - startAddr == 49) + begin + next_state = 6 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 5 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b00101 ; + end + 5 : + begin + next_state = 3 ; + temp_busy = 1'b1 ; + + temp_statepeek = 5'b00111 ; + // + temp_addr = addr + 1 ; + if (resetcount == 5) + begin + temp_resetcount = 3'b000 ; + end + else + begin + temp_resetcount = resetcount + 1 ; + end + + end + 6 : + begin + if (passCTSin == 1'b1 & cts == 1'b1) + begin + next_state = 7; + temp_busy = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b0) + begin + next_state = 8; + temp_busy = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b1) + begin + next_state = 9; + temp_busy = 1'b1 ; + end + else + begin + next_state = 6; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01001 ; + // + if (passCTSin == 1'b1 & cts == 1'b1) + begin + temp_cts = 1'b0 ; + temp_passCTSout = 1'b1 ; + end + else if (done == 2'b00 & cts == 1'b0) + begin + temp_cts = 1'b1 ; + temp_passCTSout = 1'b1 ; + end + + end + 7 : + begin + if (passCTSin == 0) + begin + next_state = 6; + temp_busy = 1'b1 ; + end + else + begin + next_state = 7; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01001 ; + // + if (passCTSin == 1'b0) + begin + temp_passCTSout = 1'b0 ; + end + + end + 8 : + begin + if (passCTSin == 1) + begin + next_state = 9; + temp_busy = 1'b1 ; + end + else + begin + next_state = 8 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01010 ; + // + if (passCTSin == 1'b1) + begin + temp_passCTSout = 1'b0 ; + end + end + 9 : + begin + if (lempty == 1'b1) + begin + next_state = 0 ; + temp_busy = 1'b0 ; + bcvalid = 1'b1 ; + end + else if (ldataready == 1'b1 & llevel == 2'b10) + begin + next_state = 10 ; + temp_busy = 1'b1 ; + end + else if (ldataready == 1'b1 & wanttriID == 1'b1) + begin + next_state = 3 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01011 ; + // + temp_resetcount = 3'b100 ; + temp_baseaddress = llevel + 1 ; + // boundNodeIDout = (lBoundNodeID+1)(6 downto 0) & "000"; + //boundNodeIDout = {(lboundNodeID + 1)[6:0], 3'b000} ; + temp_boundNodeIDout = {lboundNodeID[6:0], 3'b000} ; + // temp_addr = (((lBoundNodeID+1)(7 downto 0) & "0000")+ + // ((lBoundNodeID+1)(6 downto 0) & "00000")) (11 downto 0); + //temp_addr = (({(lboundNodeID + 1)[7:0], 4'b0000}) + ({(lboundNodeID + 1)[6:1], 5'b00000}))[11:0] ; + temp_addr = (({lboundNodeID[7:0], 4'b0000}) + ({lboundNodeID[6:1], 5'b00000})); + // startaddr = (((lBoundNodeID+1)(7 downto 0) & "0000")+ + // ((lBoundNodeID+1)(6 downto 0) & "00000")) (11 downto 0); + //startAddr = (({(lboundNodeID + 1), 4'b0000}) + ({(lboundNodeID + 1), 5'b00000})) ; + temp_startAddr = (({lboundNodeID, 4'b0000}) + ({lboundNodeID, 5'b00000})) ; + if (ldataready == 1'b1 & (wanttriID == 1'b1 | llevel == 2'b10)) + begin + temp_lack = 1'b1 ; + temp_l0reset = 1'b1 ; + end + + if (ldataready == 1'b1 & llevel == 2'b10) + begin + temp_addrind = lboundNodeID - 72 ; + temp_addrindvalid = 1'b1 ; + end + end + 10 : + begin + if (dataindvalid == 1'b1) + begin + next_state = 11 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 10 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01100 ; + // + + temp_tladdr = dataind[17:0] ; + temp_count = dataind[31:18] ; + if (dataindvalid == 1'b1) + begin + temp_addrindvalid = 1'b0 ; + temp_tladdrvalid = 1'b1 ; + end + + end + 11 : + begin + if (count == 0 | count == 1) + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + else if (wanttriID == 1'b1 & tldatavalid == 1'b1) + begin + next_state = 12 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 11 ; + temp_busy = 1'b1 ; + end + + temp_statepeek = 5'b01101 ; + // + + temp_triDatalatch = tldata ; + temp_subcount = 2'b10 ; + temp_maskcount = 2'b00 ; + if ((wanttriID == 1'b1 & tldatavalid == 1'b1) | (count == 0 | count == 1)) + begin + temp_tladdr = tladdr + 1 ; + temp_tladdrvalid = 1'b0 ; + end + + end + 12 : + begin + if (count != 0) + begin + next_state = 13 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + if (subcount == 2'b01) + begin + raygroupid = 2'b00 ; + end + else + begin + raygroupid = 2'b00 ; + end + enablenear = 1'b0 ; + if (subcount == 2'b01 | count == 0) + begin + raygroupwe = 1'b1 ; + end + + temp_statepeek = 5'b01110 ; + // + + if (maskcount == 2'b11) + begin + // triID = triDataLatch(15 downto 0); + temp_triID = triDatalatch[15:0] ; + end + else if (maskcount == 2'b10) + begin + // triID = triDataLatch(31 downto 16); + temp_triID = triDatalatch[31:16] ; + end + else if (maskcount == 2'b01) + begin + // triID = triDataLatch(47 downto 32); + temp_triID = triDatalatch[47:32] ; + end + else + begin + // triID = triDataLatch(63 downto 48); + temp_triID = triDatalatch[63:48] ; + end + if (count != 0) + begin + temp_count = count - 1 ; + if (count != 1) + begin + temp_triIDvalid = 1'b1 ; + end + + if (maskcount == 2'b01) + begin + temp_tladdrvalid = 1'b1 ; + end + end + + end + 13 : + begin + next_state = 14 ; + temp_busy = 1'b1 ; + + temp_statepeek = 5'b01111 ; + end + 14 : + begin + next_state = 12 ; + temp_busy = 1'b1 ; + temp_statepeek = 5'b10000 ; + // + + if (subcount != 0) + begin + temp_subcount = subcount - 1 ; + end + if (maskcount == 2'b11) + begin + temp_tladdr = tladdr + 1 ; + temp_tladdrvalid = 1'b0 ; + temp_triDatalatch = tldata ; + end + temp_maskcount = maskcount + 1 ; + + end + 15 : + begin + if ((newdata == 1'b0 | resultID != 2'b00) & cts == 1'b1 & passCTSin == 1'b1) + begin + next_state = 16 ; + temp_busy = 1'b1 ; + end + else if (newdata == 1'b1 & resultID == 2'b00) + begin + next_state = 18 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10001 ; + // + temp_tladdr = 0; + temp_tladdrvalid = 0; + if ((newdata == 0) | (resultID < 2'b00) & (passCTSin == 1)) + begin + temp_cts = 0; + temp_passCTSout = 1; + end + + end + 16 : + begin + if (newdata == 1'b1 & resultID == 2'b00) + begin + next_state = 17 ; + temp_busy = 1'b1 ; + end + else if (passCTSin == 1'b0) + begin + next_state = 15 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 16 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10010 ; + // + if ((passCTSin == 0) & ((newdata == 0) | (resultID == 1))) + begin + temp_passCTSout = 0; + end + + end + 17 : + begin + if (passCTSin == 1'b0) + begin + next_state = 18 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 17 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10011 ; + // + if (passCTSin == 0) + begin + temp_passCTSout = 0; + end + + + end + 18 : + begin + if (cts == 1'b0 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + next_state = 19 ; + temp_busy = 1'b1 ; + end + else if (cts == 1'b1 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 0 ; + temp_busy = 1'b0 ; + bcvalid = 1'b1 ; + end + temp_statepeek = 5'b10100 ; + // + + + + if (hit1in == 1'b1 & (hitmask[0]) == 1'b1) + begin + temp_t1 = t1in; + temp_u1 = u1in; + temp_v1 = v1in; + temp_id1 = id1in; + temp_hit1 = 1'b1; + temp_hitmask[0] = 1'b0 ; + end + if (hit2in == 1'b1 & (hitmask[1]) == 1'b1) + begin + temp_t2 = t2in ; + temp_u2 = u2in ; + temp_v2 = v2in ; + temp_id2 = id2in ; + temp_hit2 = 1'b1 ; + temp_hitmask[1] = 1'b0 ; + end + if (hit3in == 1'b1 & (hitmask[2]) == 1'b1) + begin + temp_t3 = t3in ; + temp_u3 = u3in ; + temp_v3 = v3in ; + temp_id3 = id3in ; + temp_hit3 = 1'b1 ; + temp_hitmask[2] = 1'b0 ; + end + if (cts == 1'b0 & (((hitmask[0]) == 1'b1 & hit1in == 1'b0) | ((hitmask[1]) == 1'b1 & hit2in == 1'b0) | ((hitmask[2]) == 1'b1 & hit3in == 1'b0))) + begin + temp_passCTSout = 1'b1 ; + temp_cts = 1'b1 ; + end + + end + 19 : + begin + if (passCTSin == 1'b0) + begin + next_state = 19 ; + temp_busy = 1'b1 ; + end + else + begin + next_state = 9 ; + temp_busy = 1'b1 ; + end + temp_statepeek = 5'b10101 ; + // + if (passCTSin == 1'b1) + begin + temp_passCTSout = 1'b0 ; + end + + end + endcase + end +endmodule + + + + + + // A debugging circuit that allows a single cycle pulse to be + // generated by through the ports package + module onlyonecycle (trigger, output_xhdl0, globalreset, clk); + + input trigger; + output output_xhdl0; + reg output_xhdl0; + input globalreset; + input clk; + + reg[1:0] state; + reg[1:0] next_state; + reg[0:0] count; + reg[0:0] temp_count; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + count <= 0 ; + + end + else + begin + state <= next_state ; + count <= temp_count; + end + end + + always @(state or trigger or count) + begin + case (state) + 0 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_count = 1 - 1 ; + end + 1 : + begin + output_xhdl0 = 1'b1 ; + if (count == 0) + begin + next_state = 2 ; + end + else + + begin + + next_state = 1 ; + end + temp_count = count - 1 ; + end + 2 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + + end + end + endcase + end + endmodule + + + + + + + + + + + module vblockramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, addr, addrvalid, data, datavalid, globalreset, clk); + + + output want_addr; + reg want_addr; + input addr_ready; + input[10 - 1:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[32 - 1:0] datain; + + input[10 - 1:0] addr; + input addrvalid; + output[32 - 1:0] data; + reg[32 - 1:0] data; + output datavalid; + reg datavalid; + input globalreset; + input clk; + + reg[2:0] state; + reg[2:0] next_state; + reg[10 - 1:0] waddr; + wire[10 - 1:0] saddr; + wire[32 - 1:0] dataout; + reg we; +reg [32 - 1:0]temp_data; +reg [10 - 1:0]temp_waddr ; +reg temp_datavalid; + + assign saddr = (state != 0) ? waddr : addr ; + + spramblock ramblock(we, saddr, datain, dataout, clk); + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + waddr <= 0; + data <= 0; + datavalid <= 1'b0 ; + end + else + + begin + state <= next_state ; + data <= temp_data; + waddr <= temp_waddr ; + datavalid <= temp_datavalid; + end + end + + always @(state or addr_ready or data_ready or addrvalid or datavalid) + + begin + case (state) + 0 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + + else if (addrvalid == 1'b1 & datavalid == 1'b0) + begin + next_state = 5 ; + end + else + begin + next_state = 0 ; + end + if (addr_ready == 1'b1) + begin + temp_waddr = addrin ; + end + if (addrvalid == 1'b0) + begin + temp_datavalid = 1'b0 ; + + end + + end + 5 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + next_state = 0 ; + + temp_data = dataout ; + + temp_datavalid = 1'b1 ; + + end + 1 : + begin + we = 1'b0 ; + want_addr = 1'b0 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + + end + end + 2 : + begin + want_addr = 1'b1 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + end + else if (data_ready == 1'b1) + begin + we = 1'b1 ; + + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + if (data_ready == 1'b1) + begin + temp_waddr = waddr + 1 ; + end + + end + 3 : + begin + we = 1'b0 ; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (data_ready == 1'b1) + begin + next_state = 3 ; + + end + else + begin + next_state = 2 ; + end + end + 4 : + begin + we = 1'b0 ; + want_data = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + + end + else + begin + next_state = 0 ; + end + end + endcase + end + endmodule + //----------------------------------------------------- + // Single Ported Ram Modual w/Registered Output -- + // - Synpify should infer ram from the coding style -- + // - Depth is the number of bits of address -- + // the true depth is 2**depth -- + + //----------------------------------------------------- + + //modifying this to black box ram implementation + + + module spramblock (we, addr, datain, dataout, clk); + + input we; + input[10 - 1:0] addr; + input[32 - 1:0] datain; + output[32 - 1:0] dataout; + wire[32 - 1:0] dataout; + input clk; + + + + +single_port_ram new_ram( + .clk (clk), + .we(we), + .data(datain), + .out(dataout), + .addr(addr) + ); + + + endmodule + + + + + + + + + module sramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, addr, addrvalid, data, datavalid, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk, statepeek); + + output want_addr; + reg want_addr; + input addr_ready; + input[17:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[63:0] datain; + input[17:0] addr; + input addrvalid; + + output[63:0] data; + reg[63:0] data; + reg[63:0] temp_data; + output datavalid; + reg datavalid; + reg temp_datavalid; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + reg[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + reg[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + reg[2:0] temp_statepeek; + + reg[2:0] state; + reg[2:0] next_state; + reg[17:0] waddress; + reg[17:0] temp_waddress; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + + begin + state <= 0 ; + waddress <= 0; + data <= 0; + datavalid <= 1'b0 ; + end + else + begin + state <= next_state ; + statepeek <= temp_statepeek; + data <=temp_data; + datavalid <=temp_datavalid; + waddress <= temp_waddress; + end + end + + always @(state or addr_ready or data_ready or waddress or datain or addrvalid or + datavalid or addr) + begin + case (state) + 0 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (addrvalid == 1'b1 & datavalid == 1'b0) + begin + next_state = 5 ; + + tm3_sram_addr = {1'b0, addr} ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_oe = 2'b01 ; + end + + else + begin + next_state = 0 ; + end + + temp_statepeek = 3'b001 ; + if (addr_ready == 1'b1) + begin + temp_waddress = addrin ; + end + if (addrvalid == 1'b0) + begin + temp_datavalid = 1'b0 ; + end + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b0 ; + want_data = 1'b1 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 2 ; + end + + temp_statepeek = 3'b010 ; + end + 2 : + begin + tm3_sram_oe = 2'b11 ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + tm3_sram_addr = {1'b0, waddress} ; + tm3_sram_data_xhdl0 = datain ; + if (addr_ready == 1'b1) + begin + next_state = 4 ; + end + else if (data_ready == 1'b1) + begin + + tm3_sram_we = 8'b00000000 ; + tm3_sram_adsp = 1'b0 ; + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + temp_statepeek = 3'b011 ; + if (data_ready == 1'b1) + + begin + temp_waddress = waddress + 1 ; + end + + end + 3 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + if (data_ready == 1'b1) + + begin + next_state = 3 ; + end + else + begin + next_state = 2 ; + end + temp_statepeek = 3'b100 ; + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_data = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b1) + + begin + next_state = 4 ; + end + else + begin + next_state = 0 ; + end + temp_statepeek = 3'b101 ; + end + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b1 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = 0; + want_addr = 1'b1 ; + want_data = 1'b0 ; + next_state = 0 ; + temp_statepeek = 3'b110 ; + temp_data = tm3_sram_data_in ; + temp_datavalid = 1'b1 ; + + end + + + endcase + end + endmodule + + + + + + + + + + + + + +module resultinterface (t1b, t2b, t3b, u1b, u2b, u3b, v1b, v2b, v3b, id1b, id2b, id3b, hit1b, hit2b, hit3b, resultID, newdata, resultready, resultdata, globalreset, clk); + + output[31:0] t1b; + reg[31:0] t1b; + output[31:0] t2b; + reg[31:0] t2b; + output[31:0] t3b; + reg[31:0] t3b; + output[15:0] u1b; + reg[15:0] u1b; + output[15:0] u2b; + reg[15:0] u2b; + + output[15:0] u3b; + reg[15:0] u3b; + output[15:0] v1b; + reg[15:0] v1b; + output[15:0] v2b; + reg[15:0] v2b; + output[15:0] v3b; + reg[15:0] v3b; + output[15:0] id1b; + reg[15:0] id1b; + output[15:0] id2b; + reg[15:0] id2b; + + output[15:0] id3b; + reg[15:0] id3b; + output hit1b; + reg hit1b; + output hit2b; + reg hit2b; + output hit3b; + reg hit3b; + output[1:0] resultID; + reg[1:0] resultID; + output newdata; + reg newdata; + + reg[31:0] temp_t1b; + reg[31:0] temp_t2b; + reg[31:0] temp_t3b; + reg[15:0] temp_u1b; + reg[15:0] temp_u2b; + reg[15:0] temp_u3b; + reg[15:0] temp_v1b; + reg[15:0] temp_v2b; + reg[15:0] temp_v3b; + reg[15:0] temp_id1b; + reg[15:0] temp_id2b; + reg[15:0] temp_id3b; + reg temp_hit1b; + reg temp_hit2b; + reg temp_hit3b; + reg[1:0] temp_resultID; + reg temp_newdata; + + input resultready; + input[31:0] resultdata; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + t1b <= 0; + t2b <= 0; + t3b <= 0; + u1b <= 0; + u2b <= 0; + u3b <= 0; + v1b <= 0; + + v2b <= 0; + v3b <= 0; + id1b <= 0; + id2b <= 0; + id3b <= 0; + hit1b <= 1'b0 ; + hit2b <= 1'b0 ; + hit3b <= 1'b0 ; + resultID <= 0; + newdata <= 1'b0 ; + end + else + begin + state <= next_state ; + + t1b <= temp_t1b; + newdata <= temp_newdata; + u1b <= temp_u1b; + v1b <= temp_v1b; + id1b <= temp_id1b; + hit1b <= temp_hit1b; + resultID <= temp_resultID; + t2b <= temp_t2b; + u2b <= temp_u2b; + id2b <= temp_id2b; + t3b <= temp_t3b; + u3b <= temp_u3b; + v3b <= temp_v3b; + id3b <= temp_id3b; + hit3b <= temp_hit3b; + v2b <= temp_v2b; + hit2b <= temp_hit2b; + end + end + + always @(state or resultready) + begin + case (state) + 0 : + begin + + if (resultready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_newdata = 1'b0 ; + if (resultready == 1'b1) + begin + temp_t1b = resultdata ; + end + + end + 1 : + begin + next_state = 2 ; + temp_newdata = 1'b0 ; + temp_u1b = resultdata[31:16] ; + temp_v1b = resultdata[15:0] ; + end + 2 : + begin + next_state = 3 ; + temp_newdata = 1'b0 ; + temp_id1b = resultdata[15:0] ; + temp_hit1b = resultdata[16] ; + temp_resultID = resultdata[18:17] ; + end + 3 : + begin + + next_state = 4 ; + temp_newdata = 1'b0 ; + temp_t2b = resultdata ; + end + 4 : + begin + next_state = 5 ; + temp_newdata = 1'b0 ; + temp_u2b = resultdata[31:16] ; + temp_v2b = resultdata[15:0] ; + end + 5 : + begin + next_state = 6 ; + temp_newdata = 1'b0 ; + temp_id2b = resultdata[15:0] ; + temp_hit2b = resultdata[16] ; + end + 6 : + begin + + next_state = 7 ; + temp_newdata = 1'b0 ; + temp_t3b = resultdata ; + end + 7 : + begin + next_state = 8 ; + temp_newdata = 1'b0 ; + temp_u3b = resultdata[31:16] ; + temp_v3b = resultdata[15:0] ; + end + 8 : + begin + next_state = 0 ; + temp_id3b = resultdata[15:0] ; + temp_hit3b = resultdata[16] ; + temp_newdata = 1'b1 ; + end + endcase + end + + endmodule + module rayinterface (raygroup, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, globalreset, clk); + + input[1:0] raygroup; + input raygroupwe; + input[1:0] raygroupid; + input enablenear; + input[31:0] rgData; + input[3:0] rgAddr; + input[2:0] rgWE; + + input rgAddrValid; + output rgDone; + reg rgDone; + output[31:0] raydata; + reg[31:0] raydata; + output[3:0] rayaddr; + reg[3:0] rayaddr; + output[2:0] raywe; + reg[2:0] raywe; + input globalreset; + input clk; + + + reg[31:0] rgDatal; + reg[3:0] rgAddrl; + reg[2:0] rgWEl; + reg rgAddrValidl; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + raydata <= 0; + rayaddr <= 0; + raywe <= 0; + + rgDone <= 1'b0 ; + rgDatal <= 0; + rgAddrl <= 0; + rgWEl <= 0; + rgAddrValidl <= 1'b0 ; + end + else + begin + rgDatal <= rgData ; // Latch interchip signals + rgAddrl <= rgAddr ; // To Meet Timing + rgWEl <= rgWE ; + + rgAddrValidl <= rgAddrValid ; + + if (raygroupwe == 1'b1) + begin + raydata[0] <= enablenear ; + raydata[31:1] <= 0; + raywe <= 3'b111 ; + rayaddr <= {raygroupid, raygroup} ; + if (rgAddrValidl == 1'b0) + rgDone <= 1'b0 ; + end + else if (rgAddrValidl == 1'b1 & rgDone == 1'b0) + begin + raydata <= rgDatal ; + raywe <= rgWEl ; + rayaddr <= rgAddrl ; + rgDone <= 1'b1 ; + end + else + begin + raywe <= 0; + end + end + end + endmodule + + + + +module sortedstack (keyin, datain, write, reset, peekdata, globalreset, clk); + + input[32 - 1:0] keyin; + input[13 - 1:0] datain; + input write; + input reset; + output[13 * 8 - 1:0] peekdata; + + wire[13 * 8 - 1:0] peekdata; + wire big_reset; + input globalreset; + input clk; + + reg[32 - 1:0] key0; + reg[32 - 1:0] key1; + reg[32 - 1:0] key2; + reg[32 - 1:0] key3; + reg[32 - 1:0] key4; + reg[32 - 1:0] key5; + reg[32 - 1:0] key6; + reg[32 - 1:0] key7; + reg[13 - 1:0] data0; + reg[13 - 1:0] data1; + reg[13 - 1:0] data2; + reg[13 - 1:0] data3; + reg[13 - 1:0] data4; + reg[13 - 1:0] data5; + reg[13 - 1:0] data6; + reg[13 - 1:0] data7; + reg full0; + reg full1; + reg full2; + reg full3; + reg full4; + reg full5; + reg full6; + reg full7; + reg[2:0] location; + + assign peekdata[(0 + 1) * (13) - 1:0 * (13)] = ((full0) == 1'b1) ? data0 : 0; + assign peekdata[(1 + 1) * (13) - 1:1 * (13)] = ((full1) == 1'b1) ? data1 : 0; + assign peekdata[(2 + 1) * (13) - 1:2 * (13)] = ((full2) == 1'b1) ? data2 : 0; + assign peekdata[(3 + 1) * (13) - 1:3 * (13)] = ((full3) == 1'b1) ? data3 : 0; + assign peekdata[(4 + 1) * (13) - 1:4 * (13)] = ((full4) == 1'b1) ? data4 : 0; + assign peekdata[(5 + 1) * (13) - 1:5 * (13)] = ((full5) == 1'b1) ? data5 : 0; + assign peekdata[(6 + 1) * (13) - 1:6 * (13)] = ((full6) == 1'b1) ? data6 : 0; + assign peekdata[(7 + 1) * (13) - 1:7 * (13)] = ((full7) == 1'b1) ? data7 : 0; + + // Select the proper insertion point + always @(keyin or key0 or key1 or key2 or key3 or key4 or key5 or key6 or key7 or full0 or full1 or full2 or full3 or full4 or full5 or full6 or full7) + begin + +/* PAJ -- changed for loops */ + if ((keyin < key0) | ((full0) == 1'b0)) + begin + location = 0 ; + end + else if ((keyin < key1) | ((full1) == 1'b0)) + begin + location = 1 ; + end + else if ((keyin < key2) | ((full2) == 1'b0)) + begin + location = 2 ; + end + else if ((keyin < key3) | ((full3) == 1'b0)) + begin + location = 3 ; + end + else if ((keyin < key4) | ((full4) == 1'b0)) + begin + location = 4 ; + end + else if ((keyin < key5) | ((full5) == 1'b0)) + begin + location = 5 ; + end + else if ((keyin < key6) | ((full6) == 1'b0)) + begin + location = 6 ; + end + else + begin + location = 7; + end + end + + assign big_reset = globalreset | reset; + always @(posedge clk) + begin + if (big_reset == 1'b1) + begin + full0 <= 1'b0 ; + key0 <= 0; + data0 <= 0; + full1 <= 1'b0 ; + key1 <= 0; + data1 <= 0; + full2 <= 1'b0 ; + key2 <= 0; + data2 <= 0; + full3 <= 1'b0 ; + key3 <= 0; + data3 <= 0; + full4 <= 1'b0 ; + key4 <= 0; + data4 <= 0; + full5 <= 1'b0 ; + key5 <= 0; + data5 <= 0; + full6 <= 1'b0 ; + key6 <= 0; + data6 <= 0; + full7 <= 1'b0 ; + key7 <= 0; + data7 <= 0; + end + else + begin + if (write == 1'b1) + begin + if (location == 0) + begin + key0 <= keyin; + data0 <= datain; + full0 <= 1'b1; + key1 <= key0; + data1 <= data0; + full1 <= full0; + key2 <= key1; + data2 <= data1; + full2 <= full1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 1) + begin + key1 <= keyin; + data1 <= datain; + full1 <= 1'b1; + key2 <= key1; + data2 <= data1; + full2 <= full1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 2) + begin + key2 <= keyin; + data2 <= datain; + full2 <= 1'b1; + key3 <= key2; + data3 <= data2; + full3 <= full2; + key4 <= key3; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 2) + begin + key3 <= keyin; + data3 <= datain; + full3 <= 1'b1; + data4 <= data3; + full4 <= full3; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 4) + begin + key4 <= keyin; + data4 <= datain; + full4 <= 1'b1; + key5 <= key4; + data5 <= data4; + full5 <= full4; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 5) + begin + key5 <= keyin; + data5 <= datain; + full5 <= 1'b1; + key6 <= key5; + data6 <= data5; + full6 <= full5; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 6) + begin + key6 <= keyin; + data6 <= datain; + full6 <= 1'b1; + key7 <= key6; + data7 <= data6; + full7 <= full6; + end + else if (location == 7) + begin + key7 <= keyin; + data7 <= datain; + full7 <= 1'b1; + end + end + end +end +endmodule + + + + +module listhandler (dataarrayin, commit, hitmask, ack, boundnodeID, level, empty, dataready, reset, globalreset, clk, peekoffset0, peekoffset1, peekoffset2, peekhit, peekstate); + + input[8 * 13 - 1:0] dataarrayin; + input commit; + input[2:0] hitmask; + input ack; + output[9:0] boundnodeID; + wire[9:0] boundnodeID; + output[1:0] level; + wire[1:0] level; + + output empty; + wire empty; + output dataready; + wire dataready; + input reset; + input globalreset; + input clk; + output[2:0] peekoffset0; + wire[2:0] peekoffset0; + output[2:0] peekoffset1; + wire[2:0] peekoffset1; + output[2:0] peekoffset2; + + wire[2:0] peekoffset2; + output peekhit; + wire peekhit; + output[1:0] peekstate; + reg[1:0] peekstate; + reg[1:0] temp_peekstate; + + reg[1:0] next_state; + reg[1:0] state; + reg[1:0] readlevel; + + reg[1:0] writelevel; + reg[2:0] offset0; + reg[2:0] offset1; + reg[2:0] offset2; + reg[4:0] address; + reg we; + reg[12:0] datain; + wire[12:0] dataout; + reg[2:0] lvempty; + reg busy; + reg temp_busy; + reg[2:0] temp_lvempty; + reg[1:0] temp_readlevel; + reg[1:0] temp_writelevel; + reg[2:0] temp_offset0; + reg[2:0] temp_offset1; + reg[2:0] temp_offset2; + + // Debug Stuff + + assign peekoffset0 = offset0 ; + assign peekoffset1 = offset1 ; + assign peekoffset2 = offset2 ; + assign peekhit = ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) ? 1'b1 : 1'b0 ; + + // Real Code + + spram ram(we, dataout, datain, clk); + + assign level = readlevel ; + assign boundnodeID = dataout[9:0] ; + + assign empty = (lvempty == 3'b111 & busy == 1'b0) ? 1'b1 : 1'b0 ; + assign dataready = ((((dataout[10]) == 1'b1 & (hitmask[0]) == 1'b1) | ((dataout[11]) == 1'b1 & (hitmask[1]) == 1'b1) | ((dataout[12]) == 1'b1 & (hitmask[2]) == 1'b1)) & (empty == 1'b0) & (busy == 1'b0)) ? 1'b1 : 1'b0 ; + + always @(offset0 or offset1 or offset2 or address) + begin + address[4:3] = readlevel ; + + if (address[4:3] == 2'b00) + begin + address[2:0] = offset0 ; + end + else if (address[4:3] == 2'b01) + begin + + address[2:0] = offset1 ; + end + else if (address[4:3] == 2'b10) + begin + address[2:0] = offset2 ; + end + else + begin + address[2:0] = 0; + end + end + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + lvempty <= 1; + busy <= 1'b0 ; + readlevel <= 2'b00 ; + writelevel <= 2'b00 ; + offset0 <= 3'b000 ; + offset1 <= 3'b000 ; + offset2 <= 3'b000 ; + + end + else + begin + state <= next_state ; + peekstate <= temp_peekstate ; + busy <= temp_busy; + lvempty <= temp_lvempty; + readlevel <= temp_readlevel; + writelevel <= temp_writelevel; + offset0 <= temp_offset0; + offset1 <= temp_offset1; + offset2 <= temp_offset2; + + end + end + + always @(state or commit or ack or address or dataarrayin or reset or dataready or + empty) + begin + + case (state) + 2'b00 : + begin + we = 1'b0 ; + datain = 0; + if (reset == 1'b1) + begin + next_state = 0 ; + end + else if (commit == 1'b1) + begin + next_state = 1 ; + end + else if ((ack == 1'b1) | (dataready == 1'b0 & empty == 1'b0)) + + begin + next_state = 2 ; + end + else + begin + next_state = 0 ; + end + temp_peekstate = 2'b01 ; + + if (reset == 1'b1) + begin + temp_busy = 1'b0 ; + temp_lvempty = 1; + temp_readlevel = 2'b00 ; + + temp_writelevel = 2'b00 ; + temp_offset0 = 3'b000 ; + temp_offset1 = 3'b000 ; + temp_offset2 = 3'b000 ; + end + else if (commit == 1'b1) + begin + temp_busy = 1'b1 ; + if (writelevel == 2'b00) + begin + temp_offset0 = 3'b000 ; + end + + else if (writelevel == 2'b01) + begin + temp_offset1 = 3'b000 ; + end + else if (writelevel == 2'b10) + begin + temp_offset2 = 3'b000 ; + end + temp_readlevel = writelevel ; + end + + else if (ack == 1'b1) + begin + temp_writelevel = readlevel + 1 ; + temp_busy = 1'b1 ; // This will ensure that align skips one + end + + end + 2'b01 : + begin +/* PAJ -- Unrolled loop */ + if (address[2:0] == 0) + begin + datain = dataarrayin[(1) * 13 - 1:0 * 13] ; + end + else if ( address[2:0] == 1) + begin + datain = dataarrayin[(2) * 13 - 1:1 * 13] ; + end + else if ( address[2:0] ==2) + begin + datain = dataarrayin[(3) * 13 - 1:2 * 13] ; + end + else if ( address[2:0] ==3) + begin + datain = dataarrayin[(4) * 13 - 1:3 * 13] ; + end + else if ( address[2:0] ==4) + begin + datain = dataarrayin[(5) * 13 - 1:4 * 13] ; + end + else if ( address[2:0] ==5) + begin + datain = dataarrayin[(6) * 13 - 1:5 * 13] ; + end + else if ( address[2:0] ==6) + begin + datain = dataarrayin[(7) * 13 - 1:6 * 13] ; + end + else if ( address[2:0] ==7) + begin + datain = dataarrayin[(8) * 13 - 1:7 * 13] ; + end + + + we = 1'b1 ; + if (address[2:0] == 3'b111) + begin + next_state = 2 ; + + end + else + begin + next_state = 1 ; + end + temp_peekstate = 2'b10 ; + + if (readlevel == 2'b00) + begin + temp_offset0 = offset0 + 1 ; + end + + else if (readlevel == 2'b01) + begin + temp_offset1 = offset1 + 1 ; + end + else if (readlevel == 2'b10) + begin + temp_offset2 = offset2 + 1 ; + end + if (address[2:0] == 3'b111) + begin + temp_busy = 1'b0 ; + end + + if ((datain[10]) == 1'b1 | (datain[11]) == 1'b1 | (datain[12]) == 1'b1) + begin + if (readlevel == 2'b00) + begin + temp_lvempty[0] = 1'b0 ; + end + else if (readlevel == 2'b01) + begin + temp_lvempty[1] = 1'b0 ; + end + else if (readlevel == 2'b10) + begin + + temp_lvempty[2] = 1'b0 ; + end + end + + end + 2'b10 : + begin + if (empty == 1'b0 & dataready == 1'b0) + begin + next_state = 2 ; + end + else + next_state = 0 ; + + temp_peekstate = 2'b11 ; + temp_busy = 1'b0 ; + if (empty == 1'b0 & dataready == 1'b0) + begin + if (readlevel == 2'b00) + begin + if (offset0 == 3'b111) + begin + temp_lvempty[0] = 1'b1 ; + end + else + begin + temp_offset0 = offset0 + 1 ; + end + end + else if (readlevel == 2'b01) + begin + if (offset1 == 3'b111) + begin + temp_lvempty[1] = 1'b1 ; + temp_readlevel = 2'b00 ; + end + else + begin + temp_offset1 = offset1 + 1 ; + end + end + else if (readlevel == 2'b10) + begin + if (offset2 == 3'b111) + begin + temp_lvempty[2] = 1'b1 ; + if ((lvempty[1]) == 1'b1) + begin + temp_readlevel = 2'b00 ; + end + else + begin + temp_readlevel = 2'b01 ; + end + end + else + begin + temp_offset2 = offset2 + 1 ; + end + end + end + end + endcase +end +endmodule + + + + module spram (we, dataout, datain, clk); + + input we; + output[13 - 1:0] dataout; + wire[13 - 1:0] dataout; + input[13 - 1:0] datain; + input clk; + reg[13 - 1:0] temp_reg; + + reg[13 - 1:0] mem1; + reg[13 - 1:0] mem2; + + assign dataout = mem2 ; + + always @(posedge clk) + begin + temp_reg <= 0; + if (we == 1'b1) + begin + mem1 <= datain + temp_reg; + mem2 <= mem1; + end + end + endmodule + module resultcounter (resultID, newresult, done, reset, globalreset, clk); + + input[1:0] resultID; + input newresult; + output[1:0] done; + wire[1:0] done; + input reset; + input globalreset; + input clk; + + wire big_reset; + + reg[3:0] count; + reg[1:0] curr; + + assign done = (count == 0) ? curr : 2'b00 ; + assign big_reset = globalreset | reset; + + always @(posedge clk) + begin + if (big_reset == 1'b1) + begin + count <= 4'b1000 ; + curr <= 0; + end + else + begin + if ((resultID != 0) & (newresult == 1'b1) & (count != 0)) + begin + count <= count - 1 ; + curr <= resultID ; + end + end + end + endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v b/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v new file mode 100755 index 000000000..327e10fe2 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v @@ -0,0 +1,317 @@ + + +`define MEMORY_CONTROLLER_TAGS 1 +`define MEMORY_CONTROLLER_TAG_SIZE 1 +`define TAG__str 1'b0 +`define MEMORY_CONTROLLER_ADDR_SIZE 32 +`define MEMORY_CONTROLLER_DATA_SIZE 32 + + +module memory_controller +( + clk, + memory_controller_address, + memory_controller_write_enable, + memory_controller_in, + memory_controller_out +); +input clk; +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +input memory_controller_write_enable; +input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + + +reg [4:0] str_address; +reg str_write_enable; +reg [7:0] str_in; +wire [7:0] str_out; + +single_port_ram _str ( + .clk( clk ), + .addr( str_address ), + .we( str_write_enable ), + .data( str_in ), + .out( str_out ) +); + + +wire tag; + +//must use all wires inside module..... +assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in; +reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag; +always @(posedge clk) + prevTag <= tag; +always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in) +begin + +case(tag) + + 1'b0: + begin + str_address = memory_controller_address[5-1+0:0]; + str_write_enable = memory_controller_write_enable; + str_in[8-1:0] = memory_controller_in[8-1:0]; + end +endcase + +case(prevTag) + + 1'b0: + memory_controller_out = str_out; +endcase +end + +endmodule + + +module memset + ( + clk, + reset, + start, + finish, + return_val, + m, + c, + n, + memory_controller_write_enable, + memory_controller_address, + memory_controller_in, + memory_controller_out + ); + +output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val; +input clk; +input reset; +input start; + +output finish; +reg finish; + +input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m; +input [31:0] c; +input [31:0] n; + +output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address; + +output memory_controller_write_enable; +reg memory_controller_write_enable; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; +reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in; + +output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out; + +reg [3:0] cur_state; + +/* +parameter Wait = 4'd0; +parameter entry = 4'd1; +parameter entry_1 = 4'd2; +parameter entry_2 = 4'd3; +parameter bb = 4'd4; +parameter bb_1 = 4'd5; +parameter bb1 = 4'd6; +parameter bb1_1 = 4'd7; +parameter bb_nph = 4'd8; +parameter bb2 = 4'd9; +parameter bb2_1 = 4'd10; +parameter bb2_2 = 4'd11; +parameter bb2_3 = 4'd12; +parameter bb2_4 = 4'd13; +parameter bb4 = 4'd14; +*/ + +memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out); + + +reg [31:0] indvar; +reg var1; +reg [31:0] tmp; +reg [31:0] tmp8; +reg var2; +reg [31:0] var0; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep; +reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07; +reg [31:0] indvar_next; +reg exitcond; + +always @(posedge clk) +if (reset) + cur_state <= 4'b0000; +else +case(cur_state) + 4'b0000: + begin + finish <= 1'b0; + if (start == 1'b1) + cur_state <= 4'b0001; + else + cur_state <= 4'b0000; + end + 4'b0001: + begin + + + + var0 <= n & 32'b00000000000000000000000000000011; + + cur_state <= 4'b0010; + end + 4'b0010: + begin + + var1 <= 1'b0; + var0 <= 32'b00000000000000000000000000000000; + + cur_state <= 4'b0011; + end + 4'b0011: + begin + + + if (|var1) begin + cur_state <= 4'b0110; + end + else + begin + + cur_state <= 4'b0100; + end + end + 4'b0100: + begin + + cur_state <= 4'b0101; + end + 4'b0101: + begin + cur_state <= 4'b0110; + end + 4'b0110: + begin + + var2 <= | (n [31:4]); + + cur_state <= 4'b0111; + end + 4'b0111: + begin + + if (|var2) + begin + cur_state <= 4'b1110; + end + else + begin + cur_state <= 4'b1000; + end + end + 4'b1000: + begin + + tmp <= n ; + + indvar <= 32'b00000000000000000000000000000000; + cur_state <= 4'b1001; + end + 4'b1001: + begin + + cur_state <= 4'b1010; + end + 4'b1010: + begin + tmp8 <= indvar; + indvar_next <= indvar; + cur_state <= 4'b1011; + end + 4'b1011: + begin + + scevgep <= (m & tmp8); + + exitcond <= (indvar_next == tmp); + + cur_state <= 4'b1100; + end + 4'b1100: + begin + + s_07 <= scevgep; + + cur_state <= 4'b1101; + end + 4'b1101: + + begin + + + if (exitcond) + begin + cur_state <= 4'b1110; + end + else + begin + indvar <= indvar_next; + cur_state <= 4'b1001; + end + end + + + 4'b1110: + begin + + return_val <= m; + finish <= 1'b1; + cur_state <= 4'b0000; + end +endcase + +always @(cur_state) +begin + + case(cur_state) + 4'b1101: + begin + memory_controller_address = s_07; + memory_controller_write_enable = 1'b1; + memory_controller_in = c; + end + endcase +end + +endmodule + +//--------------------------------------- +// A single-port 32x8bit RAM +// This module is tuned for VTR's benchmarks +//--------------------------------------- +module single_port_ram ( + input clk, + input we, + input [4:0] addr, + input [7:0] data, + output [7:0] out ); + + reg [7:0] ram[31:0]; + reg [7:0] internal; + + assign out = internal; + + always @(posedge clk) begin + if(wen) begin + ram[addr] <= data; + end + + if(ren) begin + internal <= ram[addr]; + end + end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v b/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v new file mode 100755 index 000000000..b4033369c --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v @@ -0,0 +1,56 @@ + module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, clk, reset); + input[31:0] Xinport; + input[31:0] Yinport; + input[31:0] Uinport; + input[31:0] Aport; + input[31:0] DXport; + input clk; + input reset; + output[31:0] Xoutport; + output[31:0] Youtport; + output[31:0] Uoutport; + reg[31:0] Xoutport; + reg[31:0] Youtport; + reg[31:0] Uoutport; + + reg[31:0] x_var; + reg[31:0] y_var; + reg[31:0] u_var; + wire[31:0] temp; + reg looping; + +assign temp = u_var * DXport; + always @(posedge clk) + begin + if (reset == 1'b1) + begin + looping <= 1'b0; + x_var <= 0; + y_var <= 0; + u_var <= 0; + end + else + if (looping == 1'b0) + begin + x_var <= Xinport; + y_var <= Yinport; + u_var <= Uinport; + looping <= 1'b1; + end + else if (x_var < Aport) + begin + u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var); + y_var <= y_var + temp;//(u_var * DXport); + x_var <= x_var + DXport; + looping <= looping; + end + else + begin + Xoutport <= x_var ; + Youtport <= y_var ; + Uoutport <= u_var ; + looping <= 1'b0; + end + end + endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v b/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v new file mode 100755 index 000000000..f88fab260 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v @@ -0,0 +1,63 @@ + +/*-------------------------------------------------------------------------- +-------------------------------------------------------------------------- +-- File Name : diffeq.v +-- Author(s) : P. Sridhar +-- Affiliation : Laboratory for Digital Design Environments +-- Department of Electrical & Computer Engineering +-- University of Cincinnati +-- Date Created : June 1991. +-- Introduction : Behavioral description of a differential equation +-- solver written in a synthesizable subset of VHDL. +-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ. +-- Obtained from the Highlevel Synthesis Workshop +-- Repository. +-- +-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati. +-- Date Modified : Sept, 91. +-- +-- Disclaimer : This comes with absolutely no guarantees of any +-- kind (just stating the obvious ...) +-- +-- Acknowledgement : The Distributed Synthesis Systems research at +-- the Laboratory for Digital Design Environments, +-- University of Cincinnati, is sponsored in part +-- by the Defense Advanced Research Projects Agency +-- under order number 7056 monitored by the Federal +-- Bureau of Investigation under contract number +-- J-FBI-89-094. +-- +-------------------------------------------------------------------------- +-------------------------------------------------------------------------*/ +module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset); + +input clk; +input reset; +input [31:0]aport; +input [31:0]dxport; +output [31:0]xport; +output [31:0]yport; +output [31:0]uport; +reg [31:0]xport; +reg [31:0]yport; +reg [31:0]uport; +wire [31:0]temp; + +assign temp = uport * dxport; +always @(posedge clk ) +begin + if (reset == 1'b1) + begin + xport <= 0; + yport <= 0; + uport <= 0; + end +else + if (xport < aport) + begin + xport <= xport + dxport; + yport <= yport + temp;//(uport * dxport); + uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport)); + end +end +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v b/openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v new file mode 100644 index 000000000..70d0b1dcb --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/matmul_8x8_fp16.v @@ -0,0 +1,1662 @@ +//////////////////////////////////////////////// +// Matrix multiplication design +// Multiplies 8x8 matrix (A) with another 8x8 matrix (B) +// to produce an 8x8 matrix (C). +// Data precision is IEEE floating point 16-bit (half precision) +// The architecture is systolic in nature (output stationary). +// 4 4x4 matmuls composed to make a larger 8x8 matmul. +// There is state machine for control and an APB +// interface for programming/configuring. +// Matrices are stores in RAM blocks. +/////////////////////////////////////////////// + +`timescale 1ns/1ns + +`define DWIDTH 16 +`define AWIDTH 10 +`define MEM_SIZE 1024 +`define DESIGN_SIZE 8 +`define MAT_MUL_SIZE 4 +`define MASK_WIDTH 4 +`define LOG2_MAT_MUL_SIZE 2 +`define NUM_CYCLES_IN_MAC 3 +`define MEM_ACCESS_LATENCY 1 +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 +`define ADDR_STRIDE_WIDTH 16 +`define REG_STDN_TPU_ADDR 32'h4 +`define REG_MATRIX_A_ADDR 32'he +`define REG_MATRIX_B_ADDR 32'h12 +`define REG_MATRIX_C_ADDR 32'h16 +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 + +module matrix_multiplication( + input clk, + input clk_mem, + input resetn, + input pe_resetn, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + input [7:0] bram_select, + input [`AWIDTH-1:0] bram_addr_ext, + output reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_ext, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_ext, + input [`MAT_MUL_SIZE-1:0] bram_we_ext +); + + + wire PCLK; + assign PCLK = clk; + reg start_reg; + reg clear_done_reg; + //Dummy register to sync all other invalid/unimplemented addresses + reg [`REG_DATAWIDTH-1:0] reg_dummy; + + reg [`AWIDTH-1:0] bram_addr_a_0_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_0_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_0_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_0_0_ext; + + reg [`AWIDTH-1:0] bram_addr_a_1_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_1_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_1_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_a_1_0_ext; + + reg [`AWIDTH-1:0] bram_addr_b_0_0_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_0_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_0_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_0_0_ext; + + reg [`AWIDTH-1:0] bram_addr_b_0_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_b_0_1_ext; + + reg [`AWIDTH-1:0] bram_addr_c_0_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_0_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_0_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_0_1_ext; + + reg [`AWIDTH-1:0] bram_addr_c_1_1_ext; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_1_1_ext; + reg [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_1_1_ext; + reg [`MASK_WIDTH-1:0] bram_we_c_1_1_ext; + + wire [`AWIDTH-1:0] bram_addr_a_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_0_0; + wire [`MASK_WIDTH-1:0] bram_we_a_0_0; + wire bram_en_a_0_0; + + wire [`AWIDTH-1:0] bram_addr_a_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_a_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_a_1_0; + wire [`MASK_WIDTH-1:0] bram_we_a_1_0; + wire bram_en_a_1_0; + + wire [`AWIDTH-1:0] bram_addr_b_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_0; + wire [`MASK_WIDTH-1:0] bram_we_b_0_0; + wire bram_en_b_0_0; + + wire [`AWIDTH-1:0] bram_addr_b_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_b_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_b_0_1; + wire [`MASK_WIDTH-1:0] bram_we_b_0_1; + wire bram_en_b_0_1; + + wire [`AWIDTH-1:0] bram_addr_c_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_0_1; + wire [`MASK_WIDTH-1:0] bram_we_c_0_1; + wire bram_en_c_0_1; + + wire [`AWIDTH-1:0] bram_addr_c_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_rdata_c_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] bram_wdata_c_1_1; + wire [`MASK_WIDTH-1:0] bram_we_c_1_1; + wire bram_en_c_1_1; + + always @* begin + case (bram_select) + + 0: begin + bram_addr_a_0_0_ext = bram_addr_ext; + bram_wdata_a_0_0_ext = bram_wdata_ext; + bram_we_a_0_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_a_0_0_ext; + end + + 1: begin + bram_addr_a_1_0_ext = bram_addr_ext; + bram_wdata_a_1_0_ext = bram_wdata_ext; + bram_we_a_1_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_a_1_0_ext; + end + + 2: begin + bram_addr_b_0_0_ext = bram_addr_ext; + bram_wdata_b_0_0_ext = bram_wdata_ext; + bram_we_b_0_0_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_b_0_0_ext; + end + + 3: begin + bram_addr_b_0_1_ext = bram_addr_ext; + bram_wdata_b_0_1_ext = bram_wdata_ext; + bram_we_b_0_1_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_b_0_1_ext; + end + + 4: begin + bram_addr_c_0_1_ext = bram_addr_ext; + bram_wdata_c_0_1_ext = bram_wdata_ext; + bram_we_c_0_1_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_c_0_1_ext; + end + + 5: begin + bram_addr_c_1_1_ext = bram_addr_ext; + bram_wdata_c_1_1_ext = bram_wdata_ext; + bram_we_c_1_1_ext = bram_we_ext; + bram_rdata_ext = bram_rdata_c_1_1_ext; + end + + default: begin + bram_rdata_ext = 0; + end + endcase + end + +///////////////////////////////////////////////// +// BRAMs to store matrix A +///////////////////////////////////////////////// + +// BRAM matrix A 0_0 (bank0) +ram matrix_A_0_0( + .addr0(bram_addr_a_0_0), + .d0(bram_wdata_a_0_0), + .we0(bram_we_a_0_0), + .q0(bram_rdata_a_0_0), + .addr1(bram_addr_a_0_0_ext), + .d1(bram_wdata_a_0_0_ext), + .we1(bram_we_a_0_0_ext), + .q1(bram_rdata_a_0_0_ext), + .clk(clk_mem)); + +// BRAM matrix A 1_0 (bank1) +ram matrix_A_1_0( + .addr0(bram_addr_a_1_0), + .d0(bram_wdata_a_1_0), + .we0(bram_we_a_1_0), + .q0(bram_rdata_a_1_0), + .addr1(bram_addr_a_1_0_ext), + .d1(bram_wdata_a_1_0_ext), + .we1(bram_we_a_1_0_ext), + .q1(bram_rdata_a_1_0_ext), + .clk(clk_mem)); + +///////////////////////////////////////////////// +// BRAMs to store matrix B +///////////////////////////////////////////////// + +// BRAM matrix B 0_0 (bank0) +ram matrix_B_0_0( + .addr0(bram_addr_b_0_0), + .d0(bram_wdata_b_0_0), + .we0(bram_we_b_0_0), + .q0(bram_rdata_b_0_0), + .addr1(bram_addr_b_0_0_ext), + .d1(bram_wdata_b_0_0_ext), + .we1(bram_we_b_0_0_ext), + .q1(bram_rdata_b_0_0_ext), + .clk(clk_mem)); + +// BRAM matrix B 0_1 (bank1) +ram matrix_B_0_1( + .addr0(bram_addr_b_0_1), + .d0(bram_wdata_b_0_1), + .we0(bram_we_b_0_1), + .q0(bram_rdata_b_0_1), + .addr1(bram_addr_b_0_1_ext), + .d1(bram_wdata_b_0_1_ext), + .we1(bram_we_b_0_1_ext), + .q1(bram_rdata_b_0_1_ext), + .clk(clk_mem)); + +///////////////////////////////////////////////// +// BRAMs to store matrix C +///////////////////////////////////////////////// + + +// BRAM matrix C 0_1 (bank0) +ram matrix_C_0_1( + .addr0(bram_addr_c_0_1), + .d0(bram_wdata_c_0_1), + .we0(bram_we_c_0_1), + .q0(bram_rdata_c_0_1), + .addr1(bram_addr_c_0_1_ext), + .d1(bram_wdata_c_0_1_ext), + .we1(bram_we_c_0_1_ext), + .q1(bram_rdata_c_0_1_ext), + .clk(clk_mem)); + +// BRAM matrix C 1_1 (bank1) +ram matrix_C_1_1( + .addr0(bram_addr_c_1_1), + .d0(bram_wdata_c_1_1), + .we0(bram_we_c_1_1), + .q0(bram_rdata_c_1_1), + .addr1(bram_addr_c_1_1_ext), + .d1(bram_wdata_c_1_1_ext), + .we1(bram_we_c_1_1_ext), + .q1(bram_rdata_c_1_1_ext), + .clk(clk_mem)); + +reg start_mat_mul; +wire done_mat_mul; + +reg [3:0] state; + +//////////////////////////////////////////////////////////////// +// Control logic +//////////////////////////////////////////////////////////////// +always @( posedge clk) begin + if (resetn == 1'b0) begin + state <= 4'b0000; + start_mat_mul <= 1'b0; + end + else begin + case (state) + + 4'b0000: begin + start_mat_mul <= 1'b0; + if (start_reg == 1'b1) begin + state <= 4'b0001; + end else begin + state <= 4'b0000; + end + end + + 4'b0001: begin + start_mat_mul <= 1'b1; + state <= 4'b1010; + end + + 4'b1010: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + state <= 4'b1000; + end + else begin + state <= 4'b1010; + end + end + + 4'b1000: begin + if (clear_done_reg == 1'b1) begin + state <= 4'b0000; + end + else begin + state <= 4'b1000; + end + end + endcase +end +end + +reg [1:0] state_apb; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +reg [`AWIDTH-1:0] address_mat_a; +reg [`AWIDTH-1:0] address_mat_b; +reg [`AWIDTH-1:0] address_mat_c; +reg [`MASK_WIDTH-1:0] validity_mask_a_rows; +reg [`MASK_WIDTH-1:0] validity_mask_a_cols; +reg [`MASK_WIDTH-1:0] validity_mask_b_rows; +reg [`MASK_WIDTH-1:0] validity_mask_b_cols; +reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + +//////////////////////////////////////////////////////////////// +// Configuration logic +//////////////////////////////////////////////////////////////// +always @(posedge PCLK) begin + if (PRESETn == 0) begin + state_apb <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + address_stride_a <= `MAT_MUL_SIZE; + address_stride_b <= `MAT_MUL_SIZE; + address_stride_c <= `MAT_MUL_SIZE; + end + + else begin + case (state_apb) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + state_apb <= `W_ENABLE; + end + else begin + state_apb <= `R_ENABLE; + end + end + PREADY <= 0; + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_STDN_TPU_ADDR : begin + start_reg <= PWDATA[0]; + clear_done_reg <= PWDATA[31]; + end + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + default : reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + state_apb <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_STDN_TPU_ADDR : PRDATA <= {done_mat_mul, 30'b0, start_mat_mul}; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + state_apb <= `IDLE; + end + default: begin + state_apb <= `IDLE; + end + endcase + end +end + +wire reset; +assign reset = ~resetn; +wire pe_reset; +assign pe_reset = ~pe_resetn; + +wire c_data_0_1_available; +assign bram_en_c_0_1 = 1'b1; +assign bram_we_c_0_1 = (c_data_0_1_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + +wire c_data_1_1_available; +assign bram_en_c_1_1 = 1'b1; +assign bram_we_c_1_1 = (c_data_1_1_available) ? {`MASK_WIDTH{1'b1}} : {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_a_0_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_a_0_0 = 1'b1; +assign bram_we_a_0_0 = {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_a_1_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_a_1_0 = 1'b1; +assign bram_we_a_1_0 = {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_b_0_0 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b_0_0 = 1'b1; +assign bram_we_b_0_0 = {`MASK_WIDTH{1'b0}}; + +assign bram_wdata_b_0_1 = {`MAT_MUL_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b_0_1 = 1'b1; +assign bram_we_b_0_1 = {`MASK_WIDTH{1'b0}}; + + +///////////////////////////////////////////////// +// The 8x8 matmul instantiation +///////////////////////////////////////////////// + +matmul_8x8_systolic u_matmul_8x8_systolic ( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + + .a_data_0_0(bram_rdata_a_0_0), + .b_data_0_0(bram_rdata_b_0_0), + .a_addr_0_0(bram_addr_a_0_0), + .b_addr_0_0(bram_addr_b_0_0), + + .a_data_1_0(bram_rdata_a_1_0), + .b_data_0_1(bram_rdata_b_0_1), + .a_addr_1_0(bram_addr_a_1_0), + .b_addr_0_1(bram_addr_b_0_1), + + .c_data_0_1(bram_wdata_c_0_1), + .c_addr_0_1(bram_addr_c_0_1), + .c_data_0_1_available(c_data_0_1_available), + + .c_data_1_1(bram_wdata_c_1_1), + .c_addr_1_1(bram_addr_c_1_1), + .c_data_1_1_available(c_data_1_1_available), + + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols) +); +endmodule + +///////////////////////////////////////////////// +// The 8x8 matmul definition +///////////////////////////////////////////////// + +module matmul_8x8_systolic( + input clk, + input reset, + input pe_reset, + input start_mat_mul, + output done_mat_mul, + + input [`AWIDTH-1:0] address_mat_a, + input [`AWIDTH-1:0] address_mat_b, + input [`AWIDTH-1:0] address_mat_c, + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_0, + output [`AWIDTH-1:0] a_addr_0_0, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_0, + output [`AWIDTH-1:0] b_addr_0_0, + + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_0, + output [`AWIDTH-1:0] a_addr_1_0, + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_1, + output [`AWIDTH-1:0] b_addr_0_1, + + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_1, + output [`AWIDTH-1:0] c_addr_0_1, + output c_data_0_1_available, + + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_1, + output [`AWIDTH-1:0] c_addr_1_1, + output c_data_1_1_available, + + input [`MASK_WIDTH-1:0] validity_mask_a_rows, + input [`MASK_WIDTH-1:0] validity_mask_a_cols, + input [`MASK_WIDTH-1:0] validity_mask_b_rows, + input [`MASK_WIDTH-1:0] validity_mask_b_cols +); + + ///////////////////////////////////////////////// + // ORing all done signals + ///////////////////////////////////////////////// + wire done_mat_mul_0_0; + wire done_mat_mul_0_1; + wire done_mat_mul_1_0; + wire done_mat_mul_1_1; + + assign done_mat_mul = done_mat_mul_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_1_NC; + + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_1_NC; + ///////////////////////////////////////////////// + // Matmul 0_0 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_0_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_0_to_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_0_to_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_0_0_NC; + assign a_data_in_0_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_0_0_NC; + assign c_data_in_0_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_0_0_NC; + assign b_data_in_0_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_0_to_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_0_0_to_0_1_NC; + wire [`AWIDTH-1:0] c_addr_0_0_NC; + wire c_data_0_0_available_NC; + +matmul_4x4_systolic u_matmul_4x4_systolic_0_0( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_0_0), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_0_0), + .b_data(b_data_0_0), + .a_data_in(a_data_in_0_0_NC), + .b_data_in(b_data_in_0_0_NC), + .c_data_in(c_data_in_0_0_NC), + .c_data_out(c_data_0_0_to_0_1_NC), + .a_data_out(a_data_0_0_to_0_1), + .b_data_out(b_data_0_0_to_1_0), + .a_addr(a_addr_0_0), + .b_addr(b_addr_0_0), + .c_addr(c_addr_0_0_NC), + .c_data_available(c_data_0_0_available_NC), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd0), + .b_loc(8'd0) +); + + ///////////////////////////////////////////////// + // Matmul 0_1 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_0_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_1_to_0_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_0_1_to_1_1; + wire [`AWIDTH-1:0] a_addr_0_1_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_0_1_NC; + assign a_data_0_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in_0_1_NC; + assign b_data_in_0_1_NC = 0; + +matmul_4x4_systolic u_matmul_4x4_systolic_0_1( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_0_1), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_0_1_NC), + .b_data(b_data_0_1), + .a_data_in(a_data_0_0_to_0_1), + .b_data_in(b_data_in_0_1_NC), + .c_data_in(c_data_0_0_to_0_1), + .c_data_out(c_data_0_1), + .a_data_out(a_data_0_1_to_0_2), + .b_data_out(b_data_0_1_to_1_1), + .a_addr(a_addr_0_1_NC), + .b_addr(b_addr_0_1), + .c_addr(c_addr_0_1), + .c_data_available(c_data_0_1_available), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd0), + .b_loc(8'd1) +); + + ///////////////////////////////////////////////// + // Matmul 1_0 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_1_0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_0_to_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_0_to_2_0; + wire [`AWIDTH-1:0] b_addr_1_0_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_0_NC; + assign b_data_1_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in_1_0_NC; + assign a_data_in_1_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in_1_0_NC; + assign c_data_in_1_0_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_0_to_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_1_0_to_1_1_NC; + wire [`AWIDTH-1:0] c_addr_1_0_NC; + wire c_data_1_0_available_NC; + +matmul_4x4_systolic u_matmul_4x4_systolic_1_0( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_1_0), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_1_0), + .b_data(b_data_1_0_NC), + .a_data_in(a_data_in_1_0_NC), + .b_data_in(b_data_0_0_to_1_0), + .c_data_in(c_data_in_1_0_NC), + .c_data_out(c_data_1_0_to_1_1_NC), + .a_data_out(a_data_1_0_to_1_1), + .b_data_out(b_data_1_0_to_2_0), + .a_addr(a_addr_1_0), + .b_addr(b_addr_1_0_NC), + .c_addr(c_addr_1_0_NC), + .c_data_available(c_data_1_0_available_NC), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd1), + .b_loc(8'd0) +); + + ///////////////////////////////////////////////// + // Matmul 1_1 + ///////////////////////////////////////////////// + + wire [3:0] flags_NC_1_1; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_1_to_1_2; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_1_to_2_1; + wire [`AWIDTH-1:0] a_addr_1_1_NC; + wire [`AWIDTH-1:0] b_addr_1_1_NC; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_1_1_NC; + assign a_data_1_1_NC = 0; + wire [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_1_1_NC; + assign b_data_1_1_NC = 0; + +matmul_4x4_systolic u_matmul_4x4_systolic_1_1( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul_1_1), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(a_data_1_1_NC), + .b_data(b_data_1_1_NC), + .a_data_in(a_data_1_0_to_1_1), + .b_data_in(b_data_0_1_to_1_1), + .c_data_in(c_data_1_0_to_1_1), + .c_data_out(c_data_1_1), + .a_data_out(a_data_1_1_to_1_2), + .b_data_out(b_data_1_1_to_2_1), + .a_addr(a_addr_1_1_NC), + .b_addr(b_addr_1_1_NC), + .c_addr(c_addr_1_1), + .c_data_available(c_data_1_1_available), + .validity_mask_a_rows({4'b0,validity_mask_a_rows}), + .validity_mask_a_cols({4'b0,validity_mask_a_cols}), + .validity_mask_b_rows({4'b0,validity_mask_b_rows}), + .validity_mask_b_cols({4'b0,validity_mask_b_cols}), + .final_mat_mul_size(8'd8), + .a_loc(8'd1), + .b_loc(8'd1) +); + +endmodule + + +////////////////////////////////// +//Dual port RAM +////////////////////////////////// +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] d0; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] d1; +input [`MAT_MUL_SIZE-1:0] we0; +input [`MAT_MUL_SIZE-1:0] we1; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] q0; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] q1; +input clk; + +`ifdef VCS +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] q0; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] q1; +reg [7:0] ram[((1<<`AWIDTH)-1):0]; +integer i; + +always @(posedge clk) +begin + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + q0[i*`DWIDTH +: `DWIDTH] <= ram[addr0+i]; + end +end + +always @(posedge clk) +begin + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `MAT_MUL_SIZE; i=i+1) begin + q1[i*`DWIDTH +: `DWIDTH] <= ram[addr1+i]; + end +end + +`else +//BRAMs available in VTR FPGA architectures have one bit write-enables. +//So let's combine multiple bits into 1. We don't have a usecase of +//writing/not-writing only parts of the word anyway. +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + +endmodule + + +////////////////////////////////////////////// +//4x4 systolic matrix multiplier +////////////////////////////////////////////// +module matmul_4x4_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, //Data values coming in from previous matmul - systolic connections + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out,//Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + final_mat_mul_size, + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; +assign clk_cnt_for_done = ((final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC) ; + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end + + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b0_data(b0_data), +.b1_data_delayed_1(b1_data_delayed_1), +.b2_data_delayed_2(b2_data_delayed_2), +.b3_data_delayed_3(b3_data_delayed_3), +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), +.final_mat_mul_size(final_mat_mul_size), +.a_loc(a_loc), +.b_loc(b_loc) +); + + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +assign a0_data_in = a_data_in[`DWIDTH-1:0]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +assign b0_data_in = b_data_in[`DWIDTH-1:0]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; + +//If b_loc is 0, that means this matmul block is on the top-row of the +//final large matmul. In that case, b will take inputs from mem. +//If b_loc != 0, that means this matmul block is not on the top-row of the +//final large matmul. In that case, b will take inputs from the matmul on top +//of this one. +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; + +//If a_loc is 0, that means this matmul block is on the left-col of the +//final large matmul. In that case, a will take inputs from mem. +//If a_loc != 0, that means this matmul block is not on the left-col of the +//final large matmul. In that case, a will take inputs from the matmul on left +//of this one. +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; + +wire [`DWIDTH-1:0] matrixC00; +wire [`DWIDTH-1:0] matrixC01; +wire [`DWIDTH-1:0] matrixC02; +wire [`DWIDTH-1:0] matrixC03; +wire [`DWIDTH-1:0] matrixC10; +wire [`DWIDTH-1:0] matrixC11; +wire [`DWIDTH-1:0] matrixC12; +wire [`DWIDTH-1:0] matrixC13; +wire [`DWIDTH-1:0] matrixC20; +wire [`DWIDTH-1:0] matrixC21; +wire [`DWIDTH-1:0] matrixC22; +wire [`DWIDTH-1:0] matrixC23; +wire [`DWIDTH-1:0] matrixC30; +wire [`DWIDTH-1:0] matrixC31; +wire [`DWIDTH-1:0] matrixC32; +wire [`DWIDTH-1:0] matrixC33; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC00(matrixC00), +.matrixC01(matrixC01), +.matrixC02(matrixC02), +.matrixC03(matrixC03), +.matrixC10(matrixC10), +.matrixC11(matrixC11), +.matrixC12(matrixC12), +.matrixC13(matrixC13), +.matrixC20(matrixC20), +.matrixC21(matrixC21), +.matrixC22(matrixC22), +.matrixC23(matrixC23), +.matrixC30(matrixC30), +.matrixC31(matrixC31), +.matrixC32(matrixC32), +.matrixC33(matrixC33) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual processing elements +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.reset(reset), +.clk(clk), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.matrixC00(matrixC00), +.matrixC01(matrixC01), +.matrixC02(matrixC02), +.matrixC03(matrixC03), +.matrixC10(matrixC10), +.matrixC11(matrixC11), +.matrixC12(matrixC12), +.matrixC13(matrixC13), +.matrixC20(matrixC20), +.matrixC21(matrixC21), +.matrixC22(matrixC22), +.matrixC23(matrixC23), +.matrixC30(matrixC30), +.matrixC31(matrixC31), +.matrixC32(matrixC32), +.matrixC33(matrixC33), +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +clk, +reset, +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC00, +matrixC01, +matrixC02, +matrixC03, +matrixC10, +matrixC11, +matrixC12, +matrixC13, +matrixC20, +matrixC21, +matrixC22, +matrixC23, +matrixC30, +matrixC31, +matrixC32, +matrixC33 +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC00; +input [`DWIDTH-1:0] matrixC01; +input [`DWIDTH-1:0] matrixC02; +input [`DWIDTH-1:0] matrixC03; +input [`DWIDTH-1:0] matrixC10; +input [`DWIDTH-1:0] matrixC11; +input [`DWIDTH-1:0] matrixC12; +input [`DWIDTH-1:0] matrixC13; +input [`DWIDTH-1:0] matrixC20; +input [`DWIDTH-1:0] matrixC21; +input [`DWIDTH-1:0] matrixC22; +input [`DWIDTH-1:0] matrixC23; +input [`DWIDTH-1:0] matrixC30; +input [`DWIDTH-1:0] matrixC31; +input [`DWIDTH-1:0] matrixC32; +input [`DWIDTH-1:0] matrixC33; + +wire row_latch_en; + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// + +assign row_latch_en = ((clk_cnt == ((final_mat_mul_size<<2) - final_mat_mul_size -1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +integer counter; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_1; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_2; +reg [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out_3; + +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col0; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col1; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col2; +wire [`MAT_MUL_SIZE*`DWIDTH-1:0] col3; +assign col0 = {matrixC30, matrixC20, matrixC10, matrixC00}; +assign col1 = {matrixC31, matrixC21, matrixC11, matrixC01}; +assign col2 = {matrixC32, matrixC22, matrixC12, matrixC02}; +assign col3 = {matrixC33, matrixC23, matrixC13, matrixC03}; + +//If save_output_to_accum is asserted, that means we are not intending to shift +//out the outputs, because the outputs are still partial sums. +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = row_latch_en ; + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c+address_stride_c; + c_data_out <= 0; + counter <= 0; + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + end + else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= col0; + c_data_out_1 <= col1; + c_data_out_2 <= col2; + c_data_out_3 <= col3; + counter <= counter + 1; + end + else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c+address_stride_c; + c_data_out <= 0; + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_addr <= c_addr - address_stride_c; + c_data_out <= c_data_out_1; + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_in; + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +a1_data_delayed_1, +a2_data_delayed_2, +a3_data_delayed_3, +b0_data, +b1_data_delayed_1, +b2_data_delayed_2, +b3_data_delayed_3, +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, +final_mat_mul_size, +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] b3_data_delayed_3; +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; +input [7:0] final_mat_mul_size; +input [7:0] a_loc; +input [7:0] b_loc; + +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if ((reset || ~start_mat_mul) || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + a_addr <= address_mat_a-address_stride_a; + a_mem_access <= 0; + end + + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + a_addr <= a_addr + address_stride_a; + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4)) ? + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign a0_data = a_data[`DWIDTH-1:0] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; + +//For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_1 <= a3_data; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + b_addr <= address_mat_b - address_stride_b; + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + b_addr <= b_addr + address_stride_b; + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4)) ? + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +//Slice data into chunks and qualify it with whether it is valid or not +assign b0_data = b_data[`DWIDTH-1:0] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; + +//For larger matmuls, more such delaying flops will be needed +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_1 <= b3_data; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +reset, +clk, +pe_reset, +a0, a1, a2, a3, +b0, b1, b2, b3, +matrixC00, +matrixC01, +matrixC02, +matrixC03, +matrixC10, +matrixC11, +matrixC12, +matrixC13, +matrixC20, +matrixC21, +matrixC22, +matrixC23, +matrixC30, +matrixC31, +matrixC32, +matrixC33, +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +output [`DWIDTH-1:0] matrixC00; +output [`DWIDTH-1:0] matrixC01; +output [`DWIDTH-1:0] matrixC02; +output [`DWIDTH-1:0] matrixC03; +output [`DWIDTH-1:0] matrixC10; +output [`DWIDTH-1:0] matrixC11; +output [`DWIDTH-1:0] matrixC12; +output [`DWIDTH-1:0] matrixC13; +output [`DWIDTH-1:0] matrixC20; +output [`DWIDTH-1:0] matrixC21; +output [`DWIDTH-1:0] matrixC22; +output [`DWIDTH-1:0] matrixC23; +output [`DWIDTH-1:0] matrixC30; +output [`DWIDTH-1:0] matrixC31; +output [`DWIDTH-1:0] matrixC32; +output [`DWIDTH-1:0] matrixC33; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a00to01, a01to02, a02to03, a03to04; +wire [`DWIDTH-1:0] a10to11, a11to12, a12to13, a13to14; +wire [`DWIDTH-1:0] a20to21, a21to22, a22to23, a23to24; +wire [`DWIDTH-1:0] a30to31, a31to32, a32to33, a33to34; + +wire [`DWIDTH-1:0] b00to10, b10to20, b20to30, b30to40; +wire [`DWIDTH-1:0] b01to11, b11to21, b21to31, b31to41; +wire [`DWIDTH-1:0] b02to12, b12to22, b22to32, b32to42; +wire [`DWIDTH-1:0] b03to13, b13to23, b23to33, b33to43; + +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe00(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a00to01), .out_b(b00to10), .out_c(matrixC00)); +processing_element pe01(.reset(effective_rst), .clk(clk), .in_a(a00to01), .in_b(b1), .out_a(a01to02), .out_b(b01to11), .out_c(matrixC01)); +processing_element pe02(.reset(effective_rst), .clk(clk), .in_a(a01to02), .in_b(b2), .out_a(a02to03), .out_b(b02to12), .out_c(matrixC02)); +processing_element pe03(.reset(effective_rst), .clk(clk), .in_a(a02to03), .in_b(b3), .out_a(a03to04), .out_b(b03to13), .out_c(matrixC03)); + +processing_element pe10(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b00to10), .out_a(a10to11), .out_b(b10to20), .out_c(matrixC10)); +processing_element pe11(.reset(effective_rst), .clk(clk), .in_a(a10to11), .in_b(b01to11), .out_a(a11to12), .out_b(b11to21), .out_c(matrixC11)); +processing_element pe12(.reset(effective_rst), .clk(clk), .in_a(a11to12), .in_b(b02to12), .out_a(a12to13), .out_b(b12to22), .out_c(matrixC12)); +processing_element pe13(.reset(effective_rst), .clk(clk), .in_a(a12to13), .in_b(b03to13), .out_a(a13to14), .out_b(b13to23), .out_c(matrixC13)); + +processing_element pe20(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b10to20), .out_a(a20to21), .out_b(b20to30), .out_c(matrixC20)); +processing_element pe21(.reset(effective_rst), .clk(clk), .in_a(a20to21), .in_b(b11to21), .out_a(a21to22), .out_b(b21to31), .out_c(matrixC21)); +processing_element pe22(.reset(effective_rst), .clk(clk), .in_a(a21to22), .in_b(b12to22), .out_a(a22to23), .out_b(b22to32), .out_c(matrixC22)); +processing_element pe23(.reset(effective_rst), .clk(clk), .in_a(a22to23), .in_b(b13to23), .out_a(a23to24), .out_b(b23to33), .out_c(matrixC23)); + +processing_element pe30(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b20to30), .out_a(a30to31), .out_b(b30to40), .out_c(matrixC30)); +processing_element pe31(.reset(effective_rst), .clk(clk), .in_a(a30to31), .in_b(b21to31), .out_a(a31to32), .out_b(b31to41), .out_c(matrixC31)); +processing_element pe32(.reset(effective_rst), .clk(clk), .in_a(a31to32), .in_b(b22to32), .out_a(a32to33), .out_b(b32to42), .out_c(matrixC32)); +processing_element pe33(.reset(effective_rst), .clk(clk), .in_a(a32to33), .in_b(b23to33), .out_a(a33to34), .out_b(b33to43), .out_c(matrixC33)); + +assign a_data_out = {a33to34,a23to24,a13to14,a03to04}; +assign b_data_out = {b33to43,b32to42,b31to41,b30to40}; + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Processing element (PE) +////////////////////////////////////////////////////////////////////////// +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + //This is an instantiation of a module that is defined in the arch file. + //It's a mode of the DSP slice (floating point 16-bit multiply and accumulate). + mac_fp u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mcml.v b/openfpga_flow/benchmarks/vtr_benchmark/mcml.v new file mode 100755 index 000000000..1a9b6bb4e --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mcml.v @@ -0,0 +1,24777 @@ + +// Skeleton +// Reads constants and instantiates all modules used by the hardware components + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +`define TRIG_WIDTH 5'b01010 //10; +`define PIPELINE_DEPTH_UPPER_LIMIT 10'b0100000000 //256; +`define ABSORB_ADDR_WIDTH 6'b010000 //16; +`define ABSORB_WORD_WIDTH 7'b01000000 //64; +`define WSCALE 22'b0111010100101111111111 //1919999; + +//From Roulette +//`define BIT_WIDTH 7'b0100000 +//`define LAYER_WIDTH 6'b000011 +`define LEFTSHIFT 6'b000011 // 2^3=8=1/0.125 where 0.125 = CHANCE of roulette +`define INTCHANCE 32'b00100000000000000000000000000000 //Based on 32 bit rand num generator +`define MIN_WEIGHT 9'b011001000 + +// From Boundary +`define BIT_WIDTH 7'b0100000 +`define LAYER_WIDTH 6'b000011 +`define INTMAX 32'b01111111111111111111111111111111 +`define INTMIN 32'b10000000000000000000000000000000 +`define DIVIDER_LATENCY 6'b011110 +`define FINAL_LATENCY 6'b011100 +`define MULT_LATENCY 1'b1 +`define ASPECT_RATIO 6'b000111 +`define TOTAL_LATENCY 7'b0111100 + +//From Move +//`define BIT_WIDTH 6'b100000 +//`define LAYER_WIDTH 6'b000011 +`define LOGSCALEFACTOR 6'b000101 +`define MAXLOG 32'b10110001011100100001011111110111 //Based on 32 bit unsigned rand num generator +`define CONST_MOVE_AMOUNT 15'b110000110101000 //Used for testing purposes only +`define MUTMAX_BITS 6'b001111 + +//From Hop +//`define BIT_WIDTH 6'b100000 +//`define LAYER_WIDTH 6'b000011 +//`define INTMAX 32'b01111111111111111111111111111111 +//`define INTMIN 32'b10000000000000000000000000000000 + +//From LogCalc +//`define BIT_WIDTH 7'b0100000 +`define MANTISSA_PRECISION 6'b001010 +`define LOG2_BIT_WIDTH 6'b000110 +`define LOG2 28'b0101100010111001000010111111 + +//From DropSpinWrapper +`define NR 10'b0100000000 +`define NZ 10'b0100000000 + +`define NR_EXP 5'b01000 //meaning `NR=2^`NR_exp or 2^8=256 +`define RGRID_SCLAE_EXP 6'b010101 //2^21 = RGRID_SCALE +`define ZGRID_SCLAE_EXP 6'b010101 //2^21 = ZGRID_SCALE + + +//`define BIT_WIDTH 7'b0100000 +`define BIT_WIDTH_2 8'b01000000 +`define WORD_WIDTH 8'b01000000 +`define ADDR_WIDTH 6'b010000 //256x256=2^8*2^8=2^16 + + +//From scatterer: +`define DIV 6'b010100//20; +`define SQRT 5'b01010 //10; +`define LAT 7'b0100101 //DIV + SQRT + 7; +`define INTMAX_2 {32'h3FFFFFFF,32'h00000001} +//`define INTMAX 32'b01111111111111111111111111111111//2147483647; +//`define INTMIN 32'b10000000000000000000000000000001//-2147483647; +`define INTMAXMinus3 32'b01111111111111111111111111111100//2147483644; +`define negINTMAXPlus3 32'b10000000000000000000000000000100//-2147483644; + +//From Reflector: +`define INTMAX_2_ref {32'h3FFFFFFF,32'hFFFFFFFF} + + +module mcml ( + reset, + clk, + + constants, + read_constants, + + result, + inc_result, + + calc_in_progress + ); + +// Total number of constants +//parameter LAST_CONSTANT = 104; +//parameter NUM_FRESNELS = 128; +//parameter NUM_TRIG_ELS = 1024; +//parameter ABSORB_ADDR_WIDTH=16; +//parameter ABSORB_WORD_WIDTH=64; +//parameter BIT_WIDTH = 32; + +input reset; +input clk; +input [31:0] constants; +input read_constants; +input inc_result; + +output calc_in_progress; +output [31:0] result; +reg calc_in_progress; +reg [31:0] result; + + +//integer i; + +wire [31:0] mem_fres_up, mem_fres_down, mem_sint, mem_cost; + +// photon calculator + +wire reset; + +// Scatterer Reflector memory look-up +wire [12:0] tindex; +wire [9:0] fresIndex; + +// DeadOrAlive Module (nothing) + +// Final results +wire [16-1:0] absorb_rdaddress, absorb_wraddress; +wire absorb_wren; +wire [64-1:0] absorb_data; +wire [64-1:0] absorb_q; + +// Flag when final results ready +wire done; +reg enable; +reg reset_calculator; + +// Combinational drivers +//reg [31:0] c_const[104 - 1:0]; +reg [31:0] c_const__103; +reg [31:0] c_const__102; +reg [31:0] c_const__101; +reg [31:0] c_const__100; +reg [31:0] c_const__99; +reg [31:0] c_const__98; +reg [31:0] c_const__97; +reg [31:0] c_const__96; +reg [31:0] c_const__95; +reg [31:0] c_const__94; +reg [31:0] c_const__93; +reg [31:0] c_const__92; +reg [31:0] c_const__91; +reg [31:0] c_const__90; +reg [31:0] c_const__89; +reg [31:0] c_const__88; +reg [31:0] c_const__87; +reg [31:0] c_const__86; +reg [31:0] c_const__85; +reg [31:0] c_const__84; +reg [31:0] c_const__83; +reg [31:0] c_const__82; +reg [31:0] c_const__81; +reg [31:0] c_const__80; +reg [31:0] c_const__79; +reg [31:0] c_const__78; +reg [31:0] c_const__77; +reg [31:0] c_const__76; +reg [31:0] c_const__75; +reg [31:0] c_const__74; +reg [31:0] c_const__73; +reg [31:0] c_const__72; +reg [31:0] c_const__71; +reg [31:0] c_const__70; +reg [31:0] c_const__69; +reg [31:0] c_const__68; +reg [31:0] c_const__67; +reg [31:0] c_const__66; +reg [31:0] c_const__65; +reg [31:0] c_const__64; +reg [31:0] c_const__63; +reg [31:0] c_const__62; +reg [31:0] c_const__61; +reg [31:0] c_const__60; +reg [31:0] c_const__59; +reg [31:0] c_const__58; +reg [31:0] c_const__57; +reg [31:0] c_const__56; +reg [31:0] c_const__55; +reg [31:0] c_const__54; +reg [31:0] c_const__53; +reg [31:0] c_const__52; +reg [31:0] c_const__51; +reg [31:0] c_const__50; +reg [31:0] c_const__49; +reg [31:0] c_const__48; +reg [31:0] c_const__47; +reg [31:0] c_const__46; +reg [31:0] c_const__45; +reg [31:0] c_const__44; +reg [31:0] c_const__43; +reg [31:0] c_const__42; +reg [31:0] c_const__41; +reg [31:0] c_const__40; +reg [31:0] c_const__39; +reg [31:0] c_const__38; +reg [31:0] c_const__37; +reg [31:0] c_const__36; +reg [31:0] c_const__35; +reg [31:0] c_const__34; +reg [31:0] c_const__33; +reg [31:0] c_const__32; +reg [31:0] c_const__31; +reg [31:0] c_const__30; +reg [31:0] c_const__29; +reg [31:0] c_const__28; +reg [31:0] c_const__27; +reg [31:0] c_const__26; +reg [31:0] c_const__25; +reg [31:0] c_const__24; +reg [31:0] c_const__23; +reg [31:0] c_const__22; +reg [31:0] c_const__21; +reg [31:0] c_const__20; +reg [31:0] c_const__19; +reg [31:0] c_const__18; +reg [31:0] c_const__17; +reg [31:0] c_const__16; +reg [31:0] c_const__15; +reg [31:0] c_const__14; +reg [31:0] c_const__13; +reg [31:0] c_const__12; +reg [31:0] c_const__11; +reg [31:0] c_const__10; +reg [31:0] c_const__9; +reg [31:0] c_const__8; +reg [31:0] c_const__7; +reg [31:0] c_const__6; +reg [31:0] c_const__5; +reg [31:0] c_const__4; +reg [31:0] c_const__3; +reg [31:0] c_const__2; +reg [31:0] c_const__1; +reg [31:0] c_const__0; + + +reg [12:0] c_counter; +reg c_toggle; + +reg [16-1:0] c_absorb_read_counter, c_absorb_write_counter; +reg [16-1:0] absorb_rdaddress_mux, absorb_wraddress_mux; +reg [64-1:0] absorb_data_mux; +reg absorb_wren_mux; + +reg [3:0] c_state; + +reg [31:0] c_result; +reg c_calc_in_progress; + +reg wren_fres_up, wren_fres_down, wren_sinp, wren_cosp, wren_sint, wren_cost; +reg [2:0] mem_layer; + +// Registered drivers +//reg [31:0] r_const[104 - 1:0]; +reg [31:0] r_const__103; +reg [31:0] r_const__102; +reg [31:0] r_const__101; +reg [31:0] r_const__100; +reg [31:0] r_const__99; +reg [31:0] r_const__98; +reg [31:0] r_const__97; +reg [31:0] r_const__96; +reg [31:0] r_const__95; +reg [31:0] r_const__94; +reg [31:0] r_const__93; +reg [31:0] r_const__92; +reg [31:0] r_const__91; +reg [31:0] r_const__90; +reg [31:0] r_const__89; +reg [31:0] r_const__88; +reg [31:0] r_const__87; +reg [31:0] r_const__86; +reg [31:0] r_const__85; +reg [31:0] r_const__84; +reg [31:0] r_const__83; +reg [31:0] r_const__82; +reg [31:0] r_const__81; +reg [31:0] r_const__80; +reg [31:0] r_const__79; +reg [31:0] r_const__78; +reg [31:0] r_const__77; +reg [31:0] r_const__76; +reg [31:0] r_const__75; +reg [31:0] r_const__74; +reg [31:0] r_const__73; +reg [31:0] r_const__72; +reg [31:0] r_const__71; +reg [31:0] r_const__70; +reg [31:0] r_const__69; +reg [31:0] r_const__68; +reg [31:0] r_const__67; +reg [31:0] r_const__66; +reg [31:0] r_const__65; +reg [31:0] r_const__64; +reg [31:0] r_const__63; +reg [31:0] r_const__62; +reg [31:0] r_const__61; +reg [31:0] r_const__60; +reg [31:0] r_const__59; +reg [31:0] r_const__58; +reg [31:0] r_const__57; +reg [31:0] r_const__56; +reg [31:0] r_const__55; +reg [31:0] r_const__54; +reg [31:0] r_const__53; +reg [31:0] r_const__52; +reg [31:0] r_const__51; +reg [31:0] r_const__50; +reg [31:0] r_const__49; +reg [31:0] r_const__48; +reg [31:0] r_const__47; +reg [31:0] r_const__46; +reg [31:0] r_const__45; +reg [31:0] r_const__44; +reg [31:0] r_const__43; +reg [31:0] r_const__42; +reg [31:0] r_const__41; +reg [31:0] r_const__40; +reg [31:0] r_const__39; +reg [31:0] r_const__38; +reg [31:0] r_const__37; +reg [31:0] r_const__36; +reg [31:0] r_const__35; +reg [31:0] r_const__34; +reg [31:0] r_const__33; +reg [31:0] r_const__32; +reg [31:0] r_const__31; +reg [31:0] r_const__30; +reg [31:0] r_const__29; +reg [31:0] r_const__28; +reg [31:0] r_const__27; +reg [31:0] r_const__26; +reg [31:0] r_const__25; +reg [31:0] r_const__24; +reg [31:0] r_const__23; +reg [31:0] r_const__22; +reg [31:0] r_const__21; +reg [31:0] r_const__20; +reg [31:0] r_const__19; +reg [31:0] r_const__18; +reg [31:0] r_const__17; +reg [31:0] r_const__16; +reg [31:0] r_const__15; +reg [31:0] r_const__14; +reg [31:0] r_const__13; +reg [31:0] r_const__12; +reg [31:0] r_const__11; +reg [31:0] r_const__10; +reg [31:0] r_const__9; +reg [31:0] r_const__8; +reg [31:0] r_const__7; +reg [31:0] r_const__6; +reg [31:0] r_const__5; +reg [31:0] r_const__4; +reg [31:0] r_const__3; +reg [31:0] r_const__2; +reg [31:0] r_const__1; +reg [31:0] r_const__0; + + + +reg [12:0] r_counter; +reg [16-1:0] r_absorb_read_counter; +reg [16-1:0] r_absorb_write_counter; +reg [3:0] r_state; +reg r_toggle; + +// Skeleton program states +parameter [3:0] ERROR_ST = 4'b0000, + READ1_ST = 4'b0001, + READ2_ST = 4'b0010, + READ3_ST = 4'b0011, + READ4_ST = 4'b0100, + READ5_ST = 4'b0101, + RESET_MEM_ST = 4'b0110, + CALC_ST = 4'b1000, + DONE1_ST = 4'b1001, + DONE2_ST = 4'b1010, + DONE3_ST = 4'b1011, + DONE4_ST = 4'b1100, + DONE5_ST = 4'b1101, + DONE6_ST = 4'b1110; + +// Instantiate lookup memories +dual_port_mem_zz u_fres_up(clk, constants, {3'b0, fresIndex}, {3'b0, mem_layer, r_counter[6:0]}, wren_fres_up, mem_fres_up); +dual_port_mem_yy u_fres_down(clk, constants, {3'b0, fresIndex}, {3'b0, mem_layer, r_counter[6:0]}, wren_fres_down, mem_fres_down); +dual_port_mem_xx u_sint(clk, constants, tindex, {mem_layer, r_counter[9:0]}, wren_sint, mem_sint); +dual_port_mem_ww u_cost(clk, constants, tindex, {mem_layer, r_counter[9:0]}, wren_cost, mem_cost); + +// Reduce size of absorption matrix +dual absorptionMatrix( .clk (clk), .data(absorb_data_mux[35:0]), + .rdaddress(absorb_rdaddress_mux), .wraddress(absorb_wraddress_mux), + .wren(absorb_wren_mux), .q(absorb_q[35:0])); +dual2 absorptionMatrix2( .clk (clk), .data(absorb_data_mux[53:36]), + .rdaddress(absorb_rdaddress_mux), .wraddress(absorb_wraddress_mux), + .wren(absorb_wren_mux), .q(absorb_q[53:36])); +dual3 absorptionMatrix3( .clk (clk), .data(absorb_data_mux[61:54]), + .rdaddress(absorb_rdaddress_mux), .wraddress(absorb_wraddress_mux), + .wren(absorb_wren_mux), .q(absorb_q[61:54])); + + + // + //peter m test since absorb_q not defined for 63:62 + assign absorb_q[63:62] = 2'b00; + + +PhotonCalculator u_calc ( + .clock(clk), .reset(reset_calculator), .enable(enable), + + // CONSTANTS + .total_photons(r_const__0), + + .randseed1(r_const__19), .randseed2(r_const__20), .randseed3(r_const__21), .randseed4(r_const__22), .randseed5(r_const__23), + + //Because it is in the module: + .initialWeight(32'b00000000000111010100101111111111), + + // Mover + .OneOver_MutMaxrad_0(r_const__32), .OneOver_MutMaxrad_1(r_const__33), .OneOver_MutMaxrad_2(r_const__34), .OneOver_MutMaxrad_3(r_const__35), .OneOver_MutMaxrad_4(r_const__36), .OneOver_MutMaxrad_5(r_const__37), + .OneOver_MutMaxdep_0(r_const__38), .OneOver_MutMaxdep_1(r_const__39), .OneOver_MutMaxdep_2(r_const__40), .OneOver_MutMaxdep_3(r_const__41), .OneOver_MutMaxdep_4(r_const__42), .OneOver_MutMaxdep_5(r_const__43), + .OneOver_Mut_0(r_const__26), .OneOver_Mut_1(r_const__27), .OneOver_Mut_2(r_const__28), .OneOver_Mut_3(r_const__29), .OneOver_Mut_4(r_const__30), .OneOver_Mut_5(r_const__31), + + // BoundaryChecker + .z1_0(r_const__50), .z1_1(r_const__51), .z1_2(r_const__52), .z1_3(r_const__53), .z1_4(r_const__54), .z1_5(r_const__55), + .z0_0(r_const__44), .z0_1(r_const__45), .z0_2(r_const__46), .z0_3(r_const__47), .z0_4(r_const__48), .z0_5(r_const__49), + .mut_0(32'b00000000000000000000000000000000), .mut_1(r_const__2), .mut_2(r_const__3), .mut_3(r_const__4), .mut_4(r_const__5), .mut_5(r_const__6), + .maxDepth_over_maxRadius(r_const__1), + + // Hop (no constants) + + // Scatterer Reflector Wrapper + .down_niOverNt_1(r_const__69), .down_niOverNt_2(r_const__70), .down_niOverNt_3(r_const__71), .down_niOverNt_4(r_const__72), .down_niOverNt_5(r_const__73), + .up_niOverNt_1(r_const__75), .up_niOverNt_2(r_const__76), .up_niOverNt_3(r_const__77), .up_niOverNt_4(r_const__78), .up_niOverNt_5(r_const__79), + .down_niOverNt_2_1({r_const__81,r_const__87}), .down_niOverNt_2_2({r_const__82,r_const__88}), .down_niOverNt_2_3({r_const__83,r_const__89}), .down_niOverNt_2_4({r_const__84,r_const__90}), .down_niOverNt_2_5({r_const__85,r_const__91}), + .up_niOverNt_2_1({r_const__93,r_const__99}), .up_niOverNt_2_2({r_const__94,r_const__100}), .up_niOverNt_2_3({r_const__95,r_const__101}), .up_niOverNt_2_4({r_const__96,r_const__102}), .up_niOverNt_2_5({r_const__97,r_const__103}), + .downCritAngle_0(r_const__7), .downCritAngle_1(r_const__8), .downCritAngle_2(r_const__9), .downCritAngle_3(r_const__10), .downCritAngle_4(r_const__11), + .upCritAngle_0(r_const__13), .upCritAngle_1(r_const__14), .upCritAngle_2(r_const__15), .upCritAngle_3(r_const__16), .upCritAngle_4(r_const__17), + .muaFraction1(r_const__57), .muaFraction2(r_const__58), .muaFraction3(r_const__59), .muaFraction4(r_const__60), .muaFraction5(r_const__61), + // Interface to memory look-up + // From Memories + .up_rFresnel(mem_fres_up), .down_rFresnel(mem_fres_down), .sint(mem_sint), .cost(mem_cost), + // To Memories + .tindex(tindex), .fresIndex(fresIndex), + + // DeadOrAlive (no Constants) + + // Absorber + .absorb_data(absorb_data), .absorb_rdaddress(absorb_rdaddress), .absorb_wraddress(absorb_wraddress), + .absorb_wren(absorb_wren), .absorb_q(absorb_q), + + // Done signal + .done(done) + ); + +// Mux to read the absorbtion array +always @(r_state or done or r_absorb_read_counter or r_absorb_write_counter or absorb_wraddress or absorb_data or absorb_rdaddress or absorb_data or absorb_wren ) +begin + if(r_state == RESET_MEM_ST) + begin + absorb_wren_mux = 1'b1; + absorb_data_mux = 64'b0; + absorb_rdaddress_mux = r_absorb_read_counter; + absorb_wraddress_mux = r_absorb_write_counter; + end + else if(done == 1'b1) + begin + absorb_rdaddress_mux = r_absorb_read_counter; + absorb_wraddress_mux = absorb_wraddress; + absorb_data_mux = absorb_data; + absorb_wren_mux = 1'b0; + end + else + begin + absorb_rdaddress_mux = absorb_rdaddress; + absorb_wraddress_mux = absorb_wraddress; + absorb_data_mux = absorb_data; + absorb_wren_mux = absorb_wren; + end +end + +// Skeleton SW/HW interface +// 1. Read constants +// 2. Wait for completion +// 3. Write data back +always @(r_state or r_absorb_read_counter or r_absorb_write_counter or result or r_toggle or r_counter or read_constants or constants or done + or inc_result or mem_cost or mem_sint or absorb_q + or r_const__103 + or r_const__102 + or r_const__101 + or r_const__100 + or r_const__99 + or r_const__98 + or r_const__97 + or r_const__96 + or r_const__95 + or r_const__94 + or r_const__93 + or r_const__92 + or r_const__91 + or r_const__90 + or r_const__89 + or r_const__88 + or r_const__87 + or r_const__86 + or r_const__85 + or r_const__84 + or r_const__83 + or r_const__82 + or r_const__81 + or r_const__80 + or r_const__79 + or r_const__78 + or r_const__77 + or r_const__76 + or r_const__75 + or r_const__74 + or r_const__73 + or r_const__72 + or r_const__71 + or r_const__70 + or r_const__69 + or r_const__68 + or r_const__67 + or r_const__66 + or r_const__65 + or r_const__64 + or r_const__63 + or r_const__62 + or r_const__61 + or r_const__60 + or r_const__59 + or r_const__58 + or r_const__57 + or r_const__56 + or r_const__55 + or r_const__54 + or r_const__53 + or r_const__52 + or r_const__51 + or r_const__50 + or r_const__49 + or r_const__48 + or r_const__47 + or r_const__46 + or r_const__45 + or r_const__44 + or r_const__43 + or r_const__42 + or r_const__41 + or r_const__40 + or r_const__39 + or r_const__38 + or r_const__37 + or r_const__36 + or r_const__35 + or r_const__34 + or r_const__33 + or r_const__32 + or r_const__31 + or r_const__30 + or r_const__29 + or r_const__28 + or r_const__27 + or r_const__26 + or r_const__25 + or r_const__24 + or r_const__23 + or r_const__22 + or r_const__21 + or r_const__20 + or r_const__19 + or r_const__18 + or r_const__17 + or r_const__16 + or r_const__15 + or r_const__14 + or r_const__13 + or r_const__12 + or r_const__11 + or r_const__10 + or r_const__9 + or r_const__8 + or r_const__7 + or r_const__6 + or r_const__5 + or r_const__4 + or r_const__3 + or r_const__2 + or r_const__1 + or r_const__0) begin + // Initialize data + //for(i = 0; i < 104; i = i + 1) begin + // c_const[i] = r_const[i]; + //end + begin +//c_const__103 = r_const__103; +c_const__102 = r_const__102; +c_const__101 = r_const__101; +c_const__100 = r_const__100; +c_const__99 = r_const__99; +c_const__98 = r_const__98; +c_const__97 = r_const__97; +c_const__96 = r_const__96; +c_const__95 = r_const__95; +c_const__94 = r_const__94; +c_const__93 = r_const__93; +c_const__92 = r_const__92; +c_const__91 = r_const__91; +c_const__90 = r_const__90; +c_const__89 = r_const__89; +c_const__88 = r_const__88; +c_const__87 = r_const__87; +c_const__86 = r_const__86; +c_const__85 = r_const__85; +c_const__84 = r_const__84; +c_const__83 = r_const__83; +c_const__82 = r_const__82; +c_const__81 = r_const__81; +c_const__80 = r_const__80; +c_const__79 = r_const__79; +c_const__78 = r_const__78; +c_const__77 = r_const__77; +c_const__76 = r_const__76; +c_const__75 = r_const__75; +c_const__74 = r_const__74; +c_const__73 = r_const__73; +c_const__72 = r_const__72; +c_const__71 = r_const__71; +c_const__70 = r_const__70; +c_const__69 = r_const__69; +c_const__68 = r_const__68; +c_const__67 = r_const__67; +c_const__66 = r_const__66; +c_const__65 = r_const__65; +c_const__64 = r_const__64; +c_const__63 = r_const__63; +c_const__62 = r_const__62; +c_const__61 = r_const__61; +c_const__60 = r_const__60; +c_const__59 = r_const__59; +c_const__58 = r_const__58; +c_const__57 = r_const__57; +c_const__56 = r_const__56; +c_const__55 = r_const__55; +c_const__54 = r_const__54; +c_const__53 = r_const__53; +c_const__52 = r_const__52; +c_const__51 = r_const__51; +c_const__50 = r_const__50; +c_const__49 = r_const__49; +c_const__48 = r_const__48; +c_const__47 = r_const__47; +c_const__46 = r_const__46; +c_const__45 = r_const__45; +c_const__44 = r_const__44; +c_const__43 = r_const__43; +c_const__42 = r_const__42; +c_const__41 = r_const__41; +c_const__40 = r_const__40; +c_const__39 = r_const__39; +c_const__38 = r_const__38; +c_const__37 = r_const__37; +c_const__36 = r_const__36; +c_const__35 = r_const__35; +c_const__34 = r_const__34; +c_const__33 = r_const__33; +c_const__32 = r_const__32; +c_const__31 = r_const__31; +c_const__30 = r_const__30; +c_const__29 = r_const__29; +c_const__28 = r_const__28; +c_const__27 = r_const__27; +c_const__26 = r_const__26; +c_const__25 = r_const__25; +c_const__24 = r_const__24; +c_const__23 = r_const__23; +c_const__22 = r_const__22; +c_const__21 = r_const__21; +c_const__20 = r_const__20; +c_const__19 = r_const__19; +c_const__18 = r_const__18; +c_const__17 = r_const__17; +c_const__16 = r_const__16; +c_const__15 = r_const__15; +c_const__14 = r_const__14; +c_const__13 = r_const__13; +c_const__12 = r_const__12; +c_const__11 = r_const__11; +c_const__10 = r_const__10; +c_const__9 = r_const__9; +c_const__8 = r_const__8; +c_const__7 = r_const__7; +c_const__6 = r_const__6; +c_const__5 = r_const__5; +c_const__4 = r_const__4; +c_const__3 = r_const__3; +c_const__2 = r_const__2; +c_const__1 = r_const__1; +c_const__0 = r_const__0; + end + /* + //honourary c_const__103 = r_const__103 + c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; +*/ + // Determine next state and which data changes + case(r_state) + //ERROR_ST: + READ1_ST: + begin + if(read_constants) + begin + // peter m redoing this to a shift register r_const 104 will shift to r_const 103 etc etc + // if its in the read_constants state + // c_const[r_counter] = constants; + c_counter = r_counter + 13'b00000000000001; + c_const__103 = constants; + //pm preventing latches + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + mem_layer = r_counter[12:10]; + end + else + begin + c_const__103 = r_const__103; + if(r_counter >= 104) + begin + c_counter = 13'b0000000000000; + c_state = READ2_ST; + //preventing latches + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + mem_layer = r_counter[12:10]; + + end + else + begin + c_counter = r_counter; + c_state = r_state; + + //preventing latches + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + mem_layer = r_counter[12:10]; + end + end + end + READ2_ST: + begin + mem_layer = r_counter[9:7]; + if(read_constants) + begin + wren_fres_up = 1'b1; + c_counter = r_counter + 13'b00000000000001; + //prevent latches + + c_const__103 = r_const__103; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + + end + else + begin + if(r_counter >= 5*128) + begin + c_counter = 13'b0000000000000; + c_state = READ3_ST; + + c_const__103 = r_const__103; + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + end + else + begin + c_counter = r_counter; + c_const__103 = r_const__103; + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + + end + end + end + READ3_ST: + begin + mem_layer = r_counter[9:7]; + c_const__103 = r_const__103; + + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + + wren_fres_up = 1'b0; + + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + // mem_layer = r_counter[12:10]; + if(read_constants) + begin + wren_fres_down = 1'b1; + c_counter = r_counter + 13'b00000000000001; + c_state = r_state; + end + else + begin + if(r_counter >= 5*128) + begin + c_counter = 13'b0000000000000; + c_state = READ4_ST; + wren_fres_down = 1'b0; + end + else + begin + c_counter = r_counter; + c_state = r_state; + wren_fres_down = 1'b0; + end + end + end + READ4_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + //wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + if(read_constants) + begin + wren_cost = 1'b1; + c_counter = r_counter + 13'b00000000000001; + c_state = r_state; + end + else + begin + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000000000000000; + c_state = READ5_ST; + wren_cost = 1'b0; + end + else + begin + c_counter = r_counter; + c_state = r_state; + wren_cost = 1'b0; + end + end + end + READ5_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + //c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + //wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + if(read_constants) + begin + wren_sint = 1'b1; + c_counter = r_counter + 13'b00000000000000000000000001; + c_state = r_state; + c_absorb_read_counter = r_absorb_read_counter; + end + else + begin + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000000000000000; + c_absorb_read_counter = 16'b0000000000000000000000000; //use to be 13 bit. Error in odin + c_state = RESET_MEM_ST; + wren_sint = 1'b0; + end + else + begin + c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_state = r_state; + wren_sint = 1'b0; + end + end + end + RESET_MEM_ST: + begin + c_const__103 = r_const__103; + // c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + //c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + //c_absorb_write_counter = r_absorb_write_counter; + //c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + + + c_counter = r_counter; + + c_toggle = 1'b0; + c_calc_in_progress = 1'b1; + c_absorb_write_counter = r_absorb_write_counter + 16'b0000000000000001; + if(r_absorb_write_counter == 16'b1111111111111111) + begin + c_state = CALC_ST; + end + else + begin + c_state = r_state; + + end + end + CALC_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + //c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + //c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + + if(done == 1'b0) + begin + c_calc_in_progress = 1'b1; + c_toggle = 1'b0; + c_counter = r_counter; + c_state = r_state; + + end + else + begin + c_toggle = 1'b0; + c_calc_in_progress = 1'b0; + c_state = DONE6_ST; + c_counter = 13'b0000000000000; + end + end + // DEBUG STATES BEGIN + + DONE1_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + c_result = r_const__103; + //original -c_result = {32'b0,r_const[r_counter]}; + if(inc_result) + begin + if(r_counter >= 13'b0000010001100) //104 + begin + c_counter = 13'b0000000000000; + c_state = DONE2_ST; + end + else + begin + c_counter = r_counter + 13'b0000000000001; + c_state = DONE1_ST; + end + end + + else + begin + if(r_counter >= 13'b0000010001100) //104 + begin + c_counter = 13'b0; + c_state = DONE2_ST; + end + else + begin + c_state = DONE1_ST; + c_counter = r_counter; + end + end + end + DONE2_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + //mem_layer = r_counter[12:10]; + + + mem_layer = r_counter[9:7]; + //c_result = {32'b00000000000000000000000000000000,mem_fres_up}; + c_result = 32'b0; + if(inc_result) + begin + c_counter = r_counter + 13'b0000000000001; + c_state = DONE1_ST; + end + else + begin + if(r_counter >= 13'b0000010001100) //104 + begin + c_counter = 13'b0000000000000; + c_state = DONE2_ST; + end + else + begin + c_counter = r_counter; + c_state = r_state; + end + end + end + DONE3_ST: + begin + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + //mem_layer = r_counter[12:10]; + + + + + mem_layer = r_counter[9:7]; + //c_result = {32'b00000000000000000000000000000000,mem_fres_down}; + c_result = 32'b0; + + if(inc_result) + begin + // stub, write constants back to see if read in properly + c_counter = r_counter + 13'b0000000000001; + c_state = DONE3_ST; + end + + else + begin + if(r_counter >= 13'b0001010000000) //5*128 = 640 + begin + c_counter = 13'b0000000000000; + c_state = DONE4_ST; + end + else + begin + c_counter = r_counter; + c_state = DONE3_ST; + end + + + + + end + end + DONE4_ST: + begin + + + + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + + c_result = mem_cost; + + if(inc_result) + begin + // stub, write constants back to see if read in properly + c_counter = r_counter + 13'b0000000000001; + c_state = DONE4_ST; + end + else + begin + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000; + c_state = DONE5_ST; + end + + else + begin + c_state = DONE4_ST; + c_counter = r_counter; + end + end + end + DONE5_ST: + begin + + c_const__103 = r_const__103; + //c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + c_result = mem_sint; + + if(r_counter >= 13'b1010000000000) //5*1024 = 5120 + begin + c_counter = 13'b0000000000000; + c_state = DONE6_ST; + end + else + begin + c_state = DONE5_ST; + if(inc_result) + begin + // stub, write constants back to see if read in properly + c_counter = r_counter + 13'b00000000000001; + end + else + begin + c_counter = r_counter; + end + end + end + + // DEBUG STATES END*/ + DONE6_ST: + begin + c_const__103 = r_const__103; + c_counter = r_counter; + //c_absorb_read_counter = r_absorb_read_counter; + //c_result = result; + c_calc_in_progress = 1'b0; + //c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + //c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + + + c_state = DONE6_ST; + + + if(r_toggle == 1'b0) + begin + c_result = absorb_q[63:32]; + // c_state = r_state; + end + else + begin + c_result = absorb_q[31:0]; + // c_state = r_state; + end + + if(inc_result) + begin + if(r_toggle == 1'b0) + begin + c_toggle = 1'b1; + c_absorb_read_counter = r_absorb_read_counter ; + end + else + begin + c_toggle = 1'b0; + c_absorb_read_counter = r_absorb_read_counter + 16'b01; + end + end + else + begin + c_absorb_read_counter = r_absorb_read_counter; + c_toggle= r_toggle; + + end + // c_state = DONE6_ST; + end + + default: + begin + c_state = ERROR_ST; + c_const__103 = r_const__103; + c_counter = r_counter; + c_absorb_read_counter = r_absorb_read_counter; + c_result = result; + c_calc_in_progress = 1'b0; + // c_state = r_state; + wren_fres_up = 1'b0; + wren_fres_down = 1'b0; + wren_sint = 1'b0; + wren_cost = 1'b0; + c_absorb_write_counter = r_absorb_write_counter; + c_toggle = r_toggle; + + mem_layer = r_counter[12:10]; + end + endcase + end // FSM always + + + +// Latch Data +always @(posedge clk) + begin + if(reset) + begin + r_counter <= 13'b0000000000000000000000000; +r_const__103 <= 32'b00000000000000000000000000000000; +r_const__102 <= 32'b00000000000000000000000000000000; +r_const__101 <= 32'b00000000000000000000000000000000; +r_const__100 <= 32'b00000000000000000000000000000000; +r_const__99 <= 32'b00000000000000000000000000000000; +r_const__98 <= 32'b00000000000000000000000000000000; +r_const__97 <= 32'b00000000000000000000000000000000; +r_const__96 <= 32'b00000000000000000000000000000000; +r_const__95 <= 32'b00000000000000000000000000000000; +r_const__94 <= 32'b00000000000000000000000000000000; +r_const__93 <= 32'b00000000000000000000000000000000; +r_const__92 <= 32'b00000000000000000000000000000000; +r_const__91 <= 32'b00000000000000000000000000000000; +r_const__90 <= 32'b00000000000000000000000000000000; +r_const__89 <= 32'b00000000000000000000000000000000; +r_const__88 <= 32'b00000000000000000000000000000000; +r_const__87 <= 32'b00000000000000000000000000000000; +r_const__86 <= 32'b00000000000000000000000000000000; +r_const__85 <= 32'b00000000000000000000000000000000; +r_const__84 <= 32'b00000000000000000000000000000000; +r_const__83 <= 32'b00000000000000000000000000000000; +r_const__82 <= 32'b00000000000000000000000000000000; +r_const__81 <= 32'b00000000000000000000000000000000; +r_const__80 <= 32'b00000000000000000000000000000000; +r_const__79 <= 32'b00000000000000000000000000000000; +r_const__78 <= 32'b00000000000000000000000000000000; +r_const__77 <= 32'b00000000000000000000000000000000; +r_const__76 <= 32'b00000000000000000000000000000000; +r_const__75 <= 32'b00000000000000000000000000000000; +r_const__74 <= 32'b00000000000000000000000000000000; +r_const__73 <= 32'b00000000000000000000000000000000; +r_const__72 <= 32'b00000000000000000000000000000000; +r_const__71 <= 32'b00000000000000000000000000000000; +r_const__70 <= 32'b00000000000000000000000000000000; +r_const__69 <= 32'b00000000000000000000000000000000; +r_const__68 <= 32'b00000000000000000000000000000000; +r_const__67 <= 32'b00000000000000000000000000000000; +r_const__66 <= 32'b00000000000000000000000000000000; +r_const__65 <= 32'b00000000000000000000000000000000; +r_const__64 <= 32'b00000000000000000000000000000000; +r_const__63 <= 32'b00000000000000000000000000000000; +r_const__62 <= 32'b00000000000000000000000000000000; +r_const__61 <= 32'b00000000000000000000000000000000; +r_const__60 <= 32'b00000000000000000000000000000000; +r_const__59 <= 32'b00000000000000000000000000000000; +r_const__58 <= 32'b00000000000000000000000000000000; +r_const__57 <= 32'b00000000000000000000000000000000; +r_const__56 <= 32'b00000000000000000000000000000000; +r_const__55 <= 32'b00000000000000000000000000000000; +r_const__54 <= 32'b00000000000000000000000000000000; +r_const__53 <= 32'b00000000000000000000000000000000; +r_const__52 <= 32'b00000000000000000000000000000000; +r_const__51 <= 32'b00000000000000000000000000000000; +r_const__50 <= 32'b00000000000000000000000000000000; +r_const__49 <= 32'b00000000000000000000000000000000; +r_const__48 <= 32'b00000000000000000000000000000000; +r_const__47 <= 32'b00000000000000000000000000000000; +r_const__46 <= 32'b00000000000000000000000000000000; +r_const__45 <= 32'b00000000000000000000000000000000; +r_const__44 <= 32'b00000000000000000000000000000000; +r_const__43 <= 32'b00000000000000000000000000000000; +r_const__42 <= 32'b00000000000000000000000000000000; +r_const__41 <= 32'b00000000000000000000000000000000; +r_const__40 <= 32'b00000000000000000000000000000000; +r_const__39 <= 32'b00000000000000000000000000000000; +r_const__38 <= 32'b00000000000000000000000000000000; +r_const__37 <= 32'b00000000000000000000000000000000; +r_const__36 <= 32'b00000000000000000000000000000000; +r_const__35 <= 32'b00000000000000000000000000000000; +r_const__34 <= 32'b00000000000000000000000000000000; +r_const__33 <= 32'b00000000000000000000000000000000; +r_const__32 <= 32'b00000000000000000000000000000000; +r_const__31 <= 32'b00000000000000000000000000000000; +r_const__30 <= 32'b00000000000000000000000000000000; +r_const__29 <= 32'b00000000000000000000000000000000; +r_const__28 <= 32'b00000000000000000000000000000000; +r_const__27 <= 32'b00000000000000000000000000000000; +r_const__26 <= 32'b00000000000000000000000000000000; +r_const__25 <= 32'b00000000000000000000000000000000; +r_const__24 <= 32'b00000000000000000000000000000000; +r_const__23 <= 32'b00000000000000000000000000000000; +r_const__22 <= 32'b00000000000000000000000000000000; +r_const__21 <= 32'b00000000000000000000000000000000; +r_const__20 <= 32'b00000000000000000000000000000000; +r_const__19 <= 32'b00000000000000000000000000000000; +r_const__18 <= 32'b00000000000000000000000000000000; +r_const__17 <= 32'b00000000000000000000000000000000; +r_const__16 <= 32'b00000000000000000000000000000000; +r_const__15 <= 32'b00000000000000000000000000000000; +r_const__14 <= 32'b00000000000000000000000000000000; +r_const__13 <= 32'b00000000000000000000000000000000; +r_const__12 <= 32'b00000000000000000000000000000000; +r_const__11 <= 32'b00000000000000000000000000000000; +r_const__10 <= 32'b00000000000000000000000000000000; +r_const__9 <= 32'b00000000000000000000000000000000; +r_const__8 <= 32'b00000000000000000000000000000000; +r_const__7 <= 32'b00000000000000000000000000000000; +r_const__6 <= 32'b00000000000000000000000000000000; +r_const__5 <= 32'b00000000000000000000000000000000; +r_const__4 <= 32'b00000000000000000000000000000000; +r_const__3 <= 32'b00000000000000000000000000000000; +r_const__2 <= 32'b00000000000000000000000000000000; +r_const__1 <= 32'b00000000000000000000000000000000; +r_const__0 <= 32'b00000000000000000000000000000000; + + r_state <= READ1_ST; + result <= 32'b00000000000000000000000000000000; + calc_in_progress <= 1'b0; + r_absorb_read_counter <= 16'b0000000000000000; + enable <= 1'b0; + r_absorb_write_counter <= 16'b0000000000000000; + reset_calculator <= 1'b1; + r_toggle <= 1'b0; + end + else + begin + r_counter <= c_counter; + if (c_state == READ1_ST) + + //for(i = 0; i < 104; i = i + 1) begin + // r_const[i] <= c_const[i]; + //end + begin + + //shift register implementation for read-in constant state + +//first one is from counter +r_const__103 <= c_const__103; +// all others shift +r_const__102 <= r_const__103; +r_const__101 <= r_const__102; +r_const__100 <= r_const__101; +r_const__99 <= r_const__100; +r_const__98 <= r_const__99; +r_const__97 <= r_const__98; +r_const__96 <= r_const__97; +r_const__95 <= r_const__96; +r_const__94 <= r_const__95; +r_const__93 <= r_const__94; +r_const__92 <= r_const__93; +r_const__91 <= r_const__92; +r_const__90 <= r_const__91; +r_const__89 <= r_const__90; +r_const__88 <= r_const__89; +r_const__87 <= r_const__88; +r_const__86 <= r_const__87; +r_const__85 <= r_const__86; +r_const__84 <= r_const__85; +r_const__83 <= r_const__84; +r_const__82 <= r_const__83; +r_const__81 <= r_const__82; +r_const__80 <= r_const__81; +r_const__79 <= r_const__80; +r_const__78 <= r_const__79; +r_const__77 <= r_const__78; +r_const__76 <= r_const__77; +r_const__75 <= r_const__76; +r_const__74 <= r_const__75; +r_const__73 <= r_const__74; +r_const__72 <= r_const__73; +r_const__71 <= r_const__72; +r_const__70 <= r_const__71; +r_const__69 <= r_const__70; +r_const__68 <= r_const__69; +r_const__67 <= r_const__68; +r_const__66 <= r_const__67; +r_const__65 <= r_const__66; +r_const__64 <= r_const__65; +r_const__63 <= r_const__64; +r_const__62 <= r_const__63; +r_const__61 <= r_const__62; +r_const__60 <= r_const__61; +r_const__59 <= r_const__60; +r_const__58 <= r_const__59; +r_const__57 <= r_const__58; +r_const__56 <= r_const__57; +r_const__55 <= r_const__56; +r_const__54 <= r_const__55; +r_const__53 <= r_const__54; +r_const__52 <= r_const__53; +r_const__51 <= r_const__52; +r_const__50 <= r_const__51; +r_const__49 <= r_const__50; +r_const__48 <= r_const__49; +r_const__47 <= r_const__48; +r_const__46 <= r_const__47; +r_const__45 <= r_const__46; +r_const__44 <= r_const__45; +r_const__43 <= r_const__44; +r_const__42 <= r_const__43; +r_const__41 <= r_const__42; +r_const__40 <= r_const__41; +r_const__39 <= r_const__40; +r_const__38 <= r_const__39; +r_const__37 <= r_const__38; +r_const__36 <= r_const__37; +r_const__35 <= r_const__36; +r_const__34 <= r_const__35; +r_const__33 <= r_const__34; +r_const__32 <= r_const__33; +r_const__31 <= r_const__32; +r_const__30 <= r_const__31; +r_const__29 <= r_const__30; +r_const__28 <= r_const__29; +r_const__27 <= r_const__28; +r_const__26 <= r_const__27; +r_const__25 <= r_const__26; +r_const__24 <= r_const__25; +r_const__23 <= r_const__24; +r_const__22 <= r_const__23; +r_const__21 <= r_const__22; +r_const__20 <= r_const__21; +r_const__19 <= r_const__20; +r_const__18 <= r_const__19; +r_const__17 <= r_const__18; +r_const__16 <= r_const__17; +r_const__15 <= r_const__16; +r_const__14 <= r_const__15; +r_const__13 <= r_const__14; +r_const__12 <= r_const__13; +r_const__11 <= r_const__12; +r_const__10 <= r_const__11; +r_const__9 <= r_const__10; +r_const__8 <= r_const__9; +r_const__7 <= r_const__8; +r_const__6 <= r_const__7; +r_const__5 <= r_const__6; +r_const__4 <= r_const__5; +r_const__3 <= r_const__4; +r_const__2 <= r_const__3; +r_const__1 <= r_const__2; +r_const__0 <= r_const__1; +end +else +begin +//original code +r_const__103 <= c_const__103; +r_const__102 <= c_const__102; +r_const__101 <= c_const__101; +r_const__100 <= c_const__100; +r_const__99 <= c_const__99; +r_const__98 <= c_const__98; +r_const__97 <= c_const__97; +r_const__96 <= c_const__96; +r_const__95 <= c_const__95; +r_const__94 <= c_const__94; +r_const__93 <= c_const__93; +r_const__92 <= c_const__92; +r_const__91 <= c_const__91; +r_const__90 <= c_const__90; +r_const__89 <= c_const__89; +r_const__88 <= c_const__88; +r_const__87 <= c_const__87; +r_const__86 <= c_const__86; +r_const__85 <= c_const__85; +r_const__84 <= c_const__84; +r_const__83 <= c_const__83; +r_const__82 <= c_const__82; +r_const__81 <= c_const__81; +r_const__80 <= c_const__80; +r_const__79 <= c_const__79; +r_const__78 <= c_const__78; +r_const__77 <= c_const__77; +r_const__76 <= c_const__76; +r_const__75 <= c_const__75; +r_const__74 <= c_const__74; +r_const__73 <= c_const__73; +r_const__72 <= c_const__72; +r_const__71 <= c_const__71; +r_const__70 <= c_const__70; +r_const__69 <= c_const__69; +r_const__68 <= c_const__68; +r_const__67 <= c_const__67; +r_const__66 <= c_const__66; +r_const__65 <= c_const__65; +r_const__64 <= c_const__64; +r_const__63 <= c_const__63; +r_const__62 <= c_const__62; +r_const__61 <= c_const__61; +r_const__60 <= c_const__60; +r_const__59 <= c_const__59; +r_const__58 <= c_const__58; +r_const__57 <= c_const__57; +r_const__56 <= c_const__56; +r_const__55 <= c_const__55; +r_const__54 <= c_const__54; +r_const__53 <= c_const__53; +r_const__52 <= c_const__52; +r_const__51 <= c_const__51; +r_const__50 <= c_const__50; +r_const__49 <= c_const__49; +r_const__48 <= c_const__48; +r_const__47 <= c_const__47; +r_const__46 <= c_const__46; +r_const__45 <= c_const__45; +r_const__44 <= c_const__44; +r_const__43 <= c_const__43; +r_const__42 <= c_const__42; +r_const__41 <= c_const__41; +r_const__40 <= c_const__40; +r_const__39 <= c_const__39; +r_const__38 <= c_const__38; +r_const__37 <= c_const__37; +r_const__36 <= c_const__36; +r_const__35 <= c_const__35; +r_const__34 <= c_const__34; +r_const__33 <= c_const__33; +r_const__32 <= c_const__32; +r_const__31 <= c_const__31; +r_const__30 <= c_const__30; +r_const__29 <= c_const__29; +r_const__28 <= c_const__28; +r_const__27 <= c_const__27; +r_const__26 <= c_const__26; +r_const__25 <= c_const__25; +r_const__24 <= c_const__24; +r_const__23 <= c_const__23; +r_const__22 <= c_const__22; +r_const__21 <= c_const__21; +r_const__20 <= c_const__20; +r_const__19 <= c_const__19; +r_const__18 <= c_const__18; +r_const__17 <= c_const__17; +r_const__16 <= c_const__16; +r_const__15 <= c_const__15; +r_const__14 <= c_const__14; +r_const__13 <= c_const__13; +r_const__12 <= c_const__12; +r_const__11 <= c_const__11; +r_const__10 <= c_const__10; +r_const__9 <= c_const__9; +r_const__8 <= c_const__8; +r_const__7 <= c_const__7; +r_const__6 <= c_const__6; +r_const__5 <= c_const__5; +r_const__4 <= c_const__4; +r_const__3 <= c_const__3; +r_const__2 <= c_const__2; +r_const__1 <= c_const__1; +r_const__0 <= c_const__0; +end + + + + + r_state <= c_state; + result <= c_result; + calc_in_progress <= c_calc_in_progress; + r_absorb_read_counter <= c_absorb_read_counter; + r_absorb_write_counter <= c_absorb_write_counter; + r_toggle <= c_toggle; + //if(c_state == CALC_ST) + //begin + enable <= 1'b1; + //end + //else + //begin + // enable = 1'b0; + //end + if(c_state == RESET_MEM_ST) + begin + reset_calculator <= 1'b1; + end + else + begin + reset_calculator <= 1'b0; + end + end + end + +endmodule + + + + + + + +module dual_port_mem_zz (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + +module dual_port_mem_yy (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + +module dual_port_mem_xx (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + +module dual_port_mem_ww (clk, data, rdaddress, wraddress , wren, q); + +// 32bit wide +// 13bit address + +input clk; +input[31:0] data; +input [12:0] rdaddress; +input [12:0] wraddress; +input wren; +output [31:0] q; + + +wire const_zero; +wire [31:0] const_zero_data; +wire [31:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 32'b00000000000000000000000000000000; +assign dont_care_out = 32'b00000000000000000000000000000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + module dual (clk, data, rdaddress, wraddress , wren, q); + +// 36bit wide +// 16bit address + +input clk; +input[35:0] data; +input [15:0] rdaddress; +input [15:0] wraddress; +input wren; +output [35:0] q; + + +wire const_zero; +wire [35:0] const_zero_data; +wire [35:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 36'b000000000000000000000000000000000000; +assign dont_care_out = 36'b000000000000000000000000000000000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + module dual2 (clk, data, rdaddress, wraddress , wren, q); + +// 18bit wide +// 16bit address + +input clk; +input[17:0] data; +input [15:0] rdaddress; +input [15:0] wraddress; +input wren; +output [17:0] q; + + +wire const_zero; +wire [17:0] const_zero_data; +wire [17:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 18'b000000000000000000; +assign dont_care_out = 18'b000000000000000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + module dual3 (clk, data, rdaddress, wraddress , wren, q); + +// 8bit wide +// 16bit address + +input clk; +input[7:0] data; +input [15:0] rdaddress; +input [15:0] wraddress; +input wren; +output [7:0] q; + + +wire const_zero; +wire [7:0] const_zero_data; +wire [7:0] dont_care_out; + +assign const_zero = 1'b0; +assign const_zero_data = 8'b00000000; +assign dont_care_out = 8'b00000000; + +dual_port_ram dpram1( + .clk (clk), + .we1(wren), + .we2(const_zero), + .data1(data), + .data2(const_zero_data), + .out1(dont_care_out), + .out2 (q), + .addr1(wraddress), + .addr2(rdaddress)); + + + endmodule + + + + // Photon Calculator +// Note: Use the same random number for fresnel (reflect) as for scatterer because they are mutually exclusive blocks +// Also scatterer needs two + + +module PhotonCalculator ( + clock, reset, enable, + + // CONSTANTS + total_photons, + + randseed1, randseed2, randseed3, randseed4, randseed5, + + initialWeight, + + // Mover + OneOver_MutMaxrad_0, OneOver_MutMaxrad_1, OneOver_MutMaxrad_2, OneOver_MutMaxrad_3, OneOver_MutMaxrad_4, OneOver_MutMaxrad_5, + OneOver_MutMaxdep_0, OneOver_MutMaxdep_1, OneOver_MutMaxdep_2, OneOver_MutMaxdep_3, OneOver_MutMaxdep_4, OneOver_MutMaxdep_5, + OneOver_Mut_0, OneOver_Mut_1, OneOver_Mut_2, OneOver_Mut_3, OneOver_Mut_4, OneOver_Mut_5, + + // BoundaryChecker + z1_0, z1_1, z1_2, z1_3, z1_4, z1_5, + z0_0, z0_1, z0_2, z0_3, z0_4, z0_5, + mut_0, mut_1, mut_2, mut_3, mut_4, mut_5, + maxDepth_over_maxRadius, + + // Hop (no constants) + + // Scatterer Reflector Wrapper + down_niOverNt_1, down_niOverNt_2, down_niOverNt_3, down_niOverNt_4, down_niOverNt_5, + up_niOverNt_1, up_niOverNt_2, up_niOverNt_3, up_niOverNt_4, up_niOverNt_5, + down_niOverNt_2_1, down_niOverNt_2_2, down_niOverNt_2_3, down_niOverNt_2_4, down_niOverNt_2_5, + up_niOverNt_2_1, up_niOverNt_2_2, up_niOverNt_2_3, up_niOverNt_2_4, up_niOverNt_2_5, + downCritAngle_0, downCritAngle_1, downCritAngle_2, downCritAngle_3, downCritAngle_4, + upCritAngle_0, upCritAngle_1, upCritAngle_2, upCritAngle_3, upCritAngle_4, + muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5, + // Interface to memory look-up + // From Memories + up_rFresnel, down_rFresnel, sint, cost, + // To Memories + tindex, fresIndex, + + // Roulette (no Constants) + + // Absorber + absorb_data, absorb_rdaddress, absorb_wraddress, + absorb_wren, absorb_q, + + // Done signal + done + ); +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter TRIG_WIDTH=10; +//parameter PIPELINE_DEPTH_UPPER_LIMIT = 256; +//parameter ABSORB_ADDR_WIDTH=16; +//parameter ABSORB_WORD_WIDTH=64; +//parameter WSCALE=1919999; + + +input clock, reset, enable; + +// CONSTANTS +input [`BIT_WIDTH-1:0] total_photons; + +input [`BIT_WIDTH-1:0] randseed1; +input [`BIT_WIDTH-1:0] randseed2; +input [`BIT_WIDTH-1:0] randseed3; +input [`BIT_WIDTH-1:0] randseed4; +input [`BIT_WIDTH-1:0] randseed5; + +input [`BIT_WIDTH-1:0] initialWeight; + +// Mover +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_0, OneOver_MutMaxrad_1, OneOver_MutMaxrad_2, OneOver_MutMaxrad_3, OneOver_MutMaxrad_4, OneOver_MutMaxrad_5; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_0, OneOver_MutMaxdep_1, OneOver_MutMaxdep_2, OneOver_MutMaxdep_3, OneOver_MutMaxdep_4, OneOver_MutMaxdep_5; +input [`BIT_WIDTH-1:0] OneOver_Mut_0, OneOver_Mut_1, OneOver_Mut_2, OneOver_Mut_3, OneOver_Mut_4, OneOver_Mut_5; + +// BoundaryChecker +input [`BIT_WIDTH-1:0] z1_0, z1_1, z1_2, z1_3, z1_4, z1_5; +input [`BIT_WIDTH-1:0] z0_0, z0_1, z0_2, z0_3, z0_4, z0_5; +input [`BIT_WIDTH-1:0] mut_0, mut_1, mut_2, mut_3, mut_4, mut_5; +input [`BIT_WIDTH-1:0] maxDepth_over_maxRadius; + +// Hop (no constants) + +// Scatterer Reflector Absorber Wrapper +input [`BIT_WIDTH-1:0] down_niOverNt_1, down_niOverNt_2, down_niOverNt_3, down_niOverNt_4, down_niOverNt_5; +input [`BIT_WIDTH-1:0] up_niOverNt_1, up_niOverNt_2, up_niOverNt_3, up_niOverNt_4, up_niOverNt_5; +input [2*`BIT_WIDTH-1:0] down_niOverNt_2_1, down_niOverNt_2_2, down_niOverNt_2_3, down_niOverNt_2_4, down_niOverNt_2_5; +input [2*`BIT_WIDTH-1:0] up_niOverNt_2_1, up_niOverNt_2_2, up_niOverNt_2_3, up_niOverNt_2_4, up_niOverNt_2_5; +input [`BIT_WIDTH-1:0] downCritAngle_0, downCritAngle_1, downCritAngle_2, downCritAngle_3, downCritAngle_4; +input [`BIT_WIDTH-1:0] upCritAngle_0, upCritAngle_1, upCritAngle_2, upCritAngle_3, upCritAngle_4; +input [`BIT_WIDTH-1:0] muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5; + + // Memory look-up interface +input [`BIT_WIDTH-1:0] up_rFresnel; +input [`BIT_WIDTH-1:0] down_rFresnel; +input [`BIT_WIDTH-1:0] sint; +input [`BIT_WIDTH-1:0] cost; + //To Memories +output [12:0] tindex; +output [9:0] fresIndex; + +// Roulette Module (nothing) + +// Final results +output [`ABSORB_ADDR_WIDTH-1:0] absorb_rdaddress, absorb_wraddress; +output absorb_wren; +output [`ABSORB_WORD_WIDTH-1:0] absorb_data; +input [`ABSORB_WORD_WIDTH-1:0] absorb_q; + +// Flag when final results ready +output done; + + +// Local variables +// Wired nets +/*mover inputs*/ +reg [`BIT_WIDTH-1:0] x_moverMux; +reg [`BIT_WIDTH-1:0] y_moverMux; +reg [`BIT_WIDTH-1:0] z_moverMux; +reg [`BIT_WIDTH-1:0] ux_moverMux; +reg [`BIT_WIDTH-1:0] uy_moverMux; +reg [`BIT_WIDTH-1:0] uz_moverMux; +reg [`BIT_WIDTH-1:0] sz_moverMux; +reg [`BIT_WIDTH-1:0] sr_moverMux; +reg [`BIT_WIDTH-1:0] sleftz_moverMux; +reg [`BIT_WIDTH-1:0] sleftr_moverMux; +reg [`LAYER_WIDTH-1:0] layer_moverMux; +reg [`BIT_WIDTH-1:0] weight_moverMux; +reg dead_moverMux; + +/*mover outputs*/ +wire [`BIT_WIDTH-1:0] x_mover; +wire [`BIT_WIDTH-1:0] y_mover; +wire [`BIT_WIDTH-1:0] z_mover; +wire [`BIT_WIDTH-1:0] ux_mover; +wire [`BIT_WIDTH-1:0] uy_mover; +wire [`BIT_WIDTH-1:0] uz_mover; +wire [`BIT_WIDTH-1:0] sz_mover; +wire [`BIT_WIDTH-1:0] sr_mover; +wire [`BIT_WIDTH-1:0] sleftz_mover; +wire [`BIT_WIDTH-1:0] sleftr_mover; +wire [`LAYER_WIDTH-1:0] layer_mover; +wire [`BIT_WIDTH-1:0] weight_mover; +wire dead_mover; + +/*boundary checker outputs*/ +wire [`BIT_WIDTH-1:0] x_boundaryChecker; +wire [`BIT_WIDTH-1:0] y_boundaryChecker; +wire [`BIT_WIDTH-1:0] z_boundaryChecker; +wire [`BIT_WIDTH-1:0] ux_boundaryChecker; +wire [`BIT_WIDTH-1:0] uy_boundaryChecker; +wire [`BIT_WIDTH-1:0] uz_boundaryChecker; +wire [`BIT_WIDTH-1:0] sz_boundaryChecker; +wire [`BIT_WIDTH-1:0] sr_boundaryChecker; +wire [`BIT_WIDTH-1:0] sleftz_boundaryChecker; +wire [`BIT_WIDTH-1:0] sleftr_boundaryChecker; +wire [`LAYER_WIDTH-1:0] layer_boundaryChecker; +wire [`BIT_WIDTH-1:0] weight_boundaryChecker; +wire dead_boundaryChecker; +wire hit_boundaryChecker; + +/*hop outputs*/ +wire [`BIT_WIDTH-1:0] x_hop; +wire [`BIT_WIDTH-1:0] y_hop; +wire [`BIT_WIDTH-1:0] z_hop; +wire [`BIT_WIDTH-1:0] ux_hop; +wire [`BIT_WIDTH-1:0] uy_hop; +wire [`BIT_WIDTH-1:0] uz_hop; +wire [`BIT_WIDTH-1:0] sz_hop; +wire [`BIT_WIDTH-1:0] sr_hop; +wire [`BIT_WIDTH-1:0] sleftz_hop; +wire [`BIT_WIDTH-1:0] sleftr_hop; +wire [`LAYER_WIDTH-1:0] layer_hop; +wire [`BIT_WIDTH-1:0] weight_hop; +wire dead_hop; +wire hit_hop; + +/*Drop spin outputs*/ +wire [`BIT_WIDTH-1:0] x_dropSpin; +wire [`BIT_WIDTH-1:0] y_dropSpin; +wire [`BIT_WIDTH-1:0] z_dropSpin; +wire [`BIT_WIDTH-1:0] ux_dropSpin; +wire [`BIT_WIDTH-1:0] uy_dropSpin; +wire [`BIT_WIDTH-1:0] uz_dropSpin; +wire [`BIT_WIDTH-1:0] sz_dropSpin; +wire [`BIT_WIDTH-1:0] sr_dropSpin; +wire [`BIT_WIDTH-1:0] sleftz_dropSpin; +wire [`BIT_WIDTH-1:0] sleftr_dropSpin; +wire [`LAYER_WIDTH-1:0] layer_dropSpin; +wire [`BIT_WIDTH-1:0] weight_dropSpin; +wire dead_dropSpin; +//Had to add this one to avoid implicit net: +wire hit_dropSpin; + +/*Dead or Alive outputs*/ +wire [`BIT_WIDTH-1:0] x_Roulette; +wire [`BIT_WIDTH-1:0] y_Roulette; +wire [`BIT_WIDTH-1:0] z_Roulette; +wire [`BIT_WIDTH-1:0] ux_Roulette; +wire [`BIT_WIDTH-1:0] uy_Roulette; +wire [`BIT_WIDTH-1:0] uz_Roulette; +wire [`BIT_WIDTH-1:0] sz_Roulette; +wire [`BIT_WIDTH-1:0] sr_Roulette; +wire [`BIT_WIDTH-1:0] sleftz_Roulette; +wire [`BIT_WIDTH-1:0] sleftr_Roulette; +wire [`LAYER_WIDTH-1:0] layer_Roulette; +wire [`BIT_WIDTH-1:0] weight_Roulette; +wire dead_Roulette; + +// internals +wire [`BIT_WIDTH-1:0] rand1, rand2, rand3, rand4, rand5; +wire [`BIT_WIDTH-1:0] logrand; + +// Combinational Drivers +reg [`BIT_WIDTH-1:0] c_num_photons_left; +reg [`BIT_WIDTH-1:0] c_counter; +reg c_done; + +// Registered Drivers +reg r_done; +reg loadseed; +reg delay_loadseed; + + +reg [`BIT_WIDTH-1:0] r_num_photons_left; +reg [`BIT_WIDTH-1:0] r_counter; + +assign done = r_done; + +//Cannot be logic in instantiatino: +wire not_reset; +assign not_reset = ~reset; + +// Connect blocks +LogCalc log_u1(.clock(clock), .reset(reset), .enable(1'b1), .in_x(rand1), .log_x(logrand)); +rng rand_u1(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed1), .number_o(rand1)); +rng rand_u2(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed2), .number_o(rand2)); +rng rand_u3(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed3), .number_o(rand3)); +rng rand_u4(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed4), .number_o(rand4)); +rng rand_u5(.clk(clock), .en(1'b1), .resetn(not_reset), .loadseed_i(loadseed), .seed_i(randseed5), .number_o(rand5)); + +Move mover( .clock(clock), .reset(reset), .enable(enable), + .x_moverMux(x_moverMux), .y_moverMux(y_moverMux), .z_moverMux(z_moverMux), + .ux_moverMux(ux_moverMux), .uy_moverMux(uy_moverMux), .uz_moverMux(uz_moverMux), + .sz_moverMux(sz_moverMux), .sr_moverMux(sr_moverMux), + .sleftz_moverMux(sleftz_moverMux), .sleftr_moverMux(sleftr_moverMux), + .layer_moverMux(layer_moverMux), .weight_moverMux(weight_moverMux), .dead_moverMux(dead_moverMux), + + .log_rand_num(logrand), + + //OUTPUTS + .x_mover(x_mover), .y_mover(y_mover), .z_mover(z_mover), + .ux_mover(ux_mover), .uy_mover(uy_mover), .uz_mover(uz_mover), + .sz_mover(sz_mover), .sr_mover(sr_mover), + .sleftz_mover(sleftz_mover), .sleftr_mover(sleftr_mover), + .layer_mover(layer_mover), .weight_mover(weight_mover), .dead_mover(dead_mover), + + // CONSTANTS + .OneOver_MutMaxrad_0(OneOver_MutMaxrad_0), .OneOver_MutMaxrad_1(OneOver_MutMaxrad_1), .OneOver_MutMaxrad_2(OneOver_MutMaxrad_2), .OneOver_MutMaxrad_3(OneOver_MutMaxrad_3), .OneOver_MutMaxrad_4(OneOver_MutMaxrad_4), .OneOver_MutMaxrad_5(OneOver_MutMaxrad_5), + .OneOver_MutMaxdep_0(OneOver_MutMaxdep_0), .OneOver_MutMaxdep_1(OneOver_MutMaxdep_1), .OneOver_MutMaxdep_2(OneOver_MutMaxdep_2), .OneOver_MutMaxdep_3(OneOver_MutMaxdep_3), .OneOver_MutMaxdep_4(OneOver_MutMaxdep_4), .OneOver_MutMaxdep_5(OneOver_MutMaxdep_5), + .OneOver_Mut_0(OneOver_Mut_0), .OneOver_Mut_1(OneOver_Mut_1), .OneOver_Mut_2(OneOver_Mut_2), .OneOver_Mut_3(OneOver_Mut_3), .OneOver_Mut_4(OneOver_Mut_4), .OneOver_Mut_5(OneOver_Mut_5) + ); + +Boundary boundaryChecker ( //INPUTS + .clock(clock), .reset(reset), .enable(enable), + .x_mover(x_mover), .y_mover(y_mover), .z_mover(z_mover), + .ux_mover(ux_mover), .uy_mover(uy_mover), .uz_mover(uz_mover), + .sz_mover(sz_mover), .sr_mover(sr_mover), + .sleftz_mover(sleftz_mover), .sleftr_mover(sleftr_mover), + .layer_mover(layer_mover), .weight_mover(weight_mover), .dead_mover(dead_mover), + + //OUTPUTS + .x_boundaryChecker(x_boundaryChecker), .y_boundaryChecker(y_boundaryChecker), .z_boundaryChecker(z_boundaryChecker), + .ux_boundaryChecker(ux_boundaryChecker), .uy_boundaryChecker(uy_boundaryChecker), .uz_boundaryChecker(uz_boundaryChecker), + .sz_boundaryChecker(sz_boundaryChecker), .sr_boundaryChecker(sr_boundaryChecker), + .sleftz_boundaryChecker(sleftz_boundaryChecker), .sleftr_boundaryChecker(sleftr_boundaryChecker), + .layer_boundaryChecker(layer_boundaryChecker), .weight_boundaryChecker(weight_boundaryChecker), .dead_boundaryChecker(dead_boundaryChecker), .hit_boundaryChecker(hit_boundaryChecker), + + //CONSTANTS + .z1_0(z1_0), .z1_1(z1_1), .z1_2(z1_2), .z1_3(z1_3), .z1_4(z1_4), .z1_5(z1_5), + .z0_0(z0_0), .z0_1(z0_1), .z0_2(z0_2), .z0_3(z0_3), .z0_4(z0_4), .z0_5(z0_5), + .mut_0(mut_0), .mut_1(mut_1), .mut_2(mut_2), .mut_3(mut_3), .mut_4(mut_4), .mut_5(mut_5), + .maxDepth_over_maxRadius(maxDepth_over_maxRadius) + ); + +Hop hopper ( //INPUTS + .clock(clock), .reset(reset), .enable(enable), + .x_boundaryChecker(x_boundaryChecker), .y_boundaryChecker(y_boundaryChecker), .z_boundaryChecker(z_boundaryChecker), + .ux_boundaryChecker(ux_boundaryChecker), .uy_boundaryChecker(uy_boundaryChecker), .uz_boundaryChecker(uz_boundaryChecker), + .sz_boundaryChecker(sz_boundaryChecker), .sr_boundaryChecker(sr_boundaryChecker), + .sleftz_boundaryChecker(sleftz_boundaryChecker), .sleftr_boundaryChecker(sleftr_boundaryChecker), + .layer_boundaryChecker(layer_boundaryChecker), .weight_boundaryChecker(weight_boundaryChecker), .dead_boundaryChecker(dead_boundaryChecker), + .hit_boundaryChecker(hit_boundaryChecker), + + //OUTPUTS + .x_hop(x_hop), .y_hop(y_hop), .z_hop(z_hop), + .ux_hop(ux_hop), .uy_hop(uy_hop), .uz_hop(uz_hop), + .sz_hop(sz_hop), .sr_hop(sr_hop), + .sleftz_hop(sleftz_hop), .sleftr_hop(sleftr_hop), + .layer_hop(layer_hop), .weight_hop(weight_hop), .dead_hop(dead_hop), .hit_hop(hit_hop) + ); + +Roulette Roulette ( //INPUTS + .clock(clock), .reset(reset), .enable(enable), + .x_RouletteMux(x_dropSpin), .y_RouletteMux(y_dropSpin), .z_RouletteMux(z_dropSpin), + .ux_RouletteMux(ux_dropSpin), .uy_RouletteMux(uy_dropSpin), .uz_RouletteMux(uz_dropSpin), + .sz_RouletteMux(sz_dropSpin), .sr_RouletteMux(sr_dropSpin), + .sleftz_RouletteMux(sleftz_dropSpin), .sleftr_RouletteMux(sleftr_dropSpin), + .layer_RouletteMux(layer_dropSpin), .weight_absorber(weight_dropSpin), .dead_RouletteMux(dead_dropSpin), + .randnumber(rand4), + + //OUTPUTS + .x_Roulette(x_Roulette), .y_Roulette(y_Roulette), .z_Roulette(z_Roulette), + .ux_Roulette(ux_Roulette), .uy_Roulette(uy_Roulette), .uz_Roulette(uz_Roulette), + .sz_Roulette(sz_Roulette), .sr_Roulette(sr_Roulette), + .sleftz_Roulette(sleftz_Roulette), .sleftr_Roulette(sleftr_Roulette), + .layer_Roulette(layer_Roulette), .weight_Roulette(weight_Roulette), .dead_Roulette(dead_Roulette) + ); + + +DropSpinWrapper dropSpin ( + .clock(clock), .reset(reset), .enable(enable), + + //From Hopper Module + .i_x(x_hop), + .i_y(y_hop), + .i_z(z_hop), + .i_ux(ux_hop), + .i_uy(uy_hop), + .i_uz(uz_hop), + .i_sz(sz_hop), + .i_sr(sr_hop), + .i_sleftz(sleftz_hop), + .i_sleftr(sleftr_hop), + .i_weight(weight_hop), + .i_layer(layer_hop), + .i_dead(dead_hop), + .i_hit(hit_hop), + + //From System Register File (5 layers)- Absorber + .muaFraction1(muaFraction1), .muaFraction2(muaFraction2), .muaFraction3(muaFraction3), .muaFraction4(muaFraction4), .muaFraction5(muaFraction5), + + //From System Register File - ScattererReflector + .down_niOverNt_1(down_niOverNt_1), + .down_niOverNt_2(down_niOverNt_2), + .down_niOverNt_3(down_niOverNt_3), + .down_niOverNt_4(down_niOverNt_4), + .down_niOverNt_5(down_niOverNt_5), + .up_niOverNt_1(up_niOverNt_1), + .up_niOverNt_2(up_niOverNt_2), + .up_niOverNt_3(up_niOverNt_3), + .up_niOverNt_4(up_niOverNt_4), + .up_niOverNt_5(up_niOverNt_5), + .down_niOverNt_2_1(down_niOverNt_2_1), + .down_niOverNt_2_2(down_niOverNt_2_2), + .down_niOverNt_2_3(down_niOverNt_2_3), + .down_niOverNt_2_4(down_niOverNt_2_4), + .down_niOverNt_2_5(down_niOverNt_2_5), + .up_niOverNt_2_1(up_niOverNt_2_1), + .up_niOverNt_2_2(up_niOverNt_2_2), + .up_niOverNt_2_3(up_niOverNt_2_3), + .up_niOverNt_2_4(up_niOverNt_2_4), + .up_niOverNt_2_5(up_niOverNt_2_5), + .downCritAngle_0(downCritAngle_0), + .downCritAngle_1(downCritAngle_1), + .downCritAngle_2(downCritAngle_2), + .downCritAngle_3(downCritAngle_3), + .downCritAngle_4(downCritAngle_4), + .upCritAngle_0(upCritAngle_0), + .upCritAngle_1(upCritAngle_1), + .upCritAngle_2(upCritAngle_2), + .upCritAngle_3(upCritAngle_3), + .upCritAngle_4(upCritAngle_4), + + // port to memory + .data(absorb_data), .rdaddress(absorb_rdaddress), .wraddress(absorb_wraddress), + .wren(absorb_wren), .q(absorb_q), + + //Generated by random number generators controlled by skeleton + .up_rFresnel(up_rFresnel), + .down_rFresnel(down_rFresnel), + .sint(sint), + .cost(cost), + .rand2(rand2), + .rand3(rand3), + .rand5(rand5), + //To Memories + .tindex(tindex), + .fresIndex(fresIndex), + + + + //To Roulette Module + .o_x(x_dropSpin), + .o_y(y_dropSpin), + .o_z(z_dropSpin), + .o_ux(ux_dropSpin), + .o_uy(uy_dropSpin), + .o_uz(uz_dropSpin), + .o_sz(sz_dropSpin), + .o_sr(sr_dropSpin), + .o_sleftz(sleftz_dropSpin), + .o_sleftr(sleftr_dropSpin), + .o_weight(weight_dropSpin), + .o_layer(layer_dropSpin), + .o_dead(dead_dropSpin), + .o_hit(hit_dropSpin) + + ); + +// Determine how many photons left +always @(r_num_photons_left or dead_Roulette or r_done or r_counter) +begin + //c_num_photons_left = r_num_photons_left; + //c_counter = 0; + + if(dead_Roulette == 1'b1 && r_done == 1'b0) + begin + if(r_num_photons_left > 0) + begin + c_num_photons_left = r_num_photons_left - 1; + c_counter = 0; + end + else + begin + c_counter = r_counter + 1; + c_num_photons_left = r_num_photons_left; + end + end + else + begin + c_num_photons_left = r_num_photons_left; + c_counter = 0; + end +end + +// Only state info is done +always @(r_done or r_counter) +begin + //c_done = r_done; + if(r_counter > `PIPELINE_DEPTH_UPPER_LIMIT) + begin + c_done = 1'b1; + end else begin + c_done = r_done; + end +end + +// Create mux to mover +always @(dead_Roulette or initialWeight or r_num_photons_left or x_Roulette or y_Roulette or z_Roulette or + ux_Roulette or uy_Roulette or uz_Roulette or sz_Roulette or sr_Roulette or sleftz_Roulette or + sleftr_Roulette or layer_Roulette or weight_Roulette or dead_Roulette) +begin + if(dead_Roulette) + begin + x_moverMux = 0; + y_moverMux = 0; + z_moverMux = 0; + ux_moverMux = 0; + uy_moverMux = 0; + uz_moverMux = 32'h7fffffff; + sz_moverMux = 0; + sr_moverMux = 0; + sleftz_moverMux = 0; + sleftr_moverMux = 0; + layer_moverMux = 3'b01; + weight_moverMux = initialWeight; + if(r_num_photons_left > 0) + begin + dead_moverMux = 1'b0; + end + else + begin + dead_moverMux = 1'b1; + end + end + else + begin + x_moverMux = x_Roulette; + y_moverMux = y_Roulette; + z_moverMux = z_Roulette; + ux_moverMux = ux_Roulette; + uy_moverMux = uy_Roulette; + uz_moverMux = uz_Roulette; + sz_moverMux = sz_Roulette; + sr_moverMux = sr_Roulette; + sleftz_moverMux = sleftz_Roulette; + sleftr_moverMux = sleftr_Roulette; + layer_moverMux = layer_Roulette; + weight_moverMux = weight_Roulette; + dead_moverMux = dead_Roulette; + end +end + +// register state +always @(posedge clock) +begin + if(reset) + begin + r_num_photons_left <= total_photons; + r_counter <= 1'b0; + r_done <= 1'b0; + delay_loadseed <= 1'b1; + loadseed <= 1'b1; + end + else + begin + if(enable) + begin + r_num_photons_left <= c_num_photons_left; + r_counter <= c_counter; + r_done <= c_done; + delay_loadseed <= 1'b0; + loadseed <= delay_loadseed; + end + end +end +endmodule + + +module Move( //INPUTS + clock, reset, enable, + x_moverMux, y_moverMux, z_moverMux, + ux_moverMux, uy_moverMux, uz_moverMux, + sz_moverMux, sr_moverMux, + sleftz_moverMux, sleftr_moverMux, + layer_moverMux, weight_moverMux, dead_moverMux, + + log_rand_num, + + //OUTPUTS + x_mover, y_mover, z_mover, + ux_mover, uy_mover, uz_mover, + sz_mover, sr_mover, + sleftz_mover, sleftr_mover, + layer_mover, weight_mover, dead_mover, + + // CONSTANTS + OneOver_MutMaxrad_0, OneOver_MutMaxrad_1, OneOver_MutMaxrad_2, OneOver_MutMaxrad_3, OneOver_MutMaxrad_4, OneOver_MutMaxrad_5, + OneOver_MutMaxdep_0, OneOver_MutMaxdep_1, OneOver_MutMaxdep_2, OneOver_MutMaxdep_3, OneOver_MutMaxdep_4, OneOver_MutMaxdep_5, + OneOver_Mut_0, OneOver_Mut_1, OneOver_Mut_2, OneOver_Mut_3, OneOver_Mut_4, OneOver_Mut_5 + ); + + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_moverMux; +input [`BIT_WIDTH-1:0] y_moverMux; +input [`BIT_WIDTH-1:0] z_moverMux; +input [`BIT_WIDTH-1:0] ux_moverMux; +input [`BIT_WIDTH-1:0] uy_moverMux; +input [`BIT_WIDTH-1:0] uz_moverMux; +input [`BIT_WIDTH-1:0] sz_moverMux; +input [`BIT_WIDTH-1:0] sr_moverMux; +input [`BIT_WIDTH-1:0] sleftz_moverMux; +input [`BIT_WIDTH-1:0] sleftr_moverMux; +input [`LAYER_WIDTH-1:0] layer_moverMux; +input [`BIT_WIDTH-1:0] weight_moverMux; +input dead_moverMux; + +output [`BIT_WIDTH-1:0] x_mover; +output [`BIT_WIDTH-1:0] y_mover; +output [`BIT_WIDTH-1:0] z_mover; +output [`BIT_WIDTH-1:0] ux_mover; +output [`BIT_WIDTH-1:0] uy_mover; +output [`BIT_WIDTH-1:0] uz_mover; +output [`BIT_WIDTH-1:0] sz_mover; +output [`BIT_WIDTH-1:0] sr_mover; +output [`BIT_WIDTH-1:0] sleftz_mover; +output [`BIT_WIDTH-1:0] sleftr_mover; +output [`LAYER_WIDTH-1:0]layer_mover; +output [`BIT_WIDTH-1:0] weight_mover; +output dead_mover; + + +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_0; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_1; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_2; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_3; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_4; +input [`BIT_WIDTH-1:0] OneOver_MutMaxrad_5; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_0; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_1; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_2; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_3; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_4; +input [`BIT_WIDTH-1:0] OneOver_MutMaxdep_5; +input [`BIT_WIDTH-1:0] OneOver_Mut_0; +input [`BIT_WIDTH-1:0] OneOver_Mut_1; +input [`BIT_WIDTH-1:0] OneOver_Mut_2; +input [`BIT_WIDTH-1:0] OneOver_Mut_3; +input [`BIT_WIDTH-1:0] OneOver_Mut_4; +input [`BIT_WIDTH-1:0] OneOver_Mut_5; +input [`BIT_WIDTH-1:0] log_rand_num; + +//------------Local Variables------------------------ +reg [`BIT_WIDTH-1:0] c_sr; +reg [`BIT_WIDTH-1:0] c_sz; +reg [2*`BIT_WIDTH-1:0] c_sr_big; +reg [2*`BIT_WIDTH-1:0] c_sz_big; +reg [`BIT_WIDTH-1:0] c_sleftr; +reg [`BIT_WIDTH-1:0] c_sleftz; + +//No signed regs, unsigned unecessary +//reg unsigned [`BIT_WIDTH-1:0] c_r_op0; +//reg unsigned [`BIT_WIDTH-1:0] c_r_op1; +//reg unsigned [`BIT_WIDTH-1:0] c_z_op0; +//reg unsigned [`BIT_WIDTH-1:0] c_z_op1; + +reg [`BIT_WIDTH-1:0] c_r_op0; +reg [`BIT_WIDTH-1:0] c_r_op1; +reg [`BIT_WIDTH-1:0] c_z_op0; +reg [`BIT_WIDTH-1:0] c_z_op1; + +// grab multiplexed constant +reg [`BIT_WIDTH-1:0] OneOver_MutMaxrad; +reg [`BIT_WIDTH-1:0] OneOver_MutMaxdep; +reg [`BIT_WIDTH-1:0] OneOver_Mut; + +//------------REGISTERED Values------------------------ +reg [`BIT_WIDTH-1:0] x_mover; +reg [`BIT_WIDTH-1:0] y_mover; +reg [`BIT_WIDTH-1:0] z_mover; +reg [`BIT_WIDTH-1:0] ux_mover; +reg [`BIT_WIDTH-1:0] uy_mover; +reg [`BIT_WIDTH-1:0] uz_mover; +reg [`BIT_WIDTH-1:0] sz_mover; +reg [`BIT_WIDTH-1:0] sr_mover; +reg [`BIT_WIDTH-1:0] sleftz_mover; +reg [`BIT_WIDTH-1:0] sleftr_mover; +reg [`LAYER_WIDTH-1:0]layer_mover; +reg [`BIT_WIDTH-1:0] weight_mover; +reg dead_mover; + + +//Need this to deal with 'unused' inputs for ODIN II +wire bigOr; +assign bigOr = sr_moverMux[0] | sr_moverMux[1] | sr_moverMux[2] | sr_moverMux[3] | sr_moverMux[4] | sr_moverMux[5] | + sr_moverMux[6] | sr_moverMux[7] | sr_moverMux[8] | sr_moverMux[9] | sr_moverMux[10] | sr_moverMux[11] | + sr_moverMux[12] | sr_moverMux[13] | sr_moverMux[14] | sr_moverMux[15] | sr_moverMux[16] | sr_moverMux[17] | + sr_moverMux[18] | sr_moverMux[19] | sr_moverMux[20] | sr_moverMux[21] | sr_moverMux[22] | sr_moverMux[23] | + sr_moverMux[24] | sr_moverMux[25] | sr_moverMux[26] | sr_moverMux[27] | sr_moverMux[28] | sr_moverMux[29] | + sr_moverMux[30] | sr_moverMux[31] | + sz_moverMux[0] | sz_moverMux[1] | sz_moverMux[2] | sz_moverMux[3] | sz_moverMux[4] | sz_moverMux[5] | + sz_moverMux[6] | sz_moverMux[7] | sz_moverMux[8] | sz_moverMux[9] | sz_moverMux[10] | sz_moverMux[11] | + sz_moverMux[12] | sz_moverMux[13] | sz_moverMux[14] | sz_moverMux[15] | sz_moverMux[16] | sz_moverMux[17] | + sz_moverMux[18] | sz_moverMux[19] | sz_moverMux[20] | sz_moverMux[21] | sz_moverMux[22] | sz_moverMux[23] | + sz_moverMux[24] | sz_moverMux[25] | sz_moverMux[26] | sz_moverMux[27] | sz_moverMux[28] | sz_moverMux[29] | + sz_moverMux[30] | sz_moverMux[31] | + 1'b1; +wire reset_new; +assign reset_new = reset & bigOr; + +// multiplex constants +always @(layer_moverMux or OneOver_MutMaxrad_0 or OneOver_MutMaxdep_0 or OneOver_Mut_0 or + OneOver_MutMaxrad_1 or OneOver_MutMaxdep_1 or OneOver_Mut_1 or + OneOver_MutMaxrad_2 or OneOver_MutMaxdep_2 or OneOver_Mut_2 or + OneOver_MutMaxrad_3 or OneOver_MutMaxdep_3 or OneOver_Mut_3 or + OneOver_MutMaxrad_4 or OneOver_MutMaxdep_4 or OneOver_Mut_4 or + OneOver_MutMaxrad_5 or OneOver_MutMaxdep_5 or OneOver_Mut_5) +begin +case(layer_moverMux) + 3'b000: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_0; + OneOver_MutMaxdep = OneOver_MutMaxdep_0; + OneOver_Mut = OneOver_Mut_0; + end + 3'b001: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_1; + OneOver_MutMaxdep = OneOver_MutMaxdep_1; + OneOver_Mut = OneOver_Mut_1; + end + 3'b010: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_2; + OneOver_MutMaxdep = OneOver_MutMaxdep_2; + OneOver_Mut = OneOver_Mut_2; + end + 3'b011: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_3; + OneOver_MutMaxdep = OneOver_MutMaxdep_3; + OneOver_Mut = OneOver_Mut_3; + end + 3'b100: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_4; + OneOver_MutMaxdep = OneOver_MutMaxdep_4; + OneOver_Mut = OneOver_Mut_4; + end + 3'b101: + begin + OneOver_MutMaxrad = OneOver_MutMaxrad_5; + OneOver_MutMaxdep = OneOver_MutMaxdep_5; + OneOver_Mut = OneOver_Mut_5; + end + default: + begin + OneOver_MutMaxrad = 0; + OneOver_MutMaxdep = 0; + OneOver_Mut = 0; + end +endcase +end + +// Determine move value +always @(sleftz_moverMux or log_rand_num or OneOver_MutMaxrad or OneOver_MutMaxdep or sleftr_moverMux or + OneOver_Mut) +begin + // Resource sharing for multipliers + if(sleftz_moverMux == 32'b0) + begin + c_r_op0 = `MAXLOG - log_rand_num; + c_r_op1 = OneOver_MutMaxrad; + c_z_op0 = `MAXLOG - log_rand_num; + c_z_op1 = OneOver_MutMaxdep; + end + else + begin + c_r_op0 = sleftr_moverMux; + c_r_op1 = OneOver_Mut; + c_z_op0 = sleftz_moverMux; + c_z_op1 = OneOver_Mut; + end +end + +// Determine move value +always @(sleftz_moverMux or c_r_op0 or c_r_op1 or c_z_op0 or c_z_op1 or sleftr_moverMux) +begin + c_sr_big = c_r_op0 * c_r_op1; + c_sz_big = c_z_op0 * c_z_op1; + if(sleftz_moverMux == 32'b0) + begin + c_sr = c_sr_big[2*`BIT_WIDTH - `LOGSCALEFACTOR - 1:`BIT_WIDTH - `LOGSCALEFACTOR]; + c_sz = c_sz_big[2*`BIT_WIDTH - `LOGSCALEFACTOR - 1:`BIT_WIDTH - `LOGSCALEFACTOR]; + + c_sleftr = sleftr_moverMux; + c_sleftz = 0; + + //c_sr = `CONST_MOVE_AMOUNT; + //c_sz = `CONST_MOVE_AMOUNT; + end + else + begin + c_sr = c_sr_big[2*`BIT_WIDTH - `MUTMAX_BITS - 1 - 1:`BIT_WIDTH - `MUTMAX_BITS - 1]; + c_sz = c_sz_big[2*`BIT_WIDTH - `MUTMAX_BITS - 1 - 1:`BIT_WIDTH - `MUTMAX_BITS - 1]; + + c_sleftz = 0; + c_sleftr = 0; + end +end + +// latch values +always @ (posedge clock) +begin + if (reset_new) + begin + // Photon variables + x_mover <= 0; + y_mover <= 0; + z_mover <= 0; + ux_mover <= 0; + uy_mover <= 0; + uz_mover <= 0; + sz_mover <= 0; + sr_mover <= 0; + sleftz_mover <= 0; + sleftr_mover <= 0; + layer_mover <= 0; + weight_mover <= 0; + dead_mover <= 1'b1; + end + else + begin + if(enable) + begin + // Photon variables + x_mover <= x_moverMux; + y_mover <= y_moverMux; + z_mover <= z_moverMux; + ux_mover <= ux_moverMux; + uy_mover <= uy_moverMux; + uz_mover <= uz_moverMux; + layer_mover <= layer_moverMux; + weight_mover <= weight_moverMux; + dead_mover <= dead_moverMux; + + sz_mover <= c_sz; + sr_mover <= c_sr; + sleftz_mover <= c_sleftz; + sleftr_mover <= c_sleftr; + end + end +end + +endmodule + + +module Boundary ( //INPUTS + clock, reset, enable, + x_mover, y_mover, z_mover, + ux_mover, uy_mover, uz_mover, + sz_mover, sr_mover, + sleftz_mover, sleftr_mover, + layer_mover, weight_mover, dead_mover, + + //OUTPUTS + x_boundaryChecker, y_boundaryChecker, z_boundaryChecker, + ux_boundaryChecker, uy_boundaryChecker, uz_boundaryChecker, + sz_boundaryChecker, sr_boundaryChecker, + sleftz_boundaryChecker, sleftr_boundaryChecker, + layer_boundaryChecker, weight_boundaryChecker, dead_boundaryChecker, hit_boundaryChecker, + + //CONSTANTS + z1_0, z1_1, z1_2, z1_3, z1_4, z1_5, + z0_0, z0_1, z0_2, z0_3, z0_4, z0_5, + mut_0, mut_1, mut_2, mut_3, mut_4, mut_5, + maxDepth_over_maxRadius + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter INTMAX=2147483647; +//parameter INTMIN=-2147483648; +//parameter DIVIDER_LATENCY=30; +//parameter FINAL_LATENCY=28; +//parameter MULT_LATENCY=1; +//parameter ASPECT_RATIO = 7; +//parameter TOTAL_LATENCY = `DIVIDER_LATENCY + `FINAL_LATENCY + `MULT_LATENCY + `MULT_LATENCY; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_mover; +input [`BIT_WIDTH-1:0] y_mover; +input [`BIT_WIDTH-1:0] z_mover; +input [`BIT_WIDTH-1:0] ux_mover; +input [`BIT_WIDTH-1:0] uy_mover; +input [`BIT_WIDTH-1:0] uz_mover; +input [`BIT_WIDTH-1:0] sz_mover; +input [`BIT_WIDTH-1:0] sr_mover; +input [`BIT_WIDTH-1:0] sleftz_mover; +input [`BIT_WIDTH-1:0] sleftr_mover; +input [`LAYER_WIDTH-1:0] layer_mover; +input [`BIT_WIDTH-1:0] weight_mover; +input dead_mover; + +output [`BIT_WIDTH-1:0] x_boundaryChecker; +output [`BIT_WIDTH-1:0] y_boundaryChecker; +output [`BIT_WIDTH-1:0] z_boundaryChecker; +output [`BIT_WIDTH-1:0] ux_boundaryChecker; +output [`BIT_WIDTH-1:0] uy_boundaryChecker; +output [`BIT_WIDTH-1:0] uz_boundaryChecker; +output [`BIT_WIDTH-1:0] sz_boundaryChecker; +output [`BIT_WIDTH-1:0] sr_boundaryChecker; +output [`BIT_WIDTH-1:0] sleftz_boundaryChecker; +output [`BIT_WIDTH-1:0] sleftr_boundaryChecker; +output [`LAYER_WIDTH-1:0]layer_boundaryChecker; +output [`BIT_WIDTH-1:0] weight_boundaryChecker; +output dead_boundaryChecker; +output hit_boundaryChecker; + +// Constants +input [`BIT_WIDTH-1:0] z1_0; +input [`BIT_WIDTH-1:0] z1_1; +input [`BIT_WIDTH-1:0] z1_2; +input [`BIT_WIDTH-1:0] z1_3; +input [`BIT_WIDTH-1:0] z1_4; +input [`BIT_WIDTH-1:0] z1_5; +input [`BIT_WIDTH-1:0] z0_0; +input [`BIT_WIDTH-1:0] z0_1; +input [`BIT_WIDTH-1:0] z0_2; +input [`BIT_WIDTH-1:0] z0_3; +input [`BIT_WIDTH-1:0] z0_4; +input [`BIT_WIDTH-1:0] z0_5; +input [`BIT_WIDTH-1:0] mut_0; +input [`BIT_WIDTH-1:0] mut_1; +input [`BIT_WIDTH-1:0] mut_2; +input [`BIT_WIDTH-1:0] mut_3; +input [`BIT_WIDTH-1:0] mut_4; +input [`BIT_WIDTH-1:0] mut_5; +input [`BIT_WIDTH-1:0] maxDepth_over_maxRadius; + + +//WIRES FOR CONNECTING REGISTERS +//reg [BIT_WIDTH-1:0] c_x [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_y [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_z [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_ux [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_uy [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_uz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sleftz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_sleftr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_weight [TOTAL_LATENCY - 1:0]; +//reg [LAYER_WIDTH-1:0] c_layer [TOTAL_LATENCY - 1:0]; +//reg c_dead [TOTAL_LATENCY - 1:0]; +//reg c_hit [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_diff[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_dl_b[TOTAL_LATENCY - 1:0]; +//reg [2*BIT_WIDTH-1:0] c_numer[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_z1[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_z0[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] c_mut[TOTAL_LATENCY - 1:0]; + +//reg [BIT_WIDTH-1:0] r_x [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_y [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_z [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_ux [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_uy [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_uz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sleftz [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_sleftr [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_weight [TOTAL_LATENCY - 1:0]; +//reg [LAYER_WIDTH-1:0] r_layer [TOTAL_LATENCY - 1:0]; +//reg r_dead [TOTAL_LATENCY - 1:0]; +//reg r_hit [TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_diff[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_dl_b[TOTAL_LATENCY - 1:0]; +//reg [2*BIT_WIDTH-1:0] r_numer[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_z1[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_z0[TOTAL_LATENCY - 1:0]; +//reg [BIT_WIDTH-1:0] r_mut[TOTAL_LATENCY - 1:0]; + + +//EXPANDED FOR ODIN +//reg [BIT_WIDTH-1:0] c_x [TOTAL_LATENCY - 1:0]; +reg [`BIT_WIDTH-1:0] c_x__0; +reg [`BIT_WIDTH-1:0] c_x__1; +reg [`BIT_WIDTH-1:0] c_x__2; +reg [`BIT_WIDTH-1:0] c_x__3; +reg [`BIT_WIDTH-1:0] c_x__4; +reg [`BIT_WIDTH-1:0] c_x__5; +reg [`BIT_WIDTH-1:0] c_x__6; +reg [`BIT_WIDTH-1:0] c_x__7; +reg [`BIT_WIDTH-1:0] c_x__8; +reg [`BIT_WIDTH-1:0] c_x__9; +reg [`BIT_WIDTH-1:0] c_x__10; +reg [`BIT_WIDTH-1:0] c_x__11; +reg [`BIT_WIDTH-1:0] c_x__12; +reg [`BIT_WIDTH-1:0] c_x__13; +reg [`BIT_WIDTH-1:0] c_x__14; +reg [`BIT_WIDTH-1:0] c_x__15; +reg [`BIT_WIDTH-1:0] c_x__16; +reg [`BIT_WIDTH-1:0] c_x__17; +reg [`BIT_WIDTH-1:0] c_x__18; +reg [`BIT_WIDTH-1:0] c_x__19; +reg [`BIT_WIDTH-1:0] c_x__20; +reg [`BIT_WIDTH-1:0] c_x__21; +reg [`BIT_WIDTH-1:0] c_x__22; +reg [`BIT_WIDTH-1:0] c_x__23; +reg [`BIT_WIDTH-1:0] c_x__24; +reg [`BIT_WIDTH-1:0] c_x__25; +reg [`BIT_WIDTH-1:0] c_x__26; +reg [`BIT_WIDTH-1:0] c_x__27; +reg [`BIT_WIDTH-1:0] c_x__28; +reg [`BIT_WIDTH-1:0] c_x__29; +reg [`BIT_WIDTH-1:0] c_x__30; +reg [`BIT_WIDTH-1:0] c_x__31; +reg [`BIT_WIDTH-1:0] c_x__32; +reg [`BIT_WIDTH-1:0] c_x__33; +reg [`BIT_WIDTH-1:0] c_x__34; +reg [`BIT_WIDTH-1:0] c_x__35; +reg [`BIT_WIDTH-1:0] c_x__36; +reg [`BIT_WIDTH-1:0] c_x__37; +reg [`BIT_WIDTH-1:0] c_x__38; +reg [`BIT_WIDTH-1:0] c_x__39; +reg [`BIT_WIDTH-1:0] c_x__40; +reg [`BIT_WIDTH-1:0] c_x__41; +reg [`BIT_WIDTH-1:0] c_x__42; +reg [`BIT_WIDTH-1:0] c_x__43; +reg [`BIT_WIDTH-1:0] c_x__44; +reg [`BIT_WIDTH-1:0] c_x__45; +reg [`BIT_WIDTH-1:0] c_x__46; +reg [`BIT_WIDTH-1:0] c_x__47; +reg [`BIT_WIDTH-1:0] c_x__48; +reg [`BIT_WIDTH-1:0] c_x__49; +reg [`BIT_WIDTH-1:0] c_x__50; +reg [`BIT_WIDTH-1:0] c_x__51; +reg [`BIT_WIDTH-1:0] c_x__52; +reg [`BIT_WIDTH-1:0] c_x__53; +reg [`BIT_WIDTH-1:0] c_x__54; +reg [`BIT_WIDTH-1:0] c_x__55; +reg [`BIT_WIDTH-1:0] c_x__56; +reg [`BIT_WIDTH-1:0] c_x__57; +reg [`BIT_WIDTH-1:0] c_x__58; +reg [`BIT_WIDTH-1:0] c_x__59; + +//reg [BIT_WIDTH-1:0] c_y [TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_y__0; +reg [`BIT_WIDTH-1:0] c_y__1; +reg [`BIT_WIDTH-1:0] c_y__2; +reg [`BIT_WIDTH-1:0] c_y__3; +reg [`BIT_WIDTH-1:0] c_y__4; +reg [`BIT_WIDTH-1:0] c_y__5; +reg [`BIT_WIDTH-1:0] c_y__6; +reg [`BIT_WIDTH-1:0] c_y__7; +reg [`BIT_WIDTH-1:0] c_y__8; +reg [`BIT_WIDTH-1:0] c_y__9; +reg [`BIT_WIDTH-1:0] c_y__10; +reg [`BIT_WIDTH-1:0] c_y__11; +reg [`BIT_WIDTH-1:0] c_y__12; +reg [`BIT_WIDTH-1:0] c_y__13; +reg [`BIT_WIDTH-1:0] c_y__14; +reg [`BIT_WIDTH-1:0] c_y__15; +reg [`BIT_WIDTH-1:0] c_y__16; +reg [`BIT_WIDTH-1:0] c_y__17; +reg [`BIT_WIDTH-1:0] c_y__18; +reg [`BIT_WIDTH-1:0] c_y__19; +reg [`BIT_WIDTH-1:0] c_y__20; +reg [`BIT_WIDTH-1:0] c_y__21; +reg [`BIT_WIDTH-1:0] c_y__22; +reg [`BIT_WIDTH-1:0] c_y__23; +reg [`BIT_WIDTH-1:0] c_y__24; +reg [`BIT_WIDTH-1:0] c_y__25; +reg [`BIT_WIDTH-1:0] c_y__26; +reg [`BIT_WIDTH-1:0] c_y__27; +reg [`BIT_WIDTH-1:0] c_y__28; +reg [`BIT_WIDTH-1:0] c_y__29; +reg [`BIT_WIDTH-1:0] c_y__30; +reg [`BIT_WIDTH-1:0] c_y__31; +reg [`BIT_WIDTH-1:0] c_y__32; +reg [`BIT_WIDTH-1:0] c_y__33; +reg [`BIT_WIDTH-1:0] c_y__34; +reg [`BIT_WIDTH-1:0] c_y__35; +reg [`BIT_WIDTH-1:0] c_y__36; +reg [`BIT_WIDTH-1:0] c_y__37; +reg [`BIT_WIDTH-1:0] c_y__38; +reg [`BIT_WIDTH-1:0] c_y__39; +reg [`BIT_WIDTH-1:0] c_y__40; +reg [`BIT_WIDTH-1:0] c_y__41; +reg [`BIT_WIDTH-1:0] c_y__42; +reg [`BIT_WIDTH-1:0] c_y__43; +reg [`BIT_WIDTH-1:0] c_y__44; +reg [`BIT_WIDTH-1:0] c_y__45; +reg [`BIT_WIDTH-1:0] c_y__46; +reg [`BIT_WIDTH-1:0] c_y__47; +reg [`BIT_WIDTH-1:0] c_y__48; +reg [`BIT_WIDTH-1:0] c_y__49; +reg [`BIT_WIDTH-1:0] c_y__50; +reg [`BIT_WIDTH-1:0] c_y__51; +reg [`BIT_WIDTH-1:0] c_y__52; +reg [`BIT_WIDTH-1:0] c_y__53; +reg [`BIT_WIDTH-1:0] c_y__54; +reg [`BIT_WIDTH-1:0] c_y__55; +reg [`BIT_WIDTH-1:0] c_y__56; +reg [`BIT_WIDTH-1:0] c_y__57; +reg [`BIT_WIDTH-1:0] c_y__58; +reg [`BIT_WIDTH-1:0] c_y__59; + + +//reg [BIT_WIDTH-1:0] c_z [TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_z__0; +reg [`BIT_WIDTH-1:0] c_z__1; +reg [`BIT_WIDTH-1:0] c_z__2; +reg [`BIT_WIDTH-1:0] c_z__3; +reg [`BIT_WIDTH-1:0] c_z__4; +reg [`BIT_WIDTH-1:0] c_z__5; +reg [`BIT_WIDTH-1:0] c_z__6; +reg [`BIT_WIDTH-1:0] c_z__7; +reg [`BIT_WIDTH-1:0] c_z__8; +reg [`BIT_WIDTH-1:0] c_z__9; +reg [`BIT_WIDTH-1:0] c_z__10; +reg [`BIT_WIDTH-1:0] c_z__11; +reg [`BIT_WIDTH-1:0] c_z__12; +reg [`BIT_WIDTH-1:0] c_z__13; +reg [`BIT_WIDTH-1:0] c_z__14; +reg [`BIT_WIDTH-1:0] c_z__15; +reg [`BIT_WIDTH-1:0] c_z__16; +reg [`BIT_WIDTH-1:0] c_z__17; +reg [`BIT_WIDTH-1:0] c_z__18; +reg [`BIT_WIDTH-1:0] c_z__19; +reg [`BIT_WIDTH-1:0] c_z__20; +reg [`BIT_WIDTH-1:0] c_z__21; +reg [`BIT_WIDTH-1:0] c_z__22; +reg [`BIT_WIDTH-1:0] c_z__23; +reg [`BIT_WIDTH-1:0] c_z__24; +reg [`BIT_WIDTH-1:0] c_z__25; +reg [`BIT_WIDTH-1:0] c_z__26; +reg [`BIT_WIDTH-1:0] c_z__27; +reg [`BIT_WIDTH-1:0] c_z__28; +reg [`BIT_WIDTH-1:0] c_z__29; +reg [`BIT_WIDTH-1:0] c_z__30; +reg [`BIT_WIDTH-1:0] c_z__31; +reg [`BIT_WIDTH-1:0] c_z__32; +reg [`BIT_WIDTH-1:0] c_z__33; +reg [`BIT_WIDTH-1:0] c_z__34; +reg [`BIT_WIDTH-1:0] c_z__35; +reg [`BIT_WIDTH-1:0] c_z__36; +reg [`BIT_WIDTH-1:0] c_z__37; +reg [`BIT_WIDTH-1:0] c_z__38; +reg [`BIT_WIDTH-1:0] c_z__39; +reg [`BIT_WIDTH-1:0] c_z__40; +reg [`BIT_WIDTH-1:0] c_z__41; +reg [`BIT_WIDTH-1:0] c_z__42; +reg [`BIT_WIDTH-1:0] c_z__43; +reg [`BIT_WIDTH-1:0] c_z__44; +reg [`BIT_WIDTH-1:0] c_z__45; +reg [`BIT_WIDTH-1:0] c_z__46; +reg [`BIT_WIDTH-1:0] c_z__47; +reg [`BIT_WIDTH-1:0] c_z__48; +reg [`BIT_WIDTH-1:0] c_z__49; +reg [`BIT_WIDTH-1:0] c_z__50; +reg [`BIT_WIDTH-1:0] c_z__51; +reg [`BIT_WIDTH-1:0] c_z__52; +reg [`BIT_WIDTH-1:0] c_z__53; +reg [`BIT_WIDTH-1:0] c_z__54; +reg [`BIT_WIDTH-1:0] c_z__55; +reg [`BIT_WIDTH-1:0] c_z__56; +reg [`BIT_WIDTH-1:0] c_z__57; +reg [`BIT_WIDTH-1:0] c_z__58; +reg [`BIT_WIDTH-1:0] c_z__59; + + + +//reg [`BIT_WIDTH-1:0] c_ux [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_ux__0; +reg [`BIT_WIDTH-1:0] c_ux__1; +reg [`BIT_WIDTH-1:0] c_ux__2; +reg [`BIT_WIDTH-1:0] c_ux__3; +reg [`BIT_WIDTH-1:0] c_ux__4; +reg [`BIT_WIDTH-1:0] c_ux__5; +reg [`BIT_WIDTH-1:0] c_ux__6; +reg [`BIT_WIDTH-1:0] c_ux__7; +reg [`BIT_WIDTH-1:0] c_ux__8; +reg [`BIT_WIDTH-1:0] c_ux__9; +reg [`BIT_WIDTH-1:0] c_ux__10; +reg [`BIT_WIDTH-1:0] c_ux__11; +reg [`BIT_WIDTH-1:0] c_ux__12; +reg [`BIT_WIDTH-1:0] c_ux__13; +reg [`BIT_WIDTH-1:0] c_ux__14; +reg [`BIT_WIDTH-1:0] c_ux__15; +reg [`BIT_WIDTH-1:0] c_ux__16; +reg [`BIT_WIDTH-1:0] c_ux__17; +reg [`BIT_WIDTH-1:0] c_ux__18; +reg [`BIT_WIDTH-1:0] c_ux__19; +reg [`BIT_WIDTH-1:0] c_ux__20; +reg [`BIT_WIDTH-1:0] c_ux__21; +reg [`BIT_WIDTH-1:0] c_ux__22; +reg [`BIT_WIDTH-1:0] c_ux__23; +reg [`BIT_WIDTH-1:0] c_ux__24; +reg [`BIT_WIDTH-1:0] c_ux__25; +reg [`BIT_WIDTH-1:0] c_ux__26; +reg [`BIT_WIDTH-1:0] c_ux__27; +reg [`BIT_WIDTH-1:0] c_ux__28; +reg [`BIT_WIDTH-1:0] c_ux__29; +reg [`BIT_WIDTH-1:0] c_ux__30; +reg [`BIT_WIDTH-1:0] c_ux__31; +reg [`BIT_WIDTH-1:0] c_ux__32; +reg [`BIT_WIDTH-1:0] c_ux__33; +reg [`BIT_WIDTH-1:0] c_ux__34; +reg [`BIT_WIDTH-1:0] c_ux__35; +reg [`BIT_WIDTH-1:0] c_ux__36; +reg [`BIT_WIDTH-1:0] c_ux__37; +reg [`BIT_WIDTH-1:0] c_ux__38; +reg [`BIT_WIDTH-1:0] c_ux__39; +reg [`BIT_WIDTH-1:0] c_ux__40; +reg [`BIT_WIDTH-1:0] c_ux__41; +reg [`BIT_WIDTH-1:0] c_ux__42; +reg [`BIT_WIDTH-1:0] c_ux__43; +reg [`BIT_WIDTH-1:0] c_ux__44; +reg [`BIT_WIDTH-1:0] c_ux__45; +reg [`BIT_WIDTH-1:0] c_ux__46; +reg [`BIT_WIDTH-1:0] c_ux__47; +reg [`BIT_WIDTH-1:0] c_ux__48; +reg [`BIT_WIDTH-1:0] c_ux__49; +reg [`BIT_WIDTH-1:0] c_ux__50; +reg [`BIT_WIDTH-1:0] c_ux__51; +reg [`BIT_WIDTH-1:0] c_ux__52; +reg [`BIT_WIDTH-1:0] c_ux__53; +reg [`BIT_WIDTH-1:0] c_ux__54; +reg [`BIT_WIDTH-1:0] c_ux__55; +reg [`BIT_WIDTH-1:0] c_ux__56; +reg [`BIT_WIDTH-1:0] c_ux__57; +reg [`BIT_WIDTH-1:0] c_ux__58; +reg [`BIT_WIDTH-1:0] c_ux__59; +//reg [`BIT_WIDTH-1:0] c_uy [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_uy__0; +reg [`BIT_WIDTH-1:0] c_uy__1; +reg [`BIT_WIDTH-1:0] c_uy__2; +reg [`BIT_WIDTH-1:0] c_uy__3; +reg [`BIT_WIDTH-1:0] c_uy__4; +reg [`BIT_WIDTH-1:0] c_uy__5; +reg [`BIT_WIDTH-1:0] c_uy__6; +reg [`BIT_WIDTH-1:0] c_uy__7; +reg [`BIT_WIDTH-1:0] c_uy__8; +reg [`BIT_WIDTH-1:0] c_uy__9; +reg [`BIT_WIDTH-1:0] c_uy__10; +reg [`BIT_WIDTH-1:0] c_uy__11; +reg [`BIT_WIDTH-1:0] c_uy__12; +reg [`BIT_WIDTH-1:0] c_uy__13; +reg [`BIT_WIDTH-1:0] c_uy__14; +reg [`BIT_WIDTH-1:0] c_uy__15; +reg [`BIT_WIDTH-1:0] c_uy__16; +reg [`BIT_WIDTH-1:0] c_uy__17; +reg [`BIT_WIDTH-1:0] c_uy__18; +reg [`BIT_WIDTH-1:0] c_uy__19; +reg [`BIT_WIDTH-1:0] c_uy__20; +reg [`BIT_WIDTH-1:0] c_uy__21; +reg [`BIT_WIDTH-1:0] c_uy__22; +reg [`BIT_WIDTH-1:0] c_uy__23; +reg [`BIT_WIDTH-1:0] c_uy__24; +reg [`BIT_WIDTH-1:0] c_uy__25; +reg [`BIT_WIDTH-1:0] c_uy__26; +reg [`BIT_WIDTH-1:0] c_uy__27; +reg [`BIT_WIDTH-1:0] c_uy__28; +reg [`BIT_WIDTH-1:0] c_uy__29; +reg [`BIT_WIDTH-1:0] c_uy__30; +reg [`BIT_WIDTH-1:0] c_uy__31; +reg [`BIT_WIDTH-1:0] c_uy__32; +reg [`BIT_WIDTH-1:0] c_uy__33; +reg [`BIT_WIDTH-1:0] c_uy__34; +reg [`BIT_WIDTH-1:0] c_uy__35; +reg [`BIT_WIDTH-1:0] c_uy__36; +reg [`BIT_WIDTH-1:0] c_uy__37; +reg [`BIT_WIDTH-1:0] c_uy__38; +reg [`BIT_WIDTH-1:0] c_uy__39; +reg [`BIT_WIDTH-1:0] c_uy__40; +reg [`BIT_WIDTH-1:0] c_uy__41; +reg [`BIT_WIDTH-1:0] c_uy__42; +reg [`BIT_WIDTH-1:0] c_uy__43; +reg [`BIT_WIDTH-1:0] c_uy__44; +reg [`BIT_WIDTH-1:0] c_uy__45; +reg [`BIT_WIDTH-1:0] c_uy__46; +reg [`BIT_WIDTH-1:0] c_uy__47; +reg [`BIT_WIDTH-1:0] c_uy__48; +reg [`BIT_WIDTH-1:0] c_uy__49; +reg [`BIT_WIDTH-1:0] c_uy__50; +reg [`BIT_WIDTH-1:0] c_uy__51; +reg [`BIT_WIDTH-1:0] c_uy__52; +reg [`BIT_WIDTH-1:0] c_uy__53; +reg [`BIT_WIDTH-1:0] c_uy__54; +reg [`BIT_WIDTH-1:0] c_uy__55; +reg [`BIT_WIDTH-1:0] c_uy__56; +reg [`BIT_WIDTH-1:0] c_uy__57; +reg [`BIT_WIDTH-1:0] c_uy__58; +reg [`BIT_WIDTH-1:0] c_uy__59; +//reg [`BIT_WIDTH-1:0] c_uz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_uz__0; +reg [`BIT_WIDTH-1:0] c_uz__1; +reg [`BIT_WIDTH-1:0] c_uz__2; +reg [`BIT_WIDTH-1:0] c_uz__3; +reg [`BIT_WIDTH-1:0] c_uz__4; +reg [`BIT_WIDTH-1:0] c_uz__5; +reg [`BIT_WIDTH-1:0] c_uz__6; +reg [`BIT_WIDTH-1:0] c_uz__7; +reg [`BIT_WIDTH-1:0] c_uz__8; +reg [`BIT_WIDTH-1:0] c_uz__9; +reg [`BIT_WIDTH-1:0] c_uz__10; +reg [`BIT_WIDTH-1:0] c_uz__11; +reg [`BIT_WIDTH-1:0] c_uz__12; +reg [`BIT_WIDTH-1:0] c_uz__13; +reg [`BIT_WIDTH-1:0] c_uz__14; +reg [`BIT_WIDTH-1:0] c_uz__15; +reg [`BIT_WIDTH-1:0] c_uz__16; +reg [`BIT_WIDTH-1:0] c_uz__17; +reg [`BIT_WIDTH-1:0] c_uz__18; +reg [`BIT_WIDTH-1:0] c_uz__19; +reg [`BIT_WIDTH-1:0] c_uz__20; +reg [`BIT_WIDTH-1:0] c_uz__21; +reg [`BIT_WIDTH-1:0] c_uz__22; +reg [`BIT_WIDTH-1:0] c_uz__23; +reg [`BIT_WIDTH-1:0] c_uz__24; +reg [`BIT_WIDTH-1:0] c_uz__25; +reg [`BIT_WIDTH-1:0] c_uz__26; +reg [`BIT_WIDTH-1:0] c_uz__27; +reg [`BIT_WIDTH-1:0] c_uz__28; +reg [`BIT_WIDTH-1:0] c_uz__29; +reg [`BIT_WIDTH-1:0] c_uz__30; +reg [`BIT_WIDTH-1:0] c_uz__31; +reg [`BIT_WIDTH-1:0] c_uz__32; +reg [`BIT_WIDTH-1:0] c_uz__33; +reg [`BIT_WIDTH-1:0] c_uz__34; +reg [`BIT_WIDTH-1:0] c_uz__35; +reg [`BIT_WIDTH-1:0] c_uz__36; +reg [`BIT_WIDTH-1:0] c_uz__37; +reg [`BIT_WIDTH-1:0] c_uz__38; +reg [`BIT_WIDTH-1:0] c_uz__39; +reg [`BIT_WIDTH-1:0] c_uz__40; +reg [`BIT_WIDTH-1:0] c_uz__41; +reg [`BIT_WIDTH-1:0] c_uz__42; +reg [`BIT_WIDTH-1:0] c_uz__43; +reg [`BIT_WIDTH-1:0] c_uz__44; +reg [`BIT_WIDTH-1:0] c_uz__45; +reg [`BIT_WIDTH-1:0] c_uz__46; +reg [`BIT_WIDTH-1:0] c_uz__47; +reg [`BIT_WIDTH-1:0] c_uz__48; +reg [`BIT_WIDTH-1:0] c_uz__49; +reg [`BIT_WIDTH-1:0] c_uz__50; +reg [`BIT_WIDTH-1:0] c_uz__51; +reg [`BIT_WIDTH-1:0] c_uz__52; +reg [`BIT_WIDTH-1:0] c_uz__53; +reg [`BIT_WIDTH-1:0] c_uz__54; +reg [`BIT_WIDTH-1:0] c_uz__55; +reg [`BIT_WIDTH-1:0] c_uz__56; +reg [`BIT_WIDTH-1:0] c_uz__57; +reg [`BIT_WIDTH-1:0] c_uz__58; +reg [`BIT_WIDTH-1:0] c_uz__59; +//reg [`BIT_WIDTH-1:0] c_sz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sz__0; +reg [`BIT_WIDTH-1:0] c_sz__1; +reg [`BIT_WIDTH-1:0] c_sz__2; +reg [`BIT_WIDTH-1:0] c_sz__3; +reg [`BIT_WIDTH-1:0] c_sz__4; +reg [`BIT_WIDTH-1:0] c_sz__5; +reg [`BIT_WIDTH-1:0] c_sz__6; +reg [`BIT_WIDTH-1:0] c_sz__7; +reg [`BIT_WIDTH-1:0] c_sz__8; +reg [`BIT_WIDTH-1:0] c_sz__9; +reg [`BIT_WIDTH-1:0] c_sz__10; +reg [`BIT_WIDTH-1:0] c_sz__11; +reg [`BIT_WIDTH-1:0] c_sz__12; +reg [`BIT_WIDTH-1:0] c_sz__13; +reg [`BIT_WIDTH-1:0] c_sz__14; +reg [`BIT_WIDTH-1:0] c_sz__15; +reg [`BIT_WIDTH-1:0] c_sz__16; +reg [`BIT_WIDTH-1:0] c_sz__17; +reg [`BIT_WIDTH-1:0] c_sz__18; +reg [`BIT_WIDTH-1:0] c_sz__19; +reg [`BIT_WIDTH-1:0] c_sz__20; +reg [`BIT_WIDTH-1:0] c_sz__21; +reg [`BIT_WIDTH-1:0] c_sz__22; +reg [`BIT_WIDTH-1:0] c_sz__23; +reg [`BIT_WIDTH-1:0] c_sz__24; +reg [`BIT_WIDTH-1:0] c_sz__25; +reg [`BIT_WIDTH-1:0] c_sz__26; +reg [`BIT_WIDTH-1:0] c_sz__27; +reg [`BIT_WIDTH-1:0] c_sz__28; +reg [`BIT_WIDTH-1:0] c_sz__29; +reg [`BIT_WIDTH-1:0] c_sz__30; +reg [`BIT_WIDTH-1:0] c_sz__31; +reg [`BIT_WIDTH-1:0] c_sz__32; +reg [`BIT_WIDTH-1:0] c_sz__33; +reg [`BIT_WIDTH-1:0] c_sz__34; +reg [`BIT_WIDTH-1:0] c_sz__35; +reg [`BIT_WIDTH-1:0] c_sz__36; +reg [`BIT_WIDTH-1:0] c_sz__37; +reg [`BIT_WIDTH-1:0] c_sz__38; +reg [`BIT_WIDTH-1:0] c_sz__39; +reg [`BIT_WIDTH-1:0] c_sz__40; +reg [`BIT_WIDTH-1:0] c_sz__41; +reg [`BIT_WIDTH-1:0] c_sz__42; +reg [`BIT_WIDTH-1:0] c_sz__43; +reg [`BIT_WIDTH-1:0] c_sz__44; +reg [`BIT_WIDTH-1:0] c_sz__45; +reg [`BIT_WIDTH-1:0] c_sz__46; +reg [`BIT_WIDTH-1:0] c_sz__47; +reg [`BIT_WIDTH-1:0] c_sz__48; +reg [`BIT_WIDTH-1:0] c_sz__49; +reg [`BIT_WIDTH-1:0] c_sz__50; +reg [`BIT_WIDTH-1:0] c_sz__51; +reg [`BIT_WIDTH-1:0] c_sz__52; +reg [`BIT_WIDTH-1:0] c_sz__53; +reg [`BIT_WIDTH-1:0] c_sz__54; +reg [`BIT_WIDTH-1:0] c_sz__55; +reg [`BIT_WIDTH-1:0] c_sz__56; +reg [`BIT_WIDTH-1:0] c_sz__57; +reg [`BIT_WIDTH-1:0] c_sz__58; +reg [`BIT_WIDTH-1:0] c_sz__59; +//reg [`BIT_WIDTH-1:0] c_sr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sr__0; +reg [`BIT_WIDTH-1:0] c_sr__1; +reg [`BIT_WIDTH-1:0] c_sr__2; +reg [`BIT_WIDTH-1:0] c_sr__3; +reg [`BIT_WIDTH-1:0] c_sr__4; +reg [`BIT_WIDTH-1:0] c_sr__5; +reg [`BIT_WIDTH-1:0] c_sr__6; +reg [`BIT_WIDTH-1:0] c_sr__7; +reg [`BIT_WIDTH-1:0] c_sr__8; +reg [`BIT_WIDTH-1:0] c_sr__9; +reg [`BIT_WIDTH-1:0] c_sr__10; +reg [`BIT_WIDTH-1:0] c_sr__11; +reg [`BIT_WIDTH-1:0] c_sr__12; +reg [`BIT_WIDTH-1:0] c_sr__13; +reg [`BIT_WIDTH-1:0] c_sr__14; +reg [`BIT_WIDTH-1:0] c_sr__15; +reg [`BIT_WIDTH-1:0] c_sr__16; +reg [`BIT_WIDTH-1:0] c_sr__17; +reg [`BIT_WIDTH-1:0] c_sr__18; +reg [`BIT_WIDTH-1:0] c_sr__19; +reg [`BIT_WIDTH-1:0] c_sr__20; +reg [`BIT_WIDTH-1:0] c_sr__21; +reg [`BIT_WIDTH-1:0] c_sr__22; +reg [`BIT_WIDTH-1:0] c_sr__23; +reg [`BIT_WIDTH-1:0] c_sr__24; +reg [`BIT_WIDTH-1:0] c_sr__25; +reg [`BIT_WIDTH-1:0] c_sr__26; +reg [`BIT_WIDTH-1:0] c_sr__27; +reg [`BIT_WIDTH-1:0] c_sr__28; +reg [`BIT_WIDTH-1:0] c_sr__29; +reg [`BIT_WIDTH-1:0] c_sr__30; +reg [`BIT_WIDTH-1:0] c_sr__31; +reg [`BIT_WIDTH-1:0] c_sr__32; +reg [`BIT_WIDTH-1:0] c_sr__33; +reg [`BIT_WIDTH-1:0] c_sr__34; +reg [`BIT_WIDTH-1:0] c_sr__35; +reg [`BIT_WIDTH-1:0] c_sr__36; +reg [`BIT_WIDTH-1:0] c_sr__37; +reg [`BIT_WIDTH-1:0] c_sr__38; +reg [`BIT_WIDTH-1:0] c_sr__39; +reg [`BIT_WIDTH-1:0] c_sr__40; +reg [`BIT_WIDTH-1:0] c_sr__41; +reg [`BIT_WIDTH-1:0] c_sr__42; +reg [`BIT_WIDTH-1:0] c_sr__43; +reg [`BIT_WIDTH-1:0] c_sr__44; +reg [`BIT_WIDTH-1:0] c_sr__45; +reg [`BIT_WIDTH-1:0] c_sr__46; +reg [`BIT_WIDTH-1:0] c_sr__47; +reg [`BIT_WIDTH-1:0] c_sr__48; +reg [`BIT_WIDTH-1:0] c_sr__49; +reg [`BIT_WIDTH-1:0] c_sr__50; +reg [`BIT_WIDTH-1:0] c_sr__51; +reg [`BIT_WIDTH-1:0] c_sr__52; +reg [`BIT_WIDTH-1:0] c_sr__53; +reg [`BIT_WIDTH-1:0] c_sr__54; +reg [`BIT_WIDTH-1:0] c_sr__55; +reg [`BIT_WIDTH-1:0] c_sr__56; +reg [`BIT_WIDTH-1:0] c_sr__57; +reg [`BIT_WIDTH-1:0] c_sr__58; +reg [`BIT_WIDTH-1:0] c_sr__59; +//reg [`BIT_WIDTH-1:0] c_sleftz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sleftz__0; +reg [`BIT_WIDTH-1:0] c_sleftz__1; +reg [`BIT_WIDTH-1:0] c_sleftz__2; +reg [`BIT_WIDTH-1:0] c_sleftz__3; +reg [`BIT_WIDTH-1:0] c_sleftz__4; +reg [`BIT_WIDTH-1:0] c_sleftz__5; +reg [`BIT_WIDTH-1:0] c_sleftz__6; +reg [`BIT_WIDTH-1:0] c_sleftz__7; +reg [`BIT_WIDTH-1:0] c_sleftz__8; +reg [`BIT_WIDTH-1:0] c_sleftz__9; +reg [`BIT_WIDTH-1:0] c_sleftz__10; +reg [`BIT_WIDTH-1:0] c_sleftz__11; +reg [`BIT_WIDTH-1:0] c_sleftz__12; +reg [`BIT_WIDTH-1:0] c_sleftz__13; +reg [`BIT_WIDTH-1:0] c_sleftz__14; +reg [`BIT_WIDTH-1:0] c_sleftz__15; +reg [`BIT_WIDTH-1:0] c_sleftz__16; +reg [`BIT_WIDTH-1:0] c_sleftz__17; +reg [`BIT_WIDTH-1:0] c_sleftz__18; +reg [`BIT_WIDTH-1:0] c_sleftz__19; +reg [`BIT_WIDTH-1:0] c_sleftz__20; +reg [`BIT_WIDTH-1:0] c_sleftz__21; +reg [`BIT_WIDTH-1:0] c_sleftz__22; +reg [`BIT_WIDTH-1:0] c_sleftz__23; +reg [`BIT_WIDTH-1:0] c_sleftz__24; +reg [`BIT_WIDTH-1:0] c_sleftz__25; +reg [`BIT_WIDTH-1:0] c_sleftz__26; +reg [`BIT_WIDTH-1:0] c_sleftz__27; +reg [`BIT_WIDTH-1:0] c_sleftz__28; +reg [`BIT_WIDTH-1:0] c_sleftz__29; +reg [`BIT_WIDTH-1:0] c_sleftz__30; +reg [`BIT_WIDTH-1:0] c_sleftz__31; +reg [`BIT_WIDTH-1:0] c_sleftz__32; +reg [`BIT_WIDTH-1:0] c_sleftz__33; +reg [`BIT_WIDTH-1:0] c_sleftz__34; +reg [`BIT_WIDTH-1:0] c_sleftz__35; +reg [`BIT_WIDTH-1:0] c_sleftz__36; +reg [`BIT_WIDTH-1:0] c_sleftz__37; +reg [`BIT_WIDTH-1:0] c_sleftz__38; +reg [`BIT_WIDTH-1:0] c_sleftz__39; +reg [`BIT_WIDTH-1:0] c_sleftz__40; +reg [`BIT_WIDTH-1:0] c_sleftz__41; +reg [`BIT_WIDTH-1:0] c_sleftz__42; +reg [`BIT_WIDTH-1:0] c_sleftz__43; +reg [`BIT_WIDTH-1:0] c_sleftz__44; +reg [`BIT_WIDTH-1:0] c_sleftz__45; +reg [`BIT_WIDTH-1:0] c_sleftz__46; +reg [`BIT_WIDTH-1:0] c_sleftz__47; +reg [`BIT_WIDTH-1:0] c_sleftz__48; +reg [`BIT_WIDTH-1:0] c_sleftz__49; +reg [`BIT_WIDTH-1:0] c_sleftz__50; +reg [`BIT_WIDTH-1:0] c_sleftz__51; +reg [`BIT_WIDTH-1:0] c_sleftz__52; +reg [`BIT_WIDTH-1:0] c_sleftz__53; +reg [`BIT_WIDTH-1:0] c_sleftz__54; +reg [`BIT_WIDTH-1:0] c_sleftz__55; +reg [`BIT_WIDTH-1:0] c_sleftz__56; +reg [`BIT_WIDTH-1:0] c_sleftz__57; +reg [`BIT_WIDTH-1:0] c_sleftz__58; +reg [`BIT_WIDTH-1:0] c_sleftz__59; +//reg [`BIT_WIDTH-1:0] c_sleftr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_sleftr__0; +reg [`BIT_WIDTH-1:0] c_sleftr__1; +reg [`BIT_WIDTH-1:0] c_sleftr__2; +reg [`BIT_WIDTH-1:0] c_sleftr__3; +reg [`BIT_WIDTH-1:0] c_sleftr__4; +reg [`BIT_WIDTH-1:0] c_sleftr__5; +reg [`BIT_WIDTH-1:0] c_sleftr__6; +reg [`BIT_WIDTH-1:0] c_sleftr__7; +reg [`BIT_WIDTH-1:0] c_sleftr__8; +reg [`BIT_WIDTH-1:0] c_sleftr__9; +reg [`BIT_WIDTH-1:0] c_sleftr__10; +reg [`BIT_WIDTH-1:0] c_sleftr__11; +reg [`BIT_WIDTH-1:0] c_sleftr__12; +reg [`BIT_WIDTH-1:0] c_sleftr__13; +reg [`BIT_WIDTH-1:0] c_sleftr__14; +reg [`BIT_WIDTH-1:0] c_sleftr__15; +reg [`BIT_WIDTH-1:0] c_sleftr__16; +reg [`BIT_WIDTH-1:0] c_sleftr__17; +reg [`BIT_WIDTH-1:0] c_sleftr__18; +reg [`BIT_WIDTH-1:0] c_sleftr__19; +reg [`BIT_WIDTH-1:0] c_sleftr__20; +reg [`BIT_WIDTH-1:0] c_sleftr__21; +reg [`BIT_WIDTH-1:0] c_sleftr__22; +reg [`BIT_WIDTH-1:0] c_sleftr__23; +reg [`BIT_WIDTH-1:0] c_sleftr__24; +reg [`BIT_WIDTH-1:0] c_sleftr__25; +reg [`BIT_WIDTH-1:0] c_sleftr__26; +reg [`BIT_WIDTH-1:0] c_sleftr__27; +reg [`BIT_WIDTH-1:0] c_sleftr__28; +reg [`BIT_WIDTH-1:0] c_sleftr__29; +reg [`BIT_WIDTH-1:0] c_sleftr__30; +reg [`BIT_WIDTH-1:0] c_sleftr__31; +reg [`BIT_WIDTH-1:0] c_sleftr__32; +reg [`BIT_WIDTH-1:0] c_sleftr__33; +reg [`BIT_WIDTH-1:0] c_sleftr__34; +reg [`BIT_WIDTH-1:0] c_sleftr__35; +reg [`BIT_WIDTH-1:0] c_sleftr__36; +reg [`BIT_WIDTH-1:0] c_sleftr__37; +reg [`BIT_WIDTH-1:0] c_sleftr__38; +reg [`BIT_WIDTH-1:0] c_sleftr__39; +reg [`BIT_WIDTH-1:0] c_sleftr__40; +reg [`BIT_WIDTH-1:0] c_sleftr__41; +reg [`BIT_WIDTH-1:0] c_sleftr__42; +reg [`BIT_WIDTH-1:0] c_sleftr__43; +reg [`BIT_WIDTH-1:0] c_sleftr__44; +reg [`BIT_WIDTH-1:0] c_sleftr__45; +reg [`BIT_WIDTH-1:0] c_sleftr__46; +reg [`BIT_WIDTH-1:0] c_sleftr__47; +reg [`BIT_WIDTH-1:0] c_sleftr__48; +reg [`BIT_WIDTH-1:0] c_sleftr__49; +reg [`BIT_WIDTH-1:0] c_sleftr__50; +reg [`BIT_WIDTH-1:0] c_sleftr__51; +reg [`BIT_WIDTH-1:0] c_sleftr__52; +reg [`BIT_WIDTH-1:0] c_sleftr__53; +reg [`BIT_WIDTH-1:0] c_sleftr__54; +reg [`BIT_WIDTH-1:0] c_sleftr__55; +reg [`BIT_WIDTH-1:0] c_sleftr__56; +reg [`BIT_WIDTH-1:0] c_sleftr__57; +reg [`BIT_WIDTH-1:0] c_sleftr__58; +reg [`BIT_WIDTH-1:0] c_sleftr__59; +//reg [`BIT_WIDTH-1:0] c_weight [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_weight__0; +reg [`BIT_WIDTH-1:0] c_weight__1; +reg [`BIT_WIDTH-1:0] c_weight__2; +reg [`BIT_WIDTH-1:0] c_weight__3; +reg [`BIT_WIDTH-1:0] c_weight__4; +reg [`BIT_WIDTH-1:0] c_weight__5; +reg [`BIT_WIDTH-1:0] c_weight__6; +reg [`BIT_WIDTH-1:0] c_weight__7; +reg [`BIT_WIDTH-1:0] c_weight__8; +reg [`BIT_WIDTH-1:0] c_weight__9; +reg [`BIT_WIDTH-1:0] c_weight__10; +reg [`BIT_WIDTH-1:0] c_weight__11; +reg [`BIT_WIDTH-1:0] c_weight__12; +reg [`BIT_WIDTH-1:0] c_weight__13; +reg [`BIT_WIDTH-1:0] c_weight__14; +reg [`BIT_WIDTH-1:0] c_weight__15; +reg [`BIT_WIDTH-1:0] c_weight__16; +reg [`BIT_WIDTH-1:0] c_weight__17; +reg [`BIT_WIDTH-1:0] c_weight__18; +reg [`BIT_WIDTH-1:0] c_weight__19; +reg [`BIT_WIDTH-1:0] c_weight__20; +reg [`BIT_WIDTH-1:0] c_weight__21; +reg [`BIT_WIDTH-1:0] c_weight__22; +reg [`BIT_WIDTH-1:0] c_weight__23; +reg [`BIT_WIDTH-1:0] c_weight__24; +reg [`BIT_WIDTH-1:0] c_weight__25; +reg [`BIT_WIDTH-1:0] c_weight__26; +reg [`BIT_WIDTH-1:0] c_weight__27; +reg [`BIT_WIDTH-1:0] c_weight__28; +reg [`BIT_WIDTH-1:0] c_weight__29; +reg [`BIT_WIDTH-1:0] c_weight__30; +reg [`BIT_WIDTH-1:0] c_weight__31; +reg [`BIT_WIDTH-1:0] c_weight__32; +reg [`BIT_WIDTH-1:0] c_weight__33; +reg [`BIT_WIDTH-1:0] c_weight__34; +reg [`BIT_WIDTH-1:0] c_weight__35; +reg [`BIT_WIDTH-1:0] c_weight__36; +reg [`BIT_WIDTH-1:0] c_weight__37; +reg [`BIT_WIDTH-1:0] c_weight__38; +reg [`BIT_WIDTH-1:0] c_weight__39; +reg [`BIT_WIDTH-1:0] c_weight__40; +reg [`BIT_WIDTH-1:0] c_weight__41; +reg [`BIT_WIDTH-1:0] c_weight__42; +reg [`BIT_WIDTH-1:0] c_weight__43; +reg [`BIT_WIDTH-1:0] c_weight__44; +reg [`BIT_WIDTH-1:0] c_weight__45; +reg [`BIT_WIDTH-1:0] c_weight__46; +reg [`BIT_WIDTH-1:0] c_weight__47; +reg [`BIT_WIDTH-1:0] c_weight__48; +reg [`BIT_WIDTH-1:0] c_weight__49; +reg [`BIT_WIDTH-1:0] c_weight__50; +reg [`BIT_WIDTH-1:0] c_weight__51; +reg [`BIT_WIDTH-1:0] c_weight__52; +reg [`BIT_WIDTH-1:0] c_weight__53; +reg [`BIT_WIDTH-1:0] c_weight__54; +reg [`BIT_WIDTH-1:0] c_weight__55; +reg [`BIT_WIDTH-1:0] c_weight__56; +reg [`BIT_WIDTH-1:0] c_weight__57; +reg [`BIT_WIDTH-1:0] c_weight__58; +reg [`BIT_WIDTH-1:0] c_weight__59; + +//reg [`LAYER_WIDTH-1:0] c_layer [TOTAL_LATENCY - 1:0]; + +reg [`LAYER_WIDTH-1:0] c_layer__0; +reg [`LAYER_WIDTH-1:0] c_layer__1; +reg [`LAYER_WIDTH-1:0] c_layer__2; +reg [`LAYER_WIDTH-1:0] c_layer__3; +reg [`LAYER_WIDTH-1:0] c_layer__4; +reg [`LAYER_WIDTH-1:0] c_layer__5; +reg [`LAYER_WIDTH-1:0] c_layer__6; +reg [`LAYER_WIDTH-1:0] c_layer__7; +reg [`LAYER_WIDTH-1:0] c_layer__8; +reg [`LAYER_WIDTH-1:0] c_layer__9; +reg [`LAYER_WIDTH-1:0] c_layer__10; +reg [`LAYER_WIDTH-1:0] c_layer__11; +reg [`LAYER_WIDTH-1:0] c_layer__12; +reg [`LAYER_WIDTH-1:0] c_layer__13; +reg [`LAYER_WIDTH-1:0] c_layer__14; +reg [`LAYER_WIDTH-1:0] c_layer__15; +reg [`LAYER_WIDTH-1:0] c_layer__16; +reg [`LAYER_WIDTH-1:0] c_layer__17; +reg [`LAYER_WIDTH-1:0] c_layer__18; +reg [`LAYER_WIDTH-1:0] c_layer__19; +reg [`LAYER_WIDTH-1:0] c_layer__20; +reg [`LAYER_WIDTH-1:0] c_layer__21; +reg [`LAYER_WIDTH-1:0] c_layer__22; +reg [`LAYER_WIDTH-1:0] c_layer__23; +reg [`LAYER_WIDTH-1:0] c_layer__24; +reg [`LAYER_WIDTH-1:0] c_layer__25; +reg [`LAYER_WIDTH-1:0] c_layer__26; +reg [`LAYER_WIDTH-1:0] c_layer__27; +reg [`LAYER_WIDTH-1:0] c_layer__28; +reg [`LAYER_WIDTH-1:0] c_layer__29; +reg [`LAYER_WIDTH-1:0] c_layer__30; +reg [`LAYER_WIDTH-1:0] c_layer__31; +reg [`LAYER_WIDTH-1:0] c_layer__32; +reg [`LAYER_WIDTH-1:0] c_layer__33; +reg [`LAYER_WIDTH-1:0] c_layer__34; +reg [`LAYER_WIDTH-1:0] c_layer__35; +reg [`LAYER_WIDTH-1:0] c_layer__36; +reg [`LAYER_WIDTH-1:0] c_layer__37; +reg [`LAYER_WIDTH-1:0] c_layer__38; +reg [`LAYER_WIDTH-1:0] c_layer__39; +reg [`LAYER_WIDTH-1:0] c_layer__40; +reg [`LAYER_WIDTH-1:0] c_layer__41; +reg [`LAYER_WIDTH-1:0] c_layer__42; +reg [`LAYER_WIDTH-1:0] c_layer__43; +reg [`LAYER_WIDTH-1:0] c_layer__44; +reg [`LAYER_WIDTH-1:0] c_layer__45; +reg [`LAYER_WIDTH-1:0] c_layer__46; +reg [`LAYER_WIDTH-1:0] c_layer__47; +reg [`LAYER_WIDTH-1:0] c_layer__48; +reg [`LAYER_WIDTH-1:0] c_layer__49; +reg [`LAYER_WIDTH-1:0] c_layer__50; +reg [`LAYER_WIDTH-1:0] c_layer__51; +reg [`LAYER_WIDTH-1:0] c_layer__52; +reg [`LAYER_WIDTH-1:0] c_layer__53; +reg [`LAYER_WIDTH-1:0] c_layer__54; +reg [`LAYER_WIDTH-1:0] c_layer__55; +reg [`LAYER_WIDTH-1:0] c_layer__56; +reg [`LAYER_WIDTH-1:0] c_layer__57; +reg [`LAYER_WIDTH-1:0] c_layer__58; +reg [`LAYER_WIDTH-1:0] c_layer__59; + + + +//reg c_dead [TOTAL_LATENCY - 1:0]; + +reg c_dead__0; +reg c_dead__1; +reg c_dead__2; +reg c_dead__3; +reg c_dead__4; +reg c_dead__5; +reg c_dead__6; +reg c_dead__7; +reg c_dead__8; +reg c_dead__9; +reg c_dead__10; +reg c_dead__11; +reg c_dead__12; +reg c_dead__13; +reg c_dead__14; +reg c_dead__15; +reg c_dead__16; +reg c_dead__17; +reg c_dead__18; +reg c_dead__19; +reg c_dead__20; +reg c_dead__21; +reg c_dead__22; +reg c_dead__23; +reg c_dead__24; +reg c_dead__25; +reg c_dead__26; +reg c_dead__27; +reg c_dead__28; +reg c_dead__29; +reg c_dead__30; +reg c_dead__31; +reg c_dead__32; +reg c_dead__33; +reg c_dead__34; +reg c_dead__35; +reg c_dead__36; +reg c_dead__37; +reg c_dead__38; +reg c_dead__39; +reg c_dead__40; +reg c_dead__41; +reg c_dead__42; +reg c_dead__43; +reg c_dead__44; +reg c_dead__45; +reg c_dead__46; +reg c_dead__47; +reg c_dead__48; +reg c_dead__49; +reg c_dead__50; +reg c_dead__51; +reg c_dead__52; +reg c_dead__53; +reg c_dead__54; +reg c_dead__55; +reg c_dead__56; +reg c_dead__57; +reg c_dead__58; +reg c_dead__59; + + +//reg c_hit [TOTAL_LATENCY - 1:0]; + +reg c_hit__0; +reg c_hit__1; +reg c_hit__2; +reg c_hit__3; +reg c_hit__4; +reg c_hit__5; +reg c_hit__6; +reg c_hit__7; +reg c_hit__8; +reg c_hit__9; +reg c_hit__10; +reg c_hit__11; +reg c_hit__12; +reg c_hit__13; +reg c_hit__14; +reg c_hit__15; +reg c_hit__16; +reg c_hit__17; +reg c_hit__18; +reg c_hit__19; +reg c_hit__20; +reg c_hit__21; +reg c_hit__22; +reg c_hit__23; +reg c_hit__24; +reg c_hit__25; +reg c_hit__26; +reg c_hit__27; +reg c_hit__28; +reg c_hit__29; +reg c_hit__30; +reg c_hit__31; +reg c_hit__32; +reg c_hit__33; +reg c_hit__34; +reg c_hit__35; +reg c_hit__36; +reg c_hit__37; +reg c_hit__38; +reg c_hit__39; +reg c_hit__40; +reg c_hit__41; +reg c_hit__42; +reg c_hit__43; +reg c_hit__44; +reg c_hit__45; +reg c_hit__46; +reg c_hit__47; +reg c_hit__48; +reg c_hit__49; +reg c_hit__50; +reg c_hit__51; +reg c_hit__52; +reg c_hit__53; +reg c_hit__54; +reg c_hit__55; +reg c_hit__56; +reg c_hit__57; +reg c_hit__58; +reg c_hit__59; + +//reg [`BIT_WIDTH-1:0] c_diff[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_diff__0; +reg [`BIT_WIDTH-1:0] c_diff__1; +reg [`BIT_WIDTH-1:0] c_diff__2; +reg [`BIT_WIDTH-1:0] c_diff__3; +reg [`BIT_WIDTH-1:0] c_diff__4; +reg [`BIT_WIDTH-1:0] c_diff__5; +reg [`BIT_WIDTH-1:0] c_diff__6; +reg [`BIT_WIDTH-1:0] c_diff__7; +reg [`BIT_WIDTH-1:0] c_diff__8; +reg [`BIT_WIDTH-1:0] c_diff__9; +reg [`BIT_WIDTH-1:0] c_diff__10; +reg [`BIT_WIDTH-1:0] c_diff__11; +reg [`BIT_WIDTH-1:0] c_diff__12; +reg [`BIT_WIDTH-1:0] c_diff__13; +reg [`BIT_WIDTH-1:0] c_diff__14; +reg [`BIT_WIDTH-1:0] c_diff__15; +reg [`BIT_WIDTH-1:0] c_diff__16; +reg [`BIT_WIDTH-1:0] c_diff__17; +reg [`BIT_WIDTH-1:0] c_diff__18; +reg [`BIT_WIDTH-1:0] c_diff__19; +reg [`BIT_WIDTH-1:0] c_diff__20; +reg [`BIT_WIDTH-1:0] c_diff__21; +reg [`BIT_WIDTH-1:0] c_diff__22; +reg [`BIT_WIDTH-1:0] c_diff__23; +reg [`BIT_WIDTH-1:0] c_diff__24; +reg [`BIT_WIDTH-1:0] c_diff__25; +reg [`BIT_WIDTH-1:0] c_diff__26; +reg [`BIT_WIDTH-1:0] c_diff__27; +reg [`BIT_WIDTH-1:0] c_diff__28; +reg [`BIT_WIDTH-1:0] c_diff__29; +reg [`BIT_WIDTH-1:0] c_diff__30; +reg [`BIT_WIDTH-1:0] c_diff__31; +reg [`BIT_WIDTH-1:0] c_diff__32; +reg [`BIT_WIDTH-1:0] c_diff__33; +reg [`BIT_WIDTH-1:0] c_diff__34; +reg [`BIT_WIDTH-1:0] c_diff__35; +reg [`BIT_WIDTH-1:0] c_diff__36; +reg [`BIT_WIDTH-1:0] c_diff__37; +reg [`BIT_WIDTH-1:0] c_diff__38; +reg [`BIT_WIDTH-1:0] c_diff__39; +reg [`BIT_WIDTH-1:0] c_diff__40; +reg [`BIT_WIDTH-1:0] c_diff__41; +reg [`BIT_WIDTH-1:0] c_diff__42; +reg [`BIT_WIDTH-1:0] c_diff__43; +reg [`BIT_WIDTH-1:0] c_diff__44; +reg [`BIT_WIDTH-1:0] c_diff__45; +reg [`BIT_WIDTH-1:0] c_diff__46; +reg [`BIT_WIDTH-1:0] c_diff__47; +reg [`BIT_WIDTH-1:0] c_diff__48; +reg [`BIT_WIDTH-1:0] c_diff__49; +reg [`BIT_WIDTH-1:0] c_diff__50; +reg [`BIT_WIDTH-1:0] c_diff__51; +reg [`BIT_WIDTH-1:0] c_diff__52; +reg [`BIT_WIDTH-1:0] c_diff__53; +reg [`BIT_WIDTH-1:0] c_diff__54; +reg [`BIT_WIDTH-1:0] c_diff__55; +reg [`BIT_WIDTH-1:0] c_diff__56; +reg [`BIT_WIDTH-1:0] c_diff__57; +reg [`BIT_WIDTH-1:0] c_diff__58; +reg [`BIT_WIDTH-1:0] c_diff__59; + + +//reg [`BIT_WIDTH-1:0] c_dl_b[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_dl_b__0; +reg [`BIT_WIDTH-1:0] c_dl_b__1; +reg [`BIT_WIDTH-1:0] c_dl_b__2; +reg [`BIT_WIDTH-1:0] c_dl_b__3; +reg [`BIT_WIDTH-1:0] c_dl_b__4; +reg [`BIT_WIDTH-1:0] c_dl_b__5; +reg [`BIT_WIDTH-1:0] c_dl_b__6; +reg [`BIT_WIDTH-1:0] c_dl_b__7; +reg [`BIT_WIDTH-1:0] c_dl_b__8; +reg [`BIT_WIDTH-1:0] c_dl_b__9; +reg [`BIT_WIDTH-1:0] c_dl_b__10; +reg [`BIT_WIDTH-1:0] c_dl_b__11; +reg [`BIT_WIDTH-1:0] c_dl_b__12; +reg [`BIT_WIDTH-1:0] c_dl_b__13; +reg [`BIT_WIDTH-1:0] c_dl_b__14; +reg [`BIT_WIDTH-1:0] c_dl_b__15; +reg [`BIT_WIDTH-1:0] c_dl_b__16; +reg [`BIT_WIDTH-1:0] c_dl_b__17; +reg [`BIT_WIDTH-1:0] c_dl_b__18; +reg [`BIT_WIDTH-1:0] c_dl_b__19; +reg [`BIT_WIDTH-1:0] c_dl_b__20; +reg [`BIT_WIDTH-1:0] c_dl_b__21; +reg [`BIT_WIDTH-1:0] c_dl_b__22; +reg [`BIT_WIDTH-1:0] c_dl_b__23; +reg [`BIT_WIDTH-1:0] c_dl_b__24; +reg [`BIT_WIDTH-1:0] c_dl_b__25; +reg [`BIT_WIDTH-1:0] c_dl_b__26; +reg [`BIT_WIDTH-1:0] c_dl_b__27; +reg [`BIT_WIDTH-1:0] c_dl_b__28; +reg [`BIT_WIDTH-1:0] c_dl_b__29; +reg [`BIT_WIDTH-1:0] c_dl_b__30; +reg [`BIT_WIDTH-1:0] c_dl_b__31; +reg [`BIT_WIDTH-1:0] c_dl_b__32; +reg [`BIT_WIDTH-1:0] c_dl_b__33; +reg [`BIT_WIDTH-1:0] c_dl_b__34; +reg [`BIT_WIDTH-1:0] c_dl_b__35; +reg [`BIT_WIDTH-1:0] c_dl_b__36; +reg [`BIT_WIDTH-1:0] c_dl_b__37; +reg [`BIT_WIDTH-1:0] c_dl_b__38; +reg [`BIT_WIDTH-1:0] c_dl_b__39; +reg [`BIT_WIDTH-1:0] c_dl_b__40; +reg [`BIT_WIDTH-1:0] c_dl_b__41; +reg [`BIT_WIDTH-1:0] c_dl_b__42; +reg [`BIT_WIDTH-1:0] c_dl_b__43; +reg [`BIT_WIDTH-1:0] c_dl_b__44; +reg [`BIT_WIDTH-1:0] c_dl_b__45; +reg [`BIT_WIDTH-1:0] c_dl_b__46; +reg [`BIT_WIDTH-1:0] c_dl_b__47; +reg [`BIT_WIDTH-1:0] c_dl_b__48; +reg [`BIT_WIDTH-1:0] c_dl_b__49; +reg [`BIT_WIDTH-1:0] c_dl_b__50; +reg [`BIT_WIDTH-1:0] c_dl_b__51; +reg [`BIT_WIDTH-1:0] c_dl_b__52; +reg [`BIT_WIDTH-1:0] c_dl_b__53; +reg [`BIT_WIDTH-1:0] c_dl_b__54; +reg [`BIT_WIDTH-1:0] c_dl_b__55; +reg [`BIT_WIDTH-1:0] c_dl_b__56; +reg [`BIT_WIDTH-1:0] c_dl_b__57; +reg [`BIT_WIDTH-1:0] c_dl_b__58; +reg [`BIT_WIDTH-1:0] c_dl_b__59; + + +//reg [2*`BIT_WIDTH-1:0] c_numer[TOTAL_LATENCY - 1:0]; + + +reg [2*`BIT_WIDTH-1:0] c_numer__0; +reg [2*`BIT_WIDTH-1:0] c_numer__1; +reg [2*`BIT_WIDTH-1:0] c_numer__2; +reg [2*`BIT_WIDTH-1:0] c_numer__3; +reg [2*`BIT_WIDTH-1:0] c_numer__4; +reg [2*`BIT_WIDTH-1:0] c_numer__5; +reg [2*`BIT_WIDTH-1:0] c_numer__6; +reg [2*`BIT_WIDTH-1:0] c_numer__7; +reg [2*`BIT_WIDTH-1:0] c_numer__8; +reg [2*`BIT_WIDTH-1:0] c_numer__9; +reg [2*`BIT_WIDTH-1:0] c_numer__10; +reg [2*`BIT_WIDTH-1:0] c_numer__11; +reg [2*`BIT_WIDTH-1:0] c_numer__12; +reg [2*`BIT_WIDTH-1:0] c_numer__13; +reg [2*`BIT_WIDTH-1:0] c_numer__14; +reg [2*`BIT_WIDTH-1:0] c_numer__15; +reg [2*`BIT_WIDTH-1:0] c_numer__16; +reg [2*`BIT_WIDTH-1:0] c_numer__17; +reg [2*`BIT_WIDTH-1:0] c_numer__18; +reg [2*`BIT_WIDTH-1:0] c_numer__19; +reg [2*`BIT_WIDTH-1:0] c_numer__20; +reg [2*`BIT_WIDTH-1:0] c_numer__21; +reg [2*`BIT_WIDTH-1:0] c_numer__22; +reg [2*`BIT_WIDTH-1:0] c_numer__23; +reg [2*`BIT_WIDTH-1:0] c_numer__24; +reg [2*`BIT_WIDTH-1:0] c_numer__25; +reg [2*`BIT_WIDTH-1:0] c_numer__26; +reg [2*`BIT_WIDTH-1:0] c_numer__27; +reg [2*`BIT_WIDTH-1:0] c_numer__28; +reg [2*`BIT_WIDTH-1:0] c_numer__29; +reg [2*`BIT_WIDTH-1:0] c_numer__30; +reg [2*`BIT_WIDTH-1:0] c_numer__31; +reg [2*`BIT_WIDTH-1:0] c_numer__32; +reg [2*`BIT_WIDTH-1:0] c_numer__33; +reg [2*`BIT_WIDTH-1:0] c_numer__34; +reg [2*`BIT_WIDTH-1:0] c_numer__35; +reg [2*`BIT_WIDTH-1:0] c_numer__36; +reg [2*`BIT_WIDTH-1:0] c_numer__37; +reg [2*`BIT_WIDTH-1:0] c_numer__38; +reg [2*`BIT_WIDTH-1:0] c_numer__39; +reg [2*`BIT_WIDTH-1:0] c_numer__40; +reg [2*`BIT_WIDTH-1:0] c_numer__41; +reg [2*`BIT_WIDTH-1:0] c_numer__42; +reg [2*`BIT_WIDTH-1:0] c_numer__43; +reg [2*`BIT_WIDTH-1:0] c_numer__44; +reg [2*`BIT_WIDTH-1:0] c_numer__45; +reg [2*`BIT_WIDTH-1:0] c_numer__46; +reg [2*`BIT_WIDTH-1:0] c_numer__47; +reg [2*`BIT_WIDTH-1:0] c_numer__48; +reg [2*`BIT_WIDTH-1:0] c_numer__49; +reg [2*`BIT_WIDTH-1:0] c_numer__50; +reg [2*`BIT_WIDTH-1:0] c_numer__51; +reg [2*`BIT_WIDTH-1:0] c_numer__52; +reg [2*`BIT_WIDTH-1:0] c_numer__53; +reg [2*`BIT_WIDTH-1:0] c_numer__54; +reg [2*`BIT_WIDTH-1:0] c_numer__55; +reg [2*`BIT_WIDTH-1:0] c_numer__56; +reg [2*`BIT_WIDTH-1:0] c_numer__57; +reg [2*`BIT_WIDTH-1:0] c_numer__58; +reg [2*`BIT_WIDTH-1:0] c_numer__59; + +//reg [`BIT_WIDTH-1:0] c_z1[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_z1__0; +reg [`BIT_WIDTH-1:0] c_z1__1; +reg [`BIT_WIDTH-1:0] c_z1__2; +reg [`BIT_WIDTH-1:0] c_z1__3; +reg [`BIT_WIDTH-1:0] c_z1__4; +reg [`BIT_WIDTH-1:0] c_z1__5; +reg [`BIT_WIDTH-1:0] c_z1__6; +reg [`BIT_WIDTH-1:0] c_z1__7; +reg [`BIT_WIDTH-1:0] c_z1__8; +reg [`BIT_WIDTH-1:0] c_z1__9; +reg [`BIT_WIDTH-1:0] c_z1__10; +reg [`BIT_WIDTH-1:0] c_z1__11; +reg [`BIT_WIDTH-1:0] c_z1__12; +reg [`BIT_WIDTH-1:0] c_z1__13; +reg [`BIT_WIDTH-1:0] c_z1__14; +reg [`BIT_WIDTH-1:0] c_z1__15; +reg [`BIT_WIDTH-1:0] c_z1__16; +reg [`BIT_WIDTH-1:0] c_z1__17; +reg [`BIT_WIDTH-1:0] c_z1__18; +reg [`BIT_WIDTH-1:0] c_z1__19; +reg [`BIT_WIDTH-1:0] c_z1__20; +reg [`BIT_WIDTH-1:0] c_z1__21; +reg [`BIT_WIDTH-1:0] c_z1__22; +reg [`BIT_WIDTH-1:0] c_z1__23; +reg [`BIT_WIDTH-1:0] c_z1__24; +reg [`BIT_WIDTH-1:0] c_z1__25; +reg [`BIT_WIDTH-1:0] c_z1__26; +reg [`BIT_WIDTH-1:0] c_z1__27; +reg [`BIT_WIDTH-1:0] c_z1__28; +reg [`BIT_WIDTH-1:0] c_z1__29; +reg [`BIT_WIDTH-1:0] c_z1__30; +reg [`BIT_WIDTH-1:0] c_z1__31; +reg [`BIT_WIDTH-1:0] c_z1__32; +reg [`BIT_WIDTH-1:0] c_z1__33; +reg [`BIT_WIDTH-1:0] c_z1__34; +reg [`BIT_WIDTH-1:0] c_z1__35; +reg [`BIT_WIDTH-1:0] c_z1__36; +reg [`BIT_WIDTH-1:0] c_z1__37; +reg [`BIT_WIDTH-1:0] c_z1__38; +reg [`BIT_WIDTH-1:0] c_z1__39; +reg [`BIT_WIDTH-1:0] c_z1__40; +reg [`BIT_WIDTH-1:0] c_z1__41; +reg [`BIT_WIDTH-1:0] c_z1__42; +reg [`BIT_WIDTH-1:0] c_z1__43; +reg [`BIT_WIDTH-1:0] c_z1__44; +reg [`BIT_WIDTH-1:0] c_z1__45; +reg [`BIT_WIDTH-1:0] c_z1__46; +reg [`BIT_WIDTH-1:0] c_z1__47; +reg [`BIT_WIDTH-1:0] c_z1__48; +reg [`BIT_WIDTH-1:0] c_z1__49; +reg [`BIT_WIDTH-1:0] c_z1__50; +reg [`BIT_WIDTH-1:0] c_z1__51; +reg [`BIT_WIDTH-1:0] c_z1__52; +reg [`BIT_WIDTH-1:0] c_z1__53; +reg [`BIT_WIDTH-1:0] c_z1__54; +reg [`BIT_WIDTH-1:0] c_z1__55; +reg [`BIT_WIDTH-1:0] c_z1__56; +reg [`BIT_WIDTH-1:0] c_z1__57; +reg [`BIT_WIDTH-1:0] c_z1__58; +reg [`BIT_WIDTH-1:0] c_z1__59; + +//reg [`BIT_WIDTH-1:0] c_z0[TOTAL_LATENCY - 1:0]; + + +reg [`BIT_WIDTH-1:0] c_z0__0; +reg [`BIT_WIDTH-1:0] c_z0__1; +reg [`BIT_WIDTH-1:0] c_z0__2; +reg [`BIT_WIDTH-1:0] c_z0__3; +reg [`BIT_WIDTH-1:0] c_z0__4; +reg [`BIT_WIDTH-1:0] c_z0__5; +reg [`BIT_WIDTH-1:0] c_z0__6; +reg [`BIT_WIDTH-1:0] c_z0__7; +reg [`BIT_WIDTH-1:0] c_z0__8; +reg [`BIT_WIDTH-1:0] c_z0__9; +reg [`BIT_WIDTH-1:0] c_z0__10; +reg [`BIT_WIDTH-1:0] c_z0__11; +reg [`BIT_WIDTH-1:0] c_z0__12; +reg [`BIT_WIDTH-1:0] c_z0__13; +reg [`BIT_WIDTH-1:0] c_z0__14; +reg [`BIT_WIDTH-1:0] c_z0__15; +reg [`BIT_WIDTH-1:0] c_z0__16; +reg [`BIT_WIDTH-1:0] c_z0__17; +reg [`BIT_WIDTH-1:0] c_z0__18; +reg [`BIT_WIDTH-1:0] c_z0__19; +reg [`BIT_WIDTH-1:0] c_z0__20; +reg [`BIT_WIDTH-1:0] c_z0__21; +reg [`BIT_WIDTH-1:0] c_z0__22; +reg [`BIT_WIDTH-1:0] c_z0__23; +reg [`BIT_WIDTH-1:0] c_z0__24; +reg [`BIT_WIDTH-1:0] c_z0__25; +reg [`BIT_WIDTH-1:0] c_z0__26; +reg [`BIT_WIDTH-1:0] c_z0__27; +reg [`BIT_WIDTH-1:0] c_z0__28; +reg [`BIT_WIDTH-1:0] c_z0__29; +reg [`BIT_WIDTH-1:0] c_z0__30; +reg [`BIT_WIDTH-1:0] c_z0__31; +reg [`BIT_WIDTH-1:0] c_z0__32; +reg [`BIT_WIDTH-1:0] c_z0__33; +reg [`BIT_WIDTH-1:0] c_z0__34; +reg [`BIT_WIDTH-1:0] c_z0__35; +reg [`BIT_WIDTH-1:0] c_z0__36; +reg [`BIT_WIDTH-1:0] c_z0__37; +reg [`BIT_WIDTH-1:0] c_z0__38; +reg [`BIT_WIDTH-1:0] c_z0__39; +reg [`BIT_WIDTH-1:0] c_z0__40; +reg [`BIT_WIDTH-1:0] c_z0__41; +reg [`BIT_WIDTH-1:0] c_z0__42; +reg [`BIT_WIDTH-1:0] c_z0__43; +reg [`BIT_WIDTH-1:0] c_z0__44; +reg [`BIT_WIDTH-1:0] c_z0__45; +reg [`BIT_WIDTH-1:0] c_z0__46; +reg [`BIT_WIDTH-1:0] c_z0__47; +reg [`BIT_WIDTH-1:0] c_z0__48; +reg [`BIT_WIDTH-1:0] c_z0__49; +reg [`BIT_WIDTH-1:0] c_z0__50; +reg [`BIT_WIDTH-1:0] c_z0__51; +reg [`BIT_WIDTH-1:0] c_z0__52; +reg [`BIT_WIDTH-1:0] c_z0__53; +reg [`BIT_WIDTH-1:0] c_z0__54; +reg [`BIT_WIDTH-1:0] c_z0__55; +reg [`BIT_WIDTH-1:0] c_z0__56; +reg [`BIT_WIDTH-1:0] c_z0__57; +reg [`BIT_WIDTH-1:0] c_z0__58; +reg [`BIT_WIDTH-1:0] c_z0__59; + + + +//reg [`BIT_WIDTH-1:0] c_mut[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] c_mut__0; +reg [`BIT_WIDTH-1:0] c_mut__1; +reg [`BIT_WIDTH-1:0] c_mut__2; +reg [`BIT_WIDTH-1:0] c_mut__3; +reg [`BIT_WIDTH-1:0] c_mut__4; +reg [`BIT_WIDTH-1:0] c_mut__5; +reg [`BIT_WIDTH-1:0] c_mut__6; +reg [`BIT_WIDTH-1:0] c_mut__7; +reg [`BIT_WIDTH-1:0] c_mut__8; +reg [`BIT_WIDTH-1:0] c_mut__9; +reg [`BIT_WIDTH-1:0] c_mut__10; +reg [`BIT_WIDTH-1:0] c_mut__11; +reg [`BIT_WIDTH-1:0] c_mut__12; +reg [`BIT_WIDTH-1:0] c_mut__13; +reg [`BIT_WIDTH-1:0] c_mut__14; +reg [`BIT_WIDTH-1:0] c_mut__15; +reg [`BIT_WIDTH-1:0] c_mut__16; +reg [`BIT_WIDTH-1:0] c_mut__17; +reg [`BIT_WIDTH-1:0] c_mut__18; +reg [`BIT_WIDTH-1:0] c_mut__19; +reg [`BIT_WIDTH-1:0] c_mut__20; +reg [`BIT_WIDTH-1:0] c_mut__21; +reg [`BIT_WIDTH-1:0] c_mut__22; +reg [`BIT_WIDTH-1:0] c_mut__23; +reg [`BIT_WIDTH-1:0] c_mut__24; +reg [`BIT_WIDTH-1:0] c_mut__25; +reg [`BIT_WIDTH-1:0] c_mut__26; +reg [`BIT_WIDTH-1:0] c_mut__27; +reg [`BIT_WIDTH-1:0] c_mut__28; +reg [`BIT_WIDTH-1:0] c_mut__29; +reg [`BIT_WIDTH-1:0] c_mut__30; +reg [`BIT_WIDTH-1:0] c_mut__31; +reg [`BIT_WIDTH-1:0] c_mut__32; +reg [`BIT_WIDTH-1:0] c_mut__33; +reg [`BIT_WIDTH-1:0] c_mut__34; +reg [`BIT_WIDTH-1:0] c_mut__35; +reg [`BIT_WIDTH-1:0] c_mut__36; +reg [`BIT_WIDTH-1:0] c_mut__37; +reg [`BIT_WIDTH-1:0] c_mut__38; +reg [`BIT_WIDTH-1:0] c_mut__39; +reg [`BIT_WIDTH-1:0] c_mut__40; +reg [`BIT_WIDTH-1:0] c_mut__41; +reg [`BIT_WIDTH-1:0] c_mut__42; +reg [`BIT_WIDTH-1:0] c_mut__43; +reg [`BIT_WIDTH-1:0] c_mut__44; +reg [`BIT_WIDTH-1:0] c_mut__45; +reg [`BIT_WIDTH-1:0] c_mut__46; +reg [`BIT_WIDTH-1:0] c_mut__47; +reg [`BIT_WIDTH-1:0] c_mut__48; +reg [`BIT_WIDTH-1:0] c_mut__49; +reg [`BIT_WIDTH-1:0] c_mut__50; +reg [`BIT_WIDTH-1:0] c_mut__51; +reg [`BIT_WIDTH-1:0] c_mut__52; +reg [`BIT_WIDTH-1:0] c_mut__53; +reg [`BIT_WIDTH-1:0] c_mut__54; +reg [`BIT_WIDTH-1:0] c_mut__55; +reg [`BIT_WIDTH-1:0] c_mut__56; +reg [`BIT_WIDTH-1:0] c_mut__57; +reg [`BIT_WIDTH-1:0] c_mut__58; +reg [`BIT_WIDTH-1:0] c_mut__59; + + +//reg [`BIT_WIDTH-1:0] r_x [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_x__0; +reg [`BIT_WIDTH-1:0] r_x__1; +reg [`BIT_WIDTH-1:0] r_x__2; +reg [`BIT_WIDTH-1:0] r_x__3; +reg [`BIT_WIDTH-1:0] r_x__4; +reg [`BIT_WIDTH-1:0] r_x__5; +reg [`BIT_WIDTH-1:0] r_x__6; +reg [`BIT_WIDTH-1:0] r_x__7; +reg [`BIT_WIDTH-1:0] r_x__8; +reg [`BIT_WIDTH-1:0] r_x__9; +reg [`BIT_WIDTH-1:0] r_x__10; +reg [`BIT_WIDTH-1:0] r_x__11; +reg [`BIT_WIDTH-1:0] r_x__12; +reg [`BIT_WIDTH-1:0] r_x__13; +reg [`BIT_WIDTH-1:0] r_x__14; +reg [`BIT_WIDTH-1:0] r_x__15; +reg [`BIT_WIDTH-1:0] r_x__16; +reg [`BIT_WIDTH-1:0] r_x__17; +reg [`BIT_WIDTH-1:0] r_x__18; +reg [`BIT_WIDTH-1:0] r_x__19; +reg [`BIT_WIDTH-1:0] r_x__20; +reg [`BIT_WIDTH-1:0] r_x__21; +reg [`BIT_WIDTH-1:0] r_x__22; +reg [`BIT_WIDTH-1:0] r_x__23; +reg [`BIT_WIDTH-1:0] r_x__24; +reg [`BIT_WIDTH-1:0] r_x__25; +reg [`BIT_WIDTH-1:0] r_x__26; +reg [`BIT_WIDTH-1:0] r_x__27; +reg [`BIT_WIDTH-1:0] r_x__28; +reg [`BIT_WIDTH-1:0] r_x__29; +reg [`BIT_WIDTH-1:0] r_x__30; +reg [`BIT_WIDTH-1:0] r_x__31; +reg [`BIT_WIDTH-1:0] r_x__32; +reg [`BIT_WIDTH-1:0] r_x__33; +reg [`BIT_WIDTH-1:0] r_x__34; +reg [`BIT_WIDTH-1:0] r_x__35; +reg [`BIT_WIDTH-1:0] r_x__36; +reg [`BIT_WIDTH-1:0] r_x__37; +reg [`BIT_WIDTH-1:0] r_x__38; +reg [`BIT_WIDTH-1:0] r_x__39; +reg [`BIT_WIDTH-1:0] r_x__40; +reg [`BIT_WIDTH-1:0] r_x__41; +reg [`BIT_WIDTH-1:0] r_x__42; +reg [`BIT_WIDTH-1:0] r_x__43; +reg [`BIT_WIDTH-1:0] r_x__44; +reg [`BIT_WIDTH-1:0] r_x__45; +reg [`BIT_WIDTH-1:0] r_x__46; +reg [`BIT_WIDTH-1:0] r_x__47; +reg [`BIT_WIDTH-1:0] r_x__48; +reg [`BIT_WIDTH-1:0] r_x__49; +reg [`BIT_WIDTH-1:0] r_x__50; +reg [`BIT_WIDTH-1:0] r_x__51; +reg [`BIT_WIDTH-1:0] r_x__52; +reg [`BIT_WIDTH-1:0] r_x__53; +reg [`BIT_WIDTH-1:0] r_x__54; +reg [`BIT_WIDTH-1:0] r_x__55; +reg [`BIT_WIDTH-1:0] r_x__56; +reg [`BIT_WIDTH-1:0] r_x__57; +reg [`BIT_WIDTH-1:0] r_x__58; +reg [`BIT_WIDTH-1:0] r_x__59; + +//reg [`BIT_WIDTH-1:0] r_y [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_y__0; +reg [`BIT_WIDTH-1:0] r_y__1; +reg [`BIT_WIDTH-1:0] r_y__2; +reg [`BIT_WIDTH-1:0] r_y__3; +reg [`BIT_WIDTH-1:0] r_y__4; +reg [`BIT_WIDTH-1:0] r_y__5; +reg [`BIT_WIDTH-1:0] r_y__6; +reg [`BIT_WIDTH-1:0] r_y__7; +reg [`BIT_WIDTH-1:0] r_y__8; +reg [`BIT_WIDTH-1:0] r_y__9; +reg [`BIT_WIDTH-1:0] r_y__10; +reg [`BIT_WIDTH-1:0] r_y__11; +reg [`BIT_WIDTH-1:0] r_y__12; +reg [`BIT_WIDTH-1:0] r_y__13; +reg [`BIT_WIDTH-1:0] r_y__14; +reg [`BIT_WIDTH-1:0] r_y__15; +reg [`BIT_WIDTH-1:0] r_y__16; +reg [`BIT_WIDTH-1:0] r_y__17; +reg [`BIT_WIDTH-1:0] r_y__18; +reg [`BIT_WIDTH-1:0] r_y__19; +reg [`BIT_WIDTH-1:0] r_y__20; +reg [`BIT_WIDTH-1:0] r_y__21; +reg [`BIT_WIDTH-1:0] r_y__22; +reg [`BIT_WIDTH-1:0] r_y__23; +reg [`BIT_WIDTH-1:0] r_y__24; +reg [`BIT_WIDTH-1:0] r_y__25; +reg [`BIT_WIDTH-1:0] r_y__26; +reg [`BIT_WIDTH-1:0] r_y__27; +reg [`BIT_WIDTH-1:0] r_y__28; +reg [`BIT_WIDTH-1:0] r_y__29; +reg [`BIT_WIDTH-1:0] r_y__30; +reg [`BIT_WIDTH-1:0] r_y__31; +reg [`BIT_WIDTH-1:0] r_y__32; +reg [`BIT_WIDTH-1:0] r_y__33; +reg [`BIT_WIDTH-1:0] r_y__34; +reg [`BIT_WIDTH-1:0] r_y__35; +reg [`BIT_WIDTH-1:0] r_y__36; +reg [`BIT_WIDTH-1:0] r_y__37; +reg [`BIT_WIDTH-1:0] r_y__38; +reg [`BIT_WIDTH-1:0] r_y__39; +reg [`BIT_WIDTH-1:0] r_y__40; +reg [`BIT_WIDTH-1:0] r_y__41; +reg [`BIT_WIDTH-1:0] r_y__42; +reg [`BIT_WIDTH-1:0] r_y__43; +reg [`BIT_WIDTH-1:0] r_y__44; +reg [`BIT_WIDTH-1:0] r_y__45; +reg [`BIT_WIDTH-1:0] r_y__46; +reg [`BIT_WIDTH-1:0] r_y__47; +reg [`BIT_WIDTH-1:0] r_y__48; +reg [`BIT_WIDTH-1:0] r_y__49; +reg [`BIT_WIDTH-1:0] r_y__50; +reg [`BIT_WIDTH-1:0] r_y__51; +reg [`BIT_WIDTH-1:0] r_y__52; +reg [`BIT_WIDTH-1:0] r_y__53; +reg [`BIT_WIDTH-1:0] r_y__54; +reg [`BIT_WIDTH-1:0] r_y__55; +reg [`BIT_WIDTH-1:0] r_y__56; +reg [`BIT_WIDTH-1:0] r_y__57; +reg [`BIT_WIDTH-1:0] r_y__58; +reg [`BIT_WIDTH-1:0] r_y__59; + + + +//reg [`BIT_WIDTH-1:0] r_z [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_z__0; +reg [`BIT_WIDTH-1:0] r_z__1; +reg [`BIT_WIDTH-1:0] r_z__2; +reg [`BIT_WIDTH-1:0] r_z__3; +reg [`BIT_WIDTH-1:0] r_z__4; +reg [`BIT_WIDTH-1:0] r_z__5; +reg [`BIT_WIDTH-1:0] r_z__6; +reg [`BIT_WIDTH-1:0] r_z__7; +reg [`BIT_WIDTH-1:0] r_z__8; +reg [`BIT_WIDTH-1:0] r_z__9; +reg [`BIT_WIDTH-1:0] r_z__10; +reg [`BIT_WIDTH-1:0] r_z__11; +reg [`BIT_WIDTH-1:0] r_z__12; +reg [`BIT_WIDTH-1:0] r_z__13; +reg [`BIT_WIDTH-1:0] r_z__14; +reg [`BIT_WIDTH-1:0] r_z__15; +reg [`BIT_WIDTH-1:0] r_z__16; +reg [`BIT_WIDTH-1:0] r_z__17; +reg [`BIT_WIDTH-1:0] r_z__18; +reg [`BIT_WIDTH-1:0] r_z__19; +reg [`BIT_WIDTH-1:0] r_z__20; +reg [`BIT_WIDTH-1:0] r_z__21; +reg [`BIT_WIDTH-1:0] r_z__22; +reg [`BIT_WIDTH-1:0] r_z__23; +reg [`BIT_WIDTH-1:0] r_z__24; +reg [`BIT_WIDTH-1:0] r_z__25; +reg [`BIT_WIDTH-1:0] r_z__26; +reg [`BIT_WIDTH-1:0] r_z__27; +reg [`BIT_WIDTH-1:0] r_z__28; +reg [`BIT_WIDTH-1:0] r_z__29; +reg [`BIT_WIDTH-1:0] r_z__30; +reg [`BIT_WIDTH-1:0] r_z__31; +reg [`BIT_WIDTH-1:0] r_z__32; +reg [`BIT_WIDTH-1:0] r_z__33; +reg [`BIT_WIDTH-1:0] r_z__34; +reg [`BIT_WIDTH-1:0] r_z__35; +reg [`BIT_WIDTH-1:0] r_z__36; +reg [`BIT_WIDTH-1:0] r_z__37; +reg [`BIT_WIDTH-1:0] r_z__38; +reg [`BIT_WIDTH-1:0] r_z__39; +reg [`BIT_WIDTH-1:0] r_z__40; +reg [`BIT_WIDTH-1:0] r_z__41; +reg [`BIT_WIDTH-1:0] r_z__42; +reg [`BIT_WIDTH-1:0] r_z__43; +reg [`BIT_WIDTH-1:0] r_z__44; +reg [`BIT_WIDTH-1:0] r_z__45; +reg [`BIT_WIDTH-1:0] r_z__46; +reg [`BIT_WIDTH-1:0] r_z__47; +reg [`BIT_WIDTH-1:0] r_z__48; +reg [`BIT_WIDTH-1:0] r_z__49; +reg [`BIT_WIDTH-1:0] r_z__50; +reg [`BIT_WIDTH-1:0] r_z__51; +reg [`BIT_WIDTH-1:0] r_z__52; +reg [`BIT_WIDTH-1:0] r_z__53; +reg [`BIT_WIDTH-1:0] r_z__54; +reg [`BIT_WIDTH-1:0] r_z__55; +reg [`BIT_WIDTH-1:0] r_z__56; +reg [`BIT_WIDTH-1:0] r_z__57; +reg [`BIT_WIDTH-1:0] r_z__58; +reg [`BIT_WIDTH-1:0] r_z__59; + +//reg [`BIT_WIDTH-1:0] r_ux [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_ux__0; +reg [`BIT_WIDTH-1:0] r_ux__1; +reg [`BIT_WIDTH-1:0] r_ux__2; +reg [`BIT_WIDTH-1:0] r_ux__3; +reg [`BIT_WIDTH-1:0] r_ux__4; +reg [`BIT_WIDTH-1:0] r_ux__5; +reg [`BIT_WIDTH-1:0] r_ux__6; +reg [`BIT_WIDTH-1:0] r_ux__7; +reg [`BIT_WIDTH-1:0] r_ux__8; +reg [`BIT_WIDTH-1:0] r_ux__9; +reg [`BIT_WIDTH-1:0] r_ux__10; +reg [`BIT_WIDTH-1:0] r_ux__11; +reg [`BIT_WIDTH-1:0] r_ux__12; +reg [`BIT_WIDTH-1:0] r_ux__13; +reg [`BIT_WIDTH-1:0] r_ux__14; +reg [`BIT_WIDTH-1:0] r_ux__15; +reg [`BIT_WIDTH-1:0] r_ux__16; +reg [`BIT_WIDTH-1:0] r_ux__17; +reg [`BIT_WIDTH-1:0] r_ux__18; +reg [`BIT_WIDTH-1:0] r_ux__19; +reg [`BIT_WIDTH-1:0] r_ux__20; +reg [`BIT_WIDTH-1:0] r_ux__21; +reg [`BIT_WIDTH-1:0] r_ux__22; +reg [`BIT_WIDTH-1:0] r_ux__23; +reg [`BIT_WIDTH-1:0] r_ux__24; +reg [`BIT_WIDTH-1:0] r_ux__25; +reg [`BIT_WIDTH-1:0] r_ux__26; +reg [`BIT_WIDTH-1:0] r_ux__27; +reg [`BIT_WIDTH-1:0] r_ux__28; +reg [`BIT_WIDTH-1:0] r_ux__29; +reg [`BIT_WIDTH-1:0] r_ux__30; +reg [`BIT_WIDTH-1:0] r_ux__31; +reg [`BIT_WIDTH-1:0] r_ux__32; +reg [`BIT_WIDTH-1:0] r_ux__33; +reg [`BIT_WIDTH-1:0] r_ux__34; +reg [`BIT_WIDTH-1:0] r_ux__35; +reg [`BIT_WIDTH-1:0] r_ux__36; +reg [`BIT_WIDTH-1:0] r_ux__37; +reg [`BIT_WIDTH-1:0] r_ux__38; +reg [`BIT_WIDTH-1:0] r_ux__39; +reg [`BIT_WIDTH-1:0] r_ux__40; +reg [`BIT_WIDTH-1:0] r_ux__41; +reg [`BIT_WIDTH-1:0] r_ux__42; +reg [`BIT_WIDTH-1:0] r_ux__43; +reg [`BIT_WIDTH-1:0] r_ux__44; +reg [`BIT_WIDTH-1:0] r_ux__45; +reg [`BIT_WIDTH-1:0] r_ux__46; +reg [`BIT_WIDTH-1:0] r_ux__47; +reg [`BIT_WIDTH-1:0] r_ux__48; +reg [`BIT_WIDTH-1:0] r_ux__49; +reg [`BIT_WIDTH-1:0] r_ux__50; +reg [`BIT_WIDTH-1:0] r_ux__51; +reg [`BIT_WIDTH-1:0] r_ux__52; +reg [`BIT_WIDTH-1:0] r_ux__53; +reg [`BIT_WIDTH-1:0] r_ux__54; +reg [`BIT_WIDTH-1:0] r_ux__55; +reg [`BIT_WIDTH-1:0] r_ux__56; +reg [`BIT_WIDTH-1:0] r_ux__57; +reg [`BIT_WIDTH-1:0] r_ux__58; +reg [`BIT_WIDTH-1:0] r_ux__59; + +//reg [`BIT_WIDTH-1:0] r_uy [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_uy__0; +reg [`BIT_WIDTH-1:0] r_uy__1; +reg [`BIT_WIDTH-1:0] r_uy__2; +reg [`BIT_WIDTH-1:0] r_uy__3; +reg [`BIT_WIDTH-1:0] r_uy__4; +reg [`BIT_WIDTH-1:0] r_uy__5; +reg [`BIT_WIDTH-1:0] r_uy__6; +reg [`BIT_WIDTH-1:0] r_uy__7; +reg [`BIT_WIDTH-1:0] r_uy__8; +reg [`BIT_WIDTH-1:0] r_uy__9; +reg [`BIT_WIDTH-1:0] r_uy__10; +reg [`BIT_WIDTH-1:0] r_uy__11; +reg [`BIT_WIDTH-1:0] r_uy__12; +reg [`BIT_WIDTH-1:0] r_uy__13; +reg [`BIT_WIDTH-1:0] r_uy__14; +reg [`BIT_WIDTH-1:0] r_uy__15; +reg [`BIT_WIDTH-1:0] r_uy__16; +reg [`BIT_WIDTH-1:0] r_uy__17; +reg [`BIT_WIDTH-1:0] r_uy__18; +reg [`BIT_WIDTH-1:0] r_uy__19; +reg [`BIT_WIDTH-1:0] r_uy__20; +reg [`BIT_WIDTH-1:0] r_uy__21; +reg [`BIT_WIDTH-1:0] r_uy__22; +reg [`BIT_WIDTH-1:0] r_uy__23; +reg [`BIT_WIDTH-1:0] r_uy__24; +reg [`BIT_WIDTH-1:0] r_uy__25; +reg [`BIT_WIDTH-1:0] r_uy__26; +reg [`BIT_WIDTH-1:0] r_uy__27; +reg [`BIT_WIDTH-1:0] r_uy__28; +reg [`BIT_WIDTH-1:0] r_uy__29; +reg [`BIT_WIDTH-1:0] r_uy__30; +reg [`BIT_WIDTH-1:0] r_uy__31; +reg [`BIT_WIDTH-1:0] r_uy__32; +reg [`BIT_WIDTH-1:0] r_uy__33; +reg [`BIT_WIDTH-1:0] r_uy__34; +reg [`BIT_WIDTH-1:0] r_uy__35; +reg [`BIT_WIDTH-1:0] r_uy__36; +reg [`BIT_WIDTH-1:0] r_uy__37; +reg [`BIT_WIDTH-1:0] r_uy__38; +reg [`BIT_WIDTH-1:0] r_uy__39; +reg [`BIT_WIDTH-1:0] r_uy__40; +reg [`BIT_WIDTH-1:0] r_uy__41; +reg [`BIT_WIDTH-1:0] r_uy__42; +reg [`BIT_WIDTH-1:0] r_uy__43; +reg [`BIT_WIDTH-1:0] r_uy__44; +reg [`BIT_WIDTH-1:0] r_uy__45; +reg [`BIT_WIDTH-1:0] r_uy__46; +reg [`BIT_WIDTH-1:0] r_uy__47; +reg [`BIT_WIDTH-1:0] r_uy__48; +reg [`BIT_WIDTH-1:0] r_uy__49; +reg [`BIT_WIDTH-1:0] r_uy__50; +reg [`BIT_WIDTH-1:0] r_uy__51; +reg [`BIT_WIDTH-1:0] r_uy__52; +reg [`BIT_WIDTH-1:0] r_uy__53; +reg [`BIT_WIDTH-1:0] r_uy__54; +reg [`BIT_WIDTH-1:0] r_uy__55; +reg [`BIT_WIDTH-1:0] r_uy__56; +reg [`BIT_WIDTH-1:0] r_uy__57; +reg [`BIT_WIDTH-1:0] r_uy__58; +reg [`BIT_WIDTH-1:0] r_uy__59; + +//reg [`BIT_WIDTH-1:0] r_uz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_uz__0; +reg [`BIT_WIDTH-1:0] r_uz__1; +reg [`BIT_WIDTH-1:0] r_uz__2; +reg [`BIT_WIDTH-1:0] r_uz__3; +reg [`BIT_WIDTH-1:0] r_uz__4; +reg [`BIT_WIDTH-1:0] r_uz__5; +reg [`BIT_WIDTH-1:0] r_uz__6; +reg [`BIT_WIDTH-1:0] r_uz__7; +reg [`BIT_WIDTH-1:0] r_uz__8; +reg [`BIT_WIDTH-1:0] r_uz__9; +reg [`BIT_WIDTH-1:0] r_uz__10; +reg [`BIT_WIDTH-1:0] r_uz__11; +reg [`BIT_WIDTH-1:0] r_uz__12; +reg [`BIT_WIDTH-1:0] r_uz__13; +reg [`BIT_WIDTH-1:0] r_uz__14; +reg [`BIT_WIDTH-1:0] r_uz__15; +reg [`BIT_WIDTH-1:0] r_uz__16; +reg [`BIT_WIDTH-1:0] r_uz__17; +reg [`BIT_WIDTH-1:0] r_uz__18; +reg [`BIT_WIDTH-1:0] r_uz__19; +reg [`BIT_WIDTH-1:0] r_uz__20; +reg [`BIT_WIDTH-1:0] r_uz__21; +reg [`BIT_WIDTH-1:0] r_uz__22; +reg [`BIT_WIDTH-1:0] r_uz__23; +reg [`BIT_WIDTH-1:0] r_uz__24; +reg [`BIT_WIDTH-1:0] r_uz__25; +reg [`BIT_WIDTH-1:0] r_uz__26; +reg [`BIT_WIDTH-1:0] r_uz__27; +reg [`BIT_WIDTH-1:0] r_uz__28; +reg [`BIT_WIDTH-1:0] r_uz__29; +reg [`BIT_WIDTH-1:0] r_uz__30; +reg [`BIT_WIDTH-1:0] r_uz__31; +reg [`BIT_WIDTH-1:0] r_uz__32; +reg [`BIT_WIDTH-1:0] r_uz__33; +reg [`BIT_WIDTH-1:0] r_uz__34; +reg [`BIT_WIDTH-1:0] r_uz__35; +reg [`BIT_WIDTH-1:0] r_uz__36; +reg [`BIT_WIDTH-1:0] r_uz__37; +reg [`BIT_WIDTH-1:0] r_uz__38; +reg [`BIT_WIDTH-1:0] r_uz__39; +reg [`BIT_WIDTH-1:0] r_uz__40; +reg [`BIT_WIDTH-1:0] r_uz__41; +reg [`BIT_WIDTH-1:0] r_uz__42; +reg [`BIT_WIDTH-1:0] r_uz__43; +reg [`BIT_WIDTH-1:0] r_uz__44; +reg [`BIT_WIDTH-1:0] r_uz__45; +reg [`BIT_WIDTH-1:0] r_uz__46; +reg [`BIT_WIDTH-1:0] r_uz__47; +reg [`BIT_WIDTH-1:0] r_uz__48; +reg [`BIT_WIDTH-1:0] r_uz__49; +reg [`BIT_WIDTH-1:0] r_uz__50; +reg [`BIT_WIDTH-1:0] r_uz__51; +reg [`BIT_WIDTH-1:0] r_uz__52; +reg [`BIT_WIDTH-1:0] r_uz__53; +reg [`BIT_WIDTH-1:0] r_uz__54; +reg [`BIT_WIDTH-1:0] r_uz__55; +reg [`BIT_WIDTH-1:0] r_uz__56; +reg [`BIT_WIDTH-1:0] r_uz__57; +reg [`BIT_WIDTH-1:0] r_uz__58; +reg [`BIT_WIDTH-1:0] r_uz__59; + + +//reg [`BIT_WIDTH-1:0] r_sz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sz__0; +reg [`BIT_WIDTH-1:0] r_sz__1; +reg [`BIT_WIDTH-1:0] r_sz__2; +reg [`BIT_WIDTH-1:0] r_sz__3; +reg [`BIT_WIDTH-1:0] r_sz__4; +reg [`BIT_WIDTH-1:0] r_sz__5; +reg [`BIT_WIDTH-1:0] r_sz__6; +reg [`BIT_WIDTH-1:0] r_sz__7; +reg [`BIT_WIDTH-1:0] r_sz__8; +reg [`BIT_WIDTH-1:0] r_sz__9; +reg [`BIT_WIDTH-1:0] r_sz__10; +reg [`BIT_WIDTH-1:0] r_sz__11; +reg [`BIT_WIDTH-1:0] r_sz__12; +reg [`BIT_WIDTH-1:0] r_sz__13; +reg [`BIT_WIDTH-1:0] r_sz__14; +reg [`BIT_WIDTH-1:0] r_sz__15; +reg [`BIT_WIDTH-1:0] r_sz__16; +reg [`BIT_WIDTH-1:0] r_sz__17; +reg [`BIT_WIDTH-1:0] r_sz__18; +reg [`BIT_WIDTH-1:0] r_sz__19; +reg [`BIT_WIDTH-1:0] r_sz__20; +reg [`BIT_WIDTH-1:0] r_sz__21; +reg [`BIT_WIDTH-1:0] r_sz__22; +reg [`BIT_WIDTH-1:0] r_sz__23; +reg [`BIT_WIDTH-1:0] r_sz__24; +reg [`BIT_WIDTH-1:0] r_sz__25; +reg [`BIT_WIDTH-1:0] r_sz__26; +reg [`BIT_WIDTH-1:0] r_sz__27; +reg [`BIT_WIDTH-1:0] r_sz__28; +reg [`BIT_WIDTH-1:0] r_sz__29; +reg [`BIT_WIDTH-1:0] r_sz__30; +reg [`BIT_WIDTH-1:0] r_sz__31; +reg [`BIT_WIDTH-1:0] r_sz__32; +reg [`BIT_WIDTH-1:0] r_sz__33; +reg [`BIT_WIDTH-1:0] r_sz__34; +reg [`BIT_WIDTH-1:0] r_sz__35; +reg [`BIT_WIDTH-1:0] r_sz__36; +reg [`BIT_WIDTH-1:0] r_sz__37; +reg [`BIT_WIDTH-1:0] r_sz__38; +reg [`BIT_WIDTH-1:0] r_sz__39; +reg [`BIT_WIDTH-1:0] r_sz__40; +reg [`BIT_WIDTH-1:0] r_sz__41; +reg [`BIT_WIDTH-1:0] r_sz__42; +reg [`BIT_WIDTH-1:0] r_sz__43; +reg [`BIT_WIDTH-1:0] r_sz__44; +reg [`BIT_WIDTH-1:0] r_sz__45; +reg [`BIT_WIDTH-1:0] r_sz__46; +reg [`BIT_WIDTH-1:0] r_sz__47; +reg [`BIT_WIDTH-1:0] r_sz__48; +reg [`BIT_WIDTH-1:0] r_sz__49; +reg [`BIT_WIDTH-1:0] r_sz__50; +reg [`BIT_WIDTH-1:0] r_sz__51; +reg [`BIT_WIDTH-1:0] r_sz__52; +reg [`BIT_WIDTH-1:0] r_sz__53; +reg [`BIT_WIDTH-1:0] r_sz__54; +reg [`BIT_WIDTH-1:0] r_sz__55; +reg [`BIT_WIDTH-1:0] r_sz__56; +reg [`BIT_WIDTH-1:0] r_sz__57; +reg [`BIT_WIDTH-1:0] r_sz__58; +reg [`BIT_WIDTH-1:0] r_sz__59; + +//reg [`BIT_WIDTH-1:0] r_sr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sr__0; +reg [`BIT_WIDTH-1:0] r_sr__1; +reg [`BIT_WIDTH-1:0] r_sr__2; +reg [`BIT_WIDTH-1:0] r_sr__3; +reg [`BIT_WIDTH-1:0] r_sr__4; +reg [`BIT_WIDTH-1:0] r_sr__5; +reg [`BIT_WIDTH-1:0] r_sr__6; +reg [`BIT_WIDTH-1:0] r_sr__7; +reg [`BIT_WIDTH-1:0] r_sr__8; +reg [`BIT_WIDTH-1:0] r_sr__9; +reg [`BIT_WIDTH-1:0] r_sr__10; +reg [`BIT_WIDTH-1:0] r_sr__11; +reg [`BIT_WIDTH-1:0] r_sr__12; +reg [`BIT_WIDTH-1:0] r_sr__13; +reg [`BIT_WIDTH-1:0] r_sr__14; +reg [`BIT_WIDTH-1:0] r_sr__15; +reg [`BIT_WIDTH-1:0] r_sr__16; +reg [`BIT_WIDTH-1:0] r_sr__17; +reg [`BIT_WIDTH-1:0] r_sr__18; +reg [`BIT_WIDTH-1:0] r_sr__19; +reg [`BIT_WIDTH-1:0] r_sr__20; +reg [`BIT_WIDTH-1:0] r_sr__21; +reg [`BIT_WIDTH-1:0] r_sr__22; +reg [`BIT_WIDTH-1:0] r_sr__23; +reg [`BIT_WIDTH-1:0] r_sr__24; +reg [`BIT_WIDTH-1:0] r_sr__25; +reg [`BIT_WIDTH-1:0] r_sr__26; +reg [`BIT_WIDTH-1:0] r_sr__27; +reg [`BIT_WIDTH-1:0] r_sr__28; +reg [`BIT_WIDTH-1:0] r_sr__29; +reg [`BIT_WIDTH-1:0] r_sr__30; +reg [`BIT_WIDTH-1:0] r_sr__31; +reg [`BIT_WIDTH-1:0] r_sr__32; +reg [`BIT_WIDTH-1:0] r_sr__33; +reg [`BIT_WIDTH-1:0] r_sr__34; +reg [`BIT_WIDTH-1:0] r_sr__35; +reg [`BIT_WIDTH-1:0] r_sr__36; +reg [`BIT_WIDTH-1:0] r_sr__37; +reg [`BIT_WIDTH-1:0] r_sr__38; +reg [`BIT_WIDTH-1:0] r_sr__39; +reg [`BIT_WIDTH-1:0] r_sr__40; +reg [`BIT_WIDTH-1:0] r_sr__41; +reg [`BIT_WIDTH-1:0] r_sr__42; +reg [`BIT_WIDTH-1:0] r_sr__43; +reg [`BIT_WIDTH-1:0] r_sr__44; +reg [`BIT_WIDTH-1:0] r_sr__45; +reg [`BIT_WIDTH-1:0] r_sr__46; +reg [`BIT_WIDTH-1:0] r_sr__47; +reg [`BIT_WIDTH-1:0] r_sr__48; +reg [`BIT_WIDTH-1:0] r_sr__49; +reg [`BIT_WIDTH-1:0] r_sr__50; +reg [`BIT_WIDTH-1:0] r_sr__51; +reg [`BIT_WIDTH-1:0] r_sr__52; +reg [`BIT_WIDTH-1:0] r_sr__53; +reg [`BIT_WIDTH-1:0] r_sr__54; +reg [`BIT_WIDTH-1:0] r_sr__55; +reg [`BIT_WIDTH-1:0] r_sr__56; +reg [`BIT_WIDTH-1:0] r_sr__57; +reg [`BIT_WIDTH-1:0] r_sr__58; +reg [`BIT_WIDTH-1:0] r_sr__59; + +//reg [`BIT_WIDTH-1:0] r_sleftz [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sleftz__0; +reg [`BIT_WIDTH-1:0] r_sleftz__1; +reg [`BIT_WIDTH-1:0] r_sleftz__2; +reg [`BIT_WIDTH-1:0] r_sleftz__3; +reg [`BIT_WIDTH-1:0] r_sleftz__4; +reg [`BIT_WIDTH-1:0] r_sleftz__5; +reg [`BIT_WIDTH-1:0] r_sleftz__6; +reg [`BIT_WIDTH-1:0] r_sleftz__7; +reg [`BIT_WIDTH-1:0] r_sleftz__8; +reg [`BIT_WIDTH-1:0] r_sleftz__9; +reg [`BIT_WIDTH-1:0] r_sleftz__10; +reg [`BIT_WIDTH-1:0] r_sleftz__11; +reg [`BIT_WIDTH-1:0] r_sleftz__12; +reg [`BIT_WIDTH-1:0] r_sleftz__13; +reg [`BIT_WIDTH-1:0] r_sleftz__14; +reg [`BIT_WIDTH-1:0] r_sleftz__15; +reg [`BIT_WIDTH-1:0] r_sleftz__16; +reg [`BIT_WIDTH-1:0] r_sleftz__17; +reg [`BIT_WIDTH-1:0] r_sleftz__18; +reg [`BIT_WIDTH-1:0] r_sleftz__19; +reg [`BIT_WIDTH-1:0] r_sleftz__20; +reg [`BIT_WIDTH-1:0] r_sleftz__21; +reg [`BIT_WIDTH-1:0] r_sleftz__22; +reg [`BIT_WIDTH-1:0] r_sleftz__23; +reg [`BIT_WIDTH-1:0] r_sleftz__24; +reg [`BIT_WIDTH-1:0] r_sleftz__25; +reg [`BIT_WIDTH-1:0] r_sleftz__26; +reg [`BIT_WIDTH-1:0] r_sleftz__27; +reg [`BIT_WIDTH-1:0] r_sleftz__28; +reg [`BIT_WIDTH-1:0] r_sleftz__29; +reg [`BIT_WIDTH-1:0] r_sleftz__30; +reg [`BIT_WIDTH-1:0] r_sleftz__31; +reg [`BIT_WIDTH-1:0] r_sleftz__32; +reg [`BIT_WIDTH-1:0] r_sleftz__33; +reg [`BIT_WIDTH-1:0] r_sleftz__34; +reg [`BIT_WIDTH-1:0] r_sleftz__35; +reg [`BIT_WIDTH-1:0] r_sleftz__36; +reg [`BIT_WIDTH-1:0] r_sleftz__37; +reg [`BIT_WIDTH-1:0] r_sleftz__38; +reg [`BIT_WIDTH-1:0] r_sleftz__39; +reg [`BIT_WIDTH-1:0] r_sleftz__40; +reg [`BIT_WIDTH-1:0] r_sleftz__41; +reg [`BIT_WIDTH-1:0] r_sleftz__42; +reg [`BIT_WIDTH-1:0] r_sleftz__43; +reg [`BIT_WIDTH-1:0] r_sleftz__44; +reg [`BIT_WIDTH-1:0] r_sleftz__45; +reg [`BIT_WIDTH-1:0] r_sleftz__46; +reg [`BIT_WIDTH-1:0] r_sleftz__47; +reg [`BIT_WIDTH-1:0] r_sleftz__48; +reg [`BIT_WIDTH-1:0] r_sleftz__49; +reg [`BIT_WIDTH-1:0] r_sleftz__50; +reg [`BIT_WIDTH-1:0] r_sleftz__51; +reg [`BIT_WIDTH-1:0] r_sleftz__52; +reg [`BIT_WIDTH-1:0] r_sleftz__53; +reg [`BIT_WIDTH-1:0] r_sleftz__54; +reg [`BIT_WIDTH-1:0] r_sleftz__55; +reg [`BIT_WIDTH-1:0] r_sleftz__56; +reg [`BIT_WIDTH-1:0] r_sleftz__57; +reg [`BIT_WIDTH-1:0] r_sleftz__58; +reg [`BIT_WIDTH-1:0] r_sleftz__59; + + + +//reg [`BIT_WIDTH-1:0] r_sleftr [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_sleftr__0; +reg [`BIT_WIDTH-1:0] r_sleftr__1; +reg [`BIT_WIDTH-1:0] r_sleftr__2; +reg [`BIT_WIDTH-1:0] r_sleftr__3; +reg [`BIT_WIDTH-1:0] r_sleftr__4; +reg [`BIT_WIDTH-1:0] r_sleftr__5; +reg [`BIT_WIDTH-1:0] r_sleftr__6; +reg [`BIT_WIDTH-1:0] r_sleftr__7; +reg [`BIT_WIDTH-1:0] r_sleftr__8; +reg [`BIT_WIDTH-1:0] r_sleftr__9; +reg [`BIT_WIDTH-1:0] r_sleftr__10; +reg [`BIT_WIDTH-1:0] r_sleftr__11; +reg [`BIT_WIDTH-1:0] r_sleftr__12; +reg [`BIT_WIDTH-1:0] r_sleftr__13; + +reg [`BIT_WIDTH-1:0] r_sleftr__14; +reg [`BIT_WIDTH-1:0] r_sleftr__15; +reg [`BIT_WIDTH-1:0] r_sleftr__16; +reg [`BIT_WIDTH-1:0] r_sleftr__17; +reg [`BIT_WIDTH-1:0] r_sleftr__18; +reg [`BIT_WIDTH-1:0] r_sleftr__19; +reg [`BIT_WIDTH-1:0] r_sleftr__20; +reg [`BIT_WIDTH-1:0] r_sleftr__21; +reg [`BIT_WIDTH-1:0] r_sleftr__22; +reg [`BIT_WIDTH-1:0] r_sleftr__23; +reg [`BIT_WIDTH-1:0] r_sleftr__24; +reg [`BIT_WIDTH-1:0] r_sleftr__25; +reg [`BIT_WIDTH-1:0] r_sleftr__26; +reg [`BIT_WIDTH-1:0] r_sleftr__27; +reg [`BIT_WIDTH-1:0] r_sleftr__28; +reg [`BIT_WIDTH-1:0] r_sleftr__29; +reg [`BIT_WIDTH-1:0] r_sleftr__30; +reg [`BIT_WIDTH-1:0] r_sleftr__31; +reg [`BIT_WIDTH-1:0] r_sleftr__32; +reg [`BIT_WIDTH-1:0] r_sleftr__33; +reg [`BIT_WIDTH-1:0] r_sleftr__34; +reg [`BIT_WIDTH-1:0] r_sleftr__35; +reg [`BIT_WIDTH-1:0] r_sleftr__36; +reg [`BIT_WIDTH-1:0] r_sleftr__37; +reg [`BIT_WIDTH-1:0] r_sleftr__38; +reg [`BIT_WIDTH-1:0] r_sleftr__39; +reg [`BIT_WIDTH-1:0] r_sleftr__40; +reg [`BIT_WIDTH-1:0] r_sleftr__41; +reg [`BIT_WIDTH-1:0] r_sleftr__42; +reg [`BIT_WIDTH-1:0] r_sleftr__43; +reg [`BIT_WIDTH-1:0] r_sleftr__44; +reg [`BIT_WIDTH-1:0] r_sleftr__45; +reg [`BIT_WIDTH-1:0] r_sleftr__46; +reg [`BIT_WIDTH-1:0] r_sleftr__47; +reg [`BIT_WIDTH-1:0] r_sleftr__48; +reg [`BIT_WIDTH-1:0] r_sleftr__49; +reg [`BIT_WIDTH-1:0] r_sleftr__50; +reg [`BIT_WIDTH-1:0] r_sleftr__51; +reg [`BIT_WIDTH-1:0] r_sleftr__52; +reg [`BIT_WIDTH-1:0] r_sleftr__53; +reg [`BIT_WIDTH-1:0] r_sleftr__54; +reg [`BIT_WIDTH-1:0] r_sleftr__55; +reg [`BIT_WIDTH-1:0] r_sleftr__56; +reg [`BIT_WIDTH-1:0] r_sleftr__57; +reg [`BIT_WIDTH-1:0] r_sleftr__58; +reg [`BIT_WIDTH-1:0] r_sleftr__59; + + +//reg [`BIT_WIDTH-1:0] r_weight [TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_weight__0; +reg [`BIT_WIDTH-1:0] r_weight__1; +reg [`BIT_WIDTH-1:0] r_weight__2; +reg [`BIT_WIDTH-1:0] r_weight__3; +reg [`BIT_WIDTH-1:0] r_weight__4; +reg [`BIT_WIDTH-1:0] r_weight__5; +reg [`BIT_WIDTH-1:0] r_weight__6; +reg [`BIT_WIDTH-1:0] r_weight__7; +reg [`BIT_WIDTH-1:0] r_weight__8; +reg [`BIT_WIDTH-1:0] r_weight__9; +reg [`BIT_WIDTH-1:0] r_weight__10; +reg [`BIT_WIDTH-1:0] r_weight__11; +reg [`BIT_WIDTH-1:0] r_weight__12; +reg [`BIT_WIDTH-1:0] r_weight__13; +reg [`BIT_WIDTH-1:0] r_weight__14; +reg [`BIT_WIDTH-1:0] r_weight__15; +reg [`BIT_WIDTH-1:0] r_weight__16; +reg [`BIT_WIDTH-1:0] r_weight__17; +reg [`BIT_WIDTH-1:0] r_weight__18; +reg [`BIT_WIDTH-1:0] r_weight__19; +reg [`BIT_WIDTH-1:0] r_weight__20; +reg [`BIT_WIDTH-1:0] r_weight__21; +reg [`BIT_WIDTH-1:0] r_weight__22; +reg [`BIT_WIDTH-1:0] r_weight__23; +reg [`BIT_WIDTH-1:0] r_weight__24; +reg [`BIT_WIDTH-1:0] r_weight__25; +reg [`BIT_WIDTH-1:0] r_weight__26; +reg [`BIT_WIDTH-1:0] r_weight__27; +reg [`BIT_WIDTH-1:0] r_weight__28; +reg [`BIT_WIDTH-1:0] r_weight__29; +reg [`BIT_WIDTH-1:0] r_weight__30; +reg [`BIT_WIDTH-1:0] r_weight__31; +reg [`BIT_WIDTH-1:0] r_weight__32; +reg [`BIT_WIDTH-1:0] r_weight__33; +reg [`BIT_WIDTH-1:0] r_weight__34; +reg [`BIT_WIDTH-1:0] r_weight__35; +reg [`BIT_WIDTH-1:0] r_weight__36; +reg [`BIT_WIDTH-1:0] r_weight__37; +reg [`BIT_WIDTH-1:0] r_weight__38; +reg [`BIT_WIDTH-1:0] r_weight__39; +reg [`BIT_WIDTH-1:0] r_weight__40; +reg [`BIT_WIDTH-1:0] r_weight__41; +reg [`BIT_WIDTH-1:0] r_weight__42; +reg [`BIT_WIDTH-1:0] r_weight__43; +reg [`BIT_WIDTH-1:0] r_weight__44; +reg [`BIT_WIDTH-1:0] r_weight__45; +reg [`BIT_WIDTH-1:0] r_weight__46; +reg [`BIT_WIDTH-1:0] r_weight__47; +reg [`BIT_WIDTH-1:0] r_weight__48; +reg [`BIT_WIDTH-1:0] r_weight__49; +reg [`BIT_WIDTH-1:0] r_weight__50; +reg [`BIT_WIDTH-1:0] r_weight__51; +reg [`BIT_WIDTH-1:0] r_weight__52; +reg [`BIT_WIDTH-1:0] r_weight__53; +reg [`BIT_WIDTH-1:0] r_weight__54; +reg [`BIT_WIDTH-1:0] r_weight__55; +reg [`BIT_WIDTH-1:0] r_weight__56; +reg [`BIT_WIDTH-1:0] r_weight__57; +reg [`BIT_WIDTH-1:0] r_weight__58; +reg [`BIT_WIDTH-1:0] r_weight__59; + +//reg [`LAYER_WIDTH-1:0] r_layer [TOTAL_LATENCY - 1:0]; + +reg [`LAYER_WIDTH-1:0] r_layer__0; +reg [`LAYER_WIDTH-1:0] r_layer__1; +reg [`LAYER_WIDTH-1:0] r_layer__2; +reg [`LAYER_WIDTH-1:0] r_layer__3; +reg [`LAYER_WIDTH-1:0] r_layer__4; +reg [`LAYER_WIDTH-1:0] r_layer__5; +reg [`LAYER_WIDTH-1:0] r_layer__6; +reg [`LAYER_WIDTH-1:0] r_layer__7; +reg [`LAYER_WIDTH-1:0] r_layer__8; +reg [`LAYER_WIDTH-1:0] r_layer__9; +reg [`LAYER_WIDTH-1:0] r_layer__10; +reg [`LAYER_WIDTH-1:0] r_layer__11; +reg [`LAYER_WIDTH-1:0] r_layer__12; +reg [`LAYER_WIDTH-1:0] r_layer__13; +reg [`LAYER_WIDTH-1:0] r_layer__14; +reg [`LAYER_WIDTH-1:0] r_layer__15; +reg [`LAYER_WIDTH-1:0] r_layer__16; +reg [`LAYER_WIDTH-1:0] r_layer__17; +reg [`LAYER_WIDTH-1:0] r_layer__18; +reg [`LAYER_WIDTH-1:0] r_layer__19; +reg [`LAYER_WIDTH-1:0] r_layer__20; +reg [`LAYER_WIDTH-1:0] r_layer__21; +reg [`LAYER_WIDTH-1:0] r_layer__22; +reg [`LAYER_WIDTH-1:0] r_layer__23; +reg [`LAYER_WIDTH-1:0] r_layer__24; +reg [`LAYER_WIDTH-1:0] r_layer__25; +reg [`LAYER_WIDTH-1:0] r_layer__26; +reg [`LAYER_WIDTH-1:0] r_layer__27; +reg [`LAYER_WIDTH-1:0] r_layer__28; +reg [`LAYER_WIDTH-1:0] r_layer__29; +reg [`LAYER_WIDTH-1:0] r_layer__30; +reg [`LAYER_WIDTH-1:0] r_layer__31; +reg [`LAYER_WIDTH-1:0] r_layer__32; +reg [`LAYER_WIDTH-1:0] r_layer__33; +reg [`LAYER_WIDTH-1:0] r_layer__34; +reg [`LAYER_WIDTH-1:0] r_layer__35; +reg [`LAYER_WIDTH-1:0] r_layer__36; +reg [`LAYER_WIDTH-1:0] r_layer__37; +reg [`LAYER_WIDTH-1:0] r_layer__38; +reg [`LAYER_WIDTH-1:0] r_layer__39; +reg [`LAYER_WIDTH-1:0] r_layer__40; +reg [`LAYER_WIDTH-1:0] r_layer__41; +reg [`LAYER_WIDTH-1:0] r_layer__42; +reg [`LAYER_WIDTH-1:0] r_layer__43; +reg [`LAYER_WIDTH-1:0] r_layer__44; +reg [`LAYER_WIDTH-1:0] r_layer__45; +reg [`LAYER_WIDTH-1:0] r_layer__46; +reg [`LAYER_WIDTH-1:0] r_layer__47; +reg [`LAYER_WIDTH-1:0] r_layer__48; +reg [`LAYER_WIDTH-1:0] r_layer__49; +reg [`LAYER_WIDTH-1:0] r_layer__50; +reg [`LAYER_WIDTH-1:0] r_layer__51; +reg [`LAYER_WIDTH-1:0] r_layer__52; +reg [`LAYER_WIDTH-1:0] r_layer__53; +reg [`LAYER_WIDTH-1:0] r_layer__54; +reg [`LAYER_WIDTH-1:0] r_layer__55; +reg [`LAYER_WIDTH-1:0] r_layer__56; +reg [`LAYER_WIDTH-1:0] r_layer__57; +reg [`LAYER_WIDTH-1:0] r_layer__58; +reg [`LAYER_WIDTH-1:0] r_layer__59; + +//reg r_dead [TOTAL_LATENCY - 1:0]; + +reg r_dead__0; +reg r_dead__1; +reg r_dead__2; +reg r_dead__3; +reg r_dead__4; +reg r_dead__5; +reg r_dead__6; +reg r_dead__7; +reg r_dead__8; +reg r_dead__9; +reg r_dead__10; +reg r_dead__11; +reg r_dead__12; +reg r_dead__13; +reg r_dead__14; +reg r_dead__15; +reg r_dead__16; +reg r_dead__17; +reg r_dead__18; +reg r_dead__19; +reg r_dead__20; +reg r_dead__21; +reg r_dead__22; +reg r_dead__23; +reg r_dead__24; +reg r_dead__25; +reg r_dead__26; +reg r_dead__27; +reg r_dead__28; +reg r_dead__29; +reg r_dead__30; +reg r_dead__31; +reg r_dead__32; +reg r_dead__33; +reg r_dead__34; +reg r_dead__35; +reg r_dead__36; +reg r_dead__37; +reg r_dead__38; +reg r_dead__39; +reg r_dead__40; +reg r_dead__41; +reg r_dead__42; +reg r_dead__43; +reg r_dead__44; +reg r_dead__45; +reg r_dead__46; +reg r_dead__47; +reg r_dead__48; +reg r_dead__49; +reg r_dead__50; +reg r_dead__51; +reg r_dead__52; +reg r_dead__53; +reg r_dead__54; +reg r_dead__55; +reg r_dead__56; +reg r_dead__57; +reg r_dead__58; +reg r_dead__59; + +//reg r_hit [TOTAL_LATENCY - 1:0]; + +reg r_hit__0; +reg r_hit__1; +reg r_hit__2; +reg r_hit__3; +reg r_hit__4; +reg r_hit__5; +reg r_hit__6; +reg r_hit__7; +reg r_hit__8; +reg r_hit__9; +reg r_hit__10; +reg r_hit__11; +reg r_hit__12; +reg r_hit__13; +reg r_hit__14; +reg r_hit__15; +reg r_hit__16; +reg r_hit__17; +reg r_hit__18; +reg r_hit__19; +reg r_hit__20; +reg r_hit__21; +reg r_hit__22; +reg r_hit__23; +reg r_hit__24; +reg r_hit__25; +reg r_hit__26; +reg r_hit__27; +reg r_hit__28; +reg r_hit__29; +reg r_hit__30; +reg r_hit__31; +reg r_hit__32; +reg r_hit__33; +reg r_hit__34; +reg r_hit__35; +reg r_hit__36; +reg r_hit__37; +reg r_hit__38; +reg r_hit__39; +reg r_hit__40; +reg r_hit__41; +reg r_hit__42; +reg r_hit__43; +reg r_hit__44; +reg r_hit__45; +reg r_hit__46; +reg r_hit__47; +reg r_hit__48; +reg r_hit__49; +reg r_hit__50; +reg r_hit__51; +reg r_hit__52; +reg r_hit__53; +reg r_hit__54; +reg r_hit__55; +reg r_hit__56; +reg r_hit__57; +reg r_hit__58; +reg r_hit__59; + +//reg [`BIT_WIDTH-1:0] r_diff[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_diff__0; +reg [`BIT_WIDTH-1:0] r_diff__1; +reg [`BIT_WIDTH-1:0] r_diff__2; +reg [`BIT_WIDTH-1:0] r_diff__3; +reg [`BIT_WIDTH-1:0] r_diff__4; +reg [`BIT_WIDTH-1:0] r_diff__5; +reg [`BIT_WIDTH-1:0] r_diff__6; +reg [`BIT_WIDTH-1:0] r_diff__7; +reg [`BIT_WIDTH-1:0] r_diff__8; +reg [`BIT_WIDTH-1:0] r_diff__9; +reg [`BIT_WIDTH-1:0] r_diff__10; +reg [`BIT_WIDTH-1:0] r_diff__11; +reg [`BIT_WIDTH-1:0] r_diff__12; +reg [`BIT_WIDTH-1:0] r_diff__13; +reg [`BIT_WIDTH-1:0] r_diff__14; +reg [`BIT_WIDTH-1:0] r_diff__15; +reg [`BIT_WIDTH-1:0] r_diff__16; +reg [`BIT_WIDTH-1:0] r_diff__17; +reg [`BIT_WIDTH-1:0] r_diff__18; +reg [`BIT_WIDTH-1:0] r_diff__19; +reg [`BIT_WIDTH-1:0] r_diff__20; +reg [`BIT_WIDTH-1:0] r_diff__21; +reg [`BIT_WIDTH-1:0] r_diff__22; +reg [`BIT_WIDTH-1:0] r_diff__23; +reg [`BIT_WIDTH-1:0] r_diff__24; +reg [`BIT_WIDTH-1:0] r_diff__25; +reg [`BIT_WIDTH-1:0] r_diff__26; +reg [`BIT_WIDTH-1:0] r_diff__27; +reg [`BIT_WIDTH-1:0] r_diff__28; +reg [`BIT_WIDTH-1:0] r_diff__29; +reg [`BIT_WIDTH-1:0] r_diff__30; +reg [`BIT_WIDTH-1:0] r_diff__31; +reg [`BIT_WIDTH-1:0] r_diff__32; +reg [`BIT_WIDTH-1:0] r_diff__33; +reg [`BIT_WIDTH-1:0] r_diff__34; +reg [`BIT_WIDTH-1:0] r_diff__35; +reg [`BIT_WIDTH-1:0] r_diff__36; +reg [`BIT_WIDTH-1:0] r_diff__37; +reg [`BIT_WIDTH-1:0] r_diff__38; +reg [`BIT_WIDTH-1:0] r_diff__39; +reg [`BIT_WIDTH-1:0] r_diff__40; +reg [`BIT_WIDTH-1:0] r_diff__41; +reg [`BIT_WIDTH-1:0] r_diff__42; +reg [`BIT_WIDTH-1:0] r_diff__43; +reg [`BIT_WIDTH-1:0] r_diff__44; +reg [`BIT_WIDTH-1:0] r_diff__45; +reg [`BIT_WIDTH-1:0] r_diff__46; +reg [`BIT_WIDTH-1:0] r_diff__47; +reg [`BIT_WIDTH-1:0] r_diff__48; +reg [`BIT_WIDTH-1:0] r_diff__49; +reg [`BIT_WIDTH-1:0] r_diff__50; +reg [`BIT_WIDTH-1:0] r_diff__51; +reg [`BIT_WIDTH-1:0] r_diff__52; +reg [`BIT_WIDTH-1:0] r_diff__53; +reg [`BIT_WIDTH-1:0] r_diff__54; +reg [`BIT_WIDTH-1:0] r_diff__55; +reg [`BIT_WIDTH-1:0] r_diff__56; +reg [`BIT_WIDTH-1:0] r_diff__57; +reg [`BIT_WIDTH-1:0] r_diff__58; +reg [`BIT_WIDTH-1:0] r_diff__59; + +//reg [`BIT_WIDTH-1:0] r_dl_b[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_dl_b__0; +reg [`BIT_WIDTH-1:0] r_dl_b__1; +reg [`BIT_WIDTH-1:0] r_dl_b__2; +reg [`BIT_WIDTH-1:0] r_dl_b__3; +reg [`BIT_WIDTH-1:0] r_dl_b__4; +reg [`BIT_WIDTH-1:0] r_dl_b__5; +reg [`BIT_WIDTH-1:0] r_dl_b__6; +reg [`BIT_WIDTH-1:0] r_dl_b__7; +reg [`BIT_WIDTH-1:0] r_dl_b__8; +reg [`BIT_WIDTH-1:0] r_dl_b__9; +reg [`BIT_WIDTH-1:0] r_dl_b__10; +reg [`BIT_WIDTH-1:0] r_dl_b__11; +reg [`BIT_WIDTH-1:0] r_dl_b__12; +reg [`BIT_WIDTH-1:0] r_dl_b__13; +reg [`BIT_WIDTH-1:0] r_dl_b__14; +reg [`BIT_WIDTH-1:0] r_dl_b__15; +reg [`BIT_WIDTH-1:0] r_dl_b__16; +reg [`BIT_WIDTH-1:0] r_dl_b__17; +reg [`BIT_WIDTH-1:0] r_dl_b__18; +reg [`BIT_WIDTH-1:0] r_dl_b__19; +reg [`BIT_WIDTH-1:0] r_dl_b__20; +reg [`BIT_WIDTH-1:0] r_dl_b__21; +reg [`BIT_WIDTH-1:0] r_dl_b__22; +reg [`BIT_WIDTH-1:0] r_dl_b__23; +reg [`BIT_WIDTH-1:0] r_dl_b__24; +reg [`BIT_WIDTH-1:0] r_dl_b__25; +reg [`BIT_WIDTH-1:0] r_dl_b__26; +reg [`BIT_WIDTH-1:0] r_dl_b__27; +reg [`BIT_WIDTH-1:0] r_dl_b__28; +reg [`BIT_WIDTH-1:0] r_dl_b__29; +reg [`BIT_WIDTH-1:0] r_dl_b__30; +reg [`BIT_WIDTH-1:0] r_dl_b__31; +reg [`BIT_WIDTH-1:0] r_dl_b__32; +reg [`BIT_WIDTH-1:0] r_dl_b__33; +reg [`BIT_WIDTH-1:0] r_dl_b__34; +reg [`BIT_WIDTH-1:0] r_dl_b__35; +reg [`BIT_WIDTH-1:0] r_dl_b__36; +reg [`BIT_WIDTH-1:0] r_dl_b__37; +reg [`BIT_WIDTH-1:0] r_dl_b__38; +reg [`BIT_WIDTH-1:0] r_dl_b__39; +reg [`BIT_WIDTH-1:0] r_dl_b__40; +reg [`BIT_WIDTH-1:0] r_dl_b__41; +reg [`BIT_WIDTH-1:0] r_dl_b__42; +reg [`BIT_WIDTH-1:0] r_dl_b__43; +reg [`BIT_WIDTH-1:0] r_dl_b__44; +reg [`BIT_WIDTH-1:0] r_dl_b__45; +reg [`BIT_WIDTH-1:0] r_dl_b__46; +reg [`BIT_WIDTH-1:0] r_dl_b__47; +reg [`BIT_WIDTH-1:0] r_dl_b__48; +reg [`BIT_WIDTH-1:0] r_dl_b__49; +reg [`BIT_WIDTH-1:0] r_dl_b__50; +reg [`BIT_WIDTH-1:0] r_dl_b__51; +reg [`BIT_WIDTH-1:0] r_dl_b__52; +reg [`BIT_WIDTH-1:0] r_dl_b__53; +reg [`BIT_WIDTH-1:0] r_dl_b__54; +reg [`BIT_WIDTH-1:0] r_dl_b__55; +reg [`BIT_WIDTH-1:0] r_dl_b__56; +reg [`BIT_WIDTH-1:0] r_dl_b__57; +reg [`BIT_WIDTH-1:0] r_dl_b__58; +reg [`BIT_WIDTH-1:0] r_dl_b__59; + +//reg [2*`BIT_WIDTH-1:0] r_numer[TOTAL_LATENCY - 1:0]; + +reg [2*`BIT_WIDTH-1:0] r_numer__0; +reg [2*`BIT_WIDTH-1:0] r_numer__1; +reg [2*`BIT_WIDTH-1:0] r_numer__2; +reg [2*`BIT_WIDTH-1:0] r_numer__3; +reg [2*`BIT_WIDTH-1:0] r_numer__4; +reg [2*`BIT_WIDTH-1:0] r_numer__5; +reg [2*`BIT_WIDTH-1:0] r_numer__6; +reg [2*`BIT_WIDTH-1:0] r_numer__7; +reg [2*`BIT_WIDTH-1:0] r_numer__8; +reg [2*`BIT_WIDTH-1:0] r_numer__9; +reg [2*`BIT_WIDTH-1:0] r_numer__10; +reg [2*`BIT_WIDTH-1:0] r_numer__11; +reg [2*`BIT_WIDTH-1:0] r_numer__12; +reg [2*`BIT_WIDTH-1:0] r_numer__13; +reg [2*`BIT_WIDTH-1:0] r_numer__14; +reg [2*`BIT_WIDTH-1:0] r_numer__15; +reg [2*`BIT_WIDTH-1:0] r_numer__16; +reg [2*`BIT_WIDTH-1:0] r_numer__17; +reg [2*`BIT_WIDTH-1:0] r_numer__18; +reg [2*`BIT_WIDTH-1:0] r_numer__19; +reg [2*`BIT_WIDTH-1:0] r_numer__20; +reg [2*`BIT_WIDTH-1:0] r_numer__21; +reg [2*`BIT_WIDTH-1:0] r_numer__22; +reg [2*`BIT_WIDTH-1:0] r_numer__23; +reg [2*`BIT_WIDTH-1:0] r_numer__24; +reg [2*`BIT_WIDTH-1:0] r_numer__25; +reg [2*`BIT_WIDTH-1:0] r_numer__26; +reg [2*`BIT_WIDTH-1:0] r_numer__27; +reg [2*`BIT_WIDTH-1:0] r_numer__28; +reg [2*`BIT_WIDTH-1:0] r_numer__29; +reg [2*`BIT_WIDTH-1:0] r_numer__30; +reg [2*`BIT_WIDTH-1:0] r_numer__31; +reg [2*`BIT_WIDTH-1:0] r_numer__32; +reg [2*`BIT_WIDTH-1:0] r_numer__33; +reg [2*`BIT_WIDTH-1:0] r_numer__34; +reg [2*`BIT_WIDTH-1:0] r_numer__35; +reg [2*`BIT_WIDTH-1:0] r_numer__36; +reg [2*`BIT_WIDTH-1:0] r_numer__37; +reg [2*`BIT_WIDTH-1:0] r_numer__38; +reg [2*`BIT_WIDTH-1:0] r_numer__39; +reg [2*`BIT_WIDTH-1:0] r_numer__40; +reg [2*`BIT_WIDTH-1:0] r_numer__41; +reg [2*`BIT_WIDTH-1:0] r_numer__42; +reg [2*`BIT_WIDTH-1:0] r_numer__43; +reg [2*`BIT_WIDTH-1:0] r_numer__44; +reg [2*`BIT_WIDTH-1:0] r_numer__45; +reg [2*`BIT_WIDTH-1:0] r_numer__46; +reg [2*`BIT_WIDTH-1:0] r_numer__47; +reg [2*`BIT_WIDTH-1:0] r_numer__48; +reg [2*`BIT_WIDTH-1:0] r_numer__49; +reg [2*`BIT_WIDTH-1:0] r_numer__50; +reg [2*`BIT_WIDTH-1:0] r_numer__51; +reg [2*`BIT_WIDTH-1:0] r_numer__52; +reg [2*`BIT_WIDTH-1:0] r_numer__53; +reg [2*`BIT_WIDTH-1:0] r_numer__54; +reg [2*`BIT_WIDTH-1:0] r_numer__55; +reg [2*`BIT_WIDTH-1:0] r_numer__56; +reg [2*`BIT_WIDTH-1:0] r_numer__57; +reg [2*`BIT_WIDTH-1:0] r_numer__58; +reg [2*`BIT_WIDTH-1:0] r_numer__59; + +//reg [`BIT_WIDTH-1:0] r_z1[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_z1__0; +reg [`BIT_WIDTH-1:0] r_z1__1; +reg [`BIT_WIDTH-1:0] r_z1__2; +reg [`BIT_WIDTH-1:0] r_z1__3; +reg [`BIT_WIDTH-1:0] r_z1__4; +reg [`BIT_WIDTH-1:0] r_z1__5; +reg [`BIT_WIDTH-1:0] r_z1__6; +reg [`BIT_WIDTH-1:0] r_z1__7; +reg [`BIT_WIDTH-1:0] r_z1__8; +reg [`BIT_WIDTH-1:0] r_z1__9; +reg [`BIT_WIDTH-1:0] r_z1__10; +reg [`BIT_WIDTH-1:0] r_z1__11; +reg [`BIT_WIDTH-1:0] r_z1__12; +reg [`BIT_WIDTH-1:0] r_z1__13; +reg [`BIT_WIDTH-1:0] r_z1__14; +reg [`BIT_WIDTH-1:0] r_z1__15; +reg [`BIT_WIDTH-1:0] r_z1__16; +reg [`BIT_WIDTH-1:0] r_z1__17; +reg [`BIT_WIDTH-1:0] r_z1__18; +reg [`BIT_WIDTH-1:0] r_z1__19; +reg [`BIT_WIDTH-1:0] r_z1__20; +reg [`BIT_WIDTH-1:0] r_z1__21; +reg [`BIT_WIDTH-1:0] r_z1__22; +reg [`BIT_WIDTH-1:0] r_z1__23; +reg [`BIT_WIDTH-1:0] r_z1__24; +reg [`BIT_WIDTH-1:0] r_z1__25; +reg [`BIT_WIDTH-1:0] r_z1__26; +reg [`BIT_WIDTH-1:0] r_z1__27; +reg [`BIT_WIDTH-1:0] r_z1__28; +reg [`BIT_WIDTH-1:0] r_z1__29; +reg [`BIT_WIDTH-1:0] r_z1__30; +reg [`BIT_WIDTH-1:0] r_z1__31; +reg [`BIT_WIDTH-1:0] r_z1__32; +reg [`BIT_WIDTH-1:0] r_z1__33; +reg [`BIT_WIDTH-1:0] r_z1__34; +reg [`BIT_WIDTH-1:0] r_z1__35; +reg [`BIT_WIDTH-1:0] r_z1__36; +reg [`BIT_WIDTH-1:0] r_z1__37; +reg [`BIT_WIDTH-1:0] r_z1__38; +reg [`BIT_WIDTH-1:0] r_z1__39; +reg [`BIT_WIDTH-1:0] r_z1__40; +reg [`BIT_WIDTH-1:0] r_z1__41; +reg [`BIT_WIDTH-1:0] r_z1__42; +reg [`BIT_WIDTH-1:0] r_z1__43; +reg [`BIT_WIDTH-1:0] r_z1__44; +reg [`BIT_WIDTH-1:0] r_z1__45; +reg [`BIT_WIDTH-1:0] r_z1__46; +reg [`BIT_WIDTH-1:0] r_z1__47; +reg [`BIT_WIDTH-1:0] r_z1__48; +reg [`BIT_WIDTH-1:0] r_z1__49; +reg [`BIT_WIDTH-1:0] r_z1__50; +reg [`BIT_WIDTH-1:0] r_z1__51; +reg [`BIT_WIDTH-1:0] r_z1__52; +reg [`BIT_WIDTH-1:0] r_z1__53; +reg [`BIT_WIDTH-1:0] r_z1__54; +reg [`BIT_WIDTH-1:0] r_z1__55; +reg [`BIT_WIDTH-1:0] r_z1__56; +reg [`BIT_WIDTH-1:0] r_z1__57; +reg [`BIT_WIDTH-1:0] r_z1__58; +reg [`BIT_WIDTH-1:0] r_z1__59; + +//reg [`BIT_WIDTH-1:0] r_z0[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_z0__0; +reg [`BIT_WIDTH-1:0] r_z0__1; +reg [`BIT_WIDTH-1:0] r_z0__2; +reg [`BIT_WIDTH-1:0] r_z0__3; +reg [`BIT_WIDTH-1:0] r_z0__4; +reg [`BIT_WIDTH-1:0] r_z0__5; +reg [`BIT_WIDTH-1:0] r_z0__6; +reg [`BIT_WIDTH-1:0] r_z0__7; +reg [`BIT_WIDTH-1:0] r_z0__8; +reg [`BIT_WIDTH-1:0] r_z0__9; +reg [`BIT_WIDTH-1:0] r_z0__10; +reg [`BIT_WIDTH-1:0] r_z0__11; +reg [`BIT_WIDTH-1:0] r_z0__12; +reg [`BIT_WIDTH-1:0] r_z0__13; +reg [`BIT_WIDTH-1:0] r_z0__14; +reg [`BIT_WIDTH-1:0] r_z0__15; +reg [`BIT_WIDTH-1:0] r_z0__16; +reg [`BIT_WIDTH-1:0] r_z0__17; +reg [`BIT_WIDTH-1:0] r_z0__18; +reg [`BIT_WIDTH-1:0] r_z0__19; +reg [`BIT_WIDTH-1:0] r_z0__20; +reg [`BIT_WIDTH-1:0] r_z0__21; +reg [`BIT_WIDTH-1:0] r_z0__22; +reg [`BIT_WIDTH-1:0] r_z0__23; +reg [`BIT_WIDTH-1:0] r_z0__24; +reg [`BIT_WIDTH-1:0] r_z0__25; +reg [`BIT_WIDTH-1:0] r_z0__26; +reg [`BIT_WIDTH-1:0] r_z0__27; +reg [`BIT_WIDTH-1:0] r_z0__28; +reg [`BIT_WIDTH-1:0] r_z0__29; +reg [`BIT_WIDTH-1:0] r_z0__30; +reg [`BIT_WIDTH-1:0] r_z0__31; +reg [`BIT_WIDTH-1:0] r_z0__32; +reg [`BIT_WIDTH-1:0] r_z0__33; +reg [`BIT_WIDTH-1:0] r_z0__34; +reg [`BIT_WIDTH-1:0] r_z0__35; +reg [`BIT_WIDTH-1:0] r_z0__36; +reg [`BIT_WIDTH-1:0] r_z0__37; +reg [`BIT_WIDTH-1:0] r_z0__38; +reg [`BIT_WIDTH-1:0] r_z0__39; +reg [`BIT_WIDTH-1:0] r_z0__40; +reg [`BIT_WIDTH-1:0] r_z0__41; +reg [`BIT_WIDTH-1:0] r_z0__42; +reg [`BIT_WIDTH-1:0] r_z0__43; +reg [`BIT_WIDTH-1:0] r_z0__44; +reg [`BIT_WIDTH-1:0] r_z0__45; +reg [`BIT_WIDTH-1:0] r_z0__46; +reg [`BIT_WIDTH-1:0] r_z0__47; +reg [`BIT_WIDTH-1:0] r_z0__48; +reg [`BIT_WIDTH-1:0] r_z0__49; +reg [`BIT_WIDTH-1:0] r_z0__50; +reg [`BIT_WIDTH-1:0] r_z0__51; +reg [`BIT_WIDTH-1:0] r_z0__52; +reg [`BIT_WIDTH-1:0] r_z0__53; +reg [`BIT_WIDTH-1:0] r_z0__54; +reg [`BIT_WIDTH-1:0] r_z0__55; +reg [`BIT_WIDTH-1:0] r_z0__56; +reg [`BIT_WIDTH-1:0] r_z0__57; +reg [`BIT_WIDTH-1:0] r_z0__58; +reg [`BIT_WIDTH-1:0] r_z0__59; +//reg [`BIT_WIDTH-1:0] r_mut[TOTAL_LATENCY - 1:0]; + +reg [`BIT_WIDTH-1:0] r_mut__0; +reg [`BIT_WIDTH-1:0] r_mut__1; +reg [`BIT_WIDTH-1:0] r_mut__2; +reg [`BIT_WIDTH-1:0] r_mut__3; +reg [`BIT_WIDTH-1:0] r_mut__4; +reg [`BIT_WIDTH-1:0] r_mut__5; +reg [`BIT_WIDTH-1:0] r_mut__6; +reg [`BIT_WIDTH-1:0] r_mut__7; +reg [`BIT_WIDTH-1:0] r_mut__8; +reg [`BIT_WIDTH-1:0] r_mut__9; +reg [`BIT_WIDTH-1:0] r_mut__10; +reg [`BIT_WIDTH-1:0] r_mut__11; +reg [`BIT_WIDTH-1:0] r_mut__12; +reg [`BIT_WIDTH-1:0] r_mut__13; +reg [`BIT_WIDTH-1:0] r_mut__14; +reg [`BIT_WIDTH-1:0] r_mut__15; +reg [`BIT_WIDTH-1:0] r_mut__16; +reg [`BIT_WIDTH-1:0] r_mut__17; +reg [`BIT_WIDTH-1:0] r_mut__18; +reg [`BIT_WIDTH-1:0] r_mut__19; +reg [`BIT_WIDTH-1:0] r_mut__20; +reg [`BIT_WIDTH-1:0] r_mut__21; +reg [`BIT_WIDTH-1:0] r_mut__22; +reg [`BIT_WIDTH-1:0] r_mut__23; +reg [`BIT_WIDTH-1:0] r_mut__24; +reg [`BIT_WIDTH-1:0] r_mut__25; +reg [`BIT_WIDTH-1:0] r_mut__26; +reg [`BIT_WIDTH-1:0] r_mut__27; +reg [`BIT_WIDTH-1:0] r_mut__28; +reg [`BIT_WIDTH-1:0] r_mut__29; +reg [`BIT_WIDTH-1:0] r_mut__30; +reg [`BIT_WIDTH-1:0] r_mut__31; +reg [`BIT_WIDTH-1:0] r_mut__32; +reg [`BIT_WIDTH-1:0] r_mut__33; +reg [`BIT_WIDTH-1:0] r_mut__34; +reg [`BIT_WIDTH-1:0] r_mut__35; +reg [`BIT_WIDTH-1:0] r_mut__36; +reg [`BIT_WIDTH-1:0] r_mut__37; +reg [`BIT_WIDTH-1:0] r_mut__38; +reg [`BIT_WIDTH-1:0] r_mut__39; +reg [`BIT_WIDTH-1:0] r_mut__40; +reg [`BIT_WIDTH-1:0] r_mut__41; +reg [`BIT_WIDTH-1:0] r_mut__42; +reg [`BIT_WIDTH-1:0] r_mut__43; +reg [`BIT_WIDTH-1:0] r_mut__44; +reg [`BIT_WIDTH-1:0] r_mut__45; +reg [`BIT_WIDTH-1:0] r_mut__46; +reg [`BIT_WIDTH-1:0] r_mut__47; +reg [`BIT_WIDTH-1:0] r_mut__48; +reg [`BIT_WIDTH-1:0] r_mut__49; +reg [`BIT_WIDTH-1:0] r_mut__50; +reg [`BIT_WIDTH-1:0] r_mut__51; +reg [`BIT_WIDTH-1:0] r_mut__52; +reg [`BIT_WIDTH-1:0] r_mut__53; +reg [`BIT_WIDTH-1:0] r_mut__54; +reg [`BIT_WIDTH-1:0] r_mut__55; +reg [`BIT_WIDTH-1:0] r_mut__56; +reg [`BIT_WIDTH-1:0] r_mut__57; +reg [`BIT_WIDTH-1:0] r_mut__58; +reg [`BIT_WIDTH-1:0] r_mut__59; + +wire [2*`BIT_WIDTH-1:0] sleftz_big; +wire [2*`BIT_WIDTH-1:0] sleftr_big; +wire [2*`BIT_WIDTH-1:0] sr_big; +wire [`BIT_WIDTH-1:0] remainder_div1; +wire [2*`BIT_WIDTH-1:0] quotient_div1; + +//ASSIGNMENTS FROM PIPE TO OUTPUT +assign x_boundaryChecker = r_x__59; +assign y_boundaryChecker = r_y__59; +assign z_boundaryChecker = r_z__59; +assign ux_boundaryChecker = r_ux__59; +assign uy_boundaryChecker = r_uy__59; +assign uz_boundaryChecker = r_uz__59; +assign sz_boundaryChecker = r_sz__59; +assign sr_boundaryChecker = r_sr__59; +assign sleftz_boundaryChecker = r_sleftz__59; +assign sleftr_boundaryChecker = r_sleftr__59; +assign weight_boundaryChecker = r_weight__59; +assign layer_boundaryChecker = r_layer__59; +assign dead_boundaryChecker = r_dead__59; +assign hit_boundaryChecker = r_hit__59; + +// divider +signed_div_30 divide_u1 ( + .clock(clock), + .denom(c_uz__0), + .numer(c_numer__0), + .quotient(quotient_div1), + .remain(remainder_div1)); + +// multipliers +mult_signed_32_bc mult_u1( + .clock(clock), + .dataa(c_diff__30), + .datab(c_mut__30), + .result(sleftz_big)); + +mult_signed_32_bc mult_u2( + .clock(clock), + .dataa(maxDepth_over_maxRadius), + .datab(c_sleftz__31), + .result(sleftr_big)); + +mult_signed_32_bc mult_u3( + .clock(clock), + .dataa(maxDepth_over_maxRadius), + .datab(c_dl_b__30), + .result(sr_big)); + +// multiplexor to find z1 and z0 +always @(c_layer__0 or z1_0 or z0_0 or mut_0 or + z1_1 or z0_1 or mut_1 or + z1_2 or z0_2 or mut_2 or + z1_3 or z0_3 or mut_3 or + z1_4 or z0_4 or mut_4 or + z1_5 or z0_5 or mut_5) +begin + case(c_layer__0) + 3'b000: + begin + c_z1__0 = z1_0; + c_z0__0 = z0_0; + c_mut__0 = mut_0; + end + 3'b001: + begin + c_z1__0 = z1_1; + c_z0__0 = z0_1; + c_mut__0 = mut_1; + end + 3'b010: + begin + c_z1__0 = z1_2; + c_z0__0 = z0_2; + c_mut__0 = mut_2; + end + 3'b011: + begin + c_z1__0 = z1_3; + c_z0__0 = z0_3; + c_mut__0 = mut_3; + end + 3'b100: + begin + c_z1__0 = z1_4; + c_z0__0 = z0_4; + c_mut__0 = mut_4; + end + 3'b101: + begin + c_z1__0 = z1_5; + c_z0__0 = z0_5; + c_mut__0 = mut_5; + end + default: + begin + c_z1__0 = 0; + c_z0__0 = 0; + c_mut__0 = 0; + end + endcase +end + +// May have to change block staments on this one for odin +// set numerator +always @(c_uz__0 or c_z1__0 or c_z__0 or c_z0__0) +begin + //c_numer__0 = 63'b0; + if(c_uz__0[31] == 1'b0) + begin + c_numer__0[63:32] = c_z1__0 - c_z__0; + c_numer__0[31:0] = 32'b0; + end + else if(c_uz__0[31] == 1'b1) + begin + c_numer__0[63:32] = c_z0__0 - c_z__0; + c_numer__0[31:0] = 32'b0; + end + else + begin + c_numer__0 = 63'b0; + end +end + +// initialize uninitialized data in pipeline +always @(x_mover or y_mover or z_mover or + ux_mover or uy_mover or uz_mover or + sz_mover or sr_mover or sleftz_mover or sleftr_mover or + weight_mover or layer_mover or dead_mover) +begin + c_x__0 = x_mover; + c_y__0 = y_mover; + c_z__0 = z_mover; + c_ux__0 = ux_mover; + c_uy__0 = uy_mover; + c_uz__0 = uz_mover; + c_sz__0 = sz_mover; + c_sr__0 = sr_mover; + c_sleftz__0 = sleftz_mover; + c_sleftr__0 = sleftr_mover; + c_weight__0 = weight_mover; + c_layer__0 = layer_mover; + c_dead__0 = dead_mover; + c_hit__0 = 1'b0; + c_diff__0 = 32'b0; + c_dl_b__0 = 32'b0; +end + +// Determine new (x,y,z) coordinates +always @(r_x__0 or r_y__0 or r_z__0 or r_ux__0 or r_uy__0 or r_uz__0 or r_sz__0 or r_sr__0 or r_sleftz__0 or r_sleftr__0 or + r_weight__0 or r_layer__0 or r_dead__0 or r_hit__0 or r_diff__0 or r_dl_b__0 or r_numer__0 or r_z1__0 or r_z0__0 or r_mut__0 or + + r_x__1 or r_y__1 or r_z__1 or r_ux__1 or r_uy__1 or r_uz__1 or r_sz__1 or r_sr__1 or r_sleftz__1 or r_sleftr__1 or + r_weight__1 or r_layer__1 or r_dead__1 or r_hit__1 or r_diff__1 or r_dl_b__1 or r_numer__1 or r_z1__1 or r_z0__1 or r_mut__1 or + + r_x__2 or r_y__2 or r_z__2 or r_ux__2 or r_uy__2 or r_uz__2 or r_sz__2 or r_sr__2 or r_sleftz__2 or r_sleftr__2 or + r_weight__2 or r_layer__2 or r_dead__2 or r_hit__2 or r_diff__2 or r_dl_b__2 or r_numer__2 or r_z1__2 or r_z0__2 or r_mut__2 or + + r_x__3 or r_y__3 or r_z__3 or r_ux__3 or r_uy__3 or r_uz__3 or r_sz__3 or r_sr__3 or r_sleftz__3 or r_sleftr__3 or + r_weight__3 or r_layer__3 or r_dead__3 or r_hit__3 or r_diff__3 or r_dl_b__3 or r_numer__3 or r_z1__3 or r_z0__3 or r_mut__3 or + + r_x__4 or r_y__4 or r_z__4 or r_ux__4 or r_uy__4 or r_uz__4 or r_sz__4 or r_sr__4 or r_sleftz__4 or r_sleftr__4 or + r_weight__4 or r_layer__4 or r_dead__4 or r_hit__4 or r_diff__4 or r_dl_b__4 or r_numer__4 or r_z1__4 or r_z0__4 or r_mut__4 or + + r_x__5 or r_y__5 or r_z__5 or r_ux__5 or r_uy__5 or r_uz__5 or r_sz__5 or r_sr__5 or r_sleftz__5 or r_sleftr__5 or + r_weight__5 or r_layer__5 or r_dead__5 or r_hit__5 or r_diff__5 or r_dl_b__5 or r_numer__5 or r_z1__5 or r_z0__5 or r_mut__5 or + + r_x__6 or r_y__6 or r_z__6 or r_ux__6 or r_uy__6 or r_uz__6 or r_sz__6 or r_sr__6 or r_sleftz__6 or r_sleftr__6 or + r_weight__6 or r_layer__6 or r_dead__6 or r_hit__6 or r_diff__6 or r_dl_b__6 or r_numer__6 or r_z1__6 or r_z0__6 or r_mut__6 or + + r_x__7 or r_y__7 or r_z__7 or r_ux__7 or r_uy__7 or r_uz__7 or r_sz__7 or r_sr__7 or r_sleftz__7 or r_sleftr__7 or + r_weight__7 or r_layer__7 or r_dead__7 or r_hit__7 or r_diff__7 or r_dl_b__7 or r_numer__7 or r_z1__7 or r_z0__7 or r_mut__7 or + + r_x__8 or r_y__8 or r_z__8 or r_ux__8 or r_uy__8 or r_uz__8 or r_sz__8 or r_sr__8 or r_sleftz__8 or r_sleftr__8 or + r_weight__8 or r_layer__8 or r_dead__8 or r_hit__8 or r_diff__8 or r_dl_b__8 or r_numer__8 or r_z1__8 or r_z0__8 or r_mut__8 or + + r_x__9 or r_y__9 or r_z__9 or r_ux__9 or r_uy__9 or r_uz__9 or r_sz__9 or r_sr__9 or r_sleftz__9 or r_sleftr__9 or + r_weight__9 or r_layer__9 or r_dead__9 or r_hit__9 or r_diff__9 or r_dl_b__9 or r_numer__9 or r_z1__9 or r_z0__9 or r_mut__9 or + + r_x__10 or r_y__10 or r_z__10 or r_ux__10 or r_uy__10 or r_uz__10 or r_sz__10 or r_sr__10 or r_sleftz__10 or r_sleftr__10 or + r_weight__10 or r_layer__10 or r_dead__10 or r_hit__10 or r_diff__10 or r_dl_b__10 or r_numer__10 or r_z1__10 or r_z0__10 or r_mut__10 or + + r_x__11 or r_y__11 or r_z__11 or r_ux__11 or r_uy__11 or r_uz__11 or r_sz__11 or r_sr__11 or r_sleftz__11 or r_sleftr__11 or + r_weight__11 or r_layer__11 or r_dead__11 or r_hit__11 or r_diff__11 or r_dl_b__11 or r_numer__11 or r_z1__11 or r_z0__11 or r_mut__11 or + + r_x__12 or r_y__12 or r_z__12 or r_ux__12 or r_uy__12 or r_uz__12 or r_sz__12 or r_sr__12 or r_sleftz__12 or r_sleftr__12 or + r_weight__12 or r_layer__12 or r_dead__12 or r_hit__12 or r_diff__12 or r_dl_b__12 or r_numer__12 or r_z1__12 or r_z0__12 or r_mut__12 or + + r_x__13 or r_y__13 or r_z__13 or r_ux__13 or r_uy__13 or r_uz__13 or r_sz__13 or r_sr__13 or r_sleftz__13 or r_sleftr__13 or + r_weight__13 or r_layer__13 or r_dead__13 or r_hit__13 or r_diff__13 or r_dl_b__13 or r_numer__13 or r_z1__13 or r_z0__13 or r_mut__13 or + + r_x__14 or r_y__14 or r_z__14 or r_ux__14 or r_uy__14 or r_uz__14 or r_sz__14 or r_sr__14 or r_sleftz__14 or r_sleftr__14 or + r_weight__14 or r_layer__14 or r_dead__14 or r_hit__14 or r_diff__14 or r_dl_b__14 or r_numer__14 or r_z1__14 or r_z0__14 or r_mut__14 or + + r_x__15 or r_y__15 or r_z__15 or r_ux__15 or r_uy__15 or r_uz__15 or r_sz__15 or r_sr__15 or r_sleftz__15 or r_sleftr__15 or + r_weight__15 or r_layer__15 or r_dead__15 or r_hit__15 or r_diff__15 or r_dl_b__15 or r_numer__15 or r_z1__15 or r_z0__15 or r_mut__15 or + + r_x__16 or r_y__16 or r_z__16 or r_ux__16 or r_uy__16 or r_uz__16 or r_sz__16 or r_sr__16 or r_sleftz__16 or r_sleftr__16 or + r_weight__16 or r_layer__16 or r_dead__16 or r_hit__16 or r_diff__16 or r_dl_b__16 or r_numer__16 or r_z1__16 or r_z0__16 or r_mut__16 or + + r_x__17 or r_y__17 or r_z__17 or r_ux__17 or r_uy__17 or r_uz__17 or r_sz__17 or r_sr__17 or r_sleftz__17 or r_sleftr__17 or + r_weight__17 or r_layer__17 or r_dead__17 or r_hit__17 or r_diff__17 or r_dl_b__17 or r_numer__17 or r_z1__17 or r_z0__17 or r_mut__17 or + + r_x__18 or r_y__18 or r_z__18 or r_ux__18 or r_uy__18 or r_uz__18 or r_sz__18 or r_sr__18 or r_sleftz__18 or r_sleftr__18 or + r_weight__18 or r_layer__18 or r_dead__18 or r_hit__18 or r_diff__18 or r_dl_b__18 or r_numer__18 or r_z1__18 or r_z0__18 or r_mut__18 or + + r_x__19 or r_y__19 or r_z__19 or r_ux__19 or r_uy__19 or r_uz__19 or r_sz__19 or r_sr__19 or r_sleftz__19 or r_sleftr__19 or + r_weight__19 or r_layer__19 or r_dead__19 or r_hit__19 or r_diff__19 or r_dl_b__19 or r_numer__19 or r_z1__19 or r_z0__19 or r_mut__19 or + + r_x__20 or r_y__20 or r_z__20 or r_ux__20 or r_uy__20 or r_uz__20 or r_sz__20 or r_sr__20 or r_sleftz__20 or r_sleftr__20 or + r_weight__20 or r_layer__20 or r_dead__20 or r_hit__20 or r_diff__20 or r_dl_b__20 or r_numer__20 or r_z1__20 or r_z0__20 or r_mut__20 or + + r_x__21 or r_y__21 or r_z__21 or r_ux__21 or r_uy__21 or r_uz__21 or r_sz__21 or r_sr__21 or r_sleftz__21 or r_sleftr__21 or + r_weight__21 or r_layer__21 or r_dead__21 or r_hit__21 or r_diff__21 or r_dl_b__21 or r_numer__21 or r_z1__21 or r_z0__21 or r_mut__21 or + + r_x__22 or r_y__22 or r_z__22 or r_ux__22 or r_uy__22 or r_uz__22 or r_sz__22 or r_sr__22 or r_sleftz__22 or r_sleftr__22 or + r_weight__22 or r_layer__22 or r_dead__22 or r_hit__22 or r_diff__22 or r_dl_b__22 or r_numer__22 or r_z1__22 or r_z0__22 or r_mut__22 or + + r_x__23 or r_y__23 or r_z__23 or r_ux__23 or r_uy__23 or r_uz__23 or r_sz__23 or r_sr__23 or r_sleftz__23 or r_sleftr__23 or + r_weight__23 or r_layer__23 or r_dead__23 or r_hit__23 or r_diff__23 or r_dl_b__23 or r_numer__23 or r_z1__23 or r_z0__23 or r_mut__23 or + + r_x__24 or r_y__24 or r_z__24 or r_ux__24 or r_uy__24 or r_uz__24 or r_sz__24 or r_sr__24 or r_sleftz__24 or r_sleftr__24 or + r_weight__24 or r_layer__24 or r_dead__24 or r_hit__24 or r_diff__24 or r_dl_b__24 or r_numer__24 or r_z1__24 or r_z0__24 or r_mut__24 or + + r_x__25 or r_y__25 or r_z__25 or r_ux__25 or r_uy__25 or r_uz__25 or r_sz__25 or r_sr__25 or r_sleftz__25 or r_sleftr__25 or + r_weight__25 or r_layer__25 or r_dead__25 or r_hit__25 or r_diff__25 or r_dl_b__25 or r_numer__25 or r_z1__25 or r_z0__25 or r_mut__25 or + + r_x__26 or r_y__26 or r_z__26 or r_ux__26 or r_uy__26 or r_uz__26 or r_sz__26 or r_sr__26 or r_sleftz__26 or r_sleftr__26 or + r_weight__26 or r_layer__26 or r_dead__26 or r_hit__26 or r_diff__26 or r_dl_b__26 or r_numer__26 or r_z1__26 or r_z0__26 or r_mut__26 or + + r_x__27 or r_y__27 or r_z__27 or r_ux__27 or r_uy__27 or r_uz__27 or r_sz__27 or r_sr__27 or r_sleftz__27 or r_sleftr__27 or + r_weight__27 or r_layer__27 or r_dead__27 or r_hit__27 or r_diff__27 or r_dl_b__27 or r_numer__27 or r_z1__27 or r_z0__27 or r_mut__27 or + + r_x__28 or r_y__28 or r_z__28 or r_ux__28 or r_uy__28 or r_uz__28 or r_sz__28 or r_sr__28 or r_sleftz__28 or r_sleftr__28 or + r_weight__28 or r_layer__28 or r_dead__28 or r_hit__28 or r_diff__28 or r_dl_b__28 or r_numer__28 or r_z1__28 or r_z0__28 or r_mut__28 or + + r_x__29 or r_y__29 or r_z__29 or r_ux__29 or r_uy__29 or r_uz__29 or r_sz__29 or r_sr__29 or r_sleftz__29 or r_sleftr__29 or + r_weight__29 or r_layer__29 or r_dead__29 or r_hit__29 or r_diff__29 or r_dl_b__29 or r_numer__29 or r_z1__29 or r_z0__29 or r_mut__29 or + + r_x__30 or r_y__30 or r_z__30 or r_ux__30 or r_uy__30 or r_uz__30 or r_sz__30 or r_sr__30 or r_sleftz__30 or r_sleftr__30 or + r_weight__30 or r_layer__30 or r_dead__30 or r_hit__30 or r_diff__30 or r_dl_b__30 or r_numer__30 or r_z1__30 or r_z0__30 or r_mut__30 or + + r_x__31 or r_y__31 or r_z__31 or r_ux__31 or r_uy__31 or r_uz__31 or r_sz__31 or r_sr__31 or r_sleftz__31 or r_sleftr__31 or + r_weight__31 or r_layer__31 or r_dead__31 or r_hit__31 or r_diff__31 or r_dl_b__31 or r_numer__31 or r_z1__31 or r_z0__31 or r_mut__31 or + + r_x__32 or r_y__32 or r_z__32 or r_ux__32 or r_uy__32 or r_uz__32 or r_sz__32 or r_sr__32 or r_sleftz__32 or r_sleftr__32 or + r_weight__32 or r_layer__32 or r_dead__32 or r_hit__32 or r_diff__32 or r_dl_b__32 or r_numer__32 or r_z1__32 or r_z0__32 or r_mut__32 or + + r_x__33 or r_y__33 or r_z__33 or r_ux__33 or r_uy__33 or r_uz__33 or r_sz__33 or r_sr__33 or r_sleftz__33 or r_sleftr__33 or + r_weight__33 or r_layer__33 or r_dead__33 or r_hit__33 or r_diff__33 or r_dl_b__33 or r_numer__33 or r_z1__33 or r_z0__33 or r_mut__33 or + + r_x__34 or r_y__34 or r_z__34 or r_ux__34 or r_uy__34 or r_uz__34 or r_sz__34 or r_sr__34 or r_sleftz__34 or r_sleftr__34 or + r_weight__34 or r_layer__34 or r_dead__34 or r_hit__34 or r_diff__34 or r_dl_b__34 or r_numer__34 or r_z1__34 or r_z0__34 or r_mut__34 or + + r_x__35 or r_y__35 or r_z__35 or r_ux__35 or r_uy__35 or r_uz__35 or r_sz__35 or r_sr__35 or r_sleftz__35 or r_sleftr__35 or + r_weight__35 or r_layer__35 or r_dead__35 or r_hit__35 or r_diff__35 or r_dl_b__35 or r_numer__35 or r_z1__35 or r_z0__35 or r_mut__35 or + + r_x__36 or r_y__36 or r_z__36 or r_ux__36 or r_uy__36 or r_uz__36 or r_sz__36 or r_sr__36 or r_sleftz__36 or r_sleftr__36 or + r_weight__36 or r_layer__36 or r_dead__36 or r_hit__36 or r_diff__36 or r_dl_b__36 or r_numer__36 or r_z1__36 or r_z0__36 or r_mut__36 or + + r_x__37 or r_y__37 or r_z__37 or r_ux__37 or r_uy__37 or r_uz__37 or r_sz__37 or r_sr__37 or r_sleftz__37 or r_sleftr__37 or + r_weight__37 or r_layer__37 or r_dead__37 or r_hit__37 or r_diff__37 or r_dl_b__37 or r_numer__37 or r_z1__37 or r_z0__37 or r_mut__37 or + + r_x__38 or r_y__38 or r_z__38 or r_ux__38 or r_uy__38 or r_uz__38 or r_sz__38 or r_sr__38 or r_sleftz__38 or r_sleftr__38 or + r_weight__38 or r_layer__38 or r_dead__38 or r_hit__38 or r_diff__38 or r_dl_b__38 or r_numer__38 or r_z1__38 or r_z0__38 or r_mut__38 or + + r_x__39 or r_y__39 or r_z__39 or r_ux__39 or r_uy__39 or r_uz__39 or r_sz__39 or r_sr__39 or r_sleftz__39 or r_sleftr__39 or + r_weight__39 or r_layer__39 or r_dead__39 or r_hit__39 or r_diff__39 or r_dl_b__39 or r_numer__39 or r_z1__39 or r_z0__39 or r_mut__39 or + + r_x__40 or r_y__40 or r_z__40 or r_ux__40 or r_uy__40 or r_uz__40 or r_sz__40 or r_sr__40 or r_sleftz__40 or r_sleftr__40 or + r_weight__40 or r_layer__40 or r_dead__40 or r_hit__40 or r_diff__40 or r_dl_b__40 or r_numer__40 or r_z1__40 or r_z0__40 or r_mut__40 or + + r_x__41 or r_y__41 or r_z__41 or r_ux__41 or r_uy__41 or r_uz__41 or r_sz__41 or r_sr__41 or r_sleftz__41 or r_sleftr__41 or + r_weight__41 or r_layer__41 or r_dead__41 or r_hit__41 or r_diff__41 or r_dl_b__41 or r_numer__41 or r_z1__41 or r_z0__41 or r_mut__41 or + + r_x__42 or r_y__42 or r_z__42 or r_ux__42 or r_uy__42 or r_uz__42 or r_sz__42 or r_sr__42 or r_sleftz__42 or r_sleftr__42 or + r_weight__42 or r_layer__42 or r_dead__42 or r_hit__42 or r_diff__42 or r_dl_b__42 or r_numer__42 or r_z1__42 or r_z0__42 or r_mut__42 or + + r_x__43 or r_y__43 or r_z__43 or r_ux__43 or r_uy__43 or r_uz__43 or r_sz__43 or r_sr__43 or r_sleftz__43 or r_sleftr__43 or + r_weight__43 or r_layer__43 or r_dead__43 or r_hit__43 or r_diff__43 or r_dl_b__43 or r_numer__43 or r_z1__43 or r_z0__43 or r_mut__43 or + + r_x__44 or r_y__44 or r_z__44 or r_ux__44 or r_uy__44 or r_uz__44 or r_sz__44 or r_sr__44 or r_sleftz__44 or r_sleftr__44 or + r_weight__44 or r_layer__44 or r_dead__44 or r_hit__44 or r_diff__44 or r_dl_b__44 or r_numer__44 or r_z1__44 or r_z0__44 or r_mut__44 or + + r_x__45 or r_y__45 or r_z__45 or r_ux__45 or r_uy__45 or r_uz__45 or r_sz__45 or r_sr__45 or r_sleftz__45 or r_sleftr__45 or + r_weight__45 or r_layer__45 or r_dead__45 or r_hit__45 or r_diff__45 or r_dl_b__45 or r_numer__45 or r_z1__45 or r_z0__45 or r_mut__45 or + + r_x__46 or r_y__46 or r_z__46 or r_ux__46 or r_uy__46 or r_uz__46 or r_sz__46 or r_sr__46 or r_sleftz__46 or r_sleftr__46 or + r_weight__46 or r_layer__46 or r_dead__46 or r_hit__46 or r_diff__46 or r_dl_b__46 or r_numer__46 or r_z1__46 or r_z0__46 or r_mut__46 or + + r_x__47 or r_y__47 or r_z__47 or r_ux__47 or r_uy__47 or r_uz__47 or r_sz__47 or r_sr__47 or r_sleftz__47 or r_sleftr__47 or + r_weight__47 or r_layer__47 or r_dead__47 or r_hit__47 or r_diff__47 or r_dl_b__47 or r_numer__47 or r_z1__47 or r_z0__47 or r_mut__47 or + + r_x__48 or r_y__48 or r_z__48 or r_ux__48 or r_uy__48 or r_uz__48 or r_sz__48 or r_sr__48 or r_sleftz__48 or r_sleftr__48 or + r_weight__48 or r_layer__48 or r_dead__48 or r_hit__48 or r_diff__48 or r_dl_b__48 or r_numer__48 or r_z1__48 or r_z0__48 or r_mut__48 or + + r_x__49 or r_y__49 or r_z__49 or r_ux__49 or r_uy__49 or r_uz__49 or r_sz__49 or r_sr__49 or r_sleftz__49 or r_sleftr__49 or + r_weight__49 or r_layer__49 or r_dead__49 or r_hit__49 or r_diff__49 or r_dl_b__49 or r_numer__49 or r_z1__49 or r_z0__49 or r_mut__49 or + + r_x__50 or r_y__50 or r_z__50 or r_ux__50 or r_uy__50 or r_uz__50 or r_sz__50 or r_sr__50 or r_sleftz__50 or r_sleftr__50 or + r_weight__50 or r_layer__50 or r_dead__50 or r_hit__50 or r_diff__50 or r_dl_b__50 or r_numer__50 or r_z1__50 or r_z0__50 or r_mut__50 or + + r_x__51 or r_y__51 or r_z__51 or r_ux__51 or r_uy__51 or r_uz__51 or r_sz__51 or r_sr__51 or r_sleftz__51 or r_sleftr__51 or + r_weight__51 or r_layer__51 or r_dead__51 or r_hit__51 or r_diff__51 or r_dl_b__51 or r_numer__51 or r_z1__51 or r_z0__51 or r_mut__51 or + + r_x__52 or r_y__52 or r_z__52 or r_ux__52 or r_uy__52 or r_uz__52 or r_sz__52 or r_sr__52 or r_sleftz__52 or r_sleftr__52 or + r_weight__52 or r_layer__52 or r_dead__52 or r_hit__52 or r_diff__52 or r_dl_b__52 or r_numer__52 or r_z1__52 or r_z0__52 or r_mut__52 or + + r_x__53 or r_y__53 or r_z__53 or r_ux__53 or r_uy__53 or r_uz__53 or r_sz__53 or r_sr__53 or r_sleftz__53 or r_sleftr__53 or + r_weight__53 or r_layer__53 or r_dead__53 or r_hit__53 or r_diff__53 or r_dl_b__53 or r_numer__53 or r_z1__53 or r_z0__53 or r_mut__53 or + + r_x__54 or r_y__54 or r_z__54 or r_ux__54 or r_uy__54 or r_uz__54 or r_sz__54 or r_sr__54 or r_sleftz__54 or r_sleftr__54 or + r_weight__54 or r_layer__54 or r_dead__54 or r_hit__54 or r_diff__54 or r_dl_b__54 or r_numer__54 or r_z1__54 or r_z0__54 or r_mut__54 or + + r_x__55 or r_y__55 or r_z__55 or r_ux__55 or r_uy__55 or r_uz__55 or r_sz__55 or r_sr__55 or r_sleftz__55 or r_sleftr__55 or + r_weight__55 or r_layer__55 or r_dead__55 or r_hit__55 or r_diff__55 or r_dl_b__55 or r_numer__55 or r_z1__55 or r_z0__55 or r_mut__55 or + + r_x__56 or r_y__56 or r_z__56 or r_ux__56 or r_uy__56 or r_uz__56 or r_sz__56 or r_sr__56 or r_sleftz__56 or r_sleftr__56 or + r_weight__56 or r_layer__56 or r_dead__56 or r_hit__56 or r_diff__56 or r_dl_b__56 or r_numer__56 or r_z1__56 or r_z0__56 or r_mut__56 or + + r_x__57 or r_y__57 or r_z__57 or r_ux__57 or r_uy__57 or r_uz__57 or r_sz__57 or r_sr__57 or r_sleftz__57 or r_sleftr__57 or + r_weight__57 or r_layer__57 or r_dead__57 or r_hit__57 or r_diff__57 or r_dl_b__57 or r_numer__57 or r_z1__57 or r_z0__57 or r_mut__57 or + + r_x__58 or r_y__58 or r_z__58 or r_ux__58 or r_uy__58 or r_uz__58 or r_sz__58 or r_sr__58 or r_sleftz__58 or r_sleftr__58 or + r_weight__58 or r_layer__58 or r_dead__58 or r_hit__58 or r_diff__58 or r_dl_b__58 or r_numer__58 or r_z1__58 or r_z0__58 or r_mut__58 or + + r_x__59 or r_y__59 or r_z__59 or r_ux__59 or r_uy__59 or r_uz__59 or r_sz__59 or r_sr__59 or r_sleftz__59 or r_sleftr__59 or + r_weight__59 or r_layer__59 or r_dead__59 or r_hit__59 or r_diff__59 or r_dl_b__59 or r_numer__59 or r_z1__59 or r_z0__59 or r_mut__59 or + + sr_big or sleftz_big or sleftr_big or quotient_div1) + + // default + // setup standard pipeline +// for(i = 1; i < `TOTAL_LATENCY; i = i + 1) +// begin +// c_x[i] = r_x[i-1]; +// c_y[i] = r_y[i-1]; +// c_z[i] = r_z[i-1]; +// c_ux[i] = r_ux[i-1]; +// c_uy[i] = r_uy[i-1]; +// c_uz[i] = r_uz[i-1]; +// c_sz[i] = r_sz[i-1]; +// c_sr[i] = r_sr[i-1]; +// c_sleftz[i] = r_sleftz[i-1]; +// c_sleftr[i] = r_sleftr[i-1]; +// c_weight[i] = r_weight[i-1]; +// c_layer[i] = r_layer[i-1]; +// c_dead[i] = r_dead[i-1]; +// c_hit[i] = r_hit[i-1]; +// c_diff[i] = r_diff[i-1]; +// c_dl_b[i] = r_dl_b[i-1]; +// c_numer[i] = r_numer[i-1]; +// c_z1[i] = r_z1[i-1]; +// c_z0[i] = r_z0[i-1]; +// c_mut[i] = r_mut[i-1]; +// end + +begin + //Instatiate all 60 instances of the above for-loop + //for 1 + c_x__1 = r_x__0; + c_y__1 = r_y__0; + c_z__1 = r_z__0; + c_ux__1 = r_ux__0; + c_uy__1 = r_uy__0; + c_uz__1 = r_uz__0; + c_sz__1 = r_sz__0; + c_sr__1 = r_sr__0; + c_sleftz__1 = r_sleftz__0; + c_sleftr__1 = r_sleftr__0; + c_weight__1 = r_weight__0; + c_layer__1 = r_layer__0; + c_dead__1 = r_dead__0; + c_hit__1 = r_hit__0; + c_diff__1 = r_diff__0; + c_dl_b__1 = r_dl_b__0; + c_numer__1 = r_numer__0; + c_z1__1 = r_z1__0; + c_z0__1 = r_z0__0; + c_mut__1 = r_mut__0; + + //for 2 + c_x__2 = r_x__1; + c_y__2 = r_y__1; + c_z__2 = r_z__1; + c_ux__2 = r_ux__1; + c_uy__2 = r_uy__1; + c_uz__2 = r_uz__1; + c_sz__2 = r_sz__1; + c_sr__2 = r_sr__1; + c_sleftz__2 = r_sleftz__1; + c_sleftr__2 = r_sleftr__1; + c_weight__2 = r_weight__1; + c_layer__2 = r_layer__1; + c_dead__2 = r_dead__1; + c_hit__2 = r_hit__1; + c_diff__2 = r_diff__1; + c_dl_b__2 = r_dl_b__1; + c_numer__2 = r_numer__1; + c_z1__2 = r_z1__1; + c_z0__2 = r_z0__1; + c_mut__2 = r_mut__1; + + //for 3 + c_x__3 = r_x__2; + c_y__3 = r_y__2; + c_z__3 = r_z__2; + c_ux__3 = r_ux__2; + c_uy__3 = r_uy__2; + c_uz__3 = r_uz__2; + c_sz__3 = r_sz__2; + c_sr__3 = r_sr__2; + c_sleftz__3 = r_sleftz__2; + c_sleftr__3 = r_sleftr__2; + c_weight__3 = r_weight__2; + c_layer__3 = r_layer__2; + c_dead__3 = r_dead__2; + c_hit__3 = r_hit__2; + c_diff__3 = r_diff__2; + c_dl_b__3 = r_dl_b__2; + c_numer__3 = r_numer__2; + c_z1__3 = r_z1__2; + c_z0__3 = r_z0__2; + c_mut__3 = r_mut__2; + + //for 4 + c_x__4 = r_x__3; + c_y__4 = r_y__3; + c_z__4 = r_z__3; + c_ux__4 = r_ux__3; + c_uy__4 = r_uy__3; + c_uz__4 = r_uz__3; + c_sz__4 = r_sz__3; + c_sr__4 = r_sr__3; + c_sleftz__4 = r_sleftz__3; + c_sleftr__4 = r_sleftr__3; + c_weight__4 = r_weight__3; + c_layer__4 = r_layer__3; + c_dead__4 = r_dead__3; + c_hit__4 = r_hit__3; + c_diff__4 = r_diff__3; + c_dl_b__4 = r_dl_b__3; + c_numer__4 = r_numer__3; + c_z1__4 = r_z1__3; + c_z0__4 = r_z0__3; + c_mut__4 = r_mut__3; + + //for 5 + c_x__5 = r_x__4; + c_y__5 = r_y__4; + c_z__5 = r_z__4; + c_ux__5 = r_ux__4; + c_uy__5 = r_uy__4; + c_uz__5 = r_uz__4; + c_sz__5 = r_sz__4; + c_sr__5 = r_sr__4; + c_sleftz__5 = r_sleftz__4; + c_sleftr__5 = r_sleftr__4; + c_weight__5 = r_weight__4; + c_layer__5 = r_layer__4; + c_dead__5 = r_dead__4; + c_hit__5 = r_hit__4; + c_diff__5 = r_diff__4; + c_dl_b__5 = r_dl_b__4; + c_numer__5 = r_numer__4; + c_z1__5 = r_z1__4; + c_z0__5 = r_z0__4; + c_mut__5 = r_mut__4; + + //for 6 + c_x__6 = r_x__5; + c_y__6 = r_y__5; + c_z__6 = r_z__5; + c_ux__6 = r_ux__5; + c_uy__6 = r_uy__5; + c_uz__6 = r_uz__5; + c_sz__6 = r_sz__5; + c_sr__6 = r_sr__5; + c_sleftz__6 = r_sleftz__5; + c_sleftr__6 = r_sleftr__5; + c_weight__6 = r_weight__5; + c_layer__6 = r_layer__5; + c_dead__6 = r_dead__5; + c_hit__6 = r_hit__5; + c_diff__6 = r_diff__5; + c_dl_b__6 = r_dl_b__5; + c_numer__6 = r_numer__5; + c_z1__6 = r_z1__5; + c_z0__6 = r_z0__5; + c_mut__6 = r_mut__5; + + //for 7 + c_x__7 = r_x__6; + c_y__7 = r_y__6; + c_z__7 = r_z__6; + c_ux__7 = r_ux__6; + c_uy__7 = r_uy__6; + c_uz__7 = r_uz__6; + c_sz__7 = r_sz__6; + c_sr__7 = r_sr__6; + c_sleftz__7 = r_sleftz__6; + c_sleftr__7 = r_sleftr__6; + c_weight__7 = r_weight__6; + c_layer__7 = r_layer__6; + c_dead__7 = r_dead__6; + c_hit__7 = r_hit__6; + c_diff__7 = r_diff__6; + c_dl_b__7 = r_dl_b__6; + c_numer__7 = r_numer__6; + c_z1__7 = r_z1__6; + c_z0__7 = r_z0__6; + c_mut__7 = r_mut__6; + + //for 8 + c_x__8 = r_x__7; + c_y__8 = r_y__7; + c_z__8 = r_z__7; + c_ux__8 = r_ux__7; + c_uy__8 = r_uy__7; + c_uz__8 = r_uz__7; + c_sz__8 = r_sz__7; + c_sr__8 = r_sr__7; + c_sleftz__8 = r_sleftz__7; + c_sleftr__8 = r_sleftr__7; + c_weight__8 = r_weight__7; + c_layer__8 = r_layer__7; + c_dead__8 = r_dead__7; + c_hit__8 = r_hit__7; + c_diff__8 = r_diff__7; + c_dl_b__8 = r_dl_b__7; + c_numer__8 = r_numer__7; + c_z1__8 = r_z1__7; + c_z0__8 = r_z0__7; + c_mut__8 = r_mut__7; + + //for 9 + c_x__9 = r_x__8; + c_y__9 = r_y__8; + c_z__9 = r_z__8; + c_ux__9 = r_ux__8; + c_uy__9 = r_uy__8; + c_uz__9 = r_uz__8; + c_sz__9 = r_sz__8; + c_sr__9 = r_sr__8; + c_sleftz__9 = r_sleftz__8; + c_sleftr__9 = r_sleftr__8; + c_weight__9 = r_weight__8; + c_layer__9 = r_layer__8; + c_dead__9 = r_dead__8; + c_hit__9 = r_hit__8; + c_diff__9 = r_diff__8; + c_dl_b__9 = r_dl_b__8; + c_numer__9 = r_numer__8; + c_z1__9 = r_z1__8; + c_z0__9 = r_z0__8; + c_mut__9 = r_mut__8; + + //for 10 + c_x__10 = r_x__9; + c_y__10 = r_y__9; + c_z__10 = r_z__9; + c_ux__10 = r_ux__9; + c_uy__10 = r_uy__9; + c_uz__10 = r_uz__9; + c_sz__10 = r_sz__9; + c_sr__10 = r_sr__9; + c_sleftz__10 = r_sleftz__9; + c_sleftr__10 = r_sleftr__9; + c_weight__10 = r_weight__9; + c_layer__10 = r_layer__9; + c_dead__10 = r_dead__9; + c_hit__10 = r_hit__9; + c_diff__10 = r_diff__9; + c_dl_b__10 = r_dl_b__9; + c_numer__10 = r_numer__9; + c_z1__10 = r_z1__9; + c_z0__10 = r_z0__9; + c_mut__10 = r_mut__9; + + //for 11 + c_x__11 = r_x__10; + c_y__11 = r_y__10; + c_z__11 = r_z__10; + c_ux__11 = r_ux__10; + c_uy__11 = r_uy__10; + c_uz__11 = r_uz__10; + c_sz__11 = r_sz__10; + c_sr__11 = r_sr__10; + c_sleftz__11 = r_sleftz__10; + c_sleftr__11 = r_sleftr__10; + c_weight__11 = r_weight__10; + c_layer__11 = r_layer__10; + c_dead__11 = r_dead__10; + c_hit__11 = r_hit__10; + c_diff__11 = r_diff__10; + c_dl_b__11 = r_dl_b__10; + c_numer__11 = r_numer__10; + c_z1__11 = r_z1__10; + c_z0__11 = r_z0__10; + c_mut__11 = r_mut__10; + + //for 12 + c_x__12 = r_x__11; + c_y__12 = r_y__11; + c_z__12 = r_z__11; + c_ux__12 = r_ux__11; + c_uy__12 = r_uy__11; + c_uz__12 = r_uz__11; + c_sz__12 = r_sz__11; + c_sr__12 = r_sr__11; + c_sleftz__12 = r_sleftz__11; + c_sleftr__12 = r_sleftr__11; + c_weight__12 = r_weight__11; + c_layer__12 = r_layer__11; + c_dead__12 = r_dead__11; + c_hit__12 = r_hit__11; + c_diff__12 = r_diff__11; + c_dl_b__12 = r_dl_b__11; + c_numer__12 = r_numer__11; + c_z1__12 = r_z1__11; + c_z0__12 = r_z0__11; + c_mut__12 = r_mut__11; + + //for 13 + c_x__13 = r_x__12; + c_y__13 = r_y__12; + c_z__13 = r_z__12; + c_ux__13 = r_ux__12; + c_uy__13 = r_uy__12; + c_uz__13 = r_uz__12; + c_sz__13 = r_sz__12; + c_sr__13 = r_sr__12; + c_sleftz__13 = r_sleftz__12; + c_sleftr__13 = r_sleftr__12; + c_weight__13 = r_weight__12; + c_layer__13 = r_layer__12; + c_dead__13 = r_dead__12; + c_hit__13 = r_hit__12; + c_diff__13 = r_diff__12; + c_dl_b__13 = r_dl_b__12; + c_numer__13 = r_numer__12; + c_z1__13 = r_z1__12; + c_z0__13 = r_z0__12; + c_mut__13 = r_mut__12; + + //for 14 + c_x__14 = r_x__13; + c_y__14 = r_y__13; + c_z__14 = r_z__13; + c_ux__14 = r_ux__13; + c_uy__14 = r_uy__13; + c_uz__14 = r_uz__13; + c_sz__14 = r_sz__13; + c_sr__14 = r_sr__13; + c_sleftz__14 = r_sleftz__13; + c_sleftr__14 = r_sleftr__13; + c_weight__14 = r_weight__13; + c_layer__14 = r_layer__13; + c_dead__14 = r_dead__13; + c_hit__14 = r_hit__13; + c_diff__14 = r_diff__13; + c_dl_b__14 = r_dl_b__13; + c_numer__14 = r_numer__13; + c_z1__14 = r_z1__13; + c_z0__14 = r_z0__13; + c_mut__14 = r_mut__13; + + //for 15 + c_x__15 = r_x__14; + c_y__15 = r_y__14; + c_z__15 = r_z__14; + c_ux__15 = r_ux__14; + c_uy__15 = r_uy__14; + c_uz__15 = r_uz__14; + c_sz__15 = r_sz__14; + c_sr__15 = r_sr__14; + c_sleftz__15 = r_sleftz__14; + c_sleftr__15 = r_sleftr__14; + c_weight__15 = r_weight__14; + c_layer__15 = r_layer__14; + c_dead__15 = r_dead__14; + c_hit__15 = r_hit__14; + c_diff__15 = r_diff__14; + c_dl_b__15 = r_dl_b__14; + c_numer__15 = r_numer__14; + c_z1__15 = r_z1__14; + c_z0__15 = r_z0__14; + c_mut__15 = r_mut__14; + + //for 16 + c_x__16 = r_x__15; + c_y__16 = r_y__15; + c_z__16 = r_z__15; + c_ux__16 = r_ux__15; + c_uy__16 = r_uy__15; + c_uz__16 = r_uz__15; + c_sz__16 = r_sz__15; + c_sr__16 = r_sr__15; + c_sleftz__16 = r_sleftz__15; + c_sleftr__16 = r_sleftr__15; + c_weight__16 = r_weight__15; + c_layer__16 = r_layer__15; + c_dead__16 = r_dead__15; + c_hit__16 = r_hit__15; + c_diff__16 = r_diff__15; + c_dl_b__16 = r_dl_b__15; + c_numer__16 = r_numer__15; + c_z1__16 = r_z1__15; + c_z0__16 = r_z0__15; + c_mut__16 = r_mut__15; + + //for 17 + c_x__17 = r_x__16; + c_y__17 = r_y__16; + c_z__17 = r_z__16; + c_ux__17 = r_ux__16; + c_uy__17 = r_uy__16; + c_uz__17 = r_uz__16; + c_sz__17 = r_sz__16; + c_sr__17 = r_sr__16; + c_sleftz__17 = r_sleftz__16; + c_sleftr__17 = r_sleftr__16; + c_weight__17 = r_weight__16; + c_layer__17 = r_layer__16; + c_dead__17 = r_dead__16; + c_hit__17 = r_hit__16; + c_diff__17 = r_diff__16; + c_dl_b__17 = r_dl_b__16; + c_numer__17 = r_numer__16; + c_z1__17 = r_z1__16; + c_z0__17 = r_z0__16; + c_mut__17 = r_mut__16; + + //for 18 + c_x__18 = r_x__17; + c_y__18 = r_y__17; + c_z__18 = r_z__17; + c_ux__18 = r_ux__17; + c_uy__18 = r_uy__17; + c_uz__18 = r_uz__17; + c_sz__18 = r_sz__17; + c_sr__18 = r_sr__17; + c_sleftz__18 = r_sleftz__17; + c_sleftr__18 = r_sleftr__17; + c_weight__18 = r_weight__17; + c_layer__18 = r_layer__17; + c_dead__18 = r_dead__17; + c_hit__18 = r_hit__17; + c_diff__18 = r_diff__17; + c_dl_b__18 = r_dl_b__17; + c_numer__18 = r_numer__17; + c_z1__18 = r_z1__17; + c_z0__18 = r_z0__17; + c_mut__18 = r_mut__17; + + //for 19 + c_x__19 = r_x__18; + c_y__19 = r_y__18; + c_z__19 = r_z__18; + c_ux__19 = r_ux__18; + c_uy__19 = r_uy__18; + c_uz__19 = r_uz__18; + c_sz__19 = r_sz__18; + c_sr__19 = r_sr__18; + c_sleftz__19 = r_sleftz__18; + c_sleftr__19 = r_sleftr__18; + c_weight__19 = r_weight__18; + c_layer__19 = r_layer__18; + c_dead__19 = r_dead__18; + c_hit__19 = r_hit__18; + c_diff__19 = r_diff__18; + c_dl_b__19 = r_dl_b__18; + c_numer__19 = r_numer__18; + c_z1__19 = r_z1__18; + c_z0__19 = r_z0__18; + c_mut__19 = r_mut__18; + + //for 20 + c_x__20 = r_x__19; + c_y__20 = r_y__19; + c_z__20 = r_z__19; + c_ux__20 = r_ux__19; + c_uy__20 = r_uy__19; + c_uz__20 = r_uz__19; + c_sz__20 = r_sz__19; + c_sr__20 = r_sr__19; + c_sleftz__20 = r_sleftz__19; + c_sleftr__20 = r_sleftr__19; + c_weight__20 = r_weight__19; + c_layer__20 = r_layer__19; + c_dead__20 = r_dead__19; + c_hit__20 = r_hit__19; + c_diff__20 = r_diff__19; + c_dl_b__20 = r_dl_b__19; + c_numer__20 = r_numer__19; + c_z1__20 = r_z1__19; + c_z0__20 = r_z0__19; + c_mut__20 = r_mut__19; + + + //for 21 + c_x__21 = r_x__20; + c_y__21 = r_y__20; + c_z__21 = r_z__20; + c_ux__21 = r_ux__20; + c_uy__21 = r_uy__20; + c_uz__21 = r_uz__20; + c_sz__21 = r_sz__20; + c_sr__21 = r_sr__20; + c_sleftz__21 = r_sleftz__20; + c_sleftr__21 = r_sleftr__20; + c_weight__21 = r_weight__20; + c_layer__21 = r_layer__20; + c_dead__21 = r_dead__20; + c_hit__21 = r_hit__20; + c_diff__21 = r_diff__20; + c_dl_b__21 = r_dl_b__20; + c_numer__21 = r_numer__20; + c_z1__21 = r_z1__20; + c_z0__21 = r_z0__20; + c_mut__21 = r_mut__20; + + //for 22 + c_x__22 = r_x__21; + c_y__22 = r_y__21; + c_z__22 = r_z__21; + c_ux__22 = r_ux__21; + c_uy__22 = r_uy__21; + c_uz__22 = r_uz__21; + c_sz__22 = r_sz__21; + c_sr__22 = r_sr__21; + c_sleftz__22 = r_sleftz__21; + c_sleftr__22 = r_sleftr__21; + c_weight__22 = r_weight__21; + c_layer__22 = r_layer__21; + c_dead__22 = r_dead__21; + c_hit__22 = r_hit__21; + c_diff__22 = r_diff__21; + c_dl_b__22 = r_dl_b__21; + c_numer__22 = r_numer__21; + c_z1__22 = r_z1__21; + c_z0__22 = r_z0__21; + c_mut__22 = r_mut__21; + + //for 23 + c_x__23 = r_x__22; + c_y__23 = r_y__22; + c_z__23 = r_z__22; + c_ux__23 = r_ux__22; + c_uy__23 = r_uy__22; + c_uz__23 = r_uz__22; + c_sz__23 = r_sz__22; + c_sr__23 = r_sr__22; + c_sleftz__23 = r_sleftz__22; + c_sleftr__23 = r_sleftr__22; + c_weight__23 = r_weight__22; + c_layer__23 = r_layer__22; + c_dead__23 = r_dead__22; + c_hit__23 = r_hit__22; + c_diff__23 = r_diff__22; + c_dl_b__23 = r_dl_b__22; + c_numer__23 = r_numer__22; + c_z1__23 = r_z1__22; + c_z0__23 = r_z0__22; + c_mut__23 = r_mut__22; + + //for 24 + c_x__24 = r_x__23; + c_y__24 = r_y__23; + c_z__24 = r_z__23; + c_ux__24 = r_ux__23; + c_uy__24 = r_uy__23; + c_uz__24 = r_uz__23; + c_sz__24 = r_sz__23; + c_sr__24 = r_sr__23; + c_sleftz__24 = r_sleftz__23; + c_sleftr__24 = r_sleftr__23; + c_weight__24 = r_weight__23; + c_layer__24 = r_layer__23; + c_dead__24 = r_dead__23; + c_hit__24 = r_hit__23; + c_diff__24 = r_diff__23; + c_dl_b__24 = r_dl_b__23; + c_numer__24 = r_numer__23; + c_z1__24 = r_z1__23; + c_z0__24 = r_z0__23; + c_mut__24 = r_mut__23; + + //for 25 + c_x__25 = r_x__24; + c_y__25 = r_y__24; + c_z__25 = r_z__24; + c_ux__25 = r_ux__24; + c_uy__25 = r_uy__24; + c_uz__25 = r_uz__24; + c_sz__25 = r_sz__24; + c_sr__25 = r_sr__24; + c_sleftz__25 = r_sleftz__24; + c_sleftr__25 = r_sleftr__24; + c_weight__25 = r_weight__24; + c_layer__25 = r_layer__24; + c_dead__25 = r_dead__24; + c_hit__25 = r_hit__24; + c_diff__25 = r_diff__24; + c_dl_b__25 = r_dl_b__24; + c_numer__25 = r_numer__24; + c_z1__25 = r_z1__24; + c_z0__25 = r_z0__24; + c_mut__25 = r_mut__24; + + //for 26 + c_x__26 = r_x__25; + c_y__26 = r_y__25; + c_z__26 = r_z__25; + c_ux__26 = r_ux__25; + c_uy__26 = r_uy__25; + c_uz__26 = r_uz__25; + c_sz__26 = r_sz__25; + c_sr__26 = r_sr__25; + c_sleftz__26 = r_sleftz__25; + c_sleftr__26 = r_sleftr__25; + c_weight__26 = r_weight__25; + c_layer__26 = r_layer__25; + c_dead__26 = r_dead__25; + c_hit__26 = r_hit__25; + c_diff__26 = r_diff__25; + c_dl_b__26 = r_dl_b__25; + c_numer__26 = r_numer__25; + c_z1__26 = r_z1__25; + c_z0__26 = r_z0__25; + c_mut__26 = r_mut__25; + + //for 27 + c_x__27 = r_x__26; + c_y__27 = r_y__26; + c_z__27 = r_z__26; + c_ux__27 = r_ux__26; + c_uy__27 = r_uy__26; + c_uz__27 = r_uz__26; + c_sz__27 = r_sz__26; + c_sr__27 = r_sr__26; + c_sleftz__27 = r_sleftz__26; + c_sleftr__27 = r_sleftr__26; + c_weight__27 = r_weight__26; + c_layer__27 = r_layer__26; + c_dead__27 = r_dead__26; + c_hit__27 = r_hit__26; + c_diff__27 = r_diff__26; + c_dl_b__27 = r_dl_b__26; + c_numer__27 = r_numer__26; + c_z1__27 = r_z1__26; + c_z0__27 = r_z0__26; + c_mut__27 = r_mut__26; + + //for 28 + c_x__28 = r_x__27; + c_y__28 = r_y__27; + c_z__28 = r_z__27; + c_ux__28 = r_ux__27; + c_uy__28 = r_uy__27; + c_uz__28 = r_uz__27; + c_sz__28 = r_sz__27; + c_sr__28 = r_sr__27; + c_sleftz__28 = r_sleftz__27; + c_sleftr__28 = r_sleftr__27; + c_weight__28 = r_weight__27; + c_layer__28 = r_layer__27; + c_dead__28 = r_dead__27; + c_hit__28 = r_hit__27; + c_diff__28 = r_diff__27; + c_dl_b__28 = r_dl_b__27; + c_numer__28 = r_numer__27; + c_z1__28 = r_z1__27; + c_z0__28 = r_z0__27; + c_mut__28 = r_mut__27; + + //for 29 + c_x__29 = r_x__28; + c_y__29 = r_y__28; + c_z__29 = r_z__28; + c_ux__29 = r_ux__28; + c_uy__29 = r_uy__28; + c_uz__29 = r_uz__28; + c_sz__29 = r_sz__28; + c_sr__29 = r_sr__28; + c_sleftz__29 = r_sleftz__28; + c_sleftr__29 = r_sleftr__28; + c_weight__29 = r_weight__28; + c_layer__29 = r_layer__28; + c_dead__29 = r_dead__28; + c_hit__29 = r_hit__28; + c_diff__29 = r_diff__28; + c_dl_b__29 = r_dl_b__28; + c_numer__29 = r_numer__28; + c_z1__29 = r_z1__28; + c_z0__29 = r_z0__28; + c_mut__29 = r_mut__28; + + //for 30 + c_x__30 = r_x__29; + c_y__30 = r_y__29; + c_z__30 = r_z__29; + c_ux__30 = r_ux__29; + c_uy__30 = r_uy__29; + c_uz__30 = r_uz__29; + c_sz__30 = r_sz__29; + c_sr__30 = r_sr__29; + c_sleftz__30 = r_sleftz__29; + c_sleftr__30 = r_sleftr__29; + c_weight__30 = r_weight__29; + c_layer__30 = r_layer__29; + c_dead__30 = r_dead__29; + // c_hit__30 = r_hit__29;// + // c_diff__30 = r_diff__29;// + // this value is set later, removing default - peter m + // c_dl_b__30 = r_dl_b__29;// + // this one too + c_numer__30 = r_numer__29; + c_z1__30 = r_z1__29; + c_z0__30 = r_z0__29; + c_mut__30 = r_mut__29; + + //for 31 + c_x__31 = r_x__30; + c_y__31 = r_y__30; + // c_z__31 = r_z__30;// + c_ux__31 = r_ux__30; + c_uy__31 = r_uy__30; + c_uz__31 = r_uz__30; + // c_sz__31 = r_sz__30;// + // c_sr__31 = r_sr__30;// + // c_sleftz__31 = r_sleftz__30;// + c_sleftr__31 = r_sleftr__30; + c_weight__31 = r_weight__30; + c_layer__31 = r_layer__30; + c_dead__31 = r_dead__30; + c_hit__31 = r_hit__30; + c_diff__31 = r_diff__30; + c_dl_b__31 = r_dl_b__30; + c_numer__31 = r_numer__30; + c_z1__31 = r_z1__30; + c_z0__31 = r_z0__30; + c_mut__31 = r_mut__30; + + //for 32 + c_x__32 = r_x__31; + c_y__32 = r_y__31; + c_z__32 = r_z__31; + c_ux__32 = r_ux__31; + c_uy__32 = r_uy__31; + c_uz__32 = r_uz__31; + c_sz__32 = r_sz__31; + c_sr__32 = r_sr__31; + c_sleftz__32 = r_sleftz__31; + // c_sleftr__32 = r_sleftr__31;// + c_weight__32 = r_weight__31; + c_layer__32 = r_layer__31; + c_dead__32 = r_dead__31; + c_hit__32 = r_hit__31; + c_diff__32 = r_diff__31; + c_dl_b__32 = r_dl_b__31; + c_numer__32 = r_numer__31; + c_z1__32 = r_z1__31; + c_z0__32 = r_z0__31; + c_mut__32 = r_mut__31; + + //for 33 + c_x__33 = r_x__32; + c_y__33 = r_y__32; + c_z__33 = r_z__32; + c_ux__33 = r_ux__32; + c_uy__33 = r_uy__32; + c_uz__33 = r_uz__32; + c_sz__33 = r_sz__32; + c_sr__33 = r_sr__32; + c_sleftz__33 = r_sleftz__32; + c_sleftr__33 = r_sleftr__32; + c_weight__33 = r_weight__32; + c_layer__33 = r_layer__32; + c_dead__33 = r_dead__32; + c_hit__33 = r_hit__32; + c_diff__33 = r_diff__32; + c_dl_b__33 = r_dl_b__32; + c_numer__33 = r_numer__32; + c_z1__33 = r_z1__32; + c_z0__33 = r_z0__32; + c_mut__33 = r_mut__32; + + //for 34 + c_x__34 = r_x__33; + c_y__34 = r_y__33; + c_z__34 = r_z__33; + c_ux__34 = r_ux__33; + c_uy__34 = r_uy__33; + c_uz__34 = r_uz__33; + c_sz__34 = r_sz__33; + c_sr__34 = r_sr__33; + c_sleftz__34 = r_sleftz__33; + c_sleftr__34 = r_sleftr__33; + c_weight__34 = r_weight__33; + c_layer__34 = r_layer__33; + c_dead__34 = r_dead__33; + c_hit__34 = r_hit__33; + c_diff__34 = r_diff__33; + c_dl_b__34 = r_dl_b__33; + c_numer__34 = r_numer__33; + c_z1__34 = r_z1__33; + c_z0__34 = r_z0__33; + c_mut__34 = r_mut__33; + + //for 35 + c_x__35 = r_x__34; + c_y__35 = r_y__34; + c_z__35 = r_z__34; + c_ux__35 = r_ux__34; + c_uy__35 = r_uy__34; + c_uz__35 = r_uz__34; + c_sz__35 = r_sz__34; + c_sr__35 = r_sr__34; + c_sleftz__35 = r_sleftz__34; + c_sleftr__35 = r_sleftr__34; + c_weight__35 = r_weight__34; + c_layer__35 = r_layer__34; + c_dead__35 = r_dead__34; + c_hit__35 = r_hit__34; + c_diff__35 = r_diff__34; + c_dl_b__35 = r_dl_b__34; + c_numer__35 = r_numer__34; + c_z1__35 = r_z1__34; + c_z0__35 = r_z0__34; + c_mut__35 = r_mut__34; + + //for 36 + c_x__36 = r_x__35; + c_y__36 = r_y__35; + c_z__36 = r_z__35; + c_ux__36 = r_ux__35; + c_uy__36 = r_uy__35; + c_uz__36 = r_uz__35; + c_sz__36 = r_sz__35; + c_sr__36 = r_sr__35; + c_sleftz__36 = r_sleftz__35; + c_sleftr__36 = r_sleftr__35; + c_weight__36 = r_weight__35; + c_layer__36 = r_layer__35; + c_dead__36 = r_dead__35; + c_hit__36 = r_hit__35; + c_diff__36 = r_diff__35; + c_dl_b__36 = r_dl_b__35; + c_numer__36 = r_numer__35; + c_z1__36 = r_z1__35; + c_z0__36 = r_z0__35; + c_mut__36 = r_mut__35; + + //for 37 + c_x__37 = r_x__36; + c_y__37 = r_y__36; + c_z__37 = r_z__36; + c_ux__37 = r_ux__36; + c_uy__37 = r_uy__36; + c_uz__37 = r_uz__36; + c_sz__37 = r_sz__36; + c_sr__37 = r_sr__36; + c_sleftz__37 = r_sleftz__36; + c_sleftr__37 = r_sleftr__36; + c_weight__37 = r_weight__36; + c_layer__37 = r_layer__36; + c_dead__37 = r_dead__36; + c_hit__37 = r_hit__36; + c_diff__37 = r_diff__36; + c_dl_b__37 = r_dl_b__36; + c_numer__37 = r_numer__36; + c_z1__37 = r_z1__36; + c_z0__37 = r_z0__36; + c_mut__37 = r_mut__36; + + //for 38 + c_x__38 = r_x__37; + c_y__38 = r_y__37; + c_z__38 = r_z__37; + c_ux__38 = r_ux__37; + c_uy__38 = r_uy__37; + c_uz__38 = r_uz__37; + c_sz__38 = r_sz__37; + c_sr__38 = r_sr__37; + c_sleftz__38 = r_sleftz__37; + c_sleftr__38 = r_sleftr__37; + c_weight__38 = r_weight__37; + c_layer__38 = r_layer__37; + c_dead__38 = r_dead__37; + c_hit__38 = r_hit__37; + c_diff__38 = r_diff__37; + c_dl_b__38 = r_dl_b__37; + c_numer__38 = r_numer__37; + c_z1__38 = r_z1__37; + c_z0__38 = r_z0__37; + c_mut__38 = r_mut__37; + + //for 39 + c_x__39 = r_x__38; + c_y__39 = r_y__38; + c_z__39 = r_z__38; + c_ux__39 = r_ux__38; + c_uy__39 = r_uy__38; + c_uz__39 = r_uz__38; + c_sz__39 = r_sz__38; + c_sr__39 = r_sr__38; + c_sleftz__39 = r_sleftz__38; + c_sleftr__39 = r_sleftr__38; + c_weight__39 = r_weight__38; + c_layer__39 = r_layer__38; + c_dead__39 = r_dead__38; + c_hit__39 = r_hit__38; + c_diff__39 = r_diff__38; + c_dl_b__39 = r_dl_b__38; + c_numer__39 = r_numer__38; + c_z1__39 = r_z1__38; + c_z0__39 = r_z0__38; + c_mut__39 = r_mut__38; + + //for 40 + c_x__40 = r_x__39; + c_y__40 = r_y__39; + c_z__40 = r_z__39; + c_ux__40 = r_ux__39; + c_uy__40 = r_uy__39; + c_uz__40 = r_uz__39; + c_sz__40 = r_sz__39; + c_sr__40 = r_sr__39; + c_sleftz__40 = r_sleftz__39; + c_sleftr__40 = r_sleftr__39; + c_weight__40 = r_weight__39; + c_layer__40 = r_layer__39; + c_dead__40 = r_dead__39; + c_hit__40 = r_hit__39; + c_diff__40 = r_diff__39; + c_dl_b__40 = r_dl_b__39; + c_numer__40 = r_numer__39; + c_z1__40 = r_z1__39; + c_z0__40 = r_z0__39; + c_mut__40 = r_mut__39; + + //for 41 + c_x__41 = r_x__40; + c_y__41 = r_y__40; + c_z__41 = r_z__40; + c_ux__41 = r_ux__40; + c_uy__41 = r_uy__40; + c_uz__41 = r_uz__40; + c_sz__41 = r_sz__40; + c_sr__41 = r_sr__40; + c_sleftz__41 = r_sleftz__40; + c_sleftr__41 = r_sleftr__40; + c_weight__41 = r_weight__40; + c_layer__41 = r_layer__40; + c_dead__41 = r_dead__40; + c_hit__41 = r_hit__40; + c_diff__41 = r_diff__40; + c_dl_b__41 = r_dl_b__40; + c_numer__41 = r_numer__40; + c_z1__41 = r_z1__40; + c_z0__41 = r_z0__40; + c_mut__41 = r_mut__40; + + //for 42 + c_x__42 = r_x__41; + c_y__42 = r_y__41; + c_z__42 = r_z__41; + c_ux__42 = r_ux__41; + c_uy__42 = r_uy__41; + c_uz__42 = r_uz__41; + c_sz__42 = r_sz__41; + c_sr__42 = r_sr__41; + c_sleftz__42 = r_sleftz__41; + c_sleftr__42 = r_sleftr__41; + c_weight__42 = r_weight__41; + c_layer__42 = r_layer__41; + c_dead__42 = r_dead__41; + c_hit__42 = r_hit__41; + c_diff__42 = r_diff__41; + c_dl_b__42 = r_dl_b__41; + c_numer__42 = r_numer__41; + c_z1__42 = r_z1__41; + c_z0__42 = r_z0__41; + c_mut__42 = r_mut__41; + + //for 43 + c_x__43 = r_x__42; + c_y__43 = r_y__42; + c_z__43 = r_z__42; + c_ux__43 = r_ux__42; + c_uy__43 = r_uy__42; + c_uz__43 = r_uz__42; + c_sz__43 = r_sz__42; + c_sr__43 = r_sr__42; + c_sleftz__43 = r_sleftz__42; + c_sleftr__43 = r_sleftr__42; + c_weight__43 = r_weight__42; + c_layer__43 = r_layer__42; + c_dead__43 = r_dead__42; + c_hit__43 = r_hit__42; + c_diff__43 = r_diff__42; + c_dl_b__43 = r_dl_b__42; + c_numer__43 = r_numer__42; + c_z1__43 = r_z1__42; + c_z0__43 = r_z0__42; + c_mut__43 = r_mut__42; + + //for 44 + c_x__44 = r_x__43; + c_y__44 = r_y__43; + c_z__44 = r_z__43; + c_ux__44 = r_ux__43; + c_uy__44 = r_uy__43; + c_uz__44 = r_uz__43; + c_sz__44 = r_sz__43; + c_sr__44 = r_sr__43; + c_sleftz__44 = r_sleftz__43; + c_sleftr__44 = r_sleftr__43; + c_weight__44 = r_weight__43; + c_layer__44 = r_layer__43; + c_dead__44 = r_dead__43; + c_hit__44 = r_hit__43; + c_diff__44 = r_diff__43; + c_dl_b__44 = r_dl_b__43; + c_numer__44 = r_numer__43; + c_z1__44 = r_z1__43; + c_z0__44 = r_z0__43; + c_mut__44 = r_mut__43; + + //for 45 + c_x__45 = r_x__44; + c_y__45 = r_y__44; + c_z__45 = r_z__44; + c_ux__45 = r_ux__44; + c_uy__45 = r_uy__44; + c_uz__45 = r_uz__44; + c_sz__45 = r_sz__44; + c_sr__45 = r_sr__44; + c_sleftz__45 = r_sleftz__44; + c_sleftr__45 = r_sleftr__44; + c_weight__45 = r_weight__44; + c_layer__45 = r_layer__44; + c_dead__45 = r_dead__44; + c_hit__45 = r_hit__44; + c_diff__45 = r_diff__44; + c_dl_b__45 = r_dl_b__44; + c_numer__45 = r_numer__44; + c_z1__45 = r_z1__44; + c_z0__45 = r_z0__44; + c_mut__45 = r_mut__44; + + //for 46 + c_x__46 = r_x__45; + c_y__46 = r_y__45; + c_z__46 = r_z__45; + c_ux__46 = r_ux__45; + c_uy__46 = r_uy__45; + c_uz__46 = r_uz__45; + c_sz__46 = r_sz__45; + c_sr__46 = r_sr__45; + c_sleftz__46 = r_sleftz__45; + c_sleftr__46 = r_sleftr__45; + c_weight__46 = r_weight__45; + c_layer__46 = r_layer__45; + c_dead__46 = r_dead__45; + c_hit__46 = r_hit__45; + c_diff__46 = r_diff__45; + c_dl_b__46 = r_dl_b__45; + c_numer__46 = r_numer__45; + c_z1__46 = r_z1__45; + c_z0__46 = r_z0__45; + c_mut__46 = r_mut__45; + + //for 47 + c_x__47 = r_x__46; + c_y__47 = r_y__46; + c_z__47 = r_z__46; + c_ux__47 = r_ux__46; + c_uy__47 = r_uy__46; + c_uz__47 = r_uz__46; + c_sz__47 = r_sz__46; + c_sr__47 = r_sr__46; + c_sleftz__47 = r_sleftz__46; + c_sleftr__47 = r_sleftr__46; + c_weight__47 = r_weight__46; + c_layer__47 = r_layer__46; + c_dead__47 = r_dead__46; + c_hit__47 = r_hit__46; + c_diff__47 = r_diff__46; + c_dl_b__47 = r_dl_b__46; + c_numer__47 = r_numer__46; + c_z1__47 = r_z1__46; + c_z0__47 = r_z0__46; + c_mut__47 = r_mut__46; + + //for 48 + c_x__48 = r_x__47; + c_y__48 = r_y__47; + c_z__48 = r_z__47; + c_ux__48 = r_ux__47; + c_uy__48 = r_uy__47; + c_uz__48 = r_uz__47; + c_sz__48 = r_sz__47; + c_sr__48 = r_sr__47; + c_sleftz__48 = r_sleftz__47; + c_sleftr__48 = r_sleftr__47; + c_weight__48 = r_weight__47; + c_layer__48 = r_layer__47; + c_dead__48 = r_dead__47; + c_hit__48 = r_hit__47; + c_diff__48 = r_diff__47; + c_dl_b__48 = r_dl_b__47; + c_numer__48 = r_numer__47; + c_z1__48 = r_z1__47; + c_z0__48 = r_z0__47; + c_mut__48 = r_mut__47; + + //for 49 + c_x__49 = r_x__48; + c_y__49 = r_y__48; + c_z__49 = r_z__48; + c_ux__49 = r_ux__48; + c_uy__49 = r_uy__48; + c_uz__49 = r_uz__48; + c_sz__49 = r_sz__48; + c_sr__49 = r_sr__48; + c_sleftz__49 = r_sleftz__48; + c_sleftr__49 = r_sleftr__48; + c_weight__49 = r_weight__48; + c_layer__49 = r_layer__48; + c_dead__49 = r_dead__48; + c_hit__49 = r_hit__48; + c_diff__49 = r_diff__48; + c_dl_b__49 = r_dl_b__48; + c_numer__49 = r_numer__48; + c_z1__49 = r_z1__48; + c_z0__49 = r_z0__48; + c_mut__49 = r_mut__48; + + //for 50 + c_x__50 = r_x__49; + c_y__50 = r_y__49; + c_z__50 = r_z__49; + c_ux__50 = r_ux__49; + c_uy__50 = r_uy__49; + c_uz__50 = r_uz__49; + c_sz__50 = r_sz__49; + c_sr__50 = r_sr__49; + c_sleftz__50 = r_sleftz__49; + c_sleftr__50 = r_sleftr__49; + c_weight__50 = r_weight__49; + c_layer__50 = r_layer__49; + c_dead__50 = r_dead__49; + c_hit__50 = r_hit__49; + c_diff__50 = r_diff__49; + c_dl_b__50 = r_dl_b__49; + c_numer__50 = r_numer__49; + c_z1__50 = r_z1__49; + c_z0__50 = r_z0__49; + c_mut__50 = r_mut__49; + + //for 51 + c_x__51 = r_x__50; + c_y__51 = r_y__50; + c_z__51 = r_z__50; + c_ux__51 = r_ux__50; + c_uy__51 = r_uy__50; + c_uz__51 = r_uz__50; + c_sz__51 = r_sz__50; + c_sr__51 = r_sr__50; + c_sleftz__51 = r_sleftz__50; + c_sleftr__51 = r_sleftr__50; + c_weight__51 = r_weight__50; + c_layer__51 = r_layer__50; + c_dead__51 = r_dead__50; + c_hit__51 = r_hit__50; + c_diff__51 = r_diff__50; + c_dl_b__51 = r_dl_b__50; + c_numer__51 = r_numer__50; + c_z1__51 = r_z1__50; + c_z0__51 = r_z0__50; + c_mut__51 = r_mut__50; + + //for 52 + c_x__52 = r_x__51; + c_y__52 = r_y__51; + c_z__52 = r_z__51; + c_ux__52 = r_ux__51; + c_uy__52 = r_uy__51; + c_uz__52 = r_uz__51; + c_sz__52 = r_sz__51; + c_sr__52 = r_sr__51; + c_sleftz__52 = r_sleftz__51; + c_sleftr__52 = r_sleftr__51; + c_weight__52 = r_weight__51; + c_layer__52 = r_layer__51; + c_dead__52 = r_dead__51; + c_hit__52 = r_hit__51; + c_diff__52 = r_diff__51; + c_dl_b__52 = r_dl_b__51; + c_numer__52 = r_numer__51; + c_z1__52 = r_z1__51; + c_z0__52 = r_z0__51; + c_mut__52 = r_mut__51; + + //for 53 + c_x__53 = r_x__52; + c_y__53 = r_y__52; + c_z__53 = r_z__52; + c_ux__53 = r_ux__52; + c_uy__53 = r_uy__52; + c_uz__53 = r_uz__52; + c_sz__53 = r_sz__52; + c_sr__53 = r_sr__52; + c_sleftz__53 = r_sleftz__52; + c_sleftr__53 = r_sleftr__52; + c_weight__53 = r_weight__52; + c_layer__53 = r_layer__52; + c_dead__53 = r_dead__52; + c_hit__53 = r_hit__52; + c_diff__53 = r_diff__52; + c_dl_b__53 = r_dl_b__52; + c_numer__53 = r_numer__52; + c_z1__53 = r_z1__52; + c_z0__53 = r_z0__52; + c_mut__53 = r_mut__52; + + //for 54 + c_x__54 = r_x__53; + c_y__54 = r_y__53; + c_z__54 = r_z__53; + c_ux__54 = r_ux__53; + c_uy__54 = r_uy__53; + c_uz__54 = r_uz__53; + c_sz__54 = r_sz__53; + c_sr__54 = r_sr__53; + c_sleftz__54 = r_sleftz__53; + c_sleftr__54 = r_sleftr__53; + c_weight__54 = r_weight__53; + c_layer__54 = r_layer__53; + c_dead__54 = r_dead__53; + c_hit__54 = r_hit__53; + c_diff__54 = r_diff__53; + c_dl_b__54 = r_dl_b__53; + c_numer__54 = r_numer__53; + c_z1__54 = r_z1__53; + c_z0__54 = r_z0__53; + c_mut__54 = r_mut__53; + + //for 55 + c_x__55 = r_x__54; + c_y__55 = r_y__54; + c_z__55 = r_z__54; + c_ux__55 = r_ux__54; + c_uy__55 = r_uy__54; + c_uz__55 = r_uz__54; + c_sz__55 = r_sz__54; + c_sr__55 = r_sr__54; + c_sleftz__55 = r_sleftz__54; + c_sleftr__55 = r_sleftr__54; + c_weight__55 = r_weight__54; + c_layer__55 = r_layer__54; + c_dead__55 = r_dead__54; + c_hit__55 = r_hit__54; + c_diff__55 = r_diff__54; + c_dl_b__55 = r_dl_b__54; + c_numer__55 = r_numer__54; + c_z1__55 = r_z1__54; + c_z0__55 = r_z0__54; + c_mut__55 = r_mut__54; + + //for 56 + c_x__56 = r_x__55; + c_y__56 = r_y__55; + c_z__56 = r_z__55; + c_ux__56 = r_ux__55; + c_uy__56 = r_uy__55; + c_uz__56 = r_uz__55; + c_sz__56 = r_sz__55; + c_sr__56 = r_sr__55; + c_sleftz__56 = r_sleftz__55; + c_sleftr__56 = r_sleftr__55; + c_weight__56 = r_weight__55; + c_layer__56 = r_layer__55; + c_dead__56 = r_dead__55; + c_hit__56 = r_hit__55; + c_diff__56 = r_diff__55; + c_dl_b__56 = r_dl_b__55; + c_numer__56 = r_numer__55; + c_z1__56 = r_z1__55; + c_z0__56 = r_z0__55; + c_mut__56 = r_mut__55; + + //for 57 + c_x__57 = r_x__56; + c_y__57 = r_y__56; + c_z__57 = r_z__56; + c_ux__57 = r_ux__56; + c_uy__57 = r_uy__56; + c_uz__57 = r_uz__56; + c_sz__57 = r_sz__56; + c_sr__57 = r_sr__56; + c_sleftz__57 = r_sleftz__56; + c_sleftr__57 = r_sleftr__56; + c_weight__57 = r_weight__56; + c_layer__57 = r_layer__56; + c_dead__57 = r_dead__56; + c_hit__57 = r_hit__56; + c_diff__57 = r_diff__56; + c_dl_b__57 = r_dl_b__56; + c_numer__57 = r_numer__56; + c_z1__57 = r_z1__56; + c_z0__57 = r_z0__56; + c_mut__57 = r_mut__56; + + //for 58 + c_x__58 = r_x__57; + c_y__58 = r_y__57; + c_z__58 = r_z__57; + c_ux__58 = r_ux__57; + c_uy__58 = r_uy__57; + c_uz__58 = r_uz__57; + c_sz__58 = r_sz__57; + c_sr__58 = r_sr__57; + c_sleftz__58 = r_sleftz__57; + c_sleftr__58 = r_sleftr__57; + c_weight__58 = r_weight__57; + c_layer__58 = r_layer__57; + c_dead__58 = r_dead__57; + c_hit__58 = r_hit__57; + c_diff__58 = r_diff__57; + c_dl_b__58 = r_dl_b__57; + c_numer__58 = r_numer__57; + c_z1__58 = r_z1__57; + c_z0__58 = r_z0__57; + c_mut__58 = r_mut__57; + + //for 59 + c_x__59 = r_x__58; + c_y__59 = r_y__58; + c_z__59 = r_z__58; + c_ux__59 = r_ux__58; + c_uy__59 = r_uy__58; + c_uz__59 = r_uz__58; + c_sz__59 = r_sz__58; + c_sr__59 = r_sr__58; + c_sleftz__59 = r_sleftz__58; + c_sleftr__59 = r_sleftr__58; + c_weight__59 = r_weight__58; + c_layer__59 = r_layer__58; + c_dead__59 = r_dead__58; + c_hit__59 = r_hit__58; + c_diff__59 = r_diff__58; + c_dl_b__59 = r_dl_b__58; + c_numer__59 = r_numer__58; + c_z1__59 = r_z1__58; + c_z0__59 = r_z0__58; + c_mut__59 = r_mut__58; + + + // Pull out and replace signals in pipe + /* STAGE 1: Division completed */ + c_dl_b__30 = quotient_div1[32:1]; + c_diff__30 = c_sz__30 - c_dl_b__30; + + if(c_uz__30 != 32'b0 && c_sz__30 > c_dl_b__30 && quotient_div1[63:32] == 32'b0) + begin + /* not horizontal & crossing. */ + c_hit__30 = 1'b1; + end + //Remove blocking on c_hit__30 + else + begin + c_hit__30 = r_hit__29; + end + + /* STAGE 2: First multiply completed */ + if(c_hit__31 == 1'b1) + begin + /*step left = (original step - distance travelled) * scaling factor*/ + + c_sleftz__31 = sleftz_big[2*`BIT_WIDTH-2:`BIT_WIDTH - 1]; + if(c_uz__31[`BIT_WIDTH-1] == 1'b0) + begin + c_z__31 = c_z1__31; + end + else + begin + c_z__31 = c_z0__31; + end + + c_sz__31 = c_dl_b__31; + c_sr__31 = sr_big[2*`BIT_WIDTH-2 - `ASPECT_RATIO:`BIT_WIDTH - 1 - `ASPECT_RATIO]; + end + //Remove blocking on c_sleftz_31, c_sr__31, c_sz__31, c_z__31 + else + begin + c_sleftz__31 = r_sleftz__30; + c_sr__31 = r_sr__30; + c_sz__31 = r_sz__30; + c_z__31 = r_z__30; + end + + /* STAGE 3: Second multiply completed */ + if(c_hit__32 == 1'b1) + begin + /*additional scaling factor on dl_b to switch to r-dimension scale*/ + c_sleftr__32 = sleftr_big[2*`BIT_WIDTH-2 - `ASPECT_RATIO:`BIT_WIDTH - 1 - `ASPECT_RATIO]; + end + //Remove blocking on c_sleftr__32 + else + begin + c_sleftr__32 = r_sleftr__31; + + end +end + +// latch values +always @ (posedge clock) +begin +// for(j = 0; j < `TOTAL_LATENCY; j = j + 1) +// begin +// if (reset) +// begin +// r_x[j] <= 32'b0; +// r_y[j] <= 32'b0; +// r_z[j] <= 32'b0; +// r_ux[j] <= 32'b0; +// r_uy[j] <= 32'b0; +// r_uz[j] <= 32'b0; +// r_sz[j] <= 32'b0; +// r_sr[j] <= 32'b0; +// r_sleftz[j] <= 32'b0; +// r_sleftr[j] <= 32'b0; +// r_weight[j] <= 32'b0; +// r_layer[j] <= 3'b0; +// r_dead[j] <= 1'b1; +// r_hit[j] <= 1'b0; +// r_diff[j] <= 32'b0; +// r_dl_b[j] <= 32'b0; +// r_numer[j] <= 64'b0; +// r_z1[j] <= 32'b0; +// r_z0[j] <= 32'b0; +// r_mut[j] <= 32'b0; +// end +// else +// begin +// if(enable) +// begin +// r_x[j] <= c_x[j]; +// r_y[j] <= c_y[j]; +// r_z[j] <= c_z[j]; +// r_ux[j] <= c_ux[j]; +// r_uy[j] <= c_uy[j]; +// r_uz[j] <= c_uz[j]; +// r_sz[j] <= c_sz[j]; +// r_sr[j] <= c_sr[j]; +// r_sleftz[j] <= c_sleftz[j]; +// r_sleftr[j] <= c_sleftr[j]; +// r_weight[j] <= c_weight[j]; +// r_layer[j] <= c_layer[j]; +// r_dead[j] <= c_dead[j]; +// r_hit[j] <= c_hit[j]; +// r_diff[j] <= c_diff[j]; +// r_dl_b[j] <= c_dl_b[j]; +// r_numer[j] <= c_numer[j]; +// r_z1[j] <= c_z1[j]; +// r_z0[j] <= c_z0[j]; +// r_mut[j] <= c_mut[j]; +// end +// end +// end + if(reset) + begin + //Instantiate all 60 aspects of loop + r_x__59 <= 32'b00000000000000000000000000000000; + r_y__59 <= 32'b00000000000000000000000000000000; + r_z__59 <= 32'b00000000000000000000000000000000; + r_ux__59 <= 32'b00000000000000000000000000000000; + r_uy__59 <= 32'b00000000000000000000000000000000; + r_uz__59 <= 32'b00000000000000000000000000000000; + r_sz__59 <= 32'b00000000000000000000000000000000; + r_sr__59 <= 32'b00000000000000000000000000000000; + r_sleftz__59 <= 32'b00000000000000000000000000000000; + r_sleftr__59 <= 32'b00000000000000000000000000000000; + r_weight__59 <= 32'b00000000000000000000000000000000; + r_layer__59 <= 3'b000; + r_dead__59 <= 1'b1; + r_hit__59 <= 1'b0; + r_diff__59 <= 32'b00000000000000000000000000000000; + r_dl_b__59 <= 32'b00000000000000000000000000000000; + r_numer__59 <= 0; + r_z1__59 <= 32'b00000000000000000000000000000000; + r_z0__59 <= 32'b00000000000000000000000000000000; + r_mut__59 <= 32'b00000000000000000000000000000000; + + r_x__58 <= 32'b00000000000000000000000000000000; + r_y__58 <= 32'b00000000000000000000000000000000; + r_z__58 <= 32'b00000000000000000000000000000000; + r_ux__58 <= 32'b00000000000000000000000000000000; + r_uy__58 <= 32'b00000000000000000000000000000000; + r_uz__58 <= 32'b00000000000000000000000000000000; + r_sz__58 <= 32'b00000000000000000000000000000000; + r_sr__58 <= 32'b00000000000000000000000000000000; + r_sleftz__58 <= 32'b00000000000000000000000000000000; + r_sleftr__58 <= 32'b00000000000000000000000000000000; + r_weight__58 <= 32'b00000000000000000000000000000000; + r_layer__58 <= 3'b000; + r_dead__58 <= 1'b1; + r_hit__58 <= 1'b0; + r_diff__58 <= 32'b00000000000000000000000000000000; + r_dl_b__58 <= 32'b00000000000000000000000000000000; + r_numer__58 <= 0; + r_z1__58 <= 32'b00000000000000000000000000000000; + r_z0__58 <= 32'b00000000000000000000000000000000; + r_mut__58 <= 32'b00000000000000000000000000000000; + + r_x__57 <= 32'b00000000000000000000000000000000; + r_y__57 <= 32'b00000000000000000000000000000000; + r_z__57 <= 32'b00000000000000000000000000000000; + r_ux__57 <= 32'b00000000000000000000000000000000; + r_uy__57 <= 32'b00000000000000000000000000000000; + r_uz__57 <= 32'b00000000000000000000000000000000; + r_sz__57 <= 32'b00000000000000000000000000000000; + r_sr__57 <= 32'b00000000000000000000000000000000; + r_sleftz__57 <= 32'b00000000000000000000000000000000; + r_sleftr__57 <= 32'b00000000000000000000000000000000; + r_weight__57 <= 32'b00000000000000000000000000000000; + r_layer__57 <= 3'b000; + r_dead__57 <= 1'b1; + r_hit__57 <= 1'b0; + r_diff__57 <= 32'b00000000000000000000000000000000; + r_dl_b__57 <= 32'b00000000000000000000000000000000; + r_numer__57 <= 0; + r_z1__57 <= 32'b00000000000000000000000000000000; + r_z0__57 <= 32'b00000000000000000000000000000000; + r_mut__57 <= 32'b00000000000000000000000000000000; + + r_x__56 <= 32'b00000000000000000000000000000000; + r_y__56 <= 32'b00000000000000000000000000000000; + r_z__56 <= 32'b00000000000000000000000000000000; + r_ux__56 <= 32'b00000000000000000000000000000000; + r_uy__56 <= 32'b00000000000000000000000000000000; + r_uz__56 <= 32'b00000000000000000000000000000000; + r_sz__56 <= 32'b00000000000000000000000000000000; + r_sr__56 <= 32'b00000000000000000000000000000000; + r_sleftz__56 <= 32'b00000000000000000000000000000000; + r_sleftr__56 <= 32'b00000000000000000000000000000000; + r_weight__56 <= 32'b00000000000000000000000000000000; + r_layer__56 <= 3'b000; + r_dead__56 <= 1'b1; + r_hit__56 <= 1'b0; + r_diff__56 <= 32'b00000000000000000000000000000000; + r_dl_b__56 <= 32'b00000000000000000000000000000000; + r_numer__56 <= 0; + r_z1__56 <= 32'b00000000000000000000000000000000; + r_z0__56 <= 32'b00000000000000000000000000000000; + r_mut__56 <= 32'b00000000000000000000000000000000; + + r_x__55 <= 32'b00000000000000000000000000000000; + r_y__55 <= 32'b00000000000000000000000000000000; + r_z__55 <= 32'b00000000000000000000000000000000; + r_ux__55 <= 32'b00000000000000000000000000000000; + r_uy__55 <= 32'b00000000000000000000000000000000; + r_uz__55 <= 32'b00000000000000000000000000000000; + r_sz__55 <= 32'b00000000000000000000000000000000; + r_sr__55 <= 32'b00000000000000000000000000000000; + r_sleftz__55 <= 32'b00000000000000000000000000000000; + r_sleftr__55 <= 32'b00000000000000000000000000000000; + r_weight__55 <= 32'b00000000000000000000000000000000; + r_layer__55 <= 3'b000; + r_dead__55 <= 1'b1; + r_hit__55 <= 1'b0; + r_diff__55 <= 32'b00000000000000000000000000000000; + r_dl_b__55 <= 32'b00000000000000000000000000000000; + r_numer__55 <= 0; + r_z1__55 <= 32'b00000000000000000000000000000000; + r_z0__55 <= 32'b00000000000000000000000000000000; + r_mut__55 <= 32'b00000000000000000000000000000000; + + r_x__54 <= 32'b00000000000000000000000000000000; + r_y__54 <= 32'b00000000000000000000000000000000; + r_z__54 <= 32'b00000000000000000000000000000000; + r_ux__54 <= 32'b00000000000000000000000000000000; + r_uy__54 <= 32'b00000000000000000000000000000000; + r_uz__54 <= 32'b00000000000000000000000000000000; + r_sz__54 <= 32'b00000000000000000000000000000000; + r_sr__54 <= 32'b00000000000000000000000000000000; + r_sleftz__54 <= 32'b00000000000000000000000000000000; + r_sleftr__54 <= 32'b00000000000000000000000000000000; + r_weight__54 <= 32'b00000000000000000000000000000000; + r_layer__54 <= 3'b000; + r_dead__54 <= 1'b1; + r_hit__54 <= 1'b0; + r_diff__54 <= 32'b00000000000000000000000000000000; + r_dl_b__54 <= 32'b00000000000000000000000000000000; + r_numer__54 <= 0; + r_z1__54 <= 32'b00000000000000000000000000000000; + r_z0__54 <= 32'b00000000000000000000000000000000; + r_mut__54 <= 32'b00000000000000000000000000000000; + + r_x__53 <= 32'b00000000000000000000000000000000; + r_y__53 <= 32'b00000000000000000000000000000000; + r_z__53 <= 32'b00000000000000000000000000000000; + r_ux__53 <= 32'b00000000000000000000000000000000; + r_uy__53 <= 32'b00000000000000000000000000000000; + r_uz__53 <= 32'b00000000000000000000000000000000; + r_sz__53 <= 32'b00000000000000000000000000000000; + r_sr__53 <= 32'b00000000000000000000000000000000; + r_sleftz__53 <= 32'b00000000000000000000000000000000; + r_sleftr__53 <= 32'b00000000000000000000000000000000; + r_weight__53 <= 32'b00000000000000000000000000000000; + r_layer__53 <= 3'b000; + r_dead__53 <= 1'b1; + r_hit__53 <= 1'b0; + r_diff__53 <= 32'b00000000000000000000000000000000; + r_dl_b__53 <= 32'b00000000000000000000000000000000; + r_numer__53 <= 0; + r_z1__53 <= 32'b00000000000000000000000000000000; + r_z0__53 <= 32'b00000000000000000000000000000000; + r_mut__53 <= 32'b00000000000000000000000000000000; + + r_x__52 <= 32'b00000000000000000000000000000000; + r_y__52 <= 32'b00000000000000000000000000000000; + r_z__52 <= 32'b00000000000000000000000000000000; + r_ux__52 <= 32'b00000000000000000000000000000000; + r_uy__52 <= 32'b00000000000000000000000000000000; + r_uz__52 <= 32'b00000000000000000000000000000000; + r_sz__52 <= 32'b00000000000000000000000000000000; + r_sr__52 <= 32'b00000000000000000000000000000000; + r_sleftz__52 <= 32'b00000000000000000000000000000000; + r_sleftr__52 <= 32'b00000000000000000000000000000000; + r_weight__52 <= 32'b00000000000000000000000000000000; + r_layer__52 <= 3'b000; + r_dead__52 <= 1'b1; + r_hit__52 <= 1'b0; + r_diff__52 <= 32'b00000000000000000000000000000000; + r_dl_b__52 <= 32'b00000000000000000000000000000000; + r_numer__52 <= 0; + r_z1__52 <= 32'b00000000000000000000000000000000; + r_z0__52 <= 32'b00000000000000000000000000000000; + r_mut__52 <= 32'b00000000000000000000000000000000; + + r_x__51 <= 32'b00000000000000000000000000000000; + r_y__51 <= 32'b00000000000000000000000000000000; + r_z__51 <= 32'b00000000000000000000000000000000; + r_ux__51 <= 32'b00000000000000000000000000000000; + r_uy__51 <= 32'b00000000000000000000000000000000; + r_uz__51 <= 32'b00000000000000000000000000000000; + r_sz__51 <= 32'b00000000000000000000000000000000; + r_sr__51 <= 32'b00000000000000000000000000000000; + r_sleftz__51 <= 32'b00000000000000000000000000000000; + r_sleftr__51 <= 32'b00000000000000000000000000000000; + r_weight__51 <= 32'b00000000000000000000000000000000; + r_layer__51 <= 3'b000; + r_dead__51 <= 1'b1; + r_hit__51 <= 1'b0; + r_diff__51 <= 32'b00000000000000000000000000000000; + r_dl_b__51 <= 32'b00000000000000000000000000000000; + r_numer__51 <= 0; + r_z1__51 <= 32'b00000000000000000000000000000000; + r_z0__51 <= 32'b00000000000000000000000000000000; + r_mut__51 <= 32'b00000000000000000000000000000000; + + r_x__50 <= 32'b00000000000000000000000000000000; + r_y__50 <= 32'b00000000000000000000000000000000; + r_z__50 <= 32'b00000000000000000000000000000000; + r_ux__50 <= 32'b00000000000000000000000000000000; + r_uy__50 <= 32'b00000000000000000000000000000000; + r_uz__50 <= 32'b00000000000000000000000000000000; + r_sz__50 <= 32'b00000000000000000000000000000000; + r_sr__50 <= 32'b00000000000000000000000000000000; + r_sleftz__50 <= 32'b00000000000000000000000000000000; + r_sleftr__50 <= 32'b00000000000000000000000000000000; + r_weight__50 <= 32'b00000000000000000000000000000000; + r_layer__50 <= 3'b000; + r_dead__50 <= 1'b1; + r_hit__50 <= 1'b0; + r_diff__50 <= 32'b00000000000000000000000000000000; + r_dl_b__50 <= 32'b00000000000000000000000000000000; + r_numer__50 <= 0; + r_z1__50 <= 32'b00000000000000000000000000000000; + r_z0__50 <= 32'b00000000000000000000000000000000; + r_mut__50 <= 32'b00000000000000000000000000000000; + + r_x__49 <= 32'b00000000000000000000000000000000; + r_y__49 <= 32'b00000000000000000000000000000000; + r_z__49 <= 32'b00000000000000000000000000000000; + r_ux__49 <= 32'b00000000000000000000000000000000; + r_uy__49 <= 32'b00000000000000000000000000000000; + r_uz__49 <= 32'b00000000000000000000000000000000; + r_sz__49 <= 32'b00000000000000000000000000000000; + r_sr__49 <= 32'b00000000000000000000000000000000; + r_sleftz__49 <= 32'b00000000000000000000000000000000; + r_sleftr__49 <= 32'b00000000000000000000000000000000; + r_weight__49 <= 32'b00000000000000000000000000000000; + r_layer__49 <= 3'b000; + r_dead__49 <= 1'b1; + r_hit__49 <= 1'b0; + r_diff__49 <= 32'b00000000000000000000000000000000; + r_dl_b__49 <= 32'b00000000000000000000000000000000; + r_numer__49 <= 0; + r_z1__49 <= 32'b00000000000000000000000000000000; + r_z0__49 <= 32'b00000000000000000000000000000000; + r_mut__49 <= 32'b00000000000000000000000000000000; + + r_x__48 <= 32'b00000000000000000000000000000000; + r_y__48 <= 32'b00000000000000000000000000000000; + r_z__48 <= 32'b00000000000000000000000000000000; + r_ux__48 <= 32'b00000000000000000000000000000000; + r_uy__48 <= 32'b00000000000000000000000000000000; + r_uz__48 <= 32'b00000000000000000000000000000000; + r_sz__48 <= 32'b00000000000000000000000000000000; + r_sr__48 <= 32'b00000000000000000000000000000000; + r_sleftz__48 <= 32'b00000000000000000000000000000000; + r_sleftr__48 <= 32'b00000000000000000000000000000000; + r_weight__48 <= 32'b00000000000000000000000000000000; + r_layer__48 <= 3'b000; + r_dead__48 <= 1'b1; + r_hit__48 <= 1'b0; + r_diff__48 <= 32'b00000000000000000000000000000000; + r_dl_b__48 <= 32'b00000000000000000000000000000000; + r_numer__48 <= 0; + r_z1__48 <= 32'b00000000000000000000000000000000; + r_z0__48 <= 32'b00000000000000000000000000000000; + r_mut__48 <= 32'b00000000000000000000000000000000; + + r_x__47 <= 32'b00000000000000000000000000000000; + r_y__47 <= 32'b00000000000000000000000000000000; + r_z__47 <= 32'b00000000000000000000000000000000; + r_ux__47 <= 32'b00000000000000000000000000000000; + r_uy__47 <= 32'b00000000000000000000000000000000; + r_uz__47 <= 32'b00000000000000000000000000000000; + r_sz__47 <= 32'b00000000000000000000000000000000; + r_sr__47 <= 32'b00000000000000000000000000000000; + r_sleftz__47 <= 32'b00000000000000000000000000000000; + r_sleftr__47 <= 32'b00000000000000000000000000000000; + r_weight__47 <= 32'b00000000000000000000000000000000; + r_layer__47 <= 3'b000; + r_dead__47 <= 1'b1; + r_hit__47 <= 1'b0; + r_diff__47 <= 32'b00000000000000000000000000000000; + r_dl_b__47 <= 32'b00000000000000000000000000000000; + r_numer__47 <= 0; + r_z1__47 <= 32'b00000000000000000000000000000000; + r_z0__47 <= 32'b00000000000000000000000000000000; + r_mut__47 <= 32'b00000000000000000000000000000000; + + r_x__46 <= 32'b00000000000000000000000000000000; + r_y__46 <= 32'b00000000000000000000000000000000; + r_z__46 <= 32'b00000000000000000000000000000000; + r_ux__46 <= 32'b00000000000000000000000000000000; + r_uy__46 <= 32'b00000000000000000000000000000000; + r_uz__46 <= 32'b00000000000000000000000000000000; + r_sz__46 <= 32'b00000000000000000000000000000000; + r_sr__46 <= 32'b00000000000000000000000000000000; + r_sleftz__46 <= 32'b00000000000000000000000000000000; + r_sleftr__46 <= 32'b00000000000000000000000000000000; + r_weight__46 <= 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32'b00000000000000000000000000000000; + r_uy__17 <= 32'b00000000000000000000000000000000; + r_uz__17 <= 32'b00000000000000000000000000000000; + r_sz__17 <= 32'b00000000000000000000000000000000; + r_sr__17 <= 32'b00000000000000000000000000000000; + r_sleftz__17 <= 32'b00000000000000000000000000000000; + r_sleftr__17 <= 32'b00000000000000000000000000000000; + r_weight__17 <= 32'b00000000000000000000000000000000; + r_layer__17 <= 3'b000; + r_dead__17 <= 1'b1; + r_hit__17 <= 1'b0; + r_diff__17 <= 32'b00000000000000000000000000000000; + r_dl_b__17 <= 32'b00000000000000000000000000000000; + r_numer__17 <= 0; + r_z1__17 <= 32'b00000000000000000000000000000000; + r_z0__17 <= 32'b00000000000000000000000000000000; + r_mut__17 <= 32'b00000000000000000000000000000000; + + r_x__16 <= 32'b00000000000000000000000000000000; + r_y__16 <= 32'b00000000000000000000000000000000; + r_z__16 <= 32'b00000000000000000000000000000000; + r_ux__16 <= 32'b00000000000000000000000000000000; + r_uy__16 <= 32'b00000000000000000000000000000000; + r_uz__16 <= 32'b00000000000000000000000000000000; + r_sz__16 <= 32'b00000000000000000000000000000000; + r_sr__16 <= 32'b00000000000000000000000000000000; + r_sleftz__16 <= 32'b00000000000000000000000000000000; + r_sleftr__16 <= 32'b00000000000000000000000000000000; + r_weight__16 <= 32'b00000000000000000000000000000000; + r_layer__16 <= 3'b000; + r_dead__16 <= 1'b1; + r_hit__16 <= 1'b0; + r_diff__16 <= 32'b00000000000000000000000000000000; + r_dl_b__16 <= 32'b00000000000000000000000000000000; + r_numer__16 <= 0; + r_z1__16 <= 32'b00000000000000000000000000000000; + r_z0__16 <= 32'b00000000000000000000000000000000; + r_mut__16 <= 32'b00000000000000000000000000000000; + + r_x__15 <= 32'b00000000000000000000000000000000; + r_y__15 <= 32'b00000000000000000000000000000000; + r_z__15 <= 32'b00000000000000000000000000000000; + r_ux__15 <= 32'b00000000000000000000000000000000; + r_uy__15 <= 32'b00000000000000000000000000000000; + r_uz__15 <= 32'b00000000000000000000000000000000; + r_sz__15 <= 32'b00000000000000000000000000000000; + r_sr__15 <= 32'b00000000000000000000000000000000; + r_sleftz__15 <= 32'b00000000000000000000000000000000; + r_sleftr__15 <= 32'b00000000000000000000000000000000; + r_weight__15 <= 32'b00000000000000000000000000000000; + r_layer__15 <= 3'b000; + r_dead__15 <= 1'b1; + r_hit__15 <= 1'b0; + r_diff__15 <= 32'b00000000000000000000000000000000; + r_dl_b__15 <= 32'b00000000000000000000000000000000; + r_numer__15 <= 0; + r_z1__15 <= 32'b00000000000000000000000000000000; + r_z0__15 <= 32'b00000000000000000000000000000000; + r_mut__15 <= 32'b00000000000000000000000000000000; + + r_x__14 <= 32'b00000000000000000000000000000000; + r_y__14 <= 32'b00000000000000000000000000000000; + r_z__14 <= 32'b00000000000000000000000000000000; + r_ux__14 <= 32'b00000000000000000000000000000000; + r_uy__14 <= 32'b00000000000000000000000000000000; + r_uz__14 <= 32'b00000000000000000000000000000000; + r_sz__14 <= 32'b00000000000000000000000000000000; + r_sr__14 <= 32'b00000000000000000000000000000000; + r_sleftz__14 <= 32'b00000000000000000000000000000000; + r_sleftr__14 <= 32'b00000000000000000000000000000000; + r_weight__14 <= 32'b00000000000000000000000000000000; + r_layer__14 <= 3'b000; + r_dead__14 <= 1'b1; + r_hit__14 <= 1'b0; + r_diff__14 <= 32'b00000000000000000000000000000000; + r_dl_b__14 <= 32'b00000000000000000000000000000000; + r_numer__14 <= 0; + r_z1__14 <= 32'b00000000000000000000000000000000; + r_z0__14 <= 32'b00000000000000000000000000000000; + r_mut__14 <= 32'b00000000000000000000000000000000; + + r_x__13 <= 32'b00000000000000000000000000000000; + r_y__13 <= 32'b00000000000000000000000000000000; + r_z__13 <= 32'b00000000000000000000000000000000; + r_ux__13 <= 32'b00000000000000000000000000000000; + r_uy__13 <= 32'b00000000000000000000000000000000; + r_uz__13 <= 32'b00000000000000000000000000000000; + r_sz__13 <= 32'b00000000000000000000000000000000; + r_sr__13 <= 32'b00000000000000000000000000000000; + r_sleftz__13 <= 32'b00000000000000000000000000000000; + r_sleftr__13 <= 32'b00000000000000000000000000000000; + r_weight__13 <= 32'b00000000000000000000000000000000; + r_layer__13 <= 3'b000; + r_dead__13 <= 1'b1; + r_hit__13 <= 1'b0; + r_diff__13 <= 32'b00000000000000000000000000000000; + r_dl_b__13 <= 32'b00000000000000000000000000000000; + r_numer__13 <= 0; + r_z1__13 <= 32'b00000000000000000000000000000000; + r_z0__13 <= 32'b00000000000000000000000000000000; + r_mut__13 <= 32'b00000000000000000000000000000000; + + r_x__12 <= 32'b00000000000000000000000000000000; + r_y__12 <= 32'b00000000000000000000000000000000; + r_z__12 <= 32'b00000000000000000000000000000000; + r_ux__12 <= 32'b00000000000000000000000000000000; + r_uy__12 <= 32'b00000000000000000000000000000000; + r_uz__12 <= 32'b00000000000000000000000000000000; + r_sz__12 <= 32'b00000000000000000000000000000000; + r_sr__12 <= 32'b00000000000000000000000000000000; + r_sleftz__12 <= 32'b00000000000000000000000000000000; + r_sleftr__12 <= 32'b00000000000000000000000000000000; + r_weight__12 <= 32'b00000000000000000000000000000000; + r_layer__12 <= 3'b000; + r_dead__12 <= 1'b1; + r_hit__12 <= 1'b0; + r_diff__12 <= 32'b00000000000000000000000000000000; + r_dl_b__12 <= 32'b00000000000000000000000000000000; + r_numer__12 <= 0; + r_z1__12 <= 32'b00000000000000000000000000000000; + r_z0__12 <= 32'b00000000000000000000000000000000; + r_mut__12 <= 32'b00000000000000000000000000000000; + + r_x__11 <= 32'b00000000000000000000000000000000; + r_y__11 <= 32'b00000000000000000000000000000000; + r_z__11 <= 32'b00000000000000000000000000000000; + r_ux__11 <= 32'b00000000000000000000000000000000; + r_uy__11 <= 32'b00000000000000000000000000000000; + r_uz__11 <= 32'b00000000000000000000000000000000; + r_sz__11 <= 32'b00000000000000000000000000000000; + r_sr__11 <= 32'b00000000000000000000000000000000; + r_sleftz__11 <= 32'b00000000000000000000000000000000; + r_sleftr__11 <= 32'b00000000000000000000000000000000; + r_weight__11 <= 32'b00000000000000000000000000000000; + r_layer__11 <= 3'b000; + r_dead__11 <= 1'b1; + r_hit__11 <= 1'b0; + r_diff__11 <= 32'b00000000000000000000000000000000; + r_dl_b__11 <= 32'b00000000000000000000000000000000; + r_numer__11 <= 0; + r_z1__11 <= 32'b00000000000000000000000000000000; + r_z0__11 <= 32'b00000000000000000000000000000000; + r_mut__11 <= 32'b00000000000000000000000000000000; + + r_x__10 <= 32'b00000000000000000000000000000000; + r_y__10 <= 32'b00000000000000000000000000000000; + r_z__10 <= 32'b00000000000000000000000000000000; + r_ux__10 <= 32'b00000000000000000000000000000000; + r_uy__10 <= 32'b00000000000000000000000000000000; + r_uz__10 <= 32'b00000000000000000000000000000000; + r_sz__10 <= 32'b00000000000000000000000000000000; + r_sr__10 <= 32'b00000000000000000000000000000000; + r_sleftz__10 <= 32'b00000000000000000000000000000000; + r_sleftr__10 <= 32'b00000000000000000000000000000000; + r_weight__10 <= 32'b00000000000000000000000000000000; + r_layer__10 <= 3'b000; + r_dead__10 <= 1'b1; + r_hit__10 <= 1'b0; + r_diff__10 <= 32'b00000000000000000000000000000000; + r_dl_b__10 <= 32'b00000000000000000000000000000000; + r_numer__10 <= 0; + r_z1__10 <= 32'b00000000000000000000000000000000; + r_z0__10 <= 32'b00000000000000000000000000000000; + r_mut__10 <= 32'b00000000000000000000000000000000; + + r_x__9 <= 32'b00000000000000000000000000000000; + r_y__9 <= 32'b00000000000000000000000000000000; + r_z__9 <= 32'b00000000000000000000000000000000; + r_ux__9 <= 32'b00000000000000000000000000000000; + r_uy__9 <= 32'b00000000000000000000000000000000; + r_uz__9 <= 32'b00000000000000000000000000000000; + r_sz__9 <= 32'b00000000000000000000000000000000; + r_sr__9 <= 32'b00000000000000000000000000000000; + r_sleftz__9 <= 32'b00000000000000000000000000000000; + r_sleftr__9 <= 32'b00000000000000000000000000000000; + r_weight__9 <= 32'b00000000000000000000000000000000; + r_layer__9 <= 3'b000; + r_dead__9 <= 1'b1; + r_hit__9 <= 1'b0; + r_diff__9 <= 32'b00000000000000000000000000000000; + r_dl_b__9 <= 32'b00000000000000000000000000000000; + r_numer__9 <= 0; + r_z1__9 <= 32'b00000000000000000000000000000000; + r_z0__9 <= 32'b00000000000000000000000000000000; + r_mut__9 <= 32'b00000000000000000000000000000000; + + r_x__8 <= 32'b00000000000000000000000000000000; + r_y__8 <= 32'b00000000000000000000000000000000; + r_z__8 <= 32'b00000000000000000000000000000000; + r_ux__8 <= 32'b00000000000000000000000000000000; + r_uy__8 <= 32'b00000000000000000000000000000000; + r_uz__8 <= 32'b00000000000000000000000000000000; + r_sz__8 <= 32'b00000000000000000000000000000000; + r_sr__8 <= 32'b00000000000000000000000000000000; + r_sleftz__8 <= 32'b00000000000000000000000000000000; + r_sleftr__8 <= 32'b00000000000000000000000000000000; + r_weight__8 <= 32'b00000000000000000000000000000000; + r_layer__8 <= 3'b000; + r_dead__8 <= 1'b1; + r_hit__8 <= 1'b0; + r_diff__8 <= 32'b00000000000000000000000000000000; + r_dl_b__8 <= 32'b00000000000000000000000000000000; + r_numer__8 <= 0; + r_z1__8 <= 32'b00000000000000000000000000000000; + r_z0__8 <= 32'b00000000000000000000000000000000; + r_mut__8 <= 32'b00000000000000000000000000000000; + + r_x__7 <= 32'b00000000000000000000000000000000; + r_y__7 <= 32'b00000000000000000000000000000000; + r_z__7 <= 32'b00000000000000000000000000000000; + r_ux__7 <= 32'b00000000000000000000000000000000; + r_uy__7 <= 32'b00000000000000000000000000000000; + r_uz__7 <= 32'b00000000000000000000000000000000; + r_sz__7 <= 32'b00000000000000000000000000000000; + r_sr__7 <= 32'b00000000000000000000000000000000; + r_sleftz__7 <= 32'b00000000000000000000000000000000; + r_sleftr__7 <= 32'b00000000000000000000000000000000; + r_weight__7 <= 32'b00000000000000000000000000000000; + r_layer__7 <= 3'b000; + r_dead__7 <= 1'b1; + r_hit__7 <= 1'b0; + r_diff__7 <= 32'b00000000000000000000000000000000; + r_dl_b__7 <= 32'b00000000000000000000000000000000; + r_numer__7 <= 0; + r_z1__7 <= 32'b00000000000000000000000000000000; + r_z0__7 <= 32'b00000000000000000000000000000000; + r_mut__7 <= 32'b00000000000000000000000000000000; + + r_x__6 <= 32'b00000000000000000000000000000000; + r_y__6 <= 32'b00000000000000000000000000000000; + r_z__6 <= 32'b00000000000000000000000000000000; + r_ux__6 <= 32'b00000000000000000000000000000000; + r_uy__6 <= 32'b00000000000000000000000000000000; + r_uz__6 <= 32'b00000000000000000000000000000000; + r_sz__6 <= 32'b00000000000000000000000000000000; + r_sr__6 <= 32'b00000000000000000000000000000000; + r_sleftz__6 <= 32'b00000000000000000000000000000000; + r_sleftr__6 <= 32'b00000000000000000000000000000000; + r_weight__6 <= 32'b00000000000000000000000000000000; + r_layer__6 <= 3'b000; + r_dead__6 <= 1'b1; + r_hit__6 <= 1'b0; + r_diff__6 <= 32'b00000000000000000000000000000000; + r_dl_b__6 <= 32'b00000000000000000000000000000000; + r_numer__6 <= 0; + r_z1__6 <= 32'b00000000000000000000000000000000; + r_z0__6 <= 32'b00000000000000000000000000000000; + r_mut__6 <= 32'b00000000000000000000000000000000; + + r_x__5 <= 32'b00000000000000000000000000000000; + r_y__5 <= 32'b00000000000000000000000000000000; + r_z__5 <= 32'b00000000000000000000000000000000; + r_ux__5 <= 32'b00000000000000000000000000000000; + r_uy__5 <= 32'b00000000000000000000000000000000; + r_uz__5 <= 32'b00000000000000000000000000000000; + r_sz__5 <= 32'b00000000000000000000000000000000; + r_sr__5 <= 32'b00000000000000000000000000000000; + r_sleftz__5 <= 32'b00000000000000000000000000000000; + r_sleftr__5 <= 32'b00000000000000000000000000000000; + r_weight__5 <= 32'b00000000000000000000000000000000; + r_layer__5 <= 3'b000; + r_dead__5 <= 1'b1; + r_hit__5 <= 1'b0; + r_diff__5 <= 32'b00000000000000000000000000000000; + r_dl_b__5 <= 32'b00000000000000000000000000000000; + r_numer__5 <= 0; + r_z1__5 <= 32'b00000000000000000000000000000000; + r_z0__5 <= 32'b00000000000000000000000000000000; + r_mut__5 <= 32'b00000000000000000000000000000000; + + r_x__4 <= 32'b00000000000000000000000000000000; + r_y__4 <= 32'b00000000000000000000000000000000; + r_z__4 <= 32'b00000000000000000000000000000000; + r_ux__4 <= 32'b00000000000000000000000000000000; + r_uy__4 <= 32'b00000000000000000000000000000000; + r_uz__4 <= 32'b00000000000000000000000000000000; + r_sz__4 <= 32'b00000000000000000000000000000000; + r_sr__4 <= 32'b00000000000000000000000000000000; + r_sleftz__4 <= 32'b00000000000000000000000000000000; + r_sleftr__4 <= 32'b00000000000000000000000000000000; + r_weight__4 <= 32'b00000000000000000000000000000000; + r_layer__4 <= 3'b000; + r_dead__4 <= 1'b1; + r_hit__4 <= 1'b0; + r_diff__4 <= 32'b00000000000000000000000000000000; + r_dl_b__4 <= 32'b00000000000000000000000000000000; + r_numer__4 <= 0; + r_z1__4 <= 32'b00000000000000000000000000000000; + r_z0__4 <= 32'b00000000000000000000000000000000; + r_mut__4 <= 32'b00000000000000000000000000000000; + + r_x__3 <= 32'b00000000000000000000000000000000; + r_y__3 <= 32'b00000000000000000000000000000000; + r_z__3 <= 32'b00000000000000000000000000000000; + r_ux__3 <= 32'b00000000000000000000000000000000; + r_uy__3 <= 32'b00000000000000000000000000000000; + r_uz__3 <= 32'b00000000000000000000000000000000; + r_sz__3 <= 32'b00000000000000000000000000000000; + r_sr__3 <= 32'b00000000000000000000000000000000; + r_sleftz__3 <= 32'b00000000000000000000000000000000; + r_sleftr__3 <= 32'b00000000000000000000000000000000; + r_weight__3 <= 32'b00000000000000000000000000000000; + r_layer__3 <= 3'b000; + r_dead__3 <= 1'b1; + r_hit__3 <= 1'b0; + r_diff__3 <= 32'b00000000000000000000000000000000; + r_dl_b__3 <= 32'b00000000000000000000000000000000; + r_numer__3 <= 0; + r_z1__3 <= 32'b00000000000000000000000000000000; + r_z0__3 <= 32'b00000000000000000000000000000000; + r_mut__3 <= 32'b00000000000000000000000000000000; + + r_x__2 <= 32'b00000000000000000000000000000000; + r_y__2 <= 32'b00000000000000000000000000000000; + r_z__2 <= 32'b00000000000000000000000000000000; + r_ux__2 <= 32'b00000000000000000000000000000000; + r_uy__2 <= 32'b00000000000000000000000000000000; + r_uz__2 <= 32'b00000000000000000000000000000000; + r_sz__2 <= 32'b00000000000000000000000000000000; + r_sr__2 <= 32'b00000000000000000000000000000000; + r_sleftz__2 <= 32'b00000000000000000000000000000000; + r_sleftr__2 <= 32'b00000000000000000000000000000000; + r_weight__2 <= 32'b00000000000000000000000000000000; + r_layer__2 <= 3'b000; + r_dead__2 <= 1'b1; + r_hit__2 <= 1'b0; + r_diff__2 <= 32'b00000000000000000000000000000000; + r_dl_b__2 <= 32'b00000000000000000000000000000000; + r_numer__2 <= 0; + r_z1__2 <= 32'b00000000000000000000000000000000; + r_z0__2 <= 32'b00000000000000000000000000000000; + r_mut__2 <= 32'b00000000000000000000000000000000; + + r_x__1 <= 32'b00000000000000000000000000000000; + r_y__1 <= 32'b00000000000000000000000000000000; + r_z__1 <= 32'b00000000000000000000000000000000; + r_ux__1 <= 32'b00000000000000000000000000000000; + r_uy__1 <= 32'b00000000000000000000000000000000; + r_uz__1 <= 32'b00000000000000000000000000000000; + r_sz__1 <= 32'b00000000000000000000000000000000; + r_sr__1 <= 32'b00000000000000000000000000000000; + r_sleftz__1 <= 32'b00000000000000000000000000000000; + r_sleftr__1 <= 32'b00000000000000000000000000000000; + r_weight__1 <= 32'b00000000000000000000000000000000; + r_layer__1 <= 3'b000; + r_dead__1 <= 1'b1; + r_hit__1 <= 1'b0; + r_diff__1 <= 32'b00000000000000000000000000000000; + r_dl_b__1 <= 32'b00000000000000000000000000000000; + r_numer__1 <= 0; + r_z1__1 <= 32'b00000000000000000000000000000000; + r_z0__1 <= 32'b00000000000000000000000000000000; + r_mut__1 <= 32'b00000000000000000000000000000000; + + r_x__0 <= 32'b00000000000000000000000000000000; + r_y__0 <= 32'b00000000000000000000000000000000; + r_z__0 <= 32'b00000000000000000000000000000000; + r_ux__0 <= 32'b00000000000000000000000000000000; + r_uy__0 <= 32'b00000000000000000000000000000000; + r_uz__0 <= 32'b00000000000000000000000000000000; + r_sz__0 <= 32'b00000000000000000000000000000000; + r_sr__0 <= 32'b00000000000000000000000000000000; + r_sleftz__0 <= 32'b00000000000000000000000000000000; + r_sleftr__0 <= 32'b00000000000000000000000000000000; + r_weight__0 <= 32'b00000000000000000000000000000000; + r_layer__0 <= 3'b000; + r_dead__0 <= 1'b0; + r_hit__0 <= 1'b0; + r_diff__0 <= 32'b00000000000000000000000000000000; + r_dl_b__0 <= 32'b00000000000000000000000000000000; + r_numer__0 <= 0; + r_z1__0 <= 32'b00000000000000000000000000000000; + r_z0__0 <= 32'b00000000000000000000000000000000; + r_mut__0 <= 32'b00000000000000000000000000000000; + end + + else + begin + if(enable) + begin + + //for 0 + r_x__0 <=c_x__0; + r_y__0 <=c_y__0; + r_z__0 <=c_z__0; + r_ux__0 <=c_ux__0; + r_uy__0 <=c_uy__0; + r_uz__0 <=c_uz__0; + r_sz__0 <=c_sz__0; + r_sr__0 <=c_sr__0; + r_sleftz__0 <=c_sleftz__0; + r_sleftr__0 <=c_sleftr__0; + r_weight__0 <=c_weight__0; + r_layer__0 <=c_layer__0; + r_dead__0 <=c_dead__0; + r_hit__0 <=c_hit__0; + r_diff__0 <=c_diff__0; + r_dl_b__0 <=c_dl_b__0; + r_numer__0 <=c_numer__0; + r_z1__0 <=c_z1__0; + r_z0__0 <=c_z0__0; + r_mut__0 <=c_mut__0; + + //for 1 + + r_x__1 <=c_x__1; + r_y__1 <=c_y__1; + r_z__1 <=c_z__1; + r_ux__1 <=c_ux__1; + r_uy__1 <=c_uy__1; + r_uz__1 <=c_uz__1; + r_sz__1 <=c_sz__1; + r_sr__1 <=c_sr__1; + r_sleftz__1 <=c_sleftz__1; + r_sleftr__1 <=c_sleftr__1; + r_weight__1 <=c_weight__1; + r_layer__1 <=c_layer__1; + r_dead__1 <=c_dead__1; + r_hit__1 <=c_hit__1; + r_diff__1 <=c_diff__1; + r_dl_b__1 <=c_dl_b__1; + r_numer__1 <=c_numer__1; + r_z1__1 <=c_z1__1; + r_z0__1 <=c_z0__1; + r_mut__1 <=c_mut__1; + + //for 2 + r_x__2 <=c_x__2; + r_y__2 <=c_y__2; + r_z__2 <=c_z__2; + r_ux__2 <=c_ux__2; + r_uy__2 <=c_uy__2; + r_uz__2 <=c_uz__2; + r_sz__2 <=c_sz__2; + r_sr__2 <=c_sr__2; + r_sleftz__2 <=c_sleftz__2; + r_sleftr__2 <=c_sleftr__2; + r_weight__2 <=c_weight__2; + r_layer__2 <=c_layer__2; + r_dead__2 <=c_dead__2; + r_hit__2 <=c_hit__2; + r_diff__2 <=c_diff__2; + r_dl_b__2 <=c_dl_b__2; + r_numer__2 <=c_numer__2; + r_z1__2 <=c_z1__2; + r_z0__2 <=c_z0__2; + r_mut__2 <=c_mut__2; + + //for 3 + r_x__3 <=c_x__3; + r_y__3 <=c_y__3; + r_z__3 <=c_z__3; + r_ux__3 <=c_ux__3; + r_uy__3 <=c_uy__3; + r_uz__3 <=c_uz__3; + r_sz__3 <=c_sz__3; + r_sr__3 <=c_sr__3; + r_sleftz__3 <=c_sleftz__3; + r_sleftr__3 <=c_sleftr__3; + r_weight__3 <=c_weight__3; + r_layer__3 <=c_layer__3; + r_dead__3 <=c_dead__3; + r_hit__3 <=c_hit__3; + r_diff__3 <=c_diff__3; + r_dl_b__3 <=c_dl_b__3; + r_numer__3 <=c_numer__3; + r_z1__3 <=c_z1__3; + r_z0__3 <=c_z0__3; + r_mut__3 <=c_mut__3; + + //for 4 + r_x__4 <=c_x__4; + r_y__4 <=c_y__4; + r_z__4 <=c_z__4; + r_ux__4 <=c_ux__4; + r_uy__4 <=c_uy__4; + r_uz__4 <=c_uz__4; + r_sz__4 <=c_sz__4; + r_sr__4 <=c_sr__4; + r_sleftz__4 <=c_sleftz__4; + r_sleftr__4 <=c_sleftr__4; + r_weight__4 <=c_weight__4; + r_layer__4 <=c_layer__4; + r_dead__4 <=c_dead__4; + r_hit__4 <=c_hit__4; + r_diff__4 <=c_diff__4; + r_dl_b__4 <=c_dl_b__4; + r_numer__4 <=c_numer__4; + r_z1__4 <=c_z1__4; + r_z0__4 <=c_z0__4; + r_mut__4 <=c_mut__4; + + //for 5 + r_x__5 <=c_x__5; + r_y__5 <=c_y__5; + r_z__5 <=c_z__5; + r_ux__5 <=c_ux__5; + r_uy__5 <=c_uy__5; + r_uz__5 <=c_uz__5; + r_sz__5 <=c_sz__5; + r_sr__5 <=c_sr__5; + r_sleftz__5 <=c_sleftz__5; + r_sleftr__5 <=c_sleftr__5; + r_weight__5 <=c_weight__5; + r_layer__5 <=c_layer__5; + r_dead__5 <=c_dead__5; + r_hit__5 <=c_hit__5; + r_diff__5 <=c_diff__5; + r_dl_b__5 <=c_dl_b__5; + r_numer__5 <=c_numer__5; + r_z1__5 <=c_z1__5; + r_z0__5 <=c_z0__5; + r_mut__5 <=c_mut__5; + + //for 6 + r_x__6 <=c_x__6; + r_y__6 <=c_y__6; + r_z__6 <=c_z__6; + r_ux__6 <=c_ux__6; + r_uy__6 <=c_uy__6; + r_uz__6 <=c_uz__6; + r_sz__6 <=c_sz__6; + r_sr__6 <=c_sr__6; + r_sleftz__6 <=c_sleftz__6; + r_sleftr__6 <=c_sleftr__6; + r_weight__6 <=c_weight__6; + r_layer__6 <=c_layer__6; + r_dead__6 <=c_dead__6; + r_hit__6 <=c_hit__6; + r_diff__6 <=c_diff__6; + r_dl_b__6 <=c_dl_b__6; + r_numer__6 <=c_numer__6; + r_z1__6 <=c_z1__6; + r_z0__6 <=c_z0__6; + r_mut__6 <=c_mut__6; + + //for 7 + r_x__7 <=c_x__7; + r_y__7 <=c_y__7; + r_z__7 <=c_z__7; + r_ux__7 <=c_ux__7; + r_uy__7 <=c_uy__7; + r_uz__7 <=c_uz__7; + r_sz__7 <=c_sz__7; + r_sr__7 <=c_sr__7; + r_sleftz__7 <=c_sleftz__7; + r_sleftr__7 <=c_sleftr__7; + r_weight__7 <=c_weight__7; + r_layer__7 <=c_layer__7; + r_dead__7 <=c_dead__7; + r_hit__7 <=c_hit__7; + r_diff__7 <=c_diff__7; + r_dl_b__7 <=c_dl_b__7; + r_numer__7 <=c_numer__7; + r_z1__7 <=c_z1__7; + r_z0__7 <=c_z0__7; + r_mut__7 <=c_mut__7; + + //for 8 + r_x__8 <=c_x__8; + r_y__8 <=c_y__8; + r_z__8 <=c_z__8; + r_ux__8 <=c_ux__8; + r_uy__8 <=c_uy__8; + r_uz__8 <=c_uz__8; + r_sz__8 <=c_sz__8; + r_sr__8 <=c_sr__8; + r_sleftz__8 <=c_sleftz__8; + r_sleftr__8 <=c_sleftr__8; + r_weight__8 <=c_weight__8; + r_layer__8 <=c_layer__8; + r_dead__8 <=c_dead__8; + r_hit__8 <=c_hit__8; + r_diff__8 <=c_diff__8; + r_dl_b__8 <=c_dl_b__8; + r_numer__8 <=c_numer__8; + r_z1__8 <=c_z1__8; + r_z0__8 <=c_z0__8; + r_mut__8 <=c_mut__8; + + //for 9 + r_x__9 <=c_x__9; + r_y__9 <=c_y__9; + r_z__9 <=c_z__9; + r_ux__9 <=c_ux__9; + r_uy__9 <=c_uy__9; + r_uz__9 <=c_uz__9; + r_sz__9 <=c_sz__9; + r_sr__9 <=c_sr__9; + r_sleftz__9 <=c_sleftz__9; + r_sleftr__9 <=c_sleftr__9; + r_weight__9 <=c_weight__9; + r_layer__9 <=c_layer__9; + r_dead__9 <=c_dead__9; + r_hit__9 <=c_hit__9; + r_diff__9 <=c_diff__9; + r_dl_b__9 <=c_dl_b__9; + r_numer__9 <=c_numer__9; + r_z1__9 <=c_z1__9; + r_z0__9 <=c_z0__9; + r_mut__9 <=c_mut__9; + + //for 10 + r_x__10 <=c_x__10; + r_y__10 <=c_y__10; + r_z__10 <=c_z__10; + r_ux__10 <=c_ux__10; + r_uy__10 <=c_uy__10; + r_uz__10 <=c_uz__10; + r_sz__10 <=c_sz__10; + r_sr__10 <=c_sr__10; + r_sleftz__10 <=c_sleftz__10; + r_sleftr__10 <=c_sleftr__10; + r_weight__10 <=c_weight__10; + r_layer__10 <=c_layer__10; + r_dead__10 <=c_dead__10; + r_hit__10 <=c_hit__10; + r_diff__10 <=c_diff__10; + r_dl_b__10 <=c_dl_b__10; + r_numer__10 <=c_numer__10; + r_z1__10 <=c_z1__10; + r_z0__10 <=c_z0__10; + r_mut__10 <=c_mut__10; + + //for 11 + r_x__11 <=c_x__11; + r_y__11 <=c_y__11; + r_z__11 <=c_z__11; + r_ux__11 <=c_ux__11; + r_uy__11 <=c_uy__11; + r_uz__11 <=c_uz__11; + r_sz__11 <=c_sz__11; + r_sr__11 <=c_sr__11; + r_sleftz__11 <=c_sleftz__11; + r_sleftr__11 <=c_sleftr__11; + r_weight__11 <=c_weight__11; + r_layer__11 <=c_layer__11; + r_dead__11 <=c_dead__11; + r_hit__11 <=c_hit__11; + r_diff__11 <=c_diff__11; + r_dl_b__11 <=c_dl_b__11; + r_numer__11 <=c_numer__11; + r_z1__11 <=c_z1__11; + r_z0__11 <=c_z0__11; + r_mut__11 <=c_mut__11; + + //for 12 + r_x__12 <=c_x__12; + r_y__12 <=c_y__12; + r_z__12 <=c_z__12; + r_ux__12 <=c_ux__12; + r_uy__12 <=c_uy__12; + r_uz__12 <=c_uz__12; + r_sz__12 <=c_sz__12; + r_sr__12 <=c_sr__12; + r_sleftz__12 <=c_sleftz__12; + r_sleftr__12 <=c_sleftr__12; + r_weight__12 <=c_weight__12; + r_layer__12 <=c_layer__12; + r_dead__12 <=c_dead__12; + r_hit__12 <=c_hit__12; + r_diff__12 <=c_diff__12; + r_dl_b__12 <=c_dl_b__12; + r_numer__12 <=c_numer__12; + r_z1__12 <=c_z1__12; + r_z0__12 <=c_z0__12; + r_mut__12 <=c_mut__12; + + //for 13 + r_x__13 <=c_x__13; + r_y__13 <=c_y__13; + r_z__13 <=c_z__13; + r_ux__13 <=c_ux__13; + r_uy__13 <=c_uy__13; + r_uz__13 <=c_uz__13; + r_sz__13 <=c_sz__13; + r_sr__13 <=c_sr__13; + r_sleftz__13 <=c_sleftz__13; + r_sleftr__13 <=c_sleftr__13; + r_weight__13 <=c_weight__13; + r_layer__13 <=c_layer__13; + r_dead__13 <=c_dead__13; + r_hit__13 <=c_hit__13; + r_diff__13 <=c_diff__13; + r_dl_b__13 <=c_dl_b__13; + r_numer__13 <=c_numer__13; + r_z1__13 <=c_z1__13; + r_z0__13 <=c_z0__13; + r_mut__13 <=c_mut__13; + + //for 14 + r_x__14 <=c_x__14; + r_y__14 <=c_y__14; + r_z__14 <=c_z__14; + r_ux__14 <=c_ux__14; + r_uy__14 <=c_uy__14; + r_uz__14 <=c_uz__14; + r_sz__14 <=c_sz__14; + r_sr__14 <=c_sr__14; + r_sleftz__14 <=c_sleftz__14; + r_sleftr__14 <=c_sleftr__14; + r_weight__14 <=c_weight__14; + r_layer__14 <=c_layer__14; + r_dead__14 <=c_dead__14; + r_hit__14 <=c_hit__14; + r_diff__14 <=c_diff__14; + r_dl_b__14 <=c_dl_b__14; + r_numer__14 <=c_numer__14; + r_z1__14 <=c_z1__14; + r_z0__14 <=c_z0__14; + r_mut__14 <=c_mut__14; + + //for 15 + r_x__15 <=c_x__15; + r_y__15 <=c_y__15; + r_z__15 <=c_z__15; + r_ux__15 <=c_ux__15; + r_uy__15 <=c_uy__15; + r_uz__15 <=c_uz__15; + r_sz__15 <=c_sz__15; + r_sr__15 <=c_sr__15; + r_sleftz__15 <=c_sleftz__15; + r_sleftr__15 <=c_sleftr__15; + r_weight__15 <=c_weight__15; + r_layer__15 <=c_layer__15; + r_dead__15 <=c_dead__15; + r_hit__15 <=c_hit__15; + r_diff__15 <=c_diff__15; + r_dl_b__15 <=c_dl_b__15; + r_numer__15 <=c_numer__15; + r_z1__15 <=c_z1__15; + r_z0__15 <=c_z0__15; + r_mut__15 <=c_mut__15; + + //for 16 + r_x__16 <=c_x__16; + r_y__16 <=c_y__16; + r_z__16 <=c_z__16; + r_ux__16 <=c_ux__16; + r_uy__16 <=c_uy__16; + r_uz__16 <=c_uz__16; + r_sz__16 <=c_sz__16; + r_sr__16 <=c_sr__16; + r_sleftz__16 <=c_sleftz__16; + r_sleftr__16 <=c_sleftr__16; + r_weight__16 <=c_weight__16; + r_layer__16 <=c_layer__16; + r_dead__16 <=c_dead__16; + r_hit__16 <=c_hit__16; + r_diff__16 <=c_diff__16; + r_dl_b__16 <=c_dl_b__16; + r_numer__16 <=c_numer__16; + r_z1__16 <=c_z1__16; + r_z0__16 <=c_z0__16; + r_mut__16 <=c_mut__16; + + //for 17 + r_x__17 <=c_x__17; + r_y__17 <=c_y__17; + r_z__17 <=c_z__17; + r_ux__17 <=c_ux__17; + r_uy__17 <=c_uy__17; + r_uz__17 <=c_uz__17; + r_sz__17 <=c_sz__17; + r_sr__17 <=c_sr__17; + r_sleftz__17 <=c_sleftz__17; + r_sleftr__17 <=c_sleftr__17; + r_weight__17 <=c_weight__17; + r_layer__17 <=c_layer__17; + r_dead__17 <=c_dead__17; + r_hit__17 <=c_hit__17; + r_diff__17 <=c_diff__17; + r_dl_b__17 <=c_dl_b__17; + r_numer__17 <=c_numer__17; + r_z1__17 <=c_z1__17; + r_z0__17 <=c_z0__17; + r_mut__17 <=c_mut__17; + + //for 18 + r_x__18 <=c_x__18; + r_y__18 <=c_y__18; + r_z__18 <=c_z__18; + r_ux__18 <=c_ux__18; + r_uy__18 <=c_uy__18; + r_uz__18 <=c_uz__18; + r_sz__18 <=c_sz__18; + r_sr__18 <=c_sr__18; + r_sleftz__18 <=c_sleftz__18; + r_sleftr__18 <=c_sleftr__18; + r_weight__18 <=c_weight__18; + r_layer__18 <=c_layer__18; + r_dead__18 <=c_dead__18; + r_hit__18 <=c_hit__18; + r_diff__18 <=c_diff__18; + r_dl_b__18 <=c_dl_b__18; + r_numer__18 <=c_numer__18; + r_z1__18 <=c_z1__18; + r_z0__18 <=c_z0__18; + r_mut__18 <=c_mut__18; + + //for 19 + r_x__19 <=c_x__19; + r_y__19 <=c_y__19; + r_z__19 <=c_z__19; + r_ux__19 <=c_ux__19; + r_uy__19 <=c_uy__19; + r_uz__19 <=c_uz__19; + r_sz__19 <=c_sz__19; + r_sr__19 <=c_sr__19; + r_sleftz__19 <=c_sleftz__19; + r_sleftr__19 <=c_sleftr__19; + r_weight__19 <=c_weight__19; + r_layer__19 <=c_layer__19; + r_dead__19 <=c_dead__19; + r_hit__19 <=c_hit__19; + r_diff__19 <=c_diff__19; + r_dl_b__19 <=c_dl_b__19; + r_numer__19 <=c_numer__19; + r_z1__19 <=c_z1__19; + r_z0__19 <=c_z0__19; + r_mut__19 <=c_mut__19; + + //for 20 + r_x__20 <=c_x__20; + r_y__20 <=c_y__20; + r_z__20 <=c_z__20; + r_ux__20 <=c_ux__20; + r_uy__20 <=c_uy__20; + r_uz__20 <=c_uz__20; + r_sz__20 <=c_sz__20; + r_sr__20 <=c_sr__20; + r_sleftz__20 <=c_sleftz__20; + r_sleftr__20 <=c_sleftr__20; + r_weight__20 <=c_weight__20; + r_layer__20 <=c_layer__20; + r_dead__20 <=c_dead__20; + r_hit__20 <=c_hit__20; + r_diff__20 <=c_diff__20; + r_dl_b__20 <=c_dl_b__20; + r_numer__20 <=c_numer__20; + r_z1__20 <=c_z1__20; + r_z0__20 <=c_z0__20; + r_mut__20 <=c_mut__20; + + + //for 21 + r_x__21 <=c_x__21; + r_y__21 <=c_y__21; + r_z__21 <=c_z__21; + r_ux__21 <=c_ux__21; + r_uy__21 <=c_uy__21; + r_uz__21 <=c_uz__21; + r_sz__21 <=c_sz__21; + r_sr__21 <=c_sr__21; + r_sleftz__21 <=c_sleftz__21; + r_sleftr__21 <=c_sleftr__21; + r_weight__21 <=c_weight__21; + r_layer__21 <=c_layer__21; + r_dead__21 <=c_dead__21; + r_hit__21 <=c_hit__21; + r_diff__21 <=c_diff__21; + r_dl_b__21 <=c_dl_b__21; + r_numer__21 <=c_numer__21; + r_z1__21 <=c_z1__21; + r_z0__21 <=c_z0__21; + r_mut__21 <=c_mut__21; + + //for 22 + r_x__22 <=c_x__22; + r_y__22 <=c_y__22; + r_z__22 <=c_z__22; + r_ux__22 <=c_ux__22; + r_uy__22 <=c_uy__22; + r_uz__22 <=c_uz__22; + r_sz__22 <=c_sz__22; + r_sr__22 <=c_sr__22; + r_sleftz__22 <=c_sleftz__22; + r_sleftr__22 <=c_sleftr__22; + r_weight__22 <=c_weight__22; + r_layer__22 <=c_layer__22; + r_dead__22 <=c_dead__22; + r_hit__22 <=c_hit__22; + r_diff__22 <=c_diff__22; + r_dl_b__22 <=c_dl_b__22; + r_numer__22 <=c_numer__22; + r_z1__22 <=c_z1__22; + r_z0__22 <=c_z0__22; + r_mut__22 <=c_mut__22; + + //for 23 + r_x__23 <=c_x__23; + r_y__23 <=c_y__23; + r_z__23 <=c_z__23; + r_ux__23 <=c_ux__23; + r_uy__23 <=c_uy__23; + r_uz__23 <=c_uz__23; + r_sz__23 <=c_sz__23; + r_sr__23 <=c_sr__23; + r_sleftz__23 <=c_sleftz__23; + r_sleftr__23 <=c_sleftr__23; + r_weight__23 <=c_weight__23; + r_layer__23 <=c_layer__23; + r_dead__23 <=c_dead__23; + r_hit__23 <=c_hit__23; + r_diff__23 <=c_diff__23; + r_dl_b__23 <=c_dl_b__23; + r_numer__23 <=c_numer__23; + r_z1__23 <=c_z1__23; + r_z0__23 <=c_z0__23; + r_mut__23 <=c_mut__23; + + //for 24 + r_x__24 <=c_x__24; + r_y__24 <=c_y__24; + r_z__24 <=c_z__24; + r_ux__24 <=c_ux__24; + r_uy__24 <=c_uy__24; + r_uz__24 <=c_uz__24; + r_sz__24 <=c_sz__24; + r_sr__24 <=c_sr__24; + r_sleftz__24 <=c_sleftz__24; + r_sleftr__24 <=c_sleftr__24; + r_weight__24 <=c_weight__24; + r_layer__24 <=c_layer__24; + r_dead__24 <=c_dead__24; + r_hit__24 <=c_hit__24; + r_diff__24 <=c_diff__24; + r_dl_b__24 <=c_dl_b__24; + r_numer__24 <=c_numer__24; + r_z1__24 <=c_z1__24; + r_z0__24 <=c_z0__24; + r_mut__24 <=c_mut__24; + + //for 25 + r_x__25 <=c_x__25; + r_y__25 <=c_y__25; + r_z__25 <=c_z__25; + r_ux__25 <=c_ux__25; + r_uy__25 <=c_uy__25; + r_uz__25 <=c_uz__25; + r_sz__25 <=c_sz__25; + r_sr__25 <=c_sr__25; + r_sleftz__25 <=c_sleftz__25; + r_sleftr__25 <=c_sleftr__25; + r_weight__25 <=c_weight__25; + r_layer__25 <=c_layer__25; + r_dead__25 <=c_dead__25; + r_hit__25 <=c_hit__25; + r_diff__25 <=c_diff__25; + r_dl_b__25 <=c_dl_b__25; + r_numer__25 <=c_numer__25; + r_z1__25 <=c_z1__25; + r_z0__25 <=c_z0__25; + r_mut__25 <=c_mut__25; + + //for 26 + r_x__26 <=c_x__26; + r_y__26 <=c_y__26; + r_z__26 <=c_z__26; + r_ux__26 <=c_ux__26; + r_uy__26 <=c_uy__26; + r_uz__26 <=c_uz__26; + r_sz__26 <=c_sz__26; + r_sr__26 <=c_sr__26; + r_sleftz__26 <=c_sleftz__26; + r_sleftr__26 <=c_sleftr__26; + r_weight__26 <=c_weight__26; + r_layer__26 <=c_layer__26; + r_dead__26 <=c_dead__26; + r_hit__26 <=c_hit__26; + r_diff__26 <=c_diff__26; + r_dl_b__26 <=c_dl_b__26; + r_numer__26 <=c_numer__26; + r_z1__26 <=c_z1__26; + r_z0__26 <=c_z0__26; + r_mut__26 <=c_mut__26; + + //for 27 + r_x__27 <=c_x__27; + r_y__27 <=c_y__27; + r_z__27 <=c_z__27; + r_ux__27 <=c_ux__27; + r_uy__27 <=c_uy__27; + r_uz__27 <=c_uz__27; + r_sz__27 <=c_sz__27; + r_sr__27 <=c_sr__27; + r_sleftz__27 <=c_sleftz__27; + r_sleftr__27 <=c_sleftr__27; + r_weight__27 <=c_weight__27; + r_layer__27 <=c_layer__27; + r_dead__27 <=c_dead__27; + r_hit__27 <=c_hit__27; + r_diff__27 <=c_diff__27; + r_dl_b__27 <=c_dl_b__27; + r_numer__27 <=c_numer__27; + r_z1__27 <=c_z1__27; + r_z0__27 <=c_z0__27; + r_mut__27 <=c_mut__27; + + //for 28 + r_x__28 <=c_x__28; + r_y__28 <=c_y__28; + r_z__28 <=c_z__28; + r_ux__28 <=c_ux__28; + r_uy__28 <=c_uy__28; + r_uz__28 <=c_uz__28; + r_sz__28 <=c_sz__28; + r_sr__28 <=c_sr__28; + r_sleftz__28 <=c_sleftz__28; + r_sleftr__28 <=c_sleftr__28; + r_weight__28 <=c_weight__28; + r_layer__28 <=c_layer__28; + r_dead__28 <=c_dead__28; + r_hit__28 <=c_hit__28; + r_diff__28 <=c_diff__28; + r_dl_b__28 <=c_dl_b__28; + r_numer__28 <=c_numer__28; + r_z1__28 <=c_z1__28; + r_z0__28 <=c_z0__28; + r_mut__28 <=c_mut__28; + + //for 29 + r_x__29 <=c_x__29; + r_y__29 <=c_y__29; + r_z__29 <=c_z__29; + r_ux__29 <=c_ux__29; + r_uy__29 <=c_uy__29; + r_uz__29 <=c_uz__29; + r_sz__29 <=c_sz__29; + r_sr__29 <=c_sr__29; + r_sleftz__29 <=c_sleftz__29; + r_sleftr__29 <=c_sleftr__29; + r_weight__29 <=c_weight__29; + r_layer__29 <=c_layer__29; + r_dead__29 <=c_dead__29; + r_hit__29 <=c_hit__29; + r_diff__29 <=c_diff__29; + r_dl_b__29 <=c_dl_b__29; + r_numer__29 <=c_numer__29; + r_z1__29 <=c_z1__29; + r_z0__29 <=c_z0__29; + r_mut__29 <=c_mut__29; + + //for 30 + r_x__30 <=c_x__30; + r_y__30 <=c_y__30; + r_z__30 <=c_z__30; + r_ux__30 <=c_ux__30; + r_uy__30 <=c_uy__30; + r_uz__30 <=c_uz__30; + r_sz__30 <=c_sz__30; + r_sr__30 <=c_sr__30; + r_sleftz__30 <=c_sleftz__30; + r_sleftr__30 <=c_sleftr__30; + r_weight__30 <=c_weight__30; + r_layer__30 <=c_layer__30; + r_dead__30 <=c_dead__30; + r_hit__30 <=c_hit__30; + r_diff__30 <=c_diff__30; + r_dl_b__30 <=c_dl_b__30; + r_numer__30 <=c_numer__30; + r_z1__30 <=c_z1__30; + r_z0__30 <=c_z0__30; + r_mut__30 <=c_mut__30; + + //for 31 + r_x__31 <=c_x__31; + r_y__31 <=c_y__31; + r_z__31 <=c_z__31; + r_ux__31 <=c_ux__31; + r_uy__31 <=c_uy__31; + r_uz__31 <=c_uz__31; + r_sz__31 <=c_sz__31; + r_sr__31 <=c_sr__31; + r_sleftz__31 <=c_sleftz__31; + r_sleftr__31 <=c_sleftr__31; + r_weight__31 <=c_weight__31; + r_layer__31 <=c_layer__31; + r_dead__31 <=c_dead__31; + r_hit__31 <=c_hit__31; + r_diff__31 <=c_diff__31; + r_dl_b__31 <=c_dl_b__31; + r_numer__31 <=c_numer__31; + r_z1__31 <=c_z1__31; + r_z0__31 <=c_z0__31; + r_mut__31 <=c_mut__31; + + //for 32 + r_x__32 <=c_x__32; + r_y__32 <=c_y__32; + r_z__32 <=c_z__32; + r_ux__32 <=c_ux__32; + r_uy__32 <=c_uy__32; + r_uz__32 <=c_uz__32; + r_sz__32 <=c_sz__32; + r_sr__32 <=c_sr__32; + r_sleftz__32 <=c_sleftz__32; + r_sleftr__32 <=c_sleftr__32; + r_weight__32 <=c_weight__32; + r_layer__32 <=c_layer__32; + r_dead__32 <=c_dead__32; + r_hit__32 <=c_hit__32; + r_diff__32 <=c_diff__32; + r_dl_b__32 <=c_dl_b__32; + r_numer__32 <=c_numer__32; + r_z1__32 <=c_z1__32; + r_z0__32 <=c_z0__32; + r_mut__32 <=c_mut__32; + + //for 33 + r_x__33 <=c_x__33; + r_y__33 <=c_y__33; + r_z__33 <=c_z__33; + r_ux__33 <=c_ux__33; + r_uy__33 <=c_uy__33; + r_uz__33 <=c_uz__33; + r_sz__33 <=c_sz__33; + r_sr__33 <=c_sr__33; + r_sleftz__33 <=c_sleftz__33; + r_sleftr__33 <=c_sleftr__33; + r_weight__33 <=c_weight__33; + r_layer__33 <=c_layer__33; + r_dead__33 <=c_dead__33; + r_hit__33 <=c_hit__33; + r_diff__33 <=c_diff__33; + r_dl_b__33 <=c_dl_b__33; + r_numer__33 <=c_numer__33; + r_z1__33 <=c_z1__33; + r_z0__33 <=c_z0__33; + r_mut__33 <=c_mut__33; + + //for 34 + r_x__34 <=c_x__34; + r_y__34 <=c_y__34; + r_z__34 <=c_z__34; + r_ux__34 <=c_ux__34; + r_uy__34 <=c_uy__34; + r_uz__34 <=c_uz__34; + r_sz__34 <=c_sz__34; + r_sr__34 <=c_sr__34; + r_sleftz__34 <=c_sleftz__34; + r_sleftr__34 <=c_sleftr__34; + r_weight__34 <=c_weight__34; + r_layer__34 <=c_layer__34; + r_dead__34 <=c_dead__34; + r_hit__34 <=c_hit__34; + r_diff__34 <=c_diff__34; + r_dl_b__34 <=c_dl_b__34; + r_numer__34 <=c_numer__34; + r_z1__34 <=c_z1__34; + r_z0__34 <=c_z0__34; + r_mut__34 <=c_mut__34; + + //for 35 + r_x__35 <=c_x__35; + r_y__35 <=c_y__35; + r_z__35 <=c_z__35; + r_ux__35 <=c_ux__35; + r_uy__35 <=c_uy__35; + r_uz__35 <=c_uz__35; + r_sz__35 <=c_sz__35; + r_sr__35 <=c_sr__35; + r_sleftz__35 <=c_sleftz__35; + r_sleftr__35 <=c_sleftr__35; + r_weight__35 <=c_weight__35; + r_layer__35 <=c_layer__35; + r_dead__35 <=c_dead__35; + r_hit__35 <=c_hit__35; + r_diff__35 <=c_diff__35; + r_dl_b__35 <=c_dl_b__35; + r_numer__35 <=c_numer__35; + r_z1__35 <=c_z1__35; + r_z0__35 <=c_z0__35; + r_mut__35 <=c_mut__35; + + //for 36 + r_x__36 <=c_x__36; + r_y__36 <=c_y__36; + r_z__36 <=c_z__36; + r_ux__36 <=c_ux__36; + r_uy__36 <=c_uy__36; + r_uz__36 <=c_uz__36; + r_sz__36 <=c_sz__36; + r_sr__36 <=c_sr__36; + r_sleftz__36 <=c_sleftz__36; + r_sleftr__36 <=c_sleftr__36; + r_weight__36 <=c_weight__36; + r_layer__36 <=c_layer__36; + r_dead__36 <=c_dead__36; + r_hit__36 <=c_hit__36; + r_diff__36 <=c_diff__36; + r_dl_b__36 <=c_dl_b__36; + r_numer__36 <=c_numer__36; + r_z1__36 <=c_z1__36; + r_z0__36 <=c_z0__36; + r_mut__36 <=c_mut__36; + + //for 37 + r_x__37 <=c_x__37; + r_y__37 <=c_y__37; + r_z__37 <=c_z__37; + r_ux__37 <=c_ux__37; + r_uy__37 <=c_uy__37; + r_uz__37 <=c_uz__37; + r_sz__37 <=c_sz__37; + r_sr__37 <=c_sr__37; + r_sleftz__37 <=c_sleftz__37; + r_sleftr__37 <=c_sleftr__37; + r_weight__37 <=c_weight__37; + r_layer__37 <=c_layer__37; + r_dead__37 <=c_dead__37; + r_hit__37 <=c_hit__37; + r_diff__37 <=c_diff__37; + r_dl_b__37 <=c_dl_b__37; + r_numer__37 <=c_numer__37; + r_z1__37 <=c_z1__37; + r_z0__37 <=c_z0__37; + r_mut__37 <=c_mut__37; + + //for 38 + r_x__38 <=c_x__38; + r_y__38 <=c_y__38; + r_z__38 <=c_z__38; + r_ux__38 <=c_ux__38; + r_uy__38 <=c_uy__38; + r_uz__38 <=c_uz__38; + r_sz__38 <=c_sz__38; + r_sr__38 <=c_sr__38; + r_sleftz__38 <=c_sleftz__38; + r_sleftr__38 <=c_sleftr__38; + r_weight__38 <=c_weight__38; + r_layer__38 <=c_layer__38; + r_dead__38 <=c_dead__38; + r_hit__38 <=c_hit__38; + r_diff__38 <=c_diff__38; + r_dl_b__38 <=c_dl_b__38; + r_numer__38 <=c_numer__38; + r_z1__38 <=c_z1__38; + r_z0__38 <=c_z0__38; + r_mut__38 <=c_mut__38; + + //for 39 + r_x__39 <=c_x__39; + r_y__39 <=c_y__39; + r_z__39 <=c_z__39; + r_ux__39 <=c_ux__39; + r_uy__39 <=c_uy__39; + r_uz__39 <=c_uz__39; + r_sz__39 <=c_sz__39; + r_sr__39 <=c_sr__39; + r_sleftz__39 <=c_sleftz__39; + r_sleftr__39 <=c_sleftr__39; + r_weight__39 <=c_weight__39; + r_layer__39 <=c_layer__39; + r_dead__39 <=c_dead__39; + r_hit__39 <=c_hit__39; + r_diff__39 <=c_diff__39; + r_dl_b__39 <=c_dl_b__39; + r_numer__39 <=c_numer__39; + r_z1__39 <=c_z1__39; + r_z0__39 <=c_z0__39; + r_mut__39 <=c_mut__39; + + //for 40 + r_x__40 <=c_x__40; + r_y__40 <=c_y__40; + r_z__40 <=c_z__40; + r_ux__40 <=c_ux__40; + r_uy__40 <=c_uy__40; + r_uz__40 <=c_uz__40; + r_sz__40 <=c_sz__40; + r_sr__40 <=c_sr__40; + r_sleftz__40 <=c_sleftz__40; + r_sleftr__40 <=c_sleftr__40; + r_weight__40 <=c_weight__40; + r_layer__40 <=c_layer__40; + r_dead__40 <=c_dead__40; + r_hit__40 <=c_hit__40; + r_diff__40 <=c_diff__40; + r_dl_b__40 <=c_dl_b__40; + r_numer__40 <=c_numer__40; + r_z1__40 <=c_z1__40; + r_z0__40 <=c_z0__40; + r_mut__40 <=c_mut__40; + + //for 41 + r_x__41 <=c_x__41; + r_y__41 <=c_y__41; + r_z__41 <=c_z__41; + r_ux__41 <=c_ux__41; + r_uy__41 <=c_uy__41; + r_uz__41 <=c_uz__41; + r_sz__41 <=c_sz__41; + r_sr__41 <=c_sr__41; + r_sleftz__41 <=c_sleftz__41; + r_sleftr__41 <=c_sleftr__41; + r_weight__41 <=c_weight__41; + r_layer__41 <=c_layer__41; + r_dead__41 <=c_dead__41; + r_hit__41 <=c_hit__41; + r_diff__41 <=c_diff__41; + r_dl_b__41 <=c_dl_b__41; + r_numer__41 <=c_numer__41; + r_z1__41 <=c_z1__41; + r_z0__41 <=c_z0__41; + r_mut__41 <=c_mut__41; + + //for 42 + r_x__42 <=c_x__42; + r_y__42 <=c_y__42; + r_z__42 <=c_z__42; + r_ux__42 <=c_ux__42; + r_uy__42 <=c_uy__42; + r_uz__42 <=c_uz__42; + r_sz__42 <=c_sz__42; + r_sr__42 <=c_sr__42; + r_sleftz__42 <=c_sleftz__42; + r_sleftr__42 <=c_sleftr__42; + r_weight__42 <=c_weight__42; + r_layer__42 <=c_layer__42; + r_dead__42 <=c_dead__42; + r_hit__42 <=c_hit__42; + r_diff__42 <=c_diff__42; + r_dl_b__42 <=c_dl_b__42; + r_numer__42 <=c_numer__42; + r_z1__42 <=c_z1__42; + r_z0__42 <=c_z0__42; + r_mut__42 <=c_mut__42; + + //for 43 + r_x__43 <=c_x__43; + r_y__43 <=c_y__43; + r_z__43 <=c_z__43; + r_ux__43 <=c_ux__43; + r_uy__43 <=c_uy__43; + r_uz__43 <=c_uz__43; + r_sz__43 <=c_sz__43; + r_sr__43 <=c_sr__43; + r_sleftz__43 <=c_sleftz__43; + r_sleftr__43 <=c_sleftr__43; + r_weight__43 <=c_weight__43; + r_layer__43 <=c_layer__43; + r_dead__43 <=c_dead__43; + r_hit__43 <=c_hit__43; + r_diff__43 <=c_diff__43; + r_dl_b__43 <=c_dl_b__43; + r_numer__43 <=c_numer__43; + r_z1__43 <=c_z1__43; + r_z0__43 <=c_z0__43; + r_mut__43 <=c_mut__43; + + //for 44 + r_x__44 <=c_x__44; + r_y__44 <=c_y__44; + r_z__44 <=c_z__44; + r_ux__44 <=c_ux__44; + r_uy__44 <=c_uy__44; + r_uz__44 <=c_uz__44; + r_sz__44 <=c_sz__44; + r_sr__44 <=c_sr__44; + r_sleftz__44 <=c_sleftz__44; + r_sleftr__44 <=c_sleftr__44; + r_weight__44 <=c_weight__44; + r_layer__44 <=c_layer__44; + r_dead__44 <=c_dead__44; + r_hit__44 <=c_hit__44; + r_diff__44 <=c_diff__44; + r_dl_b__44 <=c_dl_b__44; + r_numer__44 <=c_numer__44; + r_z1__44 <=c_z1__44; + r_z0__44 <=c_z0__44; + r_mut__44 <=c_mut__44; + + //for 45 + r_x__45 <=c_x__45; + r_y__45 <=c_y__45; + r_z__45 <=c_z__45; + r_ux__45 <=c_ux__45; + r_uy__45 <=c_uy__45; + r_uz__45 <=c_uz__45; + r_sz__45 <=c_sz__45; + r_sr__45 <=c_sr__45; + r_sleftz__45 <=c_sleftz__45; + r_sleftr__45 <=c_sleftr__45; + r_weight__45 <=c_weight__45; + r_layer__45 <=c_layer__45; + r_dead__45 <=c_dead__45; + r_hit__45 <=c_hit__45; + r_diff__45 <=c_diff__45; + r_dl_b__45 <=c_dl_b__45; + r_numer__45 <=c_numer__45; + r_z1__45 <=c_z1__45; + r_z0__45 <=c_z0__45; + r_mut__45 <=c_mut__45; + + //for 46 + r_x__46 <=c_x__46; + r_y__46 <=c_y__46; + r_z__46 <=c_z__46; + r_ux__46 <=c_ux__46; + r_uy__46 <=c_uy__46; + r_uz__46 <=c_uz__46; + r_sz__46 <=c_sz__46; + r_sr__46 <=c_sr__46; + r_sleftz__46 <=c_sleftz__46; + r_sleftr__46 <=c_sleftr__46; + r_weight__46 <=c_weight__46; + r_layer__46 <=c_layer__46; + r_dead__46 <=c_dead__46; + r_hit__46 <=c_hit__46; + r_diff__46 <=c_diff__46; + r_dl_b__46 <=c_dl_b__46; + r_numer__46 <=c_numer__46; + r_z1__46 <=c_z1__46; + r_z0__46 <=c_z0__46; + r_mut__46 <=c_mut__46; + + //for 47 + r_x__47 <=c_x__47; + r_y__47 <=c_y__47; + r_z__47 <=c_z__47; + r_ux__47 <=c_ux__47; + r_uy__47 <=c_uy__47; + r_uz__47 <=c_uz__47; + r_sz__47 <=c_sz__47; + r_sr__47 <=c_sr__47; + r_sleftz__47 <=c_sleftz__47; + r_sleftr__47 <=c_sleftr__47; + r_weight__47 <=c_weight__47; + r_layer__47 <=c_layer__47; + r_dead__47 <=c_dead__47; + r_hit__47 <=c_hit__47; + r_diff__47 <=c_diff__47; + r_dl_b__47 <=c_dl_b__47; + r_numer__47 <=c_numer__47; + r_z1__47 <=c_z1__47; + r_z0__47 <=c_z0__47; + r_mut__47 <=c_mut__47; + + //for 48 + r_x__48 <=c_x__48; + r_y__48 <=c_y__48; + r_z__48 <=c_z__48; + r_ux__48 <=c_ux__48; + r_uy__48 <=c_uy__48; + r_uz__48 <=c_uz__48; + r_sz__48 <=c_sz__48; + r_sr__48 <=c_sr__48; + r_sleftz__48 <=c_sleftz__48; + r_sleftr__48 <=c_sleftr__48; + r_weight__48 <=c_weight__48; + r_layer__48 <=c_layer__48; + r_dead__48 <=c_dead__48; + r_hit__48 <=c_hit__48; + r_diff__48 <=c_diff__48; + r_dl_b__48 <=c_dl_b__48; + r_numer__48 <=c_numer__48; + r_z1__48 <=c_z1__48; + r_z0__48 <=c_z0__48; + r_mut__48 <=c_mut__48; + + //for 49 + r_x__49 <=c_x__49; + r_y__49 <=c_y__49; + r_z__49 <=c_z__49; + r_ux__49 <=c_ux__49; + r_uy__49 <=c_uy__49; + r_uz__49 <=c_uz__49; + r_sz__49 <=c_sz__49; + r_sr__49 <=c_sr__49; + r_sleftz__49 <=c_sleftz__49; + r_sleftr__49 <=c_sleftr__49; + r_weight__49 <=c_weight__49; + r_layer__49 <=c_layer__49; + r_dead__49 <=c_dead__49; + r_hit__49 <=c_hit__49; + r_diff__49 <=c_diff__49; + r_dl_b__49 <=c_dl_b__49; + r_numer__49 <=c_numer__49; + r_z1__49 <=c_z1__49; + r_z0__49 <=c_z0__49; + r_mut__49 <=c_mut__49; + + //for 50 + r_x__50 <=c_x__50; + r_y__50 <=c_y__50; + r_z__50 <=c_z__50; + r_ux__50 <=c_ux__50; + r_uy__50 <=c_uy__50; + r_uz__50 <=c_uz__50; + r_sz__50 <=c_sz__50; + r_sr__50 <=c_sr__50; + r_sleftz__50 <=c_sleftz__50; + r_sleftr__50 <=c_sleftr__50; + r_weight__50 <=c_weight__50; + r_layer__50 <=c_layer__50; + r_dead__50 <=c_dead__50; + r_hit__50 <=c_hit__50; + r_diff__50 <=c_diff__50; + r_dl_b__50 <=c_dl_b__50; + r_numer__50 <=c_numer__50; + r_z1__50 <=c_z1__50; + r_z0__50 <=c_z0__50; + r_mut__50 <=c_mut__50; + + //for 51 + r_x__51 <=c_x__51; + r_y__51 <=c_y__51; + r_z__51 <=c_z__51; + r_ux__51 <=c_ux__51; + r_uy__51 <=c_uy__51; + r_uz__51 <=c_uz__51; + r_sz__51 <=c_sz__51; + r_sr__51 <=c_sr__51; + r_sleftz__51 <=c_sleftz__51; + r_sleftr__51 <=c_sleftr__51; + r_weight__51 <=c_weight__51; + r_layer__51 <=c_layer__51; + r_dead__51 <=c_dead__51; + r_hit__51 <=c_hit__51; + r_diff__51 <=c_diff__51; + r_dl_b__51 <=c_dl_b__51; + r_numer__51 <=c_numer__51; + r_z1__51 <=c_z1__51; + r_z0__51 <=c_z0__51; + r_mut__51 <=c_mut__51; + + //for 52 + r_x__52 <=c_x__52; + r_y__52 <=c_y__52; + r_z__52 <=c_z__52; + r_ux__52 <=c_ux__52; + r_uy__52 <=c_uy__52; + r_uz__52 <=c_uz__52; + r_sz__52 <=c_sz__52; + r_sr__52 <=c_sr__52; + r_sleftz__52 <=c_sleftz__52; + r_sleftr__52 <=c_sleftr__52; + r_weight__52 <=c_weight__52; + r_layer__52 <=c_layer__52; + r_dead__52 <=c_dead__52; + r_hit__52 <=c_hit__52; + r_diff__52 <=c_diff__52; + r_dl_b__52 <=c_dl_b__52; + r_numer__52 <=c_numer__52; + r_z1__52 <=c_z1__52; + r_z0__52 <=c_z0__52; + r_mut__52 <=c_mut__52; + + //for 53 + r_x__53 <=c_x__53; + r_y__53 <=c_y__53; + r_z__53 <=c_z__53; + r_ux__53 <=c_ux__53; + r_uy__53 <=c_uy__53; + r_uz__53 <=c_uz__53; + r_sz__53 <=c_sz__53; + r_sr__53 <=c_sr__53; + r_sleftz__53 <=c_sleftz__53; + r_sleftr__53 <=c_sleftr__53; + r_weight__53 <=c_weight__53; + r_layer__53 <=c_layer__53; + r_dead__53 <=c_dead__53; + r_hit__53 <=c_hit__53; + r_diff__53 <=c_diff__53; + r_dl_b__53 <=c_dl_b__53; + r_numer__53 <=c_numer__53; + r_z1__53 <=c_z1__53; + r_z0__53 <=c_z0__53; + r_mut__53 <=c_mut__53; + + //for 54 + r_x__54 <=c_x__54; + r_y__54 <=c_y__54; + r_z__54 <=c_z__54; + r_ux__54 <=c_ux__54; + r_uy__54 <=c_uy__54; + r_uz__54 <=c_uz__54; + r_sz__54 <=c_sz__54; + r_sr__54 <=c_sr__54; + r_sleftz__54 <=c_sleftz__54; + r_sleftr__54 <=c_sleftr__54; + r_weight__54 <=c_weight__54; + r_layer__54 <=c_layer__54; + r_dead__54 <=c_dead__54; + r_hit__54 <=c_hit__54; + r_diff__54 <=c_diff__54; + r_dl_b__54 <=c_dl_b__54; + r_numer__54 <=c_numer__54; + r_z1__54 <=c_z1__54; + r_z0__54 <=c_z0__54; + r_mut__54 <=c_mut__54; + + //for 55 + r_x__55 <=c_x__55; + r_y__55 <=c_y__55; + r_z__55 <=c_z__55; + r_ux__55 <=c_ux__55; + r_uy__55 <=c_uy__55; + r_uz__55 <=c_uz__55; + r_sz__55 <=c_sz__55; + r_sr__55 <=c_sr__55; + r_sleftz__55 <=c_sleftz__55; + r_sleftr__55 <=c_sleftr__55; + r_weight__55 <=c_weight__55; + r_layer__55 <=c_layer__55; + r_dead__55 <=c_dead__55; + r_hit__55 <=c_hit__55; + r_diff__55 <=c_diff__55; + r_dl_b__55 <=c_dl_b__55; + r_numer__55 <=c_numer__55; + r_z1__55 <=c_z1__55; + r_z0__55 <=c_z0__55; + r_mut__55 <=c_mut__55; + + //for 56 + r_x__56 <=c_x__56; + r_y__56 <=c_y__56; + r_z__56 <=c_z__56; + r_ux__56 <=c_ux__56; + r_uy__56 <=c_uy__56; + r_uz__56 <=c_uz__56; + r_sz__56 <=c_sz__56; + r_sr__56 <=c_sr__56; + r_sleftz__56 <=c_sleftz__56; + r_sleftr__56 <=c_sleftr__56; + r_weight__56 <=c_weight__56; + r_layer__56 <=c_layer__56; + r_dead__56 <=c_dead__56; + r_hit__56 <=c_hit__56; + r_diff__56 <=c_diff__56; + r_dl_b__56 <=c_dl_b__56; + r_numer__56 <=c_numer__56; + r_z1__56 <=c_z1__56; + r_z0__56 <=c_z0__56; + r_mut__56 <=c_mut__56; + + //for 57 + r_x__57 <=c_x__57; + r_y__57 <=c_y__57; + r_z__57 <=c_z__57; + r_ux__57 <=c_ux__57; + r_uy__57 <=c_uy__57; + r_uz__57 <=c_uz__57; + r_sz__57 <=c_sz__57; + r_sr__57 <=c_sr__57; + r_sleftz__57 <=c_sleftz__57; + r_sleftr__57 <=c_sleftr__57; + r_weight__57 <=c_weight__57; + r_layer__57 <=c_layer__57; + r_dead__57 <=c_dead__57; + r_hit__57 <=c_hit__57; + r_diff__57 <=c_diff__57; + r_dl_b__57 <=c_dl_b__57; + r_numer__57 <=c_numer__57; + r_z1__57 <=c_z1__57; + r_z0__57 <=c_z0__57; + r_mut__57 <=c_mut__57; + + //for 58 + r_x__58 <=c_x__58; + r_y__58 <=c_y__58; + r_z__58 <=c_z__58; + r_ux__58 <=c_ux__58; + r_uy__58 <=c_uy__58; + r_uz__58 <=c_uz__58; + r_sz__58 <=c_sz__58; + r_sr__58 <=c_sr__58; + r_sleftz__58 <=c_sleftz__58; + r_sleftr__58 <=c_sleftr__58; + r_weight__58 <=c_weight__58; + r_layer__58 <=c_layer__58; + r_dead__58 <=c_dead__58; + r_hit__58 <=c_hit__58; + r_diff__58 <=c_diff__58; + r_dl_b__58 <=c_dl_b__58; + r_numer__58 <=c_numer__58; + r_z1__58 <=c_z1__58; + r_z0__58 <=c_z0__58; + r_mut__58 <=c_mut__58; + + //for 59 + r_x__59 <=c_x__59; + r_y__59 <=c_y__59; + r_z__59 <=c_z__59; + r_ux__59 <=c_ux__59; + r_uy__59 <=c_uy__59; + r_uz__59 <=c_uz__59; + r_sz__59 <=c_sz__59; + r_sr__59 <=c_sr__59; + r_sleftz__59 <=c_sleftz__59; + r_sleftr__59 <=c_sleftr__59; + r_weight__59 <=c_weight__59; + r_layer__59 <=c_layer__59; + r_dead__59 <=c_dead__59; + r_hit__59 <=c_hit__59; + r_diff__59 <=c_diff__59; + r_dl_b__59 <=c_dl_b__59; + r_numer__59 <=c_numer__59; + r_z1__59 <=c_z1__59; + r_z0__59 <=c_z0__59; + r_mut__59 <=c_mut__59; + + end + end +end + +endmodule + + +///////////////////////////////////////////////////////////// +//mult_signed_32_bc +///////////////////////////////////////////////////////////// +module mult_signed_32_bc ( clock, dataa, datab, result); + + + input clock; + input [31:0] dataa; + input [31:0] datab; + output [63:0] result; + reg [63:0] result; + + wire [63:0] prelim_result; + + + wire [31:0] opa; + wire [31:0] opb; + wire [31:0] opa_comp; + wire [31:0] opb_comp; + + assign opa_comp = ((~dataa) + 32'b00000000000000000000000000000001); + + assign opb_comp = ((~datab) + 32'b00000000000000000000000000000001); + + + wire opa_is_neg; + wire opb_is_neg; + assign opa_is_neg = dataa[31]; + assign opb_is_neg = datab [31]; + assign opa = (opa_is_neg== 1'b1) ? opa_comp:dataa; + assign opb = (opb_is_neg == 1'b1) ? opb_comp:datab; + + + assign prelim_result = opa * opb ; + wire sign; + assign sign = dataa[31] ^ datab[31]; + + wire [63:0] prelim_result_comp; + wire [63:0] prelim_result_changed; + wire [63:0] result_changed; + assign result_changed = (sign==1'b1)? prelim_result_comp :prelim_result; + assign prelim_result_comp = ((~prelim_result) + 1); + + always @ (posedge clock) + begin + result <= result_changed; + end + + endmodule + + +///////////////////////////////////////////////////////////// +//signed_div_30 +///////////////////////////////////////////////////////////// +module signed_div_30 (clock , denom , numer, quotient, remain); + +input clock; + +input [31:0] denom; + +input [63:0] numer; + +output [63:0] quotient; + +output [31:0] remain; + +Div_64b div_replace (.clock(clock), .denom(denom), .numer(numer), .quotient(quotient), .remain(remain)); + +endmodule +module Hop( //INPUTS + clock, reset, enable, + x_boundaryChecker, y_boundaryChecker, z_boundaryChecker, + ux_boundaryChecker, uy_boundaryChecker, uz_boundaryChecker, + sz_boundaryChecker, sr_boundaryChecker, + sleftz_boundaryChecker, sleftr_boundaryChecker, + layer_boundaryChecker, weight_boundaryChecker, dead_boundaryChecker, + hit_boundaryChecker, + + //OUTPUTS + x_hop, y_hop, z_hop, + ux_hop, uy_hop, uz_hop, + sz_hop, sr_hop, + sleftz_hop, sleftr_hop, + layer_hop, weight_hop, dead_hop, hit_hop + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter INTMAX=2147483647; +//parameter INTMIN=-2147483648; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_boundaryChecker; +input [`BIT_WIDTH-1:0] y_boundaryChecker; +input [`BIT_WIDTH-1:0] z_boundaryChecker; +input [`BIT_WIDTH-1:0] ux_boundaryChecker; +input [`BIT_WIDTH-1:0] uy_boundaryChecker; +input [`BIT_WIDTH-1:0] uz_boundaryChecker; +input [`BIT_WIDTH-1:0] sz_boundaryChecker; +input [`BIT_WIDTH-1:0] sr_boundaryChecker; +input [`BIT_WIDTH-1:0] sleftz_boundaryChecker; +input [`BIT_WIDTH-1:0] sleftr_boundaryChecker; +input [`LAYER_WIDTH-1:0] layer_boundaryChecker; +input [`BIT_WIDTH-1:0] weight_boundaryChecker; +input dead_boundaryChecker; +input hit_boundaryChecker; + +output [`BIT_WIDTH-1:0] x_hop; +output [`BIT_WIDTH-1:0] y_hop; +output [`BIT_WIDTH-1:0] z_hop; +output [`BIT_WIDTH-1:0] ux_hop; +output [`BIT_WIDTH-1:0] uy_hop; +output [`BIT_WIDTH-1:0] uz_hop; +output [`BIT_WIDTH-1:0] sz_hop; +output [`BIT_WIDTH-1:0] sr_hop; +output [`BIT_WIDTH-1:0] sleftz_hop; +output [`BIT_WIDTH-1:0] sleftr_hop; +output [`LAYER_WIDTH-1:0]layer_hop; +output [`BIT_WIDTH-1:0] weight_hop; +output dead_hop; +output hit_hop; + +//------------Local Variables------------------------ +reg [`BIT_WIDTH-1:0] c_x; +reg [`BIT_WIDTH-1:0] c_y; +reg [`BIT_WIDTH-1:0] c_z; +reg c_dead; + +reg [`BIT_WIDTH:0] c_x_big; +reg [`BIT_WIDTH:0] c_y_big; +reg [`BIT_WIDTH:0] c_z_big; + +wire [2*`BIT_WIDTH-1:0] c_xmult_big; +wire [2*`BIT_WIDTH-1:0] c_ymult_big; +wire [2*`BIT_WIDTH-1:0] c_zmult_big; + +//------------REGISTERED Values------------------------ +reg [`BIT_WIDTH-1:0] x_hop; +reg [`BIT_WIDTH-1:0] y_hop; +reg [`BIT_WIDTH-1:0] z_hop; +reg [`BIT_WIDTH-1:0] ux_hop; +reg [`BIT_WIDTH-1:0] uy_hop; +reg [`BIT_WIDTH-1:0] uz_hop; +reg [`BIT_WIDTH-1:0] sz_hop; +reg [`BIT_WIDTH-1:0] sr_hop; +reg [`BIT_WIDTH-1:0] sleftz_hop; +reg [`BIT_WIDTH-1:0] sleftr_hop; +reg [`LAYER_WIDTH-1:0]layer_hop; +reg [`BIT_WIDTH-1:0] weight_hop; +reg dead_hop; +reg hit_hop; + +mult_signed_32 u1(sr_boundaryChecker, ux_boundaryChecker, c_xmult_big); +mult_signed_32 u2(sr_boundaryChecker, uy_boundaryChecker, c_ymult_big); +mult_signed_32 u3(sz_boundaryChecker, uz_boundaryChecker, c_zmult_big); + +// Determine new (x,y,z) coordinates +always @(c_dead or + c_x_big or c_y_big or c_z_big or + c_x or c_y or c_z or + x_boundaryChecker or y_boundaryChecker or z_boundaryChecker or + c_xmult_big or c_ymult_big or c_zmult_big + or hit_boundaryChecker or dead_boundaryChecker) +begin + + c_x_big = x_boundaryChecker + c_xmult_big[2*`BIT_WIDTH-2:31]; + c_y_big = y_boundaryChecker + c_ymult_big[2*`BIT_WIDTH-2:31]; + c_z_big = z_boundaryChecker + c_zmult_big[2*`BIT_WIDTH-2:31]; + + + // Calculate x position, photon dies if outside grid + if(c_x_big[`BIT_WIDTH] != c_x_big[`BIT_WIDTH-1] && x_boundaryChecker[`BIT_WIDTH-1] == c_xmult_big[2*`BIT_WIDTH-2]) + begin + if(c_x_big[`BIT_WIDTH] == 1'b0) + begin + // c_dead = 1'b1; + c_x = `INTMAX; + end + else + begin + // c_dead = 1'b1; + c_x = `INTMIN; + end + end + else + begin + c_x = c_x_big[`BIT_WIDTH-1:0]; + end + + + // Calculate y position, photon dies if outside grid + if(c_y_big[`BIT_WIDTH] != c_y_big[`BIT_WIDTH-1] && y_boundaryChecker[`BIT_WIDTH-1] == c_ymult_big[2*`BIT_WIDTH-2]) + begin + if(c_y_big[`BIT_WIDTH] == 1'b0) + begin + // c_dead = 1'b1; + c_y = `INTMAX; + end + else + begin + // c_dead = 1'b1; + c_y = `INTMIN; + end + end + else + begin + c_y = c_y_big[`BIT_WIDTH-1:0]; + end + + // Calculate z position, photon dies if outside grid + if(hit_boundaryChecker) + begin + c_z = z_boundaryChecker; + end + else if(c_z_big[`BIT_WIDTH] != c_z_big[`BIT_WIDTH-1] && z_boundaryChecker[`BIT_WIDTH-1] == c_zmult_big[2*`BIT_WIDTH-2]) + begin + // c_dead = 1'b1; + c_z = `INTMAX; + end + else if (c_z_big[`BIT_WIDTH-1] == 1'b1) + begin + // c_dead = 1'b1; + c_z = 0; + end + else + begin + c_z = c_z_big[`BIT_WIDTH-1:0]; + end + + // Calculate c_dead (necessary because odin does not support block statements). + if( (c_x_big[`BIT_WIDTH] != c_x_big[`BIT_WIDTH-1] && x_boundaryChecker[`BIT_WIDTH-1] == c_xmult_big[2*`BIT_WIDTH-2]) + |(c_y_big[`BIT_WIDTH] != c_y_big[`BIT_WIDTH-1] && y_boundaryChecker[`BIT_WIDTH-1] == c_ymult_big[2*`BIT_WIDTH-2]) + |(c_z_big[`BIT_WIDTH] != c_z_big[`BIT_WIDTH-1] && z_boundaryChecker[`BIT_WIDTH-1] == c_zmult_big[2*`BIT_WIDTH-2]) ) + begin + c_dead = 1'b1; + end + else + begin + c_dead = dead_boundaryChecker; + end + +end + +// latch values +always @ (posedge clock) +begin + if (reset) + begin + // Photon variables + x_hop <= 0; + y_hop <= 0; + z_hop <= 0; + ux_hop <= 0; + uy_hop <= 0; + uz_hop <= 0; + sz_hop <= 0; + sr_hop <= 0; + sleftz_hop <= 0; + sleftr_hop <= 0; + layer_hop <= 0; + weight_hop <= 0; + dead_hop <= 1'b1; + hit_hop <= 1'b0; + end + else + begin + if(enable) + begin + // Photon variables + ux_hop <= ux_boundaryChecker; + uy_hop <= uy_boundaryChecker; + uz_hop <= uz_boundaryChecker; + sz_hop <= sz_boundaryChecker; + sr_hop <= sr_boundaryChecker; + sleftz_hop <= sleftz_boundaryChecker; + sleftr_hop <= sleftr_boundaryChecker; + layer_hop <= layer_boundaryChecker; + weight_hop <= weight_boundaryChecker; + hit_hop <= hit_boundaryChecker; + + x_hop <= c_x; + y_hop <= c_y; + z_hop <= c_z; + dead_hop <= c_dead; + end + end +end + +endmodule + + +///////////////////////////////////////////////////////////// +//mult_signed_32 +///////////////////////////////////////////////////////////// +module mult_signed_32(a, b, c); + input [31:0]a; + input [31:0]b; + output [63:0]c; + reg [63:0]c; + + reg is_neg_a; + reg is_neg_b; + reg [31:0]a_tmp; + reg [31:0]b_tmp; + reg [63:0]c_tmp; + + +always@(a or b or is_neg_a or is_neg_b or a_tmp or b_tmp or c) +begin + + if(a[31] == 1) begin + a_tmp = -a; + is_neg_a = 1; + end else + begin + a_tmp = a; + is_neg_a = 0; + end + + if(b[31] == 1) begin + b_tmp = -b; + is_neg_b = 1; + end else + begin + b_tmp = b; + is_neg_b = 0; + end + + if( is_neg_a != is_neg_b) begin + c_tmp = -(a_tmp * b_tmp); + end else + begin + c_tmp = (a_tmp * b_tmp); + end +end + +always@(c_tmp) +begin + c = c_tmp; +end + +endmodule + + +module Roulette ( //INPUTS + clock, reset, enable, + x_RouletteMux, y_RouletteMux, z_RouletteMux, + ux_RouletteMux, uy_RouletteMux, uz_RouletteMux, + sz_RouletteMux, sr_RouletteMux, + sleftz_RouletteMux, sleftr_RouletteMux, + layer_RouletteMux, weight_absorber, dead_RouletteMux, + + //From Random Number Generator in Skeleton.v + randnumber, + + //OUTPUTS + x_Roulette, y_Roulette, z_Roulette, + ux_Roulette, uy_Roulette, uz_Roulette, + sz_Roulette, sr_Roulette, + sleftz_Roulette, sleftr_Roulette, + layer_Roulette, weight_Roulette, dead_Roulette + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; + +//parameter LEFTSHIFT=3; // 2^3=8=1/0.125 where 0.125 = CHANCE of roulette +//parameter INTCHANCE=536870912; //Based on 32 bit rand num generator +//parameter MIN_WEIGHT=200; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] x_RouletteMux; +input [`BIT_WIDTH-1:0] y_RouletteMux; +input [`BIT_WIDTH-1:0] z_RouletteMux; +input [`BIT_WIDTH-1:0] ux_RouletteMux; +input [`BIT_WIDTH-1:0] uy_RouletteMux; +input [`BIT_WIDTH-1:0] uz_RouletteMux; +input [`BIT_WIDTH-1:0] sz_RouletteMux; +input [`BIT_WIDTH-1:0] sr_RouletteMux; +input [`BIT_WIDTH-1:0] sleftz_RouletteMux; +input [`BIT_WIDTH-1:0] sleftr_RouletteMux; +input [`LAYER_WIDTH-1:0] layer_RouletteMux; +input [`BIT_WIDTH-1:0] weight_absorber; +input [`BIT_WIDTH-1:0] randnumber; +input dead_RouletteMux; + +output [`BIT_WIDTH-1:0] x_Roulette; +output [`BIT_WIDTH-1:0] y_Roulette; +output [`BIT_WIDTH-1:0] z_Roulette; +output [`BIT_WIDTH-1:0] ux_Roulette; +output [`BIT_WIDTH-1:0] uy_Roulette; +output [`BIT_WIDTH-1:0] uz_Roulette; +output [`BIT_WIDTH-1:0] sz_Roulette; +output [`BIT_WIDTH-1:0] sr_Roulette; +output [`BIT_WIDTH-1:0] sleftz_Roulette; +output [`BIT_WIDTH-1:0] sleftr_Roulette; +output [`LAYER_WIDTH-1:0]layer_Roulette; +output [`BIT_WIDTH-1:0] weight_Roulette; +output dead_Roulette; + +//------------Local Variables------------------------ +reg dead_roulette; +reg [`BIT_WIDTH-1:0] weight_roulette; +reg [31:0] randBits; //Hard-coded bitwidth because rng is 32-bit + +//------------REGISTERED Values------------------------ +reg [`BIT_WIDTH-1:0] x_Roulette; +reg [`BIT_WIDTH-1:0] y_Roulette; +reg [`BIT_WIDTH-1:0] z_Roulette; +reg [`BIT_WIDTH-1:0] ux_Roulette; +reg [`BIT_WIDTH-1:0] uy_Roulette; +reg [`BIT_WIDTH-1:0] uz_Roulette; +reg [`BIT_WIDTH-1:0] sz_Roulette; +reg [`BIT_WIDTH-1:0] sr_Roulette; +reg [`BIT_WIDTH-1:0] sleftz_Roulette; +reg [`BIT_WIDTH-1:0] sleftr_Roulette; +reg [`LAYER_WIDTH-1:0]layer_Roulette; +reg [`BIT_WIDTH-1:0] weight_Roulette; +reg dead_Roulette; + +always @ (reset or enable or weight_absorber or randBits or randnumber or dead_RouletteMux) begin + //Default case moved inside else statements for odin + //randBits = randnumber; //Reading from external random num generator + //weight_roulette=weight_absorber; //Avoid inferring a latch + //dead_roulette=dead_RouletteMux; + + if (reset) begin + //Local variables + weight_roulette=0; + dead_roulette=0; + randBits=0; + end + + else if (enable) begin + //Set default case + randBits = randnumber; + //DO ROULETTE!!! + if (weight_absorber < `MIN_WEIGHT && !dead_RouletteMux) begin + //Replicate Operator (same as 32'b000000..., except more flexible) + if (weight_absorber== {`BIT_WIDTH{1'b0}}) begin + dead_roulette = 1; + weight_roulette = weight_absorber; + end + + else if (randBits < `INTCHANCE) begin // survived the roulette + dead_roulette=0; + weight_roulette=weight_absorber << `LEFTSHIFT; //To avoid mult + end + + else begin + dead_roulette=1; + weight_roulette = weight_absorber; + end + end + + //No Roulette + else begin + weight_roulette = weight_absorber; + dead_roulette = 0; + end + end + + else //for insurance that this is default case + begin + randBits = randnumber; + weight_roulette = weight_absorber; + dead_roulette = dead_RouletteMux; + end +end + +always @ (posedge clock) begin + if (reset) begin + x_Roulette <= 0; + y_Roulette <= 0; + z_Roulette <= 0; + ux_Roulette <= 0; + uy_Roulette <= 0; + uz_Roulette <= 0; + sz_Roulette <= 0; + sr_Roulette <= 0; + sleftz_Roulette <= 0; + sleftr_Roulette <= 0; + layer_Roulette <= 0; + weight_Roulette <= 0; + dead_Roulette <= 1'b1; + end + + else if (enable) begin + //Write through values from Roulette block + dead_Roulette <= (dead_RouletteMux | dead_roulette); //OR operator ??? + weight_Roulette <= weight_roulette; //weight_absorber.read(); + + //Write through unchanged values + x_Roulette <= x_RouletteMux; + y_Roulette <= y_RouletteMux; + z_Roulette <= z_RouletteMux; + + ux_Roulette <= ux_RouletteMux; + uy_Roulette <= uy_RouletteMux; + uz_Roulette <= uz_RouletteMux; + sz_Roulette <= sz_RouletteMux; + sr_Roulette <= sr_RouletteMux; + sleftz_Roulette <= sleftz_RouletteMux; + sleftr_Roulette <= sleftr_RouletteMux; + layer_Roulette <= layer_RouletteMux; + end +end + +endmodule + + +module rng(clk, en, resetn,loadseed_i,seed_i,number_o); +input clk; +input resetn; +input en; +input loadseed_i; +input [31:0] seed_i; +output [31:0] number_o; + +wire [31:0] number_o; + +reg [31:0] c_b1, c_b2, c_b3; +reg [31:0] c_s1, c_s2, c_s3; + +reg [31:0] r_s1, r_s2, r_s3; + +assign number_o = r_s1 ^ r_s2 ^ r_s3; + +always @(loadseed_i or seed_i or r_s1 or r_s2 or r_s3) +begin + if(loadseed_i) + begin + c_b1 = 32'b0; + c_s1 = seed_i; + c_b2 = 32'b0; + c_s2 = {seed_i[5:0], seed_i[17], seed_i[18], seed_i[19], seed_i[20], seed_i[25:21], seed_i[31:26], seed_i[16:6]} ^ 32'd1493609598; + c_b3 = 32'b0; + c_s3 = {seed_i[23:16], seed_i[5], seed_i[6], seed_i[7], seed_i[15:8], seed_i[4:0], seed_i[31:24]} ^ 32'd3447127471; + end + else + begin + c_b1 = (((r_s1 << 13) ^ r_s1) >> 19); + c_s1 = (((r_s1 & 32'd4294967294) << 12) ^ c_b1); + c_b2 = (((r_s2 << 2) ^ r_s2) >> 25); + c_s2 = (((r_s2 & 32'd4294967288) << 4) ^ c_b2); + c_b3 = (((r_s3 << 3) ^ r_s3) >> 11); + c_s3 = (((r_s3 & 32'd4294967280) << 17) ^ c_b3); + end +end + + +//combinate: +always @(posedge clk or negedge resetn) + begin + if (!resetn ) + begin + r_s1 <= 32'b0; + r_s2 <= 32'b0; + r_s3 <= 32'b0; + end + else if (en) //Originally else only + begin + r_s1 <= c_s1; + r_s2 <= c_s2; + r_s3 <= c_s3; + end + end + +endmodule + + + +module LogCalc(clock, reset, enable, in_x, log_x); + +//parameter BIT_WIDTH=32; +//parameter MANTISSA_PRECISION=10; +//parameter LOG2_BIT_WIDTH = 6; +//parameter LOG2=93032639; + +input clock; +input reset; +input enable; +input [`BIT_WIDTH - 1:0] in_x; +output [`BIT_WIDTH - 1:0] log_x; + + +wire [`BIT_WIDTH - 1:0] mantissa; + +reg [`BIT_WIDTH - 1:0] c_mantissa_val; + +// deleted unsigned in these +reg [`BIT_WIDTH - 1:0] c_log_x; +reg [`LOG2_BIT_WIDTH - 1:0] c_indexFirstOne; +reg [`BIT_WIDTH - 1:0] c_temp_shift_x; +reg [`MANTISSA_PRECISION - 1:0] c_shifted_x; + +reg [`LOG2_BIT_WIDTH - 1:0] r_indexFirstOne; +reg [`BIT_WIDTH - 1:0] log_x; + +//Log_mantissa u1(c_shifted_x, clock, mantissa); +wire [31:0]blank; +assign blank = 32'b000000000000000000000000000000; +single_port_ram sram_replace0 (.clk (clock), .addr (c_shifted_x), .data (blank), .we (1'b0), .out (mantissa)); + +// priority encoder +//integer i; +//always @* +//begin +// c_indexFirstOne = 6'b0; +// for(i = 0; i < `BIT_WIDTH; i = i + 1) +// begin +// if(in_x[i]) +// c_indexFirstOne = i; +// end +//end + +// Priority encoder, loop expanded +always @(in_x) +begin + if (in_x[31]) begin + c_indexFirstOne = 6'b011111; + end + else if (in_x[30]) begin + c_indexFirstOne = 6'b011110; + end + else if (in_x[29]) begin + c_indexFirstOne = 6'b011101; + end + else if (in_x[28]) begin + c_indexFirstOne = 6'b011100; + end + else if (in_x[27]) begin + c_indexFirstOne = 6'b011011; + end + else if (in_x[26]) begin + c_indexFirstOne = 6'b011010; + end + else if (in_x[25]) begin + c_indexFirstOne = 6'b011001; + end + else if (in_x[24]) begin + c_indexFirstOne = 6'b011000; + end + else if (in_x[23]) begin + c_indexFirstOne = 6'b010111; + end + else if (in_x[22]) begin + c_indexFirstOne = 6'b010110; + end + else if (in_x[21]) begin + c_indexFirstOne = 6'b010101; + end + else if (in_x[20]) begin + c_indexFirstOne = 6'b010100; + end + else if (in_x[19]) begin + c_indexFirstOne = 6'b010011; + end + else if (in_x[18]) begin + c_indexFirstOne = 6'b010010; + end + else if (in_x[17]) begin + c_indexFirstOne = 6'b010001; + end + else if (in_x[16]) begin + c_indexFirstOne = 6'b010000; + end + else if (in_x[15]) begin + c_indexFirstOne = 6'b001111; + end + else if (in_x[14]) begin + c_indexFirstOne = 6'b001110; + end + else if (in_x[13]) begin + c_indexFirstOne = 6'b001101; + end + else if (in_x[12]) begin + c_indexFirstOne = 6'b001100; + end + else if (in_x[11]) begin + c_indexFirstOne = 6'b001011; + end + else if (in_x[10]) begin + c_indexFirstOne = 6'b001010; + end + else if (in_x[9]) begin + c_indexFirstOne = 6'b001001; + end + else if (in_x[8]) begin + c_indexFirstOne = 6'b001000; + end + else if (in_x[7]) begin + c_indexFirstOne = 6'b000111; + end + else if (in_x[6]) begin + c_indexFirstOne = 6'b000110; + end + else if (in_x[5]) begin + c_indexFirstOne = 6'b000101; + end + else if (in_x[4]) begin + c_indexFirstOne = 6'b000100; + end + else if (in_x[3]) begin + c_indexFirstOne = 6'b000011; + end + else if (in_x[2]) begin + c_indexFirstOne = 6'b000010; + end + else if (in_x[1]) begin + c_indexFirstOne = 6'b000001; + end + else if (in_x[0]) begin + c_indexFirstOne = 6'b000000; + end + else begin + c_indexFirstOne = 6'b000000; + end +end + +// shift operation based on priority encoder results + +//Need constant shift +wire [5:0]shifted; +assign shifted = c_indexFirstOne - `MANTISSA_PRECISION + 1; + +always@(c_indexFirstOne or in_x or shifted) +begin +// c_temp_shift_x = in_x >> (c_indexFirstOne - `MANTISSA_PRECISION + 1); + if(c_indexFirstOne >= `MANTISSA_PRECISION) + begin + if(shifted == 22) begin + c_temp_shift_x = in_x >> 22; + end + else if(shifted == 21) begin + c_temp_shift_x = in_x >> 21; + end + else if(shifted == 20) begin + c_temp_shift_x = in_x >> 20; + end + else if(shifted == 19) begin + c_temp_shift_x = in_x >> 19; + end + else if(shifted == 18) begin + c_temp_shift_x = in_x >> 18; + end + else if(shifted == 17) begin + c_temp_shift_x = in_x >> 17; + end + else if(shifted == 16) begin + c_temp_shift_x = in_x >> 16; + end + else if(shifted == 15) begin + c_temp_shift_x = in_x >> 15; + end + else if(shifted == 14) begin + c_temp_shift_x = in_x >> 14; + end + else if(shifted == 13) begin + c_temp_shift_x = in_x >> 13; + end + else if(shifted == 12) begin + c_temp_shift_x = in_x >> 12; + end + else if(shifted == 11) begin + c_temp_shift_x = in_x >> 11; + end + else if(shifted == 10) begin + c_temp_shift_x = in_x >> 10; + end + else if(shifted == 9) begin + c_temp_shift_x = in_x >> 9; + end + else if(shifted == 8) begin + c_temp_shift_x = in_x >> 8; + end + else if(shifted == 7) begin + c_temp_shift_x = in_x >> 7; + end + else if(shifted == 6) begin + c_temp_shift_x = in_x >> 6; + end + else if(shifted == 5) begin + c_temp_shift_x = in_x >> 5; + end + else if(shifted == 4) begin + c_temp_shift_x = in_x >> 4; + end + else if(shifted == 3) begin + c_temp_shift_x = in_x >> 3; + end + else if(shifted == 2) begin + c_temp_shift_x = in_x >> 2; + end + else if(shifted == 1) begin + c_temp_shift_x = in_x >> 1; + end + else begin + c_temp_shift_x = in_x >> 0; + end + //Store needed bits of shifted value + c_shifted_x = c_temp_shift_x[`MANTISSA_PRECISION - 1:0]; + end + else begin + c_shifted_x = in_x[`MANTISSA_PRECISION - 1:0]; + c_temp_shift_x = 32'b0; + end +end + +// calculate log +always@(r_indexFirstOne or mantissa) +begin + if(r_indexFirstOne >= `MANTISSA_PRECISION) + begin + c_log_x = mantissa - ((`MANTISSA_PRECISION - 1) * `LOG2) + (r_indexFirstOne * `LOG2); + end + else + begin + c_log_x = mantissa; + end +end + +// latch values +always @(posedge clock) +begin + if(reset) + begin + log_x <= 0; + r_indexFirstOne <= 0; + end + else + begin + if(enable) + begin + r_indexFirstOne <= c_indexFirstOne; + log_x <= c_log_x; + end + end +end + +endmodule + + + +module DropSpinWrapper ( + clock, reset, enable, + + //From Hopper Module + i_x, + i_y, + i_z, + i_ux, + i_uy, + i_uz, + i_sz, + i_sr, + i_sleftz, + i_sleftr, + i_weight, + i_layer, + i_dead, + i_hit, + + + //From System Register File (5 layers)- Absorber + muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5, + + //From System Register File - ScattererReflector + down_niOverNt_1, + down_niOverNt_2, + down_niOverNt_3, + down_niOverNt_4, + down_niOverNt_5, + up_niOverNt_1, + up_niOverNt_2, + up_niOverNt_3, + up_niOverNt_4, + up_niOverNt_5, + down_niOverNt_2_1, + down_niOverNt_2_2, + down_niOverNt_2_3, + down_niOverNt_2_4, + down_niOverNt_2_5, + up_niOverNt_2_1, + up_niOverNt_2_2, + up_niOverNt_2_3, + up_niOverNt_2_4, + up_niOverNt_2_5, + downCritAngle_0, + downCritAngle_1, + downCritAngle_2, + downCritAngle_3, + downCritAngle_4, + upCritAngle_0, + upCritAngle_1, + upCritAngle_2, + upCritAngle_3, + upCritAngle_4, + + + + ////////////////////////////////////////////////////////////////////////////// + //I/O to on-chip mem + ///////////////////////////////////////////////////////////////////////////// + + data, + rdaddress, wraddress, + wren, q, + + //From Memories + up_rFresnel, + down_rFresnel, + sint, + cost, + rand2, + rand3, + rand5, + //To Memories + tindex, + fresIndex, + + + //To DeadOrAlive Module + o_x, + o_y, + o_z, + o_ux, + o_uy, + o_uz, + o_sz, + o_sr, + o_sleftz, + o_sleftr, + o_weight, + o_layer, + o_dead, + o_hit + + ); + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; +//parameter PIPE_DEPTH = 37; +//parameter ADDR_WIDTH=16; //TODO: TBD +//parameter WORD_WIDTH=64; + +////////////////////////////////////////////////////////////////////////////// +//INPUTS +////////////////////////////////////////////////////////////////////////////// +input clock, reset, enable; + +//From Hopper Module +input [`BIT_WIDTH-1:0] i_x; +input [`BIT_WIDTH-1:0] i_y; +input [`BIT_WIDTH-1:0] i_z; +input [`BIT_WIDTH-1:0] i_ux; +input [`BIT_WIDTH-1:0] i_uy; +input [`BIT_WIDTH-1:0] i_uz; +input [`BIT_WIDTH-1:0] i_sz; +input [`BIT_WIDTH-1:0] i_sr; +input [`BIT_WIDTH-1:0] i_sleftz; +input [`BIT_WIDTH-1:0] i_sleftr; +input [`BIT_WIDTH-1:0] i_weight; +input [`LAYER_WIDTH-1:0] i_layer; +input i_dead; +input i_hit; + + +//From System Register File (5 layers)- Absorber +input [`BIT_WIDTH-1:0] muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5; + +//From System Register File - ScattererReflector +input [`BIT_WIDTH-1:0] down_niOverNt_1; +input [`BIT_WIDTH-1:0] down_niOverNt_2; +input [`BIT_WIDTH-1:0] down_niOverNt_3; +input [`BIT_WIDTH-1:0] down_niOverNt_4; +input [`BIT_WIDTH-1:0] down_niOverNt_5; +input [`BIT_WIDTH-1:0] up_niOverNt_1; +input [`BIT_WIDTH-1:0] up_niOverNt_2; +input [`BIT_WIDTH-1:0] up_niOverNt_3; +input [`BIT_WIDTH-1:0] up_niOverNt_4; +input [`BIT_WIDTH-1:0] up_niOverNt_5; +input [`WORD_WIDTH-1:0] down_niOverNt_2_1; +input [`WORD_WIDTH-1:0] down_niOverNt_2_2; +input [`WORD_WIDTH-1:0] down_niOverNt_2_3; +input [`WORD_WIDTH-1:0] down_niOverNt_2_4; +input [`WORD_WIDTH-1:0] down_niOverNt_2_5; +input [`WORD_WIDTH-1:0] up_niOverNt_2_1; +input [`WORD_WIDTH-1:0] up_niOverNt_2_2; +input [`WORD_WIDTH-1:0] up_niOverNt_2_3; +input [`WORD_WIDTH-1:0] up_niOverNt_2_4; +input [`WORD_WIDTH-1:0] up_niOverNt_2_5; +input [`BIT_WIDTH-1:0] downCritAngle_0; +input [`BIT_WIDTH-1:0] downCritAngle_1; +input [`BIT_WIDTH-1:0] downCritAngle_2; +input [`BIT_WIDTH-1:0] downCritAngle_3; +input [`BIT_WIDTH-1:0] downCritAngle_4; +input [`BIT_WIDTH-1:0] upCritAngle_0; +input [`BIT_WIDTH-1:0] upCritAngle_1; +input [`BIT_WIDTH-1:0] upCritAngle_2; +input [`BIT_WIDTH-1:0] upCritAngle_3; +input [`BIT_WIDTH-1:0] upCritAngle_4; + +//Generated by random number generators controlled by skeleton +output [12:0] tindex; +output [9:0] fresIndex; + + +input [31:0] rand2; +input [31:0] rand3; +input [31:0] rand5; +input [31:0] sint; +input [31:0] cost; +input [31:0] up_rFresnel; +input [31:0] down_rFresnel; + + + +////////////////////////////////////////////////////////////////////////////// +//OUTPUTS +///////////////////////////////////////////////////////////////////////////// +//To DeadOrAlive Module +output [`BIT_WIDTH-1:0] o_x; +output [`BIT_WIDTH-1:0] o_y; +output [`BIT_WIDTH-1:0] o_z; +output [`BIT_WIDTH-1:0] o_ux; +output [`BIT_WIDTH-1:0] o_uy; +output [`BIT_WIDTH-1:0] o_uz; +output [`BIT_WIDTH-1:0] o_sz; +output [`BIT_WIDTH-1:0] o_sr; +output [`BIT_WIDTH-1:0] o_sleftz; +output [`BIT_WIDTH-1:0] o_sleftr; +output [`BIT_WIDTH-1:0] o_weight; +output [`LAYER_WIDTH-1:0] o_layer; +output o_dead; +output o_hit; + +wire [`BIT_WIDTH-1:0] o_x; +wire [`BIT_WIDTH-1:0] o_y; +wire [`BIT_WIDTH-1:0] o_z; +reg [`BIT_WIDTH-1:0] o_ux; +reg [`BIT_WIDTH-1:0] o_uy; +reg [`BIT_WIDTH-1:0] o_uz; +wire [`BIT_WIDTH-1:0] o_sz; +wire [`BIT_WIDTH-1:0] o_sr; +wire [`BIT_WIDTH-1:0] o_sleftz; +wire [`BIT_WIDTH-1:0] o_sleftr; +wire [`BIT_WIDTH-1:0] o_weight; +reg [`LAYER_WIDTH-1:0] o_layer; +reg o_dead; +wire o_hit; + + +////////////////////////////////////////////////////////////////////////////// +//I/O to on-chip mem +///////////////////////////////////////////////////////////////////////////// + +output [`WORD_WIDTH-1:0] data; +output [`ADDR_WIDTH-1:0] rdaddress, wraddress; +output wren; +input [`WORD_WIDTH-1:0] q; + + +////////////////////////////////////////////////////////////////////////////// +//Generate SHARED REGISTER PIPELINE +////////////////////////////////////////////////////////////////////////////// +//WIRES FOR CONNECTING REGISTERS +//wire [`BIT_WIDTH-1:0] x [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] y [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] z [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] ux [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] uy [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] uz [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sz [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sr [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sleftz [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] sleftr [PIPE_DEPTH:0]; +//wire [`BIT_WIDTH-1:0] weight [PIPE_DEPTH:0]; +//wire [LAYER_WIDTH-1:0] layer [PIPE_DEPTH:0]; +//wire dead [PIPE_DEPTH:0]; +//wire hit [PIPE_DEPTH:0]; + +//WIRES FOR CONNECTING REGISTERS +//wire [32-1:0] x [37:0]; +wire [32-1:0] x__0; +wire [32-1:0] x__1; +wire [32-1:0] x__2; +wire [32-1:0] x__3; +wire [32-1:0] x__4; +wire [32-1:0] x__5; +wire [32-1:0] x__6; +wire [32-1:0] x__7; +wire [32-1:0] x__8; +wire [32-1:0] x__9; +wire [32-1:0] x__10; +wire [32-1:0] x__11; +wire [32-1:0] x__12; +wire [32-1:0] x__13; +wire [32-1:0] x__14; +wire [32-1:0] x__15; +wire [32-1:0] x__16; +wire [32-1:0] x__17; +wire [32-1:0] x__18; +wire [32-1:0] x__19; +wire [32-1:0] x__20; +wire [32-1:0] x__21; +wire [32-1:0] x__22; +wire [32-1:0] x__23; +wire [32-1:0] x__24; +wire [32-1:0] x__25; +wire [32-1:0] x__26; +wire [32-1:0] x__27; +wire [32-1:0] x__28; +wire [32-1:0] x__29; +wire [32-1:0] x__30; +wire [32-1:0] x__31; +wire [32-1:0] x__32; +wire [32-1:0] x__33; +wire [32-1:0] x__34; +wire [32-1:0] x__35; +wire [32-1:0] x__36; +wire [32-1:0] x__37; + + + + +//wire [32-1:0] y [37:0]; +wire [32-1:0] y__0; +wire [32-1:0] y__1; +wire [32-1:0] y__2; +wire [32-1:0] y__3; +wire [32-1:0] y__4; +wire [32-1:0] y__5; +wire [32-1:0] y__6; +wire [32-1:0] y__7; +wire [32-1:0] y__8; +wire [32-1:0] y__9; +wire [32-1:0] y__10; +wire [32-1:0] y__11; +wire [32-1:0] y__12; +wire [32-1:0] y__13; +wire [32-1:0] y__14; +wire [32-1:0] y__15; +wire [32-1:0] y__16; +wire [32-1:0] y__17; +wire [32-1:0] y__18; +wire [32-1:0] y__19; +wire [32-1:0] y__20; +wire [32-1:0] y__21; +wire [32-1:0] y__22; +wire [32-1:0] y__23; +wire [32-1:0] y__24; +wire [32-1:0] y__25; +wire [32-1:0] y__26; +wire [32-1:0] y__27; +wire [32-1:0] y__28; +wire [32-1:0] y__29; +wire [32-1:0] y__30; +wire [32-1:0] y__31; +wire [32-1:0] y__32; +wire [32-1:0] y__33; +wire [32-1:0] y__34; +wire [32-1:0] y__35; +wire [32-1:0] y__36; +wire [32-1:0] y__37; + + + +//wire [32-1:0] z [37:0]; +wire [32-1:0] z__0; +wire [32-1:0] z__1; +wire [32-1:0] z__2; +wire [32-1:0] z__3; +wire [32-1:0] z__4; +wire [32-1:0] z__5; +wire [32-1:0] z__6; +wire [32-1:0] z__7; +wire [32-1:0] z__8; +wire [32-1:0] z__9; +wire [32-1:0] z__10; +wire [32-1:0] z__11; +wire [32-1:0] z__12; +wire [32-1:0] z__13; +wire [32-1:0] z__14; +wire [32-1:0] z__15; +wire [32-1:0] z__16; +wire [32-1:0] z__17; +wire [32-1:0] z__18; +wire [32-1:0] z__19; +wire [32-1:0] z__20; +wire [32-1:0] z__21; +wire [32-1:0] z__22; +wire [32-1:0] z__23; +wire [32-1:0] z__24; +wire [32-1:0] z__25; +wire [32-1:0] z__26; +wire [32-1:0] z__27; +wire [32-1:0] z__28; +wire [32-1:0] z__29; +wire [32-1:0] z__30; +wire [32-1:0] z__31; +wire [32-1:0] z__32; +wire [32-1:0] z__33; +wire [32-1:0] z__34; +wire [32-1:0] z__35; +wire [32-1:0] z__36; +wire [32-1:0] z__37; + + +//wire [32-1:0] ux [37:0]; +wire [32-1:0] ux__0; +wire [32-1:0] ux__1; +wire [32-1:0] ux__2; +wire [32-1:0] ux__3; +wire [32-1:0] ux__4; +wire [32-1:0] ux__5; +wire [32-1:0] ux__6; +wire [32-1:0] ux__7; +wire [32-1:0] ux__8; +wire [32-1:0] ux__9; +wire [32-1:0] ux__10; +wire [32-1:0] ux__11; +wire [32-1:0] ux__12; +wire [32-1:0] ux__13; +wire [32-1:0] ux__14; +wire [32-1:0] ux__15; +wire [32-1:0] ux__16; +wire [32-1:0] ux__17; +wire [32-1:0] ux__18; +wire [32-1:0] ux__19; +wire [32-1:0] ux__20; +wire [32-1:0] ux__21; +wire [32-1:0] ux__22; +wire [32-1:0] ux__23; +wire [32-1:0] ux__24; +wire [32-1:0] ux__25; +wire [32-1:0] ux__26; +wire [32-1:0] ux__27; +wire [32-1:0] ux__28; +wire [32-1:0] ux__29; +wire [32-1:0] ux__30; +wire [32-1:0] ux__31; +wire [32-1:0] ux__32; +wire [32-1:0] ux__33; +wire [32-1:0] ux__34; +wire [32-1:0] ux__35; +wire [32-1:0] ux__36; +wire [32-1:0] ux__37; + + + +//wire [32-1:0] uy [37:0]; +wire [32-1:0] uy__0; +wire [32-1:0] uy__1; +wire [32-1:0] uy__2; +wire [32-1:0] uy__3; +wire [32-1:0] uy__4; +wire [32-1:0] uy__5; +wire [32-1:0] uy__6; +wire [32-1:0] uy__7; +wire [32-1:0] uy__8; +wire [32-1:0] uy__9; +wire [32-1:0] uy__10; +wire [32-1:0] uy__11; +wire [32-1:0] uy__12; +wire [32-1:0] uy__13; +wire [32-1:0] uy__14; +wire [32-1:0] uy__15; +wire [32-1:0] uy__16; +wire [32-1:0] uy__17; +wire [32-1:0] uy__18; +wire [32-1:0] uy__19; +wire [32-1:0] uy__20; +wire [32-1:0] uy__21; +wire [32-1:0] uy__22; +wire [32-1:0] uy__23; +wire [32-1:0] uy__24; +wire [32-1:0] uy__25; +wire [32-1:0] uy__26; +wire [32-1:0] uy__27; +wire [32-1:0] uy__28; +wire [32-1:0] uy__29; +wire [32-1:0] uy__30; +wire [32-1:0] uy__31; +wire [32-1:0] uy__32; +wire [32-1:0] uy__33; +wire [32-1:0] uy__34; +wire [32-1:0] uy__35; +wire [32-1:0] uy__36; +wire [32-1:0] uy__37; + + +//wire [32-1:0] uz [37:0]; +wire [32-1:0] uz__0; +wire [32-1:0] uz__1; +wire [32-1:0] uz__2; +wire [32-1:0] uz__3; +wire [32-1:0] uz__4; +wire [32-1:0] uz__5; +wire [32-1:0] uz__6; +wire [32-1:0] uz__7; +wire [32-1:0] uz__8; +wire [32-1:0] uz__9; +wire [32-1:0] uz__10; +wire [32-1:0] uz__11; +wire [32-1:0] uz__12; +wire [32-1:0] uz__13; +wire [32-1:0] uz__14; +wire [32-1:0] uz__15; +wire [32-1:0] uz__16; +wire [32-1:0] uz__17; +wire [32-1:0] uz__18; +wire [32-1:0] uz__19; +wire [32-1:0] uz__20; +wire [32-1:0] uz__21; +wire [32-1:0] uz__22; +wire [32-1:0] uz__23; +wire [32-1:0] uz__24; +wire [32-1:0] uz__25; +wire [32-1:0] uz__26; +wire [32-1:0] uz__27; +wire [32-1:0] uz__28; +wire [32-1:0] uz__29; +wire [32-1:0] uz__30; +wire [32-1:0] uz__31; +wire [32-1:0] uz__32; +wire [32-1:0] uz__33; +wire [32-1:0] uz__34; +wire [32-1:0] uz__35; +wire [32-1:0] uz__36; +wire [32-1:0] uz__37; + + +//wire [32-1:0] sz [37:0]; +wire [32-1:0] sz__0; +wire [32-1:0] sz__1; +wire [32-1:0] sz__2; +wire [32-1:0] sz__3; +wire [32-1:0] sz__4; +wire [32-1:0] sz__5; +wire [32-1:0] sz__6; +wire [32-1:0] sz__7; +wire [32-1:0] sz__8; +wire [32-1:0] sz__9; +wire [32-1:0] sz__10; +wire [32-1:0] sz__11; +wire [32-1:0] sz__12; +wire [32-1:0] sz__13; +wire [32-1:0] sz__14; +wire [32-1:0] sz__15; +wire [32-1:0] sz__16; +wire [32-1:0] sz__17; +wire [32-1:0] sz__18; +wire [32-1:0] sz__19; +wire [32-1:0] sz__20; +wire [32-1:0] sz__21; +wire [32-1:0] sz__22; +wire [32-1:0] sz__23; +wire [32-1:0] sz__24; +wire [32-1:0] sz__25; +wire [32-1:0] sz__26; +wire [32-1:0] sz__27; +wire [32-1:0] sz__28; +wire [32-1:0] sz__29; +wire [32-1:0] sz__30; +wire [32-1:0] sz__31; +wire [32-1:0] sz__32; +wire [32-1:0] sz__33; +wire [32-1:0] sz__34; +wire [32-1:0] sz__35; +wire [32-1:0] sz__36; +wire [32-1:0] sz__37; + + +//wire [32-1:0] sr [37:0]; +wire [32-1:0] sr__0; +wire [32-1:0] sr__1; +wire [32-1:0] sr__2; +wire [32-1:0] sr__3; +wire [32-1:0] sr__4; +wire [32-1:0] sr__5; +wire [32-1:0] sr__6; +wire [32-1:0] sr__7; +wire [32-1:0] sr__8; +wire [32-1:0] sr__9; +wire [32-1:0] sr__10; +wire [32-1:0] sr__11; +wire [32-1:0] sr__12; +wire [32-1:0] sr__13; +wire [32-1:0] sr__14; +wire [32-1:0] sr__15; +wire [32-1:0] sr__16; +wire [32-1:0] sr__17; +wire [32-1:0] sr__18; +wire [32-1:0] sr__19; +wire [32-1:0] sr__20; +wire [32-1:0] sr__21; +wire [32-1:0] sr__22; +wire [32-1:0] sr__23; +wire [32-1:0] sr__24; +wire [32-1:0] sr__25; +wire [32-1:0] sr__26; +wire [32-1:0] sr__27; +wire [32-1:0] sr__28; +wire [32-1:0] sr__29; +wire [32-1:0] sr__30; +wire [32-1:0] sr__31; +wire [32-1:0] sr__32; +wire [32-1:0] sr__33; +wire [32-1:0] sr__34; +wire [32-1:0] sr__35; +wire [32-1:0] sr__36; +wire [32-1:0] sr__37; + + + +//wire [32-1:0] sleftz [37:0]; +wire [32-1:0] sleftz__0; +wire [32-1:0] sleftz__1; +wire [32-1:0] sleftz__2; +wire [32-1:0] sleftz__3; +wire [32-1:0] sleftz__4; +wire [32-1:0] sleftz__5; +wire [32-1:0] sleftz__6; +wire [32-1:0] sleftz__7; +wire [32-1:0] sleftz__8; +wire [32-1:0] sleftz__9; +wire [32-1:0] sleftz__10; +wire [32-1:0] sleftz__11; +wire [32-1:0] sleftz__12; +wire [32-1:0] sleftz__13; +wire [32-1:0] sleftz__14; +wire [32-1:0] sleftz__15; +wire [32-1:0] sleftz__16; +wire [32-1:0] sleftz__17; +wire [32-1:0] sleftz__18; +wire [32-1:0] sleftz__19; +wire [32-1:0] sleftz__20; +wire [32-1:0] sleftz__21; +wire [32-1:0] sleftz__22; +wire [32-1:0] sleftz__23; +wire [32-1:0] sleftz__24; +wire [32-1:0] sleftz__25; +wire [32-1:0] sleftz__26; +wire [32-1:0] sleftz__27; +wire [32-1:0] sleftz__28; +wire [32-1:0] sleftz__29; +wire [32-1:0] sleftz__30; +wire [32-1:0] sleftz__31; +wire [32-1:0] sleftz__32; +wire [32-1:0] sleftz__33; +wire [32-1:0] sleftz__34; +wire [32-1:0] sleftz__35; +wire [32-1:0] sleftz__36; +wire [32-1:0] sleftz__37; + + +//wire [32-1:0] sleftr [37:0]; +wire [32-1:0] sleftr__0; +wire [32-1:0] sleftr__1; +wire [32-1:0] sleftr__2; +wire [32-1:0] sleftr__3; +wire [32-1:0] sleftr__4; +wire [32-1:0] sleftr__5; +wire [32-1:0] sleftr__6; +wire [32-1:0] sleftr__7; +wire [32-1:0] sleftr__8; +wire [32-1:0] sleftr__9; +wire [32-1:0] sleftr__10; +wire [32-1:0] sleftr__11; +wire [32-1:0] sleftr__12; +wire [32-1:0] sleftr__13; +wire [32-1:0] sleftr__14; +wire [32-1:0] sleftr__15; +wire [32-1:0] sleftr__16; +wire [32-1:0] sleftr__17; +wire [32-1:0] sleftr__18; +wire [32-1:0] sleftr__19; +wire [32-1:0] sleftr__20; +wire [32-1:0] sleftr__21; +wire [32-1:0] sleftr__22; +wire [32-1:0] sleftr__23; +wire [32-1:0] sleftr__24; +wire [32-1:0] sleftr__25; +wire [32-1:0] sleftr__26; +wire [32-1:0] sleftr__27; +wire [32-1:0] sleftr__28; +wire [32-1:0] sleftr__29; +wire [32-1:0] sleftr__30; +wire [32-1:0] sleftr__31; +wire [32-1:0] sleftr__32; +wire [32-1:0] sleftr__33; +wire [32-1:0] sleftr__34; +wire [32-1:0] sleftr__35; +wire [32-1:0] sleftr__36; +wire [32-1:0] sleftr__37; + + +//wire [32-1:0] weight [37:0]; +wire [32-1:0] weight__0; +wire [32-1:0] weight__1; +wire [32-1:0] weight__2; +wire [32-1:0] weight__3; +wire [32-1:0] weight__4; +wire [32-1:0] weight__5; +wire [32-1:0] weight__6; +wire [32-1:0] weight__7; +wire [32-1:0] weight__8; +wire [32-1:0] weight__9; +wire [32-1:0] weight__10; +wire [32-1:0] weight__11; +wire [32-1:0] weight__12; +wire [32-1:0] weight__13; +wire [32-1:0] weight__14; +wire [32-1:0] weight__15; +wire [32-1:0] weight__16; +wire [32-1:0] weight__17; +wire [32-1:0] weight__18; +wire [32-1:0] weight__19; +wire [32-1:0] weight__20; +wire [32-1:0] weight__21; +wire [32-1:0] weight__22; +wire [32-1:0] weight__23; +wire [32-1:0] weight__24; +wire [32-1:0] weight__25; +wire [32-1:0] weight__26; +wire [32-1:0] weight__27; +wire [32-1:0] weight__28; +wire [32-1:0] weight__29; +wire [32-1:0] weight__30; +wire [32-1:0] weight__31; +wire [32-1:0] weight__32; +wire [32-1:0] weight__33; +wire [32-1:0] weight__34; +wire [32-1:0] weight__35; +wire [32-1:0] weight__36; +wire [32-1:0] weight__37; + + +//wire [3-1:0] layer [37:0]; +wire [3-1:0] layer__0; +wire [3-1:0] layer__1; +wire [3-1:0] layer__2; +wire [3-1:0] layer__3; +wire [3-1:0] layer__4; +wire [3-1:0] layer__5; +wire [3-1:0] layer__6; +wire [3-1:0] layer__7; +wire [3-1:0] layer__8; +wire [3-1:0] layer__9; +wire [3-1:0] layer__10; +wire [3-1:0] layer__11; +wire [3-1:0] layer__12; +wire [3-1:0] layer__13; +wire [3-1:0] layer__14; +wire [3-1:0] layer__15; +wire [3-1:0] layer__16; +wire [3-1:0] layer__17; +wire [3-1:0] layer__18; +wire [3-1:0] layer__19; +wire [3-1:0] layer__20; +wire [3-1:0] layer__21; +wire [3-1:0] layer__22; +wire [3-1:0] layer__23; +wire [3-1:0] layer__24; +wire [3-1:0] layer__25; +wire [3-1:0] layer__26; +wire [3-1:0] layer__27; +wire [3-1:0] layer__28; +wire [3-1:0] layer__29; +wire [3-1:0] layer__30; +wire [3-1:0] layer__31; +wire [3-1:0] layer__32; +wire [3-1:0] layer__33; +wire [3-1:0] layer__34; +wire [3-1:0] layer__35; +wire [3-1:0] layer__36; +wire [3-1:0] layer__37; + +//wire [37:0] dead; +wire dead__0; +wire dead__1; +wire dead__2; +wire dead__3; +wire dead__4; +wire dead__5; +wire dead__6; +wire dead__7; +wire dead__8; +wire dead__9; +wire dead__10; +wire dead__11; +wire dead__12; +wire dead__13; +wire dead__14; +wire dead__15; +wire dead__16; +wire dead__17; +wire dead__18; +wire dead__19; +wire dead__20; +wire dead__21; +wire dead__22; +wire dead__23; +wire dead__24; +wire dead__25; +wire dead__26; +wire dead__27; +wire dead__28; +wire dead__29; +wire dead__30; +wire dead__31; +wire dead__32; +wire dead__33; +wire dead__34; +wire dead__35; +wire dead__36; +wire dead__37; + + +//wire [37:0] hit ; + +wire hit__0; +wire hit__1; +wire hit__2; +wire hit__3; +wire hit__4; +wire hit__5; +wire hit__6; +wire hit__7; +wire hit__8; +wire hit__9; +wire hit__10; +wire hit__11; +wire hit__12; +wire hit__13; +wire hit__14; +wire hit__15; +wire hit__16; +wire hit__17; +wire hit__18; +wire hit__19; +wire hit__20; +wire hit__21; +wire hit__22; +wire hit__23; +wire hit__24; +wire hit__25; +wire hit__26; +wire hit__27; +wire hit__28; +wire hit__29; +wire hit__30; +wire hit__31; +wire hit__32; +wire hit__33; +wire hit__34; +wire hit__35; +wire hit__36; +wire hit__37; + + +//ASSIGNMENTS FROM INPUTS TO PIPE +assign x__0 = i_x; +assign y__0 = i_y; +assign z__0 = i_z; +assign ux__0 = i_ux; +assign uy__0 = i_uy; +assign uz__0 = i_uz; +assign sz__0 = i_sz; +assign sr__0 = i_sr; +assign sleftz__0 = i_sleftz; +assign sleftr__0 = i_sleftr; +assign weight__0 = i_weight; +assign layer__0 = i_layer; +assign dead__0 = i_dead; +assign hit__0 = i_hit; + +//ASSIGNMENTS FROM PIPE TO OUTPUT +//TODO: Assign outputs from the correct module +assign o_x =x__37; +assign o_y =y__37; +assign o_z =z__37; +//assign o_ux =ux[PIPE_DEPTH]; Assigned by deadOrAliveMux +//assign o_uy =uy[PIPE_DEPTH]; Assigned by deadOrAliveMux +//assign o_uz =uz[PIPE_DEPTH]; Assigned by deadOrAliveMux +assign o_sz =sz__37; +assign o_sr =sr__37; +assign o_sleftz =sleftz__37; +assign o_sleftr =sleftr__37; +//assign o_weight =weight[PIPE_DEPTH]; Assigned by absorber module (below) +//assign o_layer =layer[PIPE_DEPTH]; Assigned by deadOrAliveMux +//assign o_dead =dead[PIPE_DEPTH]; Assigned by deadOrAliveMux +assign o_hit =hit__37; + + +//GENERATE PIPELINE +//genvar i; +//generate +// for(i=PIPE_DEPTH; i>0; i=i-1) begin: regPipe +// case(i) +// +// default: +// PhotonBlock5 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(x[i-1]), +// .i_y(y[i-1]), +// .i_z(z[i-1]), +// .i_ux(ux[i-1]), +// .i_uy(uy[i-1]), +// .i_uz(uz[i-1]), +// .i_sz(sz[i-1]), +// .i_sr(sr[i-1]), +// .i_sleftz(sleftz[i-1]), +// .i_sleftr(sleftr[i-1]), +// .i_weight(weight[i-1]), +// .i_layer(layer[i-1]), +// .i_dead(dead[i-1]), +// .i_hit(hit[i-1]), +// +// //Outputs +// .o_x(x[i]), +// .o_y(y[i]), +// .o_z(z[i]), +// .o_ux(ux[i]), +// .o_uy(uy[i]), +// .o_uz(uz[i]), +// .o_sz(sz[i]), +// .o_sr(sr[i]), +// .o_sleftz(sleftz[i]), +// .o_sleftr(sleftr[i]), +// .o_weight(weight[i]), +// .o_layer(layer[i]), +// .o_dead(dead[i]), +// .o_hit(hit[i]) +// ); +// endcase +// end +//endgenerate + +PhotonBlock5 photon37( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__36), +.i_y(y__36), +.i_z(z__36), +.i_ux(ux__36), +.i_uy(uy__36), +.i_uz(uz__36), +.i_sz(sz__36), +.i_sr(sr__36), +.i_sleftz(sleftz__36), +.i_sleftr(sleftr__36), +.i_weight(weight__36), +.i_layer(layer__36), +.i_dead(dead__36), +.i_hit(hit__36), +//Outputs +.o_x(x__37), +.o_y(y__37), +.o_z(z__37), +.o_ux(ux__37), +.o_uy(uy__37), +.o_uz(uz__37), +.o_sz(sz__37), +.o_sr(sr__37), +.o_sleftz(sleftz__37), +.o_sleftr(sleftr__37), +.o_weight(weight__37), +.o_layer(layer__37), +.o_dead(dead__37), +.o_hit(hit__37) +); +PhotonBlock5 photon36( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__35), +.i_y(y__35), +.i_z(z__35), +.i_ux(ux__35), +.i_uy(uy__35), +.i_uz(uz__35), +.i_sz(sz__35), +.i_sr(sr__35), +.i_sleftz(sleftz__35), +.i_sleftr(sleftr__35), +.i_weight(weight__35), +.i_layer(layer__35), +.i_dead(dead__35), +.i_hit(hit__35), +//Outputs +.o_x(x__36), +.o_y(y__36), +.o_z(z__36), +.o_ux(ux__36), +.o_uy(uy__36), +.o_uz(uz__36), +.o_sz(sz__36), +.o_sr(sr__36), +.o_sleftz(sleftz__36), +.o_sleftr(sleftr__36), +.o_weight(weight__36), +.o_layer(layer__36), +.o_dead(dead__36), +.o_hit(hit__36) +); +PhotonBlock5 photon35( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__34), +.i_y(y__34), +.i_z(z__34), +.i_ux(ux__34), +.i_uy(uy__34), +.i_uz(uz__34), +.i_sz(sz__34), +.i_sr(sr__34), +.i_sleftz(sleftz__34), +.i_sleftr(sleftr__34), +.i_weight(weight__34), +.i_layer(layer__34), +.i_dead(dead__34), +.i_hit(hit__34), +//Outputs +.o_x(x__35), +.o_y(y__35), +.o_z(z__35), +.o_ux(ux__35), +.o_uy(uy__35), +.o_uz(uz__35), +.o_sz(sz__35), +.o_sr(sr__35), +.o_sleftz(sleftz__35), +.o_sleftr(sleftr__35), +.o_weight(weight__35), +.o_layer(layer__35), +.o_dead(dead__35), +.o_hit(hit__35) +); +PhotonBlock5 photon34( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__33), +.i_y(y__33), +.i_z(z__33), +.i_ux(ux__33), +.i_uy(uy__33), +.i_uz(uz__33), +.i_sz(sz__33), +.i_sr(sr__33), +.i_sleftz(sleftz__33), +.i_sleftr(sleftr__33), +.i_weight(weight__33), +.i_layer(layer__33), +.i_dead(dead__33), +.i_hit(hit__33), +//Outputs +.o_x(x__34), +.o_y(y__34), +.o_z(z__34), +.o_ux(ux__34), +.o_uy(uy__34), +.o_uz(uz__34), +.o_sz(sz__34), +.o_sr(sr__34), +.o_sleftz(sleftz__34), +.o_sleftr(sleftr__34), +.o_weight(weight__34), +.o_layer(layer__34), +.o_dead(dead__34), +.o_hit(hit__34) +); +PhotonBlock5 photon33( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__32), +.i_y(y__32), +.i_z(z__32), +.i_ux(ux__32), +.i_uy(uy__32), +.i_uz(uz__32), +.i_sz(sz__32), +.i_sr(sr__32), +.i_sleftz(sleftz__32), +.i_sleftr(sleftr__32), +.i_weight(weight__32), +.i_layer(layer__32), +.i_dead(dead__32), +.i_hit(hit__32), +//Outputs +.o_x(x__33), +.o_y(y__33), +.o_z(z__33), +.o_ux(ux__33), +.o_uy(uy__33), +.o_uz(uz__33), +.o_sz(sz__33), +.o_sr(sr__33), +.o_sleftz(sleftz__33), +.o_sleftr(sleftr__33), +.o_weight(weight__33), +.o_layer(layer__33), +.o_dead(dead__33), +.o_hit(hit__33) +); +PhotonBlock5 photon32( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__31), +.i_y(y__31), +.i_z(z__31), +.i_ux(ux__31), +.i_uy(uy__31), +.i_uz(uz__31), +.i_sz(sz__31), +.i_sr(sr__31), +.i_sleftz(sleftz__31), +.i_sleftr(sleftr__31), +.i_weight(weight__31), +.i_layer(layer__31), +.i_dead(dead__31), +.i_hit(hit__31), +//Outputs +.o_x(x__32), +.o_y(y__32), +.o_z(z__32), +.o_ux(ux__32), +.o_uy(uy__32), +.o_uz(uz__32), +.o_sz(sz__32), +.o_sr(sr__32), +.o_sleftz(sleftz__32), +.o_sleftr(sleftr__32), +.o_weight(weight__32), +.o_layer(layer__32), +.o_dead(dead__32), +.o_hit(hit__32) +); +PhotonBlock5 photon31( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__30), +.i_y(y__30), +.i_z(z__30), +.i_ux(ux__30), +.i_uy(uy__30), +.i_uz(uz__30), +.i_sz(sz__30), +.i_sr(sr__30), +.i_sleftz(sleftz__30), +.i_sleftr(sleftr__30), +.i_weight(weight__30), +.i_layer(layer__30), +.i_dead(dead__30), +.i_hit(hit__30), +//Outputs +.o_x(x__31), +.o_y(y__31), +.o_z(z__31), +.o_ux(ux__31), +.o_uy(uy__31), +.o_uz(uz__31), +.o_sz(sz__31), +.o_sr(sr__31), +.o_sleftz(sleftz__31), +.o_sleftr(sleftr__31), +.o_weight(weight__31), +.o_layer(layer__31), +.o_dead(dead__31), +.o_hit(hit__31) +); +PhotonBlock5 photon30( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__29), +.i_y(y__29), +.i_z(z__29), +.i_ux(ux__29), +.i_uy(uy__29), +.i_uz(uz__29), +.i_sz(sz__29), +.i_sr(sr__29), +.i_sleftz(sleftz__29), +.i_sleftr(sleftr__29), +.i_weight(weight__29), +.i_layer(layer__29), +.i_dead(dead__29), +.i_hit(hit__29), +//Outputs +.o_x(x__30), +.o_y(y__30), +.o_z(z__30), +.o_ux(ux__30), +.o_uy(uy__30), +.o_uz(uz__30), +.o_sz(sz__30), +.o_sr(sr__30), +.o_sleftz(sleftz__30), +.o_sleftr(sleftr__30), +.o_weight(weight__30), +.o_layer(layer__30), +.o_dead(dead__30), +.o_hit(hit__30) +); +PhotonBlock5 photon29( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__28), +.i_y(y__28), +.i_z(z__28), +.i_ux(ux__28), +.i_uy(uy__28), +.i_uz(uz__28), +.i_sz(sz__28), +.i_sr(sr__28), +.i_sleftz(sleftz__28), +.i_sleftr(sleftr__28), +.i_weight(weight__28), +.i_layer(layer__28), +.i_dead(dead__28), +.i_hit(hit__28), +//Outputs +.o_x(x__29), +.o_y(y__29), +.o_z(z__29), +.o_ux(ux__29), +.o_uy(uy__29), +.o_uz(uz__29), +.o_sz(sz__29), +.o_sr(sr__29), +.o_sleftz(sleftz__29), +.o_sleftr(sleftr__29), +.o_weight(weight__29), +.o_layer(layer__29), +.o_dead(dead__29), +.o_hit(hit__29) +); +PhotonBlock5 photon28( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__27), +.i_y(y__27), +.i_z(z__27), +.i_ux(ux__27), +.i_uy(uy__27), +.i_uz(uz__27), +.i_sz(sz__27), +.i_sr(sr__27), +.i_sleftz(sleftz__27), +.i_sleftr(sleftr__27), +.i_weight(weight__27), +.i_layer(layer__27), +.i_dead(dead__27), +.i_hit(hit__27), +//Outputs +.o_x(x__28), +.o_y(y__28), +.o_z(z__28), +.o_ux(ux__28), +.o_uy(uy__28), +.o_uz(uz__28), +.o_sz(sz__28), +.o_sr(sr__28), +.o_sleftz(sleftz__28), +.o_sleftr(sleftr__28), +.o_weight(weight__28), +.o_layer(layer__28), +.o_dead(dead__28), +.o_hit(hit__28) +); +PhotonBlock5 photon27( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__26), +.i_y(y__26), +.i_z(z__26), +.i_ux(ux__26), +.i_uy(uy__26), +.i_uz(uz__26), +.i_sz(sz__26), +.i_sr(sr__26), +.i_sleftz(sleftz__26), +.i_sleftr(sleftr__26), +.i_weight(weight__26), +.i_layer(layer__26), +.i_dead(dead__26), +.i_hit(hit__26), +//Outputs +.o_x(x__27), +.o_y(y__27), +.o_z(z__27), +.o_ux(ux__27), +.o_uy(uy__27), +.o_uz(uz__27), +.o_sz(sz__27), +.o_sr(sr__27), +.o_sleftz(sleftz__27), +.o_sleftr(sleftr__27), +.o_weight(weight__27), +.o_layer(layer__27), +.o_dead(dead__27), +.o_hit(hit__27) +); +PhotonBlock5 photon26( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__25), +.i_y(y__25), +.i_z(z__25), +.i_ux(ux__25), +.i_uy(uy__25), +.i_uz(uz__25), +.i_sz(sz__25), +.i_sr(sr__25), +.i_sleftz(sleftz__25), +.i_sleftr(sleftr__25), +.i_weight(weight__25), +.i_layer(layer__25), +.i_dead(dead__25), +.i_hit(hit__25), +//Outputs +.o_x(x__26), +.o_y(y__26), +.o_z(z__26), +.o_ux(ux__26), +.o_uy(uy__26), +.o_uz(uz__26), +.o_sz(sz__26), +.o_sr(sr__26), +.o_sleftz(sleftz__26), +.o_sleftr(sleftr__26), +.o_weight(weight__26), +.o_layer(layer__26), +.o_dead(dead__26), +.o_hit(hit__26) +); +PhotonBlock5 photon25( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__24), +.i_y(y__24), +.i_z(z__24), +.i_ux(ux__24), +.i_uy(uy__24), +.i_uz(uz__24), +.i_sz(sz__24), +.i_sr(sr__24), +.i_sleftz(sleftz__24), +.i_sleftr(sleftr__24), +.i_weight(weight__24), +.i_layer(layer__24), +.i_dead(dead__24), +.i_hit(hit__24), +//Outputs +.o_x(x__25), +.o_y(y__25), +.o_z(z__25), +.o_ux(ux__25), +.o_uy(uy__25), +.o_uz(uz__25), +.o_sz(sz__25), +.o_sr(sr__25), +.o_sleftz(sleftz__25), +.o_sleftr(sleftr__25), +.o_weight(weight__25), +.o_layer(layer__25), +.o_dead(dead__25), +.o_hit(hit__25) +); +PhotonBlock5 photon24( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__23), +.i_y(y__23), +.i_z(z__23), +.i_ux(ux__23), +.i_uy(uy__23), +.i_uz(uz__23), +.i_sz(sz__23), +.i_sr(sr__23), +.i_sleftz(sleftz__23), +.i_sleftr(sleftr__23), +.i_weight(weight__23), +.i_layer(layer__23), +.i_dead(dead__23), +.i_hit(hit__23), +//Outputs +.o_x(x__24), +.o_y(y__24), +.o_z(z__24), +.o_ux(ux__24), +.o_uy(uy__24), +.o_uz(uz__24), +.o_sz(sz__24), +.o_sr(sr__24), +.o_sleftz(sleftz__24), +.o_sleftr(sleftr__24), +.o_weight(weight__24), +.o_layer(layer__24), +.o_dead(dead__24), +.o_hit(hit__24) +); +PhotonBlock5 photon23( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__22), +.i_y(y__22), +.i_z(z__22), +.i_ux(ux__22), +.i_uy(uy__22), +.i_uz(uz__22), +.i_sz(sz__22), +.i_sr(sr__22), +.i_sleftz(sleftz__22), +.i_sleftr(sleftr__22), +.i_weight(weight__22), +.i_layer(layer__22), +.i_dead(dead__22), +.i_hit(hit__22), +//Outputs +.o_x(x__23), +.o_y(y__23), +.o_z(z__23), +.o_ux(ux__23), +.o_uy(uy__23), +.o_uz(uz__23), +.o_sz(sz__23), +.o_sr(sr__23), +.o_sleftz(sleftz__23), +.o_sleftr(sleftr__23), +.o_weight(weight__23), +.o_layer(layer__23), +.o_dead(dead__23), +.o_hit(hit__23) +); +PhotonBlock5 photon22( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__21), +.i_y(y__21), +.i_z(z__21), +.i_ux(ux__21), +.i_uy(uy__21), +.i_uz(uz__21), +.i_sz(sz__21), +.i_sr(sr__21), +.i_sleftz(sleftz__21), +.i_sleftr(sleftr__21), +.i_weight(weight__21), +.i_layer(layer__21), +.i_dead(dead__21), +.i_hit(hit__21), +//Outputs +.o_x(x__22), +.o_y(y__22), +.o_z(z__22), +.o_ux(ux__22), +.o_uy(uy__22), +.o_uz(uz__22), +.o_sz(sz__22), +.o_sr(sr__22), +.o_sleftz(sleftz__22), +.o_sleftr(sleftr__22), +.o_weight(weight__22), +.o_layer(layer__22), +.o_dead(dead__22), +.o_hit(hit__22) +); +PhotonBlock5 photon21( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__20), +.i_y(y__20), +.i_z(z__20), +.i_ux(ux__20), +.i_uy(uy__20), +.i_uz(uz__20), +.i_sz(sz__20), +.i_sr(sr__20), +.i_sleftz(sleftz__20), +.i_sleftr(sleftr__20), +.i_weight(weight__20), +.i_layer(layer__20), +.i_dead(dead__20), +.i_hit(hit__20), +//Outputs +.o_x(x__21), +.o_y(y__21), +.o_z(z__21), +.o_ux(ux__21), +.o_uy(uy__21), +.o_uz(uz__21), +.o_sz(sz__21), +.o_sr(sr__21), +.o_sleftz(sleftz__21), +.o_sleftr(sleftr__21), +.o_weight(weight__21), +.o_layer(layer__21), +.o_dead(dead__21), +.o_hit(hit__21) +); +PhotonBlock5 photon20( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__19), +.i_y(y__19), +.i_z(z__19), +.i_ux(ux__19), +.i_uy(uy__19), +.i_uz(uz__19), +.i_sz(sz__19), +.i_sr(sr__19), +.i_sleftz(sleftz__19), +.i_sleftr(sleftr__19), +.i_weight(weight__19), +.i_layer(layer__19), +.i_dead(dead__19), +.i_hit(hit__19), +//Outputs +.o_x(x__20), +.o_y(y__20), +.o_z(z__20), +.o_ux(ux__20), +.o_uy(uy__20), +.o_uz(uz__20), +.o_sz(sz__20), +.o_sr(sr__20), +.o_sleftz(sleftz__20), +.o_sleftr(sleftr__20), +.o_weight(weight__20), +.o_layer(layer__20), +.o_dead(dead__20), +.o_hit(hit__20) +); +PhotonBlock5 photon19( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__18), +.i_y(y__18), +.i_z(z__18), +.i_ux(ux__18), +.i_uy(uy__18), +.i_uz(uz__18), +.i_sz(sz__18), +.i_sr(sr__18), +.i_sleftz(sleftz__18), +.i_sleftr(sleftr__18), +.i_weight(weight__18), +.i_layer(layer__18), +.i_dead(dead__18), +.i_hit(hit__18), +//Outputs +.o_x(x__19), +.o_y(y__19), +.o_z(z__19), +.o_ux(ux__19), +.o_uy(uy__19), +.o_uz(uz__19), +.o_sz(sz__19), +.o_sr(sr__19), +.o_sleftz(sleftz__19), +.o_sleftr(sleftr__19), +.o_weight(weight__19), +.o_layer(layer__19), +.o_dead(dead__19), +.o_hit(hit__19) +); +PhotonBlock5 photon18( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__17), +.i_y(y__17), +.i_z(z__17), +.i_ux(ux__17), +.i_uy(uy__17), +.i_uz(uz__17), +.i_sz(sz__17), +.i_sr(sr__17), +.i_sleftz(sleftz__17), +.i_sleftr(sleftr__17), +.i_weight(weight__17), +.i_layer(layer__17), +.i_dead(dead__17), +.i_hit(hit__17), +//Outputs +.o_x(x__18), +.o_y(y__18), +.o_z(z__18), +.o_ux(ux__18), +.o_uy(uy__18), +.o_uz(uz__18), +.o_sz(sz__18), +.o_sr(sr__18), +.o_sleftz(sleftz__18), +.o_sleftr(sleftr__18), +.o_weight(weight__18), +.o_layer(layer__18), +.o_dead(dead__18), +.o_hit(hit__18) +); +PhotonBlock5 photon17( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__16), +.i_y(y__16), +.i_z(z__16), +.i_ux(ux__16), +.i_uy(uy__16), +.i_uz(uz__16), +.i_sz(sz__16), +.i_sr(sr__16), +.i_sleftz(sleftz__16), +.i_sleftr(sleftr__16), +.i_weight(weight__16), +.i_layer(layer__16), +.i_dead(dead__16), +.i_hit(hit__16), +//Outputs +.o_x(x__17), +.o_y(y__17), +.o_z(z__17), +.o_ux(ux__17), +.o_uy(uy__17), +.o_uz(uz__17), +.o_sz(sz__17), +.o_sr(sr__17), +.o_sleftz(sleftz__17), +.o_sleftr(sleftr__17), +.o_weight(weight__17), +.o_layer(layer__17), +.o_dead(dead__17), +.o_hit(hit__17) +); +PhotonBlock5 photon16( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__15), +.i_y(y__15), +.i_z(z__15), +.i_ux(ux__15), +.i_uy(uy__15), +.i_uz(uz__15), +.i_sz(sz__15), +.i_sr(sr__15), +.i_sleftz(sleftz__15), +.i_sleftr(sleftr__15), +.i_weight(weight__15), +.i_layer(layer__15), +.i_dead(dead__15), +.i_hit(hit__15), +//Outputs +.o_x(x__16), +.o_y(y__16), +.o_z(z__16), +.o_ux(ux__16), +.o_uy(uy__16), +.o_uz(uz__16), +.o_sz(sz__16), +.o_sr(sr__16), +.o_sleftz(sleftz__16), +.o_sleftr(sleftr__16), +.o_weight(weight__16), +.o_layer(layer__16), +.o_dead(dead__16), +.o_hit(hit__16) +); +PhotonBlock5 photon15( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__14), +.i_y(y__14), +.i_z(z__14), +.i_ux(ux__14), +.i_uy(uy__14), +.i_uz(uz__14), +.i_sz(sz__14), +.i_sr(sr__14), +.i_sleftz(sleftz__14), +.i_sleftr(sleftr__14), +.i_weight(weight__14), +.i_layer(layer__14), +.i_dead(dead__14), +.i_hit(hit__14), +//Outputs +.o_x(x__15), +.o_y(y__15), +.o_z(z__15), +.o_ux(ux__15), +.o_uy(uy__15), +.o_uz(uz__15), +.o_sz(sz__15), +.o_sr(sr__15), +.o_sleftz(sleftz__15), +.o_sleftr(sleftr__15), +.o_weight(weight__15), +.o_layer(layer__15), +.o_dead(dead__15), +.o_hit(hit__15) +); +PhotonBlock5 photon14( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__13), +.i_y(y__13), +.i_z(z__13), +.i_ux(ux__13), +.i_uy(uy__13), +.i_uz(uz__13), +.i_sz(sz__13), +.i_sr(sr__13), +.i_sleftz(sleftz__13), +.i_sleftr(sleftr__13), +.i_weight(weight__13), +.i_layer(layer__13), +.i_dead(dead__13), +.i_hit(hit__13), +//Outputs +.o_x(x__14), +.o_y(y__14), +.o_z(z__14), +.o_ux(ux__14), +.o_uy(uy__14), +.o_uz(uz__14), +.o_sz(sz__14), +.o_sr(sr__14), +.o_sleftz(sleftz__14), +.o_sleftr(sleftr__14), +.o_weight(weight__14), +.o_layer(layer__14), +.o_dead(dead__14), +.o_hit(hit__14) +); +PhotonBlock5 photon13( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__12), +.i_y(y__12), +.i_z(z__12), +.i_ux(ux__12), +.i_uy(uy__12), +.i_uz(uz__12), +.i_sz(sz__12), +.i_sr(sr__12), +.i_sleftz(sleftz__12), +.i_sleftr(sleftr__12), +.i_weight(weight__12), +.i_layer(layer__12), +.i_dead(dead__12), +.i_hit(hit__12), +//Outputs +.o_x(x__13), +.o_y(y__13), +.o_z(z__13), +.o_ux(ux__13), +.o_uy(uy__13), +.o_uz(uz__13), +.o_sz(sz__13), +.o_sr(sr__13), +.o_sleftz(sleftz__13), +.o_sleftr(sleftr__13), +.o_weight(weight__13), +.o_layer(layer__13), +.o_dead(dead__13), +.o_hit(hit__13) +); +PhotonBlock5 photon12( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__11), +.i_y(y__11), +.i_z(z__11), +.i_ux(ux__11), +.i_uy(uy__11), +.i_uz(uz__11), +.i_sz(sz__11), +.i_sr(sr__11), +.i_sleftz(sleftz__11), +.i_sleftr(sleftr__11), +.i_weight(weight__11), +.i_layer(layer__11), +.i_dead(dead__11), +.i_hit(hit__11), +//Outputs +.o_x(x__12), +.o_y(y__12), +.o_z(z__12), +.o_ux(ux__12), +.o_uy(uy__12), +.o_uz(uz__12), +.o_sz(sz__12), +.o_sr(sr__12), +.o_sleftz(sleftz__12), +.o_sleftr(sleftr__12), +.o_weight(weight__12), +.o_layer(layer__12), +.o_dead(dead__12), +.o_hit(hit__12) +); +PhotonBlock5 photon11( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__10), +.i_y(y__10), +.i_z(z__10), +.i_ux(ux__10), +.i_uy(uy__10), +.i_uz(uz__10), +.i_sz(sz__10), +.i_sr(sr__10), +.i_sleftz(sleftz__10), +.i_sleftr(sleftr__10), +.i_weight(weight__10), +.i_layer(layer__10), +.i_dead(dead__10), +.i_hit(hit__10), +//Outputs +.o_x(x__11), +.o_y(y__11), +.o_z(z__11), +.o_ux(ux__11), +.o_uy(uy__11), +.o_uz(uz__11), +.o_sz(sz__11), +.o_sr(sr__11), +.o_sleftz(sleftz__11), +.o_sleftr(sleftr__11), +.o_weight(weight__11), +.o_layer(layer__11), +.o_dead(dead__11), +.o_hit(hit__11) +); +PhotonBlock5 photon10( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__9), +.i_y(y__9), +.i_z(z__9), +.i_ux(ux__9), +.i_uy(uy__9), +.i_uz(uz__9), +.i_sz(sz__9), +.i_sr(sr__9), +.i_sleftz(sleftz__9), +.i_sleftr(sleftr__9), +.i_weight(weight__9), +.i_layer(layer__9), +.i_dead(dead__9), +.i_hit(hit__9), +//Outputs +.o_x(x__10), +.o_y(y__10), +.o_z(z__10), +.o_ux(ux__10), +.o_uy(uy__10), +.o_uz(uz__10), +.o_sz(sz__10), +.o_sr(sr__10), +.o_sleftz(sleftz__10), +.o_sleftr(sleftr__10), +.o_weight(weight__10), +.o_layer(layer__10), +.o_dead(dead__10), +.o_hit(hit__10) +); +PhotonBlock5 photon9( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__8), +.i_y(y__8), +.i_z(z__8), +.i_ux(ux__8), +.i_uy(uy__8), +.i_uz(uz__8), +.i_sz(sz__8), +.i_sr(sr__8), +.i_sleftz(sleftz__8), +.i_sleftr(sleftr__8), +.i_weight(weight__8), +.i_layer(layer__8), +.i_dead(dead__8), +.i_hit(hit__8), +//Outputs +.o_x(x__9), +.o_y(y__9), +.o_z(z__9), +.o_ux(ux__9), +.o_uy(uy__9), +.o_uz(uz__9), +.o_sz(sz__9), +.o_sr(sr__9), +.o_sleftz(sleftz__9), +.o_sleftr(sleftr__9), +.o_weight(weight__9), +.o_layer(layer__9), +.o_dead(dead__9), +.o_hit(hit__9) +); +PhotonBlock5 photon8( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__7), +.i_y(y__7), +.i_z(z__7), +.i_ux(ux__7), +.i_uy(uy__7), +.i_uz(uz__7), +.i_sz(sz__7), +.i_sr(sr__7), +.i_sleftz(sleftz__7), +.i_sleftr(sleftr__7), +.i_weight(weight__7), +.i_layer(layer__7), +.i_dead(dead__7), +.i_hit(hit__7), +//Outputs +.o_x(x__8), +.o_y(y__8), +.o_z(z__8), +.o_ux(ux__8), +.o_uy(uy__8), +.o_uz(uz__8), +.o_sz(sz__8), +.o_sr(sr__8), +.o_sleftz(sleftz__8), +.o_sleftr(sleftr__8), +.o_weight(weight__8), +.o_layer(layer__8), +.o_dead(dead__8), +.o_hit(hit__8) +); +PhotonBlock5 photon7( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__6), +.i_y(y__6), +.i_z(z__6), +.i_ux(ux__6), +.i_uy(uy__6), +.i_uz(uz__6), +.i_sz(sz__6), +.i_sr(sr__6), +.i_sleftz(sleftz__6), +.i_sleftr(sleftr__6), +.i_weight(weight__6), +.i_layer(layer__6), +.i_dead(dead__6), +.i_hit(hit__6), +//Outputs +.o_x(x__7), +.o_y(y__7), +.o_z(z__7), +.o_ux(ux__7), +.o_uy(uy__7), +.o_uz(uz__7), +.o_sz(sz__7), +.o_sr(sr__7), +.o_sleftz(sleftz__7), +.o_sleftr(sleftr__7), +.o_weight(weight__7), +.o_layer(layer__7), +.o_dead(dead__7), +.o_hit(hit__7) +); +PhotonBlock5 photon6( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__5), +.i_y(y__5), +.i_z(z__5), +.i_ux(ux__5), +.i_uy(uy__5), +.i_uz(uz__5), +.i_sz(sz__5), +.i_sr(sr__5), +.i_sleftz(sleftz__5), +.i_sleftr(sleftr__5), +.i_weight(weight__5), +.i_layer(layer__5), +.i_dead(dead__5), +.i_hit(hit__5), +//Outputs +.o_x(x__6), +.o_y(y__6), +.o_z(z__6), +.o_ux(ux__6), +.o_uy(uy__6), +.o_uz(uz__6), +.o_sz(sz__6), +.o_sr(sr__6), +.o_sleftz(sleftz__6), +.o_sleftr(sleftr__6), +.o_weight(weight__6), +.o_layer(layer__6), +.o_dead(dead__6), +.o_hit(hit__6) +); +PhotonBlock5 photon5( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__4), +.i_y(y__4), +.i_z(z__4), +.i_ux(ux__4), +.i_uy(uy__4), +.i_uz(uz__4), +.i_sz(sz__4), +.i_sr(sr__4), +.i_sleftz(sleftz__4), +.i_sleftr(sleftr__4), +.i_weight(weight__4), +.i_layer(layer__4), +.i_dead(dead__4), +.i_hit(hit__4), +//Outputs +.o_x(x__5), +.o_y(y__5), +.o_z(z__5), +.o_ux(ux__5), +.o_uy(uy__5), +.o_uz(uz__5), +.o_sz(sz__5), +.o_sr(sr__5), +.o_sleftz(sleftz__5), +.o_sleftr(sleftr__5), +.o_weight(weight__5), +.o_layer(layer__5), +.o_dead(dead__5), +.o_hit(hit__5) +); +PhotonBlock5 photon4( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__3), +.i_y(y__3), +.i_z(z__3), +.i_ux(ux__3), +.i_uy(uy__3), +.i_uz(uz__3), +.i_sz(sz__3), +.i_sr(sr__3), +.i_sleftz(sleftz__3), +.i_sleftr(sleftr__3), +.i_weight(weight__3), +.i_layer(layer__3), +.i_dead(dead__3), +.i_hit(hit__3), +//Outputs +.o_x(x__4), +.o_y(y__4), +.o_z(z__4), +.o_ux(ux__4), +.o_uy(uy__4), +.o_uz(uz__4), +.o_sz(sz__4), +.o_sr(sr__4), +.o_sleftz(sleftz__4), +.o_sleftr(sleftr__4), +.o_weight(weight__4), +.o_layer(layer__4), +.o_dead(dead__4), +.o_hit(hit__4) +); +PhotonBlock5 photon3( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__2), +.i_y(y__2), +.i_z(z__2), +.i_ux(ux__2), +.i_uy(uy__2), +.i_uz(uz__2), +.i_sz(sz__2), +.i_sr(sr__2), +.i_sleftz(sleftz__2), +.i_sleftr(sleftr__2), +.i_weight(weight__2), +.i_layer(layer__2), +.i_dead(dead__2), +.i_hit(hit__2), +//Outputs +.o_x(x__3), +.o_y(y__3), +.o_z(z__3), +.o_ux(ux__3), +.o_uy(uy__3), +.o_uz(uz__3), +.o_sz(sz__3), +.o_sr(sr__3), +.o_sleftz(sleftz__3), +.o_sleftr(sleftr__3), +.o_weight(weight__3), +.o_layer(layer__3), +.o_dead(dead__3), +.o_hit(hit__3) +); +PhotonBlock5 photon2( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__1), +.i_y(y__1), +.i_z(z__1), +.i_ux(ux__1), +.i_uy(uy__1), +.i_uz(uz__1), +.i_sz(sz__1), +.i_sr(sr__1), +.i_sleftz(sleftz__1), +.i_sleftr(sleftr__1), +.i_weight(weight__1), +.i_layer(layer__1), +.i_dead(dead__1), +.i_hit(hit__1), +//Outputs +.o_x(x__2), +.o_y(y__2), +.o_z(z__2), +.o_ux(ux__2), +.o_uy(uy__2), +.o_uz(uz__2), +.o_sz(sz__2), +.o_sr(sr__2), +.o_sleftz(sleftz__2), +.o_sleftr(sleftr__2), +.o_weight(weight__2), +.o_layer(layer__2), +.o_dead(dead__2), +.o_hit(hit__2) +); +PhotonBlock5 photon1( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(x__0), +.i_y(y__0), +.i_z(z__0), +.i_ux(ux__0), +.i_uy(uy__0), +.i_uz(uz__0), +.i_sz(sz__0), +.i_sr(sr__0), +.i_sleftz(sleftz__0), +.i_sleftr(sleftr__0), +.i_weight(weight__0), +.i_layer(layer__0), +.i_dead(dead__0), +.i_hit(hit__0), +//Outputs +.o_x(x__1), +.o_y(y__1), +.o_z(z__1), +.o_ux(ux__1), +.o_uy(uy__1), +.o_uz(uz__1), +.o_sz(sz__1), +.o_sr(sr__1), +.o_sleftz(sleftz__1), +.o_sleftr(sleftr__1), +.o_weight(weight__1), +.o_layer(layer__1), +.o_dead(dead__1), +.o_hit(hit__1) +); + + + +////////////////////////////////////////////////////////////////////////////// +//Tapping into the Registered Pipeline +//***NOTE: Index must be incremented by 1 compared to SystemC version +////////////////////////////////////////////////////////////////////////////// + +//>>>>>>>>>>>>> Absorber <<<<<<<<<<<<<<<<<< +wire [`BIT_WIDTH-1:0] x_pipe, y_pipe, z_pipe; +wire [`LAYER_WIDTH-1:0] layer_pipe; +assign x_pipe=x__2; +assign y_pipe=y__2; +assign z_pipe=z__14; //TODO: Check square-root latency and modify z[14] if needed!!!! +assign layer_pipe=layer__4; + +//>>>>>>>>>>>>> ScattererReflectorWrapper <<<<<<<<<<<<<<<<<< +wire [`BIT_WIDTH-1:0] ux_scatterer; +wire [`BIT_WIDTH-1:0] uy_scatterer; +wire [`BIT_WIDTH-1:0] uz_scatterer; +wire [`BIT_WIDTH-1:0] ux_reflector; +wire [`BIT_WIDTH-1:0] uy_reflector; +wire [`BIT_WIDTH-1:0] uz_reflector; +wire [`LAYER_WIDTH-1:0] layer_reflector; +wire dead_reflector; + + + + +////////////////////////////////////////////////////////////////////////////// +//Connect up different modules +////////////////////////////////////////////////////////////////////////////// + +//>>>>>>>>>>>>> Absorber <<<<<<<<<<<<<<<<<< + +Absorber absorb ( //INPUTS + .clock(clock) , .reset(reset), .enable(enable), + + //From hopper + .weight_hop(i_weight), .hit_hop(i_hit), .dead_hop(i_dead), + + //From Shared Registers + .x_pipe (x_pipe), .y_pipe (y_pipe), .z_pipe(z_pipe), .layer_pipe(layer_pipe), + + //From System Register File (5 layers) + .muaFraction1(muaFraction1), .muaFraction2(muaFraction2), .muaFraction3(muaFraction3), .muaFraction4(muaFraction4), .muaFraction5(muaFraction5), + + //Dual-port Mem + .data(data), .rdaddress(rdaddress), .wraddress(wraddress), + .wren(wren), .q(q), + + //OUTPUT + .weight_absorber(o_weight) + + ); + +//>>>>>>>>>>>>> ScattererReflectorWrapper <<<<<<<<<<<<<<<<<< + +ScattererReflectorWrapper scattererReflector( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + //Inputs + + //Photon values + .i_uz1_pipeWrapper(uz__1), + .i_hit2_pipeWrapper(hit__1), + .i_ux3_pipeWrapper(ux__3), + .i_uz3_pipeWrapper(uz__3), + .i_layer3_pipeWrapper(layer__3), + .i_hit4_pipeWrapper(hit__3), + .i_hit6_pipeWrapper(hit__5), + .i_hit16_pipeWrapper(hit__15), + .i_layer31_pipeWrapper(layer__31), + .i_uy32_pipeWrapper(uy__32), + .i_uz32_pipeWrapper(uz__32), + .i_hit33_pipeWrapper(hit__32), + .i_ux33_pipeWrapper(ux__33), + .i_uy33_pipeWrapper(uy__33), + .i_hit34_pipeWrapper(hit__33), + .i_ux35_pipeWrapper(ux__35), + .i_uy35_pipeWrapper(uy__35), + .i_uz35_pipeWrapper(uz__35), + .i_layer35_pipeWrapper(layer__35), + .i_hit36_pipeWrapper(hit__35), + .i_ux36_pipeWrapper(ux__36), + .i_uy36_pipeWrapper(uy__36), + .i_uz36_pipeWrapper(uz__36), + .i_layer36_pipeWrapper(layer__36), + .i_dead36_pipeWrapper(dead__36), + + //Memory Interface + //Inputs + .rand2(rand2), + .rand3(rand3), + .rand5(rand5), + .sint(sint), + .cost(cost), + .up_rFresnel(up_rFresnel), + .down_rFresnel(down_rFresnel), + //Outputs + .tindex(tindex), + .fresIndex(fresIndex), + + //Constants + .down_niOverNt_1(down_niOverNt_1), + .down_niOverNt_2(down_niOverNt_2), + .down_niOverNt_3(down_niOverNt_3), + .down_niOverNt_4(down_niOverNt_4), + .down_niOverNt_5(down_niOverNt_5), + .up_niOverNt_1(up_niOverNt_1), + .up_niOverNt_2(up_niOverNt_2), + .up_niOverNt_3(up_niOverNt_3), + .up_niOverNt_4(up_niOverNt_4), + .up_niOverNt_5(up_niOverNt_5), + .down_niOverNt_2_1(down_niOverNt_2_1), + .down_niOverNt_2_2(down_niOverNt_2_2), + .down_niOverNt_2_3(down_niOverNt_2_3), + .down_niOverNt_2_4(down_niOverNt_2_4), + .down_niOverNt_2_5(down_niOverNt_2_5), + .up_niOverNt_2_1(up_niOverNt_2_1), + .up_niOverNt_2_2(up_niOverNt_2_2), + .up_niOverNt_2_3(up_niOverNt_2_3), + .up_niOverNt_2_4(up_niOverNt_2_4), + .up_niOverNt_2_5(up_niOverNt_2_5), + .downCritAngle_0(downCritAngle_0), + .downCritAngle_1(downCritAngle_1), + .downCritAngle_2(downCritAngle_2), + .downCritAngle_3(downCritAngle_3), + .downCritAngle_4(downCritAngle_4), + .upCritAngle_0(upCritAngle_0), + .upCritAngle_1(upCritAngle_1), + .upCritAngle_2(upCritAngle_2), + .upCritAngle_3(upCritAngle_3), + .upCritAngle_4(upCritAngle_4), + + //Outputs + .ux_scatterer(ux_scatterer), + .uy_scatterer(uy_scatterer), + .uz_scatterer(uz_scatterer), + + .ux_reflector(ux_reflector), + .uy_reflector(uy_reflector), + .uz_reflector(uz_reflector), + .layer_reflector(layer_reflector), + .dead_reflector(dead_reflector) + ); + + +////////////////////////////////////////////////////////////////////// +//// dead or alive MUX //// +//// //// +//// Description: //// +//// Used to determine whether the output from the scatterer //// +//// or the reflector should be used in any clock cycle //// +////////////////////////////////////////////////////////////////////// + +always @ (hit__37 or ux_scatterer or uy_scatterer or uz_scatterer or layer__37 or dead__37 or + ux_reflector or uy_reflector or uz_reflector or layer_reflector or dead_reflector) begin + case (hit__37) + 0: begin + o_ux = ux_scatterer; + o_uy = uy_scatterer; + o_uz = uz_scatterer; + o_layer = layer__37; + o_dead = dead__37; + end + 1: begin + o_ux = ux_reflector; + o_uy = uy_reflector; + o_uz = uz_reflector; + o_layer = layer_reflector; + o_dead = dead_reflector; + end + endcase + +end + +endmodule + +//Photons that make up the register pipeline +module PhotonBlock5( + //Inputs + clock, + reset, + enable, + + i_x, + i_y, + i_z, + i_ux, + i_uy, + i_uz, + i_sz, + i_sr, + i_sleftz, + i_sleftr, + i_weight, + i_layer, + i_dead, + i_hit, + //Outputs + o_x, + o_y, + o_z, + o_ux, + o_uy, + o_uz, + o_sz, + o_sr, + o_sleftz, + o_sleftr, + o_weight, + o_layer, + o_dead, + o_hit + ); + +//parameter BIT_WIDTH=32; +//parameter LAYER_WIDTH=3; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] i_x; +input [`BIT_WIDTH-1:0] i_y; +input [`BIT_WIDTH-1:0] i_z; +input [`BIT_WIDTH-1:0] i_ux; +input [`BIT_WIDTH-1:0] i_uy; +input [`BIT_WIDTH-1:0] i_uz; +input [`BIT_WIDTH-1:0] i_sz; +input [`BIT_WIDTH-1:0] i_sr; +input [`BIT_WIDTH-1:0] i_sleftz; +input [`BIT_WIDTH-1:0] i_sleftr; +input [`BIT_WIDTH-1:0] i_weight; +input [`LAYER_WIDTH-1:0] i_layer; +input i_dead; +input i_hit; + + +output [`BIT_WIDTH-1:0] o_x; +output [`BIT_WIDTH-1:0] o_y; +output [`BIT_WIDTH-1:0] o_z; +output [`BIT_WIDTH-1:0] o_ux; +output [`BIT_WIDTH-1:0] o_uy; +output [`BIT_WIDTH-1:0] o_uz; +output [`BIT_WIDTH-1:0] o_sz; +output [`BIT_WIDTH-1:0] o_sr; +output [`BIT_WIDTH-1:0] o_sleftz; +output [`BIT_WIDTH-1:0] o_sleftr; +output [`BIT_WIDTH-1:0] o_weight; +output [`LAYER_WIDTH-1:0] o_layer; +output o_dead; +output o_hit; + + +wire clock; +wire reset; +wire enable; + +wire [`BIT_WIDTH-1:0] i_x; +wire [`BIT_WIDTH-1:0] i_y; +wire [`BIT_WIDTH-1:0] i_z; +wire [`BIT_WIDTH-1:0] i_ux; +wire [`BIT_WIDTH-1:0] i_uy; +wire [`BIT_WIDTH-1:0] i_uz; +wire [`BIT_WIDTH-1:0] i_sz; +wire [`BIT_WIDTH-1:0] i_sr; +wire [`BIT_WIDTH-1:0] i_sleftz; +wire [`BIT_WIDTH-1:0] i_sleftr; +wire [`BIT_WIDTH-1:0] i_weight; +wire [`LAYER_WIDTH-1:0] i_layer; +wire i_dead; +wire i_hit; + + +reg [`BIT_WIDTH-1:0] o_x; +reg [`BIT_WIDTH-1:0] o_y; +reg [`BIT_WIDTH-1:0] o_z; +reg [`BIT_WIDTH-1:0] o_ux; +reg [`BIT_WIDTH-1:0] o_uy; +reg [`BIT_WIDTH-1:0] o_uz; +reg [`BIT_WIDTH-1:0] o_sz; +reg [`BIT_WIDTH-1:0] o_sr; +reg [`BIT_WIDTH-1:0] o_sleftz; +reg [`BIT_WIDTH-1:0] o_sleftr; +reg [`BIT_WIDTH-1:0] o_weight; +reg [`LAYER_WIDTH-1:0] o_layer; +reg o_dead; +reg o_hit; + + +always @ (posedge clock) + if(reset) begin + o_x <= {`BIT_WIDTH{1'b0}}; + o_y <= {`BIT_WIDTH{1'b0}}; + o_z <= {`BIT_WIDTH{1'b0}}; + o_ux <= {`BIT_WIDTH{1'b0}}; + o_uy <= {`BIT_WIDTH{1'b0}}; + o_uz <= {`BIT_WIDTH{1'b0}}; + o_sz <= {`BIT_WIDTH{1'b0}}; + o_sr <= {`BIT_WIDTH{1'b0}}; + o_sleftz <= {`BIT_WIDTH{1'b0}}; + o_sleftr <= {`BIT_WIDTH{1'b0}}; + o_weight <= {`BIT_WIDTH{1'b0}}; + o_layer <= {`LAYER_WIDTH{1'b0}}; + o_dead <= 1'b1; + o_hit <= 1'b0; + end else if(enable) begin + o_x <= i_x; + o_y <= i_y; + o_z <= i_z; + o_ux <= i_ux; + o_uy <= i_uy; + o_uz <= i_uz; + o_sz <= i_sz; + o_sr <= i_sr; + o_sleftz <= i_sleftz; + o_sleftr <= i_sleftr; + o_weight <= i_weight; + o_layer <= i_layer; + o_dead <= i_dead; + o_hit <= i_hit; + end +endmodule + + +//module FluenceUpdate ( //INPUTS +module Absorber ( //INPUTS + clock, reset, enable, + + //From hopper + weight_hop, hit_hop, dead_hop, + + //From Shared Registers + x_pipe, y_pipe, z_pipe, layer_pipe, + + //From System Register File (5 layers) + muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5, + + //I/O to on-chip mem -- check interface + data, rdaddress, wraddress, wren, q, + + //OUTPUT + weight_absorber + + ); + + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter `NR=256; +//parameter `NZ=256; +// +//parameter `NR_EXP=8; //meaning `NR=2^`NR_exp or 2^8=256 +//parameter `RGRID_SCLAE_EXP=21; //2^21 = RGRID_SCALE +//parameter `ZGRID_SCLAE_EXP=21; //2^21 = ZGRID_SCALE +// +// +//parameter `BIT_WIDTH=32; +//parameter `BIT_WIDTH_2=64; +//parameter `WORD_WIDTH=64; +//parameter `ADDR_WIDTH=16; //256x256=2^8*2^8=2^16 +// +// +//parameter `LAYER_WIDTH=3; +//parameter `PIPE_DEPTH = 37; + + +////////////////////////////////////////////////////////////////////////////// +//INPUTS +////////////////////////////////////////////////////////////////////////////// +input clock; +input reset; +input enable; + +//From hopper +input [`BIT_WIDTH-1:0] weight_hop; +input hit_hop; +input dead_hop; + +//From Shared Reg +//input signed [`BIT_WIDTH-1:0] x_pipe; +//input signed [`BIT_WIDTH-1:0] y_pipe; +input [`BIT_WIDTH-1:0] x_pipe; +input [`BIT_WIDTH-1:0] y_pipe; +input [`BIT_WIDTH-1:0] z_pipe; +input [`LAYER_WIDTH-1:0] layer_pipe; + +//From System Reg File +input [`BIT_WIDTH-1:0] muaFraction1, muaFraction2, muaFraction3, muaFraction4, muaFraction5; + +////////////////////////////////////////////////////////////////////////////// +//OUTPUTS +////////////////////////////////////////////////////////////////////////////// +output [`BIT_WIDTH-1:0] weight_absorber; + +////////////////////////////////////////////////////////////////////////////// +//I/O to on-chip mem -- check interface +////////////////////////////////////////////////////////////////////////////// +output [`WORD_WIDTH-1:0] data; +output [`ADDR_WIDTH-1:0] rdaddress, wraddress; +output wren; +reg wren; +input [`WORD_WIDTH-1:0] q; + +////////////////////////////////////////////////////////////////////////////// +//Local AND Registered Value Variables +////////////////////////////////////////////////////////////////////////////// +//STAGE 1 - Do nothing + +//STAGE 2 +reg [`BIT_WIDTH_2-1:0] x2_temp, y2_temp; //From mult +reg [`BIT_WIDTH_2-1:0] x2_P, y2_P; //Registered Value + +//STAGE 3 +reg [`BIT_WIDTH_2-1:0] r2_temp, r2_P; +wire [`BIT_WIDTH_2-1:0] r2_P_wire; + +//STAGE 4 +reg [`BIT_WIDTH-1:0] fractionScaled; +reg [`BIT_WIDTH-1:0] weight_P4; +reg [`BIT_WIDTH-1:0] r_P; +wire [`BIT_WIDTH-1:0] r_P_wire; + +reg [`BIT_WIDTH_2-1:0] product64bit; +reg [`BIT_WIDTH-1:0] dwa_temp; + +//STAGE 14 +reg [`BIT_WIDTH-1:0] ir_temp; +reg [`BIT_WIDTH-1:0] iz_temp; + +//STAGE 15 +reg [`BIT_WIDTH-1:0] ir_P; +reg [`BIT_WIDTH-1:0] iz_P; +reg [`BIT_WIDTH-1:0] ir_scaled; +reg [`ADDR_WIDTH-1:0] rADDR_temp; +reg [`ADDR_WIDTH-1:0] rADDR_16; + +//STAGE 16 +reg [`WORD_WIDTH-1:0] oldAbs_MEM; +reg [`WORD_WIDTH-1:0] oldAbs_P; +reg [`ADDR_WIDTH-1:0] rADDR_17; + +//STAGE 17 +reg [`BIT_WIDTH-1:0] weight_P; +reg [`BIT_WIDTH-1:0] dwa_P; +reg [`BIT_WIDTH-1:0] newWeight; + +reg [`WORD_WIDTH-1:0] newAbs_P; +reg [`WORD_WIDTH-1:0] newAbs_temp; + +//reg [`ADDR_WIDTH-1:0] wADDR; + + +////////////////////////////////////////////////////////////////////////////// +//PIPELINE weight, hit, dead +////////////////////////////////////////////////////////////////////////////// +//WIRES FOR CONNECTING REGISTERS + +//peter m made this manual +//wire [32-1:0] weight [37:0]; + +wire [32-1:0] weight__0; +wire [32-1:0] weight__1; +wire [32-1:0] weight__2; +wire [32-1:0] weight__3; +wire [32-1:0] weight__4; +wire [32-1:0] weight__5; +wire [32-1:0] weight__6; +wire [32-1:0] weight__7; +wire [32-1:0] weight__8; +wire [32-1:0] weight__9; +wire [32-1:0] weight__10; +wire [32-1:0] weight__11; +wire [32-1:0] weight__12; +wire [32-1:0] weight__13; +wire [32-1:0] weight__14; +wire [32-1:0] weight__15; +wire [32-1:0] weight__16; +wire [32-1:0] weight__17; +wire [32-1:0] weight__18; +wire [32-1:0] weight__19; +wire [32-1:0] weight__20; +wire [32-1:0] weight__21; +wire [32-1:0] weight__22; +wire [32-1:0] weight__23; +wire [32-1:0] weight__24; +wire [32-1:0] weight__25; +wire [32-1:0] weight__26; +wire [32-1:0] weight__27; +wire [32-1:0] weight__28; +wire [32-1:0] weight__29; +wire [32-1:0] weight__30; +wire [32-1:0] weight__31; +wire [32-1:0] weight__32; +wire [32-1:0] weight__33; +wire [32-1:0] weight__34; +wire [32-1:0] weight__35; +wire [32-1:0] weight__36; +wire [32-1:0] weight__37; + + +//wire [37:0] hit ; +wire hit__0; +wire hit__1; +wire hit__2; +wire hit__3; +wire hit__4; +wire hit__5; +wire hit__6; +wire hit__7; +wire hit__8; +wire hit__9; +wire hit__10; +wire hit__11; +wire hit__12; +wire hit__13; +wire hit__14; +wire hit__15; +wire hit__16; +wire hit__17; +wire hit__18; +wire hit__19; +wire hit__20; +wire hit__21; +wire hit__22; +wire hit__23; +wire hit__24; +wire hit__25; +wire hit__26; +wire hit__27; +wire hit__28; +wire hit__29; +wire hit__30; +wire hit__31; +wire hit__32; +wire hit__33; +wire hit__34; +wire hit__35; +wire hit__36; +wire hit__37; + + + +//wire [37:0] dead ; +wire dead__0; +wire dead__1; +wire dead__2; +wire dead__3; +wire dead__4; +wire dead__5; +wire dead__6; +wire dead__7; +wire dead__8; +wire dead__9; +wire dead__10; +wire dead__11; +wire dead__12; +wire dead__13; +wire dead__14; +wire dead__15; +wire dead__16; +wire dead__17; +wire dead__18; +wire dead__19; +wire dead__20; +wire dead__21; +wire dead__22; +wire dead__23; +wire dead__24; +wire dead__25; +wire dead__26; +wire dead__27; +wire dead__28; +wire dead__29; +wire dead__30; +wire dead__31; +wire dead__32; +wire dead__33; +wire dead__34; +wire dead__35; +wire dead__36; +wire dead__37; + + +//ASSIGNMENTS FROM INPUTS TO PIPE +assign weight__0 = weight_hop; +assign hit__0 = hit_hop; +assign dead__0 = dead_hop; + +//ASSIGNMENTS FROM PIPE TO OUTPUT +assign weight_absorber = weight__37; + +//GENERATE PIPELINE +//genvar i; +//generate +// for(i=`PIPE_DEPTH; i>0; i=i-1) begin: weightHitDeadPipe +// case(i) +// +// //REGISTER 17 on diagram!! +// 18: +// begin +// +// PhotonBlock2 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(newWeight), +// .i_y(hit[17]), +// .i_z(dead[17]), +// +// //Outputs +// .o_x(weight[18]), +// .o_y(hit[18]), +// .o_z(dead[18]) +// ); +// +// end +// default: +// begin +// PhotonBlock2 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(weight[i-1]), +// .i_y(hit[i-1]), +// .i_z(dead[i-1]), +// +// //Outputs +// .o_x(weight[i]), +// .o_y(hit[i]), +// .o_z(dead[i]) +// ); +// end +// endcase +// end +//endgenerate + +//Expand pipeline generation +//special case i = 18 first +PhotonBlock2 photon18( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_x(newWeight), + .i_y(hit__17), + .i_z(dead__17), + + //Outputs + .o_x(weight__18), + .o_y(hit__18), + .o_z(dead__18) + ); + +PhotonBlock2 photon37( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__36), +.i_y(hit__36), +.i_z(dead__36), +//Outputs + .o_x(weight__37), +.o_y(hit__37), +.o_z(dead__37) +); + +PhotonBlock2 photon36( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__35), +.i_y(hit__35), +.i_z(dead__35), +//Outputs + .o_x(weight__36), +.o_y(hit__36), +.o_z(dead__36) +); + +PhotonBlock2 photon35( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__34), +.i_y(hit__34), +.i_z(dead__34), +//Outputs + .o_x(weight__35), +.o_y(hit__35), +.o_z(dead__35) +); + +PhotonBlock2 photon34( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__33), +.i_y(hit__33), +.i_z(dead__33), +//Outputs + .o_x(weight__34), +.o_y(hit__34), +.o_z(dead__34) +); + +PhotonBlock2 photon33( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__32), +.i_y(hit__32), +.i_z(dead__32), +//Outputs + .o_x(weight__33), +.o_y(hit__33), +.o_z(dead__33) +); + +PhotonBlock2 photon32( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__31), +.i_y(hit__31), +.i_z(dead__31), +//Outputs + .o_x(weight__32), +.o_y(hit__32), +.o_z(dead__32) +); + +PhotonBlock2 photon31( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__30), +.i_y(hit__30), +.i_z(dead__30), +//Outputs + .o_x(weight__31), +.o_y(hit__31), +.o_z(dead__31) +); + +PhotonBlock2 photon30( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__29), +.i_y(hit__29), +.i_z(dead__29), +//Outputs + .o_x(weight__30), +.o_y(hit__30), +.o_z(dead__30) +); + +PhotonBlock2 photon29( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__28), +.i_y(hit__28), +.i_z(dead__28), +//Outputs + .o_x(weight__29), +.o_y(hit__29), +.o_z(dead__29) +); + +PhotonBlock2 photon28( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__27), +.i_y(hit__27), +.i_z(dead__27), +//Outputs + .o_x(weight__28), +.o_y(hit__28), +.o_z(dead__28) +); + +PhotonBlock2 photon27( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__26), +.i_y(hit__26), +.i_z(dead__26), +//Outputs + .o_x(weight__27), +.o_y(hit__27), +.o_z(dead__27) +); + +PhotonBlock2 photon26( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__25), +.i_y(hit__25), +.i_z(dead__25), +//Outputs + .o_x(weight__26), +.o_y(hit__26), +.o_z(dead__26) +); + +PhotonBlock2 photon25( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__24), +.i_y(hit__24), +.i_z(dead__24), +//Outputs + .o_x(weight__25), +.o_y(hit__25), +.o_z(dead__25) +); + +PhotonBlock2 photon24( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__23), +.i_y(hit__23), +.i_z(dead__23), +//Outputs + .o_x(weight__24), +.o_y(hit__24), +.o_z(dead__24) +); + +PhotonBlock2 photon23( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__22), +.i_y(hit__22), +.i_z(dead__22), +//Outputs + .o_x(weight__23), +.o_y(hit__23), +.o_z(dead__23) +); + +PhotonBlock2 photon22( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__21), +.i_y(hit__21), +.i_z(dead__21), +//Outputs + .o_x(weight__22), +.o_y(hit__22), +.o_z(dead__22) +); + +PhotonBlock2 photon21( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__20), +.i_y(hit__20), +.i_z(dead__20), +//Outputs + .o_x(weight__21), +.o_y(hit__21), +.o_z(dead__21) +); + +PhotonBlock2 photon20( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__19), +.i_y(hit__19), +.i_z(dead__19), +//Outputs + .o_x(weight__20), +.o_y(hit__20), +.o_z(dead__20) +); + +PhotonBlock2 photon19( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__18), +.i_y(hit__18), +.i_z(dead__18), +//Outputs + .o_x(weight__19), +.o_y(hit__19), +.o_z(dead__19) +); + + +PhotonBlock2 photon17( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__16), +.i_y(hit__16), +.i_z(dead__16), +//Outputs + .o_x(weight__17), +.o_y(hit__17), +.o_z(dead__17) +); + +PhotonBlock2 photon16( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__15), +.i_y(hit__15), +.i_z(dead__15), +//Outputs + .o_x(weight__16), +.o_y(hit__16), +.o_z(dead__16) +); + +PhotonBlock2 photon15( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__14), +.i_y(hit__14), +.i_z(dead__14), +//Outputs + .o_x(weight__15), +.o_y(hit__15), +.o_z(dead__15) +); + +PhotonBlock2 photon14( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__13), +.i_y(hit__13), +.i_z(dead__13), +//Outputs + .o_x(weight__14), +.o_y(hit__14), +.o_z(dead__14) +); + +PhotonBlock2 photon13( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__12), +.i_y(hit__12), +.i_z(dead__12), +//Outputs + .o_x(weight__13), +.o_y(hit__13), +.o_z(dead__13) +); + +PhotonBlock2 photon12( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__11), +.i_y(hit__11), +.i_z(dead__11), +//Outputs + .o_x(weight__12), +.o_y(hit__12), +.o_z(dead__12) +); + +PhotonBlock2 photon11( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__10), +.i_y(hit__10), +.i_z(dead__10), +//Outputs + .o_x(weight__11), +.o_y(hit__11), +.o_z(dead__11) +); + +PhotonBlock2 photon10( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__9), +.i_y(hit__9), +.i_z(dead__9), +//Outputs + .o_x(weight__10), +.o_y(hit__10), +.o_z(dead__10) +); + +PhotonBlock2 photon9( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__8), +.i_y(hit__8), +.i_z(dead__8), +//Outputs + .o_x(weight__9), +.o_y(hit__9), +.o_z(dead__9) +); + +PhotonBlock2 photon8( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__7), +.i_y(hit__7), +.i_z(dead__7), +//Outputs + .o_x(weight__8), +.o_y(hit__8), +.o_z(dead__8) +); + +PhotonBlock2 photon7( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__6), +.i_y(hit__6), +.i_z(dead__6), +//Outputs + .o_x(weight__7), +.o_y(hit__7), +.o_z(dead__7) +); + +PhotonBlock2 photon6( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__5), +.i_y(hit__5), +.i_z(dead__5), +//Outputs + .o_x(weight__6), +.o_y(hit__6), +.o_z(dead__6) +); + +PhotonBlock2 photon5( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__4), +.i_y(hit__4), +.i_z(dead__4), +//Outputs + .o_x(weight__5), +.o_y(hit__5), +.o_z(dead__5) +); + +PhotonBlock2 photon4( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__3), +.i_y(hit__3), +.i_z(dead__3), +//Outputs + .o_x(weight__4), +.o_y(hit__4), +.o_z(dead__4) +); + +PhotonBlock2 photon3( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__2), +.i_y(hit__2), +.i_z(dead__2), +//Outputs + .o_x(weight__3), +.o_y(hit__3), +.o_z(dead__3) +); + +PhotonBlock2 photon2( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__1), +.i_y(hit__1), +.i_z(dead__1), +//Outputs + .o_x(weight__2), +.o_y(hit__2), +.o_z(dead__2) +); + +PhotonBlock2 photon1( +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(weight__0), +.i_y(hit__0), +.i_z(dead__0), +//Outputs + .o_x(weight__1), +.o_y(hit__1), +.o_z(dead__1) +); + + +////////////////////////////////////////////////////////////////////////////// +//PIPELINE ir,iz,dwa +////////////////////////////////////////////////////////////////////////////// +//WIRES FOR CONNECTING REGISTERS +//wire [32-1:0] ir [37:0]; + +wire [32-1:0] ir__0; +wire [32-1:0] ir__1; +wire [32-1:0] ir__2; +wire [32-1:0] ir__3; +wire [32-1:0] ir__4; +wire [32-1:0] ir__5; +wire [32-1:0] ir__6; +wire [32-1:0] ir__7; +wire [32-1:0] ir__8; +wire [32-1:0] ir__9; +wire [32-1:0] ir__10; +wire [32-1:0] ir__11; +wire [32-1:0] ir__12; +wire [32-1:0] ir__13; +wire [32-1:0] ir__14; +wire [32-1:0] ir__15; +wire [32-1:0] ir__16; +wire [32-1:0] ir__17; +wire [32-1:0] ir__18; +wire [32-1:0] ir__19; +wire [32-1:0] ir__20; +wire [32-1:0] ir__21; +wire [32-1:0] ir__22; +wire [32-1:0] ir__23; +wire [32-1:0] ir__24; +wire [32-1:0] ir__25; +wire [32-1:0] ir__26; +wire [32-1:0] ir__27; +wire [32-1:0] ir__28; +wire [32-1:0] ir__29; +wire [32-1:0] ir__30; +wire [32-1:0] ir__31; +wire [32-1:0] ir__32; +wire [32-1:0] ir__33; +wire [32-1:0] ir__34; +wire [32-1:0] ir__35; +wire [32-1:0] ir__36; +wire [32-1:0] ir__37; + + +//wire [32-1:0] iz [37:0]; + + +wire [32-1:0] iz__0; +wire [32-1:0] iz__1; +wire [32-1:0] iz__2; +wire [32-1:0] iz__3; +wire [32-1:0] iz__4; +wire [32-1:0] iz__5; +wire [32-1:0] iz__6; +wire [32-1:0] iz__7; +wire [32-1:0] iz__8; +wire [32-1:0] iz__9; +wire [32-1:0] iz__10; +wire [32-1:0] iz__11; +wire [32-1:0] iz__12; +wire [32-1:0] iz__13; +wire [32-1:0] iz__14; +wire [32-1:0] iz__15; +wire [32-1:0] iz__16; +wire [32-1:0] iz__17; +wire [32-1:0] iz__18; +wire [32-1:0] iz__19; +wire [32-1:0] iz__20; +wire [32-1:0] iz__21; +wire [32-1:0] iz__22; +wire [32-1:0] iz__23; +wire [32-1:0] iz__24; +wire [32-1:0] iz__25; +wire [32-1:0] iz__26; +wire [32-1:0] iz__27; +wire [32-1:0] iz__28; +wire [32-1:0] iz__29; +wire [32-1:0] iz__30; +wire [32-1:0] iz__31; +wire [32-1:0] iz__32; +wire [32-1:0] iz__33; +wire [32-1:0] iz__34; +wire [32-1:0] iz__35; +wire [32-1:0] iz__36; +wire [32-1:0] iz__37; + + +//wire [32-1:0] dwa [37:0]; + + +wire [32-1:0] dwa__0; +wire [32-1:0] dwa__1; +wire [32-1:0] dwa__2; +wire [32-1:0] dwa__3; +wire [32-1:0] dwa__4; +wire [32-1:0] dwa__5; +wire [32-1:0] dwa__6; +wire [32-1:0] dwa__7; +wire [32-1:0] dwa__8; +wire [32-1:0] dwa__9; +wire [32-1:0] dwa__10; +wire [32-1:0] dwa__11; +wire [32-1:0] dwa__12; +wire [32-1:0] dwa__13; +wire [32-1:0] dwa__14; +wire [32-1:0] dwa__15; +wire [32-1:0] dwa__16; +wire [32-1:0] dwa__17; +wire [32-1:0] dwa__18; +wire [32-1:0] dwa__19; +wire [32-1:0] dwa__20; +wire [32-1:0] dwa__21; +wire [32-1:0] dwa__22; +wire [32-1:0] dwa__23; +wire [32-1:0] dwa__24; +wire [32-1:0] dwa__25; +wire [32-1:0] dwa__26; +wire [32-1:0] dwa__27; +wire [32-1:0] dwa__28; +wire [32-1:0] dwa__29; +wire [32-1:0] dwa__30; +wire [32-1:0] dwa__31; +wire [32-1:0] dwa__32; +wire [32-1:0] dwa__33; +wire [32-1:0] dwa__34; +wire [32-1:0] dwa__35; +wire [32-1:0] dwa__36; +wire [32-1:0] dwa__37; + + +//ASSIGNMENTS FROM INPUTS TO PIPE +assign ir__0 = 32'b0; +assign iz__0 = 32'b0; +assign dwa__0 = 32'b0; + +//GENERATE PIPELINE +//generate +// for(i=`PIPE_DEPTH; i>0; i=i-1) begin: IrIzDwaPipe +// case(i) +// +// //NOTE: STAGE 14 --> REGISTER 14 on diagram !! ir, iz +// 15: +// begin +// +// PhotonBlock1 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(ir_temp), +// .i_y(iz_temp), +// .i_z(dwa[14]), +// +// //Outputs +// .o_x(ir[15]), +// .o_y(iz[15]), +// .o_z(dwa[15]) +// ); +// +// end +// +// //NOTE: STAGE 4 --> REGISTER 4 on diagram !! dwa +// 5: +// begin +// +// PhotonBlock1 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(ir[4]), +// .i_y(iz[4]), +// .i_z(dwa_temp), +// +// //Outputs +// .o_x(ir[5]), +// .o_y(iz[5]), +// .o_z(dwa[5]) +// ); +// +// end +// +// default: +// begin +// +// PhotonBlock1 photon( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_x(ir[i-1]), +// .i_y(iz[i-1]), +// .i_z(dwa[i-1]), +// +// //Outputs +// .o_x(ir[i]), +// .o_y(iz[i]), +// .o_z(dwa[i]) +// ); +// end +// endcase +// end +//endgenerate + +//Expanded generation + + +//special cases first peter m + + + + PhotonBlock1 photon15q( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_x(ir_temp), + .i_y(iz_temp), + .i_z(dwa__14), + + //Outputs + .o_x(ir__15), + .o_y(iz__15), + .o_z(dwa__15) + ); + + + + //NOTE: STAGE 4 --> REGISTER 4 on diagram !! dwa + + + PhotonBlock1 photon5q( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_x(ir__4), + .i_y(iz__4), + .i_z(dwa_temp), + + //Outputs + .o_x(ir__5), + .o_y(iz__5), + .o_z(dwa__5) + ); + + PhotonBlock1 photon37q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__36), +.i_y(iz__36), +.i_z(dwa__36), +//Outputs + .o_x(ir__37), +.o_y(iz__37), +.o_z(dwa__37) +); +PhotonBlock1 photon36q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__35), +.i_y(iz__35), +.i_z(dwa__35), +//Outputs + .o_x(ir__36), +.o_y(iz__36), +.o_z(dwa__36) +); +PhotonBlock1 photon35q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__34), +.i_y(iz__34), +.i_z(dwa__34), +//Outputs + .o_x(ir__35), +.o_y(iz__35), +.o_z(dwa__35) +); +PhotonBlock1 photon34q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__33), +.i_y(iz__33), +.i_z(dwa__33), +//Outputs + .o_x(ir__34), +.o_y(iz__34), +.o_z(dwa__34) +); +PhotonBlock1 photon33q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__32), +.i_y(iz__32), +.i_z(dwa__32), +//Outputs + .o_x(ir__33), +.o_y(iz__33), +.o_z(dwa__33) +); +PhotonBlock1 photon32q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__31), +.i_y(iz__31), +.i_z(dwa__31), +//Outputs + .o_x(ir__32), +.o_y(iz__32), +.o_z(dwa__32) +); +PhotonBlock1 photon31q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__30), +.i_y(iz__30), +.i_z(dwa__30), +//Outputs + .o_x(ir__31), +.o_y(iz__31), +.o_z(dwa__31) +); +PhotonBlock1 photon30q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__29), +.i_y(iz__29), +.i_z(dwa__29), +//Outputs + .o_x(ir__30), +.o_y(iz__30), +.o_z(dwa__30) +); +PhotonBlock1 photon29q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__28), +.i_y(iz__28), +.i_z(dwa__28), +//Outputs + .o_x(ir__29), +.o_y(iz__29), +.o_z(dwa__29) +); +PhotonBlock1 photon28q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__27), +.i_y(iz__27), +.i_z(dwa__27), +//Outputs + .o_x(ir__28), +.o_y(iz__28), +.o_z(dwa__28) +); +PhotonBlock1 photon27q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__26), +.i_y(iz__26), +.i_z(dwa__26), +//Outputs + .o_x(ir__27), +.o_y(iz__27), +.o_z(dwa__27) +); +PhotonBlock1 photon26q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__25), +.i_y(iz__25), +.i_z(dwa__25), +//Outputs + .o_x(ir__26), +.o_y(iz__26), +.o_z(dwa__26) +); +PhotonBlock1 photon25q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__24), +.i_y(iz__24), +.i_z(dwa__24), +//Outputs + .o_x(ir__25), +.o_y(iz__25), +.o_z(dwa__25) +); +PhotonBlock1 photon24q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__23), +.i_y(iz__23), +.i_z(dwa__23), +//Outputs + .o_x(ir__24), +.o_y(iz__24), +.o_z(dwa__24) +); +PhotonBlock1 photon23q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__22), +.i_y(iz__22), +.i_z(dwa__22), +//Outputs + .o_x(ir__23), +.o_y(iz__23), +.o_z(dwa__23) +); +PhotonBlock1 photon22q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__21), +.i_y(iz__21), +.i_z(dwa__21), +//Outputs + .o_x(ir__22), +.o_y(iz__22), +.o_z(dwa__22) +); +PhotonBlock1 photon21q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__20), +.i_y(iz__20), +.i_z(dwa__20), +//Outputs + .o_x(ir__21), +.o_y(iz__21), +.o_z(dwa__21) +); +PhotonBlock1 photon20q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__19), +.i_y(iz__19), +.i_z(dwa__19), +//Outputs + .o_x(ir__20), +.o_y(iz__20), +.o_z(dwa__20) +); +PhotonBlock1 photon19q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__18), +.i_y(iz__18), +.i_z(dwa__18), +//Outputs + .o_x(ir__19), +.o_y(iz__19), +.o_z(dwa__19) +); +PhotonBlock1 photon18q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__17), +.i_y(iz__17), +.i_z(dwa__17), +//Outputs + .o_x(ir__18), +.o_y(iz__18), +.o_z(dwa__18) +); +PhotonBlock1 photon17q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__16), +.i_y(iz__16), +.i_z(dwa__16), +//Outputs + .o_x(ir__17), +.o_y(iz__17), +.o_z(dwa__17) +); +PhotonBlock1 photon16q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__15), +.i_y(iz__15), +.i_z(dwa__15), +//Outputs + .o_x(ir__16), +.o_y(iz__16), +.o_z(dwa__16) +); + + + + +PhotonBlock1 photon14q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__13), +.i_y(iz__13), +.i_z(dwa__13), +//Outputs + .o_x(ir__14), +.o_y(iz__14), +.o_z(dwa__14) +); +PhotonBlock1 photon13q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__12), +.i_y(iz__12), +.i_z(dwa__12), +//Outputs + .o_x(ir__13), +.o_y(iz__13), +.o_z(dwa__13) +); +PhotonBlock1 photon12q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__11), +.i_y(iz__11), +.i_z(dwa__11), +//Outputs + .o_x(ir__12), +.o_y(iz__12), +.o_z(dwa__12) +); +PhotonBlock1 photon11q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__10), +.i_y(iz__10), +.i_z(dwa__10), +//Outputs + .o_x(ir__11), +.o_y(iz__11), +.o_z(dwa__11) +); +PhotonBlock1 photon10q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__9), +.i_y(iz__9), +.i_z(dwa__9), +//Outputs + .o_x(ir__10), +.o_y(iz__10), +.o_z(dwa__10) +); +PhotonBlock1 photon9q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__8), +.i_y(iz__8), +.i_z(dwa__8), +//Outputs + .o_x(ir__9), +.o_y(iz__9), +.o_z(dwa__9) +); +PhotonBlock1 photon8q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__7), +.i_y(iz__7), +.i_z(dwa__7), +//Outputs + .o_x(ir__8), +.o_y(iz__8), +.o_z(dwa__8) +); +PhotonBlock1 photon7q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__6), +.i_y(iz__6), +.i_z(dwa__6), +//Outputs + .o_x(ir__7), +.o_y(iz__7), +.o_z(dwa__7) +); +PhotonBlock1 photon6q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__5), +.i_y(iz__5), +.i_z(dwa__5), +//Outputs + .o_x(ir__6), +.o_y(iz__6), +.o_z(dwa__6) +); + + + +PhotonBlock1 photon4q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__3), +.i_y(iz__3), +.i_z(dwa__3), +//Outputs + .o_x(ir__4), +.o_y(iz__4), +.o_z(dwa__4) +); +PhotonBlock1 photon3q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__2), +.i_y(iz__2), +.i_z(dwa__2), +//Outputs + .o_x(ir__3), +.o_y(iz__3), +.o_z(dwa__3) +); +PhotonBlock1 photon2q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__1), +.i_y(iz__1), +.i_z(dwa__1), +//Outputs + .o_x(ir__2), +.o_y(iz__2), +.o_z(dwa__2) +); +PhotonBlock1 photon1q( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_x(ir__0), +.i_y(iz__0), +.i_z(dwa__0), +//Outputs + .o_x(ir__1), +.o_y(iz__1), +.o_z(dwa__1) +); + + + +////////////////////////////////////////////////////////////////////////////// +//STAGE BY STAGE PIPELINE DESIGN +////////////////////////////////////////////////////////////////////////////// + +///////////////STAGE 2 - square of x and y///////////////////////// +always @(reset or x_pipe or y_pipe) begin + if (reset) begin + x2_temp=0; + y2_temp=0; + end + else begin + x2_temp=x_pipe*x_pipe; + y2_temp=y_pipe*y_pipe; + end +end + +///////////////STAGE 3 - square of r///////////////////////// +always @(reset or x2_P or y2_P) begin + if (reset) + r2_temp=0; + else + r2_temp=x2_P+y2_P; +end + +///////////////STAGE 4 - Find r and dwa///////////////////////// +//Create MUX +always@(layer_pipe or muaFraction1 or muaFraction2 or muaFraction3 or muaFraction4 or muaFraction5) + case(layer_pipe) + 1: fractionScaled=muaFraction1; + 2: fractionScaled=muaFraction2; + 3: fractionScaled=muaFraction3; + 4: fractionScaled=muaFraction4; + 5: fractionScaled=muaFraction5; + default: fractionScaled=0; //Sys Reset case + endcase + + +always @(reset or weight__4 or r_P_wire or weight_P4 or fractionScaled or product64bit or dead__4 or hit__4) begin + if (reset) begin + weight_P4=0; + r_P=0; + product64bit=0; + dwa_temp=0; + end + else begin + weight_P4=weight__4; + r_P=r_P_wire; //Connect to sqrt block + product64bit=weight_P4*fractionScaled; + + //Checking corner cases + if (dead__4==1) //Dead photon + dwa_temp=weight_P4;//drop all its weight + else if (hit__4==1) //Hit Boundary + dwa_temp=0; //Don't add to absorption array + else + dwa_temp=product64bit[63:32]; + end +end + +assign r2_P_wire=r2_P; + +Sqrt_64b squareRoot ( + .clk(clock), + .num_(r2_P_wire), + .res(r_P_wire) + ); + +///////////////STAGE 14 - Find ir and iz///////////////////////// +always @(reset or r_P or z_pipe or dead__14 or hit__14 or iz_temp or ir_temp) begin + if (reset) begin + ir_temp=0; + iz_temp=0; + end + + //Checking corner cases!!! + else begin + //ir_temp=r_P>>`RGRID_SCLAE_EXP; + //iz_temp=z_pipe>>`ZGRID_SCLAE_EXP; + if (dead__14==1) begin + ir_temp=`NR-1; + iz_temp=`NZ-1; + end + else if (hit__14==1) begin + ir_temp=0; + iz_temp=0; + end + else begin + if ((z_pipe>>`ZGRID_SCLAE_EXP) >=`NZ ) begin + iz_temp=`NZ-1; + end + else begin + iz_temp=z_pipe>>`ZGRID_SCLAE_EXP; + end + + if ((r_P>>`RGRID_SCLAE_EXP) >= `NR ) begin + ir_temp=`NR-1; + end + else begin + ir_temp=r_P>>`RGRID_SCLAE_EXP; + end + end + +// if (iz_temp>=`NZ) begin +// iz_temp=`NZ-1; +// end +// +// +// if (ir_temp>=`NR) begin +// ir_temp=`NR-1; +// end + + + end +end + +///////////////STAGE 15 - Compute MEM address///////////////////////// +always @(reset or ir__15 or iz__15 or ir_P or iz_P or ir_scaled) begin + if (reset) begin + ir_P=0; + iz_P=0; + ir_scaled=0; + rADDR_temp=0; + end + else begin + ir_P=ir__15; + iz_P=iz__15; + ir_scaled=ir_P<<`NR_EXP; + rADDR_temp=ir_scaled[15:0] + iz_P[15:0]; + end +end + +///////////////STAGE 16 - MEM read///////////////////////// +always @(reset or ir__16 or ir__17 or iz__16 or iz__17 or ir__18 or iz__18 or newAbs_P or q or newAbs_temp) begin + if (reset) begin + oldAbs_MEM=0; + end else begin + //Check Corner cases (RAW hazards) + if ((ir__16==ir__17) && (iz__16==iz__17)) begin + oldAbs_MEM=newAbs_temp; + end else if ((ir__16==ir__18) && (iz__16==iz__18)) begin + oldAbs_MEM=newAbs_P; //RAW hazard + end else begin + oldAbs_MEM=q; //Connect to REAL dual-port MEM + end + end + +end + +///////////////STAGE 17 - Update Weight///////////////////////// +//TO BE TESTED!!! +always @(reset or dwa__17 or weight__17 or weight_P or dwa_P or oldAbs_P) begin + if(reset) begin + dwa_P=0; //How to specify Base 10??? + weight_P=0; + newWeight = 0; + newAbs_temp =0; + end + else begin + dwa_P=dwa__17; + weight_P=weight__17; + newWeight=weight_P-dwa_P; + newAbs_temp=oldAbs_P+dwa_P; //Check bit width casting (64-bit<--64-bit+32-bit) + end +end + +////////////////////////////////////////////////////////////////////////////// +//STAGE BY STAGE - EXTRA REGISTERS +////////////////////////////////////////////////////////////////////////////// +always @ (posedge clock) +begin + if (reset) begin + //Stage 2 + x2_P<=0; + y2_P<=0; + + //Stage 3 + r2_P<=0; + + //Stage 15 + rADDR_16<=0; + + //Stage 16 + oldAbs_P<=0; + rADDR_17<=0; + + //Stage 17 + newAbs_P<=0; + // wADDR <=0; + end + + else if (enable) begin + //Stage 2 + x2_P<=x2_temp; //From comb logic above + y2_P<=y2_temp; + + //Stage 3 + r2_P<=r2_temp; + + //Stage 15 + rADDR_16<=rADDR_temp; + + //Stage 16 + oldAbs_P<=oldAbs_MEM; + rADDR_17<=rADDR_16; + + //Stage 17 + newAbs_P<=newAbs_temp; + // wADDR <=rADDR_17; + end +end + +////////////////////////////////////////////////////////////////////////////// +//INTERFACE to on-chip MEM +////////////////////////////////////////////////////////////////////////////// +always @ (posedge clock) +begin + if (reset) + wren <=0; + else + wren<=1; //Memory enabled every cycle after global enable +end + +assign rdaddress=rADDR_temp; +assign wraddress=rADDR_17; + +assign data=newAbs_temp; + +endmodule + + +//Photons that make up the register pipeline +module PhotonBlock1( + //Inputs + clock, + reset, + enable, + + i_x, + i_y, + i_z, + + //Outputs + o_x, + o_y, + o_z + ); + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter BIT_WIDTH=32; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] i_x; +input [`BIT_WIDTH-1:0] i_y; +input [`BIT_WIDTH-1:0] i_z; + + +output [`BIT_WIDTH-1:0] o_x; +output [`BIT_WIDTH-1:0] o_y; +output [`BIT_WIDTH-1:0] o_z; + +wire clock; +wire reset; +wire enable; + +wire [`BIT_WIDTH-1:0] i_x; +wire [`BIT_WIDTH-1:0] i_y; +wire [`BIT_WIDTH-1:0] i_z; + +reg [`BIT_WIDTH-1:0] o_x; +reg [`BIT_WIDTH-1:0] o_y; +reg [`BIT_WIDTH-1:0] o_z; + +always @ (posedge clock) + if(reset) begin + o_x <= {`BIT_WIDTH{1'b0}} ; + o_y <= {`BIT_WIDTH{1'b0}}; + o_z <= {`BIT_WIDTH{1'b0}}; + end else if(enable) begin + o_x <= i_x; + o_y <= i_y; + o_z <= i_z; + end +endmodule + + +//Photons that make up the register pipeline +module PhotonBlock2( + //Inputs + clock, + reset, + enable, + + i_x, + i_y, + i_z, + + //Outputs + o_x, + o_y, + o_z + ); + +////////////////////////////////////////////////////////////////////////////// +//PARAMETERS +////////////////////////////////////////////////////////////////////////////// +//parameter BIT_WIDTH=32; + +input clock; +input reset; +input enable; + +input [`BIT_WIDTH-1:0] i_x; +input i_y; +input i_z; + + +output [`BIT_WIDTH-1:0] o_x; +output o_y; +output o_z; + +wire clock; +wire reset; +wire enable; + +wire [`BIT_WIDTH-1:0] i_x; +wire i_y; +wire i_z; + +reg [`BIT_WIDTH-1:0] o_x; +reg o_y; +reg o_z; + +always @ (posedge clock) + if(reset) begin + o_x <= {`BIT_WIDTH{1'b0}} ; + o_y <= 1'b0; + o_z <= 1'b0; + end else if(enable) begin + o_x <= i_x; + o_y <= i_y; + o_z <= i_z; + end +endmodule + + + + + + + + +module ScattererReflectorWrapper ( + //Inputs + clock, + reset, + enable, + //MEMORY WRAPPER + + //Inputs + + //Photon values + i_uz1_pipeWrapper, + i_hit2_pipeWrapper, + i_ux3_pipeWrapper, + i_uz3_pipeWrapper, + i_layer3_pipeWrapper, + i_hit4_pipeWrapper, + i_hit6_pipeWrapper, + i_hit16_pipeWrapper, + i_layer31_pipeWrapper, + i_uy32_pipeWrapper, + i_uz32_pipeWrapper, + i_hit33_pipeWrapper, + i_ux33_pipeWrapper, + i_uy33_pipeWrapper, + i_hit34_pipeWrapper, + i_ux35_pipeWrapper, + i_uy35_pipeWrapper, + i_uz35_pipeWrapper, + i_layer35_pipeWrapper, + i_hit36_pipeWrapper, + i_ux36_pipeWrapper, + i_uy36_pipeWrapper, + i_uz36_pipeWrapper, + i_layer36_pipeWrapper, + i_dead36_pipeWrapper, + + + //Memory Interface + //Inputs + rand2, + rand3, + rand5, + sint, + cost, + up_rFresnel, + down_rFresnel, + //Outputs + tindex, + fresIndex, + + //Constants + down_niOverNt_1, + down_niOverNt_2, + down_niOverNt_3, + down_niOverNt_4, + down_niOverNt_5, + up_niOverNt_1, + up_niOverNt_2, + up_niOverNt_3, + up_niOverNt_4, + up_niOverNt_5, + down_niOverNt_2_1, + down_niOverNt_2_2, + down_niOverNt_2_3, + down_niOverNt_2_4, + down_niOverNt_2_5, + up_niOverNt_2_1, + up_niOverNt_2_2, + up_niOverNt_2_3, + up_niOverNt_2_4, + up_niOverNt_2_5, + downCritAngle_0, + downCritAngle_1, + downCritAngle_2, + downCritAngle_3, + downCritAngle_4, + upCritAngle_0, + upCritAngle_1, + upCritAngle_2, + upCritAngle_3, + upCritAngle_4, + + //Outputs + ux_scatterer, + uy_scatterer, + uz_scatterer, + + ux_reflector, + uy_reflector, + uz_reflector, + layer_reflector, + dead_reflector + ); + +//-------------------PARAMETER DEFINITION---------------------- +// +// +// +// +// +// +//Assign values to parameters used later in the program. + +//parameter INTMAX_2 = 64'h3FFFFFFF00000001; +//The above parameter is never used in the ScattererReflectorWrapper module itself + + +//-----------------------------PIN DECLARATION---------------------- +// +// +// +// +// +// +// +// +//Assign appropriate types to pins (input or output). + + +input clock; +input reset; +input enable; +input [2:0] i_layer31_pipeWrapper; + + + +input [31:0] i_uz1_pipeWrapper; +input i_hit2_pipeWrapper; +input [31:0] i_ux3_pipeWrapper; +input [31:0] i_uz3_pipeWrapper; +input [2:0] i_layer3_pipeWrapper; +input i_hit4_pipeWrapper; +input i_hit6_pipeWrapper; +input i_hit16_pipeWrapper; +input [31:0] i_uy32_pipeWrapper; +input [31:0] i_uz32_pipeWrapper; +input i_hit33_pipeWrapper; +input [31:0] i_ux33_pipeWrapper; +input [31:0] i_uy33_pipeWrapper; +input i_hit34_pipeWrapper; +input [31:0] i_ux35_pipeWrapper; +input [31:0] i_uy35_pipeWrapper; +input [31:0] i_uz35_pipeWrapper; +input [2:0] i_layer35_pipeWrapper; +input i_hit36_pipeWrapper; +input [31:0] i_ux36_pipeWrapper; +input [31:0] i_uy36_pipeWrapper; +input [31:0] i_uz36_pipeWrapper; +input [2:0] i_layer36_pipeWrapper; +input i_dead36_pipeWrapper; + + +//Memory Interface +input [31:0] rand2; +input [31:0] rand3; +input [31:0] rand5; +input [31:0] sint; +input [31:0] cost; +input [31:0] up_rFresnel; +input [31:0] down_rFresnel; + +output [12:0] tindex; +output [9:0] fresIndex; + + +//Constants +input [31:0] down_niOverNt_1; +input [31:0] down_niOverNt_2; +input [31:0] down_niOverNt_3; +input [31:0] down_niOverNt_4; +input [31:0] down_niOverNt_5; +input [31:0] up_niOverNt_1; +input [31:0] up_niOverNt_2; +input [31:0] up_niOverNt_3; +input [31:0] up_niOverNt_4; +input [31:0] up_niOverNt_5; +input [63:0] down_niOverNt_2_1; +input [63:0] down_niOverNt_2_2; +input [63:0] down_niOverNt_2_3; +input [63:0] down_niOverNt_2_4; +input [63:0] down_niOverNt_2_5; +input [63:0] up_niOverNt_2_1; +input [63:0] up_niOverNt_2_2; +input [63:0] up_niOverNt_2_3; +input [63:0] up_niOverNt_2_4; +input [63:0] up_niOverNt_2_5; +input [31:0] downCritAngle_0; +input [31:0] downCritAngle_1; +input [31:0] downCritAngle_2; +input [31:0] downCritAngle_3; +input [31:0] downCritAngle_4; +input [31:0] upCritAngle_0; +input [31:0] upCritAngle_1; +input [31:0] upCritAngle_2; +input [31:0] upCritAngle_3; +input [31:0] upCritAngle_4; + + +output [31:0] ux_scatterer; +output [31:0] uy_scatterer; +output [31:0] uz_scatterer; +output [31:0] ux_reflector; +output [31:0] uy_reflector; +output [31:0] uz_reflector; +output [2:0] layer_reflector; +output dead_reflector; + + + + +//-----------------------------PIN TYPES----------------------------- +// +// +// +// +// +// +// +// +//Assign pins to be wires or regs. +wire clock; +wire reset; +wire enable; + +wire [2:0] i_layer31_pipeWrapper; + +wire [31:0] i_uz1_pipeWrapper; +wire i_hit2_pipeWrapper; +wire [31:0] i_ux3_pipeWrapper; +wire [31:0] i_uz3_pipeWrapper; +wire [2:0] i_layer3_pipeWrapper; +wire i_hit4_pipeWrapper; +wire i_hit6_pipeWrapper; +wire i_hit16_pipeWrapper; +wire [31:0] i_uy32_pipeWrapper; +wire [31:0] i_uz32_pipeWrapper; +wire i_hit33_pipeWrapper; +wire [31:0] i_ux33_pipeWrapper; +wire [31:0] i_uy33_pipeWrapper; +wire i_hit34_pipeWrapper; +wire [31:0] i_ux35_pipeWrapper; +wire [31:0] i_uy35_pipeWrapper; +wire [31:0] i_uz35_pipeWrapper; +wire [2:0] i_layer35_pipeWrapper; +wire i_hit36_pipeWrapper; +wire [31:0] i_ux36_pipeWrapper; +wire [31:0] i_uy36_pipeWrapper; +wire [31:0] i_uz36_pipeWrapper; +wire [2:0] i_layer36_pipeWrapper; +wire i_dead36_pipeWrapper; + +wire [9:0] pindex; +wire [12:0] tindex; +wire [31:0] rand2; +wire [31:0] rand3; +wire [31:0] rand5; + + +//Constants +wire [31:0] down_niOverNt_1; +wire [31:0] down_niOverNt_2; +wire [31:0] down_niOverNt_3; +wire [31:0] down_niOverNt_4; +wire [31:0] down_niOverNt_5; +wire [31:0] up_niOverNt_1; +wire [31:0] up_niOverNt_2; +wire [31:0] up_niOverNt_3; +wire [31:0] up_niOverNt_4; +wire [31:0] up_niOverNt_5; +wire [63:0] down_niOverNt_2_1; +wire [63:0] down_niOverNt_2_2; +wire [63:0] down_niOverNt_2_3; +wire [63:0] down_niOverNt_2_4; +wire [63:0] down_niOverNt_2_5; +wire [63:0] up_niOverNt_2_1; +wire [63:0] up_niOverNt_2_2; +wire [63:0] up_niOverNt_2_3; +wire [63:0] up_niOverNt_2_4; +wire [63:0] up_niOverNt_2_5; +wire [31:0] downCritAngle_0; +wire [31:0] downCritAngle_1; +wire [31:0] downCritAngle_2; +wire [31:0] downCritAngle_3; +wire [31:0] downCritAngle_4; +wire [31:0] upCritAngle_0; +wire [31:0] upCritAngle_1; +wire [31:0] upCritAngle_2; +wire [31:0] upCritAngle_3; +wire [31:0] upCritAngle_4; + +//Scatterer, final calculated values +wire [31:0] ux_scatterer; +wire [31:0] uy_scatterer; +wire [31:0] uz_scatterer; +wire [31:0] ux_reflector; +wire [31:0] uy_reflector; +wire [31:0] uz_reflector; +wire [2:0] layer_reflector; +wire dead_reflector; + + +//Mathematics results signals +wire [63:0] prod1_2; +wire [63:0] prod1_4; +wire [31:0] sqrtResult1_6; +//wire [32:0] sqrtRemainder; //not necessary, not used except as dummy var in sqrt. +wire [63:0] prod1_33; +wire [63:0] prod2_33; +wire [63:0] prod3_33; +wire [63:0] prod1_34; +wire [63:0] prod2_34; +wire [63:0] prod3_34; +wire [63:0] prod4_34; +wire [63:0] quot1_16; +wire [31:0] divRemainder; +wire [63:0] prod1_36; +wire [63:0] prod2_36; +wire [63:0] prod3_36; +wire [63:0] prod4_36; +wire [63:0] prod5_36; +wire [63:0] prod6_36; + +//Scatterer Operands +wire [31:0] op1_2_1_scatterer; +wire [31:0] op1_2_2_scatterer; +wire [31:0] op1_4_1_scatterer; +wire [31:0] op1_4_2_scatterer; +wire [63:0] sqrtOperand1_6_scatterer; +wire [63:0] divNumerator1_16_scatterer; +wire [31:0] divDenominator1_16_scatterer; +wire [31:0] op1_33_1_scatterer; +wire [31:0] op1_33_2_scatterer; +wire [31:0] op2_33_1_scatterer; +wire [31:0] op2_33_2_scatterer; +wire [31:0] op3_33_1_scatterer; +wire [31:0] op3_33_2_scatterer; +wire [31:0] op1_34_1_scatterer; +wire [31:0] op1_34_2_scatterer; +wire [31:0] op2_34_1_scatterer; +wire [31:0] op2_34_2_scatterer; +wire [31:0] op3_34_1_scatterer; +wire [31:0] op3_34_2_scatterer; +wire [31:0] op4_34_1_scatterer; +wire [31:0] op4_34_2_scatterer; +wire [31:0] op1_36_1_scatterer; +wire [31:0] op1_36_2_scatterer; +wire [31:0] op2_36_1_scatterer; +wire [31:0] op2_36_2_scatterer; +wire [31:0] op3_36_1_scatterer; +wire [31:0] op3_36_2_scatterer; +wire [31:0] op4_36_1_scatterer; +wire [31:0] op4_36_2_scatterer; +wire [31:0] op5_36_1_scatterer; +wire [31:0] op5_36_2_scatterer; +wire [31:0] op6_36_1_scatterer; +wire [31:0] op6_36_2_scatterer; + + +//Reflector Operands +wire [31:0] op1_2_1_reflector; +wire [31:0] op1_2_2_reflector; +wire [31:0] op1_4_1_reflector; +wire [31:0] op1_4_2_reflector; +wire [63:0] sqrtOperand1_6_reflector; +wire [31:0] op1_36_1_reflector; +wire [31:0] op1_36_2_reflector; +wire [31:0] op2_36_1_reflector; +wire [31:0] op2_36_2_reflector; + + + + +//Operands entering the multipliers, divider, and sqrt +wire [31:0] op1_2_1; +wire [31:0] op1_2_2; +wire [31:0] op1_4_1; +wire [31:0] op1_4_2; +wire [63:0] sqrtOperand1_6; +wire [63:0] divNumerator1_16; +wire [31:0] divDenominator1_16; +wire [31:0] op1_33_1; +wire [31:0] op1_33_2; +wire [31:0] op2_33_1; +wire [31:0] op2_33_2; +wire [31:0] op3_33_1; +wire [31:0] op3_33_2; +wire [31:0] op1_34_1; +wire [31:0] op1_34_2; +wire [31:0] op2_34_1; +wire [31:0] op2_34_2; +wire [31:0] op3_34_1; +wire [31:0] op3_34_2; +wire [31:0] op4_34_1; +wire [31:0] op4_34_2; +wire [31:0] op1_36_1; +wire [31:0] op1_36_2; +wire [31:0] op2_36_1; +wire [31:0] op2_36_2; +wire [31:0] op3_36_1; +wire [31:0] op3_36_2; +wire [31:0] op4_36_1; +wire [31:0] op4_36_2; +wire [31:0] op5_36_1; +wire [31:0] op5_36_2; +wire [31:0] op6_36_1; +wire [31:0] op6_36_2; + + +reg [2:0] layerMinusOne; + +wire [31:0] sint; +wire [31:0] cost; +wire [31:0] sinp; +wire [31:0] cosp; + +wire [31:0] up_rFresnel; +wire [31:0] down_rFresnel; +wire [9:0] fresIndex; + + + +//Need this to deal with 'unused' inputs for ODIN II +wire bigOr; +assign bigOr = i_hit16_pipeWrapper|i_hit33_pipeWrapper|i_hit34_pipeWrapper| + rand2[31]|rand2[30]|rand2[29]|rand2[28]|rand2[27]|rand2[26]| + rand2[25]|rand2[24]|rand2[23]|rand2[22]|rand2[21]|rand2[20]| + rand2[19]|rand2[18]|rand2[17]|rand2[16]|rand2[15]|rand2[14]| + rand2[13]|rand2[12]|rand2[11]|rand2[10]| + rand3[31]|rand3[30]|rand3[29]|rand3[28]|rand3[27]|rand3[26]| + rand3[25]|rand3[24]|rand3[23]|rand3[22]|rand3[21]|rand3[20]| + rand3[19]|rand3[18]|rand3[17]|rand3[16]|rand3[15]|rand3[14]| + rand3[13]|rand3[12]|rand3[11]|rand3[10]| + rand5[31]|(1'b1); +wire reset_new; +assign reset_new = reset & bigOr; + + +//MUX for sending in indices for memory. +always @ (i_layer31_pipeWrapper) begin + case (i_layer31_pipeWrapper) + 3'b001: layerMinusOne = 0; + 3'b010: layerMinusOne = 1; + 3'b011: layerMinusOne = 2; + 3'b100: layerMinusOne = 3; + 3'b101: layerMinusOne = 4; + default: layerMinusOne = 0; + endcase +end + +assign tindex = {layerMinusOne, rand2[9:0]}; +assign pindex = rand3[9:0]; + + +//Arbitrarily decide on values of sine and cosine for now, should be memory lookups +Memory_Wrapper memories( + //INPUTS + .clock(clock), + //.reset(reset), //Unused. ODIN II complained. + .pindex(pindex), + //OUTPUTS + .sinp(sinp), + .cosp(cosp) + ); + + +Scatterer scatterer_0 ( + .clock(clock), + .reset(reset_new), //so pins are used + .enable(enable), + //Photon values + .i_uz1(i_uz1_pipeWrapper), + .i_ux3(i_ux3_pipeWrapper), + .i_uz3(i_uz3_pipeWrapper), + .i_uy32(i_uy32_pipeWrapper), + .i_uz32(i_uz32_pipeWrapper), + .i_ux33(i_ux33_pipeWrapper), + .i_uy33(i_uy33_pipeWrapper), + .i_ux35(i_ux35_pipeWrapper), + .i_uy35(i_uy35_pipeWrapper), + .i_uz35(i_uz35_pipeWrapper), + .i_uz36(i_uz36_pipeWrapper), + //Mathematics Results + .prod1_2(prod1_2), + .prod1_4({prod1_4[63:63], prod1_4[61:31]}), + .sqrtResult1_6(sqrtResult1_6), + .prod1_33({prod1_33[63:63], prod1_33[61:31]}), + .prod2_33({prod2_33[63:63], prod2_33[61:31]}), + .prod3_33({prod3_33[63:63], prod3_33[61:31]}), + .prod1_34({prod1_34[63:63], prod1_34[61:31]}), + .prod2_34({prod2_34[63:63], prod2_34[61:31]}), + .prod3_34({prod3_34[63:63], prod3_34[61:31]}), + .prod4_34({prod4_34[63:63], prod4_34[61:31]}), + .quot1_16(quot1_16[63:0]), + .prod1_36(prod1_36[63:0]), + .prod2_36(prod2_36[63:0]), + .prod3_36({prod3_36[63:63], prod3_36[61:31]}), + .prod4_36({prod4_36[63:63], prod4_36[61:31]}), + .prod5_36({prod5_36[63:63], prod5_36[61:31]}), + .prod6_36({prod6_36[63:63], prod6_36[61:31]}), + //Trig from Memory + .sint_Mem(sint), + .cost_Mem(cost), + .sinp_Mem(sinp), + .cosp_Mem(cosp), + //Operands for mathematics + .op1_2_1(op1_2_1_scatterer), + .op1_2_2(op1_2_2_scatterer), + .op1_4_1(op1_4_1_scatterer), + .op1_4_2(op1_4_2_scatterer), + .sqrtOperand1_6(sqrtOperand1_6_scatterer), + .divNumerator1_16(divNumerator1_16_scatterer), + .divDenominator1_16(divDenominator1_16_scatterer), + .op1_33_1(op1_33_1_scatterer), + .op1_33_2(op1_33_2_scatterer), + .op2_33_1(op2_33_1_scatterer), + .op2_33_2(op2_33_2_scatterer), + .op3_33_1(op3_33_1_scatterer), + .op3_33_2(op3_33_2_scatterer), + .op1_34_1(op1_34_1_scatterer), + .op1_34_2(op1_34_2_scatterer), + .op2_34_1(op2_34_1_scatterer), + .op2_34_2(op2_34_2_scatterer), + .op3_34_1(op3_34_1_scatterer), + .op3_34_2(op3_34_2_scatterer), + .op4_34_1(op4_34_1_scatterer), + .op4_34_2(op4_34_2_scatterer), + .op1_36_1(op1_36_1_scatterer), + .op1_36_2(op1_36_2_scatterer), + .op2_36_1(op2_36_1_scatterer), + .op2_36_2(op2_36_2_scatterer), + .op3_36_1(op3_36_1_scatterer), + .op3_36_2(op3_36_2_scatterer), + .op4_36_1(op4_36_1_scatterer), + .op4_36_2(op4_36_2_scatterer), + .op5_36_1(op5_36_1_scatterer), + .op5_36_2(op5_36_2_scatterer), + .op6_36_1(op6_36_1_scatterer), + .op6_36_2(op6_36_2_scatterer), + + //Final calculated values + .ux_scatterer(ux_scatterer), + .uy_scatterer(uy_scatterer), + .uz_scatterer(uz_scatterer) + + ); + +Reflector reflector_0 ( + + //INPUTS + .clock(clock), + .reset(reset), + .enable(enable), + //Photon values + .i_uz1(i_uz1_pipeWrapper), + .i_uz3(i_uz3_pipeWrapper), + .i_layer3(i_layer3_pipeWrapper), + .i_ux35(i_ux35_pipeWrapper), + .i_uy35(i_uy35_pipeWrapper), + .i_uz35(i_uz35_pipeWrapper), + .i_layer35(i_layer35_pipeWrapper), + .i_ux36(i_ux36_pipeWrapper), + .i_uy36(i_uy36_pipeWrapper), + .i_uz36(i_uz36_pipeWrapper), + .i_layer36(i_layer36_pipeWrapper), + .i_dead36(i_dead36_pipeWrapper), + + //Constants + .down_niOverNt_1(down_niOverNt_1), + .down_niOverNt_2(down_niOverNt_2), + .down_niOverNt_3(down_niOverNt_3), + .down_niOverNt_4(down_niOverNt_4), + .down_niOverNt_5(down_niOverNt_5), + .up_niOverNt_1(up_niOverNt_1), + .up_niOverNt_2(up_niOverNt_2), + .up_niOverNt_3(up_niOverNt_3), + .up_niOverNt_4(up_niOverNt_4), + .up_niOverNt_5(up_niOverNt_5), + .down_niOverNt_2_1(down_niOverNt_2_1), + .down_niOverNt_2_2(down_niOverNt_2_2), + .down_niOverNt_2_3(down_niOverNt_2_3), + .down_niOverNt_2_4(down_niOverNt_2_4), + .down_niOverNt_2_5(down_niOverNt_2_5), + .up_niOverNt_2_1(up_niOverNt_2_1), + .up_niOverNt_2_2(up_niOverNt_2_2), + .up_niOverNt_2_3(up_niOverNt_2_3), + .up_niOverNt_2_4(up_niOverNt_2_4), + .up_niOverNt_2_5(up_niOverNt_2_5), + .downCritAngle_0(downCritAngle_0), + .downCritAngle_1(downCritAngle_1), + .downCritAngle_2(downCritAngle_2), + .downCritAngle_3(downCritAngle_3), + .downCritAngle_4(downCritAngle_4), + .upCritAngle_0(upCritAngle_0), + .upCritAngle_1(upCritAngle_1), + .upCritAngle_2(upCritAngle_2), + .upCritAngle_3(upCritAngle_3), + .upCritAngle_4(upCritAngle_4), + + //Fresnels inputs + .rnd({1'b0, rand5[30:0]}), + .up_rFresnel(up_rFresnel), + .down_rFresnel(down_rFresnel), + + //Mathematics Results + .prod1_2(prod1_2), + .prod1_4(prod1_4), + .sqrtResult1_6(sqrtResult1_6), + .prod1_36(prod1_36), + .prod2_36(prod2_36), + + //OUTPUTS + + //Fresnels outputs + .fresIndex(fresIndex), + + //Mathematics Operands + .op1_2_1(op1_2_1_reflector), + .op1_2_2(op1_2_2_reflector), + .op1_4_1(op1_4_1_reflector), + .op1_4_2(op1_4_2_reflector), + .sqrtOperand1_6(sqrtOperand1_6_reflector), + .op1_36_1(op1_36_1_reflector), + .op1_36_2(op1_36_2_reflector), + .op2_36_1(op2_36_1_reflector), + .op2_36_2(op2_36_2_reflector), + + + //Final Calculated Results + .ux_reflector(ux_reflector), + .uy_reflector(uy_reflector), + .uz_reflector(uz_reflector), + .layer_reflector(layer_reflector), + .dead_reflector(dead_reflector) + +); + + + + + +//Multipliers, Dividers, and Sqrts for Scatterer & Reflector + +assign op1_2_1 = (i_hit2_pipeWrapper == 1'b1) ? op1_2_1_reflector : op1_2_1_scatterer; +assign op1_2_2 = (i_hit2_pipeWrapper == 1'b1) ? op1_2_2_reflector : op1_2_2_scatterer; + +Mult_32b multiplier1_2 ( + .dataa(op1_2_1), + .datab(op1_2_2), + .result(prod1_2) + ); + +assign op1_4_1 = (i_hit4_pipeWrapper == 1'b1) ? op1_4_1_reflector : op1_4_1_scatterer; +assign op1_4_2 = (i_hit4_pipeWrapper == 1'b1) ? op1_4_2_reflector : op1_4_2_scatterer; + +Mult_32b multiplier1_4 ( + .dataa(op1_4_1), + .datab(op1_4_2), + .result(prod1_4) + ); + + + +Mult_32b multiplier1_33 ( + .dataa(op1_33_1_scatterer), + .datab(op1_33_2_scatterer), + .result(prod1_33) + ); + +Mult_32b multiplier2_33 ( + .dataa(op2_33_1_scatterer), + .datab(op2_33_2_scatterer), + .result(prod2_33) + ); + +Mult_32b multiplier3_33 ( + .dataa(op3_33_1_scatterer), + .datab(op3_33_2_scatterer), + .result(prod3_33) + ); + + +Mult_32b multiplier1_34 ( + .dataa(op1_34_1_scatterer), + .datab(op1_34_2_scatterer), + .result(prod1_34) + ); + + +Mult_32b multiplier2_34 ( + .dataa(op2_34_1_scatterer), + .datab(op2_34_2_scatterer), + .result(prod2_34) + ); + + +Mult_32b multiplier3_34 ( + .dataa(op3_34_1_scatterer), + .datab(op3_34_2_scatterer), + .result(prod3_34) + ); + +Mult_32b multiplier4_34 ( + .dataa(op4_34_1_scatterer), + .datab(op4_34_2_scatterer), + .result(prod4_34) + ); + +assign op1_36_1 = (i_hit36_pipeWrapper == 1'b1) ? op1_36_1_reflector : op1_36_1_scatterer; +assign op1_36_2 = (i_hit36_pipeWrapper == 1'b1) ? op1_36_2_reflector : op1_36_2_scatterer; + +Mult_32b multiplier1_36 ( + .dataa(op1_36_1), + .datab(op1_36_2), + .result(prod1_36) + ); + +assign op2_36_1 = (i_hit36_pipeWrapper == 1'b1) ? op2_36_1_reflector : op2_36_1_scatterer; +assign op2_36_2 = (i_hit36_pipeWrapper == 1'b1) ? op2_36_2_reflector : op2_36_2_scatterer; + +Mult_32b multiplier2_36 ( + .dataa(op2_36_1), + .datab(op2_36_2), + .result(prod2_36) + ); + +Mult_32b multiplier3_36 ( + .dataa(op3_36_1_scatterer), + .datab(op3_36_2_scatterer), + .result(prod3_36) + ); + + +Mult_32b multiplier4_36 ( + .dataa(op4_36_1_scatterer), + .datab(op4_36_2_scatterer), + .result(prod4_36) + ); + + +Mult_32b multiplier5_36 ( + .dataa(op5_36_1_scatterer), + .datab(op5_36_2_scatterer), + .result(prod5_36) + ); + + +Mult_32b multiplier6_36 ( + .dataa(op6_36_1_scatterer), + .datab(op6_36_2_scatterer), + .result(prod6_36) + ); + +assign sqrtOperand1_6 = (i_hit6_pipeWrapper == 1'b1) ? sqrtOperand1_6_reflector : sqrtOperand1_6_scatterer; + +Sqrt_64b squareRoot1_6 ( + .clk(clock), + .num_(sqrtOperand1_6), + .res(sqrtResult1_6) + ); + + + +Div_64b divide1_16 ( + .clock(clock), + .denom(divDenominator1_16_scatterer), + .numer(divNumerator1_16_scatterer), + .quotient(quot1_16), + .remain(divRemainder) + ); + + +endmodule + + + + +module InternalsBlock_Reflector( + //Inputs + clock, + reset, + enable, + + i_uz_2, //uz^2 + i_uz2, //new uz, should the photon transmit to new layer + i_oneMinusUz_2, //(1-uz)^2 + i_sa2_2, //(sine of angle 2)^2 (uz2 = cosine of angle 2). + i_uz2_2, //(uz2)^2, new uz squared. + i_ux_transmitted, //new value for ux, if the photon transmits to the next layer + i_uy_transmitted, //new value for uy, if the photon transmits to the next layer + + //Outputs + o_uz_2, + o_uz2, + o_oneMinusUz_2, + o_sa2_2, + o_uz2_2, + o_ux_transmitted, + o_uy_transmitted + ); + +input clock; +input reset; +input enable; + +input [63:0] i_uz_2; +input [31:0] i_uz2; +input [63:0] i_oneMinusUz_2; +input [63:0] i_sa2_2; +input [63:0] i_uz2_2; +input [31:0] i_ux_transmitted; +input [31:0] i_uy_transmitted; + +output [63:0] o_uz_2; +output [31:0] o_uz2; +output [63:0] o_oneMinusUz_2; +output [63:0] o_sa2_2; +output [63:0] o_uz2_2; +output [31:0] o_ux_transmitted; +output [31:0] o_uy_transmitted; + + +wire clock; +wire reset; +wire enable; + +wire [63:0] i_uz_2; +wire [31:0] i_uz2; +wire [63:0] i_oneMinusUz_2; +wire [63:0] i_sa2_2; +wire [63:0] i_uz2_2; +wire [31:0] i_ux_transmitted; +wire [31:0] i_uy_transmitted; + + +reg [63:0] o_uz_2; +reg [31:0] o_uz2; +reg [63:0] o_oneMinusUz_2; +reg [63:0] o_sa2_2; +reg [63:0] o_uz2_2; +reg [31:0] o_ux_transmitted; +reg [31:0] o_uy_transmitted; + + + +always @ (posedge clock) + if(reset) begin + o_uz_2 <= 64'h3FFFFFFFFFFFFFFF; + o_uz2 <= 32'h7FFFFFFF; + o_oneMinusUz_2 <= 64'h0000000000000000; + o_sa2_2 <= 64'h0000000000000000; + o_uz2_2 <= 64'h3FFFFFFFFFFFFFFF; + o_ux_transmitted <= 32'h00000000; + o_uy_transmitted <= 32'h00000000; + end else if(enable) begin + o_uz_2 <= i_uz_2; + o_uz2 <= i_uz2; + o_oneMinusUz_2 <= i_oneMinusUz_2; + o_sa2_2 <= i_sa2_2; + o_uz2_2 <= i_uz2_2; + o_ux_transmitted <= i_ux_transmitted; + o_uy_transmitted <= i_uy_transmitted; + end +endmodule + + +module Reflector ( + + //INPUTS + clock, + reset, + enable, + //Values from Photon Pipeline + i_uz1, + i_uz3, + i_layer3, + i_ux35, + i_uy35, + i_uz35, + i_layer35, + i_ux36, + i_uy36, + i_uz36, + i_layer36, + i_dead36, + + //Constants + down_niOverNt_1, + down_niOverNt_2, + down_niOverNt_3, + down_niOverNt_4, + down_niOverNt_5, + up_niOverNt_1, + up_niOverNt_2, + up_niOverNt_3, + up_niOverNt_4, + up_niOverNt_5, + down_niOverNt_2_1, + down_niOverNt_2_2, + down_niOverNt_2_3, + down_niOverNt_2_4, + down_niOverNt_2_5, + up_niOverNt_2_1, + up_niOverNt_2_2, + up_niOverNt_2_3, + up_niOverNt_2_4, + up_niOverNt_2_5, + downCritAngle_0, + downCritAngle_1, + downCritAngle_2, + downCritAngle_3, + downCritAngle_4, + upCritAngle_0, + upCritAngle_1, + upCritAngle_2, + upCritAngle_3, + upCritAngle_4, + + //Fresnels inputs + rnd, + up_rFresnel, + down_rFresnel, + + //Mathematics Results + prod1_2, + prod1_4, + sqrtResult1_6, + prod1_36, + prod2_36, + + + //OUTPUTS + + //Fresnels outputs + fresIndex, + + //Mathematics Operands + op1_2_1, + op1_2_2, + op1_4_1, + op1_4_2, + sqrtOperand1_6, + op1_36_1, + op1_36_2, + op2_36_1, + op2_36_2, + + + //Final Calcu`LATed Results + ux_reflector, + uy_reflector, + uz_reflector, + layer_reflector, + dead_reflector +); + +//-------------------PARAMETER DEFINITION---------------------- +// +// +// +// +// +// +//Assign values to parameters used `LATer in the program. + +//parameter `DIV = 20; +//parameter `SQRT = 10; +//parameter `LAT = `DIV + `SQRT + 7; +//parameter `INTMAX_2 = 64'h3FFFFFFFFFFFFFFF; +//parameter `INTMAX = 2147483647; +//parameter `INTMIN = -2147483647; + + +//-----------------------------PIN DECLARATION---------------------- +// +// +// +// +// +// +// +// +//Assign appropriate types to pins (input or output). +input clock; +input reset; +input enable; + +//Values from Photon Pipeline +input [31:0] i_uz1; +input [31:0] i_uz3; +input [2:0] i_layer3; +input [31:0] i_ux35; +input [31:0] i_uy35; +input [31:0] i_uz35; +input [2:0] i_layer35; +input [31:0] i_ux36; +input [31:0] i_uy36; +input [31:0] i_uz36; +input [2:0] i_layer36; +input i_dead36; + +//Constants +input [31:0] down_niOverNt_1; +input [31:0] down_niOverNt_2; +input [31:0] down_niOverNt_3; +input [31:0] down_niOverNt_4; +input [31:0] down_niOverNt_5; +input [31:0] up_niOverNt_1; +input [31:0] up_niOverNt_2; +input [31:0] up_niOverNt_3; +input [31:0] up_niOverNt_4; +input [31:0] up_niOverNt_5; +input [63:0] down_niOverNt_2_1; +input [63:0] down_niOverNt_2_2; +input [63:0] down_niOverNt_2_3; +input [63:0] down_niOverNt_2_4; +input [63:0] down_niOverNt_2_5; +input [63:0] up_niOverNt_2_1; +input [63:0] up_niOverNt_2_2; +input [63:0] up_niOverNt_2_3; +input [63:0] up_niOverNt_2_4; +input [63:0] up_niOverNt_2_5; +input [31:0] downCritAngle_0; +input [31:0] downCritAngle_1; +input [31:0] downCritAngle_2; +input [31:0] downCritAngle_3; +input [31:0] downCritAngle_4; +input [31:0] upCritAngle_0; +input [31:0] upCritAngle_1; +input [31:0] upCritAngle_2; +input [31:0] upCritAngle_3; +input [31:0] upCritAngle_4; + +//Fresnels inputs +input [31:0] rnd; +input [31:0] up_rFresnel; +input [31:0] down_rFresnel; + +//Mathematics Results +input [63:0] prod1_2; +input [63:0] prod1_4; +input [31:0] sqrtResult1_6; +input [63:0] prod1_36; +input [63:0] prod2_36; + +//OUTPUTS + +//Fresnels outputs +output [9:0] fresIndex; + +//Mathematics operands +output [31:0] op1_2_1; +output [31:0] op1_2_2; +output [31:0] op1_4_1; +output [31:0] op1_4_2; +output [63:0] sqrtOperand1_6; +output [31:0] op1_36_1; +output [31:0] op1_36_2; +output [31:0] op2_36_1; +output [31:0] op2_36_2; + + +//Final Calcu`LATed Results +output [31:0] ux_reflector; +output [31:0] uy_reflector; +output [31:0] uz_reflector; +output [2:0] layer_reflector; +output dead_reflector; + + +//-----------------------------PIN TYPES----------------------------- +// +// +// +// +// +// +// +// +//Assign pins to be wires or regs. + +wire clock; +wire reset; +wire enable; +//Values from Photon Pipeline +wire [31:0] i_uz1; +wire [31:0] i_uz3; +wire [2:0] i_layer3; +wire [31:0] i_ux35; +wire [31:0] i_uy35; +wire [31:0] i_uz35; +wire [2:0] i_layer35; +wire [31:0] i_ux36; +wire [31:0] i_uy36; +wire [31:0] i_uz36; +wire [2:0] i_layer36; +wire i_dead36; + +//Constants +wire [31:0] down_niOverNt_1; +wire [31:0] down_niOverNt_2; +wire [31:0] down_niOverNt_3; +wire [31:0] down_niOverNt_4; +wire [31:0] down_niOverNt_5; +wire [31:0] up_niOverNt_1; +wire [31:0] up_niOverNt_2; +wire [31:0] up_niOverNt_3; +wire [31:0] up_niOverNt_4; +wire [31:0] up_niOverNt_5; +wire [63:0] down_niOverNt_2_1; +wire [63:0] down_niOverNt_2_2; +wire [63:0] down_niOverNt_2_3; +wire [63:0] down_niOverNt_2_4; +wire [63:0] down_niOverNt_2_5; +wire [63:0] up_niOverNt_2_1; +wire [63:0] up_niOverNt_2_2; +wire [63:0] up_niOverNt_2_3; +wire [63:0] up_niOverNt_2_4; +wire [63:0] up_niOverNt_2_5; +wire [31:0] downCritAngle_0; +wire [31:0] downCritAngle_1; +wire [31:0] downCritAngle_2; +wire [31:0] downCritAngle_3; +wire [31:0] downCritAngle_4; +wire [31:0] upCritAngle_0; +wire [31:0] upCritAngle_1; +wire [31:0] upCritAngle_2; +wire [31:0] upCritAngle_3; +wire [31:0] upCritAngle_4; + +//Fresnels inputs +wire [31:0] rnd; +wire [31:0] up_rFresnel; +wire [31:0] down_rFresnel; + +//Mathematics Results +wire [63:0] prod1_2; +wire [63:0] prod1_4; +wire [31:0] sqrtResult1_6; +wire [63:0] prod1_36; +wire [63:0] prod2_36; + +//OUTPUTS + + +//Fresnels outputs +reg [9:0] fresIndex; + +//Operands for shared resources +wire [31:0] op1_2_1; +wire [31:0] op1_2_2; +reg [31:0] op1_4_1; +wire [31:0] op1_4_2; +wire [63:0] sqrtOperand1_6; +wire [31:0] op1_36_1; +reg [31:0] op1_36_2; +wire [31:0] op2_36_1; +reg [31:0] op2_36_2; + +//Final Calcu`LATed Results +reg [31:0] ux_reflector; +reg [31:0] uy_reflector; +reg [31:0] uz_reflector; +reg [2:0] layer_reflector; +reg dead_reflector; + + +//Need this to deal with 'unused' inputs for ODIN II +wire [63:0]bigOr; +assign bigOr = i_uz3|down_niOverNt_2_1|down_niOverNt_2_2|down_niOverNt_2_3|down_niOverNt_2_3|down_niOverNt_2_4|down_niOverNt_2_5|up_niOverNt_2_1|up_niOverNt_2_2|up_niOverNt_2_3|up_niOverNt_2_3|up_niOverNt_2_4|up_niOverNt_2_5|prod1_36|prod2_36|({32'hFFFFFFFF,32'hFFFFFFFF}); +wire reset_new; +assign reset_new = reset & bigOr[63] & bigOr[62] & bigOr[61] & bigOr[60] & bigOr[59] & bigOr[58] & bigOr[57] & bigOr[56] & bigOr[55] & bigOr[54] & bigOr[53] & bigOr[52] & bigOr[51] & bigOr[50] & bigOr[49] & bigOr[48] & bigOr[47] & bigOr[46] & bigOr[45] & bigOr[44] & bigOr[43] & bigOr[42] & bigOr[41] & bigOr[40] & bigOr[39] & bigOr[38] & bigOr[37] & bigOr[36] & bigOr[35] & bigOr[34] & bigOr[33] & bigOr[32] & bigOr[31] & bigOr[30] & bigOr[29] & bigOr[28] & bigOr[27] & bigOr[26] & bigOr[25] & bigOr[24] & bigOr[23] & bigOr[22] & bigOr[21] & bigOr[20] & bigOr[19] & bigOr[18] & bigOr[17] & bigOr[16] & bigOr[15] & bigOr[14] & bigOr[13] & bigOr[12] & bigOr[11] & bigOr[10] & bigOr[9] & bigOr[8] & bigOr[7] & bigOr[6] & bigOr[5] & bigOr[4] & bigOr[3] & bigOr[2] & bigOr[1] & bigOr[0]; + + + +//-----------------------------END Pin Types------------------------- + +//Overflow Wiring +wire overflow1_4; +wire toAnd1_36_1; +wire toAnd1_36_2; +wire overflow1_36; +wire negOverflow1_36; +wire toAnd2_36_1; +wire toAnd2_36_2; +wire overflow2_36; +wire negOverflow2_36; + +//Wiring for calcu`LATing final Results +reg [31:0] new_ux; +reg [31:0] new_uy; +reg [31:0] new_uz; +reg [2:0] new_layer; +reg new_dead; +reg [31:0] downCritAngle; +reg [31:0] upCritAngle; +reg [31:0] negUz; + + + +//Wires to Connect to Internal Registers +//wire [63:0] uz_2[`LAT:0]; +//wire [31:0] uz2[`LAT:0]; +//wire [63:0] oneMinusUz_2[`LAT:0]; +//wire [63:0] sa2_2[`LAT:0]; +//wire [63:0] uz2_2[`LAT:0]; +//wire [31:0] ux_transmitted[`LAT:0]; +//wire [31:0] uy_transmitted[`LAT:0]; + +wire [63:0] uz_2__0; +wire [63:0] uz_2__1; +wire [63:0] uz_2__2; +wire [63:0] uz_2__3; +wire [63:0] uz_2__4; +wire [63:0] uz_2__5; +wire [63:0] uz_2__6; +wire [63:0] uz_2__7; +wire [63:0] uz_2__8; +wire [63:0] uz_2__9; +wire [63:0] uz_2__10; +wire [63:0] uz_2__11; +wire [63:0] uz_2__12; +wire [63:0] uz_2__13; +wire [63:0] uz_2__14; +wire [63:0] uz_2__15; +wire [63:0] uz_2__16; +wire [63:0] uz_2__17; +wire [63:0] uz_2__18; +wire [63:0] uz_2__19; +wire [63:0] uz_2__20; +wire [63:0] uz_2__21; +wire [63:0] uz_2__22; +wire [63:0] uz_2__23; +wire [63:0] uz_2__24; +wire [63:0] uz_2__25; +wire [63:0] uz_2__26; +wire [63:0] uz_2__27; +wire [63:0] uz_2__28; +wire [63:0] uz_2__29; +wire [63:0] uz_2__30; +wire [63:0] uz_2__31; +wire [63:0] uz_2__32; +wire [63:0] uz_2__33; +wire [63:0] uz_2__34; +wire [63:0] uz_2__35; +wire [63:0] uz_2__36; +wire [63:0] uz_2__37; + + + +//wire [31:0] uz2[37:0]; +wire [32-1:0] uz2__0; +wire [32-1:0] uz2__1; +wire [32-1:0] uz2__2; +wire [32-1:0] uz2__3; +wire [32-1:0] uz2__4; +wire [32-1:0] uz2__5; +wire [32-1:0] uz2__6; +wire [32-1:0] uz2__7; +wire [32-1:0] uz2__8; +wire [32-1:0] uz2__9; +wire [32-1:0] uz2__10; +wire [32-1:0] uz2__11; +wire [32-1:0] uz2__12; +wire [32-1:0] uz2__13; +wire [32-1:0] uz2__14; +wire [32-1:0] uz2__15; +wire [32-1:0] uz2__16; +wire [32-1:0] uz2__17; +wire [32-1:0] uz2__18; +wire [32-1:0] uz2__19; +wire [32-1:0] uz2__20; +wire [32-1:0] uz2__21; +wire [32-1:0] uz2__22; +wire [32-1:0] uz2__23; +wire [32-1:0] uz2__24; +wire [32-1:0] uz2__25; +wire [32-1:0] uz2__26; +wire [32-1:0] uz2__27; +wire [32-1:0] uz2__28; +wire [32-1:0] uz2__29; +wire [32-1:0] uz2__30; +wire [32-1:0] uz2__31; +wire [32-1:0] uz2__32; +wire [32-1:0] uz2__33; +wire [32-1:0] uz2__34; +wire [32-1:0] uz2__35; +wire [32-1:0] uz2__36; +wire [32-1:0] uz2__37; + + +//wire [63:0] oneMinusUz_2[37:0]; + +wire [63:0] oneMinusUz_2__0; +wire [63:0] oneMinusUz_2__1; +wire [63:0] oneMinusUz_2__2; +wire [63:0] oneMinusUz_2__3; +wire [63:0] oneMinusUz_2__4; +wire [63:0] oneMinusUz_2__5; +wire [63:0] oneMinusUz_2__6; +wire [63:0] oneMinusUz_2__7; +wire [63:0] oneMinusUz_2__8; +wire [63:0] oneMinusUz_2__9; +wire [63:0] oneMinusUz_2__10; +wire [63:0] oneMinusUz_2__11; +wire [63:0] oneMinusUz_2__12; +wire [63:0] oneMinusUz_2__13; +wire [63:0] oneMinusUz_2__14; +wire [63:0] oneMinusUz_2__15; +wire [63:0] oneMinusUz_2__16; +wire [63:0] oneMinusUz_2__17; +wire [63:0] oneMinusUz_2__18; +wire [63:0] oneMinusUz_2__19; +wire [63:0] oneMinusUz_2__20; +wire [63:0] oneMinusUz_2__21; +wire [63:0] oneMinusUz_2__22; +wire [63:0] oneMinusUz_2__23; +wire [63:0] oneMinusUz_2__24; +wire [63:0] oneMinusUz_2__25; +wire [63:0] oneMinusUz_2__26; +wire [63:0] oneMinusUz_2__27; +wire [63:0] oneMinusUz_2__28; +wire [63:0] oneMinusUz_2__29; +wire [63:0] oneMinusUz_2__30; +wire [63:0] oneMinusUz_2__31; +wire [63:0] oneMinusUz_2__32; +wire [63:0] oneMinusUz_2__33; +wire [63:0] oneMinusUz_2__34; +wire [63:0] oneMinusUz_2__35; +wire [63:0] oneMinusUz_2__36; +wire [63:0] oneMinusUz_2__37; + + +//wire [63:0] sa2_2[37:0]; +wire [63:0] sa2_2__0; +wire [63:0] sa2_2__1; +wire [63:0] sa2_2__2; +wire [63:0] sa2_2__3; +wire [63:0] sa2_2__4; +wire [63:0] sa2_2__5; +wire [63:0] sa2_2__6; +wire [63:0] sa2_2__7; +wire [63:0] sa2_2__8; +wire [63:0] sa2_2__9; +wire [63:0] sa2_2__10; +wire [63:0] sa2_2__11; +wire [63:0] sa2_2__12; +wire [63:0] sa2_2__13; +wire [63:0] sa2_2__14; +wire [63:0] sa2_2__15; +wire [63:0] sa2_2__16; +wire [63:0] sa2_2__17; +wire [63:0] sa2_2__18; +wire [63:0] sa2_2__19; +wire [63:0] sa2_2__20; +wire [63:0] sa2_2__21; +wire [63:0] sa2_2__22; +wire [63:0] sa2_2__23; +wire [63:0] sa2_2__24; +wire [63:0] sa2_2__25; +wire [63:0] sa2_2__26; +wire [63:0] sa2_2__27; +wire [63:0] sa2_2__28; +wire [63:0] sa2_2__29; +wire [63:0] sa2_2__30; +wire [63:0] sa2_2__31; +wire [63:0] sa2_2__32; +wire [63:0] sa2_2__33; +wire [63:0] sa2_2__34; +wire [63:0] sa2_2__35; +wire [63:0] sa2_2__36; +wire [63:0] sa2_2__37; + + +//wire [63:0] uz2_2[37:0]; + +wire [63:0] uz2_2__0; +wire [63:0] uz2_2__1; +wire [63:0] uz2_2__2; +wire [63:0] uz2_2__3; +wire [63:0] uz2_2__4; +wire [63:0] uz2_2__5; +wire [63:0] uz2_2__6; +wire [63:0] uz2_2__7; +wire [63:0] uz2_2__8; +wire [63:0] uz2_2__9; +wire [63:0] uz2_2__10; +wire [63:0] uz2_2__11; +wire [63:0] uz2_2__12; +wire [63:0] uz2_2__13; +wire [63:0] uz2_2__14; +wire [63:0] uz2_2__15; +wire [63:0] uz2_2__16; +wire [63:0] uz2_2__17; +wire [63:0] uz2_2__18; +wire [63:0] uz2_2__19; +wire [63:0] uz2_2__20; +wire [63:0] uz2_2__21; +wire [63:0] uz2_2__22; +wire [63:0] uz2_2__23; +wire [63:0] uz2_2__24; +wire [63:0] uz2_2__25; +wire [63:0] uz2_2__26; +wire [63:0] uz2_2__27; +wire [63:0] uz2_2__28; +wire [63:0] uz2_2__29; +wire [63:0] uz2_2__30; +wire [63:0] uz2_2__31; +wire [63:0] uz2_2__32; +wire [63:0] uz2_2__33; +wire [63:0] uz2_2__34; +wire [63:0] uz2_2__35; +wire [63:0] uz2_2__36; +wire [63:0] uz2_2__37; + +//wire [31:0] ux_transmitted[37:0]; + +wire [32-1:0] ux_transmitted__0; +wire [32-1:0] ux_transmitted__1; +wire [32-1:0] ux_transmitted__2; +wire [32-1:0] ux_transmitted__3; +wire [32-1:0] ux_transmitted__4; +wire [32-1:0] ux_transmitted__5; +wire [32-1:0] ux_transmitted__6; +wire [32-1:0] ux_transmitted__7; +wire [32-1:0] ux_transmitted__8; +wire [32-1:0] ux_transmitted__9; +wire [32-1:0] ux_transmitted__10; +wire [32-1:0] ux_transmitted__11; +wire [32-1:0] ux_transmitted__12; +wire [32-1:0] ux_transmitted__13; +wire [32-1:0] ux_transmitted__14; +wire [32-1:0] ux_transmitted__15; +wire [32-1:0] ux_transmitted__16; +wire [32-1:0] ux_transmitted__17; +wire [32-1:0] ux_transmitted__18; +wire [32-1:0] ux_transmitted__19; +wire [32-1:0] ux_transmitted__20; +wire [32-1:0] ux_transmitted__21; +wire [32-1:0] ux_transmitted__22; +wire [32-1:0] ux_transmitted__23; +wire [32-1:0] ux_transmitted__24; +wire [32-1:0] ux_transmitted__25; +wire [32-1:0] ux_transmitted__26; +wire [32-1:0] ux_transmitted__27; +wire [32-1:0] ux_transmitted__28; +wire [32-1:0] ux_transmitted__29; +wire [32-1:0] ux_transmitted__30; +wire [32-1:0] ux_transmitted__31; +wire [32-1:0] ux_transmitted__32; +wire [32-1:0] ux_transmitted__33; +wire [32-1:0] ux_transmitted__34; +wire [32-1:0] ux_transmitted__35; +wire [32-1:0] ux_transmitted__36; +wire [32-1:0] ux_transmitted__37; + +//wire [31:0] uy_transmitted[37:0]; + +wire [32-1:0] uy_transmitted__0; +wire [32-1:0] uy_transmitted__1; +wire [32-1:0] uy_transmitted__2; +wire [32-1:0] uy_transmitted__3; +wire [32-1:0] uy_transmitted__4; +wire [32-1:0] uy_transmitted__5; +wire [32-1:0] uy_transmitted__6; +wire [32-1:0] uy_transmitted__7; +wire [32-1:0] uy_transmitted__8; +wire [32-1:0] uy_transmitted__9; +wire [32-1:0] uy_transmitted__10; +wire [32-1:0] uy_transmitted__11; +wire [32-1:0] uy_transmitted__12; +wire [32-1:0] uy_transmitted__13; +wire [32-1:0] uy_transmitted__14; +wire [32-1:0] uy_transmitted__15; +wire [32-1:0] uy_transmitted__16; +wire [32-1:0] uy_transmitted__17; +wire [32-1:0] uy_transmitted__18; +wire [32-1:0] uy_transmitted__19; +wire [32-1:0] uy_transmitted__20; +wire [32-1:0] uy_transmitted__21; +wire [32-1:0] uy_transmitted__22; +wire [32-1:0] uy_transmitted__23; +wire [32-1:0] uy_transmitted__24; +wire [32-1:0] uy_transmitted__25; +wire [32-1:0] uy_transmitted__26; +wire [32-1:0] uy_transmitted__27; +wire [32-1:0] uy_transmitted__28; +wire [32-1:0] uy_transmitted__29; +wire [32-1:0] uy_transmitted__30; +wire [32-1:0] uy_transmitted__31; +wire [32-1:0] uy_transmitted__32; +wire [32-1:0] uy_transmitted__33; +wire [32-1:0] uy_transmitted__34; +wire [32-1:0] uy_transmitted__35; +wire [32-1:0] uy_transmitted__36; +wire [32-1:0] uy_transmitted__37; + +wire [63:0] new_uz_2; +wire [31:0] new_uz2; +wire [63:0] new_oneMinusUz_2; +wire [63:0] new_sa2_2; +wire [63:0] new_uz2_2; +reg [31:0] new_ux_transmitted; +reg [31:0] new_uy_transmitted; + + + +//------------------Register Pipeline----------------- +//Generation Methodology: Standard block, called InternalsBlock_Reflector, +//is repeated multiple times, based on the `LATency of the reflector and +//scatterer. This block contains the list of all internal variables +//that need to be registered and passed along in the pipeline. +// +//Previous values in the pipeline are passed to the next register on each +//clock tick. The exception comes when an internal variable gets +//calcu`LATed. Each time a new internal variable is calcu`LATed, a new +//case is added to the case statement, and instead of hooking previous +//values of that variable to next, the new, calcu`LATed values are hooked up. +// +//This method will generate many more registers than what are required, but +//it is expected that the synthesis tool will synthesize these away. +// +// +//Commenting Convention: Whenever a new value is injected into the pipe, the +//comment //Changed Value is added directly above the variable in question. +//When multiple values are calcu`LATed in a single clock cycle, multiple such +//comments are placed. Wires connected to "Changed Values" always start with +//the prefix new_. +// +//GENERATE PIPELINE + +//genvar i; +//generate +// for(i=`LAT; i>0; i=i-1) begin: internalPipe_Reflector +// case(i) +// +// 2: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// Changed Value +// .i_uz_2(new_uz_2), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// 3: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// // Changed Value +// .i_oneMinusUz_2(new_oneMinusUz_2), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// 4: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// Changed Value +// .i_sa2_2(new_sa2_2), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// 5: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// Changed Value +// .i_uz2_2(new_uz2_2), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// (`SQRT+6): +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// Changed Value +// .i_uz2(new_uz2), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// +// (`SQRT+`DIV+6): +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// Changed Value +// .i_ux_transmitted(new_ux_transmitted), //New value for ux, if photon moves to next layer +// Changed Value +// .i_uy_transmitted(new_uy_transmitted), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// default: +// InternalsBlock_Reflector pipeReg( +// Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_uz_2(uz_2[i-1]), //uz^2 +// .i_uz2(uz2[i-1]), //new uz, should the photon transmit to new layer +// .i_oneMinusUz_2(oneMinusUz_2[i-1]), //(1-uz)^2 +// .i_sa2_2(sa2_2[i-1]), //(sine of angle 2)^2 (uz2 = cosine of angle 2). +// .i_uz2_2(uz2_2[i-1]), //(uz2)^2, new uz squared. +// .i_ux_transmitted(ux_transmitted[i-1]), //New value for ux, if photon moves to next layer +// .i_uy_transmitted(uy_transmitted[i-1]), //New value for uy, if photon moves to next layer +// +// Outputs +// .o_uz_2(uz_2[i]), +// .o_uz2(uz2[i]), +// .o_oneMinusUz_2(oneMinusUz_2[i]), +// .o_sa2_2(sa2_2[i]), +// .o_uz2_2(uz2_2[i]), +// .o_ux_transmitted(ux_transmitted[i]), +// .o_uy_transmitted(uy_transmitted[i]) +// ); +// endcase +// end +//endgenerate + + + +// special cases first + + // forloop2 + InternalsBlock_Reflector pipeReg2( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + //Changed Value + .i_uz_2(new_uz_2), //uz^2 + .i_uz2(uz2__1), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__1), //(1-uz)^2 + .i_sa2_2(sa2_2__1), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__1), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__1), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__1), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__2), + .o_uz2(uz2__2), + .o_oneMinusUz_2(oneMinusUz_2__2), + .o_sa2_2(sa2_2__2), + .o_uz2_2(uz2_2__2), + .o_ux_transmitted(ux_transmitted__2), + .o_uy_transmitted(uy_transmitted__2) + ); + + // for loop3: + InternalsBlock_Reflector pipeReg3( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__2), //uz^2 + .i_uz2(uz2__2), //new uz, should the photon transmit to new layer + //Changed Value + .i_oneMinusUz_2(new_oneMinusUz_2), //(1-uz)^2 + .i_sa2_2(sa2_2__2), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__2), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__2), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__2), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__3), + .o_uz2(uz2__3), + .o_oneMinusUz_2(oneMinusUz_2__3), + .o_sa2_2(sa2_2__3), + .o_uz2_2(uz2_2__3), + .o_ux_transmitted(ux_transmitted__3), + .o_uy_transmitted(uy_transmitted__3) + ); + + // for loop4 + InternalsBlock_Reflector pipeReg4( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__3), //uz^2 + .i_uz2(uz2__3), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__3), //(1-uz)^2 + //Changed Value + .i_sa2_2(new_sa2_2), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__3), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__3), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__3), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__4), + .o_uz2(uz2__4), + .o_oneMinusUz_2(oneMinusUz_2__4), + .o_sa2_2(sa2_2__4), + .o_uz2_2(uz2_2__4), + .o_ux_transmitted(ux_transmitted__4), + .o_uy_transmitted(uy_transmitted__4) + ); + + //for loop5 + InternalsBlock_Reflector pipeReg5( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__4), //uz^2 + .i_uz2(uz2__4), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__4), //(1-uz)^2 + .i_sa2_2(sa2_2__4), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + //Changed Value + .i_uz2_2(new_uz2_2), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__4), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__4), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__5), + .o_uz2(uz2__5), + .o_oneMinusUz_2(oneMinusUz_2__5), + .o_sa2_2(sa2_2__5), + .o_uz2_2(uz2_2__5), + .o_ux_transmitted(ux_transmitted__5), + .o_uy_transmitted(uy_transmitted__5) + ); + + //for loop(10+6): + InternalsBlock_Reflector pipeReg16( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__15), //uz^2 + //Changed Value + .i_uz2(new_uz2), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__15), //(1-uz)^2 + .i_sa2_2(sa2_2__15), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__15), //(uz2)^2, new uz squared. + .i_ux_transmitted(ux_transmitted__15), //New value for ux, if photon moves to next layer + .i_uy_transmitted(uy_transmitted__15), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__16), + .o_uz2(uz2__16), + .o_oneMinusUz_2(oneMinusUz_2__16), + .o_sa2_2(sa2_2__16), + .o_uz2_2(uz2_2__16), + .o_ux_transmitted(ux_transmitted__16), + .o_uy_transmitted(uy_transmitted__16) + ); + + //for loop (10+20+6): + InternalsBlock_Reflector pipeReg36( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_uz_2(uz_2__35), //uz^2 + .i_uz2(uz2__35), //new uz, should the photon transmit to new layer + .i_oneMinusUz_2(oneMinusUz_2__35), //(1-uz)^2 + .i_sa2_2(sa2_2__35), //(sine of angle 2)^2 (uz2 = cosine of angle 2). + .i_uz2_2(uz2_2__35), //(uz2)^2, new uz squared. + //Changed Value + .i_ux_transmitted(new_ux_transmitted), //New value for ux, if photon moves to next layer + //Changed Value + .i_uy_transmitted(new_uy_transmitted), //New value for uy, if photon moves to next layer + + //Outputs + .o_uz_2(uz_2__36), + .o_uz2(uz2__36), + .o_oneMinusUz_2(oneMinusUz_2__36), + .o_sa2_2(sa2_2__36), + .o_uz2_2(uz2_2__36), + .o_ux_transmitted(ux_transmitted__36), + .o_uy_transmitted(uy_transmitted__36) + ); + + + //rest of loop + +InternalsBlock_Reflector pipeReg37( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__36), +.i_uz2(uz2__36), +.i_oneMinusUz_2(oneMinusUz_2__36), +.i_sa2_2(sa2_2__36), +.i_uz2_2(uz2_2__36), +.i_ux_transmitted(ux_transmitted__36), +.i_uy_transmitted(uy_transmitted__36), + + //outputs + +.o_uz_2(uz_2__37), +.o_uz2(uz2__37), +.o_oneMinusUz_2(oneMinusUz_2__37), +.o_sa2_2(sa2_2__37), +.o_uz2_2(uz2_2__37), +.o_ux_transmitted(ux_transmitted__37), +.o_uy_transmitted(uy_transmitted__37) +); + +//removed 36 +InternalsBlock_Reflector pipeReg35( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__34), +.i_uz2(uz2__34), +.i_oneMinusUz_2(oneMinusUz_2__34), +.i_sa2_2(sa2_2__34), +.i_uz2_2(uz2_2__34), +.i_ux_transmitted(ux_transmitted__34), +.i_uy_transmitted(uy_transmitted__34), + + //outputs + +.o_uz_2(uz_2__35), +.o_uz2(uz2__35), +.o_oneMinusUz_2(oneMinusUz_2__35), +.o_sa2_2(sa2_2__35), +.o_uz2_2(uz2_2__35), +.o_ux_transmitted(ux_transmitted__35), +.o_uy_transmitted(uy_transmitted__35) +); + +InternalsBlock_Reflector pipeReg34( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__33), +.i_uz2(uz2__33), +.i_oneMinusUz_2(oneMinusUz_2__33), +.i_sa2_2(sa2_2__33), +.i_uz2_2(uz2_2__33), +.i_ux_transmitted(ux_transmitted__33), +.i_uy_transmitted(uy_transmitted__33), + + //outputs + +.o_uz_2(uz_2__34), +.o_uz2(uz2__34), +.o_oneMinusUz_2(oneMinusUz_2__34), +.o_sa2_2(sa2_2__34), +.o_uz2_2(uz2_2__34), +.o_ux_transmitted(ux_transmitted__34), +.o_uy_transmitted(uy_transmitted__34) +); + +InternalsBlock_Reflector pipeReg33( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__32), +.i_uz2(uz2__32), +.i_oneMinusUz_2(oneMinusUz_2__32), +.i_sa2_2(sa2_2__32), +.i_uz2_2(uz2_2__32), +.i_ux_transmitted(ux_transmitted__32), +.i_uy_transmitted(uy_transmitted__32), + + //outputs + +.o_uz_2(uz_2__33), +.o_uz2(uz2__33), +.o_oneMinusUz_2(oneMinusUz_2__33), +.o_sa2_2(sa2_2__33), +.o_uz2_2(uz2_2__33), +.o_ux_transmitted(ux_transmitted__33), +.o_uy_transmitted(uy_transmitted__33) +); + +InternalsBlock_Reflector pipeReg32( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__31), +.i_uz2(uz2__31), +.i_oneMinusUz_2(oneMinusUz_2__31), +.i_sa2_2(sa2_2__31), +.i_uz2_2(uz2_2__31), +.i_ux_transmitted(ux_transmitted__31), +.i_uy_transmitted(uy_transmitted__31), + + //outputs + +.o_uz_2(uz_2__32), +.o_uz2(uz2__32), +.o_oneMinusUz_2(oneMinusUz_2__32), +.o_sa2_2(sa2_2__32), +.o_uz2_2(uz2_2__32), +.o_ux_transmitted(ux_transmitted__32), +.o_uy_transmitted(uy_transmitted__32) +); + +InternalsBlock_Reflector pipeReg31( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__30), +.i_uz2(uz2__30), +.i_oneMinusUz_2(oneMinusUz_2__30), +.i_sa2_2(sa2_2__30), +.i_uz2_2(uz2_2__30), +.i_ux_transmitted(ux_transmitted__30), +.i_uy_transmitted(uy_transmitted__30), + + //outputs + +.o_uz_2(uz_2__31), +.o_uz2(uz2__31), +.o_oneMinusUz_2(oneMinusUz_2__31), +.o_sa2_2(sa2_2__31), +.o_uz2_2(uz2_2__31), +.o_ux_transmitted(ux_transmitted__31), +.o_uy_transmitted(uy_transmitted__31) +); + +InternalsBlock_Reflector pipeReg30( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__29), +.i_uz2(uz2__29), +.i_oneMinusUz_2(oneMinusUz_2__29), +.i_sa2_2(sa2_2__29), +.i_uz2_2(uz2_2__29), +.i_ux_transmitted(ux_transmitted__29), +.i_uy_transmitted(uy_transmitted__29), + + //outputs + +.o_uz_2(uz_2__30), +.o_uz2(uz2__30), +.o_oneMinusUz_2(oneMinusUz_2__30), +.o_sa2_2(sa2_2__30), +.o_uz2_2(uz2_2__30), +.o_ux_transmitted(ux_transmitted__30), +.o_uy_transmitted(uy_transmitted__30) +); + +InternalsBlock_Reflector pipeReg29( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__28), +.i_uz2(uz2__28), +.i_oneMinusUz_2(oneMinusUz_2__28), +.i_sa2_2(sa2_2__28), +.i_uz2_2(uz2_2__28), +.i_ux_transmitted(ux_transmitted__28), +.i_uy_transmitted(uy_transmitted__28), + + //outputs + +.o_uz_2(uz_2__29), +.o_uz2(uz2__29), +.o_oneMinusUz_2(oneMinusUz_2__29), +.o_sa2_2(sa2_2__29), +.o_uz2_2(uz2_2__29), +.o_ux_transmitted(ux_transmitted__29), +.o_uy_transmitted(uy_transmitted__29) +); + +InternalsBlock_Reflector pipeReg28( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__27), +.i_uz2(uz2__27), +.i_oneMinusUz_2(oneMinusUz_2__27), +.i_sa2_2(sa2_2__27), +.i_uz2_2(uz2_2__27), +.i_ux_transmitted(ux_transmitted__27), +.i_uy_transmitted(uy_transmitted__27), + + //outputs + +.o_uz_2(uz_2__28), +.o_uz2(uz2__28), +.o_oneMinusUz_2(oneMinusUz_2__28), +.o_sa2_2(sa2_2__28), +.o_uz2_2(uz2_2__28), +.o_ux_transmitted(ux_transmitted__28), +.o_uy_transmitted(uy_transmitted__28) +); + +InternalsBlock_Reflector pipeReg27( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__26), +.i_uz2(uz2__26), +.i_oneMinusUz_2(oneMinusUz_2__26), +.i_sa2_2(sa2_2__26), +.i_uz2_2(uz2_2__26), +.i_ux_transmitted(ux_transmitted__26), +.i_uy_transmitted(uy_transmitted__26), + + //outputs + +.o_uz_2(uz_2__27), +.o_uz2(uz2__27), +.o_oneMinusUz_2(oneMinusUz_2__27), +.o_sa2_2(sa2_2__27), +.o_uz2_2(uz2_2__27), +.o_ux_transmitted(ux_transmitted__27), +.o_uy_transmitted(uy_transmitted__27) +); + +InternalsBlock_Reflector pipeReg26( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__25), +.i_uz2(uz2__25), +.i_oneMinusUz_2(oneMinusUz_2__25), +.i_sa2_2(sa2_2__25), +.i_uz2_2(uz2_2__25), +.i_ux_transmitted(ux_transmitted__25), +.i_uy_transmitted(uy_transmitted__25), + + //outputs + +.o_uz_2(uz_2__26), +.o_uz2(uz2__26), +.o_oneMinusUz_2(oneMinusUz_2__26), +.o_sa2_2(sa2_2__26), +.o_uz2_2(uz2_2__26), +.o_ux_transmitted(ux_transmitted__26), +.o_uy_transmitted(uy_transmitted__26) +); + +InternalsBlock_Reflector pipeReg25( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__24), +.i_uz2(uz2__24), +.i_oneMinusUz_2(oneMinusUz_2__24), +.i_sa2_2(sa2_2__24), +.i_uz2_2(uz2_2__24), +.i_ux_transmitted(ux_transmitted__24), +.i_uy_transmitted(uy_transmitted__24), + + //outputs + +.o_uz_2(uz_2__25), +.o_uz2(uz2__25), +.o_oneMinusUz_2(oneMinusUz_2__25), +.o_sa2_2(sa2_2__25), +.o_uz2_2(uz2_2__25), +.o_ux_transmitted(ux_transmitted__25), +.o_uy_transmitted(uy_transmitted__25) +); + +InternalsBlock_Reflector pipeReg24( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__23), +.i_uz2(uz2__23), +.i_oneMinusUz_2(oneMinusUz_2__23), +.i_sa2_2(sa2_2__23), +.i_uz2_2(uz2_2__23), +.i_ux_transmitted(ux_transmitted__23), +.i_uy_transmitted(uy_transmitted__23), + + //outputs + +.o_uz_2(uz_2__24), +.o_uz2(uz2__24), +.o_oneMinusUz_2(oneMinusUz_2__24), +.o_sa2_2(sa2_2__24), +.o_uz2_2(uz2_2__24), +.o_ux_transmitted(ux_transmitted__24), +.o_uy_transmitted(uy_transmitted__24) +); + +InternalsBlock_Reflector pipeReg23( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__22), +.i_uz2(uz2__22), +.i_oneMinusUz_2(oneMinusUz_2__22), +.i_sa2_2(sa2_2__22), +.i_uz2_2(uz2_2__22), +.i_ux_transmitted(ux_transmitted__22), +.i_uy_transmitted(uy_transmitted__22), + + //outputs + +.o_uz_2(uz_2__23), +.o_uz2(uz2__23), +.o_oneMinusUz_2(oneMinusUz_2__23), +.o_sa2_2(sa2_2__23), +.o_uz2_2(uz2_2__23), +.o_ux_transmitted(ux_transmitted__23), +.o_uy_transmitted(uy_transmitted__23) +); + +InternalsBlock_Reflector pipeReg22( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__21), +.i_uz2(uz2__21), +.i_oneMinusUz_2(oneMinusUz_2__21), +.i_sa2_2(sa2_2__21), +.i_uz2_2(uz2_2__21), +.i_ux_transmitted(ux_transmitted__21), +.i_uy_transmitted(uy_transmitted__21), + + //outputs + +.o_uz_2(uz_2__22), +.o_uz2(uz2__22), +.o_oneMinusUz_2(oneMinusUz_2__22), +.o_sa2_2(sa2_2__22), +.o_uz2_2(uz2_2__22), +.o_ux_transmitted(ux_transmitted__22), +.o_uy_transmitted(uy_transmitted__22) +); + +InternalsBlock_Reflector pipeReg21( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__20), +.i_uz2(uz2__20), +.i_oneMinusUz_2(oneMinusUz_2__20), +.i_sa2_2(sa2_2__20), +.i_uz2_2(uz2_2__20), +.i_ux_transmitted(ux_transmitted__20), +.i_uy_transmitted(uy_transmitted__20), + + //outputs + +.o_uz_2(uz_2__21), +.o_uz2(uz2__21), +.o_oneMinusUz_2(oneMinusUz_2__21), +.o_sa2_2(sa2_2__21), +.o_uz2_2(uz2_2__21), +.o_ux_transmitted(ux_transmitted__21), +.o_uy_transmitted(uy_transmitted__21) +); + +InternalsBlock_Reflector pipeReg20( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__19), +.i_uz2(uz2__19), +.i_oneMinusUz_2(oneMinusUz_2__19), +.i_sa2_2(sa2_2__19), +.i_uz2_2(uz2_2__19), +.i_ux_transmitted(ux_transmitted__19), +.i_uy_transmitted(uy_transmitted__19), + + //outputs + +.o_uz_2(uz_2__20), +.o_uz2(uz2__20), +.o_oneMinusUz_2(oneMinusUz_2__20), +.o_sa2_2(sa2_2__20), +.o_uz2_2(uz2_2__20), +.o_ux_transmitted(ux_transmitted__20), +.o_uy_transmitted(uy_transmitted__20) +); + +InternalsBlock_Reflector pipeReg19( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__18), +.i_uz2(uz2__18), +.i_oneMinusUz_2(oneMinusUz_2__18), +.i_sa2_2(sa2_2__18), +.i_uz2_2(uz2_2__18), +.i_ux_transmitted(ux_transmitted__18), +.i_uy_transmitted(uy_transmitted__18), + + //outputs + +.o_uz_2(uz_2__19), +.o_uz2(uz2__19), +.o_oneMinusUz_2(oneMinusUz_2__19), +.o_sa2_2(sa2_2__19), +.o_uz2_2(uz2_2__19), +.o_ux_transmitted(ux_transmitted__19), +.o_uy_transmitted(uy_transmitted__19) +); + +InternalsBlock_Reflector pipeReg18( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__17), +.i_uz2(uz2__17), +.i_oneMinusUz_2(oneMinusUz_2__17), +.i_sa2_2(sa2_2__17), +.i_uz2_2(uz2_2__17), +.i_ux_transmitted(ux_transmitted__17), +.i_uy_transmitted(uy_transmitted__17), + + //outputs + +.o_uz_2(uz_2__18), +.o_uz2(uz2__18), +.o_oneMinusUz_2(oneMinusUz_2__18), +.o_sa2_2(sa2_2__18), +.o_uz2_2(uz2_2__18), +.o_ux_transmitted(ux_transmitted__18), +.o_uy_transmitted(uy_transmitted__18) +); + +InternalsBlock_Reflector pipeReg17( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__16), +.i_uz2(uz2__16), +.i_oneMinusUz_2(oneMinusUz_2__16), +.i_sa2_2(sa2_2__16), +.i_uz2_2(uz2_2__16), +.i_ux_transmitted(ux_transmitted__16), +.i_uy_transmitted(uy_transmitted__16), + + //outputs + +.o_uz_2(uz_2__17), +.o_uz2(uz2__17), +.o_oneMinusUz_2(oneMinusUz_2__17), +.o_sa2_2(sa2_2__17), +.o_uz2_2(uz2_2__17), +.o_ux_transmitted(ux_transmitted__17), +.o_uy_transmitted(uy_transmitted__17) +); +//removed 16 + +InternalsBlock_Reflector pipeReg15( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__14), +.i_uz2(uz2__14), +.i_oneMinusUz_2(oneMinusUz_2__14), +.i_sa2_2(sa2_2__14), +.i_uz2_2(uz2_2__14), +.i_ux_transmitted(ux_transmitted__14), +.i_uy_transmitted(uy_transmitted__14), + + //outputs + +.o_uz_2(uz_2__15), +.o_uz2(uz2__15), +.o_oneMinusUz_2(oneMinusUz_2__15), +.o_sa2_2(sa2_2__15), +.o_uz2_2(uz2_2__15), +.o_ux_transmitted(ux_transmitted__15), +.o_uy_transmitted(uy_transmitted__15) +); + +InternalsBlock_Reflector pipeReg14( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__13), +.i_uz2(uz2__13), +.i_oneMinusUz_2(oneMinusUz_2__13), +.i_sa2_2(sa2_2__13), +.i_uz2_2(uz2_2__13), +.i_ux_transmitted(ux_transmitted__13), +.i_uy_transmitted(uy_transmitted__13), + + //outputs + +.o_uz_2(uz_2__14), +.o_uz2(uz2__14), +.o_oneMinusUz_2(oneMinusUz_2__14), +.o_sa2_2(sa2_2__14), +.o_uz2_2(uz2_2__14), +.o_ux_transmitted(ux_transmitted__14), +.o_uy_transmitted(uy_transmitted__14) +); + +InternalsBlock_Reflector pipeReg13( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__12), +.i_uz2(uz2__12), +.i_oneMinusUz_2(oneMinusUz_2__12), +.i_sa2_2(sa2_2__12), +.i_uz2_2(uz2_2__12), +.i_ux_transmitted(ux_transmitted__12), +.i_uy_transmitted(uy_transmitted__12), + + //outputs + +.o_uz_2(uz_2__13), +.o_uz2(uz2__13), +.o_oneMinusUz_2(oneMinusUz_2__13), +.o_sa2_2(sa2_2__13), +.o_uz2_2(uz2_2__13), +.o_ux_transmitted(ux_transmitted__13), +.o_uy_transmitted(uy_transmitted__13) +); + +InternalsBlock_Reflector pipeReg12( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__11), +.i_uz2(uz2__11), +.i_oneMinusUz_2(oneMinusUz_2__11), +.i_sa2_2(sa2_2__11), +.i_uz2_2(uz2_2__11), +.i_ux_transmitted(ux_transmitted__11), +.i_uy_transmitted(uy_transmitted__11), + + //outputs + +.o_uz_2(uz_2__12), +.o_uz2(uz2__12), +.o_oneMinusUz_2(oneMinusUz_2__12), +.o_sa2_2(sa2_2__12), +.o_uz2_2(uz2_2__12), +.o_ux_transmitted(ux_transmitted__12), +.o_uy_transmitted(uy_transmitted__12) +); + +InternalsBlock_Reflector pipeReg11( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__10), +.i_uz2(uz2__10), +.i_oneMinusUz_2(oneMinusUz_2__10), +.i_sa2_2(sa2_2__10), +.i_uz2_2(uz2_2__10), +.i_ux_transmitted(ux_transmitted__10), +.i_uy_transmitted(uy_transmitted__10), + + //outputs + +.o_uz_2(uz_2__11), +.o_uz2(uz2__11), +.o_oneMinusUz_2(oneMinusUz_2__11), +.o_sa2_2(sa2_2__11), +.o_uz2_2(uz2_2__11), +.o_ux_transmitted(ux_transmitted__11), +.o_uy_transmitted(uy_transmitted__11) +); + +InternalsBlock_Reflector pipeReg10( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__9), +.i_uz2(uz2__9), +.i_oneMinusUz_2(oneMinusUz_2__9), +.i_sa2_2(sa2_2__9), +.i_uz2_2(uz2_2__9), +.i_ux_transmitted(ux_transmitted__9), +.i_uy_transmitted(uy_transmitted__9), + + //outputs + +.o_uz_2(uz_2__10), +.o_uz2(uz2__10), +.o_oneMinusUz_2(oneMinusUz_2__10), +.o_sa2_2(sa2_2__10), +.o_uz2_2(uz2_2__10), +.o_ux_transmitted(ux_transmitted__10), +.o_uy_transmitted(uy_transmitted__10) +); + +InternalsBlock_Reflector pipeReg9( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__8), +.i_uz2(uz2__8), +.i_oneMinusUz_2(oneMinusUz_2__8), +.i_sa2_2(sa2_2__8), +.i_uz2_2(uz2_2__8), +.i_ux_transmitted(ux_transmitted__8), +.i_uy_transmitted(uy_transmitted__8), + + //outputs + +.o_uz_2(uz_2__9), +.o_uz2(uz2__9), +.o_oneMinusUz_2(oneMinusUz_2__9), +.o_sa2_2(sa2_2__9), +.o_uz2_2(uz2_2__9), +.o_ux_transmitted(ux_transmitted__9), +.o_uy_transmitted(uy_transmitted__9) +); + +InternalsBlock_Reflector pipeReg8( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__7), +.i_uz2(uz2__7), +.i_oneMinusUz_2(oneMinusUz_2__7), +.i_sa2_2(sa2_2__7), +.i_uz2_2(uz2_2__7), +.i_ux_transmitted(ux_transmitted__7), +.i_uy_transmitted(uy_transmitted__7), + + //outputs + +.o_uz_2(uz_2__8), +.o_uz2(uz2__8), +.o_oneMinusUz_2(oneMinusUz_2__8), +.o_sa2_2(sa2_2__8), +.o_uz2_2(uz2_2__8), +.o_ux_transmitted(ux_transmitted__8), +.o_uy_transmitted(uy_transmitted__8) +); + +InternalsBlock_Reflector pipeReg7( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__6), +.i_uz2(uz2__6), +.i_oneMinusUz_2(oneMinusUz_2__6), +.i_sa2_2(sa2_2__6), +.i_uz2_2(uz2_2__6), +.i_ux_transmitted(ux_transmitted__6), +.i_uy_transmitted(uy_transmitted__6), + + //outputs + +.o_uz_2(uz_2__7), +.o_uz2(uz2__7), +.o_oneMinusUz_2(oneMinusUz_2__7), +.o_sa2_2(sa2_2__7), +.o_uz2_2(uz2_2__7), +.o_ux_transmitted(ux_transmitted__7), +.o_uy_transmitted(uy_transmitted__7) +); + +InternalsBlock_Reflector pipeReg6( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__5), +.i_uz2(uz2__5), +.i_oneMinusUz_2(oneMinusUz_2__5), +.i_sa2_2(sa2_2__5), +.i_uz2_2(uz2_2__5), +.i_ux_transmitted(ux_transmitted__5), +.i_uy_transmitted(uy_transmitted__5), + + //outputs + +.o_uz_2(uz_2__6), +.o_uz2(uz2__6), +.o_oneMinusUz_2(oneMinusUz_2__6), +.o_sa2_2(sa2_2__6), +.o_uz2_2(uz2_2__6), +.o_ux_transmitted(ux_transmitted__6), +.o_uy_transmitted(uy_transmitted__6) +); + + +//removed 2,3,4,5 + + +//peter m +// no driver +assign uz_2__0 = 64'b0; +assign uz2__0 = 32'b0; +assign oneMinusUz_2__0 = 0; +assign sa2_2__0 = 0; +assign uz2_2__0 = 64'b0; +assign ux_transmitted__0 = 32'b00000000000000000000000000000000; +assign uy_transmitted__0 = 32'b00000000000000000000000000000000; + + +InternalsBlock_Reflector pipeReg1( +//Inputs + +.clock(clock), +.reset(reset), +.enable(enable), +.i_uz_2(uz_2__0), +.i_uz2(uz2__0), +.i_oneMinusUz_2(oneMinusUz_2__0), +.i_sa2_2(sa2_2__0), +.i_uz2_2(uz2_2__0), +.i_ux_transmitted(ux_transmitted__0), +.i_uy_transmitted(uy_transmitted__0), + + //outputs + +.o_uz_2(uz_2__1), +.o_uz2(uz2__1), +.o_oneMinusUz_2(oneMinusUz_2__1), +.o_sa2_2(sa2_2__1), +.o_uz2_2(uz2_2__1), +.o_ux_transmitted(ux_transmitted__1), +.o_uy_transmitted(uy_transmitted__1) +); + + + + +//-------------SYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is the end of the generate statement, and the beginning of the +//synchronous logic. On the clock event, the outputs calcu`LATed from +//this block are put on the output pins for reading (registered +//outputs, as per the convention). + +//Assign outputs from block on positive clock edge. +always @ (posedge clock) begin + if(reset_new) begin + //Reset internal non-pipelined registers here. + ux_reflector <= 32'h00000000; + uy_reflector <= 32'h00000000; + uz_reflector <= 32'h7FFFFFFF; + layer_reflector <= 3'b001; + dead_reflector <= 1'b1; + end else if (enable) begin + ux_reflector <= new_ux; + uy_reflector <= new_uy; + uz_reflector <= new_uz; + layer_reflector <= new_layer; + dead_reflector <= new_dead; + end +end + + +//-------------ASYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is where the asynchronous logic takes place. Things that +//occur here include setting up wiring to send to the multipliers, +//and square root unit. Also, products brought in from the wrapper +//are placed on the appropriate wires for placement in the pipeline. + +//-------------MUXES for SYNCHRONOUS LOGIC-------- +always @ (i_layer36 or downCritAngle_0 or upCritAngle_0 or + downCritAngle_1 or upCritAngle_1 or + downCritAngle_2 or upCritAngle_2 or + downCritAngle_3 or upCritAngle_3 or + downCritAngle_4 or upCritAngle_4) begin + case (i_layer36) + 1:begin + downCritAngle = downCritAngle_0; + upCritAngle = upCritAngle_0; + end + 2:begin + downCritAngle = downCritAngle_1; + upCritAngle = upCritAngle_1; + end + 3:begin + downCritAngle = downCritAngle_2; + upCritAngle = upCritAngle_2; + end + 4:begin + downCritAngle = downCritAngle_3; + upCritAngle = upCritAngle_3; + end + 5:begin + downCritAngle = downCritAngle_4; + upCritAngle = upCritAngle_4; + end + //Should never occur + default:begin + downCritAngle = downCritAngle_0; + upCritAngle = upCritAngle_0; + end + endcase +end + +always @ (i_uz35 or i_layer35) begin + negUz = -i_uz35; + case (i_uz35[31]) + 0: begin + case (i_layer35) + 1: fresIndex = {3'b000, i_uz35[30:24]}; + 2: fresIndex = {3'b001, i_uz35[30:24]}; + 3: fresIndex = {3'b010, i_uz35[30:24]}; + 4: fresIndex = {3'b011, i_uz35[30:24]}; + 5: fresIndex = {3'b100, i_uz35[30:24]}; + //Should never occur + default: fresIndex = {3'b000, i_uz35[30:24]}; + endcase + end + 1: begin + case (i_layer35) + 1: fresIndex = {3'b000, negUz[30:24]}; + 2: fresIndex = {3'b001, negUz[30:24]}; + 3: fresIndex = {3'b010, negUz[30:24]}; + 4: fresIndex = {3'b011, negUz[30:24]}; + 5: fresIndex = {3'b100, negUz[30:24]}; + //Should never occur + default: fresIndex = {3'b000, negUz[30:24]}; + endcase + end + endcase + +end + + +//-------------OPERAND SETUP---------------------- + + +//NAMING CONVENTION: +//opX_Y_Z, op stands for operand, X stands for the multiplication number for +//that clock cycle, Y stands for the clock cycle, Z is either 1 or 2 for the +//first or second operand for this multiply +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calcu`LATed will be ready for the Xth register +//location, where 0 is the register prior to any calcu`LATions being done, 1 is +//after the 1st clock cycle of calcu`LATion, etc. + +//CC 2 +assign op1_2_1 = i_uz1; +assign op1_2_2 = i_uz1; + +//CC 3 +//SUBTRACTION, see math results + +//CC 4 +always @ (i_uz3 or i_layer3 or down_niOverNt_2_1 or up_niOverNt_2_1 or + down_niOverNt_2_2 or up_niOverNt_2_2 or + down_niOverNt_2_3 or up_niOverNt_2_3 or + down_niOverNt_2_4 or up_niOverNt_2_4 or + down_niOverNt_2_5 or up_niOverNt_2_5) begin + case (i_uz3[31]) + //uz >= 0 + 0:begin + case (i_layer3) + 1: op1_4_1 = {down_niOverNt_2_1[63], down_niOverNt_2_1[61:31]}; + 2: op1_4_1 = {down_niOverNt_2_2[63], down_niOverNt_2_2[61:31]}; + 3: op1_4_1 = {down_niOverNt_2_3[63], down_niOverNt_2_3[61:31]}; + 4: op1_4_1 = {down_niOverNt_2_4[63], down_niOverNt_2_4[61:31]}; + 5: op1_4_1 = {down_niOverNt_2_5[63], down_niOverNt_2_5[61:31]}; + default: op1_4_1 = {down_niOverNt_2_1[63], down_niOverNt_2_1[61:31]}; + endcase + end + //uz < 0 + 1:begin + case (i_layer3) + 1: op1_4_1 = {up_niOverNt_2_1[63], up_niOverNt_2_1[61:31]}; + 2: op1_4_1 = {up_niOverNt_2_2[63], up_niOverNt_2_2[61:31]}; + 3: op1_4_1 = {up_niOverNt_2_3[63], up_niOverNt_2_3[61:31]}; + 4: op1_4_1 = {up_niOverNt_2_4[63], up_niOverNt_2_4[61:31]}; + 5: op1_4_1 = {up_niOverNt_2_5[63], up_niOverNt_2_5[61:31]}; + default: op1_4_1 = {up_niOverNt_2_1[63], up_niOverNt_2_1[61:31]}; + endcase + end + endcase +end + +assign op1_4_2 = {oneMinusUz_2__3[63], oneMinusUz_2__3[61:31]}; + +//CC 5 +//SUBTRACTION, see math results + +//CC `SQRT+5 -- Started in CC 6 +assign sqrtOperand1_6 = uz2_2__5; + +//CC `SQRT+`DIV+6 -- Line up with Scatterer. +assign op1_36_1 = i_ux35; + +always @ (i_uz35 or i_layer35 or down_niOverNt_1 or up_niOverNt_1 or + down_niOverNt_2 or up_niOverNt_2 or + down_niOverNt_3 or up_niOverNt_3 or + down_niOverNt_4 or up_niOverNt_4 or + down_niOverNt_5 or up_niOverNt_5) begin + case (i_uz35[31]) + 0: begin//uz >= 0 + case (i_layer35) + 1:begin + op1_36_2 = down_niOverNt_1; + op2_36_2 = down_niOverNt_1; + end + 2:begin + op1_36_2 = down_niOverNt_2; + op2_36_2 = down_niOverNt_2; + end + 3:begin + op1_36_2 = down_niOverNt_3; + op2_36_2 = down_niOverNt_3; + end + 4:begin + op1_36_2 = down_niOverNt_4; + op2_36_2 = down_niOverNt_4; + end + 5:begin + op1_36_2 = down_niOverNt_5; + op2_36_2 = down_niOverNt_5; + end + default:begin + op1_36_2 = down_niOverNt_1; + op2_36_2 = down_niOverNt_1; + end + endcase + end + 1: begin//uz < 0 + case (i_layer35) + 1:begin + op1_36_2 = up_niOverNt_1; + op2_36_2 = up_niOverNt_1; + end + 2:begin + op1_36_2 = up_niOverNt_2; + op2_36_2 = up_niOverNt_2; + end + 3:begin + op1_36_2 = up_niOverNt_3; + op2_36_2 = up_niOverNt_3; + end + 4:begin + op1_36_2 = up_niOverNt_4; + op2_36_2 = up_niOverNt_4; + end + 5:begin + op1_36_2 = up_niOverNt_5; + op2_36_2 = up_niOverNt_5; + end + default:begin + op1_36_2 = up_niOverNt_1; + op2_36_2 = up_niOverNt_1; + end + endcase + end + endcase +end + +assign op2_36_1 = i_uy35; + + + + + +//-------------MATH RESULTS---------------------- + + +//NAMING CONVENTION: +//new_VAR means that the variable named VAR will be stored into the register +//pipeline at the clock cycle indicated by the comments above it. +// +//prod stands for product, quot stands for quotient, `SQRT stands for square root +//prodX_Y means the Xth product which started calcu`LATion at the Yth clock cycle +//Similarly for quot and `SQRTResult. +// +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calcu`LATed will be ready for the Xth register +//location, where 0 is the register prior to any calcu`LATions being done, 1 is +//after the 1st clock cycle of calcu`LATion, etc. + + +//CC 2 +assign new_uz_2 = prod1_2; + +//CC 3 +sub_64b oneMinusUz2_sub( + .dataa(`INTMAX_2_ref), + .datab(uz_2__2), + .result(new_oneMinusUz_2) + ); + +//CC 4 +//Used to determine whether or not the multiply operation overflowed. +//or U1(overflow1_4, prod1_4[62], prod1_4[61], prod1_4[60], prod1_4[59], prod1_4[58]); +assign overflow1_4 = prod1_4[62]|prod1_4[61]|prod1_4[60]|prod1_4[59]|prod1_4[58]; + +//Cannot take `SQRT of negative number, that is why prod1_4[58] must be 0. + + //sign //data //padding +assign new_sa2_2 = (overflow1_4 == 1)? `INTMAX_2_ref : {prod1_4[63], prod1_4[58:0], 4'h0}; + +//5th CC +sub_64b uz2_2_sub( + .dataa(`INTMAX_2_ref), + .datab(sa2_2__4), + .result(new_uz2_2) + ); + +//CC `SQRT+5 +assign new_uz2 = sqrtResult1_6; + +//CC `SQRT+`DIV+6 -- Line up with Scatterer. + + +//Used to determine whether or not the multiply operation overflowed. +//or U2(toAnd1_36_1, prod1_36[62], prod1_36[61], prod1_36[60]); +assign toAnd1_36_1 = prod1_36[62]|prod1_36[61]|prod1_36[60]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U3(toAnd1_36_2, ~prod1_36[62], ~prod1_36[61], ~prod1_36[60]); +assign toAnd1_36_2 = ~prod1_36[62]|~prod1_36[61]|~prod1_36[60]; + +//and U4(overflow1_36, ~prod1_36[63], toAnd1_36_1); +assign overflow1_36 = ~prod1_36[63] & toAnd1_36_1; +//and U5(negOverflow1_36, prod1_36[63], toAnd1_36_2); +assign negOverflow1_36 = prod1_36[63] & toAnd1_36_2; + + +//Used to determine whether or not the multiply operation overflowed. +//or U6(toAnd2_36_1, prod2_36[62], prod2_36[61], prod2_36[60]); +assign toAnd2_36_1 = prod2_36[62]|prod2_36[61]|prod2_36[60]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U7(toAnd2_36_2, ~prod2_36[62], ~prod2_36[61], ~prod2_36[60]); +assign toAnd2_36_2 = ~prod2_36[62]|~prod2_36[61]|~prod2_36[60]; + + +//and U8(overflow2_36, ~prod2_36[63], toAnd2_36_1); +assign overflow2_36 = ~prod2_36[63] & toAnd2_36_1; +//and U9(negOverflow2_36, prod2_36[63], toAnd2_36_2); +assign negOverflow2_36 = prod2_36[63] & toAnd2_36_2; + +always @ (overflow1_36 or negOverflow1_36 or prod1_36 or + overflow2_36 or negOverflow2_36 or prod2_36) begin + case ({overflow1_36, negOverflow1_36}) + 0: new_ux_transmitted = {prod1_36[63:63], prod1_36[59:29]}; + 1: new_ux_transmitted = `INTMIN; + 2: new_ux_transmitted = `INTMAX; + //Should never occur + 3: new_ux_transmitted = {prod1_36[63:63], prod1_36[59:29]}; + endcase + + case ({overflow2_36, negOverflow2_36}) + + 0: new_uy_transmitted = {prod2_36[63:63], prod2_36[59:29]}; + 1: new_uy_transmitted = `INTMIN; + 2: new_uy_transmitted = `INTMAX; + //Should never occur + 3: new_uy_transmitted = {prod2_36[63:63], prod2_36[59:29]}; + endcase +end + + +//-------------FINAL CALCU`LATED VALUES---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +// +// +always @ (i_uz36 or downCritAngle or upCritAngle or down_rFresnel or i_ux36 or + i_uy36 or i_layer36 or i_dead36 or rnd or up_rFresnel or ux_transmitted__37 or + uy_transmitted__37 or uz2__37) begin + //REFLECTED -- Due to total internal reflection while moving down + if (~i_uz36[31] && i_uz36 <= downCritAngle) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //REFLECTED -- Due to total internal reflection while moving up + end else if (i_uz36[31] && -i_uz36 <= upCritAngle) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //REFLECTED -- Due to random number being too small while moving down + end else if (~i_uz36[31] && rnd <= down_rFresnel) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //REFLECTED -- Due to random number being too small while moving up + end else if (i_uz36[31] && rnd <= up_rFresnel) begin + new_ux = i_ux36; + new_uy = i_uy36; + new_uz = -i_uz36; + new_layer = i_layer36; + new_dead = i_dead36; + //TRANSMITTED + end else begin + new_ux = ux_transmitted__37; + new_uy = uy_transmitted__37; + case (i_uz36[31]) + 0:begin//uz >= 0 + if (i_layer36 == 5) begin + new_layer = 3'h5; + new_dead = 1'b1; + end else begin + new_layer = i_layer36+3'h1; + new_dead = i_dead36; + end + new_uz = uz2__37; + end + 1:begin//uz < 0 + if (i_layer36 == 1) begin + new_layer = 3'h1; + new_dead = 1'b1; + end else begin + new_layer = i_layer36-3'h1; + new_dead = i_dead36; + end + new_uz = -uz2__37; + end + endcase + + end +end + +endmodule + + +module Memory_Wrapper ( + //Inputs + clock, +// reset, //This is unused in the module. ODIN II complains. + pindex, + //Outputs + sinp, + cosp + ); + + +input clock; +//input reset; +input [9:0] pindex; + + +output [31:0] sinp; +output [31:0] cosp; + +//sinp_ROM sinp_MEM (.address(pindex), .clock(clock), .q(sinp)); +//cosp_ROM cosp_MEM (.address(pindex), .clock(clock), .q(cosp)); + +//Instantiate a single port ram for odin +wire [31:0]blank; +assign blank = 32'b000000000000000000000000000000; +single_port_ram sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (sinp)); +single_port_ram cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp)); + + +endmodule + + +module InternalsBlock( + //Inputs + clock, + reset, + enable, + + i_sint, + i_cost, + i_sinp, + i_cosp, + i_sintCosp, + i_sintSinp, + i_uz2, + i_uxUz, + i_uyUz, + i_uySintSinp, + i_oneMinusUz2, + i_uyUzSintCosp, + i_uxUzSintCosp, + i_uxSintSinp, + i_sqrtOneMinusUz2, + i_sintCospSqrtOneMinusUz2, + i_uxCost, + i_uzCost, + i_sqrtOneMinusUz2_inv, + i_uxNumerator, + i_uyNumerator, + i_uyCost, + i_uxQuotient, + i_uyQuotient, + //Outputs + o_sint, + o_cost, + o_sinp, + o_cosp, + o_sintCosp, + o_sintSinp, + o_uz2, + o_uxUz, + o_uyUz, + o_uySintSinp, + o_oneMinusUz2, + o_uyUzSintCosp, + o_uxUzSintCosp, + o_uxSintSinp, + o_sqrtOneMinusUz2, + o_sintCospSqrtOneMinusUz2, + o_uxCost, + o_uzCost, + o_sqrtOneMinusUz2_inv, + o_uxNumerator, + o_uyNumerator, + o_uyCost, + o_uxQuotient, + o_uyQuotient + ); + +input clock; +input reset; +input enable; + +input [31:0] i_sint; +input [31:0] i_cost; +input [31:0] i_sinp; +input [31:0] i_cosp; +input [31:0] i_sintCosp; +input [31:0] i_sintSinp; +input [63:0] i_uz2; +input [31:0] i_uxUz; +input [31:0] i_uyUz; +input [31:0] i_uySintSinp; +input [63:0] i_oneMinusUz2; +input [31:0] i_uyUzSintCosp; +input [31:0] i_uxUzSintCosp; +input [31:0] i_uxSintSinp; +input [31:0] i_sqrtOneMinusUz2; +input [31:0] i_sintCospSqrtOneMinusUz2; +input [31:0] i_uxCost; +input [31:0] i_uzCost; +input [31:0] i_sqrtOneMinusUz2_inv; +input [31:0] i_uxNumerator; +input [31:0] i_uyNumerator; +input [31:0] i_uyCost; +input [31:0] i_uxQuotient; +input [31:0] i_uyQuotient; + + +output [31:0] o_sint; +output [31:0] o_cost; +output [31:0] o_sinp; +output [31:0] o_cosp; +output [31:0] o_sintCosp; +output [31:0] o_sintSinp; +output [63:0] o_uz2; +output [31:0] o_uxUz; +output [31:0] o_uyUz; +output [31:0] o_uySintSinp; +output [63:0] o_oneMinusUz2; +output [31:0] o_uyUzSintCosp; +output [31:0] o_uxUzSintCosp; +output [31:0] o_uxSintSinp; +output [31:0] o_sqrtOneMinusUz2; +output [31:0] o_sintCospSqrtOneMinusUz2; +output [31:0] o_uxCost; +output [31:0] o_uzCost; +output [31:0] o_sqrtOneMinusUz2_inv; +output [31:0] o_uxNumerator; +output [31:0] o_uyNumerator; +output [31:0] o_uyCost; +output [31:0] o_uxQuotient; +output [31:0] o_uyQuotient; + + +wire clock; +wire reset; +wire enable; + +wire [31:0] i_sint; +wire [31:0] i_cost; +wire [31:0] i_sinp; +wire [31:0] i_cosp; +wire [31:0] i_sintCosp; +wire [31:0] i_sintSinp; +wire [63:0] i_uz2; +wire [31:0] i_uxUz; +wire [31:0] i_uyUz; +wire [31:0] i_uySintSinp; +wire [63:0] i_oneMinusUz2; +wire [31:0] i_uyUzSintCosp; +wire [31:0] i_uxUzSintCosp; +wire [31:0] i_uxSintSinp; +wire [31:0] i_sqrtOneMinusUz2; +wire [31:0] i_sintCospSqrtOneMinusUz2; +wire [31:0] i_uxCost; +wire [31:0] i_uzCost; +wire [31:0] i_sqrtOneMinusUz2_inv; +wire [31:0] i_uxNumerator; +wire [31:0] i_uyNumerator; +wire [31:0] i_uyCost; +wire [31:0] i_uxQuotient; +wire [31:0] i_uyQuotient; + + +reg [31:0] o_sint; +reg [31:0] o_cost; +reg [31:0] o_sinp; +reg [31:0] o_cosp; +reg [31:0] o_sintCosp; +reg [31:0] o_sintSinp; +reg [63:0] o_uz2; +reg [31:0] o_uxUz; +reg [31:0] o_uyUz; +reg [31:0] o_uySintSinp; +reg [63:0] o_oneMinusUz2; +reg [31:0] o_uyUzSintCosp; +reg [31:0] o_uxUzSintCosp; +reg [31:0] o_uxSintSinp; +reg [31:0] o_sqrtOneMinusUz2; +reg [31:0] o_sintCospSqrtOneMinusUz2; +reg [31:0] o_uxCost; +reg [31:0] o_uzCost; +reg [31:0] o_sqrtOneMinusUz2_inv; +reg [31:0] o_uxNumerator; +reg [31:0] o_uyNumerator; +reg [31:0] o_uyCost; +reg [31:0] o_uxQuotient; +reg [31:0] o_uyQuotient; + + + + +always @ (posedge clock) + if(reset) begin + o_sint <= 32'h00000000; + o_cost <= 32'h00000000; + o_sinp <= 32'h00000000; + o_cosp <= 32'h00000000; + o_sintCosp <= 32'h00000000; + o_sintSinp <= 32'h00000000; + o_uz2 <= 64'h0000000000000000; + o_uxUz <= 32'h00000000; + o_uyUz <= 32'h00000000; + o_uySintSinp <= 32'h00000000; + o_oneMinusUz2 <= 64'h0000000000000000; + o_uyUzSintCosp <= 32'h00000000; + o_uxUzSintCosp <= 32'h00000000; + o_uxSintSinp <= 32'h00000000; + o_sqrtOneMinusUz2 <= 32'h00000000; + o_sintCospSqrtOneMinusUz2 <= 32'h00000000; + o_uxCost <= 32'h00000000; + o_uzCost <= 32'h00000000; + o_sqrtOneMinusUz2_inv <= 32'h00000000; + o_uxNumerator <= 32'h00000000; + o_uyNumerator <= 32'h00000000; + o_uyCost <= 32'h00000000; + o_uxQuotient <= 32'h00000000; + o_uyQuotient <= 32'h00000000; + end else if(enable) begin + o_sint <= i_sint; + o_cost <= i_cost; + o_sinp <= i_sinp; + o_cosp <= i_cosp; + o_sintCosp <= i_sintCosp; + o_sintSinp <= i_sintSinp; + o_uz2 <= i_uz2; + o_uxUz <= i_uxUz; + o_uyUz <= i_uyUz; + o_uySintSinp <= i_uySintSinp; + o_oneMinusUz2 <= i_oneMinusUz2; + o_uyUzSintCosp <= i_uyUzSintCosp; + o_uxUzSintCosp <= i_uxUzSintCosp; + o_uxSintSinp <= i_uxSintSinp; + o_sqrtOneMinusUz2 <= i_sqrtOneMinusUz2; + o_sintCospSqrtOneMinusUz2 <= i_sintCospSqrtOneMinusUz2; + o_uxCost <= i_uxCost; + o_uzCost <= i_uzCost; + o_sqrtOneMinusUz2_inv <= i_sqrtOneMinusUz2_inv; + o_uxNumerator <= i_uxNumerator; + o_uyNumerator <= i_uyNumerator; + o_uyCost <= i_uyCost; + o_uxQuotient <= i_uxQuotient; + o_uyQuotient <= i_uyQuotient; + end +endmodule + + +module Scatterer ( + //INPUTS + clock, + reset, + enable, + //Values from Photon Pipeline + i_uz1, + i_ux3, + i_uz3, + i_uy32, + i_uz32, + i_ux33, + i_uy33, + i_ux35, + i_uy35, + i_uz35, + i_uz36, + + //Mathematics Results + prod1_2, + prod1_4, + sqrtResult1_6, + prod1_33, + prod2_33, + prod3_33, + prod1_34, + prod2_34, + prod3_34, + prod4_34, + quot1_16, + prod1_36, + prod2_36, + prod3_36, + prod4_36, + prod5_36, + prod6_36, + + //Trig from Memory + sint_Mem, + cost_Mem, + sinp_Mem, + cosp_Mem, + + //OUTPUTS + op1_2_1, + op1_2_2, + op1_4_1, + op1_4_2, + sqrtOperand1_6, + divNumerator1_16, + divDenominator1_16, + op1_33_1, + op1_33_2, + op2_33_1, + op2_33_2, + op3_33_1, + op3_33_2, + op1_34_1, + op1_34_2, + op2_34_1, + op2_34_2, + op3_34_1, + op3_34_2, + op4_34_1, + op4_34_2, + op1_36_1, + op1_36_2, + op2_36_1, + op2_36_2, + op3_36_1, + op3_36_2, + op4_36_1, + op4_36_2, + op5_36_1, + op5_36_2, + op6_36_1, + op6_36_2, + + //Final calculated values + ux_scatterer, + uy_scatterer, + uz_scatterer + + + ); + +//-------------------PARAMETER DEFINITION---------------------- +// +// +// +// +// +// +//Assign values to parameters used later in the program. + +//parameter DIV = 20; +//parameter SQRT = 10; +//parameter LAT = DIV + SQRT + 7; +//parameter `INTMAX_2 = 64'h3FFFFFFF00000001; +//parameter `INTMAX = 2147483647; +//parameter `INTMIN = -2147483647; +//parameter `INTMAXMinus3 = 2147483644; +//parameter neg`INTMAXPlus3 = -2147483644; + + + +//-----------------------------PIN DECLARATION---------------------- +// +// +// +// +// +// +// +// +//Assign appropriate types to pins (input or output). + +input clock; +input reset; +input enable; +//Values from Photon Pipeline +input [31:0] i_uz1; +input [31:0] i_ux3; +input [31:0] i_uz3; +input [31:0] i_uy32; +input [31:0] i_uz32; +input [31:0] i_ux33; +input [31:0] i_uy33; +input [31:0] i_ux35; +input [31:0] i_uy35; +input [31:0] i_uz35; +input [31:0] i_uz36; + +//Multiplication Results +input [63:0] prod1_2; +input [31:0] prod1_4; +input [31:0] sqrtResult1_6; +input [31:0] prod1_33; +input [31:0] prod2_33; +input [31:0] prod3_33; +input [31:0] prod1_34; +input [31:0] prod2_34; +input [31:0] prod3_34; +input [31:0] prod4_34; +input [63:0] quot1_16; +//Need all 64-bits for these two to detect overflows +input [63:0] prod1_36; +input [63:0] prod2_36; +input [31:0] prod3_36; +input [31:0] prod4_36; +input [31:0] prod5_36; +input [31:0] prod6_36; + + +//Trig Values from Memory +input [31:0] sint_Mem; +input [31:0] cost_Mem; +input [31:0] sinp_Mem; +input [31:0] cosp_Mem; + +output [31:0] op1_2_1; +output [31:0] op1_2_2; +output [31:0] op1_4_1; +output [31:0] op1_4_2; +output [63:0] sqrtOperand1_6; +output [63:0] divNumerator1_16; +output [31:0] divDenominator1_16; +output [31:0] op1_33_1; +output [31:0] op1_33_2; +output [31:0] op2_33_1; +output [31:0] op2_33_2; +output [31:0] op3_33_1; +output [31:0] op3_33_2; +output [31:0] op1_34_1; +output [31:0] op1_34_2; +output [31:0] op2_34_1; +output [31:0] op2_34_2; +output [31:0] op3_34_1; +output [31:0] op3_34_2; +output [31:0] op4_34_1; +output [31:0] op4_34_2; +output [31:0] op1_36_1; +output [31:0] op1_36_2; +output [31:0] op2_36_1; +output [31:0] op2_36_2; +output [31:0] op3_36_1; +output [31:0] op3_36_2; +output [31:0] op4_36_1; +output [31:0] op4_36_2; +output [31:0] op5_36_1; +output [31:0] op5_36_2; +output [31:0] op6_36_1; +output [31:0] op6_36_2; + +//Final Calculated Results +output [31:0] ux_scatterer; +output [31:0] uy_scatterer; +output [31:0] uz_scatterer; + + +//-----------------------------PIN TYPES----------------------------- +// +// +// +// +// +// +// +// +//Assign pins to be wires or regs. + + +wire clock; +wire reset; +wire enable; +//Values from Photon Pipeline +wire [31:0] i_uz1; +wire [31:0] i_ux3; +wire [31:0] i_uz3; +wire [31:0] i_uy32; +wire [31:0] i_uz32; +wire [31:0] i_ux33; +wire [31:0] i_uy33; +wire [31:0] i_ux35; +wire [31:0] i_uy35; +wire [31:0] i_uz35; +wire [31:0] i_uz36; + +//Multiplication Results +wire [63:0] prod1_2; +wire [31:0] prod1_4; +wire [31:0] sqrtResult1_6; +wire [31:0] prod1_33; +wire [31:0] prod2_33; +wire [31:0] prod3_33; +wire [31:0] prod1_34; +wire [31:0] prod2_34; +wire [31:0] prod3_34; +wire [31:0] prod4_34; +wire [63:0] quot1_16; +wire [63:0] prod1_36; +wire [63:0] prod2_36; +wire [31:0] prod3_36; +wire [31:0] prod4_36; +wire [31:0] prod5_36; +wire [31:0] prod6_36; + + +//Trig Values from Memory +wire [31:0] sint_Mem; +wire [31:0] cost_Mem; +wire [31:0] sinp_Mem; +wire [31:0] cosp_Mem; + +//Operands for shared resources +wire [31:0] op1_2_1; +wire [31:0] op1_2_2; +wire [31:0] op1_4_1; +wire [31:0] op1_4_2; +wire [63:0] sqrtOperand1_6; +wire [63:0] divNumerator1_16; +wire [31:0] divDenominator1_16; +wire [31:0] op1_33_1; +wire [31:0] op1_33_2; +wire [31:0] op2_33_1; +wire [31:0] op2_33_2; +wire [31:0] op3_33_1; +wire [31:0] op3_33_2; +wire [31:0] op1_34_1; +wire [31:0] op1_34_2; +wire [31:0] op2_34_1; +wire [31:0] op2_34_2; +wire [31:0] op3_34_1; +wire [31:0] op3_34_2; +wire [31:0] op4_34_1; +wire [31:0] op4_34_2; +wire [31:0] op1_36_1; +wire [31:0] op1_36_2; +wire [31:0] op2_36_1; +wire [31:0] op2_36_2; +wire [31:0] op3_36_1; +wire [31:0] op3_36_2; +wire [31:0] op4_36_1; +wire [31:0] op4_36_2; +wire [31:0] op5_36_1; +wire [31:0] op5_36_2; +wire [31:0] op6_36_1; +wire [31:0] op6_36_2; + +//Final outputs +reg [31:0] ux_scatterer; +reg [31:0] uy_scatterer; +reg [31:0] uz_scatterer; + + +//Need this to deal with 'unused' inputs for ODIN II +wire [63:0]bigOr; +assign bigOr = quot1_16|prod1_36|prod2_36|({32'hFFFFFFFF,32'hFFFFFFFF}); +wire reset_new; +assign reset_new = reset & bigOr[63] & bigOr[62] & bigOr[61] & bigOr[60] & bigOr[59] & bigOr[58] & bigOr[57] & bigOr[56] & bigOr[55] & bigOr[54] & bigOr[53] & bigOr[52] & bigOr[51] & bigOr[50] & bigOr[49] & bigOr[48] & bigOr[47] & bigOr[46] & bigOr[45] & bigOr[44] & bigOr[43] & bigOr[42] & bigOr[41] & bigOr[40] & bigOr[39] & bigOr[38] & bigOr[37] & bigOr[36] & bigOr[35] & bigOr[34] & bigOr[33] & bigOr[32] & bigOr[31] & bigOr[30] & bigOr[29] & bigOr[28] & bigOr[27] & bigOr[26] & bigOr[25] & bigOr[24] & bigOr[23] & bigOr[22] & bigOr[21] & bigOr[20] & bigOr[19] & bigOr[18] & bigOr[17] & bigOr[16] & bigOr[15] & bigOr[14] & bigOr[13] & bigOr[12] & bigOr[11] & bigOr[10] & bigOr[9] & bigOr[8] & bigOr[7] & bigOr[6] & bigOr[5] & bigOr[4] & bigOr[3] & bigOr[2] & bigOr[1] & bigOr[0]; + + +//-----------------------------END Pin Types------------------------- + + + +//Wires to Connect to Internal Registers +//wire [31:0] sint[`LAT:0]; +//wire [31:0] cost[`LAT:0]; +//wire [31:0] sinp[`LAT:0]; +//wire [31:0] cosp[`LAT:0]; +//wire [31:0] sintCosp[`LAT:0]; +//wire [31:0] sintSinp[`LAT:0]; +//wire [63:0] uz2[`LAT:0]; +//wire [31:0] uxUz[`LAT:0]; +//wire [31:0] uyUz[`LAT:0]; +//wire [31:0] uySintSinp[`LAT:0]; +//wire [63:0] oneMinusUz2[`LAT:0]; +//wire [31:0] uyUzSintCosp[`LAT:0]; +//wire [31:0] uxUzSintCosp[`LAT:0]; +//wire [31:0] uxSintSinp[`LAT:0]; +//wire [31:0] sqrtOneMinusUz2[`LAT:0]; +//wire [31:0] sintCospSqrtOneMinusUz2[`LAT:0]; +//wire [31:0] uxCost[`LAT:0]; +//wire [31:0] uzCost[`LAT:0]; +//wire [31:0] sqrtOneMinusUz2_inv[`LAT:0]; +//wire [31:0] uxNumerator[`LAT:0]; +//wire [31:0] uyNumerator[`LAT:0]; +//wire [31:0] uyCost[`LAT:0]; +//wire [31:0] uxQuotient[`LAT:0]; +//wire [31:0] uyQuotient[`LAT:0]; +//wire [31:0] sint[37:0]; +wire [32-1:0] sint__0; +wire [32-1:0] sint__1; +wire [32-1:0] sint__2; +wire [32-1:0] sint__3; +wire [32-1:0] sint__4; +wire [32-1:0] sint__5; +wire [32-1:0] sint__6; +wire [32-1:0] sint__7; +wire [32-1:0] sint__8; +wire [32-1:0] sint__9; +wire [32-1:0] sint__10; +wire [32-1:0] sint__11; +wire [32-1:0] sint__12; +wire [32-1:0] sint__13; +wire [32-1:0] sint__14; +wire [32-1:0] sint__15; +wire [32-1:0] sint__16; +wire [32-1:0] sint__17; +wire [32-1:0] sint__18; +wire [32-1:0] sint__19; +wire [32-1:0] sint__20; +wire [32-1:0] sint__21; +wire [32-1:0] sint__22; +wire [32-1:0] sint__23; +wire [32-1:0] sint__24; +wire [32-1:0] sint__25; +wire [32-1:0] sint__26; +wire [32-1:0] sint__27; +wire [32-1:0] sint__28; +wire [32-1:0] sint__29; +wire [32-1:0] sint__30; +wire [32-1:0] sint__31; +wire [32-1:0] sint__32; +wire [32-1:0] sint__33; +wire [32-1:0] sint__34; +wire [32-1:0] sint__35; +wire [32-1:0] sint__36; +wire [32-1:0] sint__37; + + + + + +//wire [31:0] cost[37:0]; + + +wire [32-1:0] cost__0; +wire [32-1:0] cost__1; +wire [32-1:0] cost__2; +wire [32-1:0] cost__3; +wire [32-1:0] cost__4; +wire [32-1:0] cost__5; +wire [32-1:0] cost__6; +wire [32-1:0] cost__7; +wire [32-1:0] cost__8; +wire [32-1:0] cost__9; +wire [32-1:0] cost__10; +wire [32-1:0] cost__11; +wire [32-1:0] cost__12; +wire [32-1:0] cost__13; +wire [32-1:0] cost__14; +wire [32-1:0] cost__15; +wire [32-1:0] cost__16; +wire [32-1:0] cost__17; +wire [32-1:0] cost__18; +wire [32-1:0] cost__19; +wire [32-1:0] cost__20; +wire [32-1:0] cost__21; +wire [32-1:0] cost__22; +wire [32-1:0] cost__23; +wire [32-1:0] cost__24; +wire [32-1:0] cost__25; +wire [32-1:0] cost__26; +wire [32-1:0] cost__27; +wire [32-1:0] cost__28; +wire [32-1:0] cost__29; +wire [32-1:0] cost__30; +wire [32-1:0] cost__31; +wire [32-1:0] cost__32; +wire [32-1:0] cost__33; +wire [32-1:0] cost__34; +wire [32-1:0] cost__35; +wire [32-1:0] cost__36; +wire [32-1:0] cost__37; + + +//wire [31:0] sinp[37:0]; + + +wire [32-1:0] sinp__0; +wire [32-1:0] sinp__1; +wire [32-1:0] sinp__2; +wire [32-1:0] sinp__3; +wire [32-1:0] sinp__4; +wire [32-1:0] sinp__5; +wire [32-1:0] sinp__6; +wire [32-1:0] sinp__7; +wire [32-1:0] sinp__8; +wire [32-1:0] sinp__9; +wire [32-1:0] sinp__10; +wire [32-1:0] sinp__11; +wire [32-1:0] sinp__12; +wire [32-1:0] sinp__13; +wire [32-1:0] sinp__14; +wire [32-1:0] sinp__15; +wire [32-1:0] sinp__16; +wire [32-1:0] sinp__17; +wire [32-1:0] sinp__18; +wire [32-1:0] sinp__19; +wire [32-1:0] sinp__20; +wire [32-1:0] sinp__21; +wire [32-1:0] sinp__22; +wire [32-1:0] sinp__23; +wire [32-1:0] sinp__24; +wire [32-1:0] sinp__25; +wire [32-1:0] sinp__26; +wire [32-1:0] sinp__27; +wire [32-1:0] sinp__28; +wire [32-1:0] sinp__29; +wire [32-1:0] sinp__30; +wire [32-1:0] sinp__31; +wire [32-1:0] sinp__32; +wire [32-1:0] sinp__33; +wire [32-1:0] sinp__34; +wire [32-1:0] sinp__35; +wire [32-1:0] sinp__36; +wire [32-1:0] sinp__37; + + +//wire [31:0] cosp[37:0]; + + +wire [32-1:0] cosp__0; +wire [32-1:0] cosp__1; +wire [32-1:0] cosp__2; +wire [32-1:0] cosp__3; +wire [32-1:0] cosp__4; +wire [32-1:0] cosp__5; +wire [32-1:0] cosp__6; +wire [32-1:0] cosp__7; +wire [32-1:0] cosp__8; +wire [32-1:0] cosp__9; +wire [32-1:0] cosp__10; +wire [32-1:0] cosp__11; +wire [32-1:0] cosp__12; +wire [32-1:0] cosp__13; +wire [32-1:0] cosp__14; +wire [32-1:0] cosp__15; +wire [32-1:0] cosp__16; +wire [32-1:0] cosp__17; +wire [32-1:0] cosp__18; +wire [32-1:0] cosp__19; +wire [32-1:0] cosp__20; +wire [32-1:0] cosp__21; +wire [32-1:0] cosp__22; +wire [32-1:0] cosp__23; +wire [32-1:0] cosp__24; +wire [32-1:0] cosp__25; +wire [32-1:0] cosp__26; +wire [32-1:0] cosp__27; +wire [32-1:0] cosp__28; +wire [32-1:0] cosp__29; +wire [32-1:0] cosp__30; +wire [32-1:0] cosp__31; +wire [32-1:0] cosp__32; +wire [32-1:0] cosp__33; +wire [32-1:0] cosp__34; +wire [32-1:0] cosp__35; +wire [32-1:0] cosp__36; +wire [32-1:0] cosp__37; + + +//wire [31:0] sintCosp[37:0]; + +wire [32-1:0] sintCosp__0; +wire [32-1:0] sintCosp__1; +wire [32-1:0] sintCosp__2; +wire [32-1:0] sintCosp__3; +wire [32-1:0] sintCosp__4; +wire [32-1:0] sintCosp__5; +wire [32-1:0] sintCosp__6; +wire [32-1:0] sintCosp__7; +wire [32-1:0] sintCosp__8; +wire [32-1:0] sintCosp__9; +wire [32-1:0] sintCosp__10; +wire [32-1:0] sintCosp__11; +wire [32-1:0] sintCosp__12; +wire [32-1:0] sintCosp__13; +wire [32-1:0] sintCosp__14; +wire [32-1:0] sintCosp__15; +wire [32-1:0] sintCosp__16; +wire [32-1:0] sintCosp__17; +wire [32-1:0] sintCosp__18; +wire [32-1:0] sintCosp__19; +wire [32-1:0] sintCosp__20; +wire [32-1:0] sintCosp__21; +wire [32-1:0] sintCosp__22; +wire [32-1:0] sintCosp__23; +wire [32-1:0] sintCosp__24; +wire [32-1:0] sintCosp__25; +wire [32-1:0] sintCosp__26; +wire [32-1:0] sintCosp__27; +wire [32-1:0] sintCosp__28; +wire [32-1:0] sintCosp__29; +wire [32-1:0] sintCosp__30; +wire [32-1:0] sintCosp__31; +wire [32-1:0] sintCosp__32; +wire [32-1:0] sintCosp__33; +wire [32-1:0] sintCosp__34; +wire [32-1:0] sintCosp__35; +wire [32-1:0] sintCosp__36; +wire [32-1:0] sintCosp__37; + + +//wire [31:0] sintSinp[37:0]; + + +wire [32-1:0] sintSinp__0; +wire [32-1:0] sintSinp__1; +wire [32-1:0] sintSinp__2; +wire [32-1:0] sintSinp__3; +wire [32-1:0] sintSinp__4; +wire [32-1:0] sintSinp__5; +wire [32-1:0] sintSinp__6; +wire [32-1:0] sintSinp__7; +wire [32-1:0] sintSinp__8; +wire [32-1:0] sintSinp__9; +wire [32-1:0] sintSinp__10; +wire [32-1:0] sintSinp__11; +wire [32-1:0] sintSinp__12; +wire [32-1:0] sintSinp__13; +wire [32-1:0] sintSinp__14; +wire [32-1:0] sintSinp__15; +wire [32-1:0] sintSinp__16; +wire [32-1:0] sintSinp__17; +wire [32-1:0] sintSinp__18; +wire [32-1:0] sintSinp__19; +wire [32-1:0] sintSinp__20; +wire [32-1:0] sintSinp__21; +wire [32-1:0] sintSinp__22; +wire [32-1:0] sintSinp__23; +wire [32-1:0] sintSinp__24; +wire [32-1:0] sintSinp__25; +wire [32-1:0] sintSinp__26; +wire [32-1:0] sintSinp__27; +wire [32-1:0] sintSinp__28; +wire [32-1:0] sintSinp__29; +wire [32-1:0] sintSinp__30; +wire [32-1:0] sintSinp__31; +wire [32-1:0] sintSinp__32; +wire [32-1:0] sintSinp__33; +wire [32-1:0] sintSinp__34; +wire [32-1:0] sintSinp__35; +wire [32-1:0] sintSinp__36; +wire [32-1:0] sintSinp__37; + + +//wire [63:0] uz2[37:0]; + + +wire [63:0] uz2__0; +wire [63:0] uz2__1; +wire [63:0] uz2__2; +wire [63:0] uz2__3; +wire [63:0] uz2__4; +wire [63:0] uz2__5; +wire [63:0] uz2__6; +wire [63:0] uz2__7; +wire [63:0] uz2__8; +wire [63:0] uz2__9; +wire [63:0] uz2__10; +wire [63:0] uz2__11; +wire [63:0] uz2__12; +wire [63:0] uz2__13; +wire [63:0] uz2__14; +wire [63:0] uz2__15; +wire [63:0] uz2__16; +wire [63:0] uz2__17; +wire [63:0] uz2__18; +wire [63:0] uz2__19; +wire [63:0] uz2__20; +wire [63:0] uz2__21; +wire [63:0] uz2__22; +wire [63:0] uz2__23; +wire [63:0] uz2__24; +wire [63:0] uz2__25; +wire [63:0] uz2__26; +wire [63:0] uz2__27; +wire [63:0] uz2__28; +wire [63:0] uz2__29; +wire [63:0] uz2__30; +wire [63:0] uz2__31; +wire [63:0] uz2__32; +wire [63:0] uz2__33; +wire [63:0] uz2__34; +wire [63:0] uz2__35; +wire [63:0] uz2__36; +wire [63:0] uz2__37; + + +//wire [31:0] uxUz[37:0]; + +wire [32-1:0] uxUz__0; +wire [32-1:0] uxUz__1; +wire [32-1:0] uxUz__2; +wire [32-1:0] uxUz__3; +wire [32-1:0] uxUz__4; +wire [32-1:0] uxUz__5; +wire [32-1:0] uxUz__6; +wire [32-1:0] uxUz__7; +wire [32-1:0] uxUz__8; +wire [32-1:0] uxUz__9; +wire [32-1:0] uxUz__10; +wire [32-1:0] uxUz__11; +wire [32-1:0] uxUz__12; +wire [32-1:0] uxUz__13; +wire [32-1:0] uxUz__14; +wire [32-1:0] uxUz__15; +wire [32-1:0] uxUz__16; +wire [32-1:0] uxUz__17; +wire [32-1:0] uxUz__18; +wire [32-1:0] uxUz__19; +wire [32-1:0] uxUz__20; +wire [32-1:0] uxUz__21; +wire [32-1:0] uxUz__22; +wire [32-1:0] uxUz__23; +wire [32-1:0] uxUz__24; +wire [32-1:0] uxUz__25; +wire [32-1:0] uxUz__26; +wire [32-1:0] uxUz__27; +wire [32-1:0] uxUz__28; +wire [32-1:0] uxUz__29; +wire [32-1:0] uxUz__30; +wire [32-1:0] uxUz__31; +wire [32-1:0] uxUz__32; +wire [32-1:0] uxUz__33; +wire [32-1:0] uxUz__34; +wire [32-1:0] uxUz__35; +wire [32-1:0] uxUz__36; +wire [32-1:0] uxUz__37; + + +//wire [31:0] uyUz[37:0]; + + +wire [32-1:0] uyUz__0; +wire [32-1:0] uyUz__1; +wire [32-1:0] uyUz__2; +wire [32-1:0] uyUz__3; +wire [32-1:0] uyUz__4; +wire [32-1:0] uyUz__5; +wire [32-1:0] uyUz__6; +wire [32-1:0] uyUz__7; +wire [32-1:0] uyUz__8; +wire [32-1:0] uyUz__9; +wire [32-1:0] uyUz__10; +wire [32-1:0] uyUz__11; +wire [32-1:0] uyUz__12; +wire [32-1:0] uyUz__13; +wire [32-1:0] uyUz__14; +wire [32-1:0] uyUz__15; +wire [32-1:0] uyUz__16; +wire [32-1:0] uyUz__17; +wire [32-1:0] uyUz__18; +wire [32-1:0] uyUz__19; +wire [32-1:0] uyUz__20; +wire [32-1:0] uyUz__21; +wire [32-1:0] uyUz__22; +wire [32-1:0] uyUz__23; +wire [32-1:0] uyUz__24; +wire [32-1:0] uyUz__25; +wire [32-1:0] uyUz__26; +wire [32-1:0] uyUz__27; +wire [32-1:0] uyUz__28; +wire [32-1:0] uyUz__29; +wire [32-1:0] uyUz__30; +wire [32-1:0] uyUz__31; +wire [32-1:0] uyUz__32; +wire [32-1:0] uyUz__33; +wire [32-1:0] uyUz__34; +wire [32-1:0] uyUz__35; +wire [32-1:0] uyUz__36; +wire [32-1:0] uyUz__37; + +//wire [31:0] uySintSinp[37:0]; + + +wire [32-1:0] uySintSinp__0; +wire [32-1:0] uySintSinp__1; +wire [32-1:0] uySintSinp__2; +wire [32-1:0] uySintSinp__3; +wire [32-1:0] uySintSinp__4; +wire [32-1:0] uySintSinp__5; +wire [32-1:0] uySintSinp__6; +wire [32-1:0] uySintSinp__7; +wire [32-1:0] uySintSinp__8; +wire [32-1:0] uySintSinp__9; +wire [32-1:0] uySintSinp__10; +wire [32-1:0] uySintSinp__11; +wire [32-1:0] uySintSinp__12; +wire [32-1:0] uySintSinp__13; +wire [32-1:0] uySintSinp__14; +wire [32-1:0] uySintSinp__15; +wire [32-1:0] uySintSinp__16; +wire [32-1:0] uySintSinp__17; +wire [32-1:0] uySintSinp__18; +wire [32-1:0] uySintSinp__19; +wire [32-1:0] uySintSinp__20; +wire [32-1:0] uySintSinp__21; +wire [32-1:0] uySintSinp__22; +wire [32-1:0] uySintSinp__23; +wire [32-1:0] uySintSinp__24; +wire [32-1:0] uySintSinp__25; +wire [32-1:0] uySintSinp__26; +wire [32-1:0] uySintSinp__27; +wire [32-1:0] uySintSinp__28; +wire [32-1:0] uySintSinp__29; +wire [32-1:0] uySintSinp__30; +wire [32-1:0] uySintSinp__31; +wire [32-1:0] uySintSinp__32; +wire [32-1:0] uySintSinp__33; +wire [32-1:0] uySintSinp__34; +wire [32-1:0] uySintSinp__35; +wire [32-1:0] uySintSinp__36; +wire [32-1:0] uySintSinp__37; + + +//wire [63:0] oneMinusUz2[37:0]; + + +wire [63:0] oneMinusUz2__0; +wire [63:0] oneMinusUz2__1; +wire [63:0] oneMinusUz2__2; +wire [63:0] oneMinusUz2__3; +wire [63:0] oneMinusUz2__4; +wire [63:0] oneMinusUz2__5; +wire [63:0] oneMinusUz2__6; +wire [63:0] oneMinusUz2__7; +wire [63:0] oneMinusUz2__8; +wire [63:0] oneMinusUz2__9; +wire [63:0] oneMinusUz2__10; +wire [63:0] oneMinusUz2__11; +wire [63:0] oneMinusUz2__12; +wire [63:0] oneMinusUz2__13; +wire [63:0] oneMinusUz2__14; +wire [63:0] oneMinusUz2__15; +wire [63:0] oneMinusUz2__16; +wire [63:0] oneMinusUz2__17; +wire [63:0] oneMinusUz2__18; +wire [63:0] oneMinusUz2__19; +wire [63:0] oneMinusUz2__20; +wire [63:0] oneMinusUz2__21; +wire [63:0] oneMinusUz2__22; +wire [63:0] oneMinusUz2__23; +wire [63:0] oneMinusUz2__24; +wire [63:0] oneMinusUz2__25; +wire [63:0] oneMinusUz2__26; +wire [63:0] oneMinusUz2__27; +wire [63:0] oneMinusUz2__28; +wire [63:0] oneMinusUz2__29; +wire [63:0] oneMinusUz2__30; +wire [63:0] oneMinusUz2__31; +wire [63:0] oneMinusUz2__32; +wire [63:0] oneMinusUz2__33; +wire [63:0] oneMinusUz2__34; +wire [63:0] oneMinusUz2__35; +wire [63:0] oneMinusUz2__36; +wire [63:0] oneMinusUz2__37; + + +//wire [31:0] uyUzSintCosp[37:0]; + + +wire [32-1:0] uyUzSintCosp__0; +wire [32-1:0] uyUzSintCosp__1; +wire [32-1:0] uyUzSintCosp__2; +wire [32-1:0] uyUzSintCosp__3; +wire [32-1:0] uyUzSintCosp__4; +wire [32-1:0] uyUzSintCosp__5; +wire [32-1:0] uyUzSintCosp__6; +wire [32-1:0] uyUzSintCosp__7; +wire [32-1:0] uyUzSintCosp__8; +wire [32-1:0] uyUzSintCosp__9; +wire [32-1:0] uyUzSintCosp__10; +wire [32-1:0] uyUzSintCosp__11; +wire [32-1:0] uyUzSintCosp__12; +wire [32-1:0] uyUzSintCosp__13; +wire [32-1:0] uyUzSintCosp__14; +wire [32-1:0] uyUzSintCosp__15; +wire [32-1:0] uyUzSintCosp__16; +wire [32-1:0] uyUzSintCosp__17; +wire [32-1:0] uyUzSintCosp__18; +wire [32-1:0] uyUzSintCosp__19; +wire [32-1:0] uyUzSintCosp__20; +wire [32-1:0] uyUzSintCosp__21; +wire [32-1:0] uyUzSintCosp__22; +wire [32-1:0] uyUzSintCosp__23; +wire [32-1:0] uyUzSintCosp__24; +wire [32-1:0] uyUzSintCosp__25; +wire [32-1:0] uyUzSintCosp__26; +wire [32-1:0] uyUzSintCosp__27; +wire [32-1:0] uyUzSintCosp__28; +wire [32-1:0] uyUzSintCosp__29; +wire [32-1:0] uyUzSintCosp__30; +wire [32-1:0] uyUzSintCosp__31; +wire [32-1:0] uyUzSintCosp__32; +wire [32-1:0] uyUzSintCosp__33; +wire [32-1:0] uyUzSintCosp__34; +wire [32-1:0] uyUzSintCosp__35; +wire [32-1:0] uyUzSintCosp__36; +wire [32-1:0] uyUzSintCosp__37; + + +//wire [31:0] uxUzSintCosp[37:0]; + + +wire [32-1:0] uxUzSintCosp__0; +wire [32-1:0] uxUzSintCosp__1; +wire [32-1:0] uxUzSintCosp__2; +wire [32-1:0] uxUzSintCosp__3; +wire [32-1:0] uxUzSintCosp__4; +wire [32-1:0] uxUzSintCosp__5; +wire [32-1:0] uxUzSintCosp__6; +wire [32-1:0] uxUzSintCosp__7; +wire [32-1:0] uxUzSintCosp__8; +wire [32-1:0] uxUzSintCosp__9; +wire [32-1:0] uxUzSintCosp__10; +wire [32-1:0] uxUzSintCosp__11; +wire [32-1:0] uxUzSintCosp__12; +wire [32-1:0] uxUzSintCosp__13; +wire [32-1:0] uxUzSintCosp__14; +wire [32-1:0] uxUzSintCosp__15; +wire [32-1:0] uxUzSintCosp__16; +wire [32-1:0] uxUzSintCosp__17; +wire [32-1:0] uxUzSintCosp__18; +wire [32-1:0] uxUzSintCosp__19; +wire [32-1:0] uxUzSintCosp__20; +wire [32-1:0] uxUzSintCosp__21; +wire [32-1:0] uxUzSintCosp__22; +wire [32-1:0] uxUzSintCosp__23; +wire [32-1:0] uxUzSintCosp__24; +wire [32-1:0] uxUzSintCosp__25; +wire [32-1:0] uxUzSintCosp__26; +wire [32-1:0] uxUzSintCosp__27; +wire [32-1:0] uxUzSintCosp__28; +wire [32-1:0] uxUzSintCosp__29; +wire [32-1:0] uxUzSintCosp__30; +wire [32-1:0] uxUzSintCosp__31; +wire [32-1:0] uxUzSintCosp__32; +wire [32-1:0] uxUzSintCosp__33; +wire [32-1:0] uxUzSintCosp__34; +wire [32-1:0] uxUzSintCosp__35; +wire [32-1:0] uxUzSintCosp__36; +wire [32-1:0] uxUzSintCosp__37; + + +//wire [31:0] uxSintSinp[37:0]; + +wire [32-1:0] uxSintSinp__0; +wire [32-1:0] uxSintSinp__1; +wire [32-1:0] uxSintSinp__2; +wire [32-1:0] uxSintSinp__3; +wire [32-1:0] uxSintSinp__4; +wire [32-1:0] uxSintSinp__5; +wire [32-1:0] uxSintSinp__6; +wire [32-1:0] uxSintSinp__7; +wire [32-1:0] uxSintSinp__8; +wire [32-1:0] uxSintSinp__9; +wire [32-1:0] uxSintSinp__10; +wire [32-1:0] uxSintSinp__11; +wire [32-1:0] uxSintSinp__12; +wire [32-1:0] uxSintSinp__13; +wire [32-1:0] uxSintSinp__14; +wire [32-1:0] uxSintSinp__15; +wire [32-1:0] uxSintSinp__16; +wire [32-1:0] uxSintSinp__17; +wire [32-1:0] uxSintSinp__18; +wire [32-1:0] uxSintSinp__19; +wire [32-1:0] uxSintSinp__20; +wire [32-1:0] uxSintSinp__21; +wire [32-1:0] uxSintSinp__22; +wire [32-1:0] uxSintSinp__23; +wire [32-1:0] uxSintSinp__24; +wire [32-1:0] uxSintSinp__25; +wire [32-1:0] uxSintSinp__26; +wire [32-1:0] uxSintSinp__27; +wire [32-1:0] uxSintSinp__28; +wire [32-1:0] uxSintSinp__29; +wire [32-1:0] uxSintSinp__30; +wire [32-1:0] uxSintSinp__31; +wire [32-1:0] uxSintSinp__32; +wire [32-1:0] uxSintSinp__33; +wire [32-1:0] uxSintSinp__34; +wire [32-1:0] uxSintSinp__35; +wire [32-1:0] uxSintSinp__36; +wire [32-1:0] uxSintSinp__37; + + +//wire [31:0] sqrtOneMinusUz2[37:0]; + +wire [32-1:0] sqrtOneMinusUz2__0; +wire [32-1:0] sqrtOneMinusUz2__1; +wire [32-1:0] sqrtOneMinusUz2__2; +wire [32-1:0] sqrtOneMinusUz2__3; +wire [32-1:0] sqrtOneMinusUz2__4; +wire [32-1:0] sqrtOneMinusUz2__5; +wire [32-1:0] sqrtOneMinusUz2__6; +wire [32-1:0] sqrtOneMinusUz2__7; +wire [32-1:0] sqrtOneMinusUz2__8; +wire [32-1:0] sqrtOneMinusUz2__9; +wire [32-1:0] sqrtOneMinusUz2__10; +wire [32-1:0] sqrtOneMinusUz2__11; +wire [32-1:0] sqrtOneMinusUz2__12; +wire [32-1:0] sqrtOneMinusUz2__13; +wire [32-1:0] sqrtOneMinusUz2__14; +wire [32-1:0] sqrtOneMinusUz2__15; +wire [32-1:0] sqrtOneMinusUz2__16; +wire [32-1:0] sqrtOneMinusUz2__17; +wire [32-1:0] sqrtOneMinusUz2__18; +wire [32-1:0] sqrtOneMinusUz2__19; +wire [32-1:0] sqrtOneMinusUz2__20; +wire [32-1:0] sqrtOneMinusUz2__21; +wire [32-1:0] sqrtOneMinusUz2__22; +wire [32-1:0] sqrtOneMinusUz2__23; +wire [32-1:0] sqrtOneMinusUz2__24; +wire [32-1:0] sqrtOneMinusUz2__25; +wire [32-1:0] sqrtOneMinusUz2__26; +wire [32-1:0] sqrtOneMinusUz2__27; +wire [32-1:0] sqrtOneMinusUz2__28; +wire [32-1:0] sqrtOneMinusUz2__29; +wire [32-1:0] sqrtOneMinusUz2__30; +wire [32-1:0] sqrtOneMinusUz2__31; +wire [32-1:0] sqrtOneMinusUz2__32; +wire [32-1:0] sqrtOneMinusUz2__33; +wire [32-1:0] sqrtOneMinusUz2__34; +wire [32-1:0] sqrtOneMinusUz2__35; +wire [32-1:0] sqrtOneMinusUz2__36; +wire [32-1:0] sqrtOneMinusUz2__37; + +//wire [31:0] sintCospSqrtOneMinusUz2[37:0]; + + +wire [32-1:0] sintCospSqrtOneMinusUz2__0; +wire [32-1:0] sintCospSqrtOneMinusUz2__1; +wire [32-1:0] sintCospSqrtOneMinusUz2__2; +wire [32-1:0] sintCospSqrtOneMinusUz2__3; +wire [32-1:0] sintCospSqrtOneMinusUz2__4; +wire [32-1:0] sintCospSqrtOneMinusUz2__5; +wire [32-1:0] sintCospSqrtOneMinusUz2__6; +wire [32-1:0] sintCospSqrtOneMinusUz2__7; +wire [32-1:0] sintCospSqrtOneMinusUz2__8; +wire [32-1:0] sintCospSqrtOneMinusUz2__9; +wire [32-1:0] sintCospSqrtOneMinusUz2__10; +wire [32-1:0] sintCospSqrtOneMinusUz2__11; +wire [32-1:0] sintCospSqrtOneMinusUz2__12; +wire [32-1:0] sintCospSqrtOneMinusUz2__13; +wire [32-1:0] sintCospSqrtOneMinusUz2__14; +wire [32-1:0] sintCospSqrtOneMinusUz2__15; +wire [32-1:0] sintCospSqrtOneMinusUz2__16; +wire [32-1:0] sintCospSqrtOneMinusUz2__17; +wire [32-1:0] sintCospSqrtOneMinusUz2__18; +wire [32-1:0] sintCospSqrtOneMinusUz2__19; +wire [32-1:0] sintCospSqrtOneMinusUz2__20; +wire [32-1:0] sintCospSqrtOneMinusUz2__21; +wire [32-1:0] sintCospSqrtOneMinusUz2__22; +wire [32-1:0] sintCospSqrtOneMinusUz2__23; +wire [32-1:0] sintCospSqrtOneMinusUz2__24; +wire [32-1:0] sintCospSqrtOneMinusUz2__25; +wire [32-1:0] sintCospSqrtOneMinusUz2__26; +wire [32-1:0] sintCospSqrtOneMinusUz2__27; +wire [32-1:0] sintCospSqrtOneMinusUz2__28; +wire [32-1:0] sintCospSqrtOneMinusUz2__29; +wire [32-1:0] sintCospSqrtOneMinusUz2__30; +wire [32-1:0] sintCospSqrtOneMinusUz2__31; +wire [32-1:0] sintCospSqrtOneMinusUz2__32; +wire [32-1:0] sintCospSqrtOneMinusUz2__33; +wire [32-1:0] sintCospSqrtOneMinusUz2__34; +wire [32-1:0] sintCospSqrtOneMinusUz2__35; +wire [32-1:0] sintCospSqrtOneMinusUz2__36; +wire [32-1:0] sintCospSqrtOneMinusUz2__37; + +//wire [31:0] uxCost[37:0]; + + +wire [32-1:0] uxCost__0; +wire [32-1:0] uxCost__1; +wire [32-1:0] uxCost__2; +wire [32-1:0] uxCost__3; +wire [32-1:0] uxCost__4; +wire [32-1:0] uxCost__5; +wire [32-1:0] uxCost__6; +wire [32-1:0] uxCost__7; +wire [32-1:0] uxCost__8; +wire [32-1:0] uxCost__9; +wire [32-1:0] uxCost__10; +wire [32-1:0] uxCost__11; +wire [32-1:0] uxCost__12; +wire [32-1:0] uxCost__13; +wire [32-1:0] uxCost__14; +wire [32-1:0] uxCost__15; +wire [32-1:0] uxCost__16; +wire [32-1:0] uxCost__17; +wire [32-1:0] uxCost__18; +wire [32-1:0] uxCost__19; +wire [32-1:0] uxCost__20; +wire [32-1:0] uxCost__21; +wire [32-1:0] uxCost__22; +wire [32-1:0] uxCost__23; +wire [32-1:0] uxCost__24; +wire [32-1:0] uxCost__25; +wire [32-1:0] uxCost__26; +wire [32-1:0] uxCost__27; +wire [32-1:0] uxCost__28; +wire [32-1:0] uxCost__29; +wire [32-1:0] uxCost__30; +wire [32-1:0] uxCost__31; +wire [32-1:0] uxCost__32; +wire [32-1:0] uxCost__33; +wire [32-1:0] uxCost__34; +wire [32-1:0] uxCost__35; +wire [32-1:0] uxCost__36; +wire [32-1:0] uxCost__37; + +//wire [31:0] uzCost[37:0]; + + +wire [32-1:0] uzCost__0; +wire [32-1:0] uzCost__1; +wire [32-1:0] uzCost__2; +wire [32-1:0] uzCost__3; +wire [32-1:0] uzCost__4; +wire [32-1:0] uzCost__5; +wire [32-1:0] uzCost__6; +wire [32-1:0] uzCost__7; +wire [32-1:0] uzCost__8; +wire [32-1:0] uzCost__9; +wire [32-1:0] uzCost__10; +wire [32-1:0] uzCost__11; +wire [32-1:0] uzCost__12; +wire [32-1:0] uzCost__13; +wire [32-1:0] uzCost__14; +wire [32-1:0] uzCost__15; +wire [32-1:0] uzCost__16; +wire [32-1:0] uzCost__17; +wire [32-1:0] uzCost__18; +wire [32-1:0] uzCost__19; +wire [32-1:0] uzCost__20; +wire [32-1:0] uzCost__21; +wire [32-1:0] uzCost__22; +wire [32-1:0] uzCost__23; +wire [32-1:0] uzCost__24; +wire [32-1:0] uzCost__25; +wire [32-1:0] uzCost__26; +wire [32-1:0] uzCost__27; +wire [32-1:0] uzCost__28; +wire [32-1:0] uzCost__29; +wire [32-1:0] uzCost__30; +wire [32-1:0] uzCost__31; +wire [32-1:0] uzCost__32; +wire [32-1:0] uzCost__33; +wire [32-1:0] uzCost__34; +wire [32-1:0] uzCost__35; +wire [32-1:0] uzCost__36; +wire [32-1:0] uzCost__37; + + +//wire [31:0] sqrtOneMinusUz2_inv[37:0]; + + +wire [32-1:0] sqrtOneMinusUz2_inv__0; +wire [32-1:0] sqrtOneMinusUz2_inv__1; +wire [32-1:0] sqrtOneMinusUz2_inv__2; +wire [32-1:0] sqrtOneMinusUz2_inv__3; +wire [32-1:0] sqrtOneMinusUz2_inv__4; +wire [32-1:0] sqrtOneMinusUz2_inv__5; +wire [32-1:0] sqrtOneMinusUz2_inv__6; +wire [32-1:0] sqrtOneMinusUz2_inv__7; +wire [32-1:0] sqrtOneMinusUz2_inv__8; +wire [32-1:0] sqrtOneMinusUz2_inv__9; +wire [32-1:0] sqrtOneMinusUz2_inv__10; +wire [32-1:0] sqrtOneMinusUz2_inv__11; +wire [32-1:0] sqrtOneMinusUz2_inv__12; +wire [32-1:0] sqrtOneMinusUz2_inv__13; +wire [32-1:0] sqrtOneMinusUz2_inv__14; +wire [32-1:0] sqrtOneMinusUz2_inv__15; +wire [32-1:0] sqrtOneMinusUz2_inv__16; +wire [32-1:0] sqrtOneMinusUz2_inv__17; +wire [32-1:0] sqrtOneMinusUz2_inv__18; +wire [32-1:0] sqrtOneMinusUz2_inv__19; +wire [32-1:0] sqrtOneMinusUz2_inv__20; +wire [32-1:0] sqrtOneMinusUz2_inv__21; +wire [32-1:0] sqrtOneMinusUz2_inv__22; +wire [32-1:0] sqrtOneMinusUz2_inv__23; +wire [32-1:0] sqrtOneMinusUz2_inv__24; +wire [32-1:0] sqrtOneMinusUz2_inv__25; +wire [32-1:0] sqrtOneMinusUz2_inv__26; +wire [32-1:0] sqrtOneMinusUz2_inv__27; +wire [32-1:0] sqrtOneMinusUz2_inv__28; +wire [32-1:0] sqrtOneMinusUz2_inv__29; +wire [32-1:0] sqrtOneMinusUz2_inv__30; +wire [32-1:0] sqrtOneMinusUz2_inv__31; +wire [32-1:0] sqrtOneMinusUz2_inv__32; +wire [32-1:0] sqrtOneMinusUz2_inv__33; +wire [32-1:0] sqrtOneMinusUz2_inv__34; +wire [32-1:0] sqrtOneMinusUz2_inv__35; +wire [32-1:0] sqrtOneMinusUz2_inv__36; +wire [32-1:0] sqrtOneMinusUz2_inv__37; + +//wire [31:0] uxNumerator[37:0]; + + +wire [32-1:0] uxNumerator__0; +wire [32-1:0] uxNumerator__1; +wire [32-1:0] uxNumerator__2; +wire [32-1:0] uxNumerator__3; +wire [32-1:0] uxNumerator__4; +wire [32-1:0] uxNumerator__5; +wire [32-1:0] uxNumerator__6; +wire [32-1:0] uxNumerator__7; +wire [32-1:0] uxNumerator__8; +wire [32-1:0] uxNumerator__9; +wire [32-1:0] uxNumerator__10; +wire [32-1:0] uxNumerator__11; +wire [32-1:0] uxNumerator__12; +wire [32-1:0] uxNumerator__13; +wire [32-1:0] uxNumerator__14; +wire [32-1:0] uxNumerator__15; +wire [32-1:0] uxNumerator__16; +wire [32-1:0] uxNumerator__17; +wire [32-1:0] uxNumerator__18; +wire [32-1:0] uxNumerator__19; +wire [32-1:0] uxNumerator__20; +wire [32-1:0] uxNumerator__21; +wire [32-1:0] uxNumerator__22; +wire [32-1:0] uxNumerator__23; +wire [32-1:0] uxNumerator__24; +wire [32-1:0] uxNumerator__25; +wire [32-1:0] uxNumerator__26; +wire [32-1:0] uxNumerator__27; +wire [32-1:0] uxNumerator__28; +wire [32-1:0] uxNumerator__29; +wire [32-1:0] uxNumerator__30; +wire [32-1:0] uxNumerator__31; +wire [32-1:0] uxNumerator__32; +wire [32-1:0] uxNumerator__33; +wire [32-1:0] uxNumerator__34; +wire [32-1:0] uxNumerator__35; +wire [32-1:0] uxNumerator__36; +wire [32-1:0] uxNumerator__37; + +//wire [31:0] uyNumerator[37:0]; + + +wire [32-1:0] uyNumerator__0; +wire [32-1:0] uyNumerator__1; +wire [32-1:0] uyNumerator__2; +wire [32-1:0] uyNumerator__3; +wire [32-1:0] uyNumerator__4; +wire [32-1:0] uyNumerator__5; +wire [32-1:0] uyNumerator__6; +wire [32-1:0] uyNumerator__7; +wire [32-1:0] uyNumerator__8; +wire [32-1:0] uyNumerator__9; +wire [32-1:0] uyNumerator__10; +wire [32-1:0] uyNumerator__11; +wire [32-1:0] uyNumerator__12; +wire [32-1:0] uyNumerator__13; +wire [32-1:0] uyNumerator__14; +wire [32-1:0] uyNumerator__15; +wire [32-1:0] uyNumerator__16; +wire [32-1:0] uyNumerator__17; +wire [32-1:0] uyNumerator__18; +wire [32-1:0] uyNumerator__19; +wire [32-1:0] uyNumerator__20; +wire [32-1:0] uyNumerator__21; +wire [32-1:0] uyNumerator__22; +wire [32-1:0] uyNumerator__23; +wire [32-1:0] uyNumerator__24; +wire [32-1:0] uyNumerator__25; +wire [32-1:0] uyNumerator__26; +wire [32-1:0] uyNumerator__27; +wire [32-1:0] uyNumerator__28; +wire [32-1:0] uyNumerator__29; +wire [32-1:0] uyNumerator__30; +wire [32-1:0] uyNumerator__31; +wire [32-1:0] uyNumerator__32; +wire [32-1:0] uyNumerator__33; +wire [32-1:0] uyNumerator__34; +wire [32-1:0] uyNumerator__35; +wire [32-1:0] uyNumerator__36; +wire [32-1:0] uyNumerator__37; + +//wire [31:0] uyCost[37:0]; + + +wire [32-1:0] uyCost__0; +wire [32-1:0] uyCost__1; +wire [32-1:0] uyCost__2; +wire [32-1:0] uyCost__3; +wire [32-1:0] uyCost__4; +wire [32-1:0] uyCost__5; +wire [32-1:0] uyCost__6; +wire [32-1:0] uyCost__7; +wire [32-1:0] uyCost__8; +wire [32-1:0] uyCost__9; +wire [32-1:0] uyCost__10; +wire [32-1:0] uyCost__11; +wire [32-1:0] uyCost__12; +wire [32-1:0] uyCost__13; +wire [32-1:0] uyCost__14; +wire [32-1:0] uyCost__15; +wire [32-1:0] uyCost__16; +wire [32-1:0] uyCost__17; +wire [32-1:0] uyCost__18; +wire [32-1:0] uyCost__19; +wire [32-1:0] uyCost__20; +wire [32-1:0] uyCost__21; +wire [32-1:0] uyCost__22; +wire [32-1:0] uyCost__23; +wire [32-1:0] uyCost__24; +wire [32-1:0] uyCost__25; +wire [32-1:0] uyCost__26; +wire [32-1:0] uyCost__27; +wire [32-1:0] uyCost__28; +wire [32-1:0] uyCost__29; +wire [32-1:0] uyCost__30; +wire [32-1:0] uyCost__31; +wire [32-1:0] uyCost__32; +wire [32-1:0] uyCost__33; +wire [32-1:0] uyCost__34; +wire [32-1:0] uyCost__35; +wire [32-1:0] uyCost__36; +wire [32-1:0] uyCost__37; + +//wire [31:0] uxQuotient[37:0]; + + +wire [32-1:0] uxQuotient__0; +wire [32-1:0] uxQuotient__1; +wire [32-1:0] uxQuotient__2; +wire [32-1:0] uxQuotient__3; +wire [32-1:0] uxQuotient__4; +wire [32-1:0] uxQuotient__5; +wire [32-1:0] uxQuotient__6; +wire [32-1:0] uxQuotient__7; +wire [32-1:0] uxQuotient__8; +wire [32-1:0] uxQuotient__9; +wire [32-1:0] uxQuotient__10; +wire [32-1:0] uxQuotient__11; +wire [32-1:0] uxQuotient__12; +wire [32-1:0] uxQuotient__13; +wire [32-1:0] uxQuotient__14; +wire [32-1:0] uxQuotient__15; +wire [32-1:0] uxQuotient__16; +wire [32-1:0] uxQuotient__17; +wire [32-1:0] uxQuotient__18; +wire [32-1:0] uxQuotient__19; +wire [32-1:0] uxQuotient__20; +wire [32-1:0] uxQuotient__21; +wire [32-1:0] uxQuotient__22; +wire [32-1:0] uxQuotient__23; +wire [32-1:0] uxQuotient__24; +wire [32-1:0] uxQuotient__25; +wire [32-1:0] uxQuotient__26; +wire [32-1:0] uxQuotient__27; +wire [32-1:0] uxQuotient__28; +wire [32-1:0] uxQuotient__29; +wire [32-1:0] uxQuotient__30; +wire [32-1:0] uxQuotient__31; +wire [32-1:0] uxQuotient__32; +wire [32-1:0] uxQuotient__33; +wire [32-1:0] uxQuotient__34; +wire [32-1:0] uxQuotient__35; +wire [32-1:0] uxQuotient__36; +wire [32-1:0] uxQuotient__37; + +//wire [31:0] uyQuotient[37:0]; + + +wire [32-1:0] uyQuotient__0; +wire [32-1:0] uyQuotient__1; +wire [32-1:0] uyQuotient__2; +wire [32-1:0] uyQuotient__3; +wire [32-1:0] uyQuotient__4; +wire [32-1:0] uyQuotient__5; +wire [32-1:0] uyQuotient__6; +wire [32-1:0] uyQuotient__7; +wire [32-1:0] uyQuotient__8; +wire [32-1:0] uyQuotient__9; +wire [32-1:0] uyQuotient__10; +wire [32-1:0] uyQuotient__11; +wire [32-1:0] uyQuotient__12; +wire [32-1:0] uyQuotient__13; +wire [32-1:0] uyQuotient__14; +wire [32-1:0] uyQuotient__15; +wire [32-1:0] uyQuotient__16; +wire [32-1:0] uyQuotient__17; +wire [32-1:0] uyQuotient__18; +wire [32-1:0] uyQuotient__19; +wire [32-1:0] uyQuotient__20; +wire [32-1:0] uyQuotient__21; +wire [32-1:0] uyQuotient__22; +wire [32-1:0] uyQuotient__23; +wire [32-1:0] uyQuotient__24; +wire [32-1:0] uyQuotient__25; +wire [32-1:0] uyQuotient__26; +wire [32-1:0] uyQuotient__27; +wire [32-1:0] uyQuotient__28; +wire [32-1:0] uyQuotient__29; +wire [32-1:0] uyQuotient__30; +wire [32-1:0] uyQuotient__31; +wire [32-1:0] uyQuotient__32; +wire [32-1:0] uyQuotient__33; +wire [32-1:0] uyQuotient__34; +wire [32-1:0] uyQuotient__35; +wire [32-1:0] uyQuotient__36; +wire [32-1:0] uyQuotient__37; + +wire [31:0] new_sint; +wire [31:0] new_cost; +wire [31:0] new_sinp; +wire [31:0] new_cosp; +wire [31:0] new_sintCosp; +wire [31:0] new_sintSinp; +wire [63:0] new_uz2; +wire [31:0] new_uxUz; +wire [31:0] new_uyUz; +wire [31:0] new_uySintSinp; +wire [63:0] new_oneMinusUz2; +wire [31:0] new_uyUzSintCosp; +wire [31:0] new_uxUzSintCosp; +wire [31:0] new_uxSintSinp; +wire [31:0] new_sqrtOneMinusUz2; +wire [31:0] new_sintCospSqrtOneMinusUz2; +wire [31:0] new_uxCost; +wire [31:0] new_uzCost; +wire [31:0] new_sqrtOneMinusUz2_inv; +wire [31:0] new_uxNumerator; +wire [31:0] new_uyNumerator; +wire [31:0] new_uyCost; +reg [31:0] new_uxQuotient; +reg [31:0] new_uyQuotient; + + +//Wiring for calculating final values +wire uxNumerOverflow; +wire uyNumerOverflow; +reg normalIncident; +wire [31:0] ux_add_1; +wire [31:0] ux_add_2; +wire uxOverflow; +wire [31:0] uy_add_1; +wire [31:0] uy_add_2; +wire uyOverflow; +wire [31:0] normalUz; +wire [31:0] uz_sub_1; +wire [31:0] uz_sub_2; +wire uzOverflow; + +wire [31:0] new_ux; +wire [31:0] new_uy; +wire [31:0] new_uz; + +wire div_overflow; +wire toAnd1_36_1; +wire toAnd1_36_2; +wire overflow1_36; +wire negOverflow1_36; +wire toAnd2_36_1; +wire toAnd2_36_2; +wire overflow2_36; +wire negOverflow2_36; + + + +//------------------Register Pipeline----------------- +//Generation Methodology: Standard block, called InternalsBlock, is +//repeated multiple times, based on the latency of the reflector and +//scatterer. This block contains the list of all internal variables +//that need to be registered and passed along in the pipeline. +// +//Previous values in the pipeline are passed to the next register on each +//clock tick. The exception comes when an internal variable gets +//calculated. Each time a new internal variable is calculated, a new +//case is added to the case statement, and instead of hooking previous +//values of that variable to next, the new, calculated values are hooked up. +// +//This method will generate many more registers than what are required, but +//it is expected that the synthesis tool will synthesize these away. +// +// +//Commenting Convention: Whenever a new value is injected into the pipe, the +//comment //Changed Value is added directly above the variable in question. +//When multiple values are calculated in a single clock cycle, multiple such +//comments are placed. Wires connected to "Changed Values" always start with +//the prefix new_. +// +//GENERATE PIPELINE +//genvar i; +//generate +// for(i=`LAT; i>0; i=i-1) begin: internalPipe +// case(i) +// +// 2: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// //Changed Value +// .i_uz2(new_uz2), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// 3: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// //Changed Value +// .i_oneMinusUz2(new_oneMinusUz2), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// 4: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// //Changed Value +// .i_uxUz(new_uxUz), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// (`SQRT+6): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// //Changed Value +// .i_sqrtOneMinusUz2(new_sqrtOneMinusUz2), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+3): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// //Changed Value +// .i_sint(new_sint), +// //Changed Value +// .i_cost(new_cost), +// //Changed Value +// .i_sinp(new_sinp), +// //Changed Value +// .i_cosp(new_cosp), +// //Changed Value +// .i_sintCosp(new_sintCosp), +// //Changed Value +// .i_sintSinp(new_sintSinp), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// //Changed Value +// .i_uyUz(new_uyUz), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+4): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// //Changed Value +// .i_uySintSinp(new_uySintSinp), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// //Changed Value +// .i_uyUzSintCosp(new_uyUzSintCosp), +// //Changed Value +// .i_uxUzSintCosp(new_uxUzSintCosp), +// //Changed Value +// .i_uxSintSinp(new_uxSintSinp), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+5): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// //Changed Value +// .i_sqrtOneMinusUz2_inv(new_sqrtOneMinusUz2_inv), +// //Changed Value +// .i_uxNumerator(new_uxNumerator), +// //Changed Value +// .i_uyNumerator(new_uyNumerator), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// (`SQRT+`DIV+6): +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// //Changed Value +// .i_sintCospSqrtOneMinusUz2(new_sintCospSqrtOneMinusUz2), +// //Changed Value +// .i_uxCost(new_uxCost), +// //Changed Value +// .i_uzCost(new_uzCost), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// //Changed Value +// .i_uyCost(new_uyCost), +// //Changed Value +// .i_uxQuotient(new_uxQuotient), +// //Changed Value +// .i_uyQuotient(new_uyQuotient), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// +// default: +// InternalsBlock pipeReg( +// //Inputs +// .clock(clock), +// .reset(reset), +// .enable(enable), +// +// .i_sint(sint[i-1]), +// .i_cost(cost[i-1]), +// .i_sinp(sinp[i-1]), +// .i_cosp(cosp[i-1]), +// .i_sintCosp(sintCosp[i-1]), +// .i_sintSinp(sintSinp[i-1]), +// .i_uz2(uz2[i-1]), +// .i_uxUz(uxUz[i-1]), +// .i_uyUz(uyUz[i-1]), +// .i_uySintSinp(uySintSinp[i-1]), +// .i_oneMinusUz2(oneMinusUz2[i-1]), +// .i_uyUzSintCosp(uyUzSintCosp[i-1]), +// .i_uxUzSintCosp(uxUzSintCosp[i-1]), +// .i_uxSintSinp(uxSintSinp[i-1]), +// .i_sqrtOneMinusUz2(sqrtOneMinusUz2[i-1]), +// .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i-1]), +// .i_uxCost(uxCost[i-1]), +// .i_uzCost(uzCost[i-1]), +// .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i-1]), +// .i_uxNumerator(uxNumerator[i-1]), +// .i_uyNumerator(uyNumerator[i-1]), +// .i_uyCost(uyCost[i-1]), +// .i_uxQuotient(uxQuotient[i-1]), +// .i_uyQuotient(uyQuotient[i-1]), +// +// //Outputs +// .o_sint(sint[i]), +// .o_cost(cost[i]), +// .o_sinp(sinp[i]), +// .o_cosp(cosp[i]), +// .o_sintCosp(sintCosp[i]), +// .o_sintSinp(sintSinp[i]), +// .o_uz2(uz2[i]), +// .o_uxUz(uxUz[i]), +// .o_uyUz(uyUz[i]), +// .o_uySintSinp(uySintSinp[i]), +// .o_oneMinusUz2(oneMinusUz2[i]), +// .o_uyUzSintCosp(uyUzSintCosp[i]), +// .o_uxUzSintCosp(uxUzSintCosp[i]), +// .o_uxSintSinp(uxSintSinp[i]), +// .o_sqrtOneMinusUz2(sqrtOneMinusUz2[i]), +// .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2[i]), +// .o_uxCost(uxCost[i]), +// .o_uzCost(uzCost[i]), +// .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv[i]), +// .o_uxNumerator(uxNumerator[i]), +// .o_uyNumerator(uyNumerator[i]), +// .o_uyCost(uyCost[i]), +// .o_uxQuotient(uxQuotient[i]), +// .o_uyQuotient(uyQuotient[i]) +// ); +// endcase +// end +//endgenerate + +//Expanded generate loop: +//special cases first + //forloop2 + InternalsBlock pipeReg2( + //Inputs + .clock(clock), + .reset(reset), + .enable(enable), + + .i_sint(sint__1), + .i_cost(cost__1), + .i_sinp(sinp__1), + .i_cosp(cosp__1), + .i_sintCosp(sintCosp__1), + .i_sintSinp(sintSinp__1), + //Changed Value + .i_uz2(new_uz2), + .i_uxUz(uxUz__1), + .i_uyUz(uyUz__1), + .i_uySintSinp(uySintSinp__1), + .i_oneMinusUz2(oneMinusUz2__1), + .i_uyUzSintCosp(uyUzSintCosp__1), + .i_uxUzSintCosp(uxUzSintCosp__1), + .i_uxSintSinp(uxSintSinp__1), + .i_sqrtOneMinusUz2(sqrtOneMinusUz2__1), + .i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__1), + .i_uxCost(uxCost__1), + .i_uzCost(uzCost__1), + .i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__1), + .i_uxNumerator(uxNumerator__1), + .i_uyNumerator(uyNumerator__1), + .i_uyCost(uyCost__1), + .i_uxQuotient(uxQuotient__1), + .i_uyQuotient(uyQuotient__1), + + //Outputs + .o_sint(sint__2), + .o_cost(cost__2), + .o_sinp(sinp__2), + .o_cosp(cosp__2), + .o_sintCosp(sintCosp__2), + .o_sintSinp(sintSinp__2), + .o_uz2(uz2__2), + .o_uxUz(uxUz__2), + .o_uyUz(uyUz__2), + .o_uySintSinp(uySintSinp__2), + .o_oneMinusUz2(oneMinusUz2__2), + .o_uyUzSintCosp(uyUzSintCosp__2), + .o_uxUzSintCosp(uxUzSintCosp__2), + .o_uxSintSinp(uxSintSinp__2), + .o_sqrtOneMinusUz2(sqrtOneMinusUz2__2), + .o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__2), + .o_uxCost(uxCost__2), + .o_uzCost(uzCost__2), + .o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__2), + .o_uxNumerator(uxNumerator__2), + .o_uyNumerator(uyNumerator__2), + .o_uyCost(uyCost__2), + .o_uxQuotient(uxQuotient__2), + .o_uyQuotient(uyQuotient__2) + ); + + + // forloop3 + InternalsBlock pipeReg3( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__2), +.i_cost(cost__2), +.i_sinp(sinp__2), +.i_cosp(cosp__2), +.i_sintCosp(sintCosp__2), +.i_sintSinp(sintSinp__2), +.i_uz2(uz2__2), +.i_uxUz(uxUz__2), +.i_uyUz(uyUz__2), +.i_uySintSinp(uySintSinp__2), +//changed +.i_oneMinusUz2(new_oneMinusUz2), +.i_uyUzSintCosp(uyUzSintCosp__2), +.i_uxUzSintCosp(uxUzSintCosp__2), +.i_uxSintSinp(uxSintSinp__2), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__2), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__2), +.i_uxCost(uxCost__2), +.i_uzCost(uzCost__2), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__2), +.i_uxNumerator(uxNumerator__2), +.i_uyNumerator(uyNumerator__2), +.i_uyCost(uyCost__2), +.i_uxQuotient(uxQuotient__2), +.i_uyQuotient(uyQuotient__2), +//Outputs +.o_sint(sint__3), +.o_cost(cost__3), +.o_sinp(sinp__3), +.o_cosp(cosp__3), +.o_sintCosp(sintCosp__3), +.o_sintSinp(sintSinp__3), +.o_uz2(uz2__3), +.o_uxUz(uxUz__3), +.o_uyUz(uyUz__3), +.o_uySintSinp(uySintSinp__3), +.o_oneMinusUz2(oneMinusUz2__3), +.o_uyUzSintCosp(uyUzSintCosp__3), +.o_uxUzSintCosp(uxUzSintCosp__3), +.o_uxSintSinp(uxSintSinp__3), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__3), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__3), +.o_uxCost(uxCost__3), +.o_uzCost(uzCost__3), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__3), +.o_uxNumerator(uxNumerator__3), +.o_uyNumerator(uyNumerator__3), +.o_uyCost(uyCost__3), +.o_uxQuotient(uxQuotient__3), +.o_uyQuotient(uyQuotient__3) +); + + //forloop4: + InternalsBlock pipeReg4( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__3), +.i_cost(cost__3), +.i_sinp(sinp__3), +.i_cosp(cosp__3), +.i_sintCosp(sintCosp__3), +.i_sintSinp(sintSinp__3), +.i_uz2(uz2__3), +//changed +.i_uxUz(new_uxUz), +.i_uyUz(uyUz__3), +.i_uySintSinp(uySintSinp__3), +.i_oneMinusUz2(oneMinusUz2__3), +.i_uyUzSintCosp(uyUzSintCosp__3), +.i_uxUzSintCosp(uxUzSintCosp__3), +.i_uxSintSinp(uxSintSinp__3), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__3), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__3), +.i_uxCost(uxCost__3), +.i_uzCost(uzCost__3), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__3), +.i_uxNumerator(uxNumerator__3), +.i_uyNumerator(uyNumerator__3), +.i_uyCost(uyCost__3), +.i_uxQuotient(uxQuotient__3), +.i_uyQuotient(uyQuotient__3), +//Outputs +.o_sint(sint__4), +.o_cost(cost__4), +.o_sinp(sinp__4), +.o_cosp(cosp__4), +.o_sintCosp(sintCosp__4), +.o_sintSinp(sintSinp__4), +.o_uz2(uz2__4), +.o_uxUz(uxUz__4), +.o_uyUz(uyUz__4), +.o_uySintSinp(uySintSinp__4), +.o_oneMinusUz2(oneMinusUz2__4), +.o_uyUzSintCosp(uyUzSintCosp__4), +.o_uxUzSintCosp(uxUzSintCosp__4), +.o_uxSintSinp(uxSintSinp__4), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__4), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__4), +.o_uxCost(uxCost__4), +.o_uzCost(uzCost__4), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__4), +.o_uxNumerator(uxNumerator__4), +.o_uyNumerator(uyNumerator__4), +.o_uyCost(uyCost__4), +.o_uxQuotient(uxQuotient__4), +.o_uyQuotient(uyQuotient__4) +); + +InternalsBlock pipeReg16( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__15), +.i_cost(cost__15), +.i_sinp(sinp__15), +.i_cosp(cosp__15), +.i_sintCosp(sintCosp__15), +.i_sintSinp(sintSinp__15), +.i_uz2(uz2__15), +.i_uxUz(uxUz__15), +.i_uyUz(uyUz__15), +.i_uySintSinp(uySintSinp__15), +.i_oneMinusUz2(oneMinusUz2__15), +.i_uyUzSintCosp(uyUzSintCosp__15), +.i_uxUzSintCosp(uxUzSintCosp__15), +.i_uxSintSinp(uxSintSinp__15), +//changed +.i_sqrtOneMinusUz2(new_sqrtOneMinusUz2), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__15), +.i_uxCost(uxCost__15), +.i_uzCost(uzCost__15), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__15), +.i_uxNumerator(uxNumerator__15), +.i_uyNumerator(uyNumerator__15), +.i_uyCost(uyCost__15), +.i_uxQuotient(uxQuotient__15), +.i_uyQuotient(uyQuotient__15), +//Outputs +.o_sint(sint__16), +.o_cost(cost__16), +.o_sinp(sinp__16), +.o_cosp(cosp__16), +.o_sintCosp(sintCosp__16), +.o_sintSinp(sintSinp__16), +.o_uz2(uz2__16), +.o_uxUz(uxUz__16), +.o_uyUz(uyUz__16), +.o_uySintSinp(uySintSinp__16), +.o_oneMinusUz2(oneMinusUz2__16), +.o_uyUzSintCosp(uyUzSintCosp__16), +.o_uxUzSintCosp(uxUzSintCosp__16), +.o_uxSintSinp(uxSintSinp__16), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__16), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__16), +.o_uxCost(uxCost__16), +.o_uzCost(uzCost__16), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__16), +.o_uxNumerator(uxNumerator__16), +.o_uyNumerator(uyNumerator__16), +.o_uyCost(uyCost__16), +.o_uxQuotient(uxQuotient__16), +.o_uyQuotient(uyQuotient__16) +); + + //forloop 33 (10+20+3): + +InternalsBlock pipeReg33( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +//changed +.i_sint(new_sint), +//changed +.i_cost(new_cost), +//changed +.i_sinp(new_sinp), +//changed +.i_cosp(new_cosp), +//changed +.i_sintCosp(new_sintCosp), +//changed +.i_sintSinp(new_sintSinp), +.i_uz2(uz2__32), +.i_uxUz(uxUz__32), +//changed +.i_uyUz(new_uyUz), +.i_uySintSinp(uySintSinp__32), +.i_oneMinusUz2(oneMinusUz2__32), +.i_uyUzSintCosp(uyUzSintCosp__32), +.i_uxUzSintCosp(uxUzSintCosp__32), +.i_uxSintSinp(uxSintSinp__32), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__32), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__32), +.i_uxCost(uxCost__32), +.i_uzCost(uzCost__32), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__32), +.i_uxNumerator(uxNumerator__32), +.i_uyNumerator(uyNumerator__32), +.i_uyCost(uyCost__32), +.i_uxQuotient(uxQuotient__32), +.i_uyQuotient(uyQuotient__32), +//Outputs +.o_sint(sint__33), +.o_cost(cost__33), +.o_sinp(sinp__33), +.o_cosp(cosp__33), +.o_sintCosp(sintCosp__33), +.o_sintSinp(sintSinp__33), +.o_uz2(uz2__33), +.o_uxUz(uxUz__33), +.o_uyUz(uyUz__33), +.o_uySintSinp(uySintSinp__33), +.o_oneMinusUz2(oneMinusUz2__33), +.o_uyUzSintCosp(uyUzSintCosp__33), +.o_uxUzSintCosp(uxUzSintCosp__33), +.o_uxSintSinp(uxSintSinp__33), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__33), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__33), +.o_uxCost(uxCost__33), +.o_uzCost(uzCost__33), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__33), +.o_uxNumerator(uxNumerator__33), +.o_uyNumerator(uyNumerator__33), +.o_uyCost(uyCost__33), +.o_uxQuotient(uxQuotient__33), +.o_uyQuotient(uyQuotient__33) +); + + //forloop34 (10+20+4): + +InternalsBlock pipeReg34( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__33), +.i_cost(cost__33), +.i_sinp(sinp__33), +.i_cosp(cosp__33), +.i_sintCosp(sintCosp__33), +.i_sintSinp(sintSinp__33), +.i_uz2(uz2__33), +.i_uxUz(uxUz__33), +.i_uyUz(uyUz__33), +//changed +.i_uySintSinp(new_uySintSinp), +.i_oneMinusUz2(oneMinusUz2__33), +//changed +.i_uyUzSintCosp(new_uyUzSintCosp), +//changed +.i_uxUzSintCosp(new_uxUzSintCosp), +//changed +.i_uxSintSinp(new_uxSintSinp), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__33), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__33), +.i_uxCost(uxCost__33), +.i_uzCost(uzCost__33), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__33), +.i_uxNumerator(uxNumerator__33), +.i_uyNumerator(uyNumerator__33), +.i_uyCost(uyCost__33), +.i_uxQuotient(uxQuotient__33), +.i_uyQuotient(uyQuotient__33), +//Outputs +.o_sint(sint__34), +.o_cost(cost__34), +.o_sinp(sinp__34), +.o_cosp(cosp__34), +.o_sintCosp(sintCosp__34), +.o_sintSinp(sintSinp__34), +.o_uz2(uz2__34), +.o_uxUz(uxUz__34), +.o_uyUz(uyUz__34), +.o_uySintSinp(uySintSinp__34), +.o_oneMinusUz2(oneMinusUz2__34), +.o_uyUzSintCosp(uyUzSintCosp__34), +.o_uxUzSintCosp(uxUzSintCosp__34), +.o_uxSintSinp(uxSintSinp__34), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__34), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__34), +.o_uxCost(uxCost__34), +.o_uzCost(uzCost__34), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__34), +.o_uxNumerator(uxNumerator__34), +.o_uyNumerator(uyNumerator__34), +.o_uyCost(uyCost__34), +.o_uxQuotient(uxQuotient__34), +.o_uyQuotient(uyQuotient__34) +); + + //forloop35(10+20+5): + InternalsBlock pipeReg35( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__34), +.i_cost(cost__34), +.i_sinp(sinp__34), +.i_cosp(cosp__34), +.i_sintCosp(sintCosp__34), +.i_sintSinp(sintSinp__34), +.i_uz2(uz2__34), +.i_uxUz(uxUz__34), +.i_uyUz(uyUz__34), +.i_uySintSinp(uySintSinp__34), +.i_oneMinusUz2(oneMinusUz2__34), +.i_uyUzSintCosp(uyUzSintCosp__34), +.i_uxUzSintCosp(uxUzSintCosp__34), +.i_uxSintSinp(uxSintSinp__34), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__34), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__34), +.i_uxCost(uxCost__34), +.i_uzCost(uzCost__34), +//changedval +.i_sqrtOneMinusUz2_inv(new_sqrtOneMinusUz2_inv), +//changed +.i_uxNumerator(new_uxNumerator), +//changed +.i_uyNumerator(new_uyNumerator), +.i_uyCost(uyCost__34), +.i_uxQuotient(uxQuotient__34), +.i_uyQuotient(uyQuotient__34), +//Outputs +.o_sint(sint__35), +.o_cost(cost__35), +.o_sinp(sinp__35), +.o_cosp(cosp__35), +.o_sintCosp(sintCosp__35), +.o_sintSinp(sintSinp__35), +.o_uz2(uz2__35), +.o_uxUz(uxUz__35), +.o_uyUz(uyUz__35), +.o_uySintSinp(uySintSinp__35), +.o_oneMinusUz2(oneMinusUz2__35), +.o_uyUzSintCosp(uyUzSintCosp__35), +.o_uxUzSintCosp(uxUzSintCosp__35), +.o_uxSintSinp(uxSintSinp__35), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__35), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__35), +.o_uxCost(uxCost__35), +.o_uzCost(uzCost__35), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__35), +.o_uxNumerator(uxNumerator__35), +.o_uyNumerator(uyNumerator__35), +.o_uyCost(uyCost__35), +.o_uxQuotient(uxQuotient__35), +.o_uyQuotient(uyQuotient__35) +); + + + //forloop36 (10+20+6): + +InternalsBlock pipeReg36( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__35), +.i_cost(cost__35), +.i_sinp(sinp__35), +.i_cosp(cosp__35), +.i_sintCosp(sintCosp__35), +.i_sintSinp(sintSinp__35), +.i_uz2(uz2__35), +.i_uxUz(uxUz__35), +.i_uyUz(uyUz__35), +.i_uySintSinp(uySintSinp__35), +.i_oneMinusUz2(oneMinusUz2__35), +.i_uyUzSintCosp(uyUzSintCosp__35), +.i_uxUzSintCosp(uxUzSintCosp__35), +.i_uxSintSinp(uxSintSinp__35), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__35), +//changed +.i_sintCospSqrtOneMinusUz2(new_sintCospSqrtOneMinusUz2), +//changed +.i_uxCost(new_uxCost), +//changed +.i_uzCost(new_uzCost), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__35), +.i_uxNumerator(uxNumerator__35), +.i_uyNumerator(uyNumerator__35), +//changed +.i_uyCost(new_uyCost), +//changed), +.i_uxQuotient(new_uxQuotient), +//cahgned +.i_uyQuotient(new_uyQuotient), +//Outputs +.o_sint(sint__36), +.o_cost(cost__36), +.o_sinp(sinp__36), +.o_cosp(cosp__36), +.o_sintCosp(sintCosp__36), +.o_sintSinp(sintSinp__36), +.o_uz2(uz2__36), +.o_uxUz(uxUz__36), +.o_uyUz(uyUz__36), +.o_uySintSinp(uySintSinp__36), +.o_oneMinusUz2(oneMinusUz2__36), +.o_uyUzSintCosp(uyUzSintCosp__36), +.o_uxUzSintCosp(uxUzSintCosp__36), +.o_uxSintSinp(uxSintSinp__36), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__36), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__36), +.o_uxCost(uxCost__36), +.o_uzCost(uzCost__36), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__36), +.o_uxNumerator(uxNumerator__36), +.o_uyNumerator(uyNumerator__36), +.o_uyCost(uyCost__36), +.o_uxQuotient(uxQuotient__36), +.o_uyQuotient(uyQuotient__36) +); + +InternalsBlock pipeReg37( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__36), +.i_cost(cost__36), +.i_sinp(sinp__36), +.i_cosp(cosp__36), +.i_sintCosp(sintCosp__36), +.i_sintSinp(sintSinp__36), +.i_uz2(uz2__36), +.i_uxUz(uxUz__36), +.i_uyUz(uyUz__36), +.i_uySintSinp(uySintSinp__36), +.i_oneMinusUz2(oneMinusUz2__36), +.i_uyUzSintCosp(uyUzSintCosp__36), +.i_uxUzSintCosp(uxUzSintCosp__36), +.i_uxSintSinp(uxSintSinp__36), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__36), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__36), +.i_uxCost(uxCost__36), +.i_uzCost(uzCost__36), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__36), +.i_uxNumerator(uxNumerator__36), +.i_uyNumerator(uyNumerator__36), +.i_uyCost(uyCost__36), +.i_uxQuotient(uxQuotient__36), +.i_uyQuotient(uyQuotient__36), +//Outputs +.o_sint(sint__37), +.o_cost(cost__37), +.o_sinp(sinp__37), +.o_cosp(cosp__37), +.o_sintCosp(sintCosp__37), +.o_sintSinp(sintSinp__37), +.o_uz2(uz2__37), +.o_uxUz(uxUz__37), +.o_uyUz(uyUz__37), +.o_uySintSinp(uySintSinp__37), +.o_oneMinusUz2(oneMinusUz2__37), +.o_uyUzSintCosp(uyUzSintCosp__37), +.o_uxUzSintCosp(uxUzSintCosp__37), +.o_uxSintSinp(uxSintSinp__37), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__37), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__37), +.o_uxCost(uxCost__37), +.o_uzCost(uzCost__37), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__37), +.o_uxNumerator(uxNumerator__37), +.o_uyNumerator(uyNumerator__37), +.o_uyCost(uyCost__37), +.o_uxQuotient(uxQuotient__37), +.o_uyQuotient(uyQuotient__37) +); + + + +InternalsBlock pipeReg32( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__31), +.i_cost(cost__31), +.i_sinp(sinp__31), +.i_cosp(cosp__31), +.i_sintCosp(sintCosp__31), +.i_sintSinp(sintSinp__31), +.i_uz2(uz2__31), +.i_uxUz(uxUz__31), +.i_uyUz(uyUz__31), +.i_uySintSinp(uySintSinp__31), +.i_oneMinusUz2(oneMinusUz2__31), +.i_uyUzSintCosp(uyUzSintCosp__31), +.i_uxUzSintCosp(uxUzSintCosp__31), +.i_uxSintSinp(uxSintSinp__31), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__31), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__31), +.i_uxCost(uxCost__31), +.i_uzCost(uzCost__31), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__31), +.i_uxNumerator(uxNumerator__31), +.i_uyNumerator(uyNumerator__31), +.i_uyCost(uyCost__31), +.i_uxQuotient(uxQuotient__31), +.i_uyQuotient(uyQuotient__31), +//Outputs +.o_sint(sint__32), +.o_cost(cost__32), +.o_sinp(sinp__32), +.o_cosp(cosp__32), +.o_sintCosp(sintCosp__32), +.o_sintSinp(sintSinp__32), +.o_uz2(uz2__32), +.o_uxUz(uxUz__32), +.o_uyUz(uyUz__32), +.o_uySintSinp(uySintSinp__32), +.o_oneMinusUz2(oneMinusUz2__32), +.o_uyUzSintCosp(uyUzSintCosp__32), +.o_uxUzSintCosp(uxUzSintCosp__32), +.o_uxSintSinp(uxSintSinp__32), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__32), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__32), +.o_uxCost(uxCost__32), +.o_uzCost(uzCost__32), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__32), +.o_uxNumerator(uxNumerator__32), +.o_uyNumerator(uyNumerator__32), +.o_uyCost(uyCost__32), +.o_uxQuotient(uxQuotient__32), +.o_uyQuotient(uyQuotient__32) +); + +InternalsBlock pipeReg31( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__30), +.i_cost(cost__30), +.i_sinp(sinp__30), +.i_cosp(cosp__30), +.i_sintCosp(sintCosp__30), +.i_sintSinp(sintSinp__30), +.i_uz2(uz2__30), +.i_uxUz(uxUz__30), +.i_uyUz(uyUz__30), +.i_uySintSinp(uySintSinp__30), +.i_oneMinusUz2(oneMinusUz2__30), +.i_uyUzSintCosp(uyUzSintCosp__30), +.i_uxUzSintCosp(uxUzSintCosp__30), +.i_uxSintSinp(uxSintSinp__30), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__30), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__30), +.i_uxCost(uxCost__30), +.i_uzCost(uzCost__30), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__30), +.i_uxNumerator(uxNumerator__30), +.i_uyNumerator(uyNumerator__30), +.i_uyCost(uyCost__30), +.i_uxQuotient(uxQuotient__30), +.i_uyQuotient(uyQuotient__30), +//Outputs +.o_sint(sint__31), +.o_cost(cost__31), +.o_sinp(sinp__31), +.o_cosp(cosp__31), +.o_sintCosp(sintCosp__31), +.o_sintSinp(sintSinp__31), +.o_uz2(uz2__31), +.o_uxUz(uxUz__31), +.o_uyUz(uyUz__31), +.o_uySintSinp(uySintSinp__31), +.o_oneMinusUz2(oneMinusUz2__31), +.o_uyUzSintCosp(uyUzSintCosp__31), +.o_uxUzSintCosp(uxUzSintCosp__31), +.o_uxSintSinp(uxSintSinp__31), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__31), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__31), +.o_uxCost(uxCost__31), +.o_uzCost(uzCost__31), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__31), +.o_uxNumerator(uxNumerator__31), +.o_uyNumerator(uyNumerator__31), +.o_uyCost(uyCost__31), +.o_uxQuotient(uxQuotient__31), +.o_uyQuotient(uyQuotient__31) +); + +InternalsBlock pipeReg30( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__29), +.i_cost(cost__29), +.i_sinp(sinp__29), +.i_cosp(cosp__29), +.i_sintCosp(sintCosp__29), +.i_sintSinp(sintSinp__29), +.i_uz2(uz2__29), +.i_uxUz(uxUz__29), +.i_uyUz(uyUz__29), +.i_uySintSinp(uySintSinp__29), +.i_oneMinusUz2(oneMinusUz2__29), +.i_uyUzSintCosp(uyUzSintCosp__29), +.i_uxUzSintCosp(uxUzSintCosp__29), +.i_uxSintSinp(uxSintSinp__29), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__29), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__29), +.i_uxCost(uxCost__29), +.i_uzCost(uzCost__29), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__29), +.i_uxNumerator(uxNumerator__29), +.i_uyNumerator(uyNumerator__29), +.i_uyCost(uyCost__29), +.i_uxQuotient(uxQuotient__29), +.i_uyQuotient(uyQuotient__29), +//Outputs +.o_sint(sint__30), +.o_cost(cost__30), +.o_sinp(sinp__30), +.o_cosp(cosp__30), +.o_sintCosp(sintCosp__30), +.o_sintSinp(sintSinp__30), +.o_uz2(uz2__30), +.o_uxUz(uxUz__30), +.o_uyUz(uyUz__30), +.o_uySintSinp(uySintSinp__30), +.o_oneMinusUz2(oneMinusUz2__30), +.o_uyUzSintCosp(uyUzSintCosp__30), +.o_uxUzSintCosp(uxUzSintCosp__30), +.o_uxSintSinp(uxSintSinp__30), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__30), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__30), +.o_uxCost(uxCost__30), +.o_uzCost(uzCost__30), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__30), +.o_uxNumerator(uxNumerator__30), +.o_uyNumerator(uyNumerator__30), +.o_uyCost(uyCost__30), +.o_uxQuotient(uxQuotient__30), +.o_uyQuotient(uyQuotient__30) +); + +InternalsBlock pipeReg29( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__28), +.i_cost(cost__28), +.i_sinp(sinp__28), +.i_cosp(cosp__28), +.i_sintCosp(sintCosp__28), +.i_sintSinp(sintSinp__28), +.i_uz2(uz2__28), +.i_uxUz(uxUz__28), +.i_uyUz(uyUz__28), +.i_uySintSinp(uySintSinp__28), +.i_oneMinusUz2(oneMinusUz2__28), +.i_uyUzSintCosp(uyUzSintCosp__28), +.i_uxUzSintCosp(uxUzSintCosp__28), +.i_uxSintSinp(uxSintSinp__28), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__28), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__28), +.i_uxCost(uxCost__28), +.i_uzCost(uzCost__28), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__28), +.i_uxNumerator(uxNumerator__28), +.i_uyNumerator(uyNumerator__28), +.i_uyCost(uyCost__28), +.i_uxQuotient(uxQuotient__28), +.i_uyQuotient(uyQuotient__28), +//Outputs +.o_sint(sint__29), +.o_cost(cost__29), +.o_sinp(sinp__29), +.o_cosp(cosp__29), +.o_sintCosp(sintCosp__29), +.o_sintSinp(sintSinp__29), +.o_uz2(uz2__29), +.o_uxUz(uxUz__29), +.o_uyUz(uyUz__29), +.o_uySintSinp(uySintSinp__29), +.o_oneMinusUz2(oneMinusUz2__29), +.o_uyUzSintCosp(uyUzSintCosp__29), +.o_uxUzSintCosp(uxUzSintCosp__29), +.o_uxSintSinp(uxSintSinp__29), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__29), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__29), +.o_uxCost(uxCost__29), +.o_uzCost(uzCost__29), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__29), +.o_uxNumerator(uxNumerator__29), +.o_uyNumerator(uyNumerator__29), +.o_uyCost(uyCost__29), +.o_uxQuotient(uxQuotient__29), +.o_uyQuotient(uyQuotient__29) +); + +InternalsBlock pipeReg28( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__27), +.i_cost(cost__27), +.i_sinp(sinp__27), +.i_cosp(cosp__27), +.i_sintCosp(sintCosp__27), +.i_sintSinp(sintSinp__27), +.i_uz2(uz2__27), +.i_uxUz(uxUz__27), +.i_uyUz(uyUz__27), +.i_uySintSinp(uySintSinp__27), +.i_oneMinusUz2(oneMinusUz2__27), +.i_uyUzSintCosp(uyUzSintCosp__27), +.i_uxUzSintCosp(uxUzSintCosp__27), +.i_uxSintSinp(uxSintSinp__27), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__27), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__27), +.i_uxCost(uxCost__27), +.i_uzCost(uzCost__27), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__27), +.i_uxNumerator(uxNumerator__27), +.i_uyNumerator(uyNumerator__27), +.i_uyCost(uyCost__27), +.i_uxQuotient(uxQuotient__27), +.i_uyQuotient(uyQuotient__27), +//Outputs +.o_sint(sint__28), +.o_cost(cost__28), +.o_sinp(sinp__28), +.o_cosp(cosp__28), +.o_sintCosp(sintCosp__28), +.o_sintSinp(sintSinp__28), +.o_uz2(uz2__28), +.o_uxUz(uxUz__28), +.o_uyUz(uyUz__28), +.o_uySintSinp(uySintSinp__28), +.o_oneMinusUz2(oneMinusUz2__28), +.o_uyUzSintCosp(uyUzSintCosp__28), +.o_uxUzSintCosp(uxUzSintCosp__28), +.o_uxSintSinp(uxSintSinp__28), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__28), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__28), +.o_uxCost(uxCost__28), +.o_uzCost(uzCost__28), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__28), +.o_uxNumerator(uxNumerator__28), +.o_uyNumerator(uyNumerator__28), +.o_uyCost(uyCost__28), +.o_uxQuotient(uxQuotient__28), +.o_uyQuotient(uyQuotient__28) +); + +InternalsBlock pipeReg27( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__26), +.i_cost(cost__26), +.i_sinp(sinp__26), +.i_cosp(cosp__26), +.i_sintCosp(sintCosp__26), +.i_sintSinp(sintSinp__26), +.i_uz2(uz2__26), +.i_uxUz(uxUz__26), +.i_uyUz(uyUz__26), +.i_uySintSinp(uySintSinp__26), +.i_oneMinusUz2(oneMinusUz2__26), +.i_uyUzSintCosp(uyUzSintCosp__26), +.i_uxUzSintCosp(uxUzSintCosp__26), +.i_uxSintSinp(uxSintSinp__26), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__26), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__26), +.i_uxCost(uxCost__26), +.i_uzCost(uzCost__26), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__26), +.i_uxNumerator(uxNumerator__26), +.i_uyNumerator(uyNumerator__26), +.i_uyCost(uyCost__26), +.i_uxQuotient(uxQuotient__26), +.i_uyQuotient(uyQuotient__26), +//Outputs +.o_sint(sint__27), +.o_cost(cost__27), +.o_sinp(sinp__27), +.o_cosp(cosp__27), +.o_sintCosp(sintCosp__27), +.o_sintSinp(sintSinp__27), +.o_uz2(uz2__27), +.o_uxUz(uxUz__27), +.o_uyUz(uyUz__27), +.o_uySintSinp(uySintSinp__27), +.o_oneMinusUz2(oneMinusUz2__27), +.o_uyUzSintCosp(uyUzSintCosp__27), +.o_uxUzSintCosp(uxUzSintCosp__27), +.o_uxSintSinp(uxSintSinp__27), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__27), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__27), +.o_uxCost(uxCost__27), +.o_uzCost(uzCost__27), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__27), +.o_uxNumerator(uxNumerator__27), +.o_uyNumerator(uyNumerator__27), +.o_uyCost(uyCost__27), +.o_uxQuotient(uxQuotient__27), +.o_uyQuotient(uyQuotient__27) +); + +InternalsBlock pipeReg26( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__25), +.i_cost(cost__25), +.i_sinp(sinp__25), +.i_cosp(cosp__25), +.i_sintCosp(sintCosp__25), +.i_sintSinp(sintSinp__25), +.i_uz2(uz2__25), +.i_uxUz(uxUz__25), +.i_uyUz(uyUz__25), +.i_uySintSinp(uySintSinp__25), +.i_oneMinusUz2(oneMinusUz2__25), +.i_uyUzSintCosp(uyUzSintCosp__25), +.i_uxUzSintCosp(uxUzSintCosp__25), +.i_uxSintSinp(uxSintSinp__25), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__25), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__25), +.i_uxCost(uxCost__25), +.i_uzCost(uzCost__25), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__25), +.i_uxNumerator(uxNumerator__25), +.i_uyNumerator(uyNumerator__25), +.i_uyCost(uyCost__25), +.i_uxQuotient(uxQuotient__25), +.i_uyQuotient(uyQuotient__25), +//Outputs +.o_sint(sint__26), +.o_cost(cost__26), +.o_sinp(sinp__26), +.o_cosp(cosp__26), +.o_sintCosp(sintCosp__26), +.o_sintSinp(sintSinp__26), +.o_uz2(uz2__26), +.o_uxUz(uxUz__26), +.o_uyUz(uyUz__26), +.o_uySintSinp(uySintSinp__26), +.o_oneMinusUz2(oneMinusUz2__26), +.o_uyUzSintCosp(uyUzSintCosp__26), +.o_uxUzSintCosp(uxUzSintCosp__26), +.o_uxSintSinp(uxSintSinp__26), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__26), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__26), +.o_uxCost(uxCost__26), +.o_uzCost(uzCost__26), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__26), +.o_uxNumerator(uxNumerator__26), +.o_uyNumerator(uyNumerator__26), +.o_uyCost(uyCost__26), +.o_uxQuotient(uxQuotient__26), +.o_uyQuotient(uyQuotient__26) +); + +InternalsBlock pipeReg25( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__24), +.i_cost(cost__24), +.i_sinp(sinp__24), +.i_cosp(cosp__24), +.i_sintCosp(sintCosp__24), +.i_sintSinp(sintSinp__24), +.i_uz2(uz2__24), +.i_uxUz(uxUz__24), +.i_uyUz(uyUz__24), +.i_uySintSinp(uySintSinp__24), +.i_oneMinusUz2(oneMinusUz2__24), +.i_uyUzSintCosp(uyUzSintCosp__24), +.i_uxUzSintCosp(uxUzSintCosp__24), +.i_uxSintSinp(uxSintSinp__24), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__24), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__24), +.i_uxCost(uxCost__24), +.i_uzCost(uzCost__24), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__24), +.i_uxNumerator(uxNumerator__24), +.i_uyNumerator(uyNumerator__24), +.i_uyCost(uyCost__24), +.i_uxQuotient(uxQuotient__24), +.i_uyQuotient(uyQuotient__24), +//Outputs +.o_sint(sint__25), +.o_cost(cost__25), +.o_sinp(sinp__25), +.o_cosp(cosp__25), +.o_sintCosp(sintCosp__25), +.o_sintSinp(sintSinp__25), +.o_uz2(uz2__25), +.o_uxUz(uxUz__25), +.o_uyUz(uyUz__25), +.o_uySintSinp(uySintSinp__25), +.o_oneMinusUz2(oneMinusUz2__25), +.o_uyUzSintCosp(uyUzSintCosp__25), +.o_uxUzSintCosp(uxUzSintCosp__25), +.o_uxSintSinp(uxSintSinp__25), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__25), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__25), +.o_uxCost(uxCost__25), +.o_uzCost(uzCost__25), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__25), +.o_uxNumerator(uxNumerator__25), +.o_uyNumerator(uyNumerator__25), +.o_uyCost(uyCost__25), +.o_uxQuotient(uxQuotient__25), +.o_uyQuotient(uyQuotient__25) +); + +InternalsBlock pipeReg24( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__23), +.i_cost(cost__23), +.i_sinp(sinp__23), +.i_cosp(cosp__23), +.i_sintCosp(sintCosp__23), +.i_sintSinp(sintSinp__23), +.i_uz2(uz2__23), +.i_uxUz(uxUz__23), +.i_uyUz(uyUz__23), +.i_uySintSinp(uySintSinp__23), +.i_oneMinusUz2(oneMinusUz2__23), +.i_uyUzSintCosp(uyUzSintCosp__23), +.i_uxUzSintCosp(uxUzSintCosp__23), +.i_uxSintSinp(uxSintSinp__23), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__23), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__23), +.i_uxCost(uxCost__23), +.i_uzCost(uzCost__23), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__23), +.i_uxNumerator(uxNumerator__23), +.i_uyNumerator(uyNumerator__23), +.i_uyCost(uyCost__23), +.i_uxQuotient(uxQuotient__23), +.i_uyQuotient(uyQuotient__23), +//Outputs +.o_sint(sint__24), +.o_cost(cost__24), +.o_sinp(sinp__24), +.o_cosp(cosp__24), +.o_sintCosp(sintCosp__24), +.o_sintSinp(sintSinp__24), +.o_uz2(uz2__24), +.o_uxUz(uxUz__24), +.o_uyUz(uyUz__24), +.o_uySintSinp(uySintSinp__24), +.o_oneMinusUz2(oneMinusUz2__24), +.o_uyUzSintCosp(uyUzSintCosp__24), +.o_uxUzSintCosp(uxUzSintCosp__24), +.o_uxSintSinp(uxSintSinp__24), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__24), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__24), +.o_uxCost(uxCost__24), +.o_uzCost(uzCost__24), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__24), +.o_uxNumerator(uxNumerator__24), +.o_uyNumerator(uyNumerator__24), +.o_uyCost(uyCost__24), +.o_uxQuotient(uxQuotient__24), +.o_uyQuotient(uyQuotient__24) +); + +InternalsBlock pipeReg23( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__22), +.i_cost(cost__22), +.i_sinp(sinp__22), +.i_cosp(cosp__22), +.i_sintCosp(sintCosp__22), +.i_sintSinp(sintSinp__22), +.i_uz2(uz2__22), +.i_uxUz(uxUz__22), +.i_uyUz(uyUz__22), +.i_uySintSinp(uySintSinp__22), +.i_oneMinusUz2(oneMinusUz2__22), +.i_uyUzSintCosp(uyUzSintCosp__22), +.i_uxUzSintCosp(uxUzSintCosp__22), +.i_uxSintSinp(uxSintSinp__22), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__22), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__22), +.i_uxCost(uxCost__22), +.i_uzCost(uzCost__22), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__22), +.i_uxNumerator(uxNumerator__22), +.i_uyNumerator(uyNumerator__22), +.i_uyCost(uyCost__22), +.i_uxQuotient(uxQuotient__22), +.i_uyQuotient(uyQuotient__22), +//Outputs +.o_sint(sint__23), +.o_cost(cost__23), +.o_sinp(sinp__23), +.o_cosp(cosp__23), +.o_sintCosp(sintCosp__23), +.o_sintSinp(sintSinp__23), +.o_uz2(uz2__23), +.o_uxUz(uxUz__23), +.o_uyUz(uyUz__23), +.o_uySintSinp(uySintSinp__23), +.o_oneMinusUz2(oneMinusUz2__23), +.o_uyUzSintCosp(uyUzSintCosp__23), +.o_uxUzSintCosp(uxUzSintCosp__23), +.o_uxSintSinp(uxSintSinp__23), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__23), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__23), +.o_uxCost(uxCost__23), +.o_uzCost(uzCost__23), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__23), +.o_uxNumerator(uxNumerator__23), +.o_uyNumerator(uyNumerator__23), +.o_uyCost(uyCost__23), +.o_uxQuotient(uxQuotient__23), +.o_uyQuotient(uyQuotient__23) +); + +InternalsBlock pipeReg22( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__21), +.i_cost(cost__21), +.i_sinp(sinp__21), +.i_cosp(cosp__21), +.i_sintCosp(sintCosp__21), +.i_sintSinp(sintSinp__21), +.i_uz2(uz2__21), +.i_uxUz(uxUz__21), +.i_uyUz(uyUz__21), +.i_uySintSinp(uySintSinp__21), +.i_oneMinusUz2(oneMinusUz2__21), +.i_uyUzSintCosp(uyUzSintCosp__21), +.i_uxUzSintCosp(uxUzSintCosp__21), +.i_uxSintSinp(uxSintSinp__21), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__21), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__21), +.i_uxCost(uxCost__21), +.i_uzCost(uzCost__21), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__21), +.i_uxNumerator(uxNumerator__21), +.i_uyNumerator(uyNumerator__21), +.i_uyCost(uyCost__21), +.i_uxQuotient(uxQuotient__21), +.i_uyQuotient(uyQuotient__21), +//Outputs +.o_sint(sint__22), +.o_cost(cost__22), +.o_sinp(sinp__22), +.o_cosp(cosp__22), +.o_sintCosp(sintCosp__22), +.o_sintSinp(sintSinp__22), +.o_uz2(uz2__22), +.o_uxUz(uxUz__22), +.o_uyUz(uyUz__22), +.o_uySintSinp(uySintSinp__22), +.o_oneMinusUz2(oneMinusUz2__22), +.o_uyUzSintCosp(uyUzSintCosp__22), +.o_uxUzSintCosp(uxUzSintCosp__22), +.o_uxSintSinp(uxSintSinp__22), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__22), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__22), +.o_uxCost(uxCost__22), +.o_uzCost(uzCost__22), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__22), +.o_uxNumerator(uxNumerator__22), +.o_uyNumerator(uyNumerator__22), +.o_uyCost(uyCost__22), +.o_uxQuotient(uxQuotient__22), +.o_uyQuotient(uyQuotient__22) +); + +InternalsBlock pipeReg21( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__20), +.i_cost(cost__20), +.i_sinp(sinp__20), +.i_cosp(cosp__20), +.i_sintCosp(sintCosp__20), +.i_sintSinp(sintSinp__20), +.i_uz2(uz2__20), +.i_uxUz(uxUz__20), +.i_uyUz(uyUz__20), +.i_uySintSinp(uySintSinp__20), +.i_oneMinusUz2(oneMinusUz2__20), +.i_uyUzSintCosp(uyUzSintCosp__20), +.i_uxUzSintCosp(uxUzSintCosp__20), +.i_uxSintSinp(uxSintSinp__20), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__20), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__20), +.i_uxCost(uxCost__20), +.i_uzCost(uzCost__20), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__20), +.i_uxNumerator(uxNumerator__20), +.i_uyNumerator(uyNumerator__20), +.i_uyCost(uyCost__20), +.i_uxQuotient(uxQuotient__20), +.i_uyQuotient(uyQuotient__20), +//Outputs +.o_sint(sint__21), +.o_cost(cost__21), +.o_sinp(sinp__21), +.o_cosp(cosp__21), +.o_sintCosp(sintCosp__21), +.o_sintSinp(sintSinp__21), +.o_uz2(uz2__21), +.o_uxUz(uxUz__21), +.o_uyUz(uyUz__21), +.o_uySintSinp(uySintSinp__21), +.o_oneMinusUz2(oneMinusUz2__21), +.o_uyUzSintCosp(uyUzSintCosp__21), +.o_uxUzSintCosp(uxUzSintCosp__21), +.o_uxSintSinp(uxSintSinp__21), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__21), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__21), +.o_uxCost(uxCost__21), +.o_uzCost(uzCost__21), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__21), +.o_uxNumerator(uxNumerator__21), +.o_uyNumerator(uyNumerator__21), +.o_uyCost(uyCost__21), +.o_uxQuotient(uxQuotient__21), +.o_uyQuotient(uyQuotient__21) +); + +InternalsBlock pipeReg20( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__19), +.i_cost(cost__19), +.i_sinp(sinp__19), +.i_cosp(cosp__19), +.i_sintCosp(sintCosp__19), +.i_sintSinp(sintSinp__19), +.i_uz2(uz2__19), +.i_uxUz(uxUz__19), +.i_uyUz(uyUz__19), +.i_uySintSinp(uySintSinp__19), +.i_oneMinusUz2(oneMinusUz2__19), +.i_uyUzSintCosp(uyUzSintCosp__19), +.i_uxUzSintCosp(uxUzSintCosp__19), +.i_uxSintSinp(uxSintSinp__19), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__19), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__19), +.i_uxCost(uxCost__19), +.i_uzCost(uzCost__19), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__19), +.i_uxNumerator(uxNumerator__19), +.i_uyNumerator(uyNumerator__19), +.i_uyCost(uyCost__19), +.i_uxQuotient(uxQuotient__19), +.i_uyQuotient(uyQuotient__19), +//Outputs +.o_sint(sint__20), +.o_cost(cost__20), +.o_sinp(sinp__20), +.o_cosp(cosp__20), +.o_sintCosp(sintCosp__20), +.o_sintSinp(sintSinp__20), +.o_uz2(uz2__20), +.o_uxUz(uxUz__20), +.o_uyUz(uyUz__20), +.o_uySintSinp(uySintSinp__20), +.o_oneMinusUz2(oneMinusUz2__20), +.o_uyUzSintCosp(uyUzSintCosp__20), +.o_uxUzSintCosp(uxUzSintCosp__20), +.o_uxSintSinp(uxSintSinp__20), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__20), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__20), +.o_uxCost(uxCost__20), +.o_uzCost(uzCost__20), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__20), +.o_uxNumerator(uxNumerator__20), +.o_uyNumerator(uyNumerator__20), +.o_uyCost(uyCost__20), +.o_uxQuotient(uxQuotient__20), +.o_uyQuotient(uyQuotient__20) +); + +InternalsBlock pipeReg19( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__18), +.i_cost(cost__18), +.i_sinp(sinp__18), +.i_cosp(cosp__18), +.i_sintCosp(sintCosp__18), +.i_sintSinp(sintSinp__18), +.i_uz2(uz2__18), +.i_uxUz(uxUz__18), +.i_uyUz(uyUz__18), +.i_uySintSinp(uySintSinp__18), +.i_oneMinusUz2(oneMinusUz2__18), +.i_uyUzSintCosp(uyUzSintCosp__18), +.i_uxUzSintCosp(uxUzSintCosp__18), +.i_uxSintSinp(uxSintSinp__18), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__18), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__18), +.i_uxCost(uxCost__18), +.i_uzCost(uzCost__18), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__18), +.i_uxNumerator(uxNumerator__18), +.i_uyNumerator(uyNumerator__18), +.i_uyCost(uyCost__18), +.i_uxQuotient(uxQuotient__18), +.i_uyQuotient(uyQuotient__18), +//Outputs +.o_sint(sint__19), +.o_cost(cost__19), +.o_sinp(sinp__19), +.o_cosp(cosp__19), +.o_sintCosp(sintCosp__19), +.o_sintSinp(sintSinp__19), +.o_uz2(uz2__19), +.o_uxUz(uxUz__19), +.o_uyUz(uyUz__19), +.o_uySintSinp(uySintSinp__19), +.o_oneMinusUz2(oneMinusUz2__19), +.o_uyUzSintCosp(uyUzSintCosp__19), +.o_uxUzSintCosp(uxUzSintCosp__19), +.o_uxSintSinp(uxSintSinp__19), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__19), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__19), +.o_uxCost(uxCost__19), +.o_uzCost(uzCost__19), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__19), +.o_uxNumerator(uxNumerator__19), +.o_uyNumerator(uyNumerator__19), +.o_uyCost(uyCost__19), +.o_uxQuotient(uxQuotient__19), +.o_uyQuotient(uyQuotient__19) +); + +InternalsBlock pipeReg18( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__17), +.i_cost(cost__17), +.i_sinp(sinp__17), +.i_cosp(cosp__17), +.i_sintCosp(sintCosp__17), +.i_sintSinp(sintSinp__17), +.i_uz2(uz2__17), +.i_uxUz(uxUz__17), +.i_uyUz(uyUz__17), +.i_uySintSinp(uySintSinp__17), +.i_oneMinusUz2(oneMinusUz2__17), +.i_uyUzSintCosp(uyUzSintCosp__17), +.i_uxUzSintCosp(uxUzSintCosp__17), +.i_uxSintSinp(uxSintSinp__17), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__17), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__17), +.i_uxCost(uxCost__17), +.i_uzCost(uzCost__17), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__17), +.i_uxNumerator(uxNumerator__17), +.i_uyNumerator(uyNumerator__17), +.i_uyCost(uyCost__17), +.i_uxQuotient(uxQuotient__17), +.i_uyQuotient(uyQuotient__17), +//Outputs +.o_sint(sint__18), +.o_cost(cost__18), +.o_sinp(sinp__18), +.o_cosp(cosp__18), +.o_sintCosp(sintCosp__18), +.o_sintSinp(sintSinp__18), +.o_uz2(uz2__18), +.o_uxUz(uxUz__18), +.o_uyUz(uyUz__18), +.o_uySintSinp(uySintSinp__18), +.o_oneMinusUz2(oneMinusUz2__18), +.o_uyUzSintCosp(uyUzSintCosp__18), +.o_uxUzSintCosp(uxUzSintCosp__18), +.o_uxSintSinp(uxSintSinp__18), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__18), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__18), +.o_uxCost(uxCost__18), +.o_uzCost(uzCost__18), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__18), +.o_uxNumerator(uxNumerator__18), +.o_uyNumerator(uyNumerator__18), +.o_uyCost(uyCost__18), +.o_uxQuotient(uxQuotient__18), +.o_uyQuotient(uyQuotient__18) +); + +InternalsBlock pipeReg17( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__16), +.i_cost(cost__16), +.i_sinp(sinp__16), +.i_cosp(cosp__16), +.i_sintCosp(sintCosp__16), +.i_sintSinp(sintSinp__16), +.i_uz2(uz2__16), +.i_uxUz(uxUz__16), +.i_uyUz(uyUz__16), +.i_uySintSinp(uySintSinp__16), +.i_oneMinusUz2(oneMinusUz2__16), +.i_uyUzSintCosp(uyUzSintCosp__16), +.i_uxUzSintCosp(uxUzSintCosp__16), +.i_uxSintSinp(uxSintSinp__16), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__16), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__16), +.i_uxCost(uxCost__16), +.i_uzCost(uzCost__16), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__16), +.i_uxNumerator(uxNumerator__16), +.i_uyNumerator(uyNumerator__16), +.i_uyCost(uyCost__16), +.i_uxQuotient(uxQuotient__16), +.i_uyQuotient(uyQuotient__16), +//Outputs +.o_sint(sint__17), +.o_cost(cost__17), +.o_sinp(sinp__17), +.o_cosp(cosp__17), +.o_sintCosp(sintCosp__17), +.o_sintSinp(sintSinp__17), +.o_uz2(uz2__17), +.o_uxUz(uxUz__17), +.o_uyUz(uyUz__17), +.o_uySintSinp(uySintSinp__17), +.o_oneMinusUz2(oneMinusUz2__17), +.o_uyUzSintCosp(uyUzSintCosp__17), +.o_uxUzSintCosp(uxUzSintCosp__17), +.o_uxSintSinp(uxSintSinp__17), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__17), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__17), +.o_uxCost(uxCost__17), +.o_uzCost(uzCost__17), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__17), +.o_uxNumerator(uxNumerator__17), +.o_uyNumerator(uyNumerator__17), +.o_uyCost(uyCost__17), +.o_uxQuotient(uxQuotient__17), +.o_uyQuotient(uyQuotient__17) +); + + +InternalsBlock pipeReg15( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__14), +.i_cost(cost__14), +.i_sinp(sinp__14), +.i_cosp(cosp__14), +.i_sintCosp(sintCosp__14), +.i_sintSinp(sintSinp__14), +.i_uz2(uz2__14), +.i_uxUz(uxUz__14), +.i_uyUz(uyUz__14), +.i_uySintSinp(uySintSinp__14), +.i_oneMinusUz2(oneMinusUz2__14), +.i_uyUzSintCosp(uyUzSintCosp__14), +.i_uxUzSintCosp(uxUzSintCosp__14), +.i_uxSintSinp(uxSintSinp__14), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__14), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__14), +.i_uxCost(uxCost__14), +.i_uzCost(uzCost__14), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__14), +.i_uxNumerator(uxNumerator__14), +.i_uyNumerator(uyNumerator__14), +.i_uyCost(uyCost__14), +.i_uxQuotient(uxQuotient__14), +.i_uyQuotient(uyQuotient__14), +//Outputs +.o_sint(sint__15), +.o_cost(cost__15), +.o_sinp(sinp__15), +.o_cosp(cosp__15), +.o_sintCosp(sintCosp__15), +.o_sintSinp(sintSinp__15), +.o_uz2(uz2__15), +.o_uxUz(uxUz__15), +.o_uyUz(uyUz__15), +.o_uySintSinp(uySintSinp__15), +.o_oneMinusUz2(oneMinusUz2__15), +.o_uyUzSintCosp(uyUzSintCosp__15), +.o_uxUzSintCosp(uxUzSintCosp__15), +.o_uxSintSinp(uxSintSinp__15), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__15), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__15), +.o_uxCost(uxCost__15), +.o_uzCost(uzCost__15), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__15), +.o_uxNumerator(uxNumerator__15), +.o_uyNumerator(uyNumerator__15), +.o_uyCost(uyCost__15), +.o_uxQuotient(uxQuotient__15), +.o_uyQuotient(uyQuotient__15) +); + +InternalsBlock pipeReg14( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__13), +.i_cost(cost__13), +.i_sinp(sinp__13), +.i_cosp(cosp__13), +.i_sintCosp(sintCosp__13), +.i_sintSinp(sintSinp__13), +.i_uz2(uz2__13), +.i_uxUz(uxUz__13), +.i_uyUz(uyUz__13), +.i_uySintSinp(uySintSinp__13), +.i_oneMinusUz2(oneMinusUz2__13), +.i_uyUzSintCosp(uyUzSintCosp__13), +.i_uxUzSintCosp(uxUzSintCosp__13), +.i_uxSintSinp(uxSintSinp__13), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__13), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__13), +.i_uxCost(uxCost__13), +.i_uzCost(uzCost__13), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__13), +.i_uxNumerator(uxNumerator__13), +.i_uyNumerator(uyNumerator__13), +.i_uyCost(uyCost__13), +.i_uxQuotient(uxQuotient__13), +.i_uyQuotient(uyQuotient__13), +//Outputs +.o_sint(sint__14), +.o_cost(cost__14), +.o_sinp(sinp__14), +.o_cosp(cosp__14), +.o_sintCosp(sintCosp__14), +.o_sintSinp(sintSinp__14), +.o_uz2(uz2__14), +.o_uxUz(uxUz__14), +.o_uyUz(uyUz__14), +.o_uySintSinp(uySintSinp__14), +.o_oneMinusUz2(oneMinusUz2__14), +.o_uyUzSintCosp(uyUzSintCosp__14), +.o_uxUzSintCosp(uxUzSintCosp__14), +.o_uxSintSinp(uxSintSinp__14), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__14), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__14), +.o_uxCost(uxCost__14), +.o_uzCost(uzCost__14), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__14), +.o_uxNumerator(uxNumerator__14), +.o_uyNumerator(uyNumerator__14), +.o_uyCost(uyCost__14), +.o_uxQuotient(uxQuotient__14), +.o_uyQuotient(uyQuotient__14) +); + +InternalsBlock pipeReg13( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__12), +.i_cost(cost__12), +.i_sinp(sinp__12), +.i_cosp(cosp__12), +.i_sintCosp(sintCosp__12), +.i_sintSinp(sintSinp__12), +.i_uz2(uz2__12), +.i_uxUz(uxUz__12), +.i_uyUz(uyUz__12), +.i_uySintSinp(uySintSinp__12), +.i_oneMinusUz2(oneMinusUz2__12), +.i_uyUzSintCosp(uyUzSintCosp__12), +.i_uxUzSintCosp(uxUzSintCosp__12), +.i_uxSintSinp(uxSintSinp__12), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__12), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__12), +.i_uxCost(uxCost__12), +.i_uzCost(uzCost__12), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__12), +.i_uxNumerator(uxNumerator__12), +.i_uyNumerator(uyNumerator__12), +.i_uyCost(uyCost__12), +.i_uxQuotient(uxQuotient__12), +.i_uyQuotient(uyQuotient__12), +//Outputs +.o_sint(sint__13), +.o_cost(cost__13), +.o_sinp(sinp__13), +.o_cosp(cosp__13), +.o_sintCosp(sintCosp__13), +.o_sintSinp(sintSinp__13), +.o_uz2(uz2__13), +.o_uxUz(uxUz__13), +.o_uyUz(uyUz__13), +.o_uySintSinp(uySintSinp__13), +.o_oneMinusUz2(oneMinusUz2__13), +.o_uyUzSintCosp(uyUzSintCosp__13), +.o_uxUzSintCosp(uxUzSintCosp__13), +.o_uxSintSinp(uxSintSinp__13), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__13), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__13), +.o_uxCost(uxCost__13), +.o_uzCost(uzCost__13), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__13), +.o_uxNumerator(uxNumerator__13), +.o_uyNumerator(uyNumerator__13), +.o_uyCost(uyCost__13), +.o_uxQuotient(uxQuotient__13), +.o_uyQuotient(uyQuotient__13) +); + +InternalsBlock pipeReg12( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__11), +.i_cost(cost__11), +.i_sinp(sinp__11), +.i_cosp(cosp__11), +.i_sintCosp(sintCosp__11), +.i_sintSinp(sintSinp__11), +.i_uz2(uz2__11), +.i_uxUz(uxUz__11), +.i_uyUz(uyUz__11), +.i_uySintSinp(uySintSinp__11), +.i_oneMinusUz2(oneMinusUz2__11), +.i_uyUzSintCosp(uyUzSintCosp__11), +.i_uxUzSintCosp(uxUzSintCosp__11), +.i_uxSintSinp(uxSintSinp__11), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__11), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__11), +.i_uxCost(uxCost__11), +.i_uzCost(uzCost__11), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__11), +.i_uxNumerator(uxNumerator__11), +.i_uyNumerator(uyNumerator__11), +.i_uyCost(uyCost__11), +.i_uxQuotient(uxQuotient__11), +.i_uyQuotient(uyQuotient__11), +//Outputs +.o_sint(sint__12), +.o_cost(cost__12), +.o_sinp(sinp__12), +.o_cosp(cosp__12), +.o_sintCosp(sintCosp__12), +.o_sintSinp(sintSinp__12), +.o_uz2(uz2__12), +.o_uxUz(uxUz__12), +.o_uyUz(uyUz__12), +.o_uySintSinp(uySintSinp__12), +.o_oneMinusUz2(oneMinusUz2__12), +.o_uyUzSintCosp(uyUzSintCosp__12), +.o_uxUzSintCosp(uxUzSintCosp__12), +.o_uxSintSinp(uxSintSinp__12), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__12), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__12), +.o_uxCost(uxCost__12), +.o_uzCost(uzCost__12), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__12), +.o_uxNumerator(uxNumerator__12), +.o_uyNumerator(uyNumerator__12), +.o_uyCost(uyCost__12), +.o_uxQuotient(uxQuotient__12), +.o_uyQuotient(uyQuotient__12) +); + +InternalsBlock pipeReg11( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__10), +.i_cost(cost__10), +.i_sinp(sinp__10), +.i_cosp(cosp__10), +.i_sintCosp(sintCosp__10), +.i_sintSinp(sintSinp__10), +.i_uz2(uz2__10), +.i_uxUz(uxUz__10), +.i_uyUz(uyUz__10), +.i_uySintSinp(uySintSinp__10), +.i_oneMinusUz2(oneMinusUz2__10), +.i_uyUzSintCosp(uyUzSintCosp__10), +.i_uxUzSintCosp(uxUzSintCosp__10), +.i_uxSintSinp(uxSintSinp__10), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__10), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__10), +.i_uxCost(uxCost__10), +.i_uzCost(uzCost__10), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__10), +.i_uxNumerator(uxNumerator__10), +.i_uyNumerator(uyNumerator__10), +.i_uyCost(uyCost__10), +.i_uxQuotient(uxQuotient__10), +.i_uyQuotient(uyQuotient__10), +//Outputs +.o_sint(sint__11), +.o_cost(cost__11), +.o_sinp(sinp__11), +.o_cosp(cosp__11), +.o_sintCosp(sintCosp__11), +.o_sintSinp(sintSinp__11), +.o_uz2(uz2__11), +.o_uxUz(uxUz__11), +.o_uyUz(uyUz__11), +.o_uySintSinp(uySintSinp__11), +.o_oneMinusUz2(oneMinusUz2__11), +.o_uyUzSintCosp(uyUzSintCosp__11), +.o_uxUzSintCosp(uxUzSintCosp__11), +.o_uxSintSinp(uxSintSinp__11), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__11), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__11), +.o_uxCost(uxCost__11), +.o_uzCost(uzCost__11), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__11), +.o_uxNumerator(uxNumerator__11), +.o_uyNumerator(uyNumerator__11), +.o_uyCost(uyCost__11), +.o_uxQuotient(uxQuotient__11), +.o_uyQuotient(uyQuotient__11) +); + +InternalsBlock pipeReg10( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__9), +.i_cost(cost__9), +.i_sinp(sinp__9), +.i_cosp(cosp__9), +.i_sintCosp(sintCosp__9), +.i_sintSinp(sintSinp__9), +.i_uz2(uz2__9), +.i_uxUz(uxUz__9), +.i_uyUz(uyUz__9), +.i_uySintSinp(uySintSinp__9), +.i_oneMinusUz2(oneMinusUz2__9), +.i_uyUzSintCosp(uyUzSintCosp__9), +.i_uxUzSintCosp(uxUzSintCosp__9), +.i_uxSintSinp(uxSintSinp__9), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__9), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__9), +.i_uxCost(uxCost__9), +.i_uzCost(uzCost__9), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__9), +.i_uxNumerator(uxNumerator__9), +.i_uyNumerator(uyNumerator__9), +.i_uyCost(uyCost__9), +.i_uxQuotient(uxQuotient__9), +.i_uyQuotient(uyQuotient__9), +//Outputs +.o_sint(sint__10), +.o_cost(cost__10), +.o_sinp(sinp__10), +.o_cosp(cosp__10), +.o_sintCosp(sintCosp__10), +.o_sintSinp(sintSinp__10), +.o_uz2(uz2__10), +.o_uxUz(uxUz__10), +.o_uyUz(uyUz__10), +.o_uySintSinp(uySintSinp__10), +.o_oneMinusUz2(oneMinusUz2__10), +.o_uyUzSintCosp(uyUzSintCosp__10), +.o_uxUzSintCosp(uxUzSintCosp__10), +.o_uxSintSinp(uxSintSinp__10), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__10), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__10), +.o_uxCost(uxCost__10), +.o_uzCost(uzCost__10), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__10), +.o_uxNumerator(uxNumerator__10), +.o_uyNumerator(uyNumerator__10), +.o_uyCost(uyCost__10), +.o_uxQuotient(uxQuotient__10), +.o_uyQuotient(uyQuotient__10) +); + +InternalsBlock pipeReg9( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__8), +.i_cost(cost__8), +.i_sinp(sinp__8), +.i_cosp(cosp__8), +.i_sintCosp(sintCosp__8), +.i_sintSinp(sintSinp__8), +.i_uz2(uz2__8), +.i_uxUz(uxUz__8), +.i_uyUz(uyUz__8), +.i_uySintSinp(uySintSinp__8), +.i_oneMinusUz2(oneMinusUz2__8), +.i_uyUzSintCosp(uyUzSintCosp__8), +.i_uxUzSintCosp(uxUzSintCosp__8), +.i_uxSintSinp(uxSintSinp__8), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__8), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__8), +.i_uxCost(uxCost__8), +.i_uzCost(uzCost__8), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__8), +.i_uxNumerator(uxNumerator__8), +.i_uyNumerator(uyNumerator__8), +.i_uyCost(uyCost__8), +.i_uxQuotient(uxQuotient__8), +.i_uyQuotient(uyQuotient__8), +//Outputs +.o_sint(sint__9), +.o_cost(cost__9), +.o_sinp(sinp__9), +.o_cosp(cosp__9), +.o_sintCosp(sintCosp__9), +.o_sintSinp(sintSinp__9), +.o_uz2(uz2__9), +.o_uxUz(uxUz__9), +.o_uyUz(uyUz__9), +.o_uySintSinp(uySintSinp__9), +.o_oneMinusUz2(oneMinusUz2__9), +.o_uyUzSintCosp(uyUzSintCosp__9), +.o_uxUzSintCosp(uxUzSintCosp__9), +.o_uxSintSinp(uxSintSinp__9), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__9), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__9), +.o_uxCost(uxCost__9), +.o_uzCost(uzCost__9), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__9), +.o_uxNumerator(uxNumerator__9), +.o_uyNumerator(uyNumerator__9), +.o_uyCost(uyCost__9), +.o_uxQuotient(uxQuotient__9), +.o_uyQuotient(uyQuotient__9) +); + +InternalsBlock pipeReg8( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__7), +.i_cost(cost__7), +.i_sinp(sinp__7), +.i_cosp(cosp__7), +.i_sintCosp(sintCosp__7), +.i_sintSinp(sintSinp__7), +.i_uz2(uz2__7), +.i_uxUz(uxUz__7), +.i_uyUz(uyUz__7), +.i_uySintSinp(uySintSinp__7), +.i_oneMinusUz2(oneMinusUz2__7), +.i_uyUzSintCosp(uyUzSintCosp__7), +.i_uxUzSintCosp(uxUzSintCosp__7), +.i_uxSintSinp(uxSintSinp__7), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__7), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__7), +.i_uxCost(uxCost__7), +.i_uzCost(uzCost__7), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__7), +.i_uxNumerator(uxNumerator__7), +.i_uyNumerator(uyNumerator__7), +.i_uyCost(uyCost__7), +.i_uxQuotient(uxQuotient__7), +.i_uyQuotient(uyQuotient__7), +//Outputs +.o_sint(sint__8), +.o_cost(cost__8), +.o_sinp(sinp__8), +.o_cosp(cosp__8), +.o_sintCosp(sintCosp__8), +.o_sintSinp(sintSinp__8), +.o_uz2(uz2__8), +.o_uxUz(uxUz__8), +.o_uyUz(uyUz__8), +.o_uySintSinp(uySintSinp__8), +.o_oneMinusUz2(oneMinusUz2__8), +.o_uyUzSintCosp(uyUzSintCosp__8), +.o_uxUzSintCosp(uxUzSintCosp__8), +.o_uxSintSinp(uxSintSinp__8), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__8), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__8), +.o_uxCost(uxCost__8), +.o_uzCost(uzCost__8), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__8), +.o_uxNumerator(uxNumerator__8), +.o_uyNumerator(uyNumerator__8), +.o_uyCost(uyCost__8), +.o_uxQuotient(uxQuotient__8), +.o_uyQuotient(uyQuotient__8) +); + +InternalsBlock pipeReg7( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__6), +.i_cost(cost__6), +.i_sinp(sinp__6), +.i_cosp(cosp__6), +.i_sintCosp(sintCosp__6), +.i_sintSinp(sintSinp__6), +.i_uz2(uz2__6), +.i_uxUz(uxUz__6), +.i_uyUz(uyUz__6), +.i_uySintSinp(uySintSinp__6), +.i_oneMinusUz2(oneMinusUz2__6), +.i_uyUzSintCosp(uyUzSintCosp__6), +.i_uxUzSintCosp(uxUzSintCosp__6), +.i_uxSintSinp(uxSintSinp__6), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__6), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__6), +.i_uxCost(uxCost__6), +.i_uzCost(uzCost__6), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__6), +.i_uxNumerator(uxNumerator__6), +.i_uyNumerator(uyNumerator__6), +.i_uyCost(uyCost__6), +.i_uxQuotient(uxQuotient__6), +.i_uyQuotient(uyQuotient__6), +//Outputs +.o_sint(sint__7), +.o_cost(cost__7), +.o_sinp(sinp__7), +.o_cosp(cosp__7), +.o_sintCosp(sintCosp__7), +.o_sintSinp(sintSinp__7), +.o_uz2(uz2__7), +.o_uxUz(uxUz__7), +.o_uyUz(uyUz__7), +.o_uySintSinp(uySintSinp__7), +.o_oneMinusUz2(oneMinusUz2__7), +.o_uyUzSintCosp(uyUzSintCosp__7), +.o_uxUzSintCosp(uxUzSintCosp__7), +.o_uxSintSinp(uxSintSinp__7), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__7), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__7), +.o_uxCost(uxCost__7), +.o_uzCost(uzCost__7), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__7), +.o_uxNumerator(uxNumerator__7), +.o_uyNumerator(uyNumerator__7), +.o_uyCost(uyCost__7), +.o_uxQuotient(uxQuotient__7), +.o_uyQuotient(uyQuotient__7) +); + +InternalsBlock pipeReg6( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__5), +.i_cost(cost__5), +.i_sinp(sinp__5), +.i_cosp(cosp__5), +.i_sintCosp(sintCosp__5), +.i_sintSinp(sintSinp__5), +.i_uz2(uz2__5), +.i_uxUz(uxUz__5), +.i_uyUz(uyUz__5), +.i_uySintSinp(uySintSinp__5), +.i_oneMinusUz2(oneMinusUz2__5), +.i_uyUzSintCosp(uyUzSintCosp__5), +.i_uxUzSintCosp(uxUzSintCosp__5), +.i_uxSintSinp(uxSintSinp__5), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__5), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__5), +.i_uxCost(uxCost__5), +.i_uzCost(uzCost__5), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__5), +.i_uxNumerator(uxNumerator__5), +.i_uyNumerator(uyNumerator__5), +.i_uyCost(uyCost__5), +.i_uxQuotient(uxQuotient__5), +.i_uyQuotient(uyQuotient__5), +//Outputs +.o_sint(sint__6), +.o_cost(cost__6), +.o_sinp(sinp__6), +.o_cosp(cosp__6), +.o_sintCosp(sintCosp__6), +.o_sintSinp(sintSinp__6), +.o_uz2(uz2__6), +.o_uxUz(uxUz__6), +.o_uyUz(uyUz__6), +.o_uySintSinp(uySintSinp__6), +.o_oneMinusUz2(oneMinusUz2__6), +.o_uyUzSintCosp(uyUzSintCosp__6), +.o_uxUzSintCosp(uxUzSintCosp__6), +.o_uxSintSinp(uxSintSinp__6), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__6), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__6), +.o_uxCost(uxCost__6), +.o_uzCost(uzCost__6), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__6), +.o_uxNumerator(uxNumerator__6), +.o_uyNumerator(uyNumerator__6), +.o_uyCost(uyCost__6), +.o_uxQuotient(uxQuotient__6), +.o_uyQuotient(uyQuotient__6) +); + +InternalsBlock pipeReg5( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__4), +.i_cost(cost__4), +.i_sinp(sinp__4), +.i_cosp(cosp__4), +.i_sintCosp(sintCosp__4), +.i_sintSinp(sintSinp__4), +.i_uz2(uz2__4), +.i_uxUz(uxUz__4), +.i_uyUz(uyUz__4), +.i_uySintSinp(uySintSinp__4), +.i_oneMinusUz2(oneMinusUz2__4), +.i_uyUzSintCosp(uyUzSintCosp__4), +.i_uxUzSintCosp(uxUzSintCosp__4), +.i_uxSintSinp(uxSintSinp__4), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__4), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__4), +.i_uxCost(uxCost__4), +.i_uzCost(uzCost__4), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__4), +.i_uxNumerator(uxNumerator__4), +.i_uyNumerator(uyNumerator__4), +.i_uyCost(uyCost__4), +.i_uxQuotient(uxQuotient__4), +.i_uyQuotient(uyQuotient__4), +//Outputs +.o_sint(sint__5), +.o_cost(cost__5), +.o_sinp(sinp__5), +.o_cosp(cosp__5), +.o_sintCosp(sintCosp__5), +.o_sintSinp(sintSinp__5), +.o_uz2(uz2__5), +.o_uxUz(uxUz__5), +.o_uyUz(uyUz__5), +.o_uySintSinp(uySintSinp__5), +.o_oneMinusUz2(oneMinusUz2__5), +.o_uyUzSintCosp(uyUzSintCosp__5), +.o_uxUzSintCosp(uxUzSintCosp__5), +.o_uxSintSinp(uxSintSinp__5), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__5), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__5), +.o_uxCost(uxCost__5), +.o_uzCost(uzCost__5), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__5), +.o_uxNumerator(uxNumerator__5), +.o_uyNumerator(uyNumerator__5), +.o_uyCost(uyCost__5), +.o_uxQuotient(uxQuotient__5), +.o_uyQuotient(uyQuotient__5) +); + + +//since these will be replaced later + + + assign sint__0 = 32'b00000000000000000000000000000000; + assign cost__0 = 32'b00000000000000000000000000000000; + assign sinp__0 = 32'b00000000000000000000000000000000; + assign cosp__0 = 32'b00000000000000000000000000000000; + assign sintCosp__0 = 32'b00000000000000000000000000000000; + assign sintSinp__0 = 32'b00000000000000000000000000000000; + assign uz2__0 = 0; + assign uxUz__0 = 32'b00000000000000000000000000000000; + assign uyUz__0 = 32'b00000000000000000000000000000000; + assign uySintSinp__0 = 32'b00000000000000000000000000000000; + assign oneMinusUz2__0 = 0; + assign uyUzSintCosp__0 = 32'b00000000000000000000000000000000; + assign uxUzSintCosp__0 = 32'b00000000000000000000000000000000; + assign uxSintSinp__0 = 32'b00000000000000000000000000000000; + assign sqrtOneMinusUz2__0 = 32'b00000000000000000000000000000000; + assign sintCospSqrtOneMinusUz2__0 = 32'b00000000000000000000000000000000; + assign uxCost__0 = 32'b00000000000000000000000000000000; + assign uzCost__0 = 32'b00000000000000000000000000000000; + assign sqrtOneMinusUz2_inv__0 = 32'b00000000000000000000000000000000; + assign uxNumerator__0 = 32'b00000000000000000000000000000000; + assign uyNumerator__0 = 32'b00000000000000000000000000000000; + assign uyCost__0 = 32'b00000000000000000000000000000000; + assign uxQuotient__0 = 32'b00000000000000000000000000000000; + assign uyQuotient__0 = 32'b00000000000000000000000000000000; + +InternalsBlock pipeReg1( +//Inputs +.clock(clock), +.reset(reset), +.enable(enable), +.i_sint(sint__0), +.i_cost(cost__0), +.i_sinp(sinp__0), +.i_cosp(cosp__0), +.i_sintCosp(sintCosp__0), +.i_sintSinp(sintSinp__0), +.i_uz2(uz2__0), +.i_uxUz(uxUz__0), +.i_uyUz(uyUz__0), +.i_uySintSinp(uySintSinp__0), +.i_oneMinusUz2(oneMinusUz2__0), +.i_uyUzSintCosp(uyUzSintCosp__0), +.i_uxUzSintCosp(uxUzSintCosp__0), +.i_uxSintSinp(uxSintSinp__0), +.i_sqrtOneMinusUz2(sqrtOneMinusUz2__0), +.i_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__0), +.i_uxCost(uxCost__0), +.i_uzCost(uzCost__0), +.i_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__0), +.i_uxNumerator(uxNumerator__0), +.i_uyNumerator(uyNumerator__0), +.i_uyCost(uyCost__0), +.i_uxQuotient(uxQuotient__0), +.i_uyQuotient(uyQuotient__0), +//Outputs +.o_sint(sint__1), +.o_cost(cost__1), +.o_sinp(sinp__1), +.o_cosp(cosp__1), +.o_sintCosp(sintCosp__1), +.o_sintSinp(sintSinp__1), +.o_uz2(uz2__1), +.o_uxUz(uxUz__1), +.o_uyUz(uyUz__1), +.o_uySintSinp(uySintSinp__1), +.o_oneMinusUz2(oneMinusUz2__1), +.o_uyUzSintCosp(uyUzSintCosp__1), +.o_uxUzSintCosp(uxUzSintCosp__1), +.o_uxSintSinp(uxSintSinp__1), +.o_sqrtOneMinusUz2(sqrtOneMinusUz2__1), +.o_sintCospSqrtOneMinusUz2(sintCospSqrtOneMinusUz2__1), +.o_uxCost(uxCost__1), +.o_uzCost(uzCost__1), +.o_sqrtOneMinusUz2_inv(sqrtOneMinusUz2_inv__1), +.o_uxNumerator(uxNumerator__1), +.o_uyNumerator(uyNumerator__1), +.o_uyCost(uyCost__1), +.o_uxQuotient(uxQuotient__1), +.o_uyQuotient(uyQuotient__1) +); + +//-------------SYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is the end of the generate statement, and the beginning of the +//synchronous logic. On the clock event, the outputs calculated from +//this block are put on the output pins for reading (registered +//outputs, as per the convention). + + + + +//Assign outputs from block on positive clock edge. +always @ (posedge clock) begin + if(reset_new) begin + //Reset internal non-pipelined registers here. + ux_scatterer <= 32'h00000000; + uy_scatterer <= 32'h00000000; + uz_scatterer <= 32'h7FFFFFFF; + end else if (enable) begin + ux_scatterer <= new_ux; + uy_scatterer <= new_uy; + uz_scatterer <= new_uz; + end +end + +//-------------ASYNCHRONOUS LOGIC---------------------- +// +// +// +// +// +// +// +// +// +// +// +// +//This is where the asynchronous logic takes place. Things that +//occur here include setting up wiring to send to the multipliers, +//divide unit, and square root unit. Also, products brought in +//from the wrapper are placed on the appropriate wires for placement +//in the pipeline. + + + + +//-------------OPERAND SETUP---------------------- + + +//NAMING CONVENTION: +//opX_Y_Z, op stands for operand, X stands for the multiplication number for +//that clock cycle, Y stands for the clock cycle, Z is either 1 or 2 for the +//first or second operand for this multiply +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calculated will be ready for the Xth register +//location, where 0 is the register prior to any calculations being done, 1 is +//after the 1st clock cycle of calculation, etc. + +//CC 2 +assign op1_2_1 = i_uz1; +assign op1_2_2 = i_uz1; + +//CC 3 +//SUBTRACTION, see math results + +//CC 4 +assign op1_4_1 = i_ux3; +assign op1_4_2 = i_uz3; + +//CC 5 -- NOOP, line up with reflector + +//CC `SQRT+5 -- Started in CC 6 +assign sqrtOperand1_6 = oneMinusUz2__5; + +//CC `SQRT+`DIV+6 -- Started in CC `SQRT+5 +assign divNumerator1_16 = `INTMAX_2; +//assign divDenominator1_16 = sqrtOneMinusUz2[`SQRT+5]; +assign divDenominator1_16 = new_sqrtOneMinusUz2; + +//CC `SQRT+`DIV+3 +assign op1_33_1 = sint_Mem; +assign op1_33_2 = cosp_Mem; + +assign op2_33_1 = sint_Mem; +assign op2_33_2 = sinp_Mem; + +assign op3_33_1 = i_uy32; +assign op3_33_2 = i_uz32; + +//CC `SQRT+`DIV+4 +assign op1_34_1 = i_ux33; +assign op1_34_2 = sintSinp__33; + +assign op2_34_1 = i_uy33; +assign op2_34_2 = sintSinp__33; + +assign op3_34_1 = uxUz__33; +assign op3_34_2 = sintCosp__33; + +assign op4_34_1 = uyUz__33; +assign op4_34_2 = sintCosp__33; + +//CC `SQRT+`DIV+5 +//2 SUBS (see math results) +//`DIVISION COMPLETE (see math results) + +//CC `SQRT+`DIV+6 -- Division is now complete and can be read. +assign op1_36_1 = uxNumerator__35; +assign op1_36_2 = new_sqrtOneMinusUz2_inv; + + +assign op2_36_1 = uyNumerator__35; +assign op2_36_2 = new_sqrtOneMinusUz2_inv; + +assign op3_36_1 = sintCosp__35; +assign op3_36_2 = sqrtOneMinusUz2__35; + +assign op4_36_1 = i_ux35; +assign op4_36_2 = cost__35; + +assign op5_36_1 = i_uy35; +assign op5_36_2 = cost__35; + +assign op6_36_1 = i_uz35; +assign op6_36_2 = cost__35; + + +//-------------MATH RESULTS---------------------- + + +//NAMING CONVENTION: +//new_VAR means that the variable named VAR will be stored into the register +//pipeline at the clock cycle indicated by the comments above it. +// +//prod stands for product, quot stands for quotient, sqrt stands for square root +//prodX_Y means the Xth product which started calculation at the Yth clock cycle +//Similarly for quot and sqrtResult. +// +// +//COMMENTING CONVENTIONS: +//CC X means that the values being calculated will be ready for the Xth register +//location, where 0 is the register prior to any calculations being done, 1 is +//after the 1st clock cycle of calculation, etc. + + +//Used to determine whether or not the divide operation overflowed. +//or U1(div_overflow, quot1_16[62], quot1_16[61], quot1_16[60], quot1_16[59], quot1_16[58], quot1_16[57], quot1_16[56], quot1_16[55], quot1_16[54], quot1_16[53], quot1_16[52], quot1_16[51], quot1_16[50], quot1_16[49], quot1_16[48], quot1_16[47]); +assign div_overflow = quot1_16[62]| quot1_16[61]| quot1_16[60]| quot1_16[59]| quot1_16[58]| quot1_16[57]| quot1_16[56]| quot1_16[55]| quot1_16[54]| quot1_16[53]| quot1_16[52]| quot1_16[51]| quot1_16[50]| quot1_16[49]| quot1_16[48]| quot1_16[47]; + +//Used to determine whether or not the multiply operation overflowed. +//or U2(toAnd1_36_1, prod1_36[62], prod1_36[61], prod1_36[60], prod1_36[59], prod1_36[58], prod1_36[57], prod1_36[56], prod1_36[55], prod1_36[54], prod1_36[53], prod1_36[52], prod1_36[51], prod1_36[50], prod1_36[49], prod1_36[48], prod1_36[47], prod1_36[46]); +assign toAnd1_36_1 = prod1_36[62]| prod1_36[61]| prod1_36[60]| prod1_36[59]| prod1_36[58]| prod1_36[57]| prod1_36[56]| prod1_36[55]| prod1_36[54]| prod1_36[53]| prod1_36[52]| prod1_36[51]| prod1_36[50]| prod1_36[49]| prod1_36[48]| prod1_36[47]| prod1_36[46]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U3(toAnd1_36_2, ~prod1_36[62], ~prod1_36[61], ~prod1_36[60], ~prod1_36[59], ~prod1_36[58], ~prod1_36[57], ~prod1_36[56], ~prod1_36[55], ~prod1_36[54], ~prod1_36[53], ~prod1_36[52], ~prod1_36[51], ~prod1_36[50], ~prod1_36[49], ~prod1_36[48], ~prod1_36[47], ~prod1_36[46]); +assign toAnd1_36_2 = ~prod1_36[62]| ~prod1_36[61]| ~prod1_36[60]| ~prod1_36[59]| ~prod1_36[58]| ~prod1_36[57]| ~prod1_36[56]| ~prod1_36[55]| ~prod1_36[54]| ~prod1_36[53]| ~prod1_36[52]| ~prod1_36[51]| ~prod1_36[50]| ~prod1_36[49]| ~prod1_36[48]| ~prod1_36[47]| ~prod1_36[46]; + +//and U4(overflow1_36, ~prod1_36[63], toAnd1_36_1); +assign overflow1_36 = ~prod1_36[63]| toAnd1_36_1; +//and U5(negOverflow1_36, prod1_36[63], toAnd1_36_2); +assign negOverflow1_36 = prod1_36[63]| toAnd1_36_2; + + +//Used to determine whether or not the multiply operation overflowed. +//or U6(toAnd2_36_1, prod2_36[62], prod2_36[61], prod2_36[60], prod2_36[59], prod2_36[58], prod2_36[57], prod2_36[56], prod2_36[55], prod2_36[54], prod2_36[53], prod2_36[52], prod2_36[51], prod2_36[50], prod2_36[49], prod2_36[48], prod2_36[47], prod2_36[46]); +assign toAnd2_36_1 = prod2_36[62]| prod2_36[61]| prod2_36[60]| prod2_36[59]| prod2_36[58]| prod2_36[57]| prod2_36[56]| prod2_36[55]| prod2_36[54]| prod2_36[53]| prod2_36[52]| prod2_36[51]| prod2_36[50]| prod2_36[49]| prod2_36[48]| prod2_36[47]| prod2_36[46]; +//Used to determine whether or not the multiply operation overflowed in the negative direction. +//or U7(toAnd2_36_2, ~prod2_36[62], ~prod2_36[61], ~prod2_36[60], ~prod2_36[59], ~prod2_36[58], ~prod2_36[57], ~prod2_36[56], ~prod2_36[55], ~prod2_36[54], ~prod2_36[53], ~prod2_36[52], ~prod2_36[51], ~prod2_36[50], ~prod2_36[49], ~prod2_36[48], ~prod2_36[47], ~prod2_36[46]); +assign toAnd2_36_2 = ~prod2_36[62]| ~prod2_36[61]| ~prod2_36[60]| ~prod2_36[59]| ~prod2_36[58]| ~prod2_36[57]| ~prod2_36[56]| ~prod2_36[55]| ~prod2_36[54]| ~prod2_36[53]| ~prod2_36[52]| ~prod2_36[51]| ~prod2_36[50]| ~prod2_36[49]| ~prod2_36[48]| ~prod2_36[47]| ~prod2_36[46]; + +//and U8(overflow2_36, ~prod2_36[63], toAnd2_36_1); +assign overflow2_36 = ~prod2_36[63]|toAnd2_36_1; +//and U9(negOverflow2_36, prod2_36[63], toAnd2_36_2); +assign negOverflow2_36 = prod2_36[63]|toAnd2_36_2; + + + +//CC 2 +assign new_uz2 = prod1_2; +//CC 3 +sub_64b oneMinusUz2_sub( + .dataa(`INTMAX_2), + .datab(uz2__2), + .result(new_oneMinusUz2) + ); + +//CC 4 +assign new_uxUz = prod1_4; +//CC `SQRT+5 +assign new_sqrtOneMinusUz2 = sqrtResult1_6; +//CC `SQRT+`DIV+3 +assign new_sintCosp = prod1_33; +assign new_sintSinp = prod2_33; +assign new_uyUz = prod3_33; +//CC `SQRT+`DIV+4 +assign new_sint = sint_Mem; +assign new_cost = cost_Mem; +assign new_sinp = sinp_Mem; +assign new_cosp = cosp_Mem; +assign new_uxSintSinp = prod1_34; +assign new_uySintSinp = prod2_34; +assign new_uxUzSintCosp = prod3_34; +assign new_uyUzSintCosp = prod4_34; +//CC `SQRT+`DIV+5 +sub_32b uxNumer_sub( + .dataa(uxUzSintCosp__34), + .datab(uySintSinp__34), + .overflow(uxNumerOverflow), + .result(new_uxNumerator) + ); + +add_32b uyNumer_add( + .dataa(uyUzSintCosp__34), + .datab(uxSintSinp__34), + .overflow(uyNumerOverflow), + .result(new_uyNumerator) + ); + + +//Possibility for division overflow (whereby the inverse is too large). Data storage for this +//value is 15 bits left of the decimal, and 16 bits to the right. +assign new_sqrtOneMinusUz2_inv = (div_overflow) ? `INTMAX : {quot1_16[63:63], quot1_16[46:16]}; + +//CC `SQRT+`DIV+6 +always @ (overflow1_36 or negOverflow1_36 or prod1_36 or overflow2_36 or negOverflow2_36 or prod2_36) begin + case ({overflow1_36, negOverflow1_36}) + 0: new_uxQuotient = {prod1_36[63:63], prod1_36[45:15]}; + 1: new_uxQuotient = `INTMIN; + 2: new_uxQuotient = `INTMAX; + //Should never occur + 3: new_uxQuotient = {prod1_36[63:63], prod1_36[45:15]}; + endcase + + case ({overflow2_36, negOverflow2_36}) + + 0: new_uyQuotient = {prod2_36[63:63], prod2_36[45:15]}; + 1: new_uyQuotient = `INTMIN; + 2: new_uyQuotient = `INTMAX; + //Should never occur + 3: new_uyQuotient = {prod2_36[63:63], prod2_36[45:15]}; + endcase +end + +//always @* begin +// new_uxQuotient = {prod1_36[63:63], prod1_36[47:16]}; +// new_uyQuotient = {prod2_36[63:63], prod2_36[47:16]}; +//end + +assign new_sintCospSqrtOneMinusUz2 = prod3_36; +assign new_uxCost = prod4_36; +assign new_uyCost = prod5_36; +assign new_uzCost = prod6_36; + + + +//-----------------------FINAL RESULT CALCULATIONS-------------- +// +// +// +// +// +// +// +//At this point, all calculations have been completed, save the +//final results. This part of the code decides whether or not the +//current calculation involved a normal (orthogonal) incident or not, +//and uses this information to determine how to calculate the +//final results. Final results are put on wires new_ux, new_uy, and +//new_uz, where they are output to registers ux_scatterer, +//uy_scatterer, and uz_scatterer on the clock event for synchronization +//(registered outputs, as per the convention). + + + +//Determine whether or not the photon calculation was done on a photon that +//was normal (orthogonal) to the plane of interest. This is to avoid divide +//by zero errors +always @ (i_uz36) begin + //If uz >= `INTMAX-3 || uz <= -`INTMAX+3, normal incident + if(i_uz36 == 32'h7FFFFFFF || i_uz36 == 32'h7FFFFFFE || i_uz36 == 32'h7FFFFFFD || i_uz36 == 32'h7FFFFFFC || i_uz36 == 32'h80000000 || i_uz36 == 32'h80000001 || i_uz36 == 32'h80000002 || i_uz36 == 32'h80000003 || i_uz36 == 32'h80000004) begin + normalIncident = 1'b1; + end else begin + normalIncident = 1'b0; + end +end + + + +//Assign calculation values for final ux result +assign ux_add_1 = (normalIncident) ? sintCosp__36 : uxQuotient__36; +assign ux_add_2 = (normalIncident) ? 32'b0 : uxCost__36; + +add_32b ux_add( + .dataa(ux_add_1), + .datab(ux_add_2), + .overflow(uxOverflow), + .result(new_ux) + ); + +//Assign calculation values for final uy result +assign uy_add_1 = (normalIncident) ? sintSinp__36 : uyQuotient__36; +assign uy_add_2 = (normalIncident) ? 32'b0 : uyCost__36; + +add_32b uy_add( + .dataa(uy_add_1), + .datab(uy_add_2), + .overflow(uyOverflow), + .result(new_uy) + ); + + + + +//Assign calculation values for final uz result. +//First MUX implements SIGN(uz) function. +assign normalUz = (i_uz36 >=0) ? cost__36 : -cost__36; +assign uz_sub_1 = (normalIncident) ? normalUz : uzCost__36; +assign uz_sub_2 = (normalIncident) ? 32'b0 : sintCospSqrtOneMinusUz2__36; + +sub_32b uz_sub( + .dataa(uz_sub_1), + .datab(uz_sub_2), + .overflow(uzOverflow), + .result(new_uz) + ); + + + +endmodule + + +//*********************************** +//Mathematical modules +//*********************************** + +module sub_64b (dataa, datab, result); + + input [63:0] dataa; + input [63:0] datab; + output [63:0] result; + + assign result = dataa - datab; + +endmodule + +module add_32b (dataa, datab, overflow, result); + + input [31:0] dataa; + input [31:0] datab; + output overflow; + output [31:0] result; + + wire [32:0]computation; //one extra bit to account for overflow + + assign computation = dataa + datab; + assign overflow = computation[32]; + assign result = computation[31:0]; + +endmodule + +module sub_32b (dataa, datab, overflow, result); + + input [31:0] dataa; + input [31:0] datab; + output overflow; + output [31:0] result; + + wire [32:0]computation; //one extra bit to account for overflow + + assign computation = dataa - datab; + assign overflow = computation[32]; + assign result = computation[31:0]; + +endmodule + +module Mult_32b (dataa, datab, result); //now signed version! + + input [31:0]dataa; + input [31:0]datab; + output [63:0]result; + + // assign result = dataa * datab; + + wire [31:0]a; + wire [31:0]b; + assign a = dataa; + assign b = datab; + + reg [63:0]c; + assign result = c; + + reg is_neg_a; + reg is_neg_b; + reg [31:0]a_tmp; + reg [31:0]b_tmp; + reg [63:0]mult_tmp; + reg [63:0]c_tmp; + +always@(a or b or is_neg_a or is_neg_b or a_tmp or b_tmp or c) +begin + if(a[31] == 1) begin + a_tmp = -a; + is_neg_a = 1; + end else + begin + a_tmp = a; + is_neg_a = 0; + end + + if(b[31] == 1) begin + b_tmp = -b; + is_neg_b = 1; + end else + begin + b_tmp = b; + is_neg_b = 0; + end + + mult_tmp = a_tmp * b_tmp; + + if( is_neg_a != is_neg_b) begin + c_tmp = -mult_tmp; + end else + begin + c_tmp = mult_tmp; + end +end + +always@(c_tmp) +begin + c = c_tmp; +end + +endmodule + + + +module Div_64b (clock, denom, numer, quotient, remain); + input clock; + input [63:0]numer; + input [31:0]denom; + output [63:0]quotient; + reg [63:0]quotient; + output [31:0]remain; + reg [31:0]remain; + + wire [63:0]quotient_temp; + wire [31:0]remain_temp; + Div_64b_unsigned div_temp(.clock(clock), .denom_(denom), .numer_(numer), .quotient(quotient_temp), .remain(remain_temp)); + + always @ (numer or denom or quotient_temp or remain_temp) begin + if ( numer[63]^denom[31] ) begin // only one is negative + quotient = -quotient_temp; + remain = -remain_temp; + end else begin + quotient = quotient_temp; + remain = remain_temp; + end + end + +endmodule + + +/*module Div_64b (clock, denom, numer, quotient, remain); + input clock; + input [63:0]numer; + input [31:0]denom; + output [63:0]quotient; + reg [63:0]quotient; + output [31:0]remain; + reg [31:0]remain; */ + +module Div_64b_unsigned (clock, denom_, numer_, quotient, remain); + input clock; + input [63:0]numer_; + input [31:0]denom_; + output [63:0]quotient; + output [31:0]remain; + + reg [63:0]numer; + reg [31:0]denom0; + + always @ (posedge clock) + begin + numer <= numer_; + denom0 <= denom_; + end + +///////////////////////////////////////////////////Unchanged starts here + reg [94:0]numer_temp_63; //need to add bits + reg [94:0]numer_temp_62; + reg [94:0]numer_temp_61; + reg [94:0]numer_temp_60_d, numer_temp_60_q; + reg [94:0]numer_temp_59; + reg [94:0]numer_temp_58; + reg [94:0]numer_temp_57_d, numer_temp_57_q; + reg [94:0]numer_temp_56; + reg [94:0]numer_temp_55; + reg [94:0]numer_temp_54_d, numer_temp_54_q; + reg [94:0]numer_temp_53; + reg [94:0]numer_temp_52; + reg [94:0]numer_temp_51_d, numer_temp_51_q; + reg [94:0]numer_temp_50; + reg [94:0]numer_temp_49; + reg [94:0]numer_temp_48_d, numer_temp_48_q; + reg [94:0]numer_temp_47; + reg [94:0]numer_temp_46; + reg [94:0]numer_temp_45_d, numer_temp_45_q; + reg [94:0]numer_temp_44; + reg [94:0]numer_temp_43; + reg [94:0]numer_temp_42_d, numer_temp_42_q; + reg [94:0]numer_temp_41; + reg [94:0]numer_temp_40; + reg [94:0]numer_temp_39_d, numer_temp_39_q; + reg [94:0]numer_temp_38; + reg [94:0]numer_temp_37; + reg [94:0]numer_temp_36_d, numer_temp_36_q; + reg [94:0]numer_temp_35; + reg [94:0]numer_temp_34; + reg [94:0]numer_temp_33_d, numer_temp_33_q; + reg [94:0]numer_temp_32; + reg [94:0]numer_temp_31; + reg [94:0]numer_temp_30_d, numer_temp_30_q; + reg [94:0]numer_temp_29; + reg [94:0]numer_temp_28; + reg [94:0]numer_temp_27_d, numer_temp_27_q; + reg [94:0]numer_temp_26; + reg [94:0]numer_temp_25; + reg [94:0]numer_temp_24; + reg [94:0]numer_temp_23_d, numer_temp_23_q; + reg [94:0]numer_temp_22; + reg [94:0]numer_temp_21; + reg [94:0]numer_temp_20; + reg [94:0]numer_temp_19_d, numer_temp_19_q; + reg [94:0]numer_temp_18; + reg [94:0]numer_temp_17; + reg [94:0]numer_temp_16; + reg [94:0]numer_temp_15_d, numer_temp_15_q; + reg [94:0]numer_temp_14; + reg [94:0]numer_temp_13; + reg [94:0]numer_temp_12; + reg [94:0]numer_temp_11_d, numer_temp_11_q; + reg [94:0]numer_temp_10; + reg [94:0]numer_temp_9; + reg [94:0]numer_temp_8; + reg [94:0]numer_temp_7_d, numer_temp_7_q; + reg [94:0]numer_temp_6; + reg [94:0]numer_temp_5; + reg [94:0]numer_temp_4; + reg [94:0]numer_temp_3_d, numer_temp_3_q; + reg [94:0]numer_temp_2; + reg [94:0]numer_temp_1_d, numer_temp_1_q; + reg [94:0]numer_temp_0; + reg [94:0]numer_temp; + + //The dummy pipeline (20 clock cycles) + reg [63:0]quo0_d; + reg [63:0]quo1_d; + reg [63:0]quo2_d; + reg [63:0]quo3_d; + reg [63:0]quo4_d; + reg [63:0]quo5_d; + reg [63:0]quo6_d; + reg [63:0]quo7_d; + reg [63:0]quo8_d; + reg [63:0]quo9_d; + reg [63:0]quo10_d; + reg [63:0]quo11_d; + reg [63:0]quo12_d; + reg [63:0]quo13_d; + reg [63:0]quo14_d; + reg [63:0]quo15_d; + reg [63:0]quo16_d; + reg [63:0]quo17_d; + reg [63:0]quo18_d; + reg [63:0]quo19_d; + + reg [63:0]quo0_q; + reg [63:0]quo1_q; + reg [63:0]quo2_q; + reg [63:0]quo3_q; + reg [63:0]quo4_q; + reg [63:0]quo5_q; + reg [63:0]quo6_q; + reg [63:0]quo7_q; + reg [63:0]quo8_q; + reg [63:0]quo9_q; + reg [63:0]quo10_q; + reg [63:0]quo11_q; + reg [63:0]quo12_q; + reg [63:0]quo13_q; + reg [63:0]quo14_q; + reg [63:0]quo15_q; + reg [63:0]quo16_q; + reg [63:0]quo17_q; + reg [63:0]quo18_q; + + reg [31:0]denom1; + reg [31:0]denom2; + reg [31:0]denom3; + reg [31:0]denom4; + reg [31:0]denom5; + reg [31:0]denom6; + reg [31:0]denom7; + reg [31:0]denom8; + reg [31:0]denom9; + reg [31:0]denom10; + reg [31:0]denom11; + reg [31:0]denom12; + reg [31:0]denom13; + reg [31:0]denom14; + reg [31:0]denom15; + reg [31:0]denom16; + reg [31:0]denom17; + reg [31:0]denom18; + reg [31:0]denom19; + + + always @(numer or denom0) begin + numer_temp_63 = {31'b0, numer}; + + //quo0[63] + if (numer_temp_63[94:63] >= denom0 ) begin + quo0_d[63] = 1'b1; + numer_temp_62 = {numer_temp_63[94:63] - denom0, numer_temp_63[62:0]}; + end else begin + quo0_d[63] = 1'b0; + numer_temp_62 = numer_temp_63; + end + + //quo0[62] + if (numer_temp_62[94:62] >= denom0 ) begin + quo0_d[62] = 1'b1; + numer_temp_61 = {numer_temp_62[94:62] - denom0, numer_temp_62[61:0]}; + end else begin + quo0_d[62] = 1'b0; + numer_temp_61 = numer_temp_62; + end + //quo0[61] + if (numer_temp_61[94:61] >= denom0 ) begin + quo0_d[61] = 1'b1; + numer_temp_60_d = {numer_temp_61[94:61] - denom0, numer_temp_61[60:0]}; + end else begin + quo0_d[61] = 1'b0; + numer_temp_60_d = numer_temp_61; + end + quo0_d[60:0] = 61'b0; + end + + always @ (posedge clock) begin + quo0_q <= quo0_d; + numer_temp_60_q <= numer_temp_60_d; + denom1 <= denom0; + end + + always @(numer_temp_60_q or denom1 or quo0_q) begin + quo1_d[63:61] = quo0_q[63:61]; + + //quo1_d[60] + if (numer_temp_60_q[94:60] >= denom1 ) begin + quo1_d[60] = 1'b1; + numer_temp_59 = {numer_temp_60_q[94:60] - denom1, numer_temp_60_q[59:0]}; + end else begin + quo1_d[60] = 1'b0; + numer_temp_59 = numer_temp_60_q; + end + //quo1_d[59] + if (numer_temp_59[94:59] >= denom1 ) begin + quo1_d[59] = 1'b1; + numer_temp_58 = {numer_temp_59[94:59] - denom1, numer_temp_59[58:0]}; + end else begin + quo1_d[59] = 1'b0; + numer_temp_58 = numer_temp_59; + end + //quo1_d[58] + if (numer_temp_58[94:58] >= denom1 ) begin + quo1_d[58] = 1'b1; + numer_temp_57_d = {numer_temp_58[94:58] - denom1, numer_temp_58[57:0]}; + end else begin + quo1_d[58] = 1'b0; + numer_temp_57_d = numer_temp_58; + end + quo1_d[57:0] = 58'b0; + end + + always @ (posedge clock) begin + quo1_q <= quo1_d; + numer_temp_57_q <= numer_temp_57_d; + denom2 <= denom1; + end + + always @ (numer_temp_57_q or denom2 or quo1_q) begin + quo2_d[63:58] = quo1_q[63:58]; + + //quo2_d[57] + if (numer_temp_57_q[94:57] >= denom2 ) begin + quo2_d[57] = 1'b1; + numer_temp_56 = {numer_temp_57_q[94:57] - denom2, numer_temp_57_q[56:0]}; + end else begin + quo2_d[57] = 1'b0; + numer_temp_56 = numer_temp_57_q; + end + //quo2_d[56] + if (numer_temp_56[94:56] >= denom2 ) begin + quo2_d[56] = 1'b1; + numer_temp_55 = {numer_temp_56[94:56] - denom2, numer_temp_56[55:0]}; + end else begin + quo2_d[56] = 1'b0; + numer_temp_55 = numer_temp_56; + end + //quo2_d[55] + if (numer_temp_55[94:55] >= denom2 ) begin + quo2_d[55] = 1'b1; + numer_temp_54_d = {numer_temp_55[94:55] - denom2, numer_temp_55[54:0]}; + end else begin + quo2_d[55] = 1'b0; + numer_temp_54_d = numer_temp_55; + end + quo2_d[54:0] = 55'b0; + end + + + always @ (posedge clock) begin + quo2_q <= quo2_d; + numer_temp_54_q <= numer_temp_54_d; + denom3 <= denom2; + end + + always @ (numer_temp_54_q or denom3 or quo2_q) begin + quo3_d[63:55] = quo2_q[63:55]; + + //quo3_d[54] + if (numer_temp_54_q[94:54] >= denom3 ) begin + quo3_d[54] = 1'b1; + numer_temp_53 = {numer_temp_54_q[94:54] - denom3, numer_temp_54_q[53:0]}; + end else begin + quo3_d[54] = 1'b0; + numer_temp_53 = numer_temp_54_q; + end + //quo3_d[53] + if (numer_temp_53[94:53] >= denom3 ) begin + quo3_d[53] = 1'b1; + numer_temp_52 = {numer_temp_53[94:53] - denom3, numer_temp_53[52:0]}; + end else begin + quo3_d[53] = 1'b0; + numer_temp_52 = numer_temp_53; + end + //quo3_d[52] + if (numer_temp_52[94:52] >= denom3 ) begin + quo3_d[52] = 1'b1; + numer_temp_51_d = {numer_temp_52[94:52] - denom3, numer_temp_52[51:0]}; + end else begin + quo3_d[52] = 1'b0; + numer_temp_51_d = numer_temp_52; + end + quo3_d[51:0] = 52'b0; + end + + always @ (posedge clock) begin + quo3_q <= quo3_d; + numer_temp_51_q <= numer_temp_51_d; + denom4 <= denom3; + end + + always @ (numer_temp_51_q or denom4 or quo3_q) begin + quo4_d[63:52] = quo3_q[63:52]; + + //quo4[51] + if (numer_temp_51_q[94:51] >= denom4 ) begin + quo4_d[51] = 1'b1; + numer_temp_50 = {numer_temp_51_q[94:51] - denom4, numer_temp_51_q[50:0]}; + end else begin + quo4_d[51] = 1'b0; + numer_temp_50 = numer_temp_51_q; + end + //quo4_d[50] + if (numer_temp_50[94:50] >= denom4 ) begin + quo4_d[50] = 1'b1; + numer_temp_49 = {numer_temp_50[94:50] - denom4, numer_temp_50[49:0]}; + end else begin + quo4_d[50] = 1'b0; + numer_temp_49 = numer_temp_50; + end + //quo4_d[49] + if (numer_temp_49[94:49] >= denom4 ) begin + quo4_d[49] = 1'b1; + numer_temp_48_d = {numer_temp_49[94:49] - denom4, numer_temp_49[48:0]}; + end else begin + quo4_d[49] = 1'b0; + numer_temp_48_d = numer_temp_49; + end + quo4_d[48:0] = 49'b0; + end + + always @ (posedge clock) begin + quo4_q <= quo4_d; + numer_temp_48_q <= numer_temp_48_d; + denom5 <= denom4; + end + + always @ (numer_temp_48_q or denom5 or quo4_q) begin + quo5_d[63:49] = quo4_q[63:49]; + + //quo5_d[48] + if (numer_temp_48_q[94:48] >= denom5 ) begin + quo5_d[48] = 1'b1; + numer_temp_47 = {numer_temp_48_q[94:48] - denom5, numer_temp_48_q[47:0]}; + end else begin + quo5_d[48] = 1'b0; + numer_temp_47 = numer_temp_48_q; + end + //quo5_d[47] + if (numer_temp_47[94:47] >= denom5 ) begin + quo5_d[47] = 1'b1; + numer_temp_46 = {numer_temp_47[94:47] - denom5, numer_temp_47[46:0]}; + end else begin + quo5_d[47] = 1'b0; + numer_temp_46 = numer_temp_47; + end + //quo5_d[46] + if (numer_temp_46[94:46] >= denom5 ) begin + quo5_d[46] = 1'b1; + numer_temp_45_d = {numer_temp_46[94:46] - denom5, numer_temp_46[45:0]}; + end else begin + quo5_d[46] = 1'b0; + numer_temp_45_d = numer_temp_46; + end + quo5_d[45:0] = 46'b0; + end + + always @ (posedge clock) begin + quo5_q <= quo5_d; + numer_temp_45_q <= numer_temp_45_d; + denom6 <= denom5; + end + + always @ (numer_temp_45_q or denom6 or quo5_q) begin + quo6_d[63:46] = quo5_q[63:46]; + + //quo6_d[45] + if (numer_temp_45_q[94:45] >= denom6 ) begin + quo6_d[45] = 1'b1; + numer_temp_44 = {numer_temp_45_q[94:45] - denom6, numer_temp_45_q[44:0]}; + end else begin + quo6_d[45] = 1'b0; + numer_temp_44 = numer_temp_45_q; + end + //quo6_d[44] + if (numer_temp_44[94:44] >= denom6 ) begin + quo6_d[44] = 1'b1; + numer_temp_43 = {numer_temp_44[94:44] - denom6, numer_temp_44[43:0]}; + end else begin + quo6_d[44] = 1'b0; + numer_temp_43 = numer_temp_44; + end + //quo6_d[43] + if (numer_temp_43[94:43] >= denom6 ) begin + quo6_d[43] = 1'b1; + numer_temp_42_d = {numer_temp_43[94:43] - denom6, numer_temp_43[42:0]}; + end else begin + quo6_d[43] = 1'b0; + numer_temp_42_d = numer_temp_43; + end + quo6_d[42:0] = 43'b0; + end + + always @ (posedge clock) begin + quo6_q<= quo6_d; + numer_temp_42_q <= numer_temp_42_d; + denom7 <= denom6; + end + + always @ (numer_temp_42_q or denom7 or quo6_q) begin + quo7_d[63:43] = quo6_q[63:43]; + + //quo7_d[42] + if (numer_temp_42_q[94:42] >= denom7 ) begin + quo7_d[42] = 1'b1; + numer_temp_41 = {numer_temp_42_q[94:42] - denom7, numer_temp_42_q[41:0]}; + end else begin + quo7_d[42] = 1'b0; + numer_temp_41 = numer_temp_42_q; + end + //quo7_d[41] + if (numer_temp_41[94:41] >= denom7 ) begin + quo7_d[41] = 1'b1; + numer_temp_40 = {numer_temp_41[94:41] - denom7, numer_temp_41[40:0]}; + end else begin + quo7_d[41] = 1'b0; + numer_temp_40 = numer_temp_41; + end + //quo7_d[40] + if (numer_temp_40[94:40] >= denom7 ) begin + quo7_d[40] = 1'b1; + numer_temp_39_d = {numer_temp_40[94:40] - denom7, numer_temp_40[39:0]}; + end else begin + quo7_d[40] = 1'b0; + numer_temp_39_d = numer_temp_40; + end + quo7_d[39:0] = 40'b0; + end + + always @ (posedge clock) begin + quo7_q <= quo7_d; + numer_temp_39_q <= numer_temp_39_d; + denom8 <= denom7; + end + + always @ (numer_temp_39_q or denom8 or quo7_q) begin + quo8_d[63:40] = quo7_q[63:40]; + + //quo8[39] + if (numer_temp_39_q[94:39] >= denom8 ) begin + quo8_d[39] = 1'b1; + numer_temp_38 = {numer_temp_39_q[94:39] - denom8, numer_temp_39_q[38:0]}; + end else begin + quo8_d[39] = 1'b0; + numer_temp_38 = numer_temp_39_q; + end + //quo8_d[38] + if (numer_temp_38[94:38] >= denom8 ) begin + quo8_d[38] = 1'b1; + numer_temp_37 = {numer_temp_38[94:38] - denom8, numer_temp_38[37:0]}; + end else begin + quo8_d[38] = 1'b0; + numer_temp_37 = numer_temp_38; + end + //quo8_d[37] + if (numer_temp_37[94:37] >= denom8 ) begin + quo8_d[37] = 1'b1; + numer_temp_36_d = {numer_temp_37[94:37] - denom8, numer_temp_37[36:0]}; + end else begin + quo8_d[37] = 1'b0; + numer_temp_36_d = numer_temp_37; + end + quo8_d[36:0] = 37'b0; + end + + always @ (posedge clock) begin + quo8_q <= quo8_d; + numer_temp_36_q <= numer_temp_36_d; + denom9 <= denom8; + end + + always @ (numer_temp_36_q or denom9 or quo8_q) begin + quo9_d[63:37] = quo8_q[63:37]; + + //quo9[36] + if (numer_temp_36_q[94:36] >= denom9 ) begin + quo9_d[36] = 1'b1; + numer_temp_35 = {numer_temp_36_q[94:36] - denom9, numer_temp_36_q[35:0]}; + end else begin + quo9_d[36] = 1'b0; + numer_temp_35 = numer_temp_36_q; + end + //quo9_d[35] + if (numer_temp_35[94:35] >= denom9 ) begin + quo9_d[35] = 1'b1; + numer_temp_34 = {numer_temp_35[94:35] - denom9, numer_temp_35[34:0]}; + end else begin + quo9_d[35] = 1'b0; + numer_temp_34 = numer_temp_35; + end + //quo9_d[34] + if (numer_temp_34[94:34] >= denom9 ) begin + quo9_d[34] = 1'b1; + numer_temp_33_d = {numer_temp_34[94:34] - denom9, numer_temp_34[33:0]}; + end else begin + quo9_d[34] = 1'b0; + numer_temp_33_d = numer_temp_34; + end + quo9_d[33:0] = 34'b0; + end + + always @ (posedge clock) begin + quo9_q <= quo9_d; + numer_temp_33_q <= numer_temp_33_d; + denom10 <= denom9; + end + + always @ (numer_temp_33_q or denom10 or quo9_q) begin + quo10_d[63:34] = quo9_q[63:34]; + + //quo10_d[33] + if (numer_temp_33_q[94:33] >= denom10 ) begin + quo10_d[33] = 1'b1; + numer_temp_32 = {numer_temp_33_q[94:33] - denom10, numer_temp_33_q[32:0]}; + end else begin + quo10_d[33] = 1'b0; + numer_temp_32 = numer_temp_33_q; + end + //quo10_d[32] + if (numer_temp_32[94:32] >= denom10 ) begin + quo10_d[32] = 1'b1; + numer_temp_31 = {numer_temp_32[94:32] - denom10, numer_temp_32[31:0]}; + end else begin + quo10_d[32] = 1'b0; + numer_temp_31 = numer_temp_32; + end + //quo10_d[31] + if (numer_temp_31[94:31] >= denom10 ) begin + quo10_d[31] = 1'b1; + numer_temp_30_d = {numer_temp_31[94:31] - denom10, numer_temp_31[30:0]}; + end else begin + quo10_d[31] = 1'b0; + numer_temp_30_d = numer_temp_31; + end + quo10_d[30:0] = 31'b0; + end + + always @ (posedge clock) begin + quo10_q <= quo10_d; + numer_temp_30_q <= numer_temp_30_d; + denom11 <= denom10; + end + + always @ (numer_temp_30_q or denom11 or quo10_q) begin + quo11_d[63:31] = quo10_q[63:31]; + + //quo11[30] + if (numer_temp_30_q[94:30] >= denom11 ) begin + quo11_d[30] = 1'b1; + numer_temp_29 = {numer_temp_30_q[94:30] - denom11, numer_temp_30_q[29:0]}; + end else begin + quo11_d[30] = 1'b0; + numer_temp_29 = numer_temp_30_q; + end + //quo11_d[29] + if (numer_temp_29[94:29] >= denom11 ) begin + quo11_d[29] = 1'b1; + numer_temp_28 = {numer_temp_29[94:29] - denom11, numer_temp_29[28:0]}; + end else begin + quo11_d[29] = 1'b0; + numer_temp_28 = numer_temp_29; + end + //quo11_d[28] + if (numer_temp_28[94:28] >= denom11 ) begin + quo11_d[28] = 1'b1; + numer_temp_27_d = {numer_temp_28[94:28] - denom11, numer_temp_28[27:0]}; + end else begin + quo11_d[28] = 1'b0; + numer_temp_27_d = numer_temp_28; + end + quo11_d[27:0] = 28'b0; + end + + always @ (posedge clock) begin + quo11_q <= quo11_d; + numer_temp_27_q <= numer_temp_27_d; + denom12 <= denom11; + end + + always @ (numer_temp_27_q or denom12 or quo11_q) begin + quo12_d[63:28] = quo11_q[63:28]; + + //quo12[27] + if (numer_temp_27_q[94:27] >= denom12 ) begin + quo12_d[27] = 1'b1; + numer_temp_26 = {numer_temp_27_q[94:27] - denom12, numer_temp_27_q[26:0]}; + end else begin + quo12_d[27] = 1'b0; + numer_temp_26 = numer_temp_27_q; + end + //quo12_d[26] + if (numer_temp_26[94:26] >= denom12 ) begin + quo12_d[26] = 1'b1; + numer_temp_25 = {numer_temp_26[94:26] - denom12, numer_temp_26[25:0]}; + end else begin + quo12_d[26] = 1'b0; + numer_temp_25 = numer_temp_26; + end + //quo12_d[25] + if (numer_temp_25[94:25] >= denom12 ) begin + quo12_d[25] = 1'b1; + numer_temp_24 = {numer_temp_25[94:25] - denom12, numer_temp_25[24:0]}; + end else begin + quo12_d[25] = 1'b0; + numer_temp_24 = numer_temp_25; + end + //quo12_d[24] + if (numer_temp_24[94:24] >= denom12 ) begin + quo12_d[24] = 1'b1; + numer_temp_23_d = {numer_temp_24[94:24] - denom12, numer_temp_24[23:0]}; + end else begin + quo12_d[24] = 1'b0; + numer_temp_23_d = numer_temp_24; + end + quo12_d[23:0] = 24'b0; + end + + always @ (posedge clock) begin + quo12_q <= quo12_d; + numer_temp_23_q <= numer_temp_23_d; + denom13 <= denom12; + end + + always @ (numer_temp_23_q or denom13 or quo12_q) begin + quo13_d[63:24] = quo12_q[63:24]; + + //quo13_d[23] + if (numer_temp_23_q[94:23] >= denom13 ) begin + quo13_d[23] = 1'b1; + numer_temp_22 = {numer_temp_23_q[94:23] - denom13, numer_temp_23_q[22:0]}; + end else begin + quo13_d[23] = 1'b0; + numer_temp_22 = numer_temp_23_q; + end + //quo13_d[22] + if (numer_temp_22[94:22] >= denom13 ) begin + quo13_d[22] = 1'b1; + numer_temp_21 = {numer_temp_22[94:22] - denom13, numer_temp_22[21:0]}; + end else begin + quo13_d[22] = 1'b0; + numer_temp_21 = numer_temp_22; + end + //quo13_d[21] + if (numer_temp_21[94:21] >= denom13 ) begin + quo13_d[21] = 1'b1; + numer_temp_20 = {numer_temp_21[94:21] - denom13, numer_temp_21[20:0]}; + end else begin + quo13_d[21] = 1'b0; + numer_temp_20 = numer_temp_21; + end + //quo13_d[20] + if (numer_temp_20[94:20] >= denom13 ) begin + quo13_d[20] = 1'b1; + numer_temp_19_d = {numer_temp_20[94:20] - denom13, numer_temp_20[19:0]}; + end else begin + quo13_d[20] = 1'b0; + numer_temp_19_d = numer_temp_20; + end + quo13_d[19:0] = 20'b0; + end + + always @ (posedge clock) begin + quo13_q <= quo13_d; + numer_temp_19_q <= numer_temp_19_d; + denom14 <= denom13; + end + + always @ (numer_temp_19_q or denom14 or quo13_q) begin + quo14_d[63:20] = quo13_q[63:20]; + + //quo14_d[19] + if (numer_temp_19_q[94:19] >= denom14 ) begin + quo14_d[19] = 1'b1; + numer_temp_18 = {numer_temp_19_q[94:19] - denom14, numer_temp_19_q[18:0]}; + end else begin + quo14_d[19] = 1'b0; + numer_temp_18 = numer_temp_19_q; + end + //quo14_d[18] + if (numer_temp_18[94:18] >= denom14 ) begin + quo14_d[18] = 1'b1; + numer_temp_17 = {numer_temp_18[94:18] - denom14, numer_temp_18[17:0]}; + end else begin + quo14_d[18] = 1'b0; + numer_temp_17 = numer_temp_18; + end + //quo14_d[17] + if (numer_temp_17[94:17] >= denom14 ) begin + quo14_d[17] = 1'b1; + numer_temp_16 = {numer_temp_17[94:17] - denom14, numer_temp_17[16:0]}; + end else begin + quo14_d[17] = 1'b0; + numer_temp_16 = numer_temp_17; + end + //quo14_d[16] + if (numer_temp_16[94:16] >= denom14 ) begin + quo14_d[16] = 1'b1; + numer_temp_15_d = {numer_temp_16[94:16] - denom14, numer_temp_16[15:0]}; + end else begin + quo14_d[16] = 1'b0; + numer_temp_15_d = numer_temp_16; + end + quo14_d[15:0] = 16'b0; + end + + always @ (posedge clock) begin + quo14_q <= quo14_d; + numer_temp_15_q <= numer_temp_15_d; + denom15 <= denom14; + end + + always @ (numer_temp_15_q or denom15 or quo14_q) begin + quo15_d[63:16] = quo14_q[63:16]; + + //quo15_d[15] + if (numer_temp_15_q[94:15] >= denom15 ) begin + quo15_d[15] = 1'b1; + numer_temp_14 = {numer_temp_15_q[94:15] - denom15, numer_temp_15_q[14:0]}; + end else begin + quo15_d[15] = 1'b0; + numer_temp_14 = numer_temp_15_q; + end + //quo15_d[14] + if (numer_temp_14[94:14] >= denom15 ) begin + quo15_d[14] = 1'b1; + numer_temp_13 = {numer_temp_14[94:14] - denom15, numer_temp_14[13:0]}; + end else begin + quo15_d[14] = 1'b0; + numer_temp_13 = numer_temp_14; + end + //quo15_d[13] + if (numer_temp_13[94:13] >= denom15 ) begin + quo15_d[13] = 1'b1; + numer_temp_12 = {numer_temp_13[94:13] - denom15, numer_temp_13[12:0]}; + end else begin + quo15_d[13] = 1'b0; + numer_temp_12 = numer_temp_13; + end + //quo15_d[12] + if (numer_temp_12[94:12] >= denom15 ) begin + quo15_d[12] = 1'b1; + numer_temp_11_d = {numer_temp_12[94:12] - denom15, numer_temp_12[11:0]}; + end else begin + quo15_d[12] = 1'b0; + numer_temp_11_d = numer_temp_12; + end + quo15_d[11:0] = 12'b0; + end + + always @ (posedge clock) begin + quo15_q <= quo15_d; + numer_temp_11_q <= numer_temp_11_d; + denom16 <= denom15; + end + + always @ (numer_temp_11_q or denom16 or quo15_q) begin + quo16_d[63:12] = quo15_q[63:12]; + + //quo16_d[11] + if (numer_temp_11_q[94:11] >= denom16 ) begin + quo16_d[11] = 1'b1; + numer_temp_10 = {numer_temp_11_q[94:11] - denom16, numer_temp_11_q[10:0]}; + end else begin + quo16_d[11] = 1'b0; + numer_temp_10 = numer_temp_11_q; + end + //quo16_d[10] + if (numer_temp_10[94:10] >= denom16 ) begin + quo16_d[10] = 1'b1; + numer_temp_9 = {numer_temp_10[94:10] - denom16, numer_temp_10[9:0]}; + end else begin + quo16_d[10] = 1'b0; + numer_temp_9 = numer_temp_10; + end + //quo16_d[9] + if (numer_temp_9[94:9] >= denom16 ) begin + quo16_d[9] = 1'b1; + numer_temp_8 = {numer_temp_9[94:9] - denom16, numer_temp_9[8:0]}; + end else begin + quo16_d[9] = 1'b0; + numer_temp_8 = numer_temp_9; + end + //quo16_d[8] + if (numer_temp_8[94:8] >= denom16 ) begin + quo16_d[8] = 1'b1; + numer_temp_7_d = {numer_temp_8[94:8] - denom16, numer_temp_8[7:0]}; + end else begin + quo16_d[8] = 1'b0; + numer_temp_7_d = numer_temp_8; + end + quo16_d[7:0] = 8'b0; + end + + always @ (posedge clock) begin + quo16_q <= quo16_d; + numer_temp_7_q <= numer_temp_7_d; + denom17 <= denom16; + end + + always @ (numer_temp_7_q or denom17 or quo16_q) begin + quo17_d[63:8] = quo16_q[63:8]; + + //quo17_d[7] + if (numer_temp_7_q[94:7] >= denom17 ) begin + quo17_d[7] = 1'b1; + numer_temp_6 = {numer_temp_7_q[94:7] - denom17, numer_temp_7_q[6:0]}; + end else begin + quo17_d[7] = 1'b0; + numer_temp_6 = numer_temp_7_q; + end + //quo17_d[6] + if (numer_temp_6[94:6] >= denom17 ) begin + quo17_d[6] = 1'b1; + numer_temp_5 = {numer_temp_6[94:6] - denom17, numer_temp_6[5:0]}; + end else begin + quo17_d[6] = 1'b0; + numer_temp_5 = numer_temp_6; + end + //quo17_d[5] + if (numer_temp_5[94:5] >= denom17 ) begin + quo17_d[5] = 1'b1; + numer_temp_4 = {numer_temp_5[94:5] - denom17, numer_temp_5[4:0]}; + end else begin + quo17_d[5] = 1'b0; + numer_temp_4 = numer_temp_5; + end + //quo17_d[4] + if (numer_temp_4[94:4] >= denom17 ) begin + quo17_d[4] = 1'b1; + numer_temp_3_d = {numer_temp_4[94:4] - denom17, numer_temp_4[3:0]}; + end else begin + quo17_d[4] = 1'b0; + numer_temp_3_d = numer_temp_4; + end + quo17_d[3:0] = 4'b0; + end + + always @ (posedge clock) begin + quo17_q <= quo17_d; + numer_temp_3_q <= numer_temp_3_d; + denom18 <= denom17; + end + + always @ (numer_temp_3_q or denom18 or quo17_q) begin + quo18_d[63:4] = quo17_q[63:4]; + + //quo18_d[3] + if (numer_temp_3_q[94:3] >= denom18 ) begin + quo18_d[3] = 1'b1; + numer_temp_2 = {numer_temp_3_q[94:3] - denom18, numer_temp_3_q[2:0]}; + end else begin + quo18_d[3] = 1'b0; + numer_temp_2 = numer_temp_3_q; + end + //quo18_d[2] + if (numer_temp_2[94:2] >= denom18 ) begin + quo18_d[2] = 1'b1; + numer_temp_1_d = {numer_temp_2[94:2] - denom18, numer_temp_2[1:0]}; + end else begin + quo18_d[2] = 1'b0; + numer_temp_1_d = numer_temp_2; + end + quo18_d[1:0] = 2'b0; + end + + always @ (posedge clock) begin + quo18_q <= quo18_d; + numer_temp_1_q <= numer_temp_1_d; + denom19 <= denom18; + end + + always @ (numer_temp_1_q or denom19 or quo18_q) begin + quo19_d[63:2] = quo18_q[63:2]; + //quo19_d[1] + if (numer_temp_1_q[94:1] >= denom19 ) begin + quo19_d[1] = 1'b1; + numer_temp_0 = {numer_temp_1_q[94:1] - denom19, numer_temp_1_q[0:0]}; + end else begin + quo19_d[1] = 1'b0; + numer_temp_0 = numer_temp_1_q; + + end + //quo19_d[0] + if (numer_temp_0[94:0] >= denom19 ) begin + quo19_d[0] = 1'b1; + numer_temp = numer_temp_0[94:0] - denom19; + end else begin + quo19_d[0] = 1'b0; + numer_temp = numer_temp_0; + end + end + + assign quotient = quo19_d; + assign remain = numer_temp[31:0]; + + + +endmodule + +/*module sqrt_64b (clk, num, res); + input clk; + input [63:0]num; + output [31:0]res; + reg [31:0]res;*/ + +//`timescale 1 ns / 1 ps + +module Sqrt_64b (clk, num_, res); + input clk; + input [63:0]num_; + output [31:0]res; + reg [31:0]res; + + reg [63:0]num; + + always @ (posedge clk) + begin + num <= num_; + end + +///////////////////////////////////////////////////Unchanged starts here + +// reg [63:0] one_[32:0]; +// reg [63:0] res_[32:0]; +// reg [63:0] op_[32:0]; + + wire [63:0]one__0; + reg [63:0]one__1; + reg [63:0]one__2; + reg [63:0]one__3_d, one__3_q; + reg [63:0]one__4; + reg [63:0]one__5; + reg [63:0]one__6; + reg [63:0]one__7_d, one__7_q; + reg [63:0]one__8; + reg [63:0]one__9; + reg [63:0]one__10; + reg [63:0]one__11_d, one__11_q; + reg [63:0]one__12; + reg [63:0]one__13; + reg [63:0]one__14; + reg [63:0]one__15_d, one__15_q; + reg [63:0]one__16; + reg [63:0]one__17; + reg [63:0]one__18_d, one__18_q; + reg [63:0]one__19; + reg [63:0]one__20; + reg [63:0]one__21_d, one__21_q; + reg [63:0]one__22; + reg [63:0]one__23; + reg [63:0]one__24_d, one__24_q; + reg [63:0]one__25; + reg [63:0]one__26; + reg [63:0]one__27_d, one__27_q; + reg [63:0]one__28; + reg [63:0]one__29; + reg [63:0]one__30_d, one__30_q; + reg [63:0]one__31; + reg [63:0]one__32; + + wire [63:0]res__0; + reg [63:0]res__1; + reg [63:0]res__2; + reg [63:0]res__3_d, res__3_q; + reg [63:0]res__4; + reg [63:0]res__5; + reg [63:0]res__6; + reg [63:0]res__7_d, res__7_q; + reg [63:0]res__8; + reg [63:0]res__9; + reg [63:0]res__10; + reg [63:0]res__11_d, res__11_q; + reg [63:0]res__12; + reg [63:0]res__13; + reg [63:0]res__14; + reg [63:0]res__15_d, res__15_q; + reg [63:0]res__16; + reg [63:0]res__17; + reg [63:0]res__18_d, res__18_q; + reg [63:0]res__19; + reg [63:0]res__20; + reg [63:0]res__21_d, res__21_q; + reg [63:0]res__22; + reg [63:0]res__23; + reg [63:0]res__24_d, res__24_q; + reg [63:0]res__25; + reg [63:0]res__26; + reg [63:0]res__27_d, res__27_q; + reg [63:0]res__28; + reg [63:0]res__29; + reg [63:0]res__30_d, res__30_q; + reg [63:0]res__31; + reg [63:0]res__32; + + wire [63:0]op__0; + reg [63:0]op__1; + reg [63:0]op__2; + reg [63:0]op__3_d, op__3_q; + reg [63:0]op__4; + reg [63:0]op__5; + reg [63:0]op__6; + reg [63:0]op__7_d, op__7_q; + reg [63:0]op__8; + reg [63:0]op__9; + reg [63:0]op__10; + reg [63:0]op__11_d, op__11_q; + reg [63:0]op__12; + reg [63:0]op__13; + reg [63:0]op__14; + reg [63:0]op__15_d, op__15_q; + reg [63:0]op__16; + reg [63:0]op__17; + reg [63:0]op__18_d, op__18_q; + reg [63:0]op__19; + reg [63:0]op__20; + reg [63:0]op__21_d, op__21_q; + reg [63:0]op__22; + reg [63:0]op__23; + reg [63:0]op__24_d, op__24_q; + reg [63:0]op__25; + reg [63:0]op__26; + reg [63:0]op__27_d, op__27_q; + reg [63:0]op__28; + reg [63:0]op__29; + reg [63:0]op__30_d, op__30_q; + reg [63:0]op__31; + reg [63:0]op__32; + + + reg [63:0]one; //This is the one that is selected in first expanded loop + reg [31:0]one_tmp; + + always @ (num) begin + + //The first for-loop: + //all of these will be zero no matter how 'one' is selected. + one[1] = 0; + one[3] = 0; + one[5] = 0; + one[7] = 0; + one[9] = 0; + one[11] = 0; + one[13] = 0; + one[15] = 0; + one[17] = 0; + one[19] = 0; + one[21] = 0; + one[23] = 0; + one[25] = 0; + one[27] = 0; + one[29] = 0; + one[31] = 0; + one[33] = 0; + one[35] = 0; + one[37] = 0; + one[39] = 0; + one[41] = 0; + one[43] = 0; + one[45] = 0; + one[47] = 0; + one[49] = 0; + one[51] = 0; + one[53] = 0; + one[55] = 0; + one[57] = 0; + one[59] = 0; + one[61] = 0; + one[63] = 0; + + one_tmp[0] = num[0]|num[1]; + one_tmp[1] = num[2]|num[3]; + one_tmp[2] = num[4]|num[5]; + one_tmp[3] = num[6]|num[7]; + one_tmp[4] = num[8]|num[9]; + one_tmp[5] = num[10]|num[11]; + one_tmp[6] = num[12]|num[13]; + one_tmp[7] = num[14]|num[15]; + one_tmp[8] = num[16]|num[17]; + one_tmp[9] = num[18]|num[19]; + one_tmp[10] = num[20]|num[21]; + one_tmp[11] = num[22]|num[23]; + one_tmp[12] = num[24]|num[25]; + one_tmp[13] = num[26]|num[27]; + one_tmp[14] = num[28]|num[29]; + one_tmp[15] = num[30]|num[31]; + one_tmp[16] = num[32]|num[33]; + one_tmp[17] = num[34]|num[35]; + one_tmp[18] = num[36]|num[37]; + one_tmp[19] = num[38]|num[39]; + one_tmp[20] = num[40]|num[41]; + one_tmp[21] = num[42]|num[43]; + one_tmp[22] = num[44]|num[45]; + one_tmp[23] = num[46]|num[47]; + one_tmp[24] = num[48]|num[49]; + one_tmp[25] = num[50]|num[51]; + one_tmp[26] = num[52]|num[53]; + one_tmp[27] = num[54]|num[55]; + one_tmp[28] = num[56]|num[57]; + one_tmp[29] = num[58]|num[59]; + one_tmp[30] = num[60]|num[61]; + one_tmp[31] = num[62]|num[63]; + + one[0] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&~one_tmp[3]&~one_tmp[2]&~one_tmp[1]&one_tmp[0]; + one[2] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&~one_tmp[3]&~one_tmp[2]&one_tmp[1]; + one[4] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&~one_tmp[3]&one_tmp[2]; + one[6] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&~one_tmp[4]&one_tmp[3]; + one[8] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&~one_tmp[5]&one_tmp[4]; + one[10] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&~one_tmp[6]&one_tmp[5]; + one[12] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&~one_tmp[7]&one_tmp[6]; + one[14] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&~one_tmp[8]&one_tmp[7]; + one[16] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&~one_tmp[9]&one_tmp[8]; + one[18] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&~one_tmp[10]&one_tmp[9]; + one[20] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&~one_tmp[11]&one_tmp[10]; + one[22] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&~one_tmp[12]&one_tmp[11]; + one[24] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&~one_tmp[13]&one_tmp[12]; + one[26] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&~one_tmp[14]&one_tmp[13]; + one[28] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&~one_tmp[15]&one_tmp[14]; + one[30] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&~one_tmp[16]&one_tmp[15]; + one[32] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&~one_tmp[17]&one_tmp[16]; + one[34] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&~one_tmp[18]&one_tmp[17]; + one[36] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&~one_tmp[19]&one_tmp[18]; + one[38] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&~one_tmp[20]&one_tmp[19]; + one[40] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&~one_tmp[21]&one_tmp[20]; + one[42] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&~one_tmp[22]&one_tmp[21]; + one[44] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&~one_tmp[23]&one_tmp[22]; + one[46] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&~one_tmp[24]&one_tmp[23]; + one[48] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&~one_tmp[25]&one_tmp[24]; + one[50] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&~one_tmp[26]&one_tmp[25]; + one[52] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&~one_tmp[27]&one_tmp[26]; + one[54] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&~one_tmp[28]&one_tmp[27]; + one[56] = ~one_tmp[31]&~one_tmp[30]&~one_tmp[29]&one_tmp[28]; + one[58] = ~one_tmp[31]&~one_tmp[30]&one_tmp[29]; + one[60] = ~one_tmp[31]&one_tmp[30]; + one[62] = one_tmp[31]; + end + +// //2nd for-loop: +// integer i; +// always @* begin +// op_[0] = num; +// one_[0] = one; +// res_[0] = 64'b0; +// res = 63'b0; +// res_assigned = 1'b0; +// +// for (i = 0; i <= 31; i=i+1) begin +// if ((one_[i] == 0) & ~res_assigned) begin +// res = res_[i]; +// res_assigned = 1'b1; +// end +// +// //Define the next stage: +// if (op_[i] >= res_[i] + one_[i]) begin +// op_[i+1] = op_[i] - res_[i] - one_[i]; +// res_[i+1] = (res_[i]>>1) + one_[i]; +// end else begin +// op_[i+1] = op_[i]; //this line had to be added for the verilog version. +// res_[i+1] = (res_[i]>>1); +// end +// one_[i+1] = (one_[i] >> 2); +// end +// +// //Add the part for really big numbers later: +// if (~res_assigned) begin +// res = res_[32]; +// end +// end + + //If-statement about defining the next stage: + assign op__0 = num; + assign res__0 = 64'b0; + assign one__0 = one; + + always @ (res__0 or op__0 or one__0) begin + + //i = 0 + if (op__0 >= res__0 + one__0) begin + op__1 = op__0 - res__0 - one__0; + res__1 = (res__0>>1) + one__0; + end else begin + op__1 = op__0; + res__1 = (res__0>>1); + end + one__1 = (one__0 >> 2); + + //i = 1 + if (op__1 >= res__1 + one__1) begin + op__2 = op__1 - res__1 - one__1; + res__2 = (res__1>>1) + one__1; + end else begin + op__2 = op__1; + res__2 = (res__1>>1); + end + one__2 = (one__1 >> 2); + + //i = 2 + if (op__2 >= res__2 + one__2) begin + op__3_d = op__2 - res__2 - one__2; + res__3_d = (res__2>>1) + one__2; + end else begin + op__3_d = op__2; + res__3_d = (res__2>>1); + end + one__3_d = (one__2 >> 2); + end + + always @ (posedge clk) begin + op__3_q <= op__3_d; + res__3_q <= res__3_d; + one__3_q <= one__3_d; + end + + always @ (op__3_q or res__3_q or one__3_q) begin + //i = 3 + if (op__3_q >= res__3_q + one__3_q) begin + op__4 = op__3_q - res__3_q - one__3_q; + res__4 = (res__3_q>>1) + one__3_q; + end else begin + op__4 = op__3_q; + res__4 = (res__3_q>>1); + end + one__4 = (one__3_q >> 2); + + //i = 4 + if (op__4 >= res__4 + one__4) begin + op__5 = op__4 - res__4 - one__4; + res__5 = (res__4>>1) + one__4; + end else begin + op__5 = op__4; + res__5 = (res__4>>1); + end + one__5 = (one__4 >> 2); + + //i = 5 + if (op__5 >= res__5 + one__5) begin + op__6 = op__5 - res__5 - one__5; + res__6 = (res__5>>1) + one__5; + end else begin + op__6 = op__5; + res__6 = (res__5>>1); + end + one__6 = (one__5 >> 2); + + //i = 6 + if (op__6 >= res__6 + one__6) begin + op__7_d = op__6 - res__6 - one__6; + res__7_d = (res__6>>1) + one__6; + end else begin + op__7_d = op__6; + res__7_d = (res__6>>1); + end + one__7_d = (one__6 >> 2); + end + + always @ (posedge clk) begin + op__7_q <= op__7_d; + one__7_q <= one__7_d; + res__7_q <= res__7_d; + end + + always @ (op__7_q or res__7_q or one__7_q) begin + //i = 7 + if (op__7_q >= res__7_q + one__7_q) begin + op__8 = op__7_q - res__7_q - one__7_q; + res__8 = (res__7_q>>1) + one__7_q; + end else begin + op__8 = op__7_q; + res__8 = (res__7_q>>1); + end + one__8 = (one__7_q >> 2); + + //i = 8 + if (op__8 >= res__8 + one__8) begin + op__9 = op__8 - res__8 - one__8; + res__9 = (res__8>>1) + one__8; + end else begin + op__9 = op__8; + res__9 = (res__8>>1); + end + one__9 = (one__8 >> 2); + + //i = 9 + if (op__9 >= res__9 + one__9) begin + op__10 = op__9 - res__9 - one__9; + res__10 = (res__9>>1) + one__9; + end else begin + op__10 = op__9; + res__10 = (res__9>>1); + end + one__10 = (one__9 >> 2); + + //i = 10 + if (op__10 >= res__10 + one__10) begin + op__11_d = op__10 - res__10 - one__10; + res__11_d = (res__10>>1) + one__10; + end else begin + op__11_d = op__10; + res__11_d = (res__10>>1); + end + one__11_d = (one__10 >> 2); + end + + always @ (posedge clk) begin + op__11_q <= op__11_d; + one__11_q <= one__11_d; + res__11_q <= res__11_d; + end + + always @ (op__11_q or res__11_q or one__11_q) begin + //i = 11 + if (op__11_q >= res__11_q + one__11_q) begin + op__12 = op__11_q - res__11_q - one__11_q; + res__12 = (res__11_q>>1) + one__11_q; + end else begin + op__12 = op__11_q; + res__12 = (res__11_q>>1); + end + one__12 = (one__11_q >> 2); + + //i = 12 + if (op__12 >= res__12 + one__12) begin + op__13 = op__12 - res__12 - one__12; + res__13 = (res__12>>1) + one__12; + end else begin + op__13 = op__12; + res__13 = (res__12>>1); + end + one__13 = (one__12 >> 2); + + //i = 13 + if (op__13 >= res__13 + one__13) begin + op__14 = op__13 - res__13 - one__13; + res__14 = (res__13>>1) + one__13; + end else begin + op__14 = op__13; + res__14 = (res__13>>1); + end + one__14 = (one__13 >> 2); + + //i = 14 + if (op__14 >= res__14 + one__14) begin + op__15_d = op__14 - res__14 - one__14; + res__15_d = (res__14>>1) + one__14; + end else begin + op__15_d = op__14; + res__15_d = (res__14>>1); + end + one__15_d = (one__14 >> 2); + end + + always @ (posedge clk) begin + op__15_q <= op__15_d; + one__15_q <= one__15_d; + res__15_q <= res__15_d; + end + + always @ (op__15_q or res__15_q or one__15_q) begin + //i = 15 + if (op__15_q >= res__15_q + one__15_q) begin + op__16 = op__15_q - res__15_q - one__15_q; + res__16 = (res__15_q>>1) + one__15_q; + end else begin + op__16 = op__15_q; + res__16 = (res__15_q>>1); + end + one__16 = (one__15_q >> 2); + + //i = 16 + if (op__16 >= res__16 + one__16) begin + op__17 = op__16 - res__16 - one__16; + res__17 = (res__16>>1) + one__16; + end else begin + op__17 = op__16; + res__17 = (res__16>>1); + end + one__17 = (one__16 >> 2); + + //i = 17 + if (op__17 >= res__17 + one__17) begin + op__18_d = op__17 - res__17 - one__17; + res__18_d = (res__17>>1) + one__17; + end else begin + op__18_d = op__17; + res__18_d = (res__17>>1); + end + one__18_d = (one__17 >> 2); + end + + always @ (posedge clk) begin + op__18_q <= op__18_d; + one__18_q <= one__18_d; + res__18_q <= res__18_d; + end + + always @ (op__18_q or res__18_q or one__18_q) begin + //i = 18 + if (op__18_q >= res__18_q + one__18_q) begin + op__19 = op__18_q - res__18_q - one__18_q; + res__19 = (res__18_q>>1) + one__18_q; + end else begin + op__19 = op__18_q; + res__19 = (res__18_q>>1); + end + one__19 = (one__18_q >> 2); + + //i = 19 + if (op__19 >= res__19 + one__19) begin + op__20 = op__19 - res__19 - one__19; + res__20 = (res__19>>1) + one__19; + end else begin + op__20 = op__19; + res__20 = (res__19>>1); + end + one__20 = (one__19 >> 2); + + //i = 20 + if (op__20 >= res__20 + one__20) begin + op__21_d = op__20 - res__20 - one__20; + res__21_d = (res__20>>1) + one__20; + end else begin + op__21_d = op__20; + res__21_d = (res__20>>1); + end + one__21_d = (one__20 >> 2); + end + + always @ (posedge clk) begin + op__21_q <= op__21_d; + one__21_q <= one__21_d; + res__21_q <= res__21_d; + end + + always @ (op__21_q or res__21_q or one__21_q) begin + //i = 21 + if (op__21_q >= res__21_q + one__21_q) begin + op__22 = op__21_q - res__21_q - one__21_q; + res__22 = (res__21_q>>1) + one__21_q; + end else begin + op__22 = op__21_q; + res__22 = (res__21_q>>1); + end + one__22 = (one__21_q >> 2); + + //i = 22 + if (op__22 >= res__22 + one__22) begin + op__23 = op__22 - res__22 - one__22; + res__23 = (res__22>>1) + one__22; + end else begin + op__23 = op__22; + res__23 = (res__22>>1); + end + one__23 = (one__22 >> 2); + + //i = 23 + if (op__23 >= res__23 + one__23) begin + op__24_d = op__23 - res__23 - one__23; + res__24_d = (res__23>>1) + one__23; + end else begin + op__24_d = op__23; + res__24_d = (res__23>>1); + end + one__24_d = (one__23 >> 2); + end + + always @ (posedge clk) begin + op__24_q <= op__24_d; + one__24_q <= one__24_d; + res__24_q <= res__24_d; + end + + always @ (op__24_q or res__24_q or one__24_q) begin + //i = 24 + if (op__24_q >= res__24_q + one__24_q) begin + op__25 = op__24_q - res__24_q - one__24_q; + res__25 = (res__24_q>>1) + one__24_q; + end else begin + op__25 = op__24_q; + res__25 = (res__24_q>>1); + end + one__25 = (one__24_q >> 2); + + //i = 25 + if (op__25 >= res__25 + one__25) begin + op__26 = op__25 - res__25 - one__25; + res__26 = (res__25>>1) + one__25; + end else begin + op__26 = op__25; + res__26 = (res__25>>1); + end + one__26 = (one__25 >> 2); + + //i = 26 + if (op__26 >= res__26 + one__26) begin + op__27_d = op__26 - res__26 - one__26; + res__27_d = (res__26>>1) + one__26; + end else begin + op__27_d = op__26; + res__27_d = (res__26>>1); + end + one__27_d = (one__26 >> 2); + end + + always @ (posedge clk) begin + op__27_q <= op__27_d; + one__27_q <= one__27_d; + res__27_q <= res__27_d; + end + + always @ (op__27_q or res__27_q or one__27_q) begin + //i = 27 + if (op__27_q >= res__27_q + one__27_q) begin + op__28 = op__27_q - res__27_q - one__27_q; + res__28 = (res__27_q>>1) + one__27_q; + end else begin + op__28 = op__27_q; + res__28 = (res__27_q>>1); + end + one__28 = (one__27_q >> 2); + + //i = 28 + if (op__28 >= res__28 + one__28) begin + op__29 = op__28 - res__28 - one__28; + res__29 = (res__28>>1) + one__28; + end else begin + op__29 = op__28; + res__29 = (res__28>>1); + end + one__29 = (one__28 >> 2); + + //i = 29 + if (op__29 >= res__29 + one__29) begin + op__30_d = op__29 - res__29 - one__29; + res__30_d = (res__29>>1) + one__29; + end else begin + op__30_d = op__29; + res__30_d = (res__29>>1); + end + one__30_d = (one__29 >> 2); + end + + always @ (posedge clk) begin + op__30_q <= op__30_d; + one__30_q <= one__30_d; + res__30_q <= res__30_d; + end + + always @* begin + //i = 30 + if (op__30_q >= res__30_q + one__30_q) begin + op__31 = op__30_q - res__30_q - one__30_q; + res__31 = (res__30_q>>1) + one__30_q; + end else begin + op__31 = op__30_q; + res__31 = (res__30_q>>1); + end + one__31 = (one__30_q >> 2); + + //i = 31 + if (op__31 >= res__31 + one__31) begin + op__32 = op__31 - res__31 - one__31; + res__32 = (res__31>>1) + one__31; + end else begin + op__32 = op__31; + res__32 = (res__31>>1); + end + one__32 = (one__31 >> 2); + end + + + //If-statement about assigning res: + always @* begin + if(one__0 == 0) begin + res = res__0[31:0]; + end else if (one__1 == 0) begin + res = res__1[31:0]; + end else if (one__2 == 0) begin + res = res__2[31:0]; + end else if (one__3_q == 0) begin + res = res__3_q[31:0]; + end else if (one__4 == 0) begin + res = res__4[31:0]; + end else if (one__5 == 0) begin + res = res__5[31:0]; + end else if (one__6 == 0) begin + res = res__6[31:0]; + end else if (one__7_q == 0) begin + res = res__7_q[31:0]; + end else if (one__8 == 0) begin + res = res__8[31:0]; + end else if (one__9 == 0) begin + res = res__9[31:0]; + end else if (one__10 == 0) begin + res = res__10[31:0]; + end else if (one__11_q == 0) begin + res = res__11_q[31:0]; + end else if (one__12 == 0) begin + res = res__12[31:0]; + end else if (one__13 == 0) begin + res = res__13[31:0]; + end else if (one__14 == 0) begin + res = res__14[31:0]; + end else if (one__15_q == 0) begin + res = res__15_q[31:0]; + end else if (one__16 == 0) begin + res = res__16[31:0]; + end else if (one__17 == 0) begin + res = res__17[31:0]; + end else if (one__18_q == 0) begin + res = res__18_q[31:0]; + end else if (one__19 == 0) begin + res = res__19[31:0]; + end else if (one__20 == 0) begin + res = res__20[31:0]; + end else if (one__21_q == 0) begin + res = res__21_q[31:0]; + end else if (one__22 == 0) begin + res = res__22[31:0]; + end else if (one__23 == 0) begin + res = res__23[31:0]; + end else if (one__24_q == 0) begin + res = res__24_q[31:0]; + end else if (one__25 == 0) begin + res = res__25[31:0]; + end else if (one__26 == 0) begin + res = res__26[31:0]; + end else if (one__27_q == 0) begin + res = res__27_q[31:0]; + end else if (one__28 == 0) begin + res = res__28[31:0]; + end else if (one__29 == 0) begin + res = res__29[31:0]; + end else if (one__30_q == 0) begin + res = res__30_q[31:0]; + end else if (one__31 == 0) begin + res = res__31[31:0]; + end else begin + res = res__32[31:0]; + end + + end + + +endmodule + + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v b/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v new file mode 100755 index 000000000..d20b58708 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v @@ -0,0 +1,6582 @@ +`define n 32 +`define max_size 30 + + +// +// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24) +// +// On Tue Jun 8 18:43:40 EDT 2010 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 256 reg +// wsiM1_MByteEn O 32 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wmemiM_MCmd O 3 reg +// wmemiM_MReqLast O 1 reg +// wmemiM_MAddr O 36 reg +// wmemiM_MBurstLength O 12 reg +// wmemiM_MDataValid O 1 reg +// wmemiM_MDataLast O 1 reg +// wmemiM_MData O 128 reg +// wmemiM_MDataByteEn O 16 reg +// wmemiM_MReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 20 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 256 +// wsiS1_MByteEn I 32 +// wsiS1_MReqInfo I 8 +// wmemiM_SResp I 2 +// wmemiM_SData I 128 +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// wmemiM_SRespLast I 1 +// wmemiM_SCmdAccept I 1 +// wmemiM_SDataAccept I 1 +// +// No combinational paths from inputs to outputs +// +// + + + +module mkDelayWorker32B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n, + + wmemiM_MCmd, + + wmemiM_MReqLast, + + wmemiM_MAddr, + + wmemiM_MBurstLength, + + wmemiM_MDataValid, + + wmemiM_MDataLast, + + wmemiM_MData, + + wmemiM_MDataByteEn, + + wmemiM_SResp, + + wmemiM_SRespLast, + + wmemiM_SData, + + wmemiM_SCmdAccept, + + wmemiM_SDataAccept, + + wmemiM_MReset_n, + + prevent_hanging_nodes); + parameter [31 : 0] dlyCtrlInit = 32'b00000000000000000000000000000000; + input wciS0_Clk; + input wciS0_MReset_n; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [19 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [255 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [31 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [255 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [31 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // value method wmemiM_mCmd + output [2 : 0] wmemiM_MCmd; + + // value method wmemiM_mReqLast + output wmemiM_MReqLast; + + // value method wmemiM_mAddr + output [35 : 0] wmemiM_MAddr; + + // value method wmemiM_mBurstLength + output [11 : 0] wmemiM_MBurstLength; + + // value method wmemiM_mDataValid + output wmemiM_MDataValid; + + // value method wmemiM_mDataLast + output wmemiM_MDataLast; + + // value method wmemiM_mData + output [127 : 0] wmemiM_MData; + + // value method wmemiM_mDataByteEn + output [15 : 0] wmemiM_MDataByteEn; + + // action method wmemiM_sResp + input [1 : 0] wmemiM_SResp; + + // action method wmemiM_sRespLast + input wmemiM_SRespLast; + + // action method wmemiM_sData + input [127 : 0] wmemiM_SData; + + // action method wmemiM_sCmdAccept + input wmemiM_SCmdAccept; + + // action method wmemiM_sDataAccept + input wmemiM_SDataAccept; + + // value method wmemiM_mReset_n + output wmemiM_MReset_n; + + output prevent_hanging_nodes; + + // Hanging node logic + + + + wire dummy1; + wire dummy2; + wire dummy3; + wire dummy4; + wire dummy5; + wire dummy6; + wire dummy7; + wire dummy8; + wire dummy9; + assign dummy1 = &mesgRF_memory__DOB; + assign dummy2 = &mesgWF_memory__DOB; + assign dummy3 = &metaRF__D_OUT; + assign dummy4 = &metaWF__D_OUT ; + assign dummy5 = &wci_reqF__D_OUT; + assign dummy6 = &wide16Fa__D_OUT; + assign dummy7 = &wide16Fb__D_OUT; + assign dummy8 = &wmemi_respF__D_OUT; + assign dummy9 = &wsiS_reqFifo__D_OUT; + + wire prevent_hang_wire; + assign prevent_hang_wire = dummy1 & dummy2 & dummy3 & dummy4 &dummy5 & dummy6 & dummy7 & dummy8 & dummy9; + assign prevent_hanging_nodes = prevent_hang_wire; + + // signals for module outputs + wire [255 : 0] wsiM1_MData; + wire [127 : 0] wmemiM_MData; + wire [35 : 0] wmemiM_MAddr; + wire [31 : 0] wciS0_SData, wsiM1_MByteEn; + wire [15 : 0] wmemiM_MDataByteEn; + wire [11 : 0] wmemiM_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM1_MReqInfo; + wire [2 : 0] wmemiM_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wmemiM_MDataLast, + wmemiM_MDataValid, + wmemiM_MReqLast, + wmemiM_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [312 : 0] wsiM_reqFifo_x_wire__wget, wsiS_wsiReq__wget; + wire [255 : 0] mesgRF_wDataIn__wget, + mesgRF_wDataOut__wget, + mesgWF_wDataIn__wget, + mesgWF_wDataOut__wget, + wsi_Es_mData_w__wget; + wire [145 : 0] wmemi_dhF_x_wire__wget; + wire [130 : 0] wmemi_wmemiResponse__wget; + wire [127 : 0] wmemi_Em_sData_w__wget; + wire [95 : 0] wsiM_extStatusW__wget, wsiS_extStatusW__wget; + wire [59 : 0] wci_wciReq__wget; + wire [51 : 0] wmemi_reqF_x_wire__wget; + wire [33 : 0] wci_respF_x_wire__wget; + wire [31 : 0] wci_Es_mData_w__wget, wsi_Es_mByteEn_w__wget; + wire [19 : 0] dlyWordsStored_acc_v1__wget, + dlyWordsStored_acc_v2__wget, + wci_Es_mAddr_w__wget; + wire [11 : 0] wsi_Es_mBurstLength_w__wget; + wire [7 : 0] dlyReadCredit_acc_v1__wget, + dlyReadCredit_acc_v2__wget, + wsi_Es_mReqInfo_w__wget; + wire [3 : 0] wci_Es_mByteEn_w__wget; + wire [2 : 0] wci_Es_mCmd_w__wget, wci_wEdge__wget, wsi_Es_mCmd_w__wget; + wire [1 : 0] wmemi_Em_sResp_w__wget; + wire dlyReadCredit_acc_v1__whas, + dlyReadCredit_acc_v2__whas, + dlyWordsStored_acc_v1__whas, + dlyWordsStored_acc_v2__whas, + mesgRF_pwDequeue__whas, + mesgRF_pwEnqueue__whas, + mesgRF_wDataIn__whas, + mesgRF_wDataOut__whas, + mesgWF_pwDequeue__whas, + mesgWF_pwEnqueue__whas, + mesgWF_wDataIn__whas, + mesgWF_wDataOut__whas, + wci_Es_mAddrSpace_w__wget, + wci_Es_mAddrSpace_w__whas, + wci_Es_mAddr_w__whas, + wci_Es_mByteEn_w__whas, + wci_Es_mCmd_w__whas, + wci_Es_mData_w__whas, + wci_ctlAckReg_1__wget, + wci_ctlAckReg_1__whas, + wci_reqF_r_clr__whas, + wci_reqF_r_deq__whas, + wci_reqF_r_enq__whas, + wci_respF_dequeueing__whas, + wci_respF_enqueueing__whas, + wci_respF_x_wire__whas, + wci_sFlagReg_1__wget, + wci_sFlagReg_1__whas, + wci_sThreadBusy_pw__whas, + wci_wEdge__whas, + wci_wciReq__whas, + wci_wci_cfrd_pw__whas, + wci_wci_cfwr_pw__whas, + wci_wci_ctrl_pw__whas, + wmemi_Em_sData_w__whas, + wmemi_Em_sRespLast_w__whas, + wmemi_Em_sResp_w__whas, + wmemi_dhF_dequeueing__whas, + wmemi_dhF_enqueueing__whas, + wmemi_dhF_x_wire__whas, + wmemi_operateD_1__wget, + wmemi_operateD_1__whas, + wmemi_peerIsReady_1__wget, + wmemi_peerIsReady_1__whas, + wmemi_reqF_dequeueing__whas, + wmemi_reqF_enqueueing__whas, + wmemi_reqF_x_wire__whas, + wmemi_sCmdAccept_w__wget, + wmemi_sCmdAccept_w__whas, + wmemi_sDataAccept_w__wget, + wmemi_sDataAccept_w__whas, + wmemi_wmemiResponse__whas, + wsiM_operateD_1__wget, + wsiM_operateD_1__whas, + wsiM_peerIsReady_1__wget, + wsiM_peerIsReady_1__whas, + wsiM_reqFifo_dequeueing__whas, + wsiM_reqFifo_enqueueing__whas, + wsiM_reqFifo_x_wire__whas, + wsiM_sThreadBusy_pw__whas, + wsiS_operateD_1__wget, + wsiS_operateD_1__whas, + wsiS_peerIsReady_1__wget, + wsiS_peerIsReady_1__whas, + wsiS_reqFifo_r_clr__whas, + wsiS_reqFifo_r_deq__whas, + wsiS_reqFifo_r_enq__whas, + wsiS_wsiReq__whas, + wsi_Es_mBurstLength_w__whas, + wsi_Es_mBurstPrecise_w__whas, + wsi_Es_mByteEn_w__whas, + wsi_Es_mCmd_w__whas, + wsi_Es_mDataInfo_w__whas, + wsi_Es_mData_w__whas, + wsi_Es_mReqInfo_w__whas, + wsi_Es_mReqLast_w__whas; + + // register abortCount + reg [31 : 0] abortCount; + wire [31 : 0] abortCount__D_IN; + wire abortCount__EN; + + // register blockDelayWrite + reg blockDelayWrite; + wire blockDelayWrite__D_IN, blockDelayWrite__EN; + + // register bytesRead + reg [31 : 0] bytesRead; + wire [31 : 0] bytesRead__D_IN; + wire bytesRead__EN; + + // register bytesWritten + reg [31 : 0] bytesWritten; + wire [31 : 0] bytesWritten__D_IN; + wire bytesWritten__EN; + + // register cyclesPassed + reg [31 : 0] cyclesPassed; + wire [31 : 0] cyclesPassed__D_IN; + wire cyclesPassed__EN; + + // register dlyCtrl + reg [31 : 0] dlyCtrl; + wire [31 : 0] dlyCtrl__D_IN; + wire dlyCtrl__EN; + + // register dlyHoldoffBytes + reg [31 : 0] dlyHoldoffBytes; + wire [31 : 0] dlyHoldoffBytes__D_IN; + wire dlyHoldoffBytes__EN; + + // register dlyHoldoffCycles + reg [31 : 0] dlyHoldoffCycles; + wire [31 : 0] dlyHoldoffCycles__D_IN; + wire dlyHoldoffCycles__EN; + + // register dlyRAG + reg [19 : 0] dlyRAG; + wire [19 : 0] dlyRAG__D_IN; + wire dlyRAG__EN; + + // register dlyReadCredit_value + reg [7 : 0] dlyReadCredit_value; + wire [7 : 0] dlyReadCredit_value__D_IN; + wire dlyReadCredit_value__EN; + + // register dlyWAG + reg [19 : 0] dlyWAG; + wire [19 : 0] dlyWAG__D_IN; + wire dlyWAG__EN; + + // register dlyWordsStored_value + reg [19 : 0] dlyWordsStored_value; + wire [19 : 0] dlyWordsStored_value__D_IN; + wire dlyWordsStored_value__EN; + + // register doAbort + reg doAbort; + wire doAbort__D_IN, doAbort__EN; + + // register endOfMessage + reg endOfMessage; + wire endOfMessage__D_IN, endOfMessage__EN; + + // register errCount // jluu removed because never used +// reg [255 : 0] errCount; +// wire [255 : 0] errCount__D_IN; +// wire errCount__EN; + + // register impreciseBurst + reg impreciseBurst; + reg impreciseBurst__D_IN; + wire impreciseBurst__EN; + + // register mesgLength + reg [14 : 0] mesgLength; + reg [14 : 0] mesgLength__D_IN; + wire mesgLength__EN; + + // register mesgLengthSoFar + reg [13 : 0] mesgLengthSoFar; + wire [13 : 0] mesgLengthSoFar__D_IN; + wire mesgLengthSoFar__EN; + + // register mesgRF_rCache + reg [267 : 0] mesgRF_rCache; + wire [267 : 0] mesgRF_rCache__D_IN; + wire mesgRF_rCache__EN; + + // register mesgRF_rRdPtr + reg [10 : 0] mesgRF_rRdPtr; + wire [10 : 0] mesgRF_rRdPtr__D_IN; + wire mesgRF_rRdPtr__EN; + + // register mesgRF_rWrPtr + reg [10 : 0] mesgRF_rWrPtr; + wire [10 : 0] mesgRF_rWrPtr__D_IN; + wire mesgRF_rWrPtr__EN; + + // register mesgRdCount + reg [31 : 0] mesgRdCount; + wire [31 : 0] mesgRdCount__D_IN; + wire mesgRdCount__EN; + + // register mesgReqValid + reg mesgReqValid; + wire mesgReqValid__D_IN, mesgReqValid__EN; + + // register mesgWF_rCache + reg [267 : 0] mesgWF_rCache; + wire [267 : 0] mesgWF_rCache__D_IN; + wire mesgWF_rCache__EN; + + // register mesgWF_rRdPtr + reg [10 : 0] mesgWF_rRdPtr; + wire [10 : 0] mesgWF_rRdPtr__D_IN; + wire mesgWF_rRdPtr__EN; + + // register mesgWF_rWrPtr + reg [10 : 0] mesgWF_rWrPtr; + wire [10 : 0] mesgWF_rWrPtr__D_IN; + wire mesgWF_rWrPtr__EN; + + // register mesgWtCount + reg [31 : 0] mesgWtCount; + wire [31 : 0] mesgWtCount__D_IN; + wire mesgWtCount__EN; + + // register opcode + reg [8 : 0] opcode; + reg [8 : 0] opcode__D_IN; + wire opcode__EN; + + // register preciseBurst + reg preciseBurst; + reg preciseBurst__D_IN; + wire preciseBurst__EN; + + // register rdSerAddr + reg [31 : 0] rdSerAddr; + wire [31 : 0] rdSerAddr__D_IN; + wire rdSerAddr__EN; + + // register rdSerEmpty + reg rdSerEmpty; + wire rdSerEmpty__D_IN, rdSerEmpty__EN; + + // register rdSerMeta + reg [31 : 0] rdSerMeta; + wire [31 : 0] rdSerMeta__D_IN; + wire rdSerMeta__EN; + + // register rdSerPos + reg [1 : 0] rdSerPos; + wire [1 : 0] rdSerPos__D_IN; + wire rdSerPos__EN; + + // register rdSerStage + reg [31 : 0] rdSerStage; + wire [31 : 0] rdSerStage__D_IN; + wire rdSerStage__EN; + + // register rdSerStage_1 + reg [31 : 0] rdSerStage_1; + wire [31 : 0] rdSerStage_1__D_IN; + wire rdSerStage_1__EN; + + // register rdSerStage_2 + reg [31 : 0] rdSerStage_2; + wire [31 : 0] rdSerStage_2__D_IN; + wire rdSerStage_2__EN; + + // register rdSerStage_3 + reg [31 : 0] rdSerStage_3; + wire [31 : 0] rdSerStage_3__D_IN; + wire rdSerStage_3__EN; + + // register rdSerUnroll + reg [15 : 0] rdSerUnroll; + wire [15 : 0] rdSerUnroll__D_IN; + wire rdSerUnroll__EN; + + // register rdSyncWord + reg rdSyncWord; + reg rdSyncWord__D_IN; + wire rdSyncWord__EN; + + // register readMeta + reg [31 : 0] readMeta; + wire [31 : 0] readMeta__D_IN; + wire readMeta__EN; + + // register readyToPush + reg readyToPush; + reg readyToPush__D_IN; + wire readyToPush__EN; + + // register readyToRequest + reg readyToRequest; + wire readyToRequest__D_IN, readyToRequest__EN; + + // register unrollCnt + reg [15 : 0] unrollCnt; + wire [15 : 0] unrollCnt__D_IN; + wire unrollCnt__EN; + + // register valExpect +// reg [255 : 0] valExpect; +// wire [255 : 0] valExpect__D_IN; +// wire valExpect__EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge__D_IN; + wire wci_cEdge__EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState__D_IN; + wire wci_cState__EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg__D_IN, wci_ctlAckReg__EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive__D_IN, wci_ctlOpActive__EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge__D_IN, wci_illegalEdge__EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState__D_IN; + wire wci_nState__EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg__D_IN; + wire wci_reqF_countReg__EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r__D_IN; + wire wci_respF_c_r__EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0__D_IN; + wire wci_respF_q_0__EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1__D_IN; + wire wci_respF_q_1__EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg__D_IN, wci_sFlagReg__EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d__D_IN, wci_sThreadBusy_d__EN; + + // register wmemiRdReq + reg [31 : 0] wmemiRdReq; + wire [31 : 0] wmemiRdReq__D_IN; + wire wmemiRdReq__EN; + + // register wmemiRdResp + reg [31 : 0] wmemiRdResp; + wire [31 : 0] wmemiRdResp__D_IN; + wire wmemiRdResp__EN; + + // register wmemiWrReq + reg [31 : 0] wmemiWrReq; + wire [31 : 0] wmemiWrReq__D_IN; + wire wmemiWrReq__EN; + + // register wmemi_busyWithMessage + reg wmemi_busyWithMessage; + wire wmemi_busyWithMessage__D_IN, wmemi_busyWithMessage__EN; + + // register wmemi_dhF_c_r + reg [1 : 0] wmemi_dhF_c_r; + wire [1 : 0] wmemi_dhF_c_r__D_IN; + wire wmemi_dhF_c_r__EN; + + // register wmemi_dhF_q_0 + reg [145 : 0] wmemi_dhF_q_0; + reg [145 : 0] wmemi_dhF_q_0__D_IN; + wire wmemi_dhF_q_0__EN; + + // register wmemi_dhF_q_1 + reg [145 : 0] wmemi_dhF_q_1; + reg [145 : 0] wmemi_dhF_q_1__D_IN; + wire wmemi_dhF_q_1__EN; + + // register wmemi_errorSticky + reg wmemi_errorSticky; + wire wmemi_errorSticky__D_IN, wmemi_errorSticky__EN; + + // register wmemi_operateD + reg wmemi_operateD; + wire wmemi_operateD__D_IN, wmemi_operateD__EN; + + // register wmemi_peerIsReady + reg wmemi_peerIsReady; + wire wmemi_peerIsReady__D_IN, wmemi_peerIsReady__EN; + + // register wmemi_reqF_c_r + reg [1 : 0] wmemi_reqF_c_r; + wire [1 : 0] wmemi_reqF_c_r__D_IN; + wire wmemi_reqF_c_r__EN; + + // register wmemi_reqF_q_0 + reg [51 : 0] wmemi_reqF_q_0; + reg [51 : 0] wmemi_reqF_q_0__D_IN; + wire wmemi_reqF_q_0__EN; + + // register wmemi_reqF_q_1 + reg [51 : 0] wmemi_reqF_q_1; + reg [51 : 0] wmemi_reqF_q_1__D_IN; + wire wmemi_reqF_q_1__EN; + + // register wmemi_statusR + reg [7 : 0] wmemi_statusR; + wire [7 : 0] wmemi_statusR__D_IN; + wire wmemi_statusR__EN; + + // register wmemi_trafficSticky + reg wmemi_trafficSticky; + wire wmemi_trafficSticky__D_IN, wmemi_trafficSticky__EN; + + // register wrtDutyCount + reg [2 : 0] wrtDutyCount; + wire [2 : 0] wrtDutyCount__D_IN; + wire wrtDutyCount__EN; + + // register wrtSerAddr + reg [31 : 0] wrtSerAddr; + wire [31 : 0] wrtSerAddr__D_IN; + wire wrtSerAddr__EN; + + // register wrtSerMeta + reg [31 : 0] wrtSerMeta; + wire [31 : 0] wrtSerMeta__D_IN; + wire wrtSerMeta__EN; + + // register wrtSerPos + reg [1 : 0] wrtSerPos; + wire [1 : 0] wrtSerPos__D_IN; + wire wrtSerPos__EN; + + // register wrtSerStage + reg [31 : 0] wrtSerStage; + wire [31 : 0] wrtSerStage__D_IN; + wire wrtSerStage__EN; + + // register wrtSerStage_1 + reg [31 : 0] wrtSerStage_1; + wire [31 : 0] wrtSerStage_1__D_IN; + wire wrtSerStage_1__EN; + + // register wrtSerStage_2 + reg [31 : 0] wrtSerStage_2; + wire [31 : 0] wrtSerStage_2__D_IN; + wire wrtSerStage_2__EN; + + // register wrtSerStage_3 + reg [31 : 0] wrtSerStage_3; + wire [31 : 0] wrtSerStage_3__D_IN; + wire wrtSerStage_3__EN; + + // register wrtSerUnroll + reg [15 : 0] wrtSerUnroll; + wire [15 : 0] wrtSerUnroll__D_IN; + wire wrtSerUnroll__EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind__D_IN; + wire wsiM_burstKind__EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky__D_IN, wsiM_errorSticky__EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount__D_IN; + wire wsiM_iMesgCount__EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD__D_IN, wsiM_operateD__EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount__D_IN; + wire wsiM_pMesgCount__EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady__D_IN, wsiM_peerIsReady__EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r__D_IN; + wire wsiM_reqFifo_c_r__EN; + + // register wsiM_reqFifo_q_0 + reg [312 : 0] wsiM_reqFifo_q_0; + reg [312 : 0] wsiM_reqFifo_q_0__D_IN; + wire wsiM_reqFifo_q_0__EN; + + // register wsiM_reqFifo_q_1 + reg [312 : 0] wsiM_reqFifo_q_1; + reg [312 : 0] wsiM_reqFifo_q_1__D_IN; + wire wsiM_reqFifo_q_1__EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d__D_IN, wsiM_sThreadBusy_d__EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR__D_IN; + wire wsiM_statusR__EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount__D_IN; + wire wsiM_tBusyCount__EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky__D_IN, wsiM_trafficSticky__EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind__D_IN; + wire wsiS_burstKind__EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky__D_IN, wsiS_errorSticky__EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount__D_IN; + wire wsiS_iMesgCount__EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD__D_IN, wsiS_operateD__EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount__D_IN; + wire wsiS_pMesgCount__EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady__D_IN, wsiS_peerIsReady__EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg__D_IN; + wire wsiS_reqFifo_countReg__EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR__D_IN; + wire wsiS_statusR__EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount__D_IN; + wire wsiS_tBusyCount__EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky__D_IN, wsiS_trafficSticky__EN; + + // register wsiWordsRemain + reg [11 : 0] wsiWordsRemain; + wire [11 : 0] wsiWordsRemain__D_IN; + wire wsiWordsRemain__EN; + + // register zeroLengthMesg + reg zeroLengthMesg; + wire zeroLengthMesg__D_IN, zeroLengthMesg__EN; + + // ports of submodule mesgRF_memory + wire [255 : 0] mesgRF_memory__DIA, mesgRF_memory__DIB, mesgRF_memory__DOB; + wire [9 : 0] mesgRF_memory__ADDRA, mesgRF_memory__ADDRB; + wire mesgRF_memory__ENA, + mesgRF_memory__ENB, + mesgRF_memory__WEA, + mesgRF_memory__WEB; + + // ports of submodule mesgWF_memory + wire [255 : 0] mesgWF_memory__DIA, mesgWF_memory__DIB, mesgWF_memory__DOB; + wire [9 : 0] mesgWF_memory__ADDRA, mesgWF_memory__ADDRB; + wire mesgWF_memory__ENA, + mesgWF_memory__ENB, + mesgWF_memory__WEA, + mesgWF_memory__WEB; + + // ports of submodule metaRF + reg [31 : 0] metaRF__D_IN; + wire [31 : 0] metaRF__D_OUT; + wire metaRF__CLR, metaRF__DEQ, metaRF__EMPTY_N, metaRF__ENQ, metaRF__FULL_N; + + // ports of submodule metaWF + wire [31 : 0] metaWF__D_IN, metaWF__D_OUT; + wire metaWF__CLR, metaWF__DEQ, metaWF__EMPTY_N, metaWF__ENQ, metaWF__FULL_N; + + // ports of submodule wci_isReset + wire wci_isReset__VAL; + + // ports of submodule wci_reqF + wire [59 : 0] wci_reqF__D_IN, wci_reqF__D_OUT; + wire wci_reqF__CLR, wci_reqF__DEQ, wci_reqF__EMPTY_N, wci_reqF__ENQ; + + // ports of submodule wide16Fa + wire [127 : 0] wide16Fa__D_IN, wide16Fa__D_OUT; + wire wide16Fa__CLR, + wide16Fa__DEQ, + wide16Fa__EMPTY_N, + wide16Fa__ENQ, + wide16Fa__FULL_N; + + // ports of submodule wide16Fb + wire [127 : 0] wide16Fb__D_IN, wide16Fb__D_OUT; + wire wide16Fb__CLR, + wide16Fb__DEQ, + wide16Fb__EMPTY_N, + wide16Fb__ENQ, + wide16Fb__FULL_N; + + // ports of submodule wmemi_isReset + wire wmemi_isReset__VAL; + + // ports of submodule wmemi_respF + wire [130 : 0] wmemi_respF__D_IN, wmemi_respF__D_OUT; + wire wmemi_respF__CLR, + wmemi_respF__DEQ, + wmemi_respF__EMPTY_N, + wmemi_respF__ENQ, + wmemi_respF__FULL_N; + + // ports of submodule wsiM_isReset + wire wsiM_isReset__VAL; + + // ports of submodule wsiS_isReset + wire wsiS_isReset__VAL; + + // ports of submodule wsiS_reqFifo + wire [312 : 0] wsiS_reqFifo__D_IN, wsiS_reqFifo__D_OUT; + wire wsiS_reqFifo__CLR, + wsiS_reqFifo__DEQ, + wsiS_reqFifo__EMPTY_N, + wsiS_reqFifo__ENQ, + wsiS_reqFifo__FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_cycles_passed_count, + CAN_FIRE_RL_delay_read_req, + CAN_FIRE_RL_delay_read_resp, + CAN_FIRE_RL_delay_write_req, + CAN_FIRE_RL_delay_write_unblock, + CAN_FIRE_RL_dlyReadCredit_accumulate, + CAN_FIRE_RL_dlyWordsStored_accumulate, + CAN_FIRE_RL_mesgRF_portA, + CAN_FIRE_RL_mesgRF_portB, + CAN_FIRE_RL_mesgRF_portB_read_data, + CAN_FIRE_RL_mesgWF_portA, + CAN_FIRE_RL_mesgWF_portB, + CAN_FIRE_RL_mesgWF_portB_read_data, + CAN_FIRE_RL_operating_actions, + CAN_FIRE_RL_rdSer_begin, + CAN_FIRE_RL_rdSer_body, + CAN_FIRE_RL_rdSer_sync, + CAN_FIRE_RL_wci_Es_doAlways_Req, + CAN_FIRE_RL_wci_cfrd, + CAN_FIRE_RL_wci_cfwr, + CAN_FIRE_RL_wci_ctlAckReg__dreg_update, + CAN_FIRE_RL_wci_ctl_op_complete, + CAN_FIRE_RL_wci_ctl_op_start, + CAN_FIRE_RL_wci_ctrl_EiI, + CAN_FIRE_RL_wci_ctrl_IsO, + CAN_FIRE_RL_wci_ctrl_OrE, + CAN_FIRE_RL_wci_reqF__updateLevelCounter, + CAN_FIRE_RL_wci_reqF_enq, + CAN_FIRE_RL_wci_request_decode, + CAN_FIRE_RL_wci_respF_both, + CAN_FIRE_RL_wci_respF_decCtr, + CAN_FIRE_RL_wci_respF_deq, + CAN_FIRE_RL_wci_respF_incCtr, + CAN_FIRE_RL_wci_sFlagReg__dreg_update, + CAN_FIRE_RL_wci_sThreadBusy_reg, + CAN_FIRE_RL_wmemi_Em_doAlways, + CAN_FIRE_RL_wmemi_dhF_both, + CAN_FIRE_RL_wmemi_dhF_decCtr, + CAN_FIRE_RL_wmemi_dhF_deq, + CAN_FIRE_RL_wmemi_dhF_incCtr, + CAN_FIRE_RL_wmemi_operateD__dreg_update, + CAN_FIRE_RL_wmemi_peerIsReady__dreg_update, + CAN_FIRE_RL_wmemi_reqF_both, + CAN_FIRE_RL_wmemi_reqF_decCtr, + CAN_FIRE_RL_wmemi_reqF_deq, + CAN_FIRE_RL_wmemi_reqF_incCtr, + CAN_FIRE_RL_wmemi_respAdvance, + CAN_FIRE_RL_wmemi_update_statusR, + CAN_FIRE_RL_wmrd_mesgBegin, + CAN_FIRE_RL_wmrd_mesgBodyResponse, + CAN_FIRE_RL_wmwt_doAbort, + CAN_FIRE_RL_wmwt_mesgBegin, + CAN_FIRE_RL_wmwt_messageFinalize, + CAN_FIRE_RL_wmwt_messagePushImprecise, + CAN_FIRE_RL_wmwt_messagePushPrecise, + CAN_FIRE_RL_wmwt_requestPrecise, + CAN_FIRE_RL_wrtSer_begin, + CAN_FIRE_RL_wrtSer_body, + CAN_FIRE_RL_wsiM_ext_status_assign, + CAN_FIRE_RL_wsiM_inc_tBusyCount, + CAN_FIRE_RL_wsiM_operateD__dreg_update, + CAN_FIRE_RL_wsiM_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiM_reqFifo_both, + CAN_FIRE_RL_wsiM_reqFifo_decCtr, + CAN_FIRE_RL_wsiM_reqFifo_deq, + CAN_FIRE_RL_wsiM_reqFifo_incCtr, + CAN_FIRE_RL_wsiM_sThreadBusy_reg, + CAN_FIRE_RL_wsiM_update_statusR, + CAN_FIRE_RL_wsiS_ext_status_assign, + CAN_FIRE_RL_wsiS_inc_tBusyCount, + CAN_FIRE_RL_wsiS_operateD__dreg_update, + CAN_FIRE_RL_wsiS_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + CAN_FIRE_RL_wsiS_reqFifo_enq, + CAN_FIRE_RL_wsiS_update_statusR, + CAN_FIRE_RL_wsi_Es_doAlways, + CAN_FIRE_RL_wsipass_doMessagePush, + CAN_FIRE_wciS0_mAddr, + CAN_FIRE_wciS0_mAddrSpace, + CAN_FIRE_wciS0_mByteEn, + CAN_FIRE_wciS0_mCmd, + CAN_FIRE_wciS0_mData, + CAN_FIRE_wciS0_mFlag, + CAN_FIRE_wmemiM_sCmdAccept, + CAN_FIRE_wmemiM_sData, + CAN_FIRE_wmemiM_sDataAccept, + CAN_FIRE_wmemiM_sResp, + CAN_FIRE_wmemiM_sRespLast, + CAN_FIRE_wsiM1_sReset_n, + CAN_FIRE_wsiM1_sThreadBusy, + CAN_FIRE_wsiS1_mBurstLength, + CAN_FIRE_wsiS1_mBurstPrecise, + CAN_FIRE_wsiS1_mByteEn, + CAN_FIRE_wsiS1_mCmd, + CAN_FIRE_wsiS1_mData, + CAN_FIRE_wsiS1_mDataInfo, + CAN_FIRE_wsiS1_mReqInfo, + CAN_FIRE_wsiS1_mReqLast, + CAN_FIRE_wsiS1_mReset_n, + WILL_FIRE_RL_cycles_passed_count, + WILL_FIRE_RL_delay_read_req, + WILL_FIRE_RL_delay_read_resp, + WILL_FIRE_RL_delay_write_req, + WILL_FIRE_RL_delay_write_unblock, + WILL_FIRE_RL_dlyReadCredit_accumulate, + WILL_FIRE_RL_dlyWordsStored_accumulate, + WILL_FIRE_RL_mesgRF_portA, + WILL_FIRE_RL_mesgRF_portB, + WILL_FIRE_RL_mesgRF_portB_read_data, + WILL_FIRE_RL_mesgWF_portA, + WILL_FIRE_RL_mesgWF_portB, + WILL_FIRE_RL_mesgWF_portB_read_data, + WILL_FIRE_RL_operating_actions, + WILL_FIRE_RL_rdSer_begin, + WILL_FIRE_RL_rdSer_body, + WILL_FIRE_RL_rdSer_sync, + WILL_FIRE_RL_wci_Es_doAlways_Req, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctlAckReg__dreg_update, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_reqF__updateLevelCounter, + WILL_FIRE_RL_wci_reqF_enq, + WILL_FIRE_RL_wci_request_decode, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_deq, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wci_sFlagReg__dreg_update, + WILL_FIRE_RL_wci_sThreadBusy_reg, + WILL_FIRE_RL_wmemi_Em_doAlways, + WILL_FIRE_RL_wmemi_dhF_both, + WILL_FIRE_RL_wmemi_dhF_decCtr, + WILL_FIRE_RL_wmemi_dhF_deq, + WILL_FIRE_RL_wmemi_dhF_incCtr, + WILL_FIRE_RL_wmemi_operateD__dreg_update, + WILL_FIRE_RL_wmemi_peerIsReady__dreg_update, + WILL_FIRE_RL_wmemi_reqF_both, + WILL_FIRE_RL_wmemi_reqF_decCtr, + WILL_FIRE_RL_wmemi_reqF_deq, + WILL_FIRE_RL_wmemi_reqF_incCtr, + WILL_FIRE_RL_wmemi_respAdvance, + WILL_FIRE_RL_wmemi_update_statusR, + WILL_FIRE_RL_wmrd_mesgBegin, + WILL_FIRE_RL_wmrd_mesgBodyResponse, + WILL_FIRE_RL_wmwt_doAbort, + WILL_FIRE_RL_wmwt_mesgBegin, + WILL_FIRE_RL_wmwt_messageFinalize, + WILL_FIRE_RL_wmwt_messagePushImprecise, + WILL_FIRE_RL_wmwt_messagePushPrecise, + WILL_FIRE_RL_wmwt_requestPrecise, + WILL_FIRE_RL_wrtSer_begin, + WILL_FIRE_RL_wrtSer_body, + WILL_FIRE_RL_wsiM_ext_status_assign, + WILL_FIRE_RL_wsiM_inc_tBusyCount, + WILL_FIRE_RL_wsiM_operateD__dreg_update, + WILL_FIRE_RL_wsiM_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiM_sThreadBusy_reg, + WILL_FIRE_RL_wsiM_update_statusR, + WILL_FIRE_RL_wsiS_ext_status_assign, + WILL_FIRE_RL_wsiS_inc_tBusyCount, + WILL_FIRE_RL_wsiS_operateD__dreg_update, + WILL_FIRE_RL_wsiS_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_update_statusR, + WILL_FIRE_RL_wsi_Es_doAlways, + WILL_FIRE_RL_wsipass_doMessagePush, + WILL_FIRE_wciS0_mAddr, + WILL_FIRE_wciS0_mAddrSpace, + WILL_FIRE_wciS0_mByteEn, + WILL_FIRE_wciS0_mCmd, + WILL_FIRE_wciS0_mData, + WILL_FIRE_wciS0_mFlag, + WILL_FIRE_wmemiM_sCmdAccept, + WILL_FIRE_wmemiM_sData, + WILL_FIRE_wmemiM_sDataAccept, + WILL_FIRE_wmemiM_sResp, + WILL_FIRE_wmemiM_sRespLast, + WILL_FIRE_wsiM1_sReset_n, + WILL_FIRE_wsiM1_sThreadBusy, + WILL_FIRE_wsiS1_mBurstLength, + WILL_FIRE_wsiS1_mBurstPrecise, + WILL_FIRE_wsiS1_mByteEn, + WILL_FIRE_wsiS1_mCmd, + WILL_FIRE_wsiS1_mData, + WILL_FIRE_wsiS1_mDataInfo, + WILL_FIRE_wsiS1_mReqInfo, + WILL_FIRE_wsiS1_mReqLast, + WILL_FIRE_wsiS1_mReset_n; + + // inputs to muxes for submodule ports + reg [127 : 0] MUX_wide16Fa__enq_1__VAL_1, MUX_wide16Fa__enq_1__VAL_2; + reg [33 : 0] MUX_wci_respF_q_0__write_1__VAL_2; + wire [312 : 0] MUX_wsiM_reqFifo_q_0__write_1__VAL_1, + MUX_wsiM_reqFifo_q_0__write_1__VAL_2, + MUX_wsiM_reqFifo_q_1__write_1__VAL_1, + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1; + wire [145 : 0] MUX_wmemi_dhF_q_0__write_1__VAL_1, + MUX_wmemi_dhF_q_0__write_1__VAL_2, + MUX_wmemi_dhF_q_1__write_1__VAL_1; + wire [51 : 0] MUX_wmemi_reqF_q_0__write_1__VAL_1, + MUX_wmemi_reqF_q_0__write_1__VAL_2, + MUX_wmemi_reqF_q_1__write_1__VAL_1, + MUX_wmemi_reqF_x_wire__wset_1__VAL_1, + MUX_wmemi_reqF_x_wire__wset_1__VAL_2; + wire [33 : 0] MUX_wci_respF_q_0__write_1__VAL_1, + MUX_wci_respF_q_1__write_1__VAL_1, + MUX_wci_respF_x_wire__wset_1__VAL_1, + MUX_wci_respF_x_wire__wset_1__VAL_2; + wire [31 : 0] MUX_mesgRdCount__write_1__VAL_1, + MUX_mesgWtCount__write_1__VAL_1, + MUX_metaWF__enq_1__VAL_1; + wire [19 : 0] MUX_dlyRAG__write_1__VAL_1, + MUX_dlyWAG__write_1__VAL_1, + MUX_dlyWordsStored_value__write_1__VAL_2; + wire [15 : 0] MUX_rdSerUnroll__write_1__VAL_2, + MUX_unrollCnt__write_1__VAL_1, + MUX_unrollCnt__write_1__VAL_2, + MUX_wrtSerUnroll__write_1__VAL_1; + wire [14 : 0] MUX_mesgLength__write_1__VAL_2, MUX_mesgLength__write_1__VAL_3; + wire [13 : 0] MUX_mesgLengthSoFar__write_1__VAL_2; + wire [11 : 0] MUX_wsiWordsRemain__write_1__VAL_2; + wire [8 : 0] MUX_opcode__write_1__VAL_2; + wire [7 : 0] MUX_dlyReadCredit_value__write_1__VAL_2; + wire [1 : 0] MUX_rdSerPos__write_1__VAL_1, + MUX_wci_respF_c_r__write_1__VAL_1, + MUX_wci_respF_c_r__write_1__VAL_2, + MUX_wmemi_dhF_c_r__write_1__VAL_1, + MUX_wmemi_dhF_c_r__write_1__VAL_2, + MUX_wmemi_reqF_c_r__write_1__VAL_1, + MUX_wmemi_reqF_c_r__write_1__VAL_2, + MUX_wrtSerPos__write_1__VAL_1, + MUX_wrtSerPos__write_1__VAL_2, + MUX_wsiM_reqFifo_c_r__write_1__VAL_1, + MUX_wsiM_reqFifo_c_r__write_1__VAL_2; + wire MUX_endOfMessage__write_1__SEL_1, + MUX_impreciseBurst__write_1__SEL_2, + MUX_mesgLength__write_1__SEL_2, + MUX_mesgRdCount__write_1__SEL_1, + MUX_metaWF__enq_1__SEL_1, + MUX_rdSerEmpty__write_1__PSEL_1, + MUX_rdSerEmpty__write_1__SEL_1, + MUX_rdSyncWord__write_1__VAL_1, + MUX_rdSyncWord__write_1__VAL_2, + MUX_wci_illegalEdge__write_1__SEL_1, + MUX_wci_illegalEdge__write_1__SEL_2, + MUX_wci_illegalEdge__write_1__VAL_2, + MUX_wci_respF_q_0__write_1__SEL_2, + MUX_wci_respF_q_1__write_1__SEL_2, + MUX_wide16Fa__enq_1__SEL_1, + MUX_wmemi_dhF_q_0__write_1__SEL_2, + MUX_wmemi_dhF_q_1__write_1__SEL_2, + MUX_wmemi_reqF_q_0__write_1__SEL_2, + MUX_wmemi_reqF_q_1__write_1__SEL_2, + MUX_wrtSerStage__write_1__SEL_1, + MUX_wrtSerStage_1__write_1__SEL_1, + MUX_wrtSerStage_2__write_1__SEL_1, + MUX_wrtSerStage_3__write_1__SEL_1, + MUX_wsiM_reqFifo_q_0__write_1__SEL_2, + MUX_wsiM_reqFifo_q_1__write_1__SEL_2; + + // remaining internal signals + reg [63 : 0] v__h17561, + v__h17806, + v__h19118, + v__h19195, + v__h21672, + v__h2670, + v__h2817, + v__h3716; + reg [31 : 0] x_data__h21804; + reg CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1, + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904; + wire [255 : 0] mesg__h22346, x__h15234, x__h16160, x__h19905; + wire [127 : 0] IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354, + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377, + x1__h19969, + x1__h19978, + x1__h20492, + x1__h20501; + wire [35 : 0] addr__h20994, addr__h21166; + wire [31 : 0] rdat__h21847, + rdat__h22030, + rdat__h22038, + rdat__h22046, + rdat__h22054, + v__h22720, + x_byteEn__h22438; + wire [23 : 0] x1_length__h17254, x__h21052, x__h21211, x__h21850; + wire [13 : 0] mlp1__h17953, x__h17298; + wire [11 : 0] x_burstLength__h22437; + wire [10 : 0] x__h15126, x__h16052; + wire [7 : 0] x1_opcode__h17253; + wire [1 : 0] wrtSerPos_11_PLUS_1___d1014; + wire NOT_dlyWordsStored_value_13_SLE_0_64_65_AND_NO_ETC___d272, + NOT_mesgRF_rRdPtr_52_PLUS_512_93_EQ_mesgRF_rWr_ETC___d208, + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698, + _dor1bytesWritten__EN_write, + metaRF_RDY_enq__41_AND_NOT_rdSerEmpty_96_97_AN_ETC___d242, + metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365, + wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397; + + // action method wciS0_mCmd + assign CAN_FIRE_wciS0_mCmd = 1'b1 ; + assign WILL_FIRE_wciS0_mCmd = 1'b1 ; + + // action method wciS0_mAddrSpace + assign CAN_FIRE_wciS0_mAddrSpace = 1'b1 ; + assign WILL_FIRE_wciS0_mAddrSpace = 1'b1 ; + + // action method wciS0_mByteEn + assign CAN_FIRE_wciS0_mByteEn = 1'b1 ; + assign WILL_FIRE_wciS0_mByteEn = 1'b1 ; + + // action method wciS0_mAddr + assign CAN_FIRE_wciS0_mAddr = 1'b1 ; + assign WILL_FIRE_wciS0_mAddr = 1'b1 ; + + // action method wciS0_mData + assign CAN_FIRE_wciS0_mData = 1'b1 ; + assign WILL_FIRE_wciS0_mData = 1'b1 ; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = wci_reqF_countReg > 2'b01 || wci_isReset__VAL ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'b1, wci_sFlagReg } ; + + // action method wciS0_mFlag + assign CAN_FIRE_wciS0_mFlag = 1'b1 ; + assign WILL_FIRE_wciS0_mFlag = 1'b1 ; + + // action method wsiS1_mCmd + assign CAN_FIRE_wsiS1_mCmd = 1'b1 ; + assign WILL_FIRE_wsiS1_mCmd = 1'b1 ; + + // action method wsiS1_mReqLast + assign CAN_FIRE_wsiS1_mReqLast = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ; + + // action method wsiS1_mBurstPrecise + assign CAN_FIRE_wsiS1_mBurstPrecise = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ; + + // action method wsiS1_mBurstLength + assign CAN_FIRE_wsiS1_mBurstLength = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstLength = 1'b1 ; + + // action method wsiS1_mData + assign CAN_FIRE_wsiS1_mData = 1'b1 ; + assign WILL_FIRE_wsiS1_mData = 1'b1 ; + + // action method wsiS1_mByteEn + assign CAN_FIRE_wsiS1_mByteEn = 1'b1 ; + assign WILL_FIRE_wsiS1_mByteEn = 1'b1 ; + + // action method wsiS1_mReqInfo + assign CAN_FIRE_wsiS1_mReqInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqInfo = 1'b1 ; + + // action method wsiS1_mDataInfo + assign CAN_FIRE_wsiS1_mDataInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mDataInfo = 1'b1 ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsiS_isReset__VAL && wsiS_operateD ; + + // action method wsiS1_mReset_n + assign CAN_FIRE_wsiS1_mReset_n = 1'b1 ; + assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = wsiM_sThreadBusy_d ? 3'b000 : wsiM_reqFifo_q_0[312:310] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[309] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[308] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsiM_sThreadBusy_d ? 12'b00 : wsiM_reqFifo_q_0[307:296] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsiM_reqFifo_q_0[295:40] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsiM_reqFifo_q_0[39:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = wsiM_sThreadBusy_d ? 8'b00000000 : wsiM_reqFifo_q_0[7:0] ; + + // action method wsiM1_sThreadBusy + assign CAN_FIRE_wsiM1_sThreadBusy = 1'b1 ; + assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsiM_isReset__VAL && wsiM_operateD ; + + // action method wsiM1_sReset_n + assign CAN_FIRE_wsiM1_sReset_n = 1'b1 ; + assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ; + + // value method wmemiM_mCmd + assign wmemiM_MCmd = wmemi_reqF_q_0[51:49] ; + + // value method wmemiM_mReqLast + assign wmemiM_MReqLast = wmemi_reqF_q_0[48] ; + + // value method wmemiM_mAddr + assign wmemiM_MAddr = wmemi_reqF_q_0[47:12] ; + + // value method wmemiM_mBurstLength + assign wmemiM_MBurstLength = wmemi_reqF_q_0[11:0] ; + + // value method wmemiM_mDataValid + assign wmemiM_MDataValid = wmemi_dhF_q_0[145] ; + + // value method wmemiM_mDataLast + assign wmemiM_MDataLast = wmemi_dhF_q_0[144] ; + + // value method wmemiM_mData + assign wmemiM_MData = wmemi_dhF_q_0[143:16] ; + + // value method wmemiM_mDataByteEn + assign wmemiM_MDataByteEn = wmemi_dhF_q_0[15:0] ; + + // action method wmemiM_sResp + assign CAN_FIRE_wmemiM_sResp = 1'b1 ; + assign WILL_FIRE_wmemiM_sResp = 1'b1 ; + + // action method wmemiM_sRespLast + assign CAN_FIRE_wmemiM_sRespLast = 1'b1 ; + assign WILL_FIRE_wmemiM_sRespLast = wmemiM_SRespLast ; + + // action method wmemiM_sData + assign CAN_FIRE_wmemiM_sData = 1'b1 ; + assign WILL_FIRE_wmemiM_sData = 1'b1 ; + + // action method wmemiM_sCmdAccept + assign CAN_FIRE_wmemiM_sCmdAccept = 1'b1 ; + assign WILL_FIRE_wmemiM_sCmdAccept = wmemiM_SCmdAccept ; + + // action method wmemiM_sDataAccept + assign CAN_FIRE_wmemiM_sDataAccept = 1'b1 ; + assign WILL_FIRE_wmemiM_sDataAccept = wmemiM_SDataAccept ; + + // value method wmemiM_mReset_n + assign wmemiM_MReset_n = !wmemi_isReset__VAL && wmemi_operateD ; + + // submodule mesgRF_memory + +// #(.PIPELINED(1'b0), +// .ADDR_WIDTH(32'b010), +// .DATA_WIDTH(32'b1056), +// .MEMSIZE(11'b1024)) mesgRF_memory + +wire [255:0] dp_out_not_used1; +wire [255:0] dp_out_not_used2; + + dual_port_ram dpram1 ( + .clk(wciS0_Clk), + .addr1(mesgRF_memory__ADDRA), + .addr2(mesgRF_memory__ADDRB), + .data1(mesgRF_memory__DIA), + .data2(mesgRF_memory__DIB), + .we1(mesgRF_memory__WEA), + .we2(mesgRF_memory__WEB), + .out1(dp_out_not_used1), + .out2(mesgRF_memory__DOB) + ); + + // submodule mesgWF_memory +//#(.PIPELINED(1'b0), +// .ADDR_WIDTH(32'b010), +// .DATA_WIDTH(32'b1056), +// .MEMSIZE(11'b1024)) mesgWF_memory( + + dual_port_ram dpram2 ( + .clk(wciS0_Clk), + .addr1(mesgWF_memory__ADDRA), + .addr2(mesgWF_memory__ADDRB), + .data1(mesgWF_memory__DIA), + .data2(mesgWF_memory__DIB), + .we1(mesgWF_memory__WEA), + .we2(mesgWF_memory__WEB), + .out1(dp_out_not_used2), + .out2(mesgWF_memory__DOB) + ); + + // submodule metaRF + arSRLFIFO_a ars1 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(metaRF__D_IN), + .ENQ(metaRF__ENQ), + .DEQ(metaRF__DEQ), + .CLR(metaRF__CLR), + .D_OUT(metaRF__D_OUT), + .EMPTY_N(metaRF__EMPTY_N), + .FULL_N(metaRF__FULL_N) + ); + + // submodule metaWF + arSRLFIFO_b ars2 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(metaWF__D_IN), + .ENQ(metaWF__ENQ), + .DEQ(metaWF__DEQ), + .CLR(metaWF__CLR), + .D_OUT(metaWF__D_OUT), + .EMPTY_N(metaWF__EMPTY_N), + .FULL_N(metaWF__FULL_N) + ); + + // submodule wci_isReset + ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset__VAL)); + + wire full_a_not_used; + // submodule wci_reqF + SizedFIFO_a sizefifo1 ( + .CLK(wciS0_Clk), + .D_IN(wci_reqF__D_IN), + .ENQ(wci_reqF__ENQ), + .DEQ(wci_reqF__DEQ), + .CLR(wci_reqF__CLR), + .D_OUT(wci_reqF__D_OUT), + .FULL_N(full_a_not_used), + .EMPTY_N(wci_reqF__EMPTY_N) + ); + + // submodule wide16Fa + arSRLFIFO_c ars3 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(wide16Fa__D_IN), + .ENQ(wide16Fa__ENQ), + .DEQ(wide16Fa__DEQ), + .CLR(wide16Fa__CLR), + .D_OUT(wide16Fa__D_OUT), + .EMPTY_N(wide16Fa__EMPTY_N), + .FULL_N(wide16Fa__FULL_N) + ); + + // submodule wide16Fb + arSRLFIFO_d ars4 ( + .CLK(wciS0_Clk), + .RST_N(wciS0_MReset_n), + .D_IN(wide16Fb__D_IN), + .ENQ(wide16Fb__ENQ), + .DEQ(wide16Fb__DEQ), + .CLR(wide16Fb__CLR), + .D_OUT(wide16Fb__D_OUT), + .EMPTY_N(wide16Fb__EMPTY_N), + .FULL_N(wide16Fb__FULL_N) + ); + + // submodule wmemi_isReset + ResetToBool wmemi_isReset(.RST(wciS0_MReset_n), .VAL(wmemi_isReset__VAL)); + + // submodule wmemi_respF +// #(.width(32'b0131), +// .guarded(32'b01)) wmemi_respF(.RST_N(wciS0_MReset_n), + SizedFIFO_x fifo_2 ( + .CLK(wciS0_Clk), + .D_IN(wmemi_respF__D_IN), + .ENQ(wmemi_respF__ENQ), + .DEQ(wmemi_respF__DEQ), + .CLR(wmemi_respF__CLR), + .D_OUT(wmemi_respF__D_OUT), + .FULL_N(wmemi_respF__FULL_N), + .EMPTY_N(wmemi_respF__EMPTY_N) + ); + + // submodule wsiM_isReset + ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset__VAL)); + + // submodule wsiS_isReset + ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset__VAL)); + + //#(.p1width(32'b1113), + // .p2depth(32'b11), + // .p3cntr_width(32'b01), + // .guarded(32'b01)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + // submodule wsiS_reqFifo + SizedFIFO_b sizefifo2 ( + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo__D_IN), + .ENQ(wsiS_reqFifo__ENQ), + .DEQ(wsiS_reqFifo__DEQ), + .CLR(wsiS_reqFifo__CLR), + .D_OUT(wsiS_reqFifo__D_OUT), + .FULL_N(wsiS_reqFifo__FULL_N), + .EMPTY_N(wsiS_reqFifo__EMPTY_N) + ); + + // rule RL_wci_request_decode + assign CAN_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + assign WILL_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + + // rule RL_wci_ctl_op_start + assign CAN_FIRE_RL_wci_ctl_op_start = + wci_reqF__EMPTY_N && wci_wci_ctrl_pw__whas ; + assign WILL_FIRE_RL_wci_ctl_op_start = + CAN_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign CAN_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b000 && + wci_reqF__D_OUT[36:34] == 3'b000 ; + assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ; + + // rule RL_wci_ctrl_OrE + assign CAN_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b010 && + wci_reqF__D_OUT[36:34] == 3'b011 ; + assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ; + + // rule RL_wci_respF_deq + assign CAN_FIRE_RL_wci_respF_deq = 1'b1 ; + assign WILL_FIRE_RL_wci_respF_deq = 1'b1 ; + + // rule RL_wmemi_update_statusR + assign CAN_FIRE_RL_wmemi_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wmemi_update_statusR = 1'b1 ; + + // rule RL_wci_sThreadBusy_reg + assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + + // rule RL_wci_sFlagReg__dreg_update + assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + + // rule RL_wsi_Es_doAlways + assign CAN_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + + // rule RL_wsiS_update_statusR + assign CAN_FIRE_RL_wsiS_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiS_update_statusR = 1'b1 ; + + // rule RL_wsiS_ext_status_assign + assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + + // rule RL_wsiS_inc_tBusyCount + assign CAN_FIRE_RL_wsiS_inc_tBusyCount = + wsiS_operateD && wsiS_peerIsReady && + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 ; + assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // rule RL_wsiS_reqFifo_enq + assign CAN_FIRE_RL_wsiS_reqFifo_enq = + wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq__wget[312:310] == 3'b001 ; + assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // rule RL_wsiS_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wsiM_update_statusR + assign CAN_FIRE_RL_wsiM_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiM_update_statusR = 1'b1 ; + + // rule RL_wsiM_ext_status_assign + assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + + // rule RL_wci_cfrd + assign CAN_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfrd_pw__whas ; + assign WILL_FIRE_RL_wci_cfrd = + CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wsiM_inc_tBusyCount + assign CAN_FIRE_RL_wsiM_inc_tBusyCount = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // rule RL_wsiM_reqFifo_deq + assign CAN_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'b00 && !wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_sThreadBusy_reg + assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + + // rule RL_wsiM_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_operating_actions + assign CAN_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + assign WILL_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + + // rule RL_wsiS_operateD__dreg_update + assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + + // rule RL_wsiM_operateD__dreg_update + assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + + // rule RL_wmrd_mesgBegin + assign CAN_FIRE_RL_wmrd_mesgBegin = + metaRF__EMPTY_N && wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && + unrollCnt == 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBegin = CAN_FIRE_RL_wmrd_mesgBegin ; + + // rule RL_wmwt_messageFinalize + assign CAN_FIRE_RL_wmwt_messageFinalize = + (!impreciseBurst || metaWF__FULL_N) && + wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397 ; + assign WILL_FIRE_RL_wmwt_messageFinalize = + CAN_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wci_Es_doAlways_Req + assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + + // rule RL_wci_reqF_enq + assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq__wget[59:57] != 3'b000 ; + assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ; + + // rule RL_wsipass_doMessagePush + assign CAN_FIRE_RL_wsipass_doMessagePush = + wsiM_reqFifo_c_r != 2'b10 && wsiS_reqFifo__EMPTY_N && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h0 ; + assign WILL_FIRE_RL_wsipass_doMessagePush = + CAN_FIRE_RL_wsipass_doMessagePush ; + + // rule RL_delay_write_req + assign CAN_FIRE_RL_delay_write_req = + wide16Fa__EMPTY_N && wmemi_reqF_c_r != 2'b10 && + wmemi_dhF_c_r != 2'b10 && + wmemi_operateD && + wmemi_peerIsReady && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + !blockDelayWrite ; + assign WILL_FIRE_RL_delay_write_req = CAN_FIRE_RL_delay_write_req ; + + // rule RL_delay_read_req + assign CAN_FIRE_RL_delay_read_req = + wmemi_reqF_c_r != 2'b10 && wmemi_operateD && wmemi_peerIsReady && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + NOT_dlyWordsStored_value_13_SLE_0_64_65_AND_NO_ETC___d272 && + (dlyReadCredit_value ^ 8'h80) > 8'b10000000 ; + assign WILL_FIRE_RL_delay_read_req = + CAN_FIRE_RL_delay_read_req && !WILL_FIRE_RL_delay_write_req ; + + // rule RL_wmwt_messagePushPrecise + assign CAN_FIRE_RL_wmwt_messagePushPrecise = + mesgWF_rRdPtr + 11'b01000000000 != mesgWF_rWrPtr && + wsiS_reqFifo__EMPTY_N && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + wsiWordsRemain != 12'b00 && + mesgReqValid && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushPrecise = + CAN_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_requestPrecise + assign CAN_FIRE_RL_wmwt_requestPrecise = + metaWF__FULL_N && wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && + readyToRequest && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_requestPrecise = + CAN_FIRE_RL_wmwt_requestPrecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_messagePushImprecise + assign CAN_FIRE_RL_wmwt_messagePushImprecise = + mesgWF_rRdPtr + 11'b01000000000 != mesgWF_rWrPtr && + wsiS_reqFifo__EMPTY_N && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + readyToPush && + impreciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushImprecise = + CAN_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wsiS_reqFifo__updateLevelCounter + assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq__whas ; + assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // rule RL_wmwt_mesgBegin + assign CAN_FIRE_RL_wmwt_mesgBegin = + wsiS_reqFifo__EMPTY_N && wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + !opcode[8] ; + assign WILL_FIRE_RL_wmwt_mesgBegin = + CAN_FIRE_RL_wmwt_mesgBegin && + !WILL_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_doAbort + assign CAN_FIRE_RL_wmwt_doAbort = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && doAbort ; + assign WILL_FIRE_RL_wmwt_doAbort = CAN_FIRE_RL_wmwt_doAbort ; + + // rule RL_wmemi_Em_doAlways + assign CAN_FIRE_RL_wmemi_Em_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wmemi_Em_doAlways = 1'b1 ; + + // rule RL_rdSer_sync + assign CAN_FIRE_RL_rdSer_sync = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && rdSyncWord ; + assign WILL_FIRE_RL_rdSer_sync = CAN_FIRE_RL_rdSer_sync ; + + // rule RL_rdSer_body + assign CAN_FIRE_RL_rdSer_body = + NOT_mesgRF_rRdPtr_52_PLUS_512_93_EQ_mesgRF_rWr_ETC___d208 && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + rdSerUnroll != 16'b0000000000000000 && + !rdSyncWord ; + assign WILL_FIRE_RL_rdSer_body = CAN_FIRE_RL_rdSer_body ; + + // rule RL_rdSer_begin + assign CAN_FIRE_RL_rdSer_begin = + metaRF_RDY_enq__41_AND_NOT_rdSerEmpty_96_97_AN_ETC___d242 && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + rdSerUnroll == 16'b0000000000000000 && + !rdSyncWord ; + assign WILL_FIRE_RL_rdSer_begin = CAN_FIRE_RL_rdSer_begin ; + + // rule RL_delay_read_resp + assign CAN_FIRE_RL_delay_read_resp = + wide16Fb__FULL_N && wmemi_respF__EMPTY_N && wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 ; + assign WILL_FIRE_RL_delay_read_resp = CAN_FIRE_RL_delay_read_resp ; + + // rule RL_delay_write_unblock + assign CAN_FIRE_RL_delay_write_unblock = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && blockDelayWrite ; + assign WILL_FIRE_RL_delay_write_unblock = CAN_FIRE_RL_delay_write_unblock ; + + // rule RL_wrtSer_begin + assign CAN_FIRE_RL_wrtSer_begin = + metaWF__EMPTY_N && + metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365 && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + wrtSerUnroll == 16'b0000000000000000 ; + assign WILL_FIRE_RL_wrtSer_begin = CAN_FIRE_RL_wrtSer_begin ; + + // rule RL_cycles_passed_count + assign CAN_FIRE_RL_cycles_passed_count = wsiS_statusR[0] ; + assign WILL_FIRE_RL_cycles_passed_count = CAN_FIRE_RL_cycles_passed_count ; + + // rule RL_dlyWordsStored_accumulate + assign CAN_FIRE_RL_dlyWordsStored_accumulate = 1'b1 ; + assign WILL_FIRE_RL_dlyWordsStored_accumulate = 1'b1 ; + + // rule RL_dlyReadCredit_accumulate + assign CAN_FIRE_RL_dlyReadCredit_accumulate = 1'b1 ; + assign WILL_FIRE_RL_dlyReadCredit_accumulate = 1'b1 ; + + // rule RL_wci_ctrl_IsO + assign CAN_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b001 && + wci_reqF__D_OUT[36:34] == 3'b001 ; + assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ; + + // rule RL_mesgRF_portB_read_data + assign CAN_FIRE_RL_mesgRF_portB_read_data = 1'b1 ; + assign WILL_FIRE_RL_mesgRF_portB_read_data = 1'b1 ; + + // rule RL_wmrd_mesgBodyResponse + assign CAN_FIRE_RL_wmrd_mesgBodyResponse = + wsiM_reqFifo_c_r != 2'b10 && mesgRF_rRdPtr != mesgRF_rWrPtr && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + unrollCnt != 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + CAN_FIRE_RL_wmrd_mesgBodyResponse ; + + // rule RL_wsiM_reqFifo_both + assign CAN_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'b01) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b10 || wsiM_reqFifo_x_wire__whas) && + CAN_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ; + + // rule RL_wsiM_reqFifo_decCtr + assign CAN_FIRE_RL_wsiM_reqFifo_decCtr = + CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ; + + // rule RL_wsiM_reqFifo_incCtr + assign CAN_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'b00) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b01 || wsiM_reqFifo_x_wire__whas) && + wsiM_reqFifo_enqueueing__whas && + !CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ; + + // rule RL_mesgRF_portB + assign CAN_FIRE_RL_mesgRF_portB = 1'b1 ; + assign WILL_FIRE_RL_mesgRF_portB = 1'b1 ; + + // rule RL_mesgRF_portA + assign CAN_FIRE_RL_mesgRF_portA = 1'b1 ; + assign WILL_FIRE_RL_mesgRF_portA = 1'b1 ; + + // rule RL_mesgWF_portB_read_data + assign CAN_FIRE_RL_mesgWF_portB_read_data = 1'b1 ; + assign WILL_FIRE_RL_mesgWF_portB_read_data = 1'b1 ; + + // rule RL_wrtSer_body + assign CAN_FIRE_RL_wrtSer_body = + mesgWF_rRdPtr != mesgWF_rWrPtr && + CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 && + (wrtSerPos != 2'b11 && wrtSerUnroll != 16'b0000000000000001 || + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904) && + wci_cState == 3'b010 && + dlyCtrl[3:0] == 4'h7 && + wrtSerUnroll != 16'b0000000000000000 ; + assign WILL_FIRE_RL_wrtSer_body = CAN_FIRE_RL_wrtSer_body ; + + // rule RL_wci_ctl_op_complete + assign CAN_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'b10 && wci_ctlOpActive && wci_ctlAckReg ; + assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_cfwr + assign CAN_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfwr_pw__whas ; + assign WILL_FIRE_RL_wci_cfwr = + CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctlAckReg__dreg_update + assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + + // rule RL_wci_respF_both + assign CAN_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'b01) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b10 || wci_respF_x_wire__whas) && + wci_respF_c_r != 2'b00 && + wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ; + + // rule RL_wci_respF_decCtr + assign CAN_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'b00 && !wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ; + + // rule RL_wci_respF_incCtr + assign CAN_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'b00) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b01 || wci_respF_x_wire__whas) && + wci_respF_enqueueing__whas && + !(wci_respF_c_r != 2'b00) ; + assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ; + + // rule RL_wci_reqF__updateLevelCounter + assign CAN_FIRE_RL_wci_reqF__updateLevelCounter = + (wci_wciReq__wget[59:57] != 3'b000) != wci_reqF_r_deq__whas ; + assign WILL_FIRE_RL_wci_reqF__updateLevelCounter = + CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // rule RL_mesgWF_portB + assign CAN_FIRE_RL_mesgWF_portB = 1'b1 ; + assign WILL_FIRE_RL_mesgWF_portB = 1'b1 ; + + // rule RL_mesgWF_portA + assign CAN_FIRE_RL_mesgWF_portA = 1'b1 ; + assign WILL_FIRE_RL_mesgWF_portA = 1'b1 ; + + // rule RL_wmemi_respAdvance + assign CAN_FIRE_RL_wmemi_respAdvance = + wmemi_respF__FULL_N && wmemi_operateD && wmemi_peerIsReady && + wmemi_wmemiResponse__wget[130:129] != 2'b00 ; + assign WILL_FIRE_RL_wmemi_respAdvance = CAN_FIRE_RL_wmemi_respAdvance ; + + // rule RL_wmemi_peerIsReady__dreg_update + assign CAN_FIRE_RL_wmemi_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmemi_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wmemi_operateD__dreg_update + assign CAN_FIRE_RL_wmemi_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmemi_operateD__dreg_update = 1'b1 ; + + // rule RL_wmemi_dhF_deq + assign CAN_FIRE_RL_wmemi_dhF_deq = wmemiM_SDataAccept ; + assign WILL_FIRE_RL_wmemi_dhF_deq = wmemiM_SDataAccept ; + + // rule RL_wmemi_reqF_deq + assign CAN_FIRE_RL_wmemi_reqF_deq = wmemiM_SCmdAccept ; + assign WILL_FIRE_RL_wmemi_reqF_deq = wmemiM_SCmdAccept ; + + // rule RL_wmemi_dhF_both + assign CAN_FIRE_RL_wmemi_dhF_both = + ((wmemi_dhF_c_r == 2'b01) ? + CAN_FIRE_RL_delay_write_req : + wmemi_dhF_c_r != 2'b10 || CAN_FIRE_RL_delay_write_req) && + wmemi_dhF_dequeueing__whas && + CAN_FIRE_RL_delay_write_req ; + assign WILL_FIRE_RL_wmemi_dhF_both = CAN_FIRE_RL_wmemi_dhF_both ; + + // rule RL_wmemi_dhF_decCtr + assign CAN_FIRE_RL_wmemi_dhF_decCtr = + wmemi_dhF_dequeueing__whas && !CAN_FIRE_RL_delay_write_req ; + assign WILL_FIRE_RL_wmemi_dhF_decCtr = CAN_FIRE_RL_wmemi_dhF_decCtr ; + + // rule RL_wmemi_dhF_incCtr + assign CAN_FIRE_RL_wmemi_dhF_incCtr = + ((wmemi_dhF_c_r == 2'b00) ? + CAN_FIRE_RL_delay_write_req : + wmemi_dhF_c_r != 2'b01 || CAN_FIRE_RL_delay_write_req) && + CAN_FIRE_RL_delay_write_req && + !wmemi_dhF_dequeueing__whas ; + assign WILL_FIRE_RL_wmemi_dhF_incCtr = CAN_FIRE_RL_wmemi_dhF_incCtr ; + + // rule RL_wmemi_reqF_both + assign CAN_FIRE_RL_wmemi_reqF_both = + ((wmemi_reqF_c_r == 2'b01) ? + wmemi_reqF_enqueueing__whas : + wmemi_reqF_c_r != 2'b10 || wmemi_reqF_enqueueing__whas) && + wmemi_reqF_dequeueing__whas && + wmemi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmemi_reqF_both = CAN_FIRE_RL_wmemi_reqF_both ; + + // rule RL_wmemi_reqF_incCtr + assign CAN_FIRE_RL_wmemi_reqF_incCtr = + ((wmemi_reqF_c_r == 2'b00) ? + wmemi_reqF_enqueueing__whas : + wmemi_reqF_c_r != 2'b01 || wmemi_reqF_enqueueing__whas) && + wmemi_reqF_enqueueing__whas && + !wmemi_reqF_dequeueing__whas ; + assign WILL_FIRE_RL_wmemi_reqF_incCtr = CAN_FIRE_RL_wmemi_reqF_incCtr ; + + // rule RL_wmemi_reqF_decCtr + assign CAN_FIRE_RL_wmemi_reqF_decCtr = + wmemi_reqF_dequeueing__whas && !wmemi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmemi_reqF_decCtr = CAN_FIRE_RL_wmemi_reqF_decCtr ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge__write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge__write_1__VAL_2 = + wci_reqF__D_OUT[36:34] != 3'b100 && wci_reqF__D_OUT[36:34] != 3'b101 && + wci_reqF__D_OUT[36:34] != 3'b110 ; + assign MUX_wci_respF_c_r__write_1__VAL_2 = wci_respF_c_r + 2'b01 ; + assign MUX_wci_respF_c_r__write_1__VAL_1 = wci_respF_c_r - 2'b01 ; + assign MUX_wci_respF_x_wire__wset_1__VAL_2 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_illegalEdge__write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState != 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && wci_cState != 3'b001 && + wci_cState != 3'b011 || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState != 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && wci_cState != 3'b011 && + wci_cState != 3'b010 && + wci_cState != 3'b001 || + wci_reqF__D_OUT[36:34] == 3'b100 || + wci_reqF__D_OUT[36:34] == 3'b101 || + wci_reqF__D_OUT[36:34] == 3'b110 || + wci_reqF__D_OUT[36:34] == 3'b111) ; + assign MUX_wci_respF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 ; + assign MUX_wci_respF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_1 = wsiM_reqFifo_c_r - 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_2 = wsiM_reqFifo_c_r + 2'b01 ; + assign MUX_wsiM_reqFifo_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 ; + assign MUX_wsiM_reqFifo_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 ; + assign MUX_mesgLength__write_1__VAL_2 = + (wsiS_reqFifo__D_OUT[39:8] == 32'b00000000000000000000000000000000) ? + 15'b100000000000000 : + { 1'b1, wsiS_reqFifo__D_OUT[304:296], 5'b00000 } ; + assign MUX_mesgLengthSoFar__write_1__VAL_2 = mesgLengthSoFar + 14'b00000000000001 ; + assign MUX_opcode__write_1__VAL_2 = { 1'b1, wsiS_reqFifo__D_OUT[7:0] } ; + assign MUX_unrollCnt__write_1__VAL_1 = + (metaRF__D_OUT[23:0] == 24'b000000000000000000000000) ? 16'b0000000000000001 : metaRF__D_OUT[20:5] ; + assign MUX_unrollCnt__write_1__VAL_2 = unrollCnt - 16'b0000000000000001 ; + assign MUX_wsiWordsRemain__write_1__VAL_2 = wsiWordsRemain - 12'b01 ; + assign MUX_mesgLength__write_1__VAL_3 = { 1'b1, mlp1__h17953[8:0], 5'b00000 } ; + assign MUX_mesgRdCount__write_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 ; + assign MUX_dlyRAG__write_1__VAL_1 = dlyRAG + 20'b00000000000000000001 ; + assign MUX_dlyWAG__write_1__VAL_1 = dlyWAG + 20'b00000000000000000001 ; + assign MUX_mesgRdCount__write_1__VAL_1 = mesgRdCount + 32'b00000000000000000000000000000001 ; + assign MUX_mesgWtCount__write_1__VAL_1 = mesgWtCount + 32'b00000000000000000000000000000001 ; + assign MUX_metaWF__enq_1__VAL_1 = { x1_opcode__h17253, x1_length__h17254 } ; + assign MUX_rdSerPos__write_1__VAL_1 = rdSerPos + 2'b01 ; + assign MUX_rdSerUnroll__write_1__VAL_2 = rdSerUnroll - 16'b0000000000000001 ; + assign MUX_rdSyncWord__write_1__VAL_1 = + rdSerPos != 2'b11 && rdSerUnroll == 16'b0000000000000001 ; + assign MUX_wmemi_dhF_c_r__write_1__VAL_1 = wmemi_dhF_c_r - 2'b01 ; + assign MUX_wmemi_dhF_c_r__write_1__VAL_2 = wmemi_dhF_c_r + 2'b01 ; + assign MUX_wmemi_dhF_q_0__write_1__VAL_2 = + { 2'b11, wide16Fa__D_OUT, 16'b1111111111111111 } ; + assign MUX_wmemi_dhF_q_0__write_1__VAL_1 = + (wmemi_dhF_c_r == 2'b01) ? + MUX_wmemi_dhF_q_0__write_1__VAL_2 : + wmemi_dhF_q_1 ; + assign MUX_wmemi_dhF_q_1__write_1__VAL_1 = + (wmemi_dhF_c_r == 2'b10) ? + MUX_wmemi_dhF_q_0__write_1__VAL_2 : + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; + assign MUX_wmemi_reqF_c_r__write_1__VAL_1 = wmemi_reqF_c_r - 2'b01 ; + assign MUX_wmemi_reqF_c_r__write_1__VAL_2 = wmemi_reqF_c_r + 2'b01 ; + assign MUX_wrtSerUnroll__write_1__VAL_1 = wrtSerUnroll - 16'b0000000000000001 ; + assign MUX_wmemi_dhF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b00 ; + assign MUX_wmemi_dhF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b01 ; + assign MUX_wmemi_reqF_x_wire__wset_1__VAL_1 = { 4'b0101, addr__h20994, 12'b01 } ; + assign MUX_wmemi_reqF_x_wire__wset_1__VAL_2 = { 4'b0011, addr__h21166, 12'b01 } ; + assign MUX_wci_respF_x_wire__wset_1__VAL_1 = { 2'b01, x_data__h21804 } ; + always@(WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire__wset_1__VAL_1 or + WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire__wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0__write_1__VAL_2 = + MUX_wci_respF_x_wire__wset_1__VAL_1; + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0__write_1__VAL_2 = + MUX_wci_respF_x_wire__wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0__write_1__VAL_2 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0__write_1__VAL_2 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_0__write_1__VAL_1 = + (wci_respF_c_r == 2'b01) ? + MUX_wci_respF_q_0__write_1__VAL_2 : + wci_respF_q_1 ; + assign MUX_wci_respF_q_1__write_1__VAL_1 = + (wci_respF_c_r == 2'b10) ? + MUX_wci_respF_q_0__write_1__VAL_2 : + 34'h0AAAAAAAA ; + assign MUX_rdSyncWord__write_1__VAL_2 = + rdSerPos != 2'b11 && v__h22720[23:0] == 24'b000000000000000000000000 ; + assign MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 = + { 3'b001, + unrollCnt == 16'b0000000000000001, + 1'b1, + x_burstLength__h22437, + mesg__h22346, + x_byteEn__h22438, + readMeta[31:24] } ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_2 = + WILL_FIRE_RL_wmrd_mesgBodyResponse ? + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 : + wsiS_reqFifo__D_OUT ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b01) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b10) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ; + assign MUX_rdSerEmpty__write_1__PSEL_1 = + WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body ; + assign MUX_rdSerEmpty__write_1__SEL_1 = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + assign MUX_dlyReadCredit_value__write_1__VAL_2 = + dlyReadCredit_value + + (WILL_FIRE_RL_delay_read_req ? 8'b11111111 : 8'b00000000) + + (CAN_FIRE_RL_delay_read_resp ? 8'b00000001 : 8'b00000000) ; + assign MUX_dlyWordsStored_value__write_1__VAL_2 = + dlyWordsStored_value + + (CAN_FIRE_RL_delay_write_req ? 20'b00000000000000000001 : 20'b00000000000000000000) + + (WILL_FIRE_RL_delay_read_req ? 20'b00000000000000000001: 20'b00000000000000000000) ; + assign MUX_wmemi_reqF_q_0__write_1__VAL_2 = + WILL_FIRE_RL_delay_read_req ? + MUX_wmemi_reqF_x_wire__wset_1__VAL_1 : + MUX_wmemi_reqF_x_wire__wset_1__VAL_2 ; + assign MUX_wmemi_reqF_q_0__write_1__VAL_1 = + (wmemi_reqF_c_r == 2'b01) ? + MUX_wmemi_reqF_q_0__write_1__VAL_2 : + wmemi_reqF_q_1 ; + assign MUX_wmemi_reqF_q_1__write_1__VAL_1 = + (wmemi_reqF_c_r == 2'b10) ? + MUX_wmemi_reqF_q_0__write_1__VAL_2 : + 52'h0AAAAAAAAAAAA ; + assign MUX_wmemi_reqF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b00 ; + assign MUX_wmemi_reqF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b01 ; + always@(wrtSerPos or + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354 or + x1__h19969 or x1__h19978) + begin + case (wrtSerPos) + 2'b00: MUX_wide16Fa__enq_1__VAL_2 = x1__h19969; + 2'b01: MUX_wide16Fa__enq_1__VAL_2 = x1__h19978; + default: MUX_wide16Fa__enq_1__VAL_2 = + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354; + endcase + end + always@(wrtSerPos or + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377 or + x1__h20492 or x1__h20501) + begin + case (wrtSerPos) + 2'b00: MUX_wide16Fa__enq_1__VAL_1 = x1__h20492; + 2'b01: MUX_wide16Fa__enq_1__VAL_1 = x1__h20501; + default: MUX_wide16Fa__enq_1__VAL_1 = + IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377; + endcase + end + assign MUX_wrtSerPos__write_1__VAL_1 = + (wrtSerUnroll == 16'b0000000000000001) ? 2'b00 : wrtSerPos_11_PLUS_1___d1014 ; + assign MUX_wrtSerPos__write_1__VAL_2 = + (metaWF__D_OUT[23:0] == 24'b000000000000000000000000) ? + 2'b00 : + wrtSerPos_11_PLUS_1___d1014 ; + assign MUX_endOfMessage__write_1__SEL_1 = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 ; + assign MUX_impreciseBurst__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] ; + assign MUX_mesgLength__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] ; + assign MUX_metaWF__enq_1__SEL_1 = + WILL_FIRE_RL_wmwt_messageFinalize && impreciseBurst ; + assign MUX_wrtSerStage__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b00 ; + assign MUX_wrtSerStage_1__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b01 ; + assign MUX_wrtSerStage_2__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b10 ; + assign MUX_wrtSerStage_3__write_1__SEL_1 = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b11 ; + assign MUX_wide16Fa__enq_1__SEL_1 = + WILL_FIRE_RL_wrtSer_begin && + (wrtSerPos == 2'b11 || metaWF__D_OUT[23:0] == 24'b000000000000000000000000) ; + + // inlined wires + assign wci_wciReq__whas = 1'b1 ; + assign wci_wciReq__wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_reqF_r_enq__whas = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF_r_clr__whas = 1'b0 ; + assign wci_respF_dequeueing__whas = wci_respF_c_r != 2'b00 ; + assign wci_wEdge__wget = wci_reqF__D_OUT[36:34] ; + assign wci_sThreadBusy_pw__whas = 1'b0 ; + assign wci_sFlagReg_1__wget = 1'b0 ; + assign wci_wci_cfwr_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b001 ; + assign wci_sFlagReg_1__whas = 1'b0 ; + assign wci_wci_cfrd_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_wci_ctrl_pw__whas = + wci_reqF__EMPTY_N && !wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_reqF_r_deq__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_respF_enqueueing__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_respF_x_wire__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_cfwr ; + assign wci_wEdge__whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_ctlAckReg_1__wget = 1'b1 ; + assign wci_ctlAckReg_1__whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wmemi_operateD_1__wget = 1'b1 ; + assign wmemi_operateD_1__whas = wci_cState == 3'b010 ; + assign wmemi_peerIsReady_1__whas = 1'b0 ; + assign wmemi_peerIsReady_1__wget = 1'b0 ; + assign wsiM_reqFifo_dequeueing__whas = CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw__whas = wsiM1_SThreadBusy ; + assign wsiM_operateD_1__wget = 1'b1 ; + assign wsiM_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiM_peerIsReady_1__wget = 1'b1 ; + assign wsiM_peerIsReady_1__whas = wsiM1_SReset_n ; + assign wsiM_extStatusW__wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + assign wsiS_reqFifo_r_clr__whas = 1'b0 ; + assign wsiS_wsiReq__wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsiS_wsiReq__whas = 1'b1 ; + assign wsiS_reqFifo_r_enq__whas = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_operateD_1__wget = 1'b1 ; + assign wsiS_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiS_peerIsReady_1__wget = 1'b1 ; + assign wsiS_peerIsReady_1__whas = wsiS1_MReset_n ; + assign wsiS_extStatusW__wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsi_Es_mCmd_w__wget = wsiS1_MCmd ; + assign wsi_Es_mCmd_w__whas = 1'b1 ; + assign wsi_Es_mReqLast_w__whas = wsiS1_MReqLast ; + assign wsi_Es_mBurstPrecise_w__whas = wsiS1_MBurstPrecise ; + assign wsi_Es_mBurstLength_w__wget = wsiS1_MBurstLength ; + assign wsi_Es_mBurstLength_w__whas = 1'b1 ; + assign wsi_Es_mData_w__wget = wsiS1_MData ; + assign wsi_Es_mData_w__whas = 1'b1 ; + assign wsi_Es_mByteEn_w__whas = 1'b1 ; + assign wsi_Es_mByteEn_w__wget = wsiS1_MByteEn ; + assign wsi_Es_mReqInfo_w__wget = wsiS1_MReqInfo ; + assign wsi_Es_mReqInfo_w__whas = 1'b1 ; + assign wsi_Es_mDataInfo_w__whas = 1'b1 ; + assign wsiM_reqFifo_enqueueing__whas = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + assign wsiM_reqFifo_x_wire__whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wsipass_doMessagePush ; + assign wci_Es_mCmd_w__wget = wciS0_MCmd ; + assign wci_Es_mCmd_w__whas = 1'b1 ; + assign wci_Es_mAddrSpace_w__wget = wciS0_MAddrSpace ; + assign wci_Es_mAddrSpace_w__whas = 1'b1 ; + assign wci_Es_mAddr_w__wget = wciS0_MAddr ; + assign wci_Es_mAddr_w__whas = 1'b1 ; + assign wci_Es_mData_w__wget = wciS0_MData ; + assign wci_Es_mByteEn_w__wget = wciS0_MByteEn ; + assign wci_Es_mData_w__whas = 1'b1 ; + assign wci_Es_mByteEn_w__whas = 1'b1 ; + assign wmemi_reqF_dequeueing__whas = + wmemiM_SCmdAccept && wmemi_reqF_c_r != 2'b00 ; + assign wmemi_dhF_enqueueing__whas = CAN_FIRE_RL_delay_write_req ; + assign wmemi_dhF_x_wire__wget = MUX_wmemi_dhF_q_0__write_1__VAL_2 ; + assign wmemi_dhF_x_wire__whas = CAN_FIRE_RL_delay_write_req ; + assign wmemi_dhF_dequeueing__whas = + wmemiM_SDataAccept && wmemi_dhF_c_r != 2'b00 ; + assign wmemi_wmemiResponse__wget = + { wmemiM_SResp, wmemiM_SRespLast, wmemiM_SData } ; + assign wmemi_wmemiResponse__whas = 1'b1 ; + assign wmemi_sDataAccept_w__wget = 1'b1 ; + assign wmemi_sCmdAccept_w__wget = 1'b1 ; + assign wmemi_sCmdAccept_w__whas = wmemiM_SCmdAccept ; + assign wmemi_sDataAccept_w__whas = wmemiM_SDataAccept ; + assign mesgWF_wDataIn__wget = wsiS_reqFifo__D_OUT[295:40] ; + assign mesgWF_wDataOut__wget = + (mesgWF_rCache[267] && mesgWF_rCache[266:256] == mesgWF_rRdPtr) ? + mesgWF_rCache[255:0] : + mesgWF_memory__DOB ; + assign mesgRF_wDataIn__whas = CAN_FIRE_RL_rdSer_body ; + assign mesgWF_wDataOut__whas = 1'b1 ; + assign mesgRF_pwDequeue__whas = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + assign mesgRF_pwEnqueue__whas = CAN_FIRE_RL_rdSer_body ; + assign mesgRF_wDataOut__wget = + (mesgRF_rCache[267] && mesgRF_rCache[266:256] == mesgRF_rRdPtr) ? + mesgRF_rCache[255:0] : + mesgRF_memory__DOB ; + assign mesgRF_wDataOut__whas = 1'b1 ; + assign dlyWordsStored_acc_v1__wget = 20'b00000000000000000001 ; + assign dlyWordsStored_acc_v1__whas = CAN_FIRE_RL_delay_write_req ; + assign dlyWordsStored_acc_v2__wget = 20'b00000000000000000001 ; + assign dlyReadCredit_acc_v1__wget = 8'b11111111 ; + assign dlyReadCredit_acc_v2__wget = 8'b00000001 ; + assign dlyReadCredit_acc_v2__whas = CAN_FIRE_RL_delay_read_resp ; + assign wmemi_Em_sResp_w__wget = wmemiM_SResp ; + assign wmemi_Em_sRespLast_w__whas = wmemiM_SRespLast ; + assign wmemi_Em_sResp_w__whas = 1'b1 ; + assign wmemi_Em_sData_w__wget = wmemiM_SData ; + assign wmemi_Em_sData_w__whas = 1'b1 ; + assign wci_respF_x_wire__wget = MUX_wci_respF_q_0__write_1__VAL_2 ; + assign mesgRF_wDataIn__wget = { 224'b000000000000000000000000, v__h22720 } ; + assign wsiM_reqFifo_x_wire__wget = MUX_wsiM_reqFifo_q_0__write_1__VAL_2 ; + assign wmemi_reqF_enqueueing__whas = + WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_delay_write_req ; + assign wmemi_reqF_x_wire__wget = MUX_wmemi_reqF_q_0__write_1__VAL_2 ; + assign wmemi_reqF_x_wire__whas = wmemi_reqF_enqueueing__whas ; + assign dlyWordsStored_acc_v2__whas = WILL_FIRE_RL_delay_read_req ; + assign dlyReadCredit_acc_v1__whas = WILL_FIRE_RL_delay_read_req ; + assign wsiS_reqFifo_r_deq__whas = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign mesgWF_pwEnqueue__whas = + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign mesgWF_wDataIn__whas = mesgWF_pwEnqueue__whas ; + assign mesgWF_pwDequeue__whas = CAN_FIRE_RL_wrtSer_body ; + + // register abortCount + assign abortCount__D_IN = abortCount + 32'b00000000000000000000000000000001 ; + assign abortCount__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register blockDelayWrite + assign blockDelayWrite__D_IN = + WILL_FIRE_RL_delay_write_req && wrtDutyCount == 3'b111 ; + assign blockDelayWrite__EN = + WILL_FIRE_RL_delay_write_req || + WILL_FIRE_RL_delay_write_unblock ; + + // register bytesRead + assign bytesRead__D_IN = bytesRead + 32'b00000000000000000000000000100000 ; + assign bytesRead__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && bytesRead != 32'hFFFFFFFF ; + + // register bytesWritten + assign bytesWritten__D_IN = bytesWritten + 32'b00000000000000000000000000100000 ; + assign bytesWritten__EN = + _dor1bytesWritten__EN_write && bytesWritten != 32'hFFFFFFFF ; + + // register cyclesPassed + assign cyclesPassed__D_IN = cyclesPassed + 32'b000000000000000000000000001000001 ; + assign cyclesPassed__EN = wsiS_statusR[0] && cyclesPassed != 32'hFFFFFFFF ; + + // register dlyCtrl + assign dlyCtrl__D_IN = wci_reqF__D_OUT[31:0] ; + assign dlyCtrl__EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[51:32] == 20'h0 ; + + // register dlyHoldoffBytes + assign dlyHoldoffBytes__D_IN = wci_reqF__D_OUT[31:0] ; + assign dlyHoldoffBytes__EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[51:32] == 20'h00004 ; + + // register dlyHoldoffCycles + assign dlyHoldoffCycles__D_IN = wci_reqF__D_OUT[31:0] ; + assign dlyHoldoffCycles__EN = + WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[51:32] == 20'h00008 ; + + // register dlyRAG + assign dlyRAG__D_IN = + WILL_FIRE_RL_delay_read_req ? MUX_dlyRAG__write_1__VAL_1 : 20'b00000000000000000000 ; + assign dlyRAG__EN = + WILL_FIRE_RL_delay_read_req || WILL_FIRE_RL_wci_ctrl_IsO ; + + // register dlyReadCredit_value + assign dlyReadCredit_value__EN = 1'b1 ; + assign dlyReadCredit_value__D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 8'b00000001 : + MUX_dlyReadCredit_value__write_1__VAL_2 ; + + // register dlyWAG + assign dlyWAG__D_IN = + WILL_FIRE_RL_delay_write_req ? + MUX_dlyWAG__write_1__VAL_1 : + 20'b00000000000000000000 ; + assign dlyWAG__EN = + WILL_FIRE_RL_delay_write_req || WILL_FIRE_RL_wci_ctrl_IsO ; + + // register dlyWordsStored_value + assign dlyWordsStored_value__EN = 1'b1 ; + assign dlyWordsStored_value__D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 20'b00000000000000000000 : + MUX_dlyWordsStored_value__write_1__VAL_2 ; + + // register doAbort + assign doAbort__D_IN = 1'b0 ; + assign doAbort__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register endOfMessage + assign endOfMessage__D_IN = MUX_endOfMessage__write_1__SEL_1 ; + assign endOfMessage__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 || + WILL_FIRE_RL_wmwt_messageFinalize ; + + // register errCount - jluu: removed because never used +// assign errCount__D_IN = errCount + 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ; +// assign errCount__EN = +// WILL_FIRE_RL_wmwt_messagePushImprecise && +// wsiS_reqFifo__D_OUT[295:40] != valExpect && +// (wsiS_reqFifo__D_OUT[307:296] != 12'b01 || +// wsiS_reqFifo__D_OUT[39:8] != 32'b00000000000000000000000000000000) ; + + // register impreciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: impreciseBurst__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: impreciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: impreciseBurst__D_IN = 1'b0; + default: impreciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign impreciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register mesgLength + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or + MUX_mesgLength__write_1__VAL_2 or + MUX_endOfMessage__write_1__SEL_1 or + MUX_mesgLength__write_1__VAL_3 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: mesgLength__D_IN = 15'b010101010101010; + MUX_mesgLength__write_1__SEL_2: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_2; + MUX_endOfMessage__write_1__SEL_1: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_3; + WILL_FIRE_RL_wmwt_messageFinalize: mesgLength__D_IN = 15'b010101010101010; + default: mesgLength__D_IN = 15'b010101010101010 /* unspecified value */ ; + endcase + assign mesgLength__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 || + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register mesgLengthSoFar + assign mesgLengthSoFar__D_IN = + MUX_impreciseBurst__write_1__SEL_2 ? + 14'b00000000000000 : + MUX_mesgLengthSoFar__write_1__VAL_2 ; + assign mesgLengthSoFar__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // register mesgRF_rCache + assign mesgRF_rCache__EN = CAN_FIRE_RL_rdSer_body ; + assign mesgRF_rCache__D_IN = { 1'b1, mesgRF_rWrPtr, x__h16160 } ; + + // register mesgRF_rRdPtr + assign mesgRF_rRdPtr__D_IN = x__h16052 ; + assign mesgRF_rRdPtr__EN = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + + // register mesgRF_rWrPtr + assign mesgRF_rWrPtr__D_IN = mesgRF_rWrPtr + 11'b1 ; + assign mesgRF_rWrPtr__EN = CAN_FIRE_RL_rdSer_body ; + + // register mesgRdCount + assign mesgRdCount__D_IN = + MUX_mesgRdCount__write_1__SEL_1 ? + MUX_mesgRdCount__write_1__VAL_1 : + 32'b00000000000000000000000000000000 ; + assign mesgRdCount__EN = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register mesgReqValid + assign mesgReqValid__D_IN = !WILL_FIRE_RL_wmwt_messageFinalize ; + assign mesgReqValid__EN = + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register mesgWF_rCache + assign mesgWF_rCache__D_IN = { 1'b1, mesgWF_rWrPtr, x__h15234 } ; + assign mesgWF_rCache__EN = mesgWF_pwEnqueue__whas ; + + // register mesgWF_rRdPtr + assign mesgWF_rRdPtr__D_IN = x__h15126 ; + assign mesgWF_rRdPtr__EN = CAN_FIRE_RL_wrtSer_body ; + + // register mesgWF_rWrPtr + assign mesgWF_rWrPtr__D_IN = mesgWF_rWrPtr + 11'b1 ; + assign mesgWF_rWrPtr__EN = mesgWF_pwEnqueue__whas ; + + // register mesgWtCount + assign mesgWtCount__D_IN = + WILL_FIRE_RL_wmwt_messageFinalize ? + MUX_mesgWtCount__write_1__VAL_1 : + 32'b00000000000000000000000000000000 ; + assign mesgWtCount__EN = + WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wci_ctrl_IsO ; + + // register opcode + always@(WILL_FIRE_RL_wmwt_doAbort or + WILL_FIRE_RL_wmwt_mesgBegin or + MUX_opcode__write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: opcode__D_IN = 9'b010101010; + WILL_FIRE_RL_wmwt_mesgBegin: opcode__D_IN = MUX_opcode__write_1__VAL_2; + WILL_FIRE_RL_wmwt_messageFinalize: opcode__D_IN = 9'b010101010; + default: opcode__D_IN = 9'b010101010 /* unspecified value */ ; + endcase + assign opcode__EN = + WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wmwt_doAbort || + WILL_FIRE_RL_wmwt_mesgBegin ; + + // register preciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: preciseBurst__D_IN = 1'b0; + MUX_mesgLength__write_1__SEL_2: preciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: preciseBurst__D_IN = 1'b0; + default: preciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign preciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register rdSerAddr + assign rdSerAddr__D_IN = 32'h0 ; + assign rdSerAddr__EN = 1'b0 ; + + // register rdSerEmpty + assign rdSerEmpty__D_IN = !MUX_rdSerEmpty__write_1__SEL_1 ; + assign rdSerEmpty__EN = + (WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body) && + (rdSerEmpty || rdSerPos == 2'b00) || + WILL_FIRE_RL_rdSer_sync ; + + // register rdSerMeta + assign rdSerMeta__D_IN = metaRF__D_IN ; + assign rdSerMeta__EN = CAN_FIRE_RL_rdSer_begin ; + + // register rdSerPos + assign rdSerPos__D_IN = + MUX_rdSerEmpty__write_1__PSEL_1 ? + MUX_rdSerPos__write_1__VAL_1 : + 2'b00 ; + assign rdSerPos__EN = + WILL_FIRE_RL_rdSer_begin || WILL_FIRE_RL_rdSer_body || + WILL_FIRE_RL_rdSer_sync ; + + // register rdSerStage + assign rdSerStage__D_IN = wide16Fb__D_OUT[31:0] ; + assign rdSerStage__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerStage_1 + assign rdSerStage_1__D_IN = wide16Fb__D_OUT[63:32] ; + assign rdSerStage_1__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerStage_2 + assign rdSerStage_2__D_IN = wide16Fb__D_OUT[95:64] ; + assign rdSerStage_2__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerStage_3 + assign rdSerStage_3__D_IN = wide16Fb__D_OUT[127:96] ; + assign rdSerStage_3__EN = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // register rdSerUnroll + assign rdSerUnroll__D_IN = + WILL_FIRE_RL_rdSer_begin ? + v__h22720[20:5] : + MUX_rdSerUnroll__write_1__VAL_2 ; + assign rdSerUnroll__EN = MUX_rdSerEmpty__write_1__PSEL_1 ; + + // register rdSyncWord + always@(WILL_FIRE_RL_rdSer_body or + MUX_rdSyncWord__write_1__VAL_1 or + WILL_FIRE_RL_rdSer_begin or + MUX_rdSyncWord__write_1__VAL_2 or WILL_FIRE_RL_rdSer_sync) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_rdSer_body: + rdSyncWord__D_IN = MUX_rdSyncWord__write_1__VAL_1; + WILL_FIRE_RL_rdSer_begin: + rdSyncWord__D_IN = MUX_rdSyncWord__write_1__VAL_2; + WILL_FIRE_RL_rdSer_sync: rdSyncWord__D_IN = 1'b0; + default: rdSyncWord__D_IN = 1'b0 /* unspecified value */ ; + endcase + end + assign rdSyncWord__EN = + WILL_FIRE_RL_rdSer_body || WILL_FIRE_RL_rdSer_begin || + WILL_FIRE_RL_rdSer_sync ; + + // register readMeta + assign readMeta__D_IN = metaRF__D_OUT ; + assign readMeta__EN = CAN_FIRE_RL_wmrd_mesgBegin ; + + // register readyToPush + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + MUX_endOfMessage__write_1__SEL_1) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: readyToPush__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: readyToPush__D_IN = 1'b1; + MUX_endOfMessage__write_1__SEL_1: readyToPush__D_IN = 1'b0; + default: readyToPush__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign readyToPush__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[307:296] == 12'b01 || + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_doAbort ; + + // register readyToRequest + assign readyToRequest__D_IN = MUX_mesgLength__write_1__SEL_2 ; + assign readyToRequest__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register unrollCnt + assign unrollCnt__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + MUX_unrollCnt__write_1__VAL_1 : + MUX_unrollCnt__write_1__VAL_2 ; + assign unrollCnt__EN = + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + + // register valExpect : jluu removed because never used +// assign valExpect__D_IN = valExpect + 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ; +// assign valExpect__EN = +// WILL_FIRE_RL_wmwt_messagePushImprecise && +// (wsiS_reqFifo__D_OUT[307:296] != 12'b01 || +// wsiS_reqFifo__D_OUT[39:8] != 32'b00000000000000000000000000000000) ; + + // register wci_cEdge + assign wci_cEdge__D_IN = wci_reqF__D_OUT[36:34] ; + assign wci_cEdge__EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState__D_IN = wci_nState ; + assign wci_cState__EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg__D_IN = wci_ctlAckReg_1__whas ; + assign wci_ctlAckReg__EN = 1'b1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive__D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive__EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge__D_IN = + !MUX_wci_illegalEdge__write_1__SEL_1 && + MUX_wci_illegalEdge__write_1__VAL_2 ; + assign wci_illegalEdge__EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge__write_1__SEL_2 ; + + // register wci_nState + always@(wci_reqF__D_OUT) + begin + case (wci_reqF__D_OUT[36:34]) + 3'b000: wci_nState__D_IN = 3'b001; + 3'b001: wci_nState__D_IN = 3'b010; + 3'b010: wci_nState__D_IN = 3'b011; + default: wci_nState__D_IN = 3'b000; + endcase + end + assign wci_nState__EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState == 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && + (wci_cState == 3'b001 || wci_cState == 3'b011) || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState == 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && + (wci_cState == 3'b011 || wci_cState == 3'b010 || + wci_cState == 3'b001)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg__D_IN = + (wci_wciReq__wget[59:57] != 3'b000) ? + wci_reqF_countReg + 2'b01 : + wci_reqF_countReg - 2'b01 ; + assign wci_reqF_countReg__EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // register wci_respF_c_r + assign wci_respF_c_r__D_IN = + WILL_FIRE_RL_wci_respF_decCtr ? + MUX_wci_respF_c_r__write_1__VAL_1 : + MUX_wci_respF_c_r__write_1__VAL_2 ; + assign wci_respF_c_r__EN = + WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ; + + // register wci_respF_q_0 + assign wci_respF_q_0__EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0__write_1__VAL_1 or + MUX_wci_respF_q_0__write_1__SEL_2 or + MUX_wci_respF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_1; + MUX_wci_respF_q_0__write_1__SEL_2: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0__D_IN = wci_respF_q_1; + default: wci_respF_q_0__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_respF_q_1 + assign wci_respF_q_1__EN = + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1__write_1__VAL_1 or + MUX_wci_respF_q_1__write_1__SEL_2 or + MUX_wci_respF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1__D_IN = MUX_wci_respF_q_1__write_1__VAL_1; + MUX_wci_respF_q_1__write_1__SEL_2: + wci_respF_q_1__D_IN = MUX_wci_respF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1__D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_sFlagReg + assign wci_sFlagReg__D_IN = 1'b0 ; + assign wci_sFlagReg__EN = 1'b1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d__D_IN = 1'b0 ; + assign wci_sThreadBusy_d__EN = 1'b1 ; + + // register wmemiRdReq + assign wmemiRdReq__D_IN = wmemiRdReq + 32'b00000000000000000000000000000001 ; + assign wmemiRdReq__EN = WILL_FIRE_RL_delay_read_req ; + + // register wmemiRdResp + assign wmemiRdResp__D_IN = wmemiRdResp + 32'b00000000000000000000000000000001 ; + assign wmemiRdResp__EN = CAN_FIRE_RL_delay_read_resp ; + + // register wmemiWrReq + assign wmemiWrReq__D_IN = wmemiWrReq + 32'b00000000000000000000000000000001 ; + assign wmemiWrReq__EN = CAN_FIRE_RL_delay_write_req ; + + // register wmemi_busyWithMessage + assign wmemi_busyWithMessage__D_IN = 1'b0 ; + assign wmemi_busyWithMessage__EN = 1'b0 ; + + // register wmemi_dhF_c_r + assign wmemi_dhF_c_r__D_IN = + WILL_FIRE_RL_wmemi_dhF_decCtr ? + MUX_wmemi_dhF_c_r__write_1__VAL_1 : + MUX_wmemi_dhF_c_r__write_1__VAL_2 ; + assign wmemi_dhF_c_r__EN = + WILL_FIRE_RL_wmemi_dhF_decCtr || WILL_FIRE_RL_wmemi_dhF_incCtr ; + + // register wmemi_dhF_q_0 + always@(WILL_FIRE_RL_wmemi_dhF_both or + MUX_wmemi_dhF_q_0__write_1__VAL_1 or + MUX_wmemi_dhF_q_0__write_1__SEL_2 or + MUX_wmemi_dhF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmemi_dhF_decCtr or wmemi_dhF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_dhF_both: + wmemi_dhF_q_0__D_IN = MUX_wmemi_dhF_q_0__write_1__VAL_1; + MUX_wmemi_dhF_q_0__write_1__SEL_2: + wmemi_dhF_q_0__D_IN = MUX_wmemi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_dhF_decCtr: wmemi_dhF_q_0__D_IN = wmemi_dhF_q_1; + default: wmemi_dhF_q_0__D_IN = + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_dhF_q_0__EN = + WILL_FIRE_RL_wmemi_dhF_both || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b00 || + WILL_FIRE_RL_wmemi_dhF_decCtr ; + + // register wmemi_dhF_q_1 + always@(WILL_FIRE_RL_wmemi_dhF_both or + MUX_wmemi_dhF_q_1__write_1__VAL_1 or + MUX_wmemi_dhF_q_1__write_1__SEL_2 or + MUX_wmemi_dhF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmemi_dhF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_dhF_both: + wmemi_dhF_q_1__D_IN = MUX_wmemi_dhF_q_1__write_1__VAL_1; + MUX_wmemi_dhF_q_1__write_1__SEL_2: + wmemi_dhF_q_1__D_IN = MUX_wmemi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_dhF_decCtr: + wmemi_dhF_q_1__D_IN = 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + default: wmemi_dhF_q_1__D_IN = + 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_dhF_q_1__EN = + WILL_FIRE_RL_wmemi_dhF_both || + WILL_FIRE_RL_wmemi_dhF_incCtr && wmemi_dhF_c_r == 2'b01 || + WILL_FIRE_RL_wmemi_dhF_decCtr ; + + // register wmemi_errorSticky + assign wmemi_errorSticky__D_IN = 1'b0 ; + assign wmemi_errorSticky__EN = 1'b0 ; + + // register wmemi_operateD + assign wmemi_operateD__D_IN = wci_cState == 3'b010 ; + assign wmemi_operateD__EN = 1'b1 ; + + // register wmemi_peerIsReady + assign wmemi_peerIsReady__D_IN = 1'b1 ; + assign wmemi_peerIsReady__EN = 1'b1 ; + + // register wmemi_reqF_c_r + assign wmemi_reqF_c_r__D_IN = + WILL_FIRE_RL_wmemi_reqF_decCtr ? + MUX_wmemi_reqF_c_r__write_1__VAL_1 : + MUX_wmemi_reqF_c_r__write_1__VAL_2 ; + assign wmemi_reqF_c_r__EN = + WILL_FIRE_RL_wmemi_reqF_decCtr || + WILL_FIRE_RL_wmemi_reqF_incCtr ; + + // register wmemi_reqF_q_0 + always@(WILL_FIRE_RL_wmemi_reqF_both or + MUX_wmemi_reqF_q_0__write_1__VAL_1 or + MUX_wmemi_reqF_q_0__write_1__SEL_2 or + MUX_wmemi_reqF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmemi_reqF_decCtr or wmemi_reqF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_reqF_both: + wmemi_reqF_q_0__D_IN = MUX_wmemi_reqF_q_0__write_1__VAL_1; + MUX_wmemi_reqF_q_0__write_1__SEL_2: + wmemi_reqF_q_0__D_IN = MUX_wmemi_reqF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_0__D_IN = wmemi_reqF_q_1; + default: wmemi_reqF_q_0__D_IN = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_reqF_q_0__EN = + WILL_FIRE_RL_wmemi_reqF_both || + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b00 || + WILL_FIRE_RL_wmemi_reqF_decCtr ; + + // register wmemi_reqF_q_1 + always@(WILL_FIRE_RL_wmemi_reqF_both or + MUX_wmemi_reqF_q_1__write_1__VAL_1 or + MUX_wmemi_reqF_q_1__write_1__SEL_2 or + MUX_wmemi_reqF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmemi_reqF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmemi_reqF_both: + wmemi_reqF_q_1__D_IN = MUX_wmemi_reqF_q_1__write_1__VAL_1; + MUX_wmemi_reqF_q_1__write_1__SEL_2: + wmemi_reqF_q_1__D_IN = MUX_wmemi_reqF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmemi_reqF_decCtr: wmemi_reqF_q_1__D_IN = 52'h0AAAAAAAAAAAA; + default: wmemi_reqF_q_1__D_IN = + 52'hAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmemi_reqF_q_1__EN = + WILL_FIRE_RL_wmemi_reqF_both || + WILL_FIRE_RL_wmemi_reqF_incCtr && wmemi_reqF_c_r == 2'b01 || + WILL_FIRE_RL_wmemi_reqF_decCtr ; + + // register wmemi_statusR + assign wmemi_statusR__D_IN = + { wmemi_isReset__VAL, + !wmemi_peerIsReady, + !wmemi_operateD, + wmemi_errorSticky, + 3'b000, + wmemi_trafficSticky } ; + assign wmemi_statusR__EN = 1'b1 ; + + // register wmemi_trafficSticky + assign wmemi_trafficSticky__D_IN = 1'b1 ; + assign wmemi_trafficSticky__EN = wmemiM_SCmdAccept ; + + // register wrtDutyCount + assign wrtDutyCount__D_IN = wrtDutyCount + 3'b001 ; + assign wrtDutyCount__EN = CAN_FIRE_RL_delay_write_req ; + + // register wrtSerAddr + assign wrtSerAddr__D_IN = 32'h0 ; + assign wrtSerAddr__EN = 1'b0 ; + + // register wrtSerMeta + assign wrtSerMeta__D_IN = metaWF__D_OUT ; + assign wrtSerMeta__EN = CAN_FIRE_RL_wrtSer_begin ; + + // register wrtSerPos + assign wrtSerPos__D_IN = + WILL_FIRE_RL_wrtSer_body ? + MUX_wrtSerPos__write_1__VAL_1 : + MUX_wrtSerPos__write_1__VAL_2 ; + assign wrtSerPos__EN = + WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ; + + // register wrtSerStage + assign wrtSerStage__D_IN = + MUX_wrtSerStage__write_1__SEL_1 ? x__h19905[31:0] : metaWF__D_OUT ; + assign wrtSerStage__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b00 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b00 ; + + // register wrtSerStage_1 + assign wrtSerStage_1__D_IN = + MUX_wrtSerStage_1__write_1__SEL_1 ? + x__h19905[31:0] : + metaWF__D_OUT ; + assign wrtSerStage_1__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b01 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b01 ; + + // register wrtSerStage_2 + assign wrtSerStage_2__D_IN = + MUX_wrtSerStage_2__write_1__SEL_1 ? + x__h19905[31:0] : + metaWF__D_OUT ; + assign wrtSerStage_2__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b10 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b10 ; + + // register wrtSerStage_3 + assign wrtSerStage_3__D_IN = + MUX_wrtSerStage_3__write_1__SEL_1 ? + x__h19905[31:0] : + metaWF__D_OUT ; + assign wrtSerStage_3__EN = + WILL_FIRE_RL_wrtSer_body && wrtSerPos == 2'b11 || + WILL_FIRE_RL_wrtSer_begin && wrtSerPos == 2'b11 ; + + // register wrtSerUnroll + assign wrtSerUnroll__D_IN = + WILL_FIRE_RL_wrtSer_body ? + MUX_wrtSerUnroll__write_1__VAL_1 : + metaWF__D_OUT[20:5] ; + assign wrtSerUnroll__EN = + WILL_FIRE_RL_wrtSer_body || WILL_FIRE_RL_wrtSer_begin ; + + // register wsiM_burstKind + assign wsiM_burstKind__D_IN = + (wsiM_burstKind == 2'b00) ? + (wsiM_reqFifo_q_0[308] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiM_burstKind__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 && + (wsiM_burstKind == 2'b00 || + wsiM_burstKind == 2'b01 && wsiM_reqFifo_q_0[309] || + wsiM_burstKind == 2'b10 && wsiM_reqFifo_q_0[307:296] == 12'b01) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky__D_IN = 1'b0 ; + assign wsiM_errorSticky__EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount__D_IN = wsiM_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiM_iMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 && + wsiM_burstKind == 2'b10 && + wsiM_reqFifo_q_0[307:296] == 12'b01 ; + + // register wsiM_operateD + assign wsiM_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiM_operateD__EN = 1'b1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount__D_IN = wsiM_pMesgCount + 32'b00000000000000000000000000000001; + assign wsiM_pMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 && + wsiM_burstKind == 2'b01 && + wsiM_reqFifo_q_0[309] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady__D_IN = wsiM1_SReset_n ; + assign wsiM_peerIsReady__EN = 1'b1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r__D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_c_r__write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r__write_1__VAL_2 ; + assign wsiM_reqFifo_c_r__EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; + + // register wsiM_reqFifo_q_0 + assign wsiM_reqFifo_q_0__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_1; + MUX_wsiM_reqFifo_q_0__write_1__SEL_2: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0__D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0__D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_reqFifo_q_1 + assign wsiM_reqFifo_q_1__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_1__write_1__VAL_1; + MUX_wsiM_reqFifo_q_1__write_1__SEL_2: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1__D_IN = + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + default: wsiM_reqFifo_q_1__D_IN = + 313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d__D_IN = wsiM1_SThreadBusy ; + assign wsiM_sThreadBusy_d__EN = 1'b1 ; + + // register wsiM_statusR + assign wsiM_statusR__D_IN = + { wsiM_isReset__VAL, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'b00, + wsiM_sThreadBusy_d, + 1'b0, + wsiM_trafficSticky } ; + assign wsiM_statusR__EN = 1'b1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount__D_IN = wsiM_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiM_tBusyCount__EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky__D_IN = 1'b1 ; + assign wsiM_trafficSticky__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[312:310] == 3'b001 ; + + // register wsiS_burstKind + assign wsiS_burstKind__D_IN = + (wsiS_burstKind == 2'b00) ? + (wsiS_wsiReq__wget[308] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiS_burstKind__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'b00 || + wsiS_burstKind == 2'b01 && wsiS_wsiReq__wget[309] || + wsiS_burstKind == 2'b10 && wsiS_wsiReq__wget[307:296] == 12'b01) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky__D_IN = 1'b1 ; + assign wsiS_errorSticky__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo__FULL_N ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount__D_IN = wsiS_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_iMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b10 && + wsiS_wsiReq__wget[307:296] == 12'b01 ; + + // register wsiS_operateD + assign wsiS_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiS_operateD__EN = 1'b1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount__D_IN = wsiS_pMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_pMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b01 && + wsiS_wsiReq__wget[309] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady__D_IN = wsiS1_MReset_n ; + assign wsiS_peerIsReady__EN = 1'b1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg__D_IN = + CAN_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'b01 : + wsiS_reqFifo_countReg - 2'b01 ; + assign wsiS_reqFifo_countReg__EN = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // register wsiS_statusR + assign wsiS_statusR__EN = 1'b1 ; + assign wsiS_statusR__D_IN = + { wsiS_isReset__VAL, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'b00, + NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady, + 1'b0, + wsiS_trafficSticky } ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount__D_IN = wsiS_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiS_tBusyCount__EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky__D_IN = 1'b1 ; + assign wsiS_trafficSticky__EN = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiWordsRemain + assign wsiWordsRemain__D_IN = + MUX_mesgLength__write_1__SEL_2 ? + wsiS_reqFifo__D_OUT[307:296] : + MUX_wsiWordsRemain__write_1__VAL_2 ; + assign wsiWordsRemain__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[308] || + WILL_FIRE_RL_wmwt_messagePushPrecise ; + + // register zeroLengthMesg + assign zeroLengthMesg__D_IN = wsiS_reqFifo__D_OUT[39:8] == 32'b00000000000000000000000000000000 ; + assign zeroLengthMesg__EN = MUX_mesgLength__write_1__SEL_2 ; + + // submodule mesgRF_memory + assign mesgRF_memory__WEA = CAN_FIRE_RL_rdSer_body ; + assign mesgRF_memory__ADDRA = mesgRF_rWrPtr[9:0] ; + assign mesgRF_memory__WEB = 1'b0 ; + assign mesgRF_memory__ADDRB = + CAN_FIRE_RL_wmrd_mesgBodyResponse ? + x__h16052[9:0] : + mesgRF_rRdPtr[9:0] ; + assign mesgRF_memory__DIB = + 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign mesgRF_memory__ENA = 1'b1 ; + assign mesgRF_memory__ENB = 1'b1 ; + assign mesgRF_memory__DIA = x__h16160 ; + + // submodule mesgWF_memory + assign mesgWF_memory__ADDRA = mesgWF_rWrPtr[9:0] ; + assign mesgWF_memory__WEB = 1'b0 ; + assign mesgWF_memory__DIB = + 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; + assign mesgWF_memory__ENA = 1'b1 ; + assign mesgWF_memory__ENB = 1'b1 ; + assign mesgWF_memory__WEA = mesgWF_pwEnqueue__whas ; + assign mesgWF_memory__DIA = x__h15234 ; + assign mesgWF_memory__ADDRB = + CAN_FIRE_RL_wrtSer_body ? x__h15126[9:0] : mesgWF_rRdPtr[9:0] ; + + // submodule metaRF + always@(rdSerPos or + rdSerStage_3 or wide16Fb__D_OUT or rdSerStage_1 or rdSerStage_2) + begin + case (rdSerPos) + 2'b00: metaRF__D_IN = wide16Fb__D_OUT[31:0]; + 2'b01: metaRF__D_IN = rdSerStage_1; + 2'b10: metaRF__D_IN = rdSerStage_2; + 2'b11: metaRF__D_IN = rdSerStage_3; + endcase + end + assign metaRF__DEQ = CAN_FIRE_RL_wmrd_mesgBegin ; + assign metaRF__CLR = 1'b0 ; + assign metaRF__ENQ = CAN_FIRE_RL_rdSer_begin ; + + // submodule metaWF + assign metaWF__CLR = 1'b0 ; + assign metaWF__D_IN = + MUX_metaWF__enq_1__SEL_1 ? + MUX_metaWF__enq_1__VAL_1 : + MUX_metaWF__enq_1__VAL_1 ; + assign metaWF__ENQ = + WILL_FIRE_RL_wmwt_messageFinalize && impreciseBurst || + WILL_FIRE_RL_wmwt_requestPrecise ; + assign metaWF__DEQ = CAN_FIRE_RL_wrtSer_begin ; + + // submodule wci_reqF + assign wci_reqF__D_IN = wci_wciReq__wget ; + assign wci_reqF__DEQ = wci_reqF_r_deq__whas ; + assign wci_reqF__ENQ = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF__CLR = 1'b0 ; + + // submodule wide16Fa + assign wide16Fa__DEQ = CAN_FIRE_RL_delay_write_req ; + assign wide16Fa__CLR = 1'b0 ; + assign wide16Fa__D_IN = + MUX_wide16Fa__enq_1__SEL_1 ? + MUX_wide16Fa__enq_1__VAL_1 : + MUX_wide16Fa__enq_1__VAL_2 ; + assign wide16Fa__ENQ = + WILL_FIRE_RL_wrtSer_begin && + (wrtSerPos == 2'b11 || metaWF__D_OUT[23:0] == 24'b000000000000000000000000) || + WILL_FIRE_RL_wrtSer_body && + (wrtSerPos == 2'b11 || wrtSerUnroll == 16'b0000000000000001) ; + + // submodule wide16Fb + assign wide16Fb__D_IN = wmemi_respF__D_OUT[127:0] ; + assign wide16Fb__ENQ = CAN_FIRE_RL_delay_read_resp ; + assign wide16Fb__CLR = 1'b0 ; + assign wide16Fb__DEQ = + MUX_rdSerEmpty__write_1__PSEL_1 && + (rdSerEmpty || rdSerPos == 2'b00) ; + + // submodule wmemi_respF + assign wmemi_respF__D_IN = wmemi_wmemiResponse__wget ; + assign wmemi_respF__DEQ = CAN_FIRE_RL_delay_read_resp ; + assign wmemi_respF__ENQ = CAN_FIRE_RL_wmemi_respAdvance ; + assign wmemi_respF__CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo__D_IN = wsiS_wsiReq__wget ; + assign wsiS_reqFifo__ENQ = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo__CLR = 1'b0 ; + assign wsiS_reqFifo__DEQ = wsiS_reqFifo_r_deq__whas ; + + // remaining internal signals + assign IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_mesgWF_w_ETC___d354 = + { (wrtSerPos == 2'b10) ? 32'h0 : x__h19905[31:0], + (wrtSerPos == 2'b10) ? x__h19905[31:0] : wrtSerStage_2, + wrtSerStage_1, + wrtSerStage } ; + assign IF_wrtSerPos_11_EQ_2_14_THEN_0x0_ELSE_metaWF_f_ETC___d377 = + { (wrtSerPos == 2'b10) ? 32'h0 : metaWF__D_OUT, + (wrtSerPos == 2'b10) ? metaWF__D_OUT : wrtSerStage_2, + wrtSerStage_1, + wrtSerStage } ; + assign NOT_dlyWordsStored_value_13_SLE_0_64_65_AND_NO_ETC___d272 = + (dlyWordsStored_value ^ 20'h80000) > 20'b10000000000000000000 && + dlyHoldoffBytes >= bytesWritten && + dlyHoldoffCycles >= cyclesPassed ; + assign NOT_mesgRF_rRdPtr_52_PLUS_512_93_EQ_mesgRF_rWr_ETC___d208 = + mesgRF_rRdPtr + 11'b01000000000 != mesgRF_rWrPtr && + (!rdSerEmpty && rdSerPos != 2'b00 || wide16Fb__EMPTY_N) ; + assign NOT_wsiS_reqFifo_countReg_96_ULE_1_97___d698 = + wsiS_reqFifo_countReg > 2'b01 ; + assign _dor1bytesWritten__EN_write = + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign addr__h20994 = { 12'b00, x__h21052 } ; + assign addr__h21166 = { 12'b00, x__h21211 } ; + assign mesg__h22346 = mesgRF_wDataOut__wget ; + assign metaRF_RDY_enq__41_AND_NOT_rdSerEmpty_96_97_AN_ETC___d242 = + metaRF__FULL_N && + (!rdSerEmpty && rdSerPos != 2'b00 || wide16Fb__EMPTY_N) ; + assign metaWF_RDY_deq__58_AND_NOT_wrtSerPos_11_EQ_3_1_ETC___d365 = + metaWF__EMPTY_N && + (wrtSerPos != 2'b11 && metaWF__D_OUT[23:0] != 24'b000000000000000000000000 || + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904) ; + assign mlp1__h17953 = MUX_mesgLengthSoFar__write_1__VAL_2 ; + assign rdat__h21847 = { 8'b00000000, x__h21850 } ; + assign rdat__h22030 = { 12'b00, dlyWordsStored_value } ; + assign rdat__h22038 = { 24'b000000000000000000000000, dlyReadCredit_value } ; + assign rdat__h22046 = { 12'b00, dlyWAG } ; + assign rdat__h22054 = { 12'b00, dlyRAG } ; + assign v__h22720 = metaRF__D_IN ; + assign wci_cState_9_EQ_2_0_AND_dlyCtrl_4_BITS_3_TO_0__ETC___d397 = + wci_cState == 3'b010 && dlyCtrl[3:0] == 4'h7 && mesgLength[14] && + !doAbort && + (preciseBurst && wsiWordsRemain == 12'b00 || + impreciseBurst && endOfMessage) ; + assign wrtSerPos_11_PLUS_1___d1014 = wrtSerPos + 2'b01 ; + assign x1__h19969 = { 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, x__h19905[31:0] } ; + assign x1__h19978 = { 64'b0000000000000000000000000000000000000000000000000000000000000000, x__h19905[31:0], wrtSerStage } ; + assign x1__h20492 = { 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, metaWF__D_OUT } ; + assign x1__h20501 = { 64'b0000000000000000000000000000000000000000000000000000000000000000, metaWF__D_OUT, wrtSerStage } ; + assign x1_length__h17254 = { 10'b0000000000, x__h17298 } ; + assign x1_opcode__h17253 = opcode[8] ? opcode[7:0] : 8'b00000000 ; + assign x__h15126 = mesgWF_rRdPtr + 11'b1 ; + assign x__h15234 = + mesgWF_pwEnqueue__whas ? wsiS_reqFifo__D_OUT[295:40] : 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; + assign x__h16052 = mesgRF_rRdPtr + 11'b1 ; + assign x__h16160 = CAN_FIRE_RL_rdSer_body ? mesgRF_wDataIn__wget : 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; + assign x__h17298 = mesgLength[14] ? mesgLength[13:0] : 14'b00000000000000 ; + assign x__h19905 = mesgWF_wDataOut__wget ; + assign x__h21052 = { dlyRAG, 4'h0 } ; + assign x__h21211 = { dlyWAG, 4'h0 } ; + assign x__h21850 = { wmemi_statusR, wsiS_statusR, wsiM_statusR } ; + assign x_burstLength__h22437 = + (readMeta[23:0] == 24'b000000000000000000000000) ? 12'b01 : readMeta[16:5] ; + assign x_byteEn__h22438 = (readMeta[23:0] == 24'b000000000000000000000000) ? 32'b00000000000000000000000000000000 : 32'hFFFFFFFF ; + always@(wci_reqF__D_OUT or + dlyCtrl or + dlyHoldoffBytes or + dlyHoldoffCycles or + mesgWtCount or + mesgRdCount or + bytesWritten or + rdat__h21847 or + wsiS_extStatusW__wget or + wsiM_extStatusW__wget or + wmemiWrReq or + wmemiRdReq or + wmemiRdResp or + rdat__h22030 or rdat__h22038 or rdat__h22046 or rdat__h22054) + begin + case (wci_reqF__D_OUT[51:32]) + 20'h0: x_data__h21804 = dlyCtrl; + 20'h00004: x_data__h21804 = dlyHoldoffBytes; + 20'h00008: x_data__h21804 = dlyHoldoffCycles; + 20'h0000C: x_data__h21804 = mesgWtCount; + 20'h00010: x_data__h21804 = mesgRdCount; + 20'h00014: x_data__h21804 = bytesWritten; + 20'h00018: x_data__h21804 = rdat__h21847; + 20'h0001C: x_data__h21804 = 32'b00000000000000000000000000000000; + 20'h00020: x_data__h21804 = wsiS_extStatusW__wget[95:64]; + 20'h00024: x_data__h21804 = wsiS_extStatusW__wget[63:32]; + 20'h00028: x_data__h21804 = wsiS_extStatusW__wget[31:0]; + 20'h0002C: x_data__h21804 = wsiM_extStatusW__wget[95:64]; + 20'h00030: x_data__h21804 = wsiM_extStatusW__wget[63:32]; + 20'h00034: x_data__h21804 = wsiM_extStatusW__wget[31:0]; + 20'h00038: x_data__h21804 = wmemiWrReq; + 20'h0003C: x_data__h21804 = wmemiRdReq; + 20'h00040: x_data__h21804 = wmemiRdResp; + 20'h00044: x_data__h21804 = rdat__h22030; + 20'h00048: x_data__h21804 = rdat__h22038; + 20'h0004C: x_data__h21804 = rdat__h22046; + 20'h00050: x_data__h21804 = rdat__h22054; + default: x_data__h21804 = 32'b00000000000000000000000000000000; + endcase + end + always@(wrtSerPos or wide16Fa__FULL_N) + begin + case (wrtSerPos) + // 2'b00, 2'b01, 2'b10 + 2'b10: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wide16Fa__FULL_N; + 2'b00: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wide16Fa__FULL_N; + 2'b01: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wide16Fa__FULL_N; + 2'b11: + IF_wrtSerPos_11_EQ_0_12_OR_wrtSerPos_11_EQ_1_1_ETC___d904 = + wrtSerPos != 2'b11 || wide16Fa__FULL_N; + endcase + end + always@(wrtSerPos) + begin + case (wrtSerPos) + // 2'b00, 2'b01, 2'b10, 2'b11: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b00: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b01: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b10: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + 2'b11: CASE_wrtSerPos_0b1_0_1_1_1_2_1_3_0b1__q1 = 1'b1; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (!wciS0_MReset_n) + begin + abortCount <= 32'b00000000000000000000000000000000; + blockDelayWrite <= 1'b0; + bytesRead <= 32'b00; + bytesWritten <= 32'b00000000000000000000000000000000; + cyclesPassed <= 32'b00000000000000000000000000000000; + dlyCtrl <= dlyCtrlInit; + dlyHoldoffBytes <= 32'b00000000000000000000000000000000; + dlyHoldoffCycles <= 32'b00000000000000000000000000000000; + dlyRAG <= 20'b00000000000000000000; + dlyReadCredit_value <= 8'b00000000; + dlyWAG <= 20'b00000000000000000000; + dlyWordsStored_value <= 20'b00000000000000000000; + doAbort <= 1'b0; + endOfMessage <= 1'b0; +// errCount <= 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + impreciseBurst <= 1'b0; + mesgLength <= 15'b010101010101010; + mesgLengthSoFar <= 14'b00000000000000; + mesgRF_rCache <= + 268'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mesgRF_rRdPtr <= 11'b0; + mesgRF_rWrPtr <= 11'b0; + mesgRdCount <= 32'b00000000000000000000000000000000; + mesgReqValid <= 1'b0; + mesgWF_rCache <= + 268'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + mesgWF_rRdPtr <= 11'b0; + mesgWF_rWrPtr <= 11'b0; + mesgWtCount <= 32'b00000000000000000000000000000000; + opcode <= 9'b010101010; + preciseBurst <= 1'b0; + rdSerAddr <= 32'b00000000000000000000000000000000; + rdSerEmpty <= 1'b1; + rdSerPos <= 2'b00; + rdSerUnroll <= 16'b0000000000000000; + rdSyncWord <= 1'b0; + readyToPush <= 1'b0; + readyToRequest <= 1'b0; + unrollCnt <= 16'b0000000000000000; +// valExpect <= 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + wci_cEdge <= 3'b111; + wci_cState <= 3'b000; + wci_ctlAckReg <= 1'b0; + wci_ctlOpActive <= 1'b0; + wci_illegalEdge <= 1'b0; + wci_nState <= 3'b000; + wci_reqF_countReg <= 2'b00; + wci_respF_c_r <= 2'b00; + wci_respF_q_0 <= 34'h0AAAAAAAA; + wci_respF_q_1 <= 34'h0AAAAAAAA; + wci_sFlagReg <= 1'b0; + wci_sThreadBusy_d <= 1'b1; + wmemiRdReq <= 32'b00000000000000000000000000000000; + wmemiRdResp <= 32'b00000000000000000000000000000000; + wmemiWrReq <= 32'b00000000000000000000000000000000; + wmemi_busyWithMessage <= 1'b0; + wmemi_dhF_c_r <= 2'b00; + wmemi_dhF_q_0 <= + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_dhF_q_1 <= + 146'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; + wmemi_errorSticky <= 1'b0; + wmemi_operateD <= 1'b0; + wmemi_peerIsReady <= 1'b1; + wmemi_reqF_c_r <= 2'b00; + wmemi_reqF_q_0 <= 52'h0AAAAAAAAAAAA; + wmemi_reqF_q_1 <= 52'h0AAAAAAAAAAAA; + wmemi_trafficSticky <= 1'b0; + wrtDutyCount <= 3'b000; + wrtSerAddr <= 32'b00000000000000000000000000000000; + wrtSerPos <= 2'b00; + wrtSerUnroll <= 16'b0000000000000000; + wsiM_burstKind <= 2'b00; + wsiM_errorSticky <= 1'b0; + wsiM_iMesgCount <= 32'b00000000000000000000000000000000; + wsiM_operateD <= 1'b0; + wsiM_pMesgCount <= 32'b00000000000000000000000000000000; + wsiM_peerIsReady <= 1'b0; + wsiM_reqFifo_c_r <= 2'b00; + wsiM_reqFifo_q_0 <= + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_reqFifo_q_1 <= + 313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00; + wsiM_sThreadBusy_d <= 1'b1; + wsiM_tBusyCount <= 32'b00000000000000000000000000000000; + wsiM_trafficSticky <= 1'b0; + wsiS_burstKind <= 2'b00; + wsiS_errorSticky <= 1'b0; + wsiS_iMesgCount <= 32'b00000000000000000000000000000000; + wsiS_operateD <= 1'b0; + wsiS_pMesgCount <= 32'b00000000000000000000000000000000; + wsiS_peerIsReady <= 1'b0; + wsiS_reqFifo_countReg <= 2'b00; + wsiS_tBusyCount <= 32'b00000000000000000000000000000000; + wsiS_trafficSticky <= 1'b0; + wsiWordsRemain <= 12'b00; + zeroLengthMesg <= 1'b0; + end + else + begin + if (abortCount__EN) + abortCount <= abortCount__D_IN; + if (blockDelayWrite__EN) + blockDelayWrite <= blockDelayWrite__D_IN; + if (bytesRead__EN) bytesRead <= bytesRead__D_IN; + if (bytesWritten__EN) + bytesWritten <= bytesWritten__D_IN; + if (cyclesPassed__EN) + cyclesPassed <= cyclesPassed__D_IN; + if (dlyCtrl__EN) dlyCtrl <= dlyCtrl__D_IN; + if (dlyHoldoffBytes__EN) + dlyHoldoffBytes <= dlyHoldoffBytes__D_IN; + if (dlyHoldoffCycles__EN) + dlyHoldoffCycles <= dlyHoldoffCycles__D_IN; + if (dlyRAG__EN) dlyRAG <= dlyRAG__D_IN; + if (dlyReadCredit_value__EN) + dlyReadCredit_value <= + dlyReadCredit_value__D_IN; + if (dlyWAG__EN) dlyWAG <= dlyWAG__D_IN; + if (dlyWordsStored_value__EN) + dlyWordsStored_value <= + dlyWordsStored_value__D_IN; + if (doAbort__EN) doAbort <= doAbort__D_IN; + if (endOfMessage__EN) + endOfMessage <= endOfMessage__D_IN; +// if (errCount__EN) errCount <= errCount__D_IN; + if (impreciseBurst__EN) + impreciseBurst <= impreciseBurst__D_IN; + if (mesgLength__EN) + mesgLength <= mesgLength__D_IN; + if (mesgLengthSoFar__EN) + mesgLengthSoFar <= mesgLengthSoFar__D_IN; + if (mesgRF_rCache__EN) + mesgRF_rCache <= mesgRF_rCache__D_IN; + if (mesgRF_rRdPtr__EN) + mesgRF_rRdPtr <= mesgRF_rRdPtr__D_IN; + if (mesgRF_rWrPtr__EN) + mesgRF_rWrPtr <= mesgRF_rWrPtr__D_IN; + if (mesgRdCount__EN) + mesgRdCount <= mesgRdCount__D_IN; + if (mesgReqValid__EN) + mesgReqValid <= mesgReqValid__D_IN; + if (mesgWF_rCache__EN) + mesgWF_rCache <= mesgWF_rCache__D_IN; + if (mesgWF_rRdPtr__EN) + mesgWF_rRdPtr <= mesgWF_rRdPtr__D_IN; + if (mesgWF_rWrPtr__EN) + mesgWF_rWrPtr <= mesgWF_rWrPtr__D_IN; + if (mesgWtCount__EN) + mesgWtCount <= mesgWtCount__D_IN; + if (opcode__EN) opcode <= opcode__D_IN; + if (preciseBurst__EN) + preciseBurst <= preciseBurst__D_IN; + if (rdSerAddr__EN) rdSerAddr <= rdSerAddr__D_IN; + if (rdSerEmpty__EN) + rdSerEmpty <= rdSerEmpty__D_IN; + if (rdSerPos__EN) rdSerPos <= rdSerPos__D_IN; + if (rdSerUnroll__EN) + rdSerUnroll <= rdSerUnroll__D_IN; + if (rdSyncWord__EN) + rdSyncWord <= rdSyncWord__D_IN; + if (readyToPush__EN) + readyToPush <= readyToPush__D_IN; + if (readyToRequest__EN) + readyToRequest <= readyToRequest__D_IN; + if (unrollCnt__EN) unrollCnt <= unrollCnt__D_IN; +// if (valExpect__EN) valExpect <= valExpect__D_IN; + if (wci_cEdge__EN) wci_cEdge <= wci_cEdge__D_IN; + if (wci_cState__EN) + wci_cState <= wci_cState__D_IN; + if (wci_ctlAckReg__EN) + wci_ctlAckReg <= wci_ctlAckReg__D_IN; + if (wci_ctlOpActive__EN) + wci_ctlOpActive <= wci_ctlOpActive__D_IN; + if (wci_illegalEdge__EN) + wci_illegalEdge <= wci_illegalEdge__D_IN; + if (wci_nState__EN) + wci_nState <= wci_nState__D_IN; + if (wci_reqF_countReg__EN) + wci_reqF_countReg <= wci_reqF_countReg__D_IN; + if (wci_respF_c_r__EN) + wci_respF_c_r <= wci_respF_c_r__D_IN; + if (wci_respF_q_0__EN) + wci_respF_q_0 <= wci_respF_q_0__D_IN; + if (wci_respF_q_1__EN) + wci_respF_q_1 <= wci_respF_q_1__D_IN; + if (wci_sFlagReg__EN) + wci_sFlagReg <= wci_sFlagReg__D_IN; + if (wci_sThreadBusy_d__EN) + wci_sThreadBusy_d <= wci_sThreadBusy_d__D_IN; + if (wmemiRdReq__EN) + wmemiRdReq <= wmemiRdReq__D_IN; + if (wmemiRdResp__EN) + wmemiRdResp <= wmemiRdResp__D_IN; + if (wmemiWrReq__EN) + wmemiWrReq <= wmemiWrReq__D_IN; + if (wmemi_busyWithMessage__EN) + wmemi_busyWithMessage <= + wmemi_busyWithMessage__D_IN; + if (wmemi_dhF_c_r__EN) + wmemi_dhF_c_r <= wmemi_dhF_c_r__D_IN; + if (wmemi_dhF_q_0__EN) + wmemi_dhF_q_0 <= wmemi_dhF_q_0__D_IN; + if (wmemi_dhF_q_1__EN) + wmemi_dhF_q_1 <= wmemi_dhF_q_1__D_IN; + if (wmemi_errorSticky__EN) + wmemi_errorSticky <= wmemi_errorSticky__D_IN; + if (wmemi_operateD__EN) + wmemi_operateD <= wmemi_operateD__D_IN; + if (wmemi_peerIsReady__EN) + wmemi_peerIsReady <= wmemi_peerIsReady__D_IN; + if (wmemi_reqF_c_r__EN) + wmemi_reqF_c_r <= wmemi_reqF_c_r__D_IN; + if (wmemi_reqF_q_0__EN) + wmemi_reqF_q_0 <= wmemi_reqF_q_0__D_IN; + if (wmemi_reqF_q_1__EN) + wmemi_reqF_q_1 <= wmemi_reqF_q_1__D_IN; + if (wmemi_trafficSticky__EN) + wmemi_trafficSticky <= + wmemi_trafficSticky__D_IN; + if (wrtDutyCount__EN) + wrtDutyCount <= wrtDutyCount__D_IN; + if (wrtSerAddr__EN) + wrtSerAddr <= wrtSerAddr__D_IN; + if (wrtSerPos__EN) wrtSerPos <= wrtSerPos__D_IN; + if (wrtSerUnroll__EN) + wrtSerUnroll <= wrtSerUnroll__D_IN; + if (wsiM_burstKind__EN) + wsiM_burstKind <= wsiM_burstKind__D_IN; + if (wsiM_errorSticky__EN) + wsiM_errorSticky <= wsiM_errorSticky__D_IN; + if (wsiM_iMesgCount__EN) + wsiM_iMesgCount <= wsiM_iMesgCount__D_IN; + if (wsiM_operateD__EN) + wsiM_operateD <= wsiM_operateD__D_IN; + if (wsiM_pMesgCount__EN) + wsiM_pMesgCount <= wsiM_pMesgCount__D_IN; + if (wsiM_peerIsReady__EN) + wsiM_peerIsReady <= wsiM_peerIsReady__D_IN; + if (wsiM_reqFifo_c_r__EN) + wsiM_reqFifo_c_r <= wsiM_reqFifo_c_r__D_IN; + if (wsiM_reqFifo_q_0__EN) + wsiM_reqFifo_q_0 <= wsiM_reqFifo_q_0__D_IN; + if (wsiM_reqFifo_q_1__EN) + wsiM_reqFifo_q_1 <= wsiM_reqFifo_q_1__D_IN; + if (wsiM_sThreadBusy_d__EN) + wsiM_sThreadBusy_d <= wsiM_sThreadBusy_d__D_IN; + if (wsiM_tBusyCount__EN) + wsiM_tBusyCount <= wsiM_tBusyCount__D_IN; + if (wsiM_trafficSticky__EN) + wsiM_trafficSticky <= wsiM_trafficSticky__D_IN; + if (wsiS_burstKind__EN) + wsiS_burstKind <= wsiS_burstKind__D_IN; + if (wsiS_errorSticky__EN) + wsiS_errorSticky <= wsiS_errorSticky__D_IN; + if (wsiS_iMesgCount__EN) + wsiS_iMesgCount <= wsiS_iMesgCount__D_IN; + if (wsiS_operateD__EN) + wsiS_operateD <= wsiS_operateD__D_IN; + if (wsiS_pMesgCount__EN) + wsiS_pMesgCount <= wsiS_pMesgCount__D_IN; + if (wsiS_peerIsReady__EN) + wsiS_peerIsReady <= wsiS_peerIsReady__D_IN; + if (wsiS_reqFifo_countReg__EN) + wsiS_reqFifo_countReg <= + wsiS_reqFifo_countReg__D_IN; + if (wsiS_tBusyCount__EN) + wsiS_tBusyCount <= wsiS_tBusyCount__D_IN; + if (wsiS_trafficSticky__EN) + wsiS_trafficSticky <= wsiS_trafficSticky__D_IN; + if (wsiWordsRemain__EN) + wsiWordsRemain <= wsiWordsRemain__D_IN; + if (zeroLengthMesg__EN) + zeroLengthMesg <= zeroLengthMesg__D_IN; + end + if (rdSerMeta__EN) rdSerMeta <= rdSerMeta__D_IN; + if (rdSerStage__EN) rdSerStage <= rdSerStage__D_IN; + if (rdSerStage_1__EN) + rdSerStage_1 <= rdSerStage_1__D_IN; + if (rdSerStage_2__EN) + rdSerStage_2 <= rdSerStage_2__D_IN; + if (rdSerStage_3__EN) + rdSerStage_3 <= rdSerStage_3__D_IN; + if (readMeta__EN) readMeta <= readMeta__D_IN; + if (wmemi_statusR__EN) + wmemi_statusR <= wmemi_statusR__D_IN; + if (wrtSerMeta__EN) wrtSerMeta <= wrtSerMeta__D_IN; + if (wrtSerStage__EN) wrtSerStage <= wrtSerStage__D_IN; + if (wrtSerStage_1__EN) + wrtSerStage_1 <= wrtSerStage_1__D_IN; + if (wrtSerStage_2__EN) + wrtSerStage_2 <= wrtSerStage_2__D_IN; + if (wrtSerStage_3__EN) + wrtSerStage_3 <= wrtSerStage_3__D_IN; + if (wsiM_statusR__EN) + wsiM_statusR <= wsiM_statusR__D_IN; + if (wsiS_statusR__EN) + wsiS_statusR <= wsiS_statusR__D_IN; + end + + // handling of system tasks + + +endmodule // mkDelayWorker32B + + + + +module ResetToBool (RST, VAL); + +input RST; +output VAL; +reg VAL; + +always @ (RST or VAL) +begin + +if (RST == 1) +VAL=1'b0; + +end +endmodule + + +module arSRLFIFO_a (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [31:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [31:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_a fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + +module arSRLFIFO_b (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [31:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [31:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_b fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + +module arSRLFIFO_c (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [127:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [127:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_c fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + + +module arSRLFIFO_d (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [127:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [127:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_d fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + +module SizedFIFO_a (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [59:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [59:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_f fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + +module SizedFIFO_b (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [312:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [312:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_g fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + +module SizedFIFO_x (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [130:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [130:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_x fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v b/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v new file mode 100755 index 000000000..505c46b30 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v @@ -0,0 +1,1494 @@ +// +// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24) +// +// On Tue Jun 8 18:41:53 EDT 2010 +// +// +// Ports: +// Name I/O size props +// RDY_iport0_put O 1 +// RDY_iport1_put O 1 +// oport_get O 153 +// RDY_oport_get O 1 +// CLK I 1 clock +// RST_N I 1 reset +// iport0_put I 153 +// iport1_put I 153 +// EN_iport0_put I 1 +// EN_iport1_put I 1 +// EN_oport_get I 1 +// +// No combinational paths from inputs to outputs +// +// + + + +module mkPktMerge(CLK, + RST_N, + + iport0_put, + EN_iport0_put, + RDY_iport0_put, + + iport1_put, + EN_iport1_put, + RDY_iport1_put, + + EN_oport_get, + oport_get, + RDY_oport_get); + input CLK; + input RST_N; + + // action method iport0_put + input [152 : 0] iport0_put; + input EN_iport0_put; + output RDY_iport0_put; + + // action method iport1_put + input [152 : 0] iport1_put; + input EN_iport1_put; + output RDY_iport1_put; + + // actionvalue method oport_get + input EN_oport_get; + output [152 : 0] oport_get; + output RDY_oport_get; + + // signals for module outputs + wire [152 : 0] oport_get; + wire RDY_iport0_put, RDY_iport1_put, RDY_oport_get; + + // register fi0Active + reg fi0Active; + wire fi0Active__D_IN; + wire fi0Active__EN; + + // register fi0HasPrio + reg fi0HasPrio; + reg fi0HasPrio__D_IN; + wire fi0HasPrio__EN; + + // register fi1Active + reg fi1Active; + wire fi1Active__D_IN, fi1Active__EN; + + // ports of submodule fi0 + wire [152 : 0] fi0__D_IN, fi0__D_OUT; + wire fi0__CLR, fi0__DEQ, fi0__EMPTY_N, fi0__ENQ, fi0__FULL_N; + + // ports of submodule fi1 + wire [152 : 0] fi1__D_IN, fi1__D_OUT; + wire fi1__CLR, fi1__DEQ, fi1__EMPTY_N, fi1__ENQ, fi1__FULL_N; + + // ports of submodule fo + reg [152 : 0] fo__D_IN; + wire [152 : 0] fo__D_OUT; + wire fo__CLR, fo__DEQ, fo__EMPTY_N, fo__ENQ, fo__FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_arbitrate, + CAN_FIRE_RL_fi0_advance, + CAN_FIRE_RL_fi1_advance, + CAN_FIRE_iport0_put, + CAN_FIRE_iport1_put, + CAN_FIRE_oport_get, + WILL_FIRE_RL_arbitrate, + WILL_FIRE_RL_fi0_advance, + WILL_FIRE_RL_fi1_advance, + WILL_FIRE_iport0_put, + WILL_FIRE_iport1_put, + WILL_FIRE_oport_get; + + // inputs to muxes for submodule ports + wire [152 : 0] MUX_fo__enq_1__VAL_1; + wire MUX_fi0Active__write_1__SEL_1, + MUX_fi0Active__write_1__VAL_1, + MUX_fi1Active__write_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h679; + wire fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10; + + // action method iport0_put + assign RDY_iport0_put = fi0__FULL_N ; + assign CAN_FIRE_iport0_put = fi0__FULL_N ; + assign WILL_FIRE_iport0_put = EN_iport0_put ; + + // action method iport1_put + assign RDY_iport1_put = fi1__FULL_N ; + assign CAN_FIRE_iport1_put = fi1__FULL_N ; + assign WILL_FIRE_iport1_put = EN_iport1_put ; + + // actionvalue method oport_get + assign oport_get = fo__D_OUT ; + assign RDY_oport_get = fo__EMPTY_N ; + assign CAN_FIRE_oport_get = fo__EMPTY_N ; + assign WILL_FIRE_oport_get = EN_oport_get ; + + // submodule fi0 + arSRLFIFO_a fi0 (.CLK(CLK), + .RST_N(RST_N), + .D_IN(fi0__D_IN), + .ENQ(fi0__ENQ), + .DEQ(fi0__DEQ), + .CLR(fi0__CLR), + .D_OUT(fi0__D_OUT), + .EMPTY_N(fi0__EMPTY_N), + .FULL_N(fi0__FULL_N)); + + // submodule fi1 + arSRLFIFO_b fi1 + (.CLK(CLK), + .RST_N(RST_N), + .D_IN(fi1__D_IN), + .ENQ(fi1__ENQ), + .DEQ(fi1__DEQ), + .CLR(fi1__CLR), + .D_OUT(fi1__D_OUT), + .EMPTY_N(fi1__EMPTY_N), + .FULL_N(fi1__FULL_N)); + + // submodule fo + arSRLFIFO_c fo + (.CLK(CLK), + .RST_N(RST_N), + .D_IN(fo__D_IN), + .ENQ(fo__ENQ), + .DEQ(fo__DEQ), + .CLR(fo__CLR), + .D_OUT(fo__D_OUT), + .EMPTY_N(fo__EMPTY_N), + .FULL_N(fo__FULL_N)); + + // rule RL_arbitrate + assign CAN_FIRE_RL_arbitrate = + fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10 && + fi0__EMPTY_N && + fi1__EMPTY_N && + !fi0Active && + !fi1Active ; + assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ; + + // rule RL_fi0_advance + assign CAN_FIRE_RL_fi0_advance = fi0__EMPTY_N && fo__FULL_N && !fi1Active ; + assign WILL_FIRE_RL_fi0_advance = + CAN_FIRE_RL_fi0_advance && !WILL_FIRE_RL_arbitrate ; + + // rule RL_fi1_advance + assign CAN_FIRE_RL_fi1_advance = fi1__EMPTY_N && fo__FULL_N && !fi0Active ; + assign WILL_FIRE_RL_fi1_advance = + CAN_FIRE_RL_fi1_advance && !WILL_FIRE_RL_fi0_advance && + !WILL_FIRE_RL_arbitrate ; + + // inputs to muxes for submodule ports + assign MUX_fi0Active__write_1__SEL_1 = WILL_FIRE_RL_arbitrate && fi0HasPrio ; + assign MUX_fi1Active__write_1__SEL_1 = + WILL_FIRE_RL_arbitrate && !fi0HasPrio ; + assign MUX_fi0Active__write_1__VAL_1 = + fi0HasPrio ? !fi0__D_OUT[151] : !fi1__D_OUT[151] ; + assign MUX_fo__enq_1__VAL_1 = fi0HasPrio ? fi0__D_OUT : fi1__D_OUT ; + + // register fi0Active + assign fi0Active__D_IN = + MUX_fi0Active__write_1__SEL_1 ? + MUX_fi0Active__write_1__VAL_1 : + !fi0__D_OUT[151] ; + assign fi0Active__EN = + WILL_FIRE_RL_arbitrate && fi0HasPrio || + WILL_FIRE_RL_fi0_advance ; + + // register fi0HasPrio + always@(WILL_FIRE_RL_arbitrate or + fi0HasPrio or WILL_FIRE_RL_fi0_advance or WILL_FIRE_RL_fi1_advance) + begin + // case (1'b1) // synopsys parallel_case + // WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio; + // WILL_FIRE_RL_fi0_advance: fi0HasPrio__D_IN = 1'd0; + // WILL_FIRE_RL_fi1_advance: fi0HasPrio__D_IN = 1'd1; + //case (1'b1) // synopsys parallel_case + // WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio; + fi0HasPrio__D_IN = !fi0HasPrio; + // WILL_FIRE_RL_fi0_advance: fi0HasPrio__D_IN = 1'd0; + // WILL_FIRE_RL_fi1_advance: fi0HasPrio__D_IN = 1'd1; + +// endcase + //endcase + end + assign fi0HasPrio__EN = + WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance || + WILL_FIRE_RL_fi1_advance ; + + // register fi1Active + assign fi1Active__D_IN = + MUX_fi1Active__write_1__SEL_1 ? + MUX_fi0Active__write_1__VAL_1 : + !fi1__D_OUT[151] ; + assign fi1Active__EN = + WILL_FIRE_RL_arbitrate && !fi0HasPrio || + WILL_FIRE_RL_fi1_advance ; + + // submodule fi0 + assign fi0__D_IN = iport0_put ; + assign fi0__DEQ = + WILL_FIRE_RL_arbitrate && fi0HasPrio || + WILL_FIRE_RL_fi0_advance ; + assign fi0__ENQ = EN_iport0_put ; + assign fi0__CLR = 1'b0 ; + + // submodule fi1 + assign fi1__D_IN = iport1_put ; + assign fi1__DEQ = + WILL_FIRE_RL_arbitrate && !fi0HasPrio || + WILL_FIRE_RL_fi1_advance ; + assign fi1__ENQ = EN_iport1_put ; + assign fi1__CLR = 1'b0 ; + + // submodule fo + always@(WILL_FIRE_RL_arbitrate or + MUX_fo__enq_1__VAL_1 or + WILL_FIRE_RL_fi0_advance or + fi0__D_OUT or WILL_FIRE_RL_fi1_advance or fi1__D_OUT) + begin + // case (1'b1) // synopsys parallel_case + //WILL_FIRE_RL_arbitrate: fo__D_IN = MUX_fo__enq_1__VAL_1; + fo__D_IN = MUX_fo__enq_1__VAL_1; + // WILL_FIRE_RL_fi0_advance: fo__D_IN = fi0__D_OUT; + // WILL_FIRE_RL_fi1_advance: fo__D_IN = fi1__D_OUT; + + // endcase + end + assign fo__DEQ = EN_oport_get ; + assign fo__ENQ = + WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance || + WILL_FIRE_RL_fi1_advance ; + assign fo__CLR = 1'b0 ; + + // remaining internal signals + assign fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10 = + fo__FULL_N && (fi0HasPrio ? fi0__EMPTY_N : fi1__EMPTY_N) ; + + // handling of inlined registers + + always@(posedge CLK) + begin + if (!RST_N) + begin + fi0Active <= 1'd0; + fi0HasPrio <= 1'd1; + fi1Active <= 1'd0; + end + else + begin + if (fi0Active__EN) fi0Active <= fi0Active__D_IN; + if (fi0HasPrio__EN) + fi0HasPrio <= fi0HasPrio__D_IN; + if (fi1Active__EN) fi1Active <= fi1Active__D_IN; + end + end + + + // handling of system tasks + + +endmodule // mkPktMerge + + + + +module arSRLFIFO_a (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [152:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [152:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_a fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset +`define dw 153 +`define aw 4 +`define n 32 +`define max_size 30 + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) && !re) empty_n_r <= 1'b0; + else + if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1; + end +always @(posedge clk ) +begin + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1; + else + if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0; +end +endmodule + + +module arSRLFIFO_b (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [152:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [152:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_b fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) && !re) empty_n_r <= 1'b0; + else + if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1; + end +always @(posedge clk ) +begin + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1; + else + if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0; +end +endmodule + + + + +module arSRLFIFO_c (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N); + +input CLK; +input RST_N; +input [152:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [152:0] D_OUT; +output EMPTY_N; +output FULL_N; + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_c fifo_1 +(.clk(CLK), + .rst(RST_N), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) && !re) empty_n_r <= 1'b0; + else + if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1; + end +always @(posedge clk ) +begin + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1; + else + if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0; +end +endmodule + + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v b/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v new file mode 100755 index 000000000..bf033bc57 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter4B.v @@ -0,0 +1,4375 @@ +`define n 32 +`define max_size 30 + +// +// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24) +// +// On Tue Jun 8 18:43:05 EDT 2010 +// +// +// Ports: +// Name I/O size props +// wciS0_SResp O 2 reg +// wciS0_SData O 32 reg +// wciS0_SThreadBusy O 1 +// wciS0_SFlag O 2 +// wmiM_MCmd O 3 +// wmiM_MReqLast O 1 reg +// wmiM_MReqInfo O 1 reg +// wmiM_MAddrSpace O 1 reg +// wmiM_MAddr O 14 reg +// wmiM_MBurstLength O 12 reg +// wmiM_MDataValid O 1 +// wmiM_MDataLast O 1 reg +// wmiM_MData O 32 reg +// wmiM_MDataByteEn O 4 reg +// wmiM_MFlag O 32 +// wmiM_MReset_n O 1 +// wsiM1_MCmd O 3 +// wsiM1_MReqLast O 1 +// wsiM1_MBurstPrecise O 1 +// wsiM1_MBurstLength O 12 +// wsiM1_MData O 32 reg +// wsiM1_MByteEn O 4 reg +// wsiM1_MReqInfo O 8 +// wsiM1_MReset_n O 1 +// wsiS1_SThreadBusy O 1 +// wsiS1_SReset_n O 1 +// wciS0_Clk I 1 clock +// wciS0_MReset_n I 1 reset +// wciS0_MCmd I 3 +// wciS0_MAddrSpace I 1 +// wciS0_MByteEn I 4 +// wciS0_MAddr I 20 +// wciS0_MData I 32 +// wciS0_MFlag I 2 unused +// wmiM_SResp I 2 +// wmiM_SData I 32 +// wmiM_SFlag I 32 reg +// wsiS1_MCmd I 3 +// wsiS1_MBurstLength I 12 +// wsiS1_MData I 32 +// wsiS1_MByteEn I 4 +// wsiS1_MReqInfo I 8 +// wmiM_SThreadBusy I 1 reg +// wmiM_SDataThreadBusy I 1 reg +// wmiM_SRespLast I 1 unused +// wmiM_SReset_n I 1 reg +// wsiM1_SThreadBusy I 1 reg +// wsiM1_SReset_n I 1 reg +// wsiS1_MReqLast I 1 +// wsiS1_MBurstPrecise I 1 +// wsiS1_MReset_n I 1 reg +// +// No combinational paths from inputs to outputs +// +// + +module mkSMAdapter4B(wciS0_Clk, + wciS0_MReset_n, + + wciS0_MCmd, + + + wciS0_MAddrSpace, + + wciS0_MByteEn, + + wciS0_MAddr, + + wciS0_MData, + + wciS0_SResp, + + wciS0_SData, + + wciS0_SThreadBusy, + + wciS0_SFlag, + + wciS0_MFlag, + + wmiM_MCmd, + + wmiM_MReqLast, + + wmiM_MReqInfo, + + wmiM_MAddrSpace, + + wmiM_MAddr, + + wmiM_MBurstLength, + + wmiM_MDataValid, + + wmiM_MDataLast, + + wmiM_MData, + + wmiM_MDataByteEn, + + wmiM_SResp, + + wmiM_SData, + + wmiM_SThreadBusy, + + wmiM_SDataThreadBusy, + + wmiM_SRespLast, + + wmiM_SFlag, + + wmiM_MFlag, + + wmiM_MReset_n, + + wmiM_SReset_n, + + wsiM1_MCmd, + + wsiM1_MReqLast, + + wsiM1_MBurstPrecise, + + wsiM1_MBurstLength, + + wsiM1_MData, + + wsiM1_MByteEn, + + wsiM1_MReqInfo, + + wsiM1_SThreadBusy, + + wsiM1_MReset_n, + + wsiM1_SReset_n, + + wsiS1_MCmd, + + wsiS1_MReqLast, + + wsiS1_MBurstPrecise, + + wsiS1_MBurstLength, + + wsiS1_MData, + + wsiS1_MByteEn, + + wsiS1_MReqInfo, + + wsiS1_SThreadBusy, + + wsiS1_SReset_n, + + wsiS1_MReset_n, + prevent_sweep_node); + parameter [31 : 0] smaCtrlInit = 32'b0; + input wciS0_Clk; + input wciS0_MReset_n; + output prevent_sweep_node; + + // action method wciS0_mCmd + input [2 : 0] wciS0_MCmd; + + // action method wciS0_mAddrSpace + input wciS0_MAddrSpace; + + // action method wciS0_mByteEn + input [3 : 0] wciS0_MByteEn; + + // action method wciS0_mAddr + input [19 : 0] wciS0_MAddr; + + // action method wciS0_mData + input [31 : 0] wciS0_MData; + + // value method wciS0_sResp + output [1 : 0] wciS0_SResp; + + // value method wciS0_sData + output [31 : 0] wciS0_SData; + + // value method wciS0_sThreadBusy + output wciS0_SThreadBusy; + + // value method wciS0_sFlag + output [1 : 0] wciS0_SFlag; + + // action method wciS0_mFlag + input [1 : 0] wciS0_MFlag; + + // value method wmiM_mCmd + output [2 : 0] wmiM_MCmd; + + // value method wmiM_mReqLast + output wmiM_MReqLast; + + // value method wmiM_mReqInfo + output wmiM_MReqInfo; + + // value method wmiM_mAddrSpace + output wmiM_MAddrSpace; + + // value method wmiM_mAddr + output [13 : 0] wmiM_MAddr; + + // value method wmiM_mBurstLength + output [11 : 0] wmiM_MBurstLength; + + // value method wmiM_mDataValid + output wmiM_MDataValid; + + // value method wmiM_mDataLast + output wmiM_MDataLast; + + // value method wmiM_mData + output [31 : 0] wmiM_MData; + + // value method wmiM_mDataInfo + + // value method wmiM_mDataByteEn + output [3 : 0] wmiM_MDataByteEn; + + // action method wmiM_sResp + input [1 : 0] wmiM_SResp; + + // action method wmiM_sData + input [31 : 0] wmiM_SData; + + // action method wmiM_sThreadBusy + input wmiM_SThreadBusy; + + // action method wmiM_sDataThreadBusy + input wmiM_SDataThreadBusy; + + // action method wmiM_sRespLast + input wmiM_SRespLast; + + // action method wmiM_sFlag + input [31 : 0] wmiM_SFlag; + + // value method wmiM_mFlag + output [31 : 0] wmiM_MFlag; + + // value method wmiM_mReset_n + output wmiM_MReset_n; + + // action method wmiM_sReset_n + input wmiM_SReset_n; + + // value method wsiM1_mCmd + output [2 : 0] wsiM1_MCmd; + + // value method wsiM1_mReqLast + output wsiM1_MReqLast; + + // value method wsiM1_mBurstPrecise + output wsiM1_MBurstPrecise; + + // value method wsiM1_mBurstLength + output [11 : 0] wsiM1_MBurstLength; + + // value method wsiM1_mData + output [31 : 0] wsiM1_MData; + + // value method wsiM1_mByteEn + output [3 : 0] wsiM1_MByteEn; + + // value method wsiM1_mReqInfo + output [7 : 0] wsiM1_MReqInfo; + + // value method wsiM1_mDataInfo + + // action method wsiM1_sThreadBusy + input wsiM1_SThreadBusy; + + // value method wsiM1_mReset_n + output wsiM1_MReset_n; + + // action method wsiM1_sReset_n + input wsiM1_SReset_n; + + // action method wsiS1_mCmd + input [2 : 0] wsiS1_MCmd; + + // action method wsiS1_mReqLast + input wsiS1_MReqLast; + + // action method wsiS1_mBurstPrecise + input wsiS1_MBurstPrecise; + + // action method wsiS1_mBurstLength + input [11 : 0] wsiS1_MBurstLength; + + // action method wsiS1_mData + input [31 : 0] wsiS1_MData; + + // action method wsiS1_mByteEn + input [3 : 0] wsiS1_MByteEn; + + // action method wsiS1_mReqInfo + input [7 : 0] wsiS1_MReqInfo; + + // action method wsiS1_mDataInfo + + // value method wsiS1_sThreadBusy + output wsiS1_SThreadBusy; + + // value method wsiS1_sReset_n + output wsiS1_SReset_n; + + // action method wsiS1_mReset_n + input wsiS1_MReset_n; + + // signals for module outputs + wire [31 : 0] wciS0_SData, wmiM_MData, wmiM_MFlag, wsiM1_MData; + wire [13 : 0] wmiM_MAddr; + wire [11 : 0] wmiM_MBurstLength, wsiM1_MBurstLength; + wire [7 : 0] wsiM1_MReqInfo; + wire [3 : 0] wmiM_MDataByteEn, wsiM1_MByteEn; + wire [2 : 0] wmiM_MCmd, wsiM1_MCmd; + wire [1 : 0] wciS0_SFlag, wciS0_SResp; + wire wciS0_SThreadBusy, + wmiM_MAddrSpace, + wmiM_MDataLast, + wmiM_MDataValid, + wmiM_MReqInfo, + wmiM_MReqLast, + wmiM_MReset_n, + wsiM1_MBurstPrecise, + wsiM1_MReqLast, + wsiM1_MReset_n, + wsiS1_SReset_n, + wsiS1_SThreadBusy; + + // inlined wires + wire [95 : 0] wsiM_extStatusW__wget, wsiS_extStatusW__wget; + wire [60 : 0] wsiM_reqFifo_x_wire__wget, wsiS_wsiReq__wget; + wire [59 : 0] wci_wciReq__wget; + wire [37 : 0] wmi_dhF_x_wire__wget; + wire [33 : 0] wci_respF_x_wire__wget, wmi_wmiResponse__wget; + wire [31 : 0] wci_Es_mData_w__wget, + wmi_Em_sData_w__wget, + wmi_mFlagF_x_wire__wget, + wmi_reqF_x_wire__wget, + wsi_Es_mData_w__wget; + wire [19 : 0] wci_Es_mAddr_w__wget; + wire [11 : 0] wsi_Es_mBurstLength_w__wget; + wire [7 : 0] wsi_Es_mReqInfo_w__wget; + wire [3 : 0] fabRespCredit_acc_v1__wget, + fabRespCredit_acc_v2__wget, + wci_Es_mByteEn_w__wget, + wsi_Es_mByteEn_w__wget; + wire [2 : 0] wci_Es_mCmd_w__wget, wci_wEdge__wget, wsi_Es_mCmd_w__wget; + wire [1 : 0] wmi_Em_sResp_w__wget; + wire fabRespCredit_acc_v1__whas, + fabRespCredit_acc_v2__whas, + mesgPreRequest_1__wget, + mesgPreRequest_1__whas, + wci_Es_mAddrSpace_w__wget, + wci_Es_mAddrSpace_w__whas, + wci_Es_mAddr_w__whas, + wci_Es_mByteEn_w__whas, + wci_Es_mCmd_w__whas, + wci_Es_mData_w__whas, + wci_ctlAckReg_1__wget, + wci_ctlAckReg_1__whas, + wci_reqF_r_clr__whas, + wci_reqF_r_deq__whas, + wci_reqF_r_enq__whas, + wci_respF_dequeueing__whas, + wci_respF_enqueueing__whas, + wci_respF_x_wire__whas, + wci_sFlagReg_1__wget, + wci_sFlagReg_1__whas, + wci_sThreadBusy_pw__whas, + wci_wEdge__whas, + wci_wciReq__whas, + wci_wci_cfrd_pw__whas, + wci_wci_cfwr_pw__whas, + wci_wci_ctrl_pw__whas, + wmi_Em_sData_w__whas, + wmi_Em_sResp_w__whas, + wmi_dhF_dequeueing__whas, + wmi_dhF_enqueueing__whas, + wmi_dhF_x_wire__whas, + wmi_mFlagF_dequeueing__whas, + wmi_mFlagF_enqueueing__whas, + wmi_mFlagF_x_wire__whas, + wmi_operateD_1__wget, + wmi_operateD_1__whas, + wmi_peerIsReady_1__wget, + wmi_peerIsReady_1__whas, + wmi_reqF_dequeueing__whas, + wmi_reqF_enqueueing__whas, + wmi_reqF_x_wire__whas, + wmi_sDataThreadBusy_d_1__wget, + wmi_sDataThreadBusy_d_1__whas, + wmi_sThreadBusy_d_1__wget, + wmi_sThreadBusy_d_1__whas, + wmi_wmiResponse__whas, + wsiM_operateD_1__wget, + wsiM_operateD_1__whas, + wsiM_peerIsReady_1__wget, + wsiM_peerIsReady_1__whas, + wsiM_reqFifo_dequeueing__whas, + wsiM_reqFifo_enqueueing__whas, + wsiM_reqFifo_x_wire__whas, + wsiM_sThreadBusy_pw__whas, + wsiS_operateD_1__wget, + wsiS_operateD_1__whas, + wsiS_peerIsReady_1__wget, + wsiS_peerIsReady_1__whas, + wsiS_reqFifo_r_clr__whas, + wsiS_reqFifo_r_deq__whas, + wsiS_reqFifo_r_enq__whas, + wsiS_wsiReq__whas, + wsi_Es_mBurstLength_w__whas, + wsi_Es_mBurstPrecise_w__whas, + wsi_Es_mByteEn_w__whas, + wsi_Es_mCmd_w__whas, + wsi_Es_mDataInfo_w__whas, + wsi_Es_mData_w__whas, + wsi_Es_mReqInfo_w__whas, + wsi_Es_mReqLast_w__whas; + + // register abortCount + reg [31 : 0] abortCount; + wire [31 : 0] abortCount__D_IN; + wire abortCount__EN; + + // register doAbort + reg doAbort; + wire doAbort__D_IN, doAbort__EN; + + // register endOfMessage + reg endOfMessage; + wire endOfMessage__D_IN, endOfMessage__EN; + + // register errCount + reg [31 : 0] errCount; + wire [31 : 0] errCount__D_IN; + wire errCount__EN; + + // register fabRespCredit_value + reg [3 : 0] fabRespCredit_value; + wire [3 : 0] fabRespCredit_value__D_IN; + wire fabRespCredit_value__EN; + + // register fabWordsCurReq + reg [13 : 0] fabWordsCurReq; + wire [13 : 0] fabWordsCurReq__D_IN; + wire fabWordsCurReq__EN; + + // register fabWordsRemain + reg [13 : 0] fabWordsRemain; + wire [13 : 0] fabWordsRemain__D_IN; + wire fabWordsRemain__EN; + + // register firstMsgReq + reg firstMsgReq; + wire firstMsgReq__D_IN, firstMsgReq__EN; + + // register impreciseBurst + reg impreciseBurst; + reg impreciseBurst__D_IN; + wire impreciseBurst__EN; + + // register lastMesg + reg [31 : 0] lastMesg; + wire [31 : 0] lastMesg__D_IN; + wire lastMesg__EN; + + // register mesgCount + reg [31 : 0] mesgCount; + reg [31 : 0] mesgCount__D_IN; + wire mesgCount__EN; + + // register mesgLength + reg [14 : 0] mesgLength; + reg [14 : 0] mesgLength__D_IN; + wire mesgLength__EN; + + // register mesgLengthSoFar + reg [13 : 0] mesgLengthSoFar; + wire [13 : 0] mesgLengthSoFar__D_IN; + wire mesgLengthSoFar__EN; + + // register mesgPreRequest + reg mesgPreRequest; + wire mesgPreRequest__D_IN, mesgPreRequest__EN; + + // register mesgReqAddr + reg [13 : 0] mesgReqAddr; + wire [13 : 0] mesgReqAddr__D_IN; + wire mesgReqAddr__EN; + + // register mesgReqOK + reg mesgReqOK; + wire mesgReqOK__D_IN, mesgReqOK__EN; + + // register mesgReqValid + reg mesgReqValid; + wire mesgReqValid__D_IN, mesgReqValid__EN; + + // register opcode + reg [8 : 0] opcode; + reg [8 : 0] opcode__D_IN; + wire opcode__EN; + + // register preciseBurst + reg preciseBurst; + reg preciseBurst__D_IN; + wire preciseBurst__EN; + + // register readyToPush + reg readyToPush; + reg readyToPush__D_IN; + wire readyToPush__EN; + + // register readyToRequest + reg readyToRequest; + wire readyToRequest__D_IN, readyToRequest__EN; + + // register smaCtrl + reg [31 : 0] smaCtrl; + wire [31 : 0] smaCtrl__D_IN; + wire smaCtrl__EN; + + // register thisMesg + reg [31 : 0] thisMesg; + reg [31 : 0] thisMesg__D_IN; + wire thisMesg__EN; + + // register unrollCnt + reg [15 : 0] unrollCnt; + wire [15 : 0] unrollCnt__D_IN; + wire unrollCnt__EN; + + // register valExpect + reg [31 : 0] valExpect; + wire [31 : 0] valExpect__D_IN; + wire valExpect__EN; + + // register wci_cEdge + reg [2 : 0] wci_cEdge; + wire [2 : 0] wci_cEdge__D_IN; + wire wci_cEdge__EN; + + // register wci_cState + reg [2 : 0] wci_cState; + wire [2 : 0] wci_cState__D_IN; + wire wci_cState__EN; + + // register wci_ctlAckReg + reg wci_ctlAckReg; + wire wci_ctlAckReg__D_IN, wci_ctlAckReg__EN; + + // register wci_ctlOpActive + reg wci_ctlOpActive; + wire wci_ctlOpActive__D_IN, wci_ctlOpActive__EN; + + // register wci_illegalEdge + reg wci_illegalEdge; + wire wci_illegalEdge__D_IN, wci_illegalEdge__EN; + + // register wci_nState + reg [2 : 0] wci_nState; + reg [2 : 0] wci_nState__D_IN; + wire wci_nState__EN; + + // register wci_reqF_countReg + reg [1 : 0] wci_reqF_countReg; + wire [1 : 0] wci_reqF_countReg__D_IN; + wire wci_reqF_countReg__EN; + + // register wci_respF_c_r + reg [1 : 0] wci_respF_c_r; + wire [1 : 0] wci_respF_c_r__D_IN; + wire wci_respF_c_r__EN; + + // register wci_respF_q_0 + reg [33 : 0] wci_respF_q_0; + reg [33 : 0] wci_respF_q_0__D_IN; + wire wci_respF_q_0__EN; + + // register wci_respF_q_1 + reg [33 : 0] wci_respF_q_1; + reg [33 : 0] wci_respF_q_1__D_IN; + wire wci_respF_q_1__EN; + + // register wci_sFlagReg + reg wci_sFlagReg; + wire wci_sFlagReg__D_IN, wci_sFlagReg__EN; + + // register wci_sThreadBusy_d + reg wci_sThreadBusy_d; + wire wci_sThreadBusy_d__D_IN, wci_sThreadBusy_d__EN; + + // register wmi_busyWithMessage + reg wmi_busyWithMessage; + wire wmi_busyWithMessage__D_IN, wmi_busyWithMessage__EN; + + // register wmi_dhF_c_r + reg [1 : 0] wmi_dhF_c_r; + wire [1 : 0] wmi_dhF_c_r__D_IN; + wire wmi_dhF_c_r__EN; + + // register wmi_dhF_q_0 + reg [37 : 0] wmi_dhF_q_0; + reg [37 : 0] wmi_dhF_q_0__D_IN; + wire wmi_dhF_q_0__EN; + + // register wmi_dhF_q_1 + reg [37 : 0] wmi_dhF_q_1; + reg [37 : 0] wmi_dhF_q_1__D_IN; + wire wmi_dhF_q_1__EN; + + // register wmi_mFlagF_c_r + reg [1 : 0] wmi_mFlagF_c_r; + wire [1 : 0] wmi_mFlagF_c_r__D_IN; + wire wmi_mFlagF_c_r__EN; + + // register wmi_mFlagF_q_0 + reg [31 : 0] wmi_mFlagF_q_0; + reg [31 : 0] wmi_mFlagF_q_0__D_IN; + wire wmi_mFlagF_q_0__EN; + + // register wmi_mFlagF_q_1 + reg [31 : 0] wmi_mFlagF_q_1; + reg [31 : 0] wmi_mFlagF_q_1__D_IN; + wire wmi_mFlagF_q_1__EN; + + // register wmi_operateD + reg wmi_operateD; + wire wmi_operateD__D_IN, wmi_operateD__EN; + + // register wmi_peerIsReady + reg wmi_peerIsReady; + wire wmi_peerIsReady__D_IN, wmi_peerIsReady__EN; + + // register wmi_reqF_c_r + reg [1 : 0] wmi_reqF_c_r; + wire [1 : 0] wmi_reqF_c_r__D_IN; + wire wmi_reqF_c_r__EN; + + // register wmi_reqF_q_0 + reg [31 : 0] wmi_reqF_q_0; + reg [31 : 0] wmi_reqF_q_0__D_IN; + wire wmi_reqF_q_0__EN; + + // register wmi_reqF_q_1 + reg [31 : 0] wmi_reqF_q_1; + reg [31 : 0] wmi_reqF_q_1__D_IN; + wire wmi_reqF_q_1__EN; + + // register wmi_sDataThreadBusy_d + reg wmi_sDataThreadBusy_d; + wire wmi_sDataThreadBusy_d__D_IN, wmi_sDataThreadBusy_d__EN; + + // register wmi_sFlagReg + reg [31 : 0] wmi_sFlagReg; + wire [31 : 0] wmi_sFlagReg__D_IN; + wire wmi_sFlagReg__EN; + + // register wmi_sThreadBusy_d + reg wmi_sThreadBusy_d; + wire wmi_sThreadBusy_d__D_IN, wmi_sThreadBusy_d__EN; + + // register wsiM_burstKind + reg [1 : 0] wsiM_burstKind; + wire [1 : 0] wsiM_burstKind__D_IN; + wire wsiM_burstKind__EN; + + // register wsiM_errorSticky + reg wsiM_errorSticky; + wire wsiM_errorSticky__D_IN, wsiM_errorSticky__EN; + + // register wsiM_iMesgCount + reg [31 : 0] wsiM_iMesgCount; + wire [31 : 0] wsiM_iMesgCount__D_IN; + wire wsiM_iMesgCount__EN; + + // register wsiM_operateD + reg wsiM_operateD; + wire wsiM_operateD__D_IN, wsiM_operateD__EN; + + // register wsiM_pMesgCount + reg [31 : 0] wsiM_pMesgCount; + wire [31 : 0] wsiM_pMesgCount__D_IN; + wire wsiM_pMesgCount__EN; + + // register wsiM_peerIsReady + reg wsiM_peerIsReady; + wire wsiM_peerIsReady__D_IN, wsiM_peerIsReady__EN; + + // register wsiM_reqFifo_c_r + reg [1 : 0] wsiM_reqFifo_c_r; + wire [1 : 0] wsiM_reqFifo_c_r__D_IN; + wire wsiM_reqFifo_c_r__EN; + + // register wsiM_reqFifo_q_0 + reg [60 : 0] wsiM_reqFifo_q_0; + reg [60 : 0] wsiM_reqFifo_q_0__D_IN; + wire wsiM_reqFifo_q_0__EN; + + // register wsiM_reqFifo_q_1 + reg [60 : 0] wsiM_reqFifo_q_1; + reg [60 : 0] wsiM_reqFifo_q_1__D_IN; + wire wsiM_reqFifo_q_1__EN; + + // register wsiM_sThreadBusy_d + reg wsiM_sThreadBusy_d; + wire wsiM_sThreadBusy_d__D_IN, wsiM_sThreadBusy_d__EN; + + // register wsiM_statusR + reg [7 : 0] wsiM_statusR; + wire [7 : 0] wsiM_statusR__D_IN; + wire wsiM_statusR__EN; + + // register wsiM_tBusyCount + reg [31 : 0] wsiM_tBusyCount; + wire [31 : 0] wsiM_tBusyCount__D_IN; + wire wsiM_tBusyCount__EN; + + // register wsiM_trafficSticky + reg wsiM_trafficSticky; + wire wsiM_trafficSticky__D_IN, wsiM_trafficSticky__EN; + + // register wsiS_burstKind + reg [1 : 0] wsiS_burstKind; + wire [1 : 0] wsiS_burstKind__D_IN; + wire wsiS_burstKind__EN; + + // register wsiS_errorSticky + reg wsiS_errorSticky; + wire wsiS_errorSticky__D_IN, wsiS_errorSticky__EN; + + // register wsiS_iMesgCount + reg [31 : 0] wsiS_iMesgCount; + wire [31 : 0] wsiS_iMesgCount__D_IN; + wire wsiS_iMesgCount__EN; + + // register wsiS_operateD + reg wsiS_operateD; + wire wsiS_operateD__D_IN, wsiS_operateD__EN; + + // register wsiS_pMesgCount + reg [31 : 0] wsiS_pMesgCount; + wire [31 : 0] wsiS_pMesgCount__D_IN; + wire wsiS_pMesgCount__EN; + + // register wsiS_peerIsReady + reg wsiS_peerIsReady; + wire wsiS_peerIsReady__D_IN, wsiS_peerIsReady__EN; + + // register wsiS_reqFifo_countReg + reg [1 : 0] wsiS_reqFifo_countReg; + wire [1 : 0] wsiS_reqFifo_countReg__D_IN; + wire wsiS_reqFifo_countReg__EN; + + // register wsiS_statusR + reg [7 : 0] wsiS_statusR; + wire [7 : 0] wsiS_statusR__D_IN; + wire wsiS_statusR__EN; + + // register wsiS_tBusyCount + reg [31 : 0] wsiS_tBusyCount; + wire [31 : 0] wsiS_tBusyCount__D_IN; + wire wsiS_tBusyCount__EN; + + // register wsiS_trafficSticky + reg wsiS_trafficSticky; + wire wsiS_trafficSticky__D_IN, wsiS_trafficSticky__EN; + + // register wsiWordsRemain + reg [11 : 0] wsiWordsRemain; + wire [11 : 0] wsiWordsRemain__D_IN; + wire wsiWordsRemain__EN; + + // register zeroLengthMesg + reg zeroLengthMesg; + wire zeroLengthMesg__D_IN, zeroLengthMesg__EN; + + // ports of submodule wci_isReset + wire wci_isReset__VAL; + + // ports of submodule wci_reqF + wire [59 : 0] wci_reqF__D_IN, wci_reqF__D_OUT; + wire wci_reqF__CLR, wci_reqF__DEQ, wci_reqF__EMPTY_N, wci_reqF__ENQ; + + // ports of submodule wmi_isReset + wire wmi_isReset__VAL; + + // ports of submodule wmi_respF + wire [31 : 0] wmi_respF__D_IN; + wire [31:0] wmi_respF__D_OUT; + wire wmi_respF__CLR, + wmi_respF__DEQ, + wmi_respF__EMPTY_N, + wmi_respF__ENQ, + wmi_respF__FULL_N; + + // ports of submodule wsiM_isReset + wire wsiM_isReset__VAL; + + // ports of submodule wsiS_isReset + wire wsiS_isReset__VAL; + + // ports of submodule wsiS_reqFifo + wire [60 : 0] wsiS_reqFifo__D_IN, wsiS_reqFifo__D_OUT; + wire wsiS_reqFifo__CLR, + wsiS_reqFifo__DEQ, + wsiS_reqFifo__EMPTY_N, + wsiS_reqFifo__ENQ, + wsiS_reqFifo__FULL_N; + + // rule scheduling signals + wire CAN_FIRE_RL_fabRespCredit_accumulate, + CAN_FIRE_RL_mesgPreRequest__dreg_update, + CAN_FIRE_RL_operating_actions, + CAN_FIRE_RL_wci_Es_doAlways_Req, + CAN_FIRE_RL_wci_cfrd, + CAN_FIRE_RL_wci_cfwr, + CAN_FIRE_RL_wci_ctlAckReg__dreg_update, + CAN_FIRE_RL_wci_ctl_op_complete, + CAN_FIRE_RL_wci_ctl_op_start, + CAN_FIRE_RL_wci_ctrl_EiI, + CAN_FIRE_RL_wci_ctrl_IsO, + CAN_FIRE_RL_wci_ctrl_OrE, + CAN_FIRE_RL_wci_reqF__updateLevelCounter, + CAN_FIRE_RL_wci_reqF_enq, + CAN_FIRE_RL_wci_request_decode, + CAN_FIRE_RL_wci_respF_both, + CAN_FIRE_RL_wci_respF_decCtr, + CAN_FIRE_RL_wci_respF_deq, + CAN_FIRE_RL_wci_respF_incCtr, + CAN_FIRE_RL_wci_sFlagReg__dreg_update, + CAN_FIRE_RL_wci_sThreadBusy_reg, + CAN_FIRE_RL_wmi_Em_doAlways, + CAN_FIRE_RL_wmi_dhF_both, + CAN_FIRE_RL_wmi_dhF_decCtr, + CAN_FIRE_RL_wmi_dhF_deq, + CAN_FIRE_RL_wmi_dhF_incCtr, + CAN_FIRE_RL_wmi_mFlagF_both, + CAN_FIRE_RL_wmi_mFlagF_decCtr, + CAN_FIRE_RL_wmi_mFlagF_incCtr, + CAN_FIRE_RL_wmi_operateD__dreg_update, + CAN_FIRE_RL_wmi_peerIsReady__dreg_update, + CAN_FIRE_RL_wmi_reqF_both, + CAN_FIRE_RL_wmi_reqF_decCtr, + CAN_FIRE_RL_wmi_reqF_deq, + CAN_FIRE_RL_wmi_reqF_incCtr, + CAN_FIRE_RL_wmi_respAdvance, + CAN_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update, + CAN_FIRE_RL_wmi_sThreadBusy_d__dreg_update, + CAN_FIRE_RL_wmrd_mesgBegin, + CAN_FIRE_RL_wmrd_mesgBodyPreRequest, + CAN_FIRE_RL_wmrd_mesgBodyRequest, + CAN_FIRE_RL_wmrd_mesgBodyResponse, + CAN_FIRE_RL_wmwt_doAbort, + CAN_FIRE_RL_wmwt_mesgBegin, + CAN_FIRE_RL_wmwt_messageFinalize, + CAN_FIRE_RL_wmwt_messagePushImprecise, + CAN_FIRE_RL_wmwt_messagePushPrecise, + CAN_FIRE_RL_wmwt_requestPrecise, + CAN_FIRE_RL_wsiM_ext_status_assign, + CAN_FIRE_RL_wsiM_inc_tBusyCount, + CAN_FIRE_RL_wsiM_operateD__dreg_update, + CAN_FIRE_RL_wsiM_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiM_reqFifo_both, + CAN_FIRE_RL_wsiM_reqFifo_decCtr, + CAN_FIRE_RL_wsiM_reqFifo_deq, + CAN_FIRE_RL_wsiM_reqFifo_incCtr, + CAN_FIRE_RL_wsiM_sThreadBusy_reg, + CAN_FIRE_RL_wsiM_update_statusR, + CAN_FIRE_RL_wsiS_ext_status_assign, + CAN_FIRE_RL_wsiS_inc_tBusyCount, + CAN_FIRE_RL_wsiS_operateD__dreg_update, + CAN_FIRE_RL_wsiS_peerIsReady__dreg_update, + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + CAN_FIRE_RL_wsiS_reqFifo_enq, + CAN_FIRE_RL_wsiS_update_statusR, + CAN_FIRE_RL_wsi_Es_doAlways, + CAN_FIRE_RL_wsipass_doMessagePush, + CAN_FIRE_wciS0_mAddr, + CAN_FIRE_wciS0_mAddrSpace, + CAN_FIRE_wciS0_mByteEn, + CAN_FIRE_wciS0_mCmd, + CAN_FIRE_wciS0_mData, + CAN_FIRE_wciS0_mFlag, + CAN_FIRE_wmiM_sData, + CAN_FIRE_wmiM_sDataThreadBusy, + CAN_FIRE_wmiM_sFlag, + CAN_FIRE_wmiM_sReset_n, + CAN_FIRE_wmiM_sResp, + CAN_FIRE_wmiM_sRespLast, + CAN_FIRE_wmiM_sThreadBusy, + CAN_FIRE_wsiM1_sReset_n, + CAN_FIRE_wsiM1_sThreadBusy, + CAN_FIRE_wsiS1_mBurstLength, + CAN_FIRE_wsiS1_mBurstPrecise, + CAN_FIRE_wsiS1_mByteEn, + CAN_FIRE_wsiS1_mCmd, + CAN_FIRE_wsiS1_mData, + CAN_FIRE_wsiS1_mDataInfo, + CAN_FIRE_wsiS1_mReqInfo, + CAN_FIRE_wsiS1_mReqLast, + CAN_FIRE_wsiS1_mReset_n, + WILL_FIRE_RL_fabRespCredit_accumulate, + WILL_FIRE_RL_mesgPreRequest__dreg_update, + WILL_FIRE_RL_operating_actions, + WILL_FIRE_RL_wci_Es_doAlways_Req, + WILL_FIRE_RL_wci_cfrd, + WILL_FIRE_RL_wci_cfwr, + WILL_FIRE_RL_wci_ctlAckReg__dreg_update, + WILL_FIRE_RL_wci_ctl_op_complete, + WILL_FIRE_RL_wci_ctl_op_start, + WILL_FIRE_RL_wci_ctrl_EiI, + WILL_FIRE_RL_wci_ctrl_IsO, + WILL_FIRE_RL_wci_ctrl_OrE, + WILL_FIRE_RL_wci_reqF__updateLevelCounter, + WILL_FIRE_RL_wci_reqF_enq, + WILL_FIRE_RL_wci_request_decode, + WILL_FIRE_RL_wci_respF_both, + WILL_FIRE_RL_wci_respF_decCtr, + WILL_FIRE_RL_wci_respF_deq, + WILL_FIRE_RL_wci_respF_incCtr, + WILL_FIRE_RL_wci_sFlagReg__dreg_update, + WILL_FIRE_RL_wci_sThreadBusy_reg, + WILL_FIRE_RL_wmi_Em_doAlways, + WILL_FIRE_RL_wmi_dhF_both, + WILL_FIRE_RL_wmi_dhF_decCtr, + WILL_FIRE_RL_wmi_dhF_deq, + WILL_FIRE_RL_wmi_dhF_incCtr, + WILL_FIRE_RL_wmi_mFlagF_both, + WILL_FIRE_RL_wmi_mFlagF_decCtr, + WILL_FIRE_RL_wmi_mFlagF_incCtr, + WILL_FIRE_RL_wmi_operateD__dreg_update, + WILL_FIRE_RL_wmi_peerIsReady__dreg_update, + WILL_FIRE_RL_wmi_reqF_both, + WILL_FIRE_RL_wmi_reqF_decCtr, + WILL_FIRE_RL_wmi_reqF_deq, + WILL_FIRE_RL_wmi_reqF_incCtr, + WILL_FIRE_RL_wmi_respAdvance, + WILL_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update, + WILL_FIRE_RL_wmi_sThreadBusy_d__dreg_update, + WILL_FIRE_RL_wmrd_mesgBegin, + WILL_FIRE_RL_wmrd_mesgBodyPreRequest, + WILL_FIRE_RL_wmrd_mesgBodyRequest, + WILL_FIRE_RL_wmrd_mesgBodyResponse, + WILL_FIRE_RL_wmwt_doAbort, + WILL_FIRE_RL_wmwt_mesgBegin, + WILL_FIRE_RL_wmwt_messageFinalize, + WILL_FIRE_RL_wmwt_messagePushImprecise, + WILL_FIRE_RL_wmwt_messagePushPrecise, + WILL_FIRE_RL_wmwt_requestPrecise, + WILL_FIRE_RL_wsiM_ext_status_assign, + WILL_FIRE_RL_wsiM_inc_tBusyCount, + WILL_FIRE_RL_wsiM_operateD__dreg_update, + WILL_FIRE_RL_wsiM_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiM_reqFifo_both, + WILL_FIRE_RL_wsiM_reqFifo_decCtr, + WILL_FIRE_RL_wsiM_reqFifo_deq, + WILL_FIRE_RL_wsiM_reqFifo_incCtr, + WILL_FIRE_RL_wsiM_sThreadBusy_reg, + WILL_FIRE_RL_wsiM_update_statusR, + WILL_FIRE_RL_wsiS_ext_status_assign, + WILL_FIRE_RL_wsiS_inc_tBusyCount, + WILL_FIRE_RL_wsiS_operateD__dreg_update, + WILL_FIRE_RL_wsiS_peerIsReady__dreg_update, + WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter, + WILL_FIRE_RL_wsiS_reqFifo_enq, + WILL_FIRE_RL_wsiS_update_statusR, + WILL_FIRE_RL_wsi_Es_doAlways, + WILL_FIRE_RL_wsipass_doMessagePush, + WILL_FIRE_wciS0_mAddr, + WILL_FIRE_wciS0_mAddrSpace, + WILL_FIRE_wciS0_mByteEn, + WILL_FIRE_wciS0_mCmd, + WILL_FIRE_wciS0_mData, + WILL_FIRE_wciS0_mFlag, + WILL_FIRE_wmiM_sData, + WILL_FIRE_wmiM_sDataThreadBusy, + WILL_FIRE_wmiM_sFlag, + WILL_FIRE_wmiM_sReset_n, + WILL_FIRE_wmiM_sResp, + WILL_FIRE_wmiM_sRespLast, + WILL_FIRE_wmiM_sThreadBusy, + WILL_FIRE_wsiM1_sReset_n, + WILL_FIRE_wsiM1_sThreadBusy, + WILL_FIRE_wsiS1_mBurstLength, + WILL_FIRE_wsiS1_mBurstPrecise, + WILL_FIRE_wsiS1_mByteEn, + WILL_FIRE_wsiS1_mCmd, + WILL_FIRE_wsiS1_mData, + WILL_FIRE_wsiS1_mDataInfo, + WILL_FIRE_wsiS1_mReqInfo, + WILL_FIRE_wsiS1_mReqLast, + WILL_FIRE_wsiS1_mReset_n; + + // inputs to muxes for submodule ports + reg [33 : 0] MUX_wci_respF_q_0__write_1__VAL_1; + reg [31 : 0] MUX_wmi_reqF_q_0__write_1__VAL_1; + wire [60 : 0] MUX_wsiM_reqFifo_q_0__write_1__VAL_1, + MUX_wsiM_reqFifo_q_0__write_1__VAL_2, + MUX_wsiM_reqFifo_q_1__write_1__VAL_1, + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1; + wire [37 : 0] MUX_wmi_dhF_q_0__write_1__VAL_1, + MUX_wmi_dhF_q_0__write_1__VAL_2, + MUX_wmi_dhF_q_1__write_1__VAL_1, + MUX_wmi_dhF_x_wire__wset_1__VAL_1, + MUX_wmi_dhF_x_wire__wset_1__VAL_2; + wire [33 : 0] MUX_wci_respF_q_0__write_1__VAL_2, + MUX_wci_respF_q_1__write_1__VAL_2, + MUX_wci_respF_x_wire__wset_1__VAL_1, + MUX_wci_respF_x_wire__wset_1__VAL_2; + wire [31 : 0] MUX_mesgCount__write_1__VAL_1, + MUX_thisMesg__write_1__VAL_1, + MUX_thisMesg__write_1__VAL_2, + MUX_wmi_mFlagF_q_0__write_1__VAL_1, + MUX_wmi_mFlagF_q_1__write_1__VAL_1, + MUX_wmi_mFlagF_x_wire__wset_1__VAL_1, + MUX_wmi_mFlagF_x_wire__wset_1__VAL_3, + MUX_wmi_reqF_q_0__write_1__VAL_2, + MUX_wmi_reqF_q_1__write_1__VAL_2, + MUX_wmi_reqF_x_wire__wset_1__VAL_1, + MUX_wmi_reqF_x_wire__wset_1__VAL_2, + MUX_wmi_reqF_x_wire__wset_1__VAL_3; + wire [15 : 0] MUX_unrollCnt__write_1__VAL_1, MUX_unrollCnt__write_1__VAL_2; + wire [14 : 0] MUX_mesgLength__write_1__VAL_2, MUX_mesgLength__write_1__VAL_4; + wire [13 : 0] MUX_fabWordsRemain__write_1__VAL_1, + MUX_fabWordsRemain__write_1__VAL_2, + MUX_mesgReqAddr__write_1__VAL_2; + wire [11 : 0] MUX_wsiWordsRemain__write_1__VAL_2; + wire [8 : 0] MUX_opcode__write_1__VAL_2; + wire [3 : 0] MUX_fabRespCredit_value__write_1__VAL_2; + wire [1 : 0] MUX_wci_respF_c_r__write_1__VAL_1, + MUX_wci_respF_c_r__write_1__VAL_2, + MUX_wmi_dhF_c_r__write_1__VAL_1, + MUX_wmi_dhF_c_r__write_1__VAL_2, + MUX_wmi_mFlagF_c_r__write_1__VAL_1, + MUX_wmi_mFlagF_c_r__write_1__VAL_2, + MUX_wmi_reqF_c_r__write_1__VAL_1, + MUX_wmi_reqF_c_r__write_1__VAL_2, + MUX_wsiM_reqFifo_c_r__write_1__VAL_1, + MUX_wsiM_reqFifo_c_r__write_1__VAL_2; + wire MUX_endOfMessage__write_1__SEL_1, + MUX_impreciseBurst__write_1__SEL_2, + MUX_lastMesg__write_1__SEL_2, + MUX_mesgCount__write_1__SEL_1, + MUX_mesgLength__write_1__SEL_2, + MUX_wci_illegalEdge__write_1__SEL_1, + MUX_wci_illegalEdge__write_1__SEL_2, + MUX_wci_illegalEdge__write_1__VAL_2, + MUX_wci_respF_q_0__write_1__SEL_1, + MUX_wci_respF_q_1__write_1__SEL_1, + MUX_wmi_dhF_q_0__write_1__SEL_2, + MUX_wmi_dhF_q_1__write_1__SEL_2, + MUX_wmi_mFlagF_q_0__write_1__SEL_2, + MUX_wmi_mFlagF_q_1__write_1__SEL_2, + MUX_wmi_mFlagF_x_wire__wset_1__SEL_2, + MUX_wmi_reqF_q_0__write_1__SEL_1, + MUX_wmi_reqF_q_1__write_1__SEL_1, + MUX_wsiM_reqFifo_q_0__write_1__SEL_2, + MUX_wsiM_reqFifo_q_1__write_1__SEL_2, + MUX_wsiM_reqFifo_x_wire__wset_1__SEL_1; + + // remaining internal signals + reg [63 : 0] v__h15314, + v__h16237, + v__h16483, + v__h18176, + v__h18253, + v__h19470, + v__h2653, + v__h2800, + v__h3699; + reg [31 : 0] value__h6065, x_data__h15447; + wire [31 : 0] rdat__h15540; + wire [23 : 0] mesgMetaF_length__h16810, mesgMetaF_length__h17723; + wire [15 : 0] wsiBurstLength__h18454, x__h15543, x_length__h17087; + wire [13 : 0] IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753, + addr__h16647, + b__h19084, + mlp1B__h16631, + mlp1__h16630; + wire [11 : 0] bl__h17580, x_burstLength__h18559; + wire [7 : 0] mesgMetaF_opcode__h16809; + wire [3 : 0] b__h13937, x_byteEn__h18561; + wire NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290, + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355, + wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165, + x__h16715, + x__h18884; + + // action method wciS0_mCmd + assign CAN_FIRE_wciS0_mCmd = 1'b1 ; + assign WILL_FIRE_wciS0_mCmd = 1'b1 ; + + // action method wciS0_mAddrSpace + assign CAN_FIRE_wciS0_mAddrSpace = 1'b1 ; + assign WILL_FIRE_wciS0_mAddrSpace = 1'b1 ; + + // action method wciS0_mByteEn + assign CAN_FIRE_wciS0_mByteEn = 1'b1 ; + assign WILL_FIRE_wciS0_mByteEn = 1'b1 ; + + // action method wciS0_mAddr + assign CAN_FIRE_wciS0_mAddr = 1'b1 ; + assign WILL_FIRE_wciS0_mAddr = 1'b1 ; + + // action method wciS0_mData + assign CAN_FIRE_wciS0_mData = 1'b1 ; + assign WILL_FIRE_wciS0_mData = 1'b1 ; + + // value method wciS0_sResp + assign wciS0_SResp = wci_respF_q_0[33:32] ; + + // value method wciS0_sData + assign wciS0_SData = wci_respF_q_0[31:0] ; + + // value method wciS0_sThreadBusy + assign wciS0_SThreadBusy = wci_reqF_countReg > 2'b01 || wci_isReset__VAL ; + + // value method wciS0_sFlag + assign wciS0_SFlag = { 1'b1, wci_sFlagReg } ; + + // action method wciS0_mFlag + assign CAN_FIRE_wciS0_mFlag = 1'b1 ; + assign WILL_FIRE_wciS0_mFlag = 1'b1 ; + + // value method wmiM_mCmd + assign wmiM_MCmd = wmi_sThreadBusy_d ? 3'b000 : wmi_reqF_q_0[31:29] ; + + // value method wmiM_mReqLast + assign wmiM_MReqLast = wmi_reqF_q_0[28] ; + + // value method wmiM_mReqInfo + assign wmiM_MReqInfo = wmi_reqF_q_0[27] ; + + // value method wmiM_mAddrSpace + assign wmiM_MAddrSpace = wmi_reqF_q_0[26] ; + + // value method wmiM_mAddr + assign wmiM_MAddr = wmi_reqF_q_0[25:12] ; + + // value method wmiM_mBurstLength + assign wmiM_MBurstLength = wmi_reqF_q_0[11:0] ; + + // value method wmiM_mDataValid + assign wmiM_MDataValid = !wmi_sDataThreadBusy_d && wmi_dhF_q_0[37] ; + + // value method wmiM_mDataLast + assign wmiM_MDataLast = wmi_dhF_q_0[36] ; + + // value method wmiM_mData + assign wmiM_MData = wmi_dhF_q_0[35:4] ; + + // value method wmiM_mDataByteEn + assign wmiM_MDataByteEn = wmi_dhF_q_0[3:0] ; + + // action method wmiM_sResp + assign CAN_FIRE_wmiM_sResp = 1'b1 ; + assign WILL_FIRE_wmiM_sResp = 1'b1 ; + + // action method wmiM_sData + assign CAN_FIRE_wmiM_sData = 1'b1 ; + assign WILL_FIRE_wmiM_sData = 1'b1 ; + + // action method wmiM_sThreadBusy + assign CAN_FIRE_wmiM_sThreadBusy = 1'b1 ; + assign WILL_FIRE_wmiM_sThreadBusy = wmiM_SThreadBusy ; + + // action method wmiM_sDataThreadBusy + assign CAN_FIRE_wmiM_sDataThreadBusy = 1'b1 ; + assign WILL_FIRE_wmiM_sDataThreadBusy = wmiM_SDataThreadBusy ; + + // action method wmiM_sRespLast + assign CAN_FIRE_wmiM_sRespLast = 1'b1 ; + assign WILL_FIRE_wmiM_sRespLast = wmiM_SRespLast ; + + // action method wmiM_sFlag + assign CAN_FIRE_wmiM_sFlag = 1'b1 ; + assign WILL_FIRE_wmiM_sFlag = 1'b1 ; + + // value method wmiM_mFlag + assign wmiM_MFlag = wmi_sThreadBusy_d ? 32'b00000000000000000000000000000000 : wmi_mFlagF_q_0 ; + + // value method wmiM_mReset_n + assign wmiM_MReset_n = !wmi_isReset__VAL && wmi_operateD ; + + // action method wmiM_sReset_n + assign CAN_FIRE_wmiM_sReset_n = 1'b1 ; + assign WILL_FIRE_wmiM_sReset_n = wmiM_SReset_n ; + + // value method wsiM1_mCmd + assign wsiM1_MCmd = wsiM_sThreadBusy_d ? 3'b000 : wsiM_reqFifo_q_0[60:58] ; + + // value method wsiM1_mReqLast + assign wsiM1_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ; + + // value method wsiM1_mBurstPrecise + assign wsiM1_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ; + + // value method wsiM1_mBurstLength + assign wsiM1_MBurstLength = + wsiM_sThreadBusy_d ? 12'b000000000000 : wsiM_reqFifo_q_0[55:44] ; + + // value method wsiM1_mData + assign wsiM1_MData = wsiM_reqFifo_q_0[43:12] ; + + // value method wsiM1_mByteEn + assign wsiM1_MByteEn = wsiM_reqFifo_q_0[11:8] ; + + // value method wsiM1_mReqInfo + assign wsiM1_MReqInfo = wsiM_sThreadBusy_d ? 8'b00000000 : wsiM_reqFifo_q_0[7:0] ; + + // action method wsiM1_sThreadBusy + assign CAN_FIRE_wsiM1_sThreadBusy = 1'b1 ; + assign WILL_FIRE_wsiM1_sThreadBusy = wsiM1_SThreadBusy ; + + // value method wsiM1_mReset_n + assign wsiM1_MReset_n = !wsiM_isReset__VAL && wsiM_operateD ; + + // action method wsiM1_sReset_n + assign CAN_FIRE_wsiM1_sReset_n = 1'b1 ; + assign WILL_FIRE_wsiM1_sReset_n = wsiM1_SReset_n ; + + // action method wsiS1_mCmd + assign CAN_FIRE_wsiS1_mCmd = 1'b1 ; + assign WILL_FIRE_wsiS1_mCmd = 1'b1 ; + + // action method wsiS1_mReqLast + assign CAN_FIRE_wsiS1_mReqLast = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqLast = wsiS1_MReqLast ; + + // action method wsiS1_mBurstPrecise + assign CAN_FIRE_wsiS1_mBurstPrecise = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstPrecise = wsiS1_MBurstPrecise ; + + // action method wsiS1_mBurstLength + assign CAN_FIRE_wsiS1_mBurstLength = 1'b1 ; + assign WILL_FIRE_wsiS1_mBurstLength = 1'b1 ; + + // action method wsiS1_mData + assign CAN_FIRE_wsiS1_mData = 1'b1 ; + assign WILL_FIRE_wsiS1_mData = 1'b1 ; + + // action method wsiS1_mByteEn + assign CAN_FIRE_wsiS1_mByteEn = 1'b1 ; + assign WILL_FIRE_wsiS1_mByteEn = 1'b1 ; + + // action method wsiS1_mReqInfo + assign CAN_FIRE_wsiS1_mReqInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mReqInfo = 1'b1 ; + + // action method wsiS1_mDataInfo + assign CAN_FIRE_wsiS1_mDataInfo = 1'b1 ; + assign WILL_FIRE_wsiS1_mDataInfo = 1'b1 ; + + // value method wsiS1_sThreadBusy + assign wsiS1_SThreadBusy = + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady ; + + // value method wsiS1_sReset_n + assign wsiS1_SReset_n = !wsiS_isReset__VAL && wsiS_operateD ; + + // action method wsiS1_mReset_n + assign CAN_FIRE_wsiS1_mReset_n = 1'b1 ; + assign WILL_FIRE_wsiS1_mReset_n = wsiS1_MReset_n ; + + // submodule wci_isReset + ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset__VAL)); + + +wire full_not_used; + // submodule wci_reqF + SizedFIFO_a size_fifoA( + + .CLK(wciS0_Clk), + .D_IN(wci_reqF__D_IN), + .ENQ(wci_reqF__ENQ), + .DEQ(wci_reqF__DEQ), + .CLR(wci_reqF__CLR), + .D_OUT(wci_reqF__D_OUT), + .FULL_N(full_not_used), + .EMPTY_N(wci_reqF__EMPTY_N) + ); + +wire dummy1; +assign dummy1 = &wci_reqF__D_OUT; +assign prevent_sweep_node = dummy1 & dummy2 & dummy3; + + // submodule wmi_isReset + ResetToBool wmi_isReset(.RST(wciS0_MReset_n), .VAL(wmi_isReset__VAL)); + + // submodule wmi_respF + //34 width + SizedFIFO_b size_fifoB ( + .CLK(wciS0_Clk), + .D_IN(wmi_respF__D_IN), + .ENQ(wmi_respF__ENQ), + .DEQ(wmi_respF__DEQ), + .CLR(wmi_respF__CLR), + .D_OUT(wmi_respF__D_OUT), + .FULL_N(wmi_respF__FULL_N), + .EMPTY_N(wmi_respF__EMPTY_N) + ); +wire dummy2; +assign dummy2 = &wmi_respF__D_OUT; + + // submodule wsiM_isReset + ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset__VAL)); + + // submodule wsiS_isReset + ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset__VAL)); + + // submodule wsiS_reqFifo + // SizedFIFO #(.p1width(32'd61), +// .p2depth(32'd3), + // .p3cntr_width(32'b00000000000000000000000000000001), + // .guarded(32'b00000000000000000000000000000001)) wsiS_reqFifo(.RST_N(wciS0_MReset_n), + + + SizedFIFO_c size_fifoc( + + .CLK(wciS0_Clk), + .D_IN(wsiS_reqFifo__D_IN), + .ENQ(wsiS_reqFifo__ENQ), + .DEQ(wsiS_reqFifo__DEQ), + .CLR(wsiS_reqFifo__CLR), + .D_OUT(wsiS_reqFifo__D_OUT), + .FULL_N(wsiS_reqFifo__FULL_N), + .EMPTY_N(wsiS_reqFifo__EMPTY_N) + ); + +wire dummy3; +assign dummy3 = &wsiS_reqFifo__D_OUT; + + + // rule RL_wci_request_decode + assign CAN_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + assign WILL_FIRE_RL_wci_request_decode = wci_reqF__EMPTY_N ; + + // rule RL_wsiS_ext_status_assign + assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'b1 ; + + // rule RL_wsiM_ext_status_assign + assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'b1 ; + + // rule RL_wci_cfrd + assign CAN_FIRE_RL_wci_cfrd = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfrd_pw__whas ; + assign WILL_FIRE_RL_wci_cfrd = + CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wmrd_mesgBodyRequest + assign CAN_FIRE_RL_wmrd_mesgBodyRequest = + NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290 && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + mesgPreRequest ; + assign WILL_FIRE_RL_wmrd_mesgBodyRequest = + CAN_FIRE_RL_wmrd_mesgBodyRequest ; + + // rule RL_wmrd_mesgBodyPreRequest + assign CAN_FIRE_RL_wmrd_mesgBodyPreRequest = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + fabWordsRemain != 14'b00000000000000 && + (fabRespCredit_value ^ 4'h8) > 4'b1000 && + mesgReqOK ; + assign WILL_FIRE_RL_wmrd_mesgBodyPreRequest = + CAN_FIRE_RL_wmrd_mesgBodyPreRequest && + !WILL_FIRE_RL_wmrd_mesgBodyRequest ; + + // rule RL_wmrd_mesgBegin + assign CAN_FIRE_RL_wmrd_mesgBegin = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + unrollCnt == 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBegin = CAN_FIRE_RL_wmrd_mesgBegin ; + + // rule RL_wci_ctl_op_start + assign CAN_FIRE_RL_wci_ctl_op_start = + wci_reqF__EMPTY_N && wci_wci_ctrl_pw__whas ; + assign WILL_FIRE_RL_wci_ctl_op_start = + CAN_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctrl_EiI + assign CAN_FIRE_RL_wci_ctrl_EiI = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b000 && + wci_reqF__D_OUT[36:34] == 3'b000 ; + assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ; + + // rule RL_wci_ctrl_OrE + assign CAN_FIRE_RL_wci_ctrl_OrE = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b010 && + wci_reqF__D_OUT[36:34] == 3'b011 ; + assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ; + + // rule RL_wci_respF_deq + assign CAN_FIRE_RL_wci_respF_deq = 1'b1 ; + assign WILL_FIRE_RL_wci_respF_deq = 1'b1 ; + + // rule RL_wci_sThreadBusy_reg + assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'b1 ; + + // rule RL_wci_sFlagReg__dreg_update + assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'b1 ; + + // rule RL_wsi_Es_doAlways + assign CAN_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wsi_Es_doAlways = 1'b1 ; + + // rule RL_wsiS_update_statusR + assign CAN_FIRE_RL_wsiS_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiS_update_statusR = 1'b1 ; + + // rule RL_wsiS_inc_tBusyCount + assign CAN_FIRE_RL_wsiS_inc_tBusyCount = + wsiS_operateD && wsiS_peerIsReady && + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 ; + assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // rule RL_wsiS_reqFifo_enq + assign CAN_FIRE_RL_wsiS_reqFifo_enq = + wsiS_operateD && wsiS_peerIsReady && + wsiS_wsiReq__wget[60:58] == 3'b001 ; + assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // rule RL_wsiS_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wsiM_update_statusR + assign CAN_FIRE_RL_wsiM_update_statusR = 1'b1 ; + assign WILL_FIRE_RL_wsiM_update_statusR = 1'b1 ; + + // rule RL_wsiM_inc_tBusyCount + assign CAN_FIRE_RL_wsiM_inc_tBusyCount = + wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // rule RL_wsiM_reqFifo_deq + assign CAN_FIRE_RL_wsiM_reqFifo_deq = + wsiM_reqFifo_c_r != 2'b00 && !wsiM_sThreadBusy_d ; + assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ; + + // rule RL_wsiM_sThreadBusy_reg + assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'b1 ; + + // rule RL_wsiM_peerIsReady__dreg_update + assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_operating_actions + assign CAN_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + assign WILL_FIRE_RL_operating_actions = wci_cState == 3'b010 ; + + // rule RL_wsiS_operateD__dreg_update + assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'b1 ; + + // rule RL_wsiM_operateD__dreg_update + assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'b1 ; + + // rule RL_wmrd_mesgBodyResponse + assign CAN_FIRE_RL_wmrd_mesgBodyResponse = + wmi_respF__EMPTY_N && (smaCtrl[4] || wsiM_reqFifo_c_r != 2'b10) && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 || + smaCtrl[3:0] == 4'h9) && + unrollCnt != 16'b0000000000000000 ; + assign WILL_FIRE_RL_wmrd_mesgBodyResponse = + CAN_FIRE_RL_wmrd_mesgBodyResponse ; + + // rule RL_wmwt_messagePushImprecise + assign CAN_FIRE_RL_wmwt_messagePushImprecise = + wmi_reqF_c_r != 2'b10 && wmi_dhF_c_r != 2'b10 && + wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165 && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + readyToPush && + impreciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushImprecise = + CAN_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_messagePushPrecise + assign CAN_FIRE_RL_wmwt_messagePushPrecise = + wmi_dhF_c_r != 2'b10 && wsiS_reqFifo__EMPTY_N && wmi_operateD && + wmi_peerIsReady && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + wsiWordsRemain != 12'b000000000000 && + mesgReqValid && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_messagePushPrecise = + CAN_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_requestPrecise + assign CAN_FIRE_RL_wmwt_requestPrecise = + wmi_reqF_c_r != 2'b10 && wmi_mFlagF_c_r != 2'b10 && wmi_operateD && + wmi_peerIsReady && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + readyToRequest && + preciseBurst ; + assign WILL_FIRE_RL_wmwt_requestPrecise = + CAN_FIRE_RL_wmwt_requestPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // rule RL_wmwt_messageFinalize + assign CAN_FIRE_RL_wmwt_messageFinalize = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + mesgLength[14] && + !doAbort && + (preciseBurst && wsiWordsRemain == 12'b000000000000 || + impreciseBurst && endOfMessage) ; + assign WILL_FIRE_RL_wmwt_messageFinalize = + CAN_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_mesgBegin + assign CAN_FIRE_RL_wmwt_mesgBegin = + wsiS_reqFifo__EMPTY_N && wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + !wmi_sThreadBusy_d && + !wmi_sDataThreadBusy_d && + !opcode[8] ; + assign WILL_FIRE_RL_wmwt_mesgBegin = + CAN_FIRE_RL_wmwt_mesgBegin && + !WILL_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise && + !WILL_FIRE_RL_wmwt_messageFinalize ; + + // rule RL_wmwt_doAbort + assign CAN_FIRE_RL_wmwt_doAbort = + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) && + doAbort ; + assign WILL_FIRE_RL_wmwt_doAbort = CAN_FIRE_RL_wmwt_doAbort ; + + // rule RL_wmi_Em_doAlways + assign CAN_FIRE_RL_wmi_Em_doAlways = 1'b1 ; + assign WILL_FIRE_RL_wmi_Em_doAlways = 1'b1 ; + + // rule RL_wci_Es_doAlways_Req + assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'b1 ; + + // rule RL_wci_reqF_enq + assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq__wget[59:57] != 3'b000 ; + assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ; + + // rule RL_wsipass_doMessagePush + assign CAN_FIRE_RL_wsipass_doMessagePush = + wsiS_reqFifo__EMPTY_N && + (smaCtrl[4] || wsiM_reqFifo_c_r != 2'b10) && + wci_cState == 3'b010 && + (smaCtrl[3:0] == 4'h0 || smaCtrl[3:0] == 4'h3) ; + assign WILL_FIRE_RL_wsipass_doMessagePush = + CAN_FIRE_RL_wsipass_doMessagePush && + !WILL_FIRE_RL_wmwt_messagePushPrecise && + !WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // rule RL_wci_cfwr + assign CAN_FIRE_RL_wci_cfwr = + wci_respF_c_r != 2'b10 && wci_reqF__EMPTY_N && + wci_wci_cfwr_pw__whas ; + assign WILL_FIRE_RL_wci_cfwr = + CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start && + !WILL_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_reqF__updateLevelCounter + assign CAN_FIRE_RL_wci_reqF__updateLevelCounter = + (wci_wciReq__wget[59:57] != 3'b000) != wci_reqF_r_deq__whas ; + assign WILL_FIRE_RL_wci_reqF__updateLevelCounter = + CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // rule RL_wsiS_reqFifo__updateLevelCounter + assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq__whas ; + assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // rule RL_wsiM_reqFifo_both + assign CAN_FIRE_RL_wsiM_reqFifo_both = + ((wsiM_reqFifo_c_r == 2'b01) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b10 || wsiM_reqFifo_x_wire__whas) && + CAN_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ; + + // rule RL_wsiM_reqFifo_decCtr + assign CAN_FIRE_RL_wsiM_reqFifo_decCtr = + CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing__whas ; + assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ; + + // rule RL_wsiM_reqFifo_incCtr + assign CAN_FIRE_RL_wsiM_reqFifo_incCtr = + ((wsiM_reqFifo_c_r == 2'b00) ? + wsiM_reqFifo_x_wire__whas : + wsiM_reqFifo_c_r != 2'b01 || wsiM_reqFifo_x_wire__whas) && + wsiM_reqFifo_enqueueing__whas && + !CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ; + + // rule RL_mesgPreRequest__dreg_update + assign CAN_FIRE_RL_mesgPreRequest__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_mesgPreRequest__dreg_update = 1'b1 ; + + // rule RL_fabRespCredit_accumulate + assign CAN_FIRE_RL_fabRespCredit_accumulate = 1'b1 ; + assign WILL_FIRE_RL_fabRespCredit_accumulate = 1'b1 ; + + // rule RL_wci_ctrl_IsO + assign CAN_FIRE_RL_wci_ctrl_IsO = + wci_wci_ctrl_pw__whas && WILL_FIRE_RL_wci_ctl_op_start && + wci_cState == 3'b001 && + wci_reqF__D_OUT[36:34] == 3'b001 ; + assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ; + + // rule RL_wci_ctl_op_complete + assign CAN_FIRE_RL_wci_ctl_op_complete = + wci_respF_c_r != 2'b10 && wci_ctlOpActive && wci_ctlAckReg ; + assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ; + + // rule RL_wci_ctlAckReg__dreg_update + assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'b1 ; + + // rule RL_wci_respF_both + assign CAN_FIRE_RL_wci_respF_both = + ((wci_respF_c_r == 2'b01) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b10 || wci_respF_x_wire__whas) && + wci_respF_c_r != 2'b00 && + wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ; + + // rule RL_wci_respF_decCtr + assign CAN_FIRE_RL_wci_respF_decCtr = + wci_respF_c_r != 2'b00 && !wci_respF_enqueueing__whas ; + assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ; + + // rule RL_wci_respF_incCtr + assign CAN_FIRE_RL_wci_respF_incCtr = + ((wci_respF_c_r == 2'b00) ? + wci_respF_x_wire__whas : + wci_respF_c_r != 2'b01 || wci_respF_x_wire__whas) && + wci_respF_enqueueing__whas && + !(wci_respF_c_r != 2'b00) ; + assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ; + + // rule RL_wmi_dhF_deq + assign CAN_FIRE_RL_wmi_dhF_deq = !wmi_sDataThreadBusy_d ; + assign WILL_FIRE_RL_wmi_dhF_deq = CAN_FIRE_RL_wmi_dhF_deq ; + + // rule RL_wmi_respAdvance + assign CAN_FIRE_RL_wmi_respAdvance = + wmi_respF__FULL_N && wmi_operateD && wmi_peerIsReady && + wmi_wmiResponse__wget[33:32] != 2'b00 ; + assign WILL_FIRE_RL_wmi_respAdvance = CAN_FIRE_RL_wmi_respAdvance ; + + // rule RL_wmi_reqF_deq + assign CAN_FIRE_RL_wmi_reqF_deq = !wmi_sThreadBusy_d ; + assign WILL_FIRE_RL_wmi_reqF_deq = CAN_FIRE_RL_wmi_reqF_deq ; + + // rule RL_wmi_peerIsReady__dreg_update + assign CAN_FIRE_RL_wmi_peerIsReady__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_peerIsReady__dreg_update = 1'b1 ; + + // rule RL_wmi_operateD__dreg_update + assign CAN_FIRE_RL_wmi_operateD__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_operateD__dreg_update = 1'b1 ; + + // rule RL_wmi_sDataThreadBusy_d__dreg_update + assign CAN_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_sDataThreadBusy_d__dreg_update = 1'b1 ; + + // rule RL_wmi_sThreadBusy_d__dreg_update + assign CAN_FIRE_RL_wmi_sThreadBusy_d__dreg_update = 1'b1 ; + assign WILL_FIRE_RL_wmi_sThreadBusy_d__dreg_update = 1'b1 ; + + // rule RL_wmi_dhF_decCtr + assign CAN_FIRE_RL_wmi_dhF_decCtr = + wmi_dhF_dequeueing__whas && !wmi_dhF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_dhF_decCtr = CAN_FIRE_RL_wmi_dhF_decCtr ; + + // rule RL_wmi_dhF_both + assign CAN_FIRE_RL_wmi_dhF_both = + ((wmi_dhF_c_r == 2'b01) ? + wmi_dhF_enqueueing__whas : + wmi_dhF_c_r != 2'b10 || wmi_dhF_enqueueing__whas) && + wmi_dhF_dequeueing__whas && + wmi_dhF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_dhF_both = CAN_FIRE_RL_wmi_dhF_both ; + + // rule RL_wmi_dhF_incCtr + assign CAN_FIRE_RL_wmi_dhF_incCtr = + ((wmi_dhF_c_r == 2'b00) ? + wmi_dhF_enqueueing__whas : + wmi_dhF_c_r != 2'b01 || wmi_dhF_enqueueing__whas) && + wmi_dhF_enqueueing__whas && + !wmi_dhF_dequeueing__whas ; + assign WILL_FIRE_RL_wmi_dhF_incCtr = CAN_FIRE_RL_wmi_dhF_incCtr ; + + // rule RL_wmi_mFlagF_both + assign CAN_FIRE_RL_wmi_mFlagF_both = + ((wmi_mFlagF_c_r == 2'b01) ? + wmi_mFlagF_enqueueing__whas : + wmi_mFlagF_c_r != 2'b10 || wmi_mFlagF_enqueueing__whas) && + wmi_mFlagF_dequeueing__whas && + wmi_mFlagF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_mFlagF_both = CAN_FIRE_RL_wmi_mFlagF_both ; + + // rule RL_wmi_mFlagF_decCtr + assign CAN_FIRE_RL_wmi_mFlagF_decCtr = + wmi_mFlagF_dequeueing__whas && !wmi_mFlagF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_mFlagF_decCtr = CAN_FIRE_RL_wmi_mFlagF_decCtr ; + + // rule RL_wmi_mFlagF_incCtr + assign CAN_FIRE_RL_wmi_mFlagF_incCtr = + ((wmi_mFlagF_c_r == 2'b00) ? + wmi_mFlagF_enqueueing__whas : + wmi_mFlagF_c_r != 2'b01 || wmi_mFlagF_enqueueing__whas) && + wmi_mFlagF_enqueueing__whas && + !wmi_mFlagF_dequeueing__whas ; + assign WILL_FIRE_RL_wmi_mFlagF_incCtr = CAN_FIRE_RL_wmi_mFlagF_incCtr ; + + // rule RL_wmi_reqF_both + assign CAN_FIRE_RL_wmi_reqF_both = + ((wmi_reqF_c_r == 2'b01) ? + wmi_reqF_x_wire__whas : + wmi_reqF_c_r != 2'b10 || wmi_reqF_x_wire__whas) && + wmi_reqF_dequeueing__whas && + wmi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_reqF_both = CAN_FIRE_RL_wmi_reqF_both ; + + // rule RL_wmi_reqF_incCtr + assign CAN_FIRE_RL_wmi_reqF_incCtr = + ((wmi_reqF_c_r == 2'b00) ? + wmi_reqF_x_wire__whas : + wmi_reqF_c_r != 2'b01 || wmi_reqF_x_wire__whas) && + wmi_reqF_enqueueing__whas && + !wmi_reqF_dequeueing__whas ; + assign WILL_FIRE_RL_wmi_reqF_incCtr = CAN_FIRE_RL_wmi_reqF_incCtr ; + + // rule RL_wmi_reqF_decCtr + assign CAN_FIRE_RL_wmi_reqF_decCtr = + wmi_reqF_dequeueing__whas && !wmi_reqF_enqueueing__whas ; + assign WILL_FIRE_RL_wmi_reqF_decCtr = CAN_FIRE_RL_wmi_reqF_decCtr ; + + // inputs to muxes for submodule ports + assign MUX_wci_illegalEdge__write_1__SEL_1 = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ; + assign MUX_wci_illegalEdge__write_1__VAL_2 = + wci_reqF__D_OUT[36:34] != 3'b100 && wci_reqF__D_OUT[36:34] != 3'b101 && + wci_reqF__D_OUT[36:34] != 3'b110 ; + assign MUX_wci_respF_c_r__write_1__VAL_1 = wci_respF_c_r - 2'b01 ; + assign MUX_wci_respF_c_r__write_1__VAL_2 = wci_respF_c_r + 2'b01 ; + assign MUX_wci_respF_x_wire__wset_1__VAL_1 = + wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ; + assign MUX_wci_illegalEdge__write_1__SEL_2 = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState != 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && wci_cState != 3'b001 && + wci_cState != 3'b011 || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState != 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && wci_cState != 3'b011 && + wci_cState != 3'b010 && + wci_cState != 3'b001 || + wci_reqF__D_OUT[36:34] == 3'b100 || + wci_reqF__D_OUT[36:34] == 3'b101 || + wci_reqF__D_OUT[36:34] == 3'b110 || + wci_reqF__D_OUT[36:34] == 3'b111) ; + assign MUX_wci_respF_q_0__write_1__SEL_1 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 ; + assign MUX_wci_respF_q_1__write_1__SEL_1 = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_1 = wsiM_reqFifo_c_r - 2'b01 ; + assign MUX_wsiM_reqFifo_c_r__write_1__VAL_2 = wsiM_reqFifo_c_r + 2'b01 ; + assign MUX_wci_respF_x_wire__wset_1__VAL_2 = { 2'b01, x_data__h15447 } ; + always@(WILL_FIRE_RL_wci_ctl_op_complete or + MUX_wci_respF_x_wire__wset_1__VAL_1 or + WILL_FIRE_RL_wci_cfrd or + MUX_wci_respF_x_wire__wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wci_ctl_op_complete: + MUX_wci_respF_q_0__write_1__VAL_1 = + MUX_wci_respF_x_wire__wset_1__VAL_1; + WILL_FIRE_RL_wci_cfrd: + MUX_wci_respF_q_0__write_1__VAL_1 = + MUX_wci_respF_x_wire__wset_1__VAL_2; + WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0__write_1__VAL_1 = 34'h1C0DE4201; + default: MUX_wci_respF_q_0__write_1__VAL_1 = + 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wci_respF_q_0__write_1__VAL_2 = + (wci_respF_c_r == 2'b01) ? + MUX_wci_respF_q_0__write_1__VAL_1 : + wci_respF_q_1 ; + assign MUX_wci_respF_q_1__write_1__VAL_2 = + (wci_respF_c_r == 2'b10) ? + MUX_wci_respF_q_0__write_1__VAL_1 : + 34'h0AAAAAAAA ; + assign MUX_wsiM_reqFifo_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 ; + assign MUX_wsiM_reqFifo_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 ; + assign MUX_endOfMessage__write_1__SEL_1 = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 ; + assign MUX_impreciseBurst__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] ; + assign MUX_lastMesg__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_requestPrecise || WILL_FIRE_RL_wmrd_mesgBegin ; + assign MUX_mesgCount__write_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 ; + assign MUX_mesgLength__write_1__SEL_2 = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] ; + assign MUX_wmi_mFlagF_x_wire__wset_1__SEL_2 = + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18884 ; + assign MUX_wsiM_reqFifo_x_wire__wset_1__SEL_1 = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] ; + assign MUX_fabRespCredit_value__write_1__VAL_2 = + fabRespCredit_value + + (CAN_FIRE_RL_wmrd_mesgBodyRequest ? b__h13937 : 4'b0000) + + (CAN_FIRE_RL_wmrd_mesgBodyResponse ? 4'b0001 : 4'b0000) ; + assign MUX_fabWordsRemain__write_1__VAL_1 = + (wmi_sFlagReg[23:0] == 24'b000000000000000000000000) ? 14'b00000000000001 : wmi_sFlagReg[15:2] ; + assign MUX_fabWordsRemain__write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ; + assign MUX_mesgCount__write_1__VAL_1 = mesgCount + 32'b00000000000000000000000000000001 ; + assign MUX_mesgLength__write_1__VAL_2 = + (wsiS_reqFifo__D_OUT[11:8] == 4'b0000) ? + 15'b100000000000000 : + { 1'b1, wsiS_reqFifo__D_OUT[55:44], 2'b00 } ; + assign MUX_mesgLength__write_1__VAL_4 = { 1'b1, mlp1B__h16631 } ; + assign MUX_mesgReqAddr__write_1__VAL_2 = + mesgReqAddr + { fabWordsCurReq[11:0], 2'b00 } ; + assign MUX_opcode__write_1__VAL_2 = { 1'b1, wsiS_reqFifo__D_OUT[7:0] } ; + assign MUX_thisMesg__write_1__VAL_1 = + { mesgCount[7:0], mesgMetaF_opcode__h16809, x_length__h17087 } ; + assign MUX_thisMesg__write_1__VAL_2 = + { mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ; + assign MUX_unrollCnt__write_1__VAL_2 = unrollCnt - 16'b0000000000000001 ; + assign MUX_unrollCnt__write_1__VAL_1 = + (wmi_sFlagReg[23:0] == 24'b000000000000000000000000) ? 16'b0000000000000001 : wmi_sFlagReg[17:2] ; + assign MUX_wmi_dhF_c_r__write_1__VAL_1 = wmi_dhF_c_r - 2'b01 ; + assign MUX_wmi_dhF_c_r__write_1__VAL_2 = wmi_dhF_c_r + 2'b01 ; + assign MUX_wmi_dhF_x_wire__wset_1__VAL_1 = + { 1'b1, + wsiWordsRemain == 12'b000000000001, + wsiS_reqFifo__D_OUT[43:12], + 4'b1111 } ; + assign MUX_wmi_dhF_x_wire__wset_1__VAL_2 = + { 1'b1, x__h16715, wsiS_reqFifo__D_OUT[43:12], 4'b1111 } ; + assign MUX_wmi_dhF_q_0__write_1__VAL_2 = + WILL_FIRE_RL_wmwt_messagePushPrecise ? + MUX_wmi_dhF_x_wire__wset_1__VAL_1 : + MUX_wmi_dhF_x_wire__wset_1__VAL_2 ; + assign MUX_wmi_dhF_q_0__write_1__VAL_1 = + (wmi_dhF_c_r == 2'b01) ? + MUX_wmi_dhF_q_0__write_1__VAL_2 : + wmi_dhF_q_1 ; + assign MUX_wmi_dhF_q_1__write_1__VAL_1 = + (wmi_dhF_c_r == 2'b10) ? + MUX_wmi_dhF_q_0__write_1__VAL_2 : + 38'h0AAAAAAAAA ; + assign MUX_wmi_mFlagF_c_r__write_1__VAL_1 = wmi_mFlagF_c_r - 2'b01 ; + assign MUX_wmi_mFlagF_c_r__write_1__VAL_2 = wmi_mFlagF_c_r + 2'b01 ; + assign MUX_wmi_mFlagF_x_wire__wset_1__VAL_1 = + { mesgMetaF_opcode__h16809, mesgMetaF_length__h16810 } ; + assign MUX_wmi_mFlagF_x_wire__wset_1__VAL_3 = + { mesgMetaF_opcode__h16809, mesgMetaF_length__h17723 } ; + assign MUX_wmi_mFlagF_q_0__write_1__VAL_1 = + (wmi_mFlagF_c_r == 2'b01) ? value__h6065 : wmi_mFlagF_q_1 ; + assign MUX_wmi_mFlagF_q_1__write_1__VAL_1 = + (wmi_mFlagF_c_r == 2'b10) ? value__h6065 : 32'b00000000000000000000000000000000 ; + assign MUX_wmi_reqF_c_r__write_1__VAL_1 = wmi_reqF_c_r - 2'b01 ; + assign MUX_wmi_reqF_c_r__write_1__VAL_2 = wmi_reqF_c_r + 2'b01 ; + assign MUX_wmi_reqF_x_wire__wset_1__VAL_1 = { 20'b00111000000000000000, bl__h17580 } ; + assign MUX_wmi_reqF_x_wire__wset_1__VAL_2 = + { 4'b0101, x__h18884, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ; + assign MUX_wmi_reqF_x_wire__wset_1__VAL_3 = + { 4'b0011, x__h16715, 1'b0, addr__h16647, 12'b000000000001 } ; + always@(WILL_FIRE_RL_wmwt_requestPrecise or + MUX_wmi_reqF_x_wire__wset_1__VAL_1 or + WILL_FIRE_RL_wmrd_mesgBodyRequest or + MUX_wmi_reqF_x_wire__wset_1__VAL_2 or + WILL_FIRE_RL_wmwt_messagePushImprecise or + MUX_wmi_reqF_x_wire__wset_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmwt_requestPrecise: + MUX_wmi_reqF_q_0__write_1__VAL_1 = MUX_wmi_reqF_x_wire__wset_1__VAL_1; + WILL_FIRE_RL_wmrd_mesgBodyRequest: + MUX_wmi_reqF_q_0__write_1__VAL_1 = MUX_wmi_reqF_x_wire__wset_1__VAL_2; + WILL_FIRE_RL_wmwt_messagePushImprecise: + MUX_wmi_reqF_q_0__write_1__VAL_1 = MUX_wmi_reqF_x_wire__wset_1__VAL_3; + default: MUX_wmi_reqF_q_0__write_1__VAL_1 = + 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign MUX_wmi_reqF_q_0__write_1__VAL_2 = + (wmi_reqF_c_r == 2'b01) ? + MUX_wmi_reqF_q_0__write_1__VAL_1 : + wmi_reqF_q_1 ; + assign MUX_wmi_reqF_q_1__write_1__VAL_2 = + (wmi_reqF_c_r == 2'b10) ? + MUX_wmi_reqF_q_0__write_1__VAL_1 : + 32'b00001010101010101010101010101010 ; + assign MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 = + { 3'b001, + unrollCnt == 16'b0000000000000001, + !smaCtrl[5], + x_burstLength__h18559, + wmi_respF__D_OUT[31:0], + x_byteEn__h18561, + thisMesg[23:16] } ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_2 = + MUX_wsiM_reqFifo_x_wire__wset_1__SEL_1 ? + MUX_wsiM_reqFifo_x_wire__wset_1__VAL_1 : + wsiS_reqFifo__D_OUT ; + assign MUX_wsiM_reqFifo_q_0__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b01) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + wsiM_reqFifo_q_1 ; + assign MUX_wsiM_reqFifo_q_1__write_1__VAL_1 = + (wsiM_reqFifo_c_r == 2'b10) ? + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 : + 61'h00000AAAAAAAAA00 ; + assign MUX_wsiWordsRemain__write_1__VAL_2 = wsiWordsRemain - 12'b000000000001 ; + assign MUX_wmi_reqF_q_0__write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b00 ; + assign MUX_wmi_reqF_q_1__write_1__SEL_1 = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b01 ; + assign MUX_wmi_mFlagF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b00 ; + assign MUX_wmi_mFlagF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b01 ; + assign MUX_wmi_dhF_q_0__write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b00 ; + assign MUX_wmi_dhF_q_1__write_1__SEL_2 = + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b01 ; + + // inlined wires + assign wci_wciReq__wget = + { wciS0_MCmd, + wciS0_MAddrSpace, + wciS0_MByteEn, + wciS0_MAddr, + wciS0_MData } ; + assign wci_wciReq__whas = 1'b1 ; + assign wci_reqF_r_enq__whas = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF_r_clr__whas = 1'b0 ; + assign wci_respF_dequeueing__whas = wci_respF_c_r != 2'b00 ; + assign wci_wEdge__wget = wci_reqF__D_OUT[36:34] ; + assign wci_sThreadBusy_pw__whas = 1'b0 ; + assign wci_sFlagReg_1__wget = 1'b0 ; + assign wci_sFlagReg_1__whas = 1'b0 ; + assign wci_wci_cfwr_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b001 ; + assign wci_wci_cfrd_pw__whas = + wci_reqF__EMPTY_N && wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_wci_ctrl_pw__whas = + wci_reqF__EMPTY_N && !wci_reqF__D_OUT[56] && + wci_reqF__D_OUT[59:57] == 3'b010 ; + assign wci_reqF_r_deq__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_respF_enqueueing__whas = + WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr || + WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_respF_x_wire__whas = + WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd || + WILL_FIRE_RL_wci_cfwr ; + assign wci_ctlAckReg_1__wget = 1'b1 ; + assign wci_wEdge__whas = WILL_FIRE_RL_wci_ctl_op_start ; + assign wci_ctlAckReg_1__whas = + WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO || + WILL_FIRE_RL_wci_ctrl_EiI ; + assign wsiM_reqFifo_dequeueing__whas = CAN_FIRE_RL_wsiM_reqFifo_deq ; + assign wsiM_sThreadBusy_pw__whas = wsiM1_SThreadBusy ; + assign wsiM_operateD_1__wget = 1'b1 ; + assign wsiM_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiM_peerIsReady_1__wget = 1'b1 ; + assign wsiM_peerIsReady_1__whas = wsiM1_SReset_n ; + assign wsiM_extStatusW__wget = + { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ; + assign wsiS_wsiReq__wget = + { wsiS1_MCmd, + wsiS1_MReqLast, + wsiS1_MBurstPrecise, + wsiS1_MBurstLength, + wsiS1_MData, + wsiS1_MByteEn, + wsiS1_MReqInfo } ; + assign wsiS_wsiReq__whas = 1'b1 ; + assign wsiS_reqFifo_r_enq__whas = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo_r_clr__whas = 1'b0 ; + assign wsiS_operateD_1__wget = 1'b1 ; + assign wsiS_operateD_1__whas = wci_cState == 3'b010 ; + assign wsiS_peerIsReady_1__wget = 1'b1 ; + assign wsiS_extStatusW__wget = + { wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ; + assign wsiS_peerIsReady_1__whas = wsiS1_MReset_n ; + assign wsi_Es_mCmd_w__wget = wsiS1_MCmd ; + assign wsi_Es_mReqLast_w__whas = wsiS1_MReqLast ; + assign wsi_Es_mCmd_w__whas = 1'b1 ; + assign wsi_Es_mBurstPrecise_w__whas = wsiS1_MBurstPrecise ; + assign wsi_Es_mBurstLength_w__whas = 1'b1 ; + assign wsi_Es_mBurstLength_w__wget = wsiS1_MBurstLength ; + assign wsi_Es_mData_w__wget = wsiS1_MData ; + assign wsi_Es_mData_w__whas = 1'b1 ; + assign wsi_Es_mByteEn_w__wget = wsiS1_MByteEn ; + assign wsi_Es_mByteEn_w__whas = 1'b1 ; + assign wsi_Es_mReqInfo_w__whas = 1'b1 ; + assign wsi_Es_mReqInfo_w__wget = wsiS1_MReqInfo ; + assign wsi_Es_mDataInfo_w__whas = 1'b1 ; + assign wci_respF_x_wire__wget = MUX_wci_respF_q_0__write_1__VAL_1 ; + assign wsiM_reqFifo_enqueueing__whas = + (WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmrd_mesgBodyResponse) && + !smaCtrl[4] ; + assign wsiM_reqFifo_x_wire__whas = + WILL_FIRE_RL_wmrd_mesgBodyResponse && !smaCtrl[4] || + WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ; + assign wsiS_reqFifo_r_deq__whas = + WILL_FIRE_RL_wsipass_doMessagePush || + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign wsiM_reqFifo_x_wire__wget = MUX_wsiM_reqFifo_q_0__write_1__VAL_2 ; + assign wmi_reqF_enqueueing__whas = + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise || + WILL_FIRE_RL_wmrd_mesgBodyRequest ; + assign wmi_reqF_x_wire__wget = MUX_wmi_reqF_q_0__write_1__VAL_1 ; + assign wmi_reqF_x_wire__whas = + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wmrd_mesgBodyRequest || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign wmi_reqF_dequeueing__whas = + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_c_r != 2'b00 ; + assign wmi_mFlagF_x_wire__wget = value__h6065 ; + assign wmi_mFlagF_enqueueing__whas = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18884 || + WILL_FIRE_RL_wmwt_requestPrecise ; + assign wmi_mFlagF_x_wire__whas = wmi_mFlagF_enqueueing__whas ; + assign wmi_mFlagF_dequeueing__whas = + WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] && + wmi_mFlagF_c_r != 2'b00 ; + assign wmi_dhF_enqueueing__whas = + WILL_FIRE_RL_wmwt_messagePushPrecise || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + assign wmi_dhF_x_wire__wget = MUX_wmi_dhF_q_0__write_1__VAL_2 ; + assign wmi_dhF_x_wire__whas = wmi_dhF_enqueueing__whas ; + assign wmi_dhF_dequeueing__whas = + WILL_FIRE_RL_wmi_dhF_deq && wmi_dhF_c_r != 2'b00 ; + assign wmi_wmiResponse__wget = { wmiM_SResp, wmiM_SData } ; + assign wmi_wmiResponse__whas = 1'b1 ; + assign wmi_sThreadBusy_d_1__wget = 1'b1 ; + assign wmi_sThreadBusy_d_1__whas = wmiM_SThreadBusy ; + assign wmi_sDataThreadBusy_d_1__wget = 1'b1 ; + assign wmi_operateD_1__wget = 1'b1 ; + assign wmi_sDataThreadBusy_d_1__whas = wmiM_SDataThreadBusy ; + assign wmi_operateD_1__whas = wci_cState == 3'b010 ; + assign wmi_peerIsReady_1__whas = wmiM_SReset_n ; + assign wmi_peerIsReady_1__wget = 1'b1 ; + assign fabRespCredit_acc_v1__wget = b__h13937 ; + assign fabRespCredit_acc_v2__wget = 4'b0001 ; + assign fabRespCredit_acc_v1__whas = CAN_FIRE_RL_wmrd_mesgBodyRequest ; + assign fabRespCredit_acc_v2__whas = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + assign mesgPreRequest_1__wget = 1'b1 ; + assign mesgPreRequest_1__whas = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ; + assign wci_Es_mCmd_w__wget = wciS0_MCmd ; + assign wci_Es_mAddrSpace_w__wget = wciS0_MAddrSpace ; + assign wci_Es_mCmd_w__whas = 1'b1 ; + assign wci_Es_mAddrSpace_w__whas = 1'b1 ; + assign wci_Es_mAddr_w__wget = wciS0_MAddr ; + assign wci_Es_mAddr_w__whas = 1'b1 ; + assign wci_Es_mData_w__wget = wciS0_MData ; + assign wci_Es_mData_w__whas = 1'b1 ; + assign wci_Es_mByteEn_w__whas = 1'b1 ; + assign wci_Es_mByteEn_w__wget = wciS0_MByteEn ; + assign wmi_Em_sResp_w__wget = wmiM_SResp ; + assign wmi_Em_sResp_w__whas = 1'b1 ; + assign wmi_Em_sData_w__wget = wmiM_SData ; + assign wmi_Em_sData_w__whas = 1'b1 ; + + // register abortCount + assign abortCount__D_IN = abortCount + 32'b00000000000000000000000000000001 ; + assign abortCount__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register doAbort + assign doAbort__D_IN = 1'b0 ; + assign doAbort__EN = CAN_FIRE_RL_wmwt_doAbort ; + + // register endOfMessage + assign endOfMessage__D_IN = MUX_endOfMessage__write_1__SEL_1 ; + assign endOfMessage__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_messageFinalize ; + + // register errCount + assign errCount__D_IN = errCount + 32'b00000000000000000000000000000001 ; + assign errCount__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + wsiS_reqFifo__D_OUT[43:12] != valExpect && + (!x__h16715 || wsiS_reqFifo__D_OUT[11:8] != 4'b0000) ; + + // register fabRespCredit_value + assign fabRespCredit_value__D_IN = + WILL_FIRE_RL_wci_ctrl_IsO ? + 4'b0010 : + MUX_fabRespCredit_value__write_1__VAL_2 ; + assign fabRespCredit_value__EN = 1'b1 ; + + // register fabWordsCurReq + assign fabWordsCurReq__D_IN = + (fabWordsRemain <= b__h19084) ? fabWordsRemain : b__h19084 ; + assign fabWordsCurReq__EN = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ; + + // register fabWordsRemain + assign fabWordsRemain__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + MUX_fabWordsRemain__write_1__VAL_1 : + MUX_fabWordsRemain__write_1__VAL_2 ; + assign fabWordsRemain__EN = + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyRequest ; + + // register firstMsgReq + assign firstMsgReq__EN = 1'b0 ; + assign firstMsgReq__D_IN = 1'b0 ; + + // register impreciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: impreciseBurst__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: impreciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: impreciseBurst__D_IN = 1'b0; + default: impreciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign impreciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register lastMesg + assign lastMesg__D_IN = + (MUX_endOfMessage__write_1__SEL_1 || + MUX_lastMesg__write_1__SEL_2) ? + thisMesg : + 32'hFEFEFFFE ; + assign lastMesg__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register mesgCount + always@(MUX_mesgCount__write_1__SEL_1 or + MUX_mesgCount__write_1__VAL_1 or + WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO) + begin + case (1'b1) // synopsys parallel_case + MUX_mesgCount__write_1__SEL_1: + mesgCount__D_IN = MUX_mesgCount__write_1__VAL_1; + WILL_FIRE_RL_wmwt_messageFinalize: + mesgCount__D_IN = MUX_mesgCount__write_1__VAL_1; + WILL_FIRE_RL_wci_ctrl_IsO: mesgCount__D_IN = 32'b00000000000000000000000000000000; + default: mesgCount__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign mesgCount__EN = + WILL_FIRE_RL_wmrd_mesgBodyResponse && unrollCnt == 16'b0000000000000001 || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register mesgLength + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or + MUX_mesgLength__write_1__VAL_2 or + WILL_FIRE_RL_wmwt_messageFinalize or + MUX_endOfMessage__write_1__SEL_1 or MUX_mesgLength__write_1__VAL_4) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: mesgLength__D_IN = 15'b010101010101010; + MUX_mesgLength__write_1__SEL_2: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_2; + WILL_FIRE_RL_wmwt_messageFinalize: mesgLength__D_IN = 15'b010101010101010; + MUX_endOfMessage__write_1__SEL_1: + mesgLength__D_IN = MUX_mesgLength__write_1__VAL_4; + default: mesgLength__D_IN = 15'b010101010101010 /* unspecified value */ ; + endcase + assign mesgLength__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register mesgLengthSoFar + assign mesgLengthSoFar__D_IN = + MUX_impreciseBurst__write_1__SEL_2 ? 14'b00000000000000 : mlp1__h16630 ; + assign mesgLengthSoFar__EN = + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messagePushImprecise ; + + // register mesgPreRequest + assign mesgPreRequest__D_IN = WILL_FIRE_RL_wmrd_mesgBodyPreRequest ; + assign mesgPreRequest__EN = 1'b1 ; + + // register mesgReqAddr + assign mesgReqAddr__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + 14'b00000000000000 : + MUX_mesgReqAddr__write_1__VAL_2 ; + assign mesgReqAddr__EN = + WILL_FIRE_RL_wmrd_mesgBodyRequest || + WILL_FIRE_RL_wmrd_mesgBegin ; + + // register mesgReqOK + assign mesgReqOK__D_IN = + WILL_FIRE_RL_wmrd_mesgBodyResponse || + WILL_FIRE_RL_wmrd_mesgBegin ; + assign mesgReqOK__EN = + WILL_FIRE_RL_wmrd_mesgBodyPreRequest || + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + + // register mesgReqValid + assign mesgReqValid__D_IN = !WILL_FIRE_RL_wmwt_messageFinalize ; + assign mesgReqValid__EN = + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register opcode + always@(WILL_FIRE_RL_wmwt_doAbort or + WILL_FIRE_RL_wmwt_mesgBegin or + MUX_opcode__write_1__VAL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: opcode__D_IN = 9'b010101010; + WILL_FIRE_RL_wmwt_mesgBegin: opcode__D_IN = MUX_opcode__write_1__VAL_2; + WILL_FIRE_RL_wmwt_messageFinalize: opcode__D_IN = 9'b010101010; + default: opcode__D_IN = 9'b010101010 /* unspecified value */ ; + endcase + assign opcode__EN = + WILL_FIRE_RL_wmwt_mesgBegin || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register preciseBurst + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_mesgLength__write_1__SEL_2 or WILL_FIRE_RL_wmwt_messageFinalize) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: preciseBurst__D_IN = 1'b0; + MUX_mesgLength__write_1__SEL_2: preciseBurst__D_IN = 1'b1; + WILL_FIRE_RL_wmwt_messageFinalize: preciseBurst__D_IN = 1'b0; + default: preciseBurst__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign preciseBurst__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messageFinalize || + WILL_FIRE_RL_wmwt_doAbort ; + + // register readyToPush + always@(WILL_FIRE_RL_wmwt_doAbort or + MUX_impreciseBurst__write_1__SEL_2 or + MUX_endOfMessage__write_1__SEL_1) + case (1'b1) + WILL_FIRE_RL_wmwt_doAbort: readyToPush__D_IN = 1'b0; + MUX_impreciseBurst__write_1__SEL_2: readyToPush__D_IN = 1'b1; + MUX_endOfMessage__write_1__SEL_1: readyToPush__D_IN = 1'b0; + default: readyToPush__D_IN = 1'b0 /* unspecified value */ ; + endcase + assign readyToPush__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_doAbort ; + + // register readyToRequest + assign readyToRequest__D_IN = MUX_mesgLength__write_1__SEL_2 ; + assign readyToRequest__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_requestPrecise ; + + // register smaCtrl + assign smaCtrl__D_IN = wci_reqF__D_OUT[31:0] ; + assign smaCtrl__EN = WILL_FIRE_RL_wci_cfwr && wci_reqF__D_OUT[39:32] == 8'h0 ; + + // register thisMesg + always@(MUX_endOfMessage__write_1__SEL_1 or + MUX_thisMesg__write_1__VAL_1 or + WILL_FIRE_RL_wmrd_mesgBegin or + MUX_thisMesg__write_1__VAL_2 or + WILL_FIRE_RL_wmwt_requestPrecise or WILL_FIRE_RL_wci_ctrl_IsO) + begin + case (1'b1) // synopsys parallel_case + MUX_endOfMessage__write_1__SEL_1: + thisMesg__D_IN = MUX_thisMesg__write_1__VAL_1; + WILL_FIRE_RL_wmrd_mesgBegin: + thisMesg__D_IN = MUX_thisMesg__write_1__VAL_2; + WILL_FIRE_RL_wmwt_requestPrecise: + thisMesg__D_IN = MUX_thisMesg__write_1__VAL_1; + WILL_FIRE_RL_wci_ctrl_IsO: thisMesg__D_IN = 32'hFEFEFFFE; + default: thisMesg__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign thisMesg__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && x__h16715 || + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmwt_requestPrecise || + WILL_FIRE_RL_wci_ctrl_IsO ; + + // register unrollCnt + assign unrollCnt__D_IN = + WILL_FIRE_RL_wmrd_mesgBegin ? + MUX_unrollCnt__write_1__VAL_1 : + MUX_unrollCnt__write_1__VAL_2 ; + assign unrollCnt__EN = + WILL_FIRE_RL_wmrd_mesgBegin || + WILL_FIRE_RL_wmrd_mesgBodyResponse ; + + // register valExpect + assign valExpect__D_IN = valExpect + 32'b00000000000000000000000000000001 ; + assign valExpect__EN = + WILL_FIRE_RL_wmwt_messagePushImprecise && + (!x__h16715 || wsiS_reqFifo__D_OUT[11:8] != 4'b0000) ; + + // register wci_cEdge + assign wci_cEdge__D_IN = wci_reqF__D_OUT[36:34] ; + assign wci_cEdge__EN = WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_cState + assign wci_cState__D_IN = wci_nState ; + assign wci_cState__EN = + WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ; + + // register wci_ctlAckReg + assign wci_ctlAckReg__D_IN = wci_ctlAckReg_1__whas ; + assign wci_ctlAckReg__EN = 1'b1 ; + + // register wci_ctlOpActive + assign wci_ctlOpActive__D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ; + assign wci_ctlOpActive__EN = + WILL_FIRE_RL_wci_ctl_op_complete || + WILL_FIRE_RL_wci_ctl_op_start ; + + // register wci_illegalEdge + assign wci_illegalEdge__D_IN = + !MUX_wci_illegalEdge__write_1__SEL_1 && + MUX_wci_illegalEdge__write_1__VAL_2 ; + assign wci_illegalEdge__EN = + WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge || + MUX_wci_illegalEdge__write_1__SEL_2 ; + + // register wci_nState + always@(wci_reqF__D_OUT) + begin + case (wci_reqF__D_OUT[36:34]) + 3'b000: wci_nState__D_IN = 3'b001; + 3'b001: wci_nState__D_IN = 3'b010; + 3'b010: wci_nState__D_IN = 3'b011; + default: wci_nState__D_IN = 3'b000; + endcase + end + assign wci_nState__EN = + WILL_FIRE_RL_wci_ctl_op_start && + (wci_reqF__D_OUT[36:34] == 3'b000 && wci_cState == 3'b000 || + wci_reqF__D_OUT[36:34] == 3'b001 && + (wci_cState == 3'b001 || wci_cState == 3'b011) || + wci_reqF__D_OUT[36:34] == 3'b010 && wci_cState == 3'b010 || + wci_reqF__D_OUT[36:34] == 3'b011 && + (wci_cState == 3'b011 || wci_cState == 3'b010 || + wci_cState == 3'b001)) ; + + // register wci_reqF_countReg + assign wci_reqF_countReg__D_IN = + (wci_wciReq__wget[59:57] != 3'b000) ? + wci_reqF_countReg + 2'b01 : + wci_reqF_countReg - 2'b01 ; + assign wci_reqF_countReg__EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ; + + // register wci_respF_c_r + assign wci_respF_c_r__D_IN = + WILL_FIRE_RL_wci_respF_decCtr ? + MUX_wci_respF_c_r__write_1__VAL_1 : + MUX_wci_respF_c_r__write_1__VAL_2 ; + assign wci_respF_c_r__EN = + WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ; + + // register wci_respF_q_0 + assign wci_respF_q_0__EN = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b00 || + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(MUX_wci_respF_q_0__write_1__SEL_1 or + MUX_wci_respF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_respF_q_0__write_1__SEL_1: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_0__D_IN = MUX_wci_respF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0__D_IN = wci_respF_q_1; + default: wci_respF_q_0__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_respF_q_1 + assign wci_respF_q_1__EN = + WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'b01 || + WILL_FIRE_RL_wci_respF_both || + WILL_FIRE_RL_wci_respF_decCtr ; + always@(MUX_wci_respF_q_1__write_1__SEL_1 or + MUX_wci_respF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wci_respF_both or + MUX_wci_respF_q_1__write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wci_respF_q_1__write_1__SEL_1: + wci_respF_q_1__D_IN = MUX_wci_respF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wci_respF_both: + wci_respF_q_1__D_IN = MUX_wci_respF_q_1__write_1__VAL_2; + WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1__D_IN = 34'h0AAAAAAAA; + default: wci_respF_q_1__D_IN = 34'h2AAAAAAAA /* unspecified value */ ; + endcase + end + + // register wci_sFlagReg + assign wci_sFlagReg__D_IN = 1'b0 ; + assign wci_sFlagReg__EN = 1'b1 ; + + // register wci_sThreadBusy_d + assign wci_sThreadBusy_d__D_IN = 1'b0 ; + assign wci_sThreadBusy_d__EN = 1'b1 ; + + // register wmi_busyWithMessage + assign wmi_busyWithMessage__D_IN = 1'b0 ; + assign wmi_busyWithMessage__EN = 1'b0 ; + + // register wmi_dhF_c_r + assign wmi_dhF_c_r__D_IN = + WILL_FIRE_RL_wmi_dhF_decCtr ? + MUX_wmi_dhF_c_r__write_1__VAL_1 : + MUX_wmi_dhF_c_r__write_1__VAL_2 ; + assign wmi_dhF_c_r__EN = + WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ; + + // register wmi_dhF_q_0 + always@(WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_0__write_1__VAL_1 or + MUX_wmi_dhF_q_0__write_1__SEL_2 or + MUX_wmi_dhF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_dhF_both: + wmi_dhF_q_0__D_IN = MUX_wmi_dhF_q_0__write_1__VAL_1; + MUX_wmi_dhF_q_0__write_1__SEL_2: + wmi_dhF_q_0__D_IN = MUX_wmi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0__D_IN = wmi_dhF_q_1; + default: wmi_dhF_q_0__D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_dhF_q_0__EN = + WILL_FIRE_RL_wmi_dhF_both || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b00 || + WILL_FIRE_RL_wmi_dhF_decCtr ; + + // register wmi_dhF_q_1 + always@(WILL_FIRE_RL_wmi_dhF_both or + MUX_wmi_dhF_q_1__write_1__VAL_1 or + MUX_wmi_dhF_q_1__write_1__SEL_2 or + MUX_wmi_dhF_q_0__write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_dhF_both: + wmi_dhF_q_1__D_IN = MUX_wmi_dhF_q_1__write_1__VAL_1; + MUX_wmi_dhF_q_1__write_1__SEL_2: + wmi_dhF_q_1__D_IN = MUX_wmi_dhF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1__D_IN = 38'h0AAAAAAAAA; + default: wmi_dhF_q_1__D_IN = 38'h2AAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_dhF_q_1__EN = + WILL_FIRE_RL_wmi_dhF_both || + WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_c_r == 2'b01 || + WILL_FIRE_RL_wmi_dhF_decCtr ; + + // register wmi_mFlagF_c_r + assign wmi_mFlagF_c_r__D_IN = + WILL_FIRE_RL_wmi_mFlagF_decCtr ? + MUX_wmi_mFlagF_c_r__write_1__VAL_1 : + MUX_wmi_mFlagF_c_r__write_1__VAL_2 ; + assign wmi_mFlagF_c_r__EN = + WILL_FIRE_RL_wmi_mFlagF_decCtr || + WILL_FIRE_RL_wmi_mFlagF_incCtr ; + + // register wmi_mFlagF_q_0 + always@(WILL_FIRE_RL_wmi_mFlagF_both or + MUX_wmi_mFlagF_q_0__write_1__VAL_1 or + MUX_wmi_mFlagF_q_0__write_1__SEL_2 or + value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_mFlagF_both: + wmi_mFlagF_q_0__D_IN = MUX_wmi_mFlagF_q_0__write_1__VAL_1; + MUX_wmi_mFlagF_q_0__write_1__SEL_2: wmi_mFlagF_q_0__D_IN = value__h6065; + WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0__D_IN = wmi_mFlagF_q_1; + default: wmi_mFlagF_q_0__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_mFlagF_q_0__EN = + WILL_FIRE_RL_wmi_mFlagF_both || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b00 || + WILL_FIRE_RL_wmi_mFlagF_decCtr ; + + // register wmi_mFlagF_q_1 + always@(WILL_FIRE_RL_wmi_mFlagF_both or + MUX_wmi_mFlagF_q_1__write_1__VAL_1 or + MUX_wmi_mFlagF_q_1__write_1__SEL_2 or + value__h6065 or WILL_FIRE_RL_wmi_mFlagF_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wmi_mFlagF_both: + wmi_mFlagF_q_1__D_IN = MUX_wmi_mFlagF_q_1__write_1__VAL_1; + MUX_wmi_mFlagF_q_1__write_1__SEL_2: wmi_mFlagF_q_1__D_IN = value__h6065; + WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1__D_IN = 32'b00000000000000000000000000000000; + default: wmi_mFlagF_q_1__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_mFlagF_q_1__EN = + WILL_FIRE_RL_wmi_mFlagF_both || + WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_c_r == 2'b01 || + WILL_FIRE_RL_wmi_mFlagF_decCtr ; + + // register wmi_operateD + assign wmi_operateD__D_IN = wci_cState == 3'b010 ; + assign wmi_operateD__EN = 1'b1 ; + + // register wmi_peerIsReady + assign wmi_peerIsReady__D_IN = wmiM_SReset_n ; + assign wmi_peerIsReady__EN = 1'b1 ; + + // register wmi_reqF_c_r + assign wmi_reqF_c_r__D_IN = + WILL_FIRE_RL_wmi_reqF_decCtr ? + MUX_wmi_reqF_c_r__write_1__VAL_1 : + MUX_wmi_reqF_c_r__write_1__VAL_2 ; + assign wmi_reqF_c_r__EN = + WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ; + + // register wmi_reqF_q_0 + always@(MUX_wmi_reqF_q_0__write_1__SEL_1 or + MUX_wmi_reqF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wmi_reqF_both or + MUX_wmi_reqF_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1) + begin + case (1'b1) // synopsys parallel_case + MUX_wmi_reqF_q_0__write_1__SEL_1: + wmi_reqF_q_0__D_IN = MUX_wmi_reqF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wmi_reqF_both: + wmi_reqF_q_0__D_IN = MUX_wmi_reqF_q_0__write_1__VAL_2; + WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_0__D_IN = wmi_reqF_q_1; + default: wmi_reqF_q_0__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_reqF_q_0__EN = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b00 || + WILL_FIRE_RL_wmi_reqF_both || + WILL_FIRE_RL_wmi_reqF_decCtr ; + + // register wmi_reqF_q_1 + always@(MUX_wmi_reqF_q_1__write_1__SEL_1 or + MUX_wmi_reqF_q_0__write_1__VAL_1 or + WILL_FIRE_RL_wmi_reqF_both or + MUX_wmi_reqF_q_1__write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr) + begin + case (1'b1) // synopsys parallel_case + MUX_wmi_reqF_q_1__write_1__SEL_1: + wmi_reqF_q_1__D_IN = MUX_wmi_reqF_q_0__write_1__VAL_1; + WILL_FIRE_RL_wmi_reqF_both: + wmi_reqF_q_1__D_IN = MUX_wmi_reqF_q_1__write_1__VAL_2; + WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_1__D_IN = 32'b00001010101010101010101010101010; + default: wmi_reqF_q_1__D_IN = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + assign wmi_reqF_q_1__EN = + WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_c_r == 2'b01 || + WILL_FIRE_RL_wmi_reqF_both || + WILL_FIRE_RL_wmi_reqF_decCtr ; + + // register wmi_sDataThreadBusy_d + assign wmi_sDataThreadBusy_d__D_IN = wmiM_SDataThreadBusy ; + assign wmi_sDataThreadBusy_d__EN = 1'b1 ; + + // register wmi_sFlagReg + assign wmi_sFlagReg__D_IN = wmiM_SFlag ; + assign wmi_sFlagReg__EN = 1'b1 ; + + // register wmi_sThreadBusy_d + assign wmi_sThreadBusy_d__D_IN = wmiM_SThreadBusy ; + assign wmi_sThreadBusy_d__EN = 1'b1 ; + + // register wsiM_burstKind + assign wsiM_burstKind__D_IN = + (wsiM_burstKind == 2'b00) ? + (wsiM_reqFifo_q_0[56] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiM_burstKind__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 && + (wsiM_burstKind == 2'b00 || + wsiM_burstKind == 2'b01 && wsiM_reqFifo_q_0[57] || + wsiM_burstKind == 2'b10 && wsiM_reqFifo_q_0[55:44] == 12'b000000000001) ; + + // register wsiM_errorSticky + assign wsiM_errorSticky__D_IN = 1'b0 ; + assign wsiM_errorSticky__EN = 1'b0 ; + + // register wsiM_iMesgCount + assign wsiM_iMesgCount__D_IN = wsiM_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiM_iMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 && + wsiM_burstKind == 2'b10 && + wsiM_reqFifo_q_0[55:44] == 12'b000000000001 ; + + // register wsiM_operateD + assign wsiM_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiM_operateD__EN = 1'b1 ; + + // register wsiM_pMesgCount + assign wsiM_pMesgCount__D_IN = wsiM_pMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiM_pMesgCount__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 && + wsiM_burstKind == 2'b01 && + wsiM_reqFifo_q_0[57] ; + + // register wsiM_peerIsReady + assign wsiM_peerIsReady__D_IN = wsiM1_SReset_n ; + assign wsiM_peerIsReady__EN = 1'b1 ; + + // register wsiM_reqFifo_c_r + assign wsiM_reqFifo_c_r__D_IN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr ? + MUX_wsiM_reqFifo_c_r__write_1__VAL_1 : + MUX_wsiM_reqFifo_c_r__write_1__VAL_2 ; + assign wsiM_reqFifo_c_r__EN = + WILL_FIRE_RL_wsiM_reqFifo_decCtr || + WILL_FIRE_RL_wsiM_reqFifo_incCtr ; + + // register wsiM_reqFifo_q_0 + assign wsiM_reqFifo_q_0__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b00 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_0__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_0__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_1; + MUX_wsiM_reqFifo_q_0__write_1__SEL_2: + wsiM_reqFifo_q_0__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_0__D_IN = wsiM_reqFifo_q_1; + default: wsiM_reqFifo_q_0__D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_reqFifo_q_1 + assign wsiM_reqFifo_q_1__EN = + WILL_FIRE_RL_wsiM_reqFifo_both || + WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'b01 || + WILL_FIRE_RL_wsiM_reqFifo_decCtr ; + always@(WILL_FIRE_RL_wsiM_reqFifo_both or + MUX_wsiM_reqFifo_q_1__write_1__VAL_1 or + MUX_wsiM_reqFifo_q_1__write_1__SEL_2 or + MUX_wsiM_reqFifo_q_0__write_1__VAL_2 or + WILL_FIRE_RL_wsiM_reqFifo_decCtr) + begin + case (1'b1) // synopsys parallel_case + WILL_FIRE_RL_wsiM_reqFifo_both: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_1__write_1__VAL_1; + MUX_wsiM_reqFifo_q_1__write_1__SEL_2: + wsiM_reqFifo_q_1__D_IN = MUX_wsiM_reqFifo_q_0__write_1__VAL_2; + WILL_FIRE_RL_wsiM_reqFifo_decCtr: + wsiM_reqFifo_q_1__D_IN = 61'h00000AAAAAAAAA00; + default: wsiM_reqFifo_q_1__D_IN = + 61'h0AAAAAAAAAAAAAAA /* unspecified value */ ; + endcase + end + + // register wsiM_sThreadBusy_d + assign wsiM_sThreadBusy_d__D_IN = wsiM1_SThreadBusy ; + assign wsiM_sThreadBusy_d__EN = 1'b1 ; + + // register wsiM_statusR + assign wsiM_statusR__D_IN = + { wsiM_isReset__VAL, + !wsiM_peerIsReady, + !wsiM_operateD, + wsiM_errorSticky, + wsiM_burstKind != 2'b00, + wsiM_sThreadBusy_d, + 1'b0, + wsiM_trafficSticky } ; + assign wsiM_statusR__EN = 1'b1 ; + + // register wsiM_tBusyCount + assign wsiM_tBusyCount__D_IN = wsiM_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiM_tBusyCount__EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ; + + // register wsiM_trafficSticky + assign wsiM_trafficSticky__D_IN = 1'b1 ; + assign wsiM_trafficSticky__EN = + WILL_FIRE_RL_wsiM_reqFifo_deq && + wsiM_reqFifo_q_0[60:58] == 3'b001 ; + + // register wsiS_burstKind + assign wsiS_burstKind__D_IN = + (wsiS_burstKind == 2'b00) ? + (wsiS_wsiReq__wget[56] ? 2'b01 : 2'b10) : + 2'b00 ; + assign wsiS_burstKind__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && + (wsiS_burstKind == 2'b00 || + wsiS_burstKind == 2'b01 && wsiS_wsiReq__wget[57] || + wsiS_burstKind == 2'b10 && wsiS_wsiReq__wget[55:44] == 12'b000000000001) ; + + // register wsiS_errorSticky + assign wsiS_errorSticky__D_IN = 1'b1 ; + assign wsiS_errorSticky__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo__FULL_N ; + + // register wsiS_iMesgCount + assign wsiS_iMesgCount__D_IN = wsiS_iMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_iMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b10 && + wsiS_wsiReq__wget[55:44] == 12'b000000000001 ; + + // register wsiS_operateD + assign wsiS_operateD__D_IN = wci_cState == 3'b010 ; + assign wsiS_operateD__EN = 1'b1 ; + + // register wsiS_pMesgCount + assign wsiS_pMesgCount__D_IN = wsiS_pMesgCount + 32'b00000000000000000000000000000001 ; + assign wsiS_pMesgCount__EN = + WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'b01 && + wsiS_wsiReq__wget[57] ; + + // register wsiS_peerIsReady + assign wsiS_peerIsReady__D_IN = wsiS1_MReset_n ; + assign wsiS_peerIsReady__EN = 1'b1 ; + + // register wsiS_reqFifo_countReg + assign wsiS_reqFifo_countReg__D_IN = + CAN_FIRE_RL_wsiS_reqFifo_enq ? + wsiS_reqFifo_countReg + 2'b01 : + wsiS_reqFifo_countReg - 2'b01 ; + assign wsiS_reqFifo_countReg__EN = + CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ; + + // register wsiS_statusR + assign wsiS_statusR__EN = 1'b1 ; + assign wsiS_statusR__D_IN = + { wsiS_isReset__VAL, + !wsiS_peerIsReady, + !wsiS_operateD, + wsiS_errorSticky, + wsiS_burstKind != 2'b00, + NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 || + wsiS_isReset__VAL || + !wsiS_operateD || + !wsiS_peerIsReady, + 1'b0, + wsiS_trafficSticky } ; + + // register wsiS_tBusyCount + assign wsiS_tBusyCount__D_IN = wsiS_tBusyCount + 32'b00000000000000000000000000000001 ; + assign wsiS_tBusyCount__EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ; + + // register wsiS_trafficSticky + assign wsiS_trafficSticky__D_IN = 1'b1 ; + assign wsiS_trafficSticky__EN = CAN_FIRE_RL_wsiS_reqFifo_enq ; + + // register wsiWordsRemain + assign wsiWordsRemain__D_IN = + MUX_mesgLength__write_1__SEL_2 ? + wsiS_reqFifo__D_OUT[55:44] : + MUX_wsiWordsRemain__write_1__VAL_2 ; + assign wsiWordsRemain__EN = + WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo__D_OUT[56] || + WILL_FIRE_RL_wmwt_messagePushPrecise ; + + // register zeroLengthMesg + assign zeroLengthMesg__D_IN = wsiS_reqFifo__D_OUT[11:8] == 4'b0000 ; + assign zeroLengthMesg__EN = MUX_mesgLength__write_1__SEL_2 ; + + // submodule wci_reqF + assign wci_reqF__D_IN = wci_wciReq__wget ; + assign wci_reqF__DEQ = wci_reqF_r_deq__whas ; + assign wci_reqF__ENQ = CAN_FIRE_RL_wci_reqF_enq ; + assign wci_reqF__CLR = 1'b0 ; + + // submodule wmi_respF + assign wmi_respF__D_IN = wmi_wmiResponse__wget ; + assign wmi_respF__DEQ = CAN_FIRE_RL_wmrd_mesgBodyResponse ; + assign wmi_respF__ENQ = CAN_FIRE_RL_wmi_respAdvance ; + assign wmi_respF__CLR = 1'b0 ; + + // submodule wsiS_reqFifo + assign wsiS_reqFifo__D_IN = wsiS_wsiReq__wget ; + assign wsiS_reqFifo__ENQ = CAN_FIRE_RL_wsiS_reqFifo_enq ; + assign wsiS_reqFifo__CLR = 1'b0 ; + assign wsiS_reqFifo__DEQ = wsiS_reqFifo_r_deq__whas ; + + // remaining internal signals + assign IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 = + mesgLength[14] ? mesgLength[13:0] : 14'b00000000000000 ; + assign NOT_wmi_reqF_c_r_46_EQ_2_47_48_AND_wmi_operate_ETC___d290 = + wmi_reqF_c_r != 2'b10 && wmi_operateD && wmi_peerIsReady && + (!x__h18884 || wmi_mFlagF_c_r != 2'b10) ; + assign NOT_wsiS_reqFifo_countReg_53_ULE_1_54___d355 = + wsiS_reqFifo_countReg > 2'b01 ; + assign addr__h16647 = { mesgLengthSoFar[11:0], 2'b00 } ; + // assign b__h13937 = -fabWordsCurReq[3:0] ; + assign b__h13937 = fabWordsCurReq[3:0] ; +// assign b__h19084 = { {10{fabRespCredit_value[3]}}, fabRespCredit_value } ; +assign b__h19084 = { {fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3],fabRespCredit_value[3]}, fabRespCredit_value } ; + assign bl__h17580 = + zeroLengthMesg ? + 12'b000000000001 : + IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753[13:2] ; + assign mesgMetaF_length__h16810 = { 10'b0000000000, mlp1B__h16631 } ; + assign mesgMetaF_length__h17723 = + { 10'b0000000000, + IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ; + assign mesgMetaF_opcode__h16809 = opcode[8] ? opcode[7:0] : 8'b00000000 ; + assign mlp1B__h16631 = { mlp1__h16630[11:0], 2'b00 } ; + assign mlp1__h16630 = mesgLengthSoFar + 14'b00000000000001 ; + assign rdat__h15540 = { 16'b0000000000000000, x__h15543 } ; + assign wsiBurstLength__h18454 = + smaCtrl[5] ? 16'b0000000000000010 : { 2'b00, thisMesg[15:2] } ; + assign wsiS_reqFifo_i_notEmpty__52_AND_wmi_operateD_5_ETC___d165 = + wsiS_reqFifo__EMPTY_N && wmi_operateD && wmi_peerIsReady && + (!x__h16715 || wmi_mFlagF_c_r != 2'b10) ; + assign x__h15543 = { wsiS_statusR, wsiM_statusR } ; + assign x__h16715 = wsiS_reqFifo__D_OUT[55:44] == 12'b000000000001 ; + assign x__h18884 = fabWordsRemain == fabWordsCurReq ; + assign x_burstLength__h18559 = + (thisMesg[15:0] == 16'b0000000000000000 || smaCtrl[5] && unrollCnt == 16'b0000000000000001) ? + 12'b000000000001 : + (smaCtrl[5] ? 12'b111111111111 : wsiBurstLength__h18454[11:0]) ; + assign x_byteEn__h18561 = (thisMesg[15:0] == 16'b0000000000000000) ? 4'b0000 : 4'b1111 ; + assign x_length__h17087 = + { 2'b00, + IF_mesgLength_22_BIT_14_23_THEN_mesgLength_22__ETC___d753 } ; + always@(wci_reqF__D_OUT or + smaCtrl or + mesgCount or + abortCount or + thisMesg or + lastMesg or + rdat__h15540 or wsiS_extStatusW__wget or wsiM_extStatusW__wget) + begin + case (wci_reqF__D_OUT[39:32]) + 8'h0: x_data__h15447 = smaCtrl; + 8'h04: x_data__h15447 = mesgCount; + 8'h08: x_data__h15447 = abortCount; + 8'h10: x_data__h15447 = thisMesg; + 8'h14: x_data__h15447 = lastMesg; + 8'h18: x_data__h15447 = rdat__h15540; + 8'h20: x_data__h15447 = wsiS_extStatusW__wget[95:64]; + 8'h24: x_data__h15447 = wsiS_extStatusW__wget[63:32]; + 8'h28: x_data__h15447 = wsiS_extStatusW__wget[31:0]; + 8'h2C: x_data__h15447 = wsiM_extStatusW__wget[95:64]; + 8'h30: x_data__h15447 = wsiM_extStatusW__wget[63:32]; + 8'h34: x_data__h15447 = wsiM_extStatusW__wget[31:0]; + default: x_data__h15447 = 32'b00000000000000000000000000000000; + endcase + end + always@(MUX_endOfMessage__write_1__SEL_1 or + MUX_wmi_mFlagF_x_wire__wset_1__VAL_1 or + MUX_wmi_mFlagF_x_wire__wset_1__SEL_2 or + WILL_FIRE_RL_wmwt_requestPrecise or + MUX_wmi_mFlagF_x_wire__wset_1__VAL_3) + begin + case (1'b1) // synopsys parallel_case + MUX_endOfMessage__write_1__SEL_1: + value__h6065 = MUX_wmi_mFlagF_x_wire__wset_1__VAL_1; + MUX_wmi_mFlagF_x_wire__wset_1__SEL_2: + value__h6065 = 32'hAAAAAAAA /* unspecified value */ ; + WILL_FIRE_RL_wmwt_requestPrecise: + value__h6065 = MUX_wmi_mFlagF_x_wire__wset_1__VAL_3; + default: value__h6065 = 32'hAAAAAAAA /* unspecified value */ ; + endcase + end + + // handling of inlined registers + + always@(posedge wciS0_Clk) + begin + if (!wciS0_MReset_n) + begin + abortCount <= 32'b00000000000000000000000000000000; + doAbort <= 1'b0; + endOfMessage <= 1'b0; + errCount <= 32'b00000000000000000000000000000000; + fabRespCredit_value <= 4'b0000; + fabWordsRemain <= 14'b00000000000000; + firstMsgReq <= 1'b0; + impreciseBurst <= 1'b0; + lastMesg <= 32'hFEFEFFFE; + mesgCount <= 32'b00000000000000000000000000000000; + mesgLength <= 15'b010101010101010; + mesgLengthSoFar <= 14'b00000000000000; + mesgPreRequest <= 1'b0; + mesgReqOK <= 1'b0; + mesgReqValid <= 1'b0; + opcode <= 9'b010101010; + preciseBurst <= 1'b0; + readyToPush <= 1'b0; + readyToRequest <= 1'b0; + smaCtrl <= smaCtrlInit; + thisMesg <= 32'hFEFEFFFE; + unrollCnt <= 16'b0000000000000000; + valExpect <= 32'b00000000000000000000000000000000; + wci_cEdge <= 3'b111; + wci_cState <= 3'b000; + wci_ctlAckReg <= 1'b0; + wci_ctlOpActive <= 1'b0; + wci_illegalEdge <= 1'b0; + wci_nState <= 3'b000; + wci_reqF_countReg <= 2'b00; + wci_respF_c_r <= 2'b00; + wci_respF_q_0 <= 34'h0AAAAAAAA; + wci_respF_q_1 <= 34'h0AAAAAAAA; + wci_sFlagReg <= 1'b0; + wci_sThreadBusy_d <= 1'b1; + wmi_busyWithMessage <= 1'b0; + wmi_dhF_c_r <= 2'b00; + wmi_dhF_q_0 <= 38'h0AAAAAAAAA; + wmi_dhF_q_1 <= 38'h0AAAAAAAAA; + wmi_mFlagF_c_r <= 2'b00; + wmi_mFlagF_q_0 <= 32'b00000000000000000000000000000000; + wmi_mFlagF_q_1 <= 32'b00000000000000000000000000000000; + wmi_operateD <= 1'b0; + wmi_peerIsReady <= 1'b0; + wmi_reqF_c_r <= 2'b00; + wmi_reqF_q_0 <= 32'b00001010101010101010101010101010; + wmi_reqF_q_1 <= 32'b00001010101010101010101010101010; + wmi_sDataThreadBusy_d <= 1'b0; + wmi_sFlagReg <= 32'b00000000000000000000000000000000; + wmi_sThreadBusy_d <= 1'b0; + wsiM_burstKind <= 2'b00; + wsiM_errorSticky <= 1'b0; + wsiM_iMesgCount <= 32'b00000000000000000000000000000000; + wsiM_operateD <= 1'b0; + wsiM_pMesgCount <= 32'b00000000000000000000000000000000; + wsiM_peerIsReady <= 1'b0; + wsiM_reqFifo_c_r <= 2'b00; + wsiM_reqFifo_q_0 <= 61'h00000AAAAAAAAA00; + wsiM_reqFifo_q_1 <= 61'h00000AAAAAAAAA00; + wsiM_sThreadBusy_d <= 1'b1; + wsiM_tBusyCount <= 32'b00000000000000000000000000000000; + wsiM_trafficSticky <= 1'b0; + wsiS_burstKind <= 2'b00; + wsiS_errorSticky <= 1'b0; + wsiS_iMesgCount <= 32'b00000000000000000000000000000000; + wsiS_operateD <= 1'b0; + wsiS_pMesgCount <= 32'b00000000000000000000000000000000; + wsiS_peerIsReady <= 1'b0; + wsiS_reqFifo_countReg <= 2'b00; + wsiS_tBusyCount <= 32'b00000000000000000000000000000000; + wsiS_trafficSticky <= 1'b0; + wsiWordsRemain <= 12'b000000000000; + zeroLengthMesg <= 1'b0; + end + else + begin + if (abortCount__EN) + abortCount <= abortCount__D_IN; + if (doAbort__EN) doAbort <= doAbort__D_IN; + if (endOfMessage__EN) + endOfMessage <= endOfMessage__D_IN; + if (errCount__EN) errCount <= errCount__D_IN; + if (fabRespCredit_value__EN) + fabRespCredit_value <= + fabRespCredit_value__D_IN; + if (fabWordsRemain__EN) + fabWordsRemain <= fabWordsRemain__D_IN; + if (firstMsgReq__EN) + firstMsgReq <= firstMsgReq__D_IN; + if (impreciseBurst__EN) + impreciseBurst <= impreciseBurst__D_IN; + if (lastMesg__EN) lastMesg <= lastMesg__D_IN; + if (mesgCount__EN) mesgCount <= mesgCount__D_IN; + if (mesgLength__EN) + mesgLength <= mesgLength__D_IN; + if (mesgLengthSoFar__EN) + mesgLengthSoFar <= mesgLengthSoFar__D_IN; + if (mesgPreRequest__EN) + mesgPreRequest <= mesgPreRequest__D_IN; + if (mesgReqOK__EN) mesgReqOK <= mesgReqOK__D_IN; + if (mesgReqValid__EN) + mesgReqValid <= mesgReqValid__D_IN; + if (opcode__EN) opcode <= opcode__D_IN; + if (preciseBurst__EN) + preciseBurst <= preciseBurst__D_IN; + if (readyToPush__EN) + readyToPush <= readyToPush__D_IN; + if (readyToRequest__EN) + readyToRequest <= readyToRequest__D_IN; + if (smaCtrl__EN) smaCtrl <= smaCtrl__D_IN; + if (thisMesg__EN) thisMesg <= thisMesg__D_IN; + if (unrollCnt__EN) unrollCnt <= unrollCnt__D_IN; + if (valExpect__EN) valExpect <= valExpect__D_IN; + if (wci_cEdge__EN) wci_cEdge <= wci_cEdge__D_IN; + if (wci_cState__EN) + wci_cState <= wci_cState__D_IN; + if (wci_ctlAckReg__EN) + wci_ctlAckReg <= wci_ctlAckReg__D_IN; + if (wci_ctlOpActive__EN) + wci_ctlOpActive <= wci_ctlOpActive__D_IN; + if (wci_illegalEdge__EN) + wci_illegalEdge <= wci_illegalEdge__D_IN; + if (wci_nState__EN) + wci_nState <= wci_nState__D_IN; + if (wci_reqF_countReg__EN) + wci_reqF_countReg <= wci_reqF_countReg__D_IN; + if (wci_respF_c_r__EN) + wci_respF_c_r <= wci_respF_c_r__D_IN; + if (wci_respF_q_0__EN) + wci_respF_q_0 <= wci_respF_q_0__D_IN; + if (wci_respF_q_1__EN) + wci_respF_q_1 <= wci_respF_q_1__D_IN; + if (wci_sFlagReg__EN) + wci_sFlagReg <= wci_sFlagReg__D_IN; + if (wci_sThreadBusy_d__EN) + wci_sThreadBusy_d <= wci_sThreadBusy_d__D_IN; + if (wmi_busyWithMessage__EN) + wmi_busyWithMessage <= + wmi_busyWithMessage__D_IN; + if (wmi_dhF_c_r__EN) + wmi_dhF_c_r <= wmi_dhF_c_r__D_IN; + if (wmi_dhF_q_0__EN) + wmi_dhF_q_0 <= wmi_dhF_q_0__D_IN; + if (wmi_dhF_q_1__EN) + wmi_dhF_q_1 <= wmi_dhF_q_1__D_IN; + if (wmi_mFlagF_c_r__EN) + wmi_mFlagF_c_r <= wmi_mFlagF_c_r__D_IN; + if (wmi_mFlagF_q_0__EN) + wmi_mFlagF_q_0 <= wmi_mFlagF_q_0__D_IN; + if (wmi_mFlagF_q_1__EN) + wmi_mFlagF_q_1 <= wmi_mFlagF_q_1__D_IN; + if (wmi_operateD__EN) + wmi_operateD <= wmi_operateD__D_IN; + if (wmi_peerIsReady__EN) + wmi_peerIsReady <= wmi_peerIsReady__D_IN; + if (wmi_reqF_c_r__EN) + wmi_reqF_c_r <= wmi_reqF_c_r__D_IN; + if (wmi_reqF_q_0__EN) + wmi_reqF_q_0 <= wmi_reqF_q_0__D_IN; + if (wmi_reqF_q_1__EN) + wmi_reqF_q_1 <= wmi_reqF_q_1__D_IN; + if (wmi_sDataThreadBusy_d__EN) + wmi_sDataThreadBusy_d <= + wmi_sDataThreadBusy_d__D_IN; + if (wmi_sFlagReg__EN) + wmi_sFlagReg <= wmi_sFlagReg__D_IN; + if (wmi_sThreadBusy_d__EN) + wmi_sThreadBusy_d <= wmi_sThreadBusy_d__D_IN; + if (wsiM_burstKind__EN) + wsiM_burstKind <= wsiM_burstKind__D_IN; + if (wsiM_errorSticky__EN) + wsiM_errorSticky <= wsiM_errorSticky__D_IN; + if (wsiM_iMesgCount__EN) + wsiM_iMesgCount <= wsiM_iMesgCount__D_IN; + if (wsiM_operateD__EN) + wsiM_operateD <= wsiM_operateD__D_IN; + if (wsiM_pMesgCount__EN) + wsiM_pMesgCount <= wsiM_pMesgCount__D_IN; + if (wsiM_peerIsReady__EN) + wsiM_peerIsReady <= wsiM_peerIsReady__D_IN; + if (wsiM_reqFifo_c_r__EN) + wsiM_reqFifo_c_r <= wsiM_reqFifo_c_r__D_IN; + if (wsiM_reqFifo_q_0__EN) + wsiM_reqFifo_q_0 <= wsiM_reqFifo_q_0__D_IN; + if (wsiM_reqFifo_q_1__EN) + wsiM_reqFifo_q_1 <= wsiM_reqFifo_q_1__D_IN; + if (wsiM_sThreadBusy_d__EN) + wsiM_sThreadBusy_d <= wsiM_sThreadBusy_d__D_IN; + if (wsiM_tBusyCount__EN) + wsiM_tBusyCount <= wsiM_tBusyCount__D_IN; + if (wsiM_trafficSticky__EN) + wsiM_trafficSticky <= wsiM_trafficSticky__D_IN; + if (wsiS_burstKind__EN) + wsiS_burstKind <= wsiS_burstKind__D_IN; + if (wsiS_errorSticky__EN) + wsiS_errorSticky <= wsiS_errorSticky__D_IN; + if (wsiS_iMesgCount__EN) + wsiS_iMesgCount <= wsiS_iMesgCount__D_IN; + if (wsiS_operateD__EN) + wsiS_operateD <= wsiS_operateD__D_IN; + if (wsiS_pMesgCount__EN) + wsiS_pMesgCount <= wsiS_pMesgCount__D_IN; + if (wsiS_peerIsReady__EN) + wsiS_peerIsReady <= wsiS_peerIsReady__D_IN; + if (wsiS_reqFifo_countReg__EN) + wsiS_reqFifo_countReg <= + wsiS_reqFifo_countReg__D_IN; + if (wsiS_tBusyCount__EN) + wsiS_tBusyCount <= wsiS_tBusyCount__D_IN; + if (wsiS_trafficSticky__EN) + wsiS_trafficSticky <= wsiS_trafficSticky__D_IN; + if (wsiWordsRemain__EN) + wsiWordsRemain <= wsiWordsRemain__D_IN; + if (zeroLengthMesg__EN) + zeroLengthMesg <= zeroLengthMesg__D_IN; + end + if (fabWordsCurReq__EN) + fabWordsCurReq <= fabWordsCurReq__D_IN; + if (mesgReqAddr__EN) mesgReqAddr <= mesgReqAddr__D_IN; + if (wsiM_statusR__EN) + wsiM_statusR <= wsiM_statusR__D_IN; + if (wsiS_statusR__EN) + wsiS_statusR <= wsiS_statusR__D_IN; + end + + +endmodule // mkSMAdapter4B + + + + + +module SizedFIFO_a (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [59:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [59:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_a fifo_1 +(.clk(CLK), + .rst(CLR), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + +module SizedFIFO_b (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [31:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [31:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_b fifo_1 +(.clk(CLK), + .rst(CLR), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter awb=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + + + + +module SizedFIFO_c (CLK, D_IN,ENQ,DEQ,CLR,D_OUT,FULL_N,EMPTY_N); + + +input CLK; +input [60:0] D_IN; +input ENQ; +input DEQ; +input CLR; +output [60:0] D_OUT; +output FULL_N; +output EMPTY_N; + + + + +wire fulln; +wire emptyn; + +wire always_one; +wire always_zero; + +assign always_one = 1'b1; +assign always_zero = 1'b0; + +generic_fifo_sc_c fifo_1 +(.clk(CLK), + .rst(always_one), + .clr (CLR), + .din (D_IN), + .we (ENQ), + .dout (D_OUT), + .re (DEQ), + .full_r (FULL_N), + .empty_r(EMPTY_N), + .full_n_r (fulln), + .empty_n_r (emptyn) + ); + + + + + + + + +endmodule + + + + + + + + +///////////////////////////////////////////////////////////////////// +//// //// +//// Universal FIFO Single Clock //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// D/L from: http://www.opencores.org/cores/generic_fifos/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __ +// +// __Date: 2002-09-25 05:42:06 __ +// __Revision: 1.1.1.1 __ +// __Author: rudi __ +// __Locker: __ +// __State: Exp __ +// +// Change History: +// __Log: not supported by cvs2svn __ +// +// +// +// +// +// +// +// +// +// + + +/* + +Description +=========== + +I/Os +---- +rst low active, either sync. or async. master reset (see below how to select) +clr synchronous clear (just like reset but always synchronous), high active +re read enable, synchronous, high active +we read enable, synchronous, high active +din Data Input +dout Data Output + +full Indicates the FIFO is full (combinatorial output) +full_r same as above, but registered output (see note below) +empty Indicates the FIFO is empty +empty_r same as above, but registered output (see note below) + +full_n Indicates if the FIFO has space for N entries (combinatorial output) +full_n_r same as above, but registered output (see note below) +empty_n Indicates the FIFO has at least N entries (combinatorial output) +empty_n_r same as above, but registered output (see note below) + +level indicates the FIFO level: + 2'b00 0-25% full + 2'b01 25-50% full + 2'b10 50-75% full + 2'b11 %75-100% full + +combinatorial vs. registered status outputs +------------------------------------------- +Both the combinatorial and registered status outputs have exactly the same +synchronous timing. Meaning they are being asserted immediately at the clock +edge after the last read or write. The combinatorial outputs however, pass +through several levels of logic before they are output. The registered status +outputs are direct outputs of a flip-flop. The reason both are provided, is +that the registered outputs require quite a bit of additional logic inside +the FIFO. If you can meet timing of your device with the combinatorial +outputs, use them ! The FIFO will be smaller. If the status signals are +in the critical pass, use the registered outputs, they have a much smaller +output delay (actually only Tcq). + +Parameters +---------- +The FIFO takes 3 parameters: +dw Data bus width +aw Address bus width (Determines the FIFO size by evaluating 2^aw) +n N is a second status threshold constant for full_n and empty_n + If you have no need for the second status threshold, do not + connect the outputs and the logic should be removed by your + synthesis tool. + +Synthesis Results +----------------- +In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs +at about 116 MHz (IO insertion disabled). The registered status outputs +are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be +available. + + +Misc +---- +This design assumes you will do appropriate status checking externally. + +IMPORTANT ! writing while the FIFO is full or reading while the FIFO is +empty will place the FIFO in an undefined state. + +*/ + + +// Selecting Sync. or Async Reset +// ------------------------------ +// Uncomment one of the two lines below. The first line for +// synchronous reset, the second for asynchronous reset + +//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset +//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset + +/* +parameter dw=8; +parameter aw=8; +parameter n=32; +parameter max_size = 1<= (`n-1) ) & !re) empty_n_r <= 1'b0; + else + if(re & (cnt <= `n ) & !we) empty_n_r <= 1'b1; + +always @(posedge clk ) + if(!rst) full_n_r <= 1'b0; + else + if(clr) full_n_r <= 1'b0; + else + if(we & (cnt >= (`max_size-`n) ) & !re) full_n_r <= 1'b1; + else + if(re & (cnt <= (`max_size-`n+1)) & !we) full_n_r <= 1'b0; + +endmodule + + +module ResetToBool (RST, VAL); + +input RST; +output VAL; +reg VAL; + +always @ (RST or VAL) +begin + +if (RST == 1) +VAL=1'b0; + +end +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/or1200.v b/openfpga_flow/benchmarks/vtr_benchmark/or1200.v new file mode 100755 index 000000000..e6f75b38e --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/or1200.v @@ -0,0 +1,5236 @@ +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. + +`define OR1200_DCFGR_RES1 28'h0000000 + + + + +`define OR1200_M2R_BYTE0 4'b0000 +`define OR1200_M2R_BYTE1 4'b0001 +`define OR1200_M2R_BYTE2 4'b0010 +`define OR1200_M2R_BYTE3 4'b0011 +`define OR1200_M2R_EXTB0 4'b0100 +`define OR1200_M2R_EXTB1 4'b0101 +`define OR1200_M2R_EXTB2 4'b0110 +`define OR1200_M2R_EXTB3 4'b0111 +`define OR1200_M2R_ZERO 4'b0000 + + +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS 9 // Num cache sets +`define OR1200_ICCFGR_CBS 9 // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 + +//`define OR1200_ICCFGR_NCW_BITS 2:0 +//`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +//`define OR1200_ICCFGR_RES1_BITS 31:15 + + +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS 9 // Num cache sets +`define OR1200_DCCFGR_CBS 9 // 16 byte cache block +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 + + + +//`define OR1200_DCCFGR_NCW_BITS 2:0 +//`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +//`define OR1200_DCCFGR_RES1_BITS 31:15 + + +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'b101 // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 + +// CPUCFGR fields +//`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +//`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +/* +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +*/ +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +//`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values + +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'b110 // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 + + +// IMMUCFGR fields +/* +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +*/ +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 + +//`define OR1200_IMMUCFGR_RES1_BITS 31:12 + + + +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +/* +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 +*/ +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +/* +`define OR1200_UPR_RES1_BITS 23:11 +`define OR1200_UPR_CUP_BITS 31:24 +*/ + +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + + +`define OR1200_DU_DSR_WIDTH 14 + + +`define OR1200_EXCEPT_UNUSED 3'hf +`define OR1200_EXCEPT_TRAP 3'he +`define OR1200_EXCEPT_BREAK 3'hd +`define OR1200_EXCEPT_SYSCALL 3'hc +`define OR1200_EXCEPT_RANGE 3'hb +`define OR1200_EXCEPT_ITLBMISS 3'ha +`define OR1200_EXCEPT_DTLBMISS 3'h9 +`define OR1200_EXCEPT_INT 3'h8 +`define OR1200_EXCEPT_ILLEGAL 3'h7 +`define OR1200_EXCEPT_ALIGN 3'h6 +`define OR1200_EXCEPT_TICK 3'h5 +`define OR1200_EXCEPT_IPF 3'h4 +`define OR1200_EXCEPT_DPF 3'h3 +`define OR1200_EXCEPT_BUSERR 3'h2 +`define OR1200_EXCEPT_RESET 3'h1 +`define OR1200_EXCEPT_NONE 3'h0 + +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 +`define OR1200_ALUOP_WIDTH 4 +`define OR1200_ALUOP_NOP 4'b000 + +`define OR1200_ALUOP_ADD 4'b0000 +`define OR1200_ALUOP_ADDC 4'b0001 +`define OR1200_ALUOP_SUB 4'b0010 +`define OR1200_ALUOP_AND 4'b0011 +`define OR1200_ALUOP_OR 4'b0100 +`define OR1200_ALUOP_XOR 4'b0101 +`define OR1200_ALUOP_MUL 4'b0110 +`define OR1200_ALUOP_CUST5 4'b0111 +`define OR1200_ALUOP_SHROT 4'b1000 +`define OR1200_ALUOP_DIV 4'b1001 +`define OR1200_ALUOP_DIVU 4'b1010 + +`define OR1200_ALUOP_IMM 4'b1011 +`define OR1200_ALUOP_MOVHI 4'b1100 +`define OR1200_ALUOP_COMP 4'b1101 +`define OR1200_ALUOP_MTSR 4'b1110 +`define OR1200_ALUOP_MFSR 4'b1111 +`define OR1200_ALUOP_CMOV 4'b1110 +`define OR1200_ALUOP_FF1 4'b1111 + +`define OR1200_MACOP_WIDTH 2 +`define OR1200_MACOP_NOP 2'b00 +`define OR1200_MACOP_MAC 2'b01 +`define OR1200_MACOP_MSB 2'b10 + + +`define OR1200_SHROTOP_WIDTH 2 +`define OR1200_SHROTOP_NOP 2'b00 +`define OR1200_SHROTOP_SLL 2'b00 +`define OR1200_SHROTOP_SRL 2'b01 +`define OR1200_SHROTOP_SRA 2'b10 +`define OR1200_SHROTOP_ROR 2'b11 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 2 +`define OR1200_ONE_CYCLE 2'b00 +`define OR1200_TWO_CYCLES 2'b01 + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'b00 +`define OR1200_SEL_IMM 2'b01 +`define OR1200_SEL_EX_FORW 2'b10 +`define OR1200_SEL_WB_FORW 2'b11 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'b000 +`define OR1200_BRANCHOP_J 3'b001 +`define OR1200_BRANCHOP_JR 3'b010 +`define OR1200_BRANCHOP_BAL 3'b011 +`define OR1200_BRANCHOP_BF 3'b100 +`define OR1200_BRANCHOP_BNF 3'b101 +`define OR1200_BRANCHOP_RFE 3'b110 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 2-1: write-back mux selects +`define OR1200_RFWBOP_WIDTH 3 +`define OR1200_RFWBOP_NOP 3'b000 +`define OR1200_RFWBOP_ALU 3'b001 +`define OR1200_RFWBOP_LSU 3'b011 +`define OR1200_RFWBOP_SPRS 3'b101 +`define OR1200_RFWBOP_LR 3'b111 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 3'b011 +`define OR1200_COMPOP_WIDTH 4 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + + +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_BE 12 +`define OR1200_DU_DSR_TE 13 +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +//`define OR1200_SHROTOP_POS 7:6 + +// ALU instructions multicycle field in machine word +//`define OR1200_ALUMCYC_POS 9:8 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +`define OR1200_OR32_CUST5 6'b111100 + + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +`define OR1200_SPR_GROUP_SYS 5'b00000 +`define OR1200_SPR_GROUP_DMMU 5'b00001 +`define OR1200_SPR_GROUP_IMMU 5'b00010 +`define OR1200_SPR_GROUP_DC 5'b00011 +`define OR1200_SPR_GROUP_IC 5'b00100 +`define OR1200_SPR_GROUP_MAC 5'b00101 +`define OR1200_SPR_GROUP_DU 5'b00110 +`define OR1200_SPR_GROUP_PM 5'b01000 +`define OR1200_SPR_GROUP_PIC 5'b01001 +`define OR1200_SPR_GROUP_TT 5'b01010 + + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'b0000000 +`define OR1200_SPR_RF 6'b100000 // 1024 >> 5 +`define OR1200_SPR_NPC 11'b00000010000 +`define OR1200_SPR_SR 11'b00000010001 +`define OR1200_SPR_PPC 11'b00000010010 +`define OR1200_SPR_EPCR 11'b00000100000 +`define OR1200_SPR_EEAR 11'b00000110000 +`define OR1200_SPR_ESR 11'b00001000000 + +// +// SR bits +// +`define OR1200_SR_WIDTH 16 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Unused +`define OR1200_SR_OV 11 // Unused +`define OR1200_SR_OVE 12 // Unused +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 + + +// +// Bits that define offset inside the group + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// +// Bit positions inside PMR (don't change) + +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 + + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'b01000 + + + +// Define it if you want PIC implemented + + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'b00 +`define OR1200_PIC_OFS_PICSR 2'b10 + +// Position of offset bits inside SPR address + + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'b0 +`define OR1200_TT_OFS_TTCR 1'b1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// TTMR bits +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 + + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// +// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which +// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer +// default setup, but if you need to remain backward compatible, define your shift bits, which were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 +`define OR1200_ITLB_INDXW 6 + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_ICLS 4 + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_DCLS 4 + +// Define to perform store refill (potential performance penalty) +// `define OR1200_DC_STORE_REFILL + +// +// DC configurations +`define OR1200_DCSIZE 12 // 4096 + +`define OR1200_DCTAG_W 21 + + + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h00800000 +`define OR1200_QMEM_IMASK 32'hfff00000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h00800000 +`define OR1200_QMEM_DMASK 32'hfff00000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + + +// UPR values +`define OR1200_UPR_UP 1'b1 +`define OR1200_UPR_DCP 1'b1 + +`define OR1200_UPR_ICP 1'b1 + +`define OR1200_UPR_DMP 1'b1 + +`define OR1200_UPR_IMP 1'b1 + +`define OR1200_UPR_MP 1'b1 // MAC always present + +`define OR1200_UPR_DUP 1'b1 + + +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present + +`define OR1200_UPR_PMP 1'b1 + +`define OR1200_UPR_PICP 1'b1 + +`define OR1200_UPR_TTP 1'b1 + +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + + +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 + +// DMMUCFGR values +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 + + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +// IMMUCFGR values +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 + + +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 + +// DCCFGR values +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 + + +// ICCFGR fields +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 + +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 + + +// DCFGR fields +`define OR1200_DCFGR_WPCI_BITS 3 + +// DCFGR values + +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. + +`define OR1200_DCFGR_RES1 28'h0000000 + + +module or1200_flat( // or1200_cpu + // Clk & Rst + clk, rst, + + // Insn interface + ic_en, + icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o, + icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i, + immu_en, + + // Debug unit + ex_insn, ex_freeze, id_pc, branch_op, + spr_dat_npc, rf_dataw, + du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt, + du_except, du_dat_cpu, + + // Data interface + dc_en, + dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o, + dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i, + dmmu_en, + + // Interrupt & tick exceptions + sig_int, sig_tick, + + // SPR interface + supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm, + spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we +); + +//parameter dw = `OR1200_OPERAND_WIDTH; +//parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O ports +// + +// +// Clk & Rst +// +input clk; +input rst; + +// +// Insn (IC) interface +// +output ic_en; +output [31:0] icpu_adr_o; +output icpu_cycstb_o; +output [3:0] icpu_sel_o; +output [3:0] icpu_tag_o; +input [31:0] icpu_dat_i; +input icpu_ack_i; +input icpu_rty_i; +input icpu_err_i; +input [31:0] icpu_adr_i; +input [3:0] icpu_tag_i; + +// +// Insn (IMMU) interface +// +output immu_en; + +// +// Debug interface +// +output [31:0] ex_insn; +output ex_freeze; +output [31:0] id_pc; +output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; + +input du_stall; +input [`OR1200_OPERAND_WIDTH-1:0] du_addr; +input [`OR1200_OPERAND_WIDTH-1:0] du_dat_du; +input du_read; +input du_write; +input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +input du_hwbkpt; +output [12:0] du_except; +output [`OR1200_OPERAND_WIDTH-1:0] du_dat_cpu; +output [`OR1200_OPERAND_WIDTH-1:0] rf_dataw; + +// +// Data (DC) interface +// +output [31:0] dcpu_adr_o; +output dcpu_cycstb_o; +output dcpu_we_o; +output [3:0] dcpu_sel_o; +output [3:0] dcpu_tag_o; +output [31:0] dcpu_dat_o; +input [31:0] dcpu_dat_i; +input dcpu_ack_i; +input dcpu_rty_i; +input dcpu_err_i; +input [3:0] dcpu_tag_i; +output dc_en; + +// +// Data (DMMU) interface +// +output dmmu_en; + +// +// SPR interface +// +output supv; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_pic; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_tt; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_pm; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_dmmu; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_immu; +input [`OR1200_OPERAND_WIDTH-1:0] spr_dat_du; +output [`OR1200_OPERAND_WIDTH-1:0] spr_addr; +output [`OR1200_OPERAND_WIDTH-1:0] spr_dat_cpu; +output [`OR1200_OPERAND_WIDTH-1:0] spr_dat_npc; +output [31:0] spr_cs; +output spr_we; + +// +// Interrupt exceptions +// +input sig_int; +input sig_tick; + +// +// Internal wires +// +wire [31:0] if_insn; +wire [31:0] if_pc; +wire [31:2] lr_sav; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb; +wire rf_rda; +wire rf_rdb; +wire [`OR1200_OPERAND_WIDTH-1:0] simm; +wire [`OR1200_OPERAND_WIDTH-1:2] branch_addrofs; +wire [`OR1200_ALUOP_WIDTH-1:0] alu_op; +wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +wire [`OR1200_COMPOP_WIDTH-1:0] comp_op; +wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +wire genpc_freeze; +wire if_freeze; +wire id_freeze; +wire ex_freeze; +wire wb_freeze; +wire [`OR1200_SEL_WIDTH-1:0] sel_a; +wire [`OR1200_SEL_WIDTH-1:0] sel_b; +wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_dataw; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_dataa; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_datab; +wire [`OR1200_OPERAND_WIDTH-1:0] muxed_b; +wire [`OR1200_OPERAND_WIDTH-1:0] wb_forw; +wire wbforw_valid; +wire [`OR1200_OPERAND_WIDTH-1:0] operand_a; +wire [`OR1200_OPERAND_WIDTH-1:0] operand_b; +wire [`OR1200_OPERAND_WIDTH-1:0] alu_dataout; +wire [`OR1200_OPERAND_WIDTH-1:0] lsu_dataout; +wire [`OR1200_OPERAND_WIDTH-1:0] sprs_dataout; +wire [31:0] lsu_addrofs; +wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +wire [`OR1200_EXCEPT_WIDTH-1:0] except_type; +wire [4:0] cust5_op; +wire [5:0] cust5_limm; +wire flushpipe; +wire extend_flush; +wire branch_taken; +wire flag; +wire flagforw; +wire flag_we; +wire k_carry; +wire cyforw; +wire cy_we; +wire lsu_stall; +wire epcr_we; +wire eear_we; +wire esr_we; +wire pc_we; +wire [31:0] epcr; +wire [31:0] eear; +wire [`OR1200_SR_WIDTH-1:0] esr; +wire sr_we; +wire [`OR1200_SR_WIDTH-1:0] to_sr; +wire [`OR1200_SR_WIDTH-1:0] sr; +wire except_start; +wire except_started; +wire [31:0] wb_insn; +wire [15:0] spr_addrimm; +wire sig_syscall; +wire sig_trap; +wire [31:0] spr_dat_cfgr; +wire [31:0] spr_dat_rf; +wire [31:0] spr_dat_npc; +wire [31:0] spr_dat_ppc; +wire [31:0] spr_dat_mac; +wire force_dslot_fetch; +wire no_more_dslot; +wire ex_void; +wire if_stall; +wire id_macrc_op; +wire ex_macrc_op; +wire [`OR1200_MACOP_WIDTH-1:0] mac_op; +wire [31:0] mult_mac_result; +wire mac_stall; +wire [12:0] except_stop; +wire genpc_refetch; +wire rfe; +wire lsu_unstall; +wire except_align; +wire except_dtlbmiss; +wire except_dmmufault; +wire except_illegal; +wire except_itlbmiss; +wire except_immufault; +wire except_ibuserr; +wire except_dbuserr; +wire abort_ex; + +// +// Send exceptions to Debug Unit +// +assign du_except = except_stop; + +// +// Data cache enable +// +assign dc_en = sr[`OR1200_SR_DCE]; + +// +// Instruction cache enable +// +assign ic_en = sr[`OR1200_SR_ICE]; + +// +// DMMU enable +// +assign dmmu_en = sr[`OR1200_SR_DME]; + +// +// IMMU enable +// +assign immu_en = sr[`OR1200_SR_IME]; + +// +// SUPV bit +// +assign supv = sr[`OR1200_SR_SM]; + +// +// Instantiation of instruction fetch block +// +or1200_genpc or1200_genpc( + .clk(clk), + .rst(rst), + .icpu_adr_o(icpu_adr_o), + .icpu_cycstb_o(icpu_cycstb_o), + .icpu_sel_o(icpu_sel_o), + .icpu_tag_o(icpu_tag_o), + .icpu_rty_i(icpu_rty_i), + .icpu_adr_i(icpu_adr_i), + + .branch_op(branch_op), + .except_type(except_type), + .except_start(except_start), + .except_prefix(sr[`OR1200_SR_EPH]), + .branch_addrofs(branch_addrofs), + .lr_restor(operand_b), + .flag(flag), + .taken(branch_taken), + .binsn_addr(lr_sav), + .epcr(epcr), + .spr_dat_i(spr_dat_cpu), + .spr_pc_we(pc_we), + .genpc_refetch(genpc_refetch), + .genpc_freeze(genpc_freeze), + .genpc_stop_prefetch(1'b0), + .no_more_dslot(no_more_dslot) +); + +// +// Instantiation of instruction fetch block +// +or1200_if or1200_if( + .clk(clk), + .rst(rst), + .icpu_dat_i(icpu_dat_i), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i), + .icpu_adr_i(icpu_adr_i), + .icpu_tag_i(icpu_tag_i), + + .if_freeze(if_freeze), + .if_insn(if_insn), + .if_pc(if_pc), + .flushpipe(flushpipe), + .if_stall(if_stall), + .no_more_dslot(no_more_dslot), + .genpc_refetch(genpc_refetch), + .rfe(rfe), + .except_itlbmiss(except_itlbmiss), + .except_immufault(except_immufault), + .except_ibuserr(except_ibuserr) +); + +// +// Instantiation of instruction decode/control logic +// +or1200_ctrl or1200_ctrl( + .clk(clk), + .rst(rst), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .flushpipe(flushpipe), + .if_insn(if_insn), + .ex_insn(ex_insn), + .branch_op(branch_op), + .branch_taken(branch_taken), + .rf_addra(rf_addra), + .rf_addrb(rf_addrb), + .rf_rda(rf_rda), + .rf_rdb(rf_rdb), + .alu_op(alu_op), + .mac_op(mac_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .rf_addrw(rf_addrw), + .rfwb_op(rfwb_op), + .wb_insn(wb_insn), + .simm(simm), + .branch_addrofs(branch_addrofs), + .lsu_addrofs(lsu_addrofs), + .sel_a(sel_a), + .sel_b(sel_b), + .lsu_op(lsu_op), + .cust5_op(cust5_op), + .cust5_limm(cust5_limm), + .multicycle(multicycle), + .spr_addrimm(spr_addrimm), + .wbforw_valid(wbforw_valid), + .sig_syscall(sig_syscall), + .sig_trap(sig_trap), + .force_dslot_fetch(force_dslot_fetch), + .no_more_dslot(no_more_dslot), + .ex_void(ex_void), + .id_macrc_op(id_macrc_op), + .ex_macrc_op(ex_macrc_op), + .rfe(rfe), + .du_hwbkpt(du_hwbkpt), + .except_illegal(except_illegal) +); + +// +// Instantiation of register file +// +or1200_rf or1200_rf( + .clk(clk), + .rst(rst), + .supv(sr[`OR1200_SR_SM]), + .wb_freeze(wb_freeze), + .addrw(rf_addrw), + .dataw(rf_dataw), + .id_freeze(id_freeze), + .we(rfwb_op[0]), + .flushpipe(flushpipe), + .addra(rf_addra), + .rda(rf_rda), + .dataa(rf_dataa), + .addrb(rf_addrb), + .rdb(rf_rdb), + .datab(rf_datab), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_rf) +); + +// +// Instantiation of operand muxes +// +or1200_operandmuxes or1200_operandmuxes( + .clk(clk), + .rst(rst), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .rf_dataa(rf_dataa), + .rf_datab(rf_datab), + .ex_forw(rf_dataw), + .wb_forw(wb_forw), + .simm(simm), + .sel_a(sel_a), + .sel_b(sel_b), + .operand_a(operand_a), + .operand_b(operand_b), + .muxed_b(muxed_b) +); + +// +// Instantiation of CPU's ALU +// +or1200_alu or1200_alu( + .a(operand_a), + .b(operand_b), + .mult_mac_result(mult_mac_result), + .macrc_op(ex_macrc_op), + .alu_op(alu_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .cust5_op(cust5_op), + .cust5_limm(cust5_limm), + .result(alu_dataout), + .flagforw(flagforw), + .flag_we(flag_we), + .cyforw(cyforw), + .cy_we(cy_we), + .flag(flag), + .k_carry(k_carry) +); + +// +// Instantiation of CPU's ALU +// +or1200_mult_mac or1200_mult_mac( + .clk(clk), + .rst(rst), + .ex_freeze(ex_freeze), + .id_macrc_op(id_macrc_op), + .macrc_op(ex_macrc_op), + .a(operand_a), + .b(operand_b), + .mac_op(mac_op), + .alu_op(alu_op), + .result(mult_mac_result), + .mac_stall_r(mac_stall), + .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]), + .spr_write(spr_we), + .spr_addr(spr_addr), + .spr_dat_i(spr_dat_cpu), + .spr_dat_o(spr_dat_mac) +); + +// +// Instantiation of CPU's SPRS block +// +or1200_sprs or1200_sprs( + .clk(clk), + .rst(rst), + .addrbase(operand_a), + .addrofs(spr_addrimm), + .dat_i(operand_b), + .alu_op(alu_op), + .flagforw(flagforw), + .flag_we(flag_we), + .flag(flag), + .cyforw(cyforw), + .cy_we(cy_we), + .carry(k_carry), + .to_wbmux(sprs_dataout), + + .du_addr(du_addr), + .du_dat_du(du_dat_du), + .du_read(du_read), + .du_write(du_write), + .du_dat_cpu(du_dat_cpu), + + .spr_addr(spr_addr), + .spr_dat_pic(spr_dat_pic), + .spr_dat_tt(spr_dat_tt), + .spr_dat_pm(spr_dat_pm), + .spr_dat_cfgr(spr_dat_cfgr), + .spr_dat_rf(spr_dat_rf), + .spr_dat_npc(spr_dat_npc), + .spr_dat_ppc(spr_dat_ppc), + .spr_dat_mac(spr_dat_mac), + .spr_dat_dmmu(spr_dat_dmmu), + .spr_dat_immu(spr_dat_immu), + .spr_dat_du(spr_dat_du), + .spr_dat_o(spr_dat_cpu), + .spr_cs(spr_cs), + .spr_we(spr_we), + + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .pc_we(pc_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + .except_started(except_started), + + .sr_we(sr_we), + .to_sr(to_sr), + .sr(sr), + .branch_op(branch_op) +); + +// +// Instantiation of load/store unit +// +or1200_lsu or1200_lsu( + .addrbase(operand_a), + .addrofs(lsu_addrofs), + .lsu_op(lsu_op), + .lsu_datain(operand_b), + .lsu_dataout(lsu_dataout), + .lsu_stall(lsu_stall), + .lsu_unstall(lsu_unstall), + .du_stall(du_stall), + .except_align(except_align), + .except_dtlbmiss(except_dtlbmiss), + .except_dmmufault(except_dmmufault), + .except_dbuserr(except_dbuserr), + + .dcpu_adr_o(dcpu_adr_o), + .dcpu_cycstb_o(dcpu_cycstb_o), + .dcpu_we_o(dcpu_we_o), + .dcpu_sel_o(dcpu_sel_o), + .dcpu_tag_o(dcpu_tag_o), + .dcpu_dat_o(dcpu_dat_o), + .dcpu_dat_i(dcpu_dat_i), + .dcpu_ack_i(dcpu_ack_i), + .dcpu_rty_i(dcpu_rty_i), + .dcpu_err_i(dcpu_err_i), + .dcpu_tag_i(dcpu_tag_i) +); + +// +// Instantiation of write-back muxes +// +or1200_wbmux or1200_wbmux( + .clk(clk), + .rst(rst), + .wb_freeze(wb_freeze), + .rfwb_op(rfwb_op), + .muxin_a(alu_dataout), + .muxin_b(lsu_dataout), + .muxin_c(sprs_dataout), + .muxin_d({lr_sav, 2'b0}), + .muxout(rf_dataw), + .muxreg(wb_forw), + .muxreg_valid(wbforw_valid) +); + +// +// Instantiation of freeze logic +// +or1200_freeze or1200_freeze( + .clk(clk), + .rst(rst), + .multicycle(multicycle), + .flushpipe(flushpipe), + .extend_flush(extend_flush), + .lsu_stall(lsu_stall), + .if_stall(if_stall), + .lsu_unstall(lsu_unstall), + .force_dslot_fetch(force_dslot_fetch), + .abort_ex(abort_ex), + .du_stall(du_stall), + .mac_stall(mac_stall), + .genpc_freeze(genpc_freeze), + .if_freeze(if_freeze), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i) +); + +// +// Instantiation of exception block +// +or1200_except or1200_except( + .clk(clk), + .rst(rst), + .sig_ibuserr(except_ibuserr), + .sig_dbuserr(except_dbuserr), + .sig_illegal(except_illegal), + .sig_align(except_align), + .sig_range(1'b0), + .sig_dtlbmiss(except_dtlbmiss), + .sig_dmmufault(except_dmmufault), + .sig_int(sig_int), + .sig_syscall(sig_syscall), + .sig_trap(sig_trap), + .sig_itlbmiss(except_itlbmiss), + .sig_immufault(except_immufault), + .sig_tick(sig_tick), + .branch_taken(branch_taken), + .icpu_ack_i(icpu_ack_i), + .icpu_err_i(icpu_err_i), + .dcpu_ack_i(dcpu_ack_i), + .dcpu_err_i(dcpu_err_i), + .genpc_freeze(genpc_freeze), + .id_freeze(id_freeze), + .ex_freeze(ex_freeze), + .wb_freeze(wb_freeze), + .if_stall(if_stall), + .if_pc(if_pc), + .id_pc(id_pc), + .lr_sav(lr_sav), + .flushpipe(flushpipe), + .extend_flush(extend_flush), + .except_type(except_type), + .except_start(except_start), + .except_started(except_started), + .except_stop(except_stop), + .ex_void(ex_void), + .spr_dat_ppc(spr_dat_ppc), + .spr_dat_npc(spr_dat_npc), + + .datain(operand_b), + .du_dsr(du_dsr), + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .pc_we(pc_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + + .lsu_addr(dcpu_adr_o), + .sr_we(sr_we), + .to_sr(to_sr), + .sr(sr), + .abort_ex(abort_ex) +); + +// +// Instantiation of configuration registers +// +or1200_cfgr or1200_cfgr( + .spr_addr(spr_addr), + .spr_dat_o(spr_dat_cfgr) +); + +endmodule + + + +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'b000 +`define OR1200_BRANCHOP_J 3'b001 +`define OR1200_BRANCHOP_JR 3'b010 +`define OR1200_BRANCHOP_BAL 3'b011 +`define OR1200_BRANCHOP_BF 3'b100 +`define OR1200_BRANCHOP_BNF 3'b101 +`define OR1200_BRANCHOP_RFE 3'b110 +`define OR1200_EXCEPT_WIDTH 4 +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +module or1200_genpc( + // Clock and reset + clk, rst, + + // External i/f to IC + icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o, + icpu_rty_i, icpu_adr_i, + + // Internal i/f + branch_op, except_type,except_start, except_prefix, + branch_addrofs, lr_restor, flag, taken, + binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch, + genpc_freeze, genpc_stop_prefetch, no_more_dslot +); + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External i/f to IC +// +output [31:0] icpu_adr_o; +output icpu_cycstb_o; +output [3:0] icpu_sel_o; +output [3:0] icpu_tag_o; +input icpu_rty_i; +input [31:0] icpu_adr_i; + +// +// Internal i/f +// +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +input [`OR1200_EXCEPT_WIDTH-1:0] except_type; +input except_start; +input except_prefix; +input [31:2] branch_addrofs; +input [31:0] lr_restor; +input flag; +output taken; + +input [31:2] binsn_addr; +input [31:0] epcr; +input [31:0] spr_dat_i; +input spr_pc_we; +input genpc_refetch; +input genpc_freeze; +input genpc_stop_prefetch; +input no_more_dslot; + +// +// Internal wires and regs +// +reg [31:2] pcreg; +reg [31:0] pc; +reg taken; /* Set to in case of jump or taken branch */ +reg genpc_refetch_r; + +// +// Address of insn to be fecthed +// +assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc; +// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc; + +// +// Control access to IC subsystem +// +// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot; +assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store +//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r); +//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch); +assign icpu_sel_o = 4'b1111; +assign icpu_tag_o = `OR1200_ITAG_NI; + +// +// genpc_freeze_r +// +always @(posedge clk ) + if (rst) + genpc_refetch_r <= 1'b0; + else if (genpc_refetch) + genpc_refetch_r <= 1'b1; + else + genpc_refetch_r <= 1'b0; + +// +// Async calculation of new PC value. This value is used for addressing the IC. +// +always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type + or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin + case ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case + {2'b00, `OR1200_BRANCHOP_NOP}: begin + pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; + taken = 1'b0; + end + {2'b00, `OR1200_BRANCHOP_J}: begin + + pc = {branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_JR}: begin + + pc = lr_restor; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_BAL}: begin + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_BF}: + if (flag) begin + + pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + else begin + + pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; + taken = 1'b0; + end + {2'b00, `OR1200_BRANCHOP_BNF}: + if (flag) begin + pc = {pcreg + 30'b000000000000000000000000000001, 2'b0}; + + taken = 1'b0; + end + else begin pc = {binsn_addr + branch_addrofs, 2'b0}; + taken = 1'b1; + end + {2'b00, `OR1200_BRANCHOP_RFE}: begin + + pc = epcr; + taken = 1'b1; + end + {2'b01, 3'b000}: begin + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b001}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b010}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b011}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b100}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b101}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b110}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + {2'b01, 3'b111}: begin + + pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V}; + taken = 1'b1; + end + default: begin + + pc = spr_dat_i; + taken = 1'b0; + end + endcase +end + +// +// PC register +// +always @(posedge clk ) + if (rst) +// pcreg <= 30'd63; + pcreg <= ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),8'b11111111, `OR1200_EXCEPT_V} - 1) >> 2; + else if (spr_pc_we) + pcreg <= spr_dat_i[31:2]; + else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) +// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch) + pcreg <= pc[31:2]; + + wire unused; + assign unused = |except_prefix & | binsn_addr | genpc_stop_prefetch ; +endmodule + +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +//`define OR1200_OR32_CUST5 6'b111100 + + +module or1200_if( + // Clock and reset + clk, rst, + + // External i/f to IC + icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i, + + // Internal i/f + if_freeze, if_insn, if_pc, flushpipe, + if_stall, no_more_dslot, genpc_refetch, rfe, + except_itlbmiss, except_immufault, except_ibuserr +); + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// External i/f to IC +// +input [31:0] icpu_dat_i; +input icpu_ack_i; +input icpu_err_i; +input [31:0] icpu_adr_i; +input [3:0] icpu_tag_i; + +// +// Internal i/f +// +input if_freeze; +output [31:0] if_insn; +output [31:0] if_pc; +input flushpipe; +output if_stall; +input no_more_dslot; +output genpc_refetch; +input rfe; +output except_itlbmiss; +output except_immufault; +output except_ibuserr; + +// +// Internal wires and regs +// +reg [31:0] insn_saved; +reg [31:0] addr_saved; +reg saved; + +// +// IF stage insn +// +assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h0410000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h0610000}; +assign if_pc = saved ? addr_saved : icpu_adr_i; +// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot; +assign if_stall = !icpu_err_i & !icpu_ack_i & !saved; +assign genpc_refetch = saved & icpu_ack_i; +assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot; +assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot; +assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot; + +// +// Flag for saved insn/address +// +always @(posedge clk ) + if (rst) + saved <= 1'b0; + else if (flushpipe) + saved <= 1'b0; + else if (icpu_ack_i & if_freeze & !saved) + saved <= 1'b1; + else if (!if_freeze) + saved <= 1'b0; + +// +// Store fetched instruction +// +always @(posedge clk ) + if (rst) + insn_saved <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (flushpipe) + insn_saved <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (icpu_ack_i & if_freeze & !saved) + insn_saved <= icpu_dat_i; + else if (!if_freeze) + insn_saved <= {`OR1200_OR32_NOP, 26'h0410000}; + +// +// Store fetched instruction's address +// +always @(posedge clk ) + if (rst) + addr_saved <= 32'h00000000; + else if (flushpipe) + addr_saved <= 32'h00000000; + else if (icpu_ack_i & if_freeze & !saved) + addr_saved <= icpu_adr_i; + else if (!if_freeze) + addr_saved <= icpu_adr_i; + +endmodule + +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Instruction decode //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Majority of instruction decoding is performed here. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.12 2005/01/07 09:31:07 andreje +// sign/zero extension for l.sfxxi instructions corrected +// +// Revision 1.11 2004/06/08 18:17:36 lampret +// Non-functional changes. Coding style fixes. +// +// Revision 1.10 2004/05/09 19:49:04 lampret +// Added some l.cust5 custom instructions as example +// +// Revision 1.9 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.8.4.1 2004/02/11 01:40:11 lampret +// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. +// +// Revision 1.8 2003/04/24 00:16:07 lampret +// No functional changes. Added defines to disable implementation of multiplier/MAC +// +// Revision 1.7 2002/09/07 05:42:02 lampret +// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. +// +// Revision 1.6 2002/03/29 15:16:54 lampret +// Some of the warnings fixed. +// +// Revision 1.5 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.4 2002/01/28 01:15:59 lampret +// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. +// +// Revision 1.3 2002/01/18 14:21:43 lampret +// Fixed 'the NPC single-step fix'. +// +// Revision 1.2 2002/01/14 06:18:22 lampret +// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.14 2001/11/30 18:59:17 simons +// force_dslot_fetch does not work - allways zero. +// +// Revision 1.13 2001/11/20 18:46:15 simons +// Break point bug fixed +// +// Revision 1.12 2001/11/18 08:36:28 lampret +// For GDB changed single stepping and disabled trap exception. +// +// Revision 1.11 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.10 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.9 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.8 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.7 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// + + +module or1200_ctrl( + // Clock and reset + clk, rst, + + // Internal i/f + id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op, branch_taken, + rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op, + wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op, + cust5_op, cust5_limm, + multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap, + force_dslot_fetch, no_more_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe,du_hwbkpt, except_illegal +); + +// +// I/O +// +input clk; +input rst; +input id_freeze; +input ex_freeze; +input wb_freeze; +input flushpipe; +input [31:0] if_insn; +output [31:0] ex_insn; +output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +input branch_taken; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb; +output rf_rda; +output rf_rdb; +output [`OR1200_ALUOP_WIDTH-1:0] alu_op; +output [`OR1200_MACOP_WIDTH-1:0] mac_op; +output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +output [31:0] wb_insn; +output [31:0] simm; +output [31:2] branch_addrofs; +output [31:0] lsu_addrofs; +output [`OR1200_SEL_WIDTH-1:0] sel_a; +output [`OR1200_SEL_WIDTH-1:0] sel_b; +output [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +output [`OR1200_COMPOP_WIDTH-1:0] comp_op; +output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +output [4:0] cust5_op; +output [5:0] cust5_limm; +output [15:0] spr_addrimm; +input wbforw_valid; +input du_hwbkpt; +output sig_syscall; +output sig_trap; +output force_dslot_fetch; +output no_more_dslot; +output ex_void; +output id_macrc_op; +output ex_macrc_op; +output rfe; +output except_illegal; + +// +// Internal wires and regs +// +reg [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op; +reg [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; +reg [`OR1200_ALUOP_WIDTH-1:0] alu_op; + +reg [`OR1200_MACOP_WIDTH-1:0] mac_op; +reg ex_macrc_op; + +reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; +reg [31:0] id_insn; +reg [31:0] ex_insn; +reg [31:0] wb_insn; +reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw; +reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +reg [31:0] lsu_addrofs; +reg [`OR1200_SEL_WIDTH-1:0] sel_a; +reg [`OR1200_SEL_WIDTH-1:0] sel_b; +reg sel_imm; +reg [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +reg [`OR1200_COMPOP_WIDTH-1:0] comp_op; +reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +reg imm_signextend; +reg [15:0] spr_addrimm; +reg sig_syscall; +reg sig_trap; +reg except_illegal; +wire id_void; + +// +// Register file read addresses +// +assign rf_addra = if_insn[20:16]; +assign rf_addrb = if_insn[15:11]; +assign rf_rda = if_insn[31]; +assign rf_rdb = if_insn[30]; + +// +// Force fetch of delay slot instruction when jump/branch is preceeded by load/store +// instructions +// +// SIMON +// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op)); +assign force_dslot_fetch = 1'b0; +assign no_more_dslot = |branch_op & !id_void & branch_taken | (branch_op == `OR1200_BRANCHOP_RFE); +assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16]; +assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]; + +// +// Sign/Zero extension of immediates +// +assign simm = (imm_signextend == 1'b1) ? {{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]},{id_insn[15]}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]}; + +// +// Sign extension of branch offset +// +assign branch_addrofs = {{ex_insn[25]},{ex_insn[25]},{ex_insn[25]},{ex_insn[25]},{ex_insn[25]}, ex_insn[25:0]}; + +// +// l.macrc in ID stage +// + +assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16]; + +// +// cust5_op, cust5_limm (L immediate) +// +assign cust5_op = ex_insn[4:0]; +assign cust5_limm = ex_insn[10:5]; + +// +// +// +assign rfe = (pre_branch_op == `OR1200_BRANCHOP_RFE) | (branch_op == `OR1200_BRANCHOP_RFE); + +// +// Generation of sel_a +// +always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) + if ((id_insn[20:16] == rf_addrw) && rfwb_op[0]) + sel_a = `OR1200_SEL_EX_FORW; + else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid) + sel_a = `OR1200_SEL_WB_FORW; + else + sel_a = `OR1200_SEL_RF; + +// +// Generation of sel_b +// +always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw) + if (sel_imm) + sel_b = `OR1200_SEL_IMM; + else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0]) + sel_b = `OR1200_SEL_EX_FORW; + else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid) + sel_b = `OR1200_SEL_WB_FORW; + else + sel_b = `OR1200_SEL_RF; + +// +// l.macrc in EX stage +// + +always @(posedge clk ) begin + if (rst) + ex_macrc_op <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + ex_macrc_op <= 1'b0; + else if (!ex_freeze) + ex_macrc_op <= id_macrc_op; +end +// +// Decode of spr_addrimm +// +always @(posedge clk ) begin + if (rst) + spr_addrimm <= 16'h0000; + else if (!ex_freeze & id_freeze | flushpipe) + spr_addrimm <= 16'h0000; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + // l.mfspr + `OR1200_OR32_MFSPR: + spr_addrimm <= id_insn[15:0]; + // l.mtspr + default: + spr_addrimm <= {id_insn[25:21], id_insn[10:0]}; + endcase + end +end + +// +// Decode of multicycle +// +always @(id_insn) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.lwz + `OR1200_OR32_LWZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lbz + `OR1200_OR32_LBZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lbs + `OR1200_OR32_LBS: + multicycle = `OR1200_TWO_CYCLES; + + // l.lhz + `OR1200_OR32_LHZ: + multicycle = `OR1200_TWO_CYCLES; + + // l.lhs + `OR1200_OR32_LHS: + multicycle = `OR1200_TWO_CYCLES; + + // l.sw + `OR1200_OR32_SW: + multicycle = `OR1200_TWO_CYCLES; + + // l.sb + `OR1200_OR32_SB: + multicycle = `OR1200_TWO_CYCLES; + + // l.sh + `OR1200_OR32_SH: + multicycle = `OR1200_TWO_CYCLES; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + multicycle = id_insn[9:8]; + + // Single cycle instructions + default: begin + multicycle = `OR1200_ONE_CYCLE; + end + + endcase + +end + +// +// Decode of imm_signextend +// +always @(id_insn) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.addi + `OR1200_OR32_ADDI: + imm_signextend = 1'b1; + + // l.addic + `OR1200_OR32_ADDIC: + imm_signextend = 1'b1; + + // l.xori + `OR1200_OR32_XORI: + imm_signextend = 1'b1; + + // l.muli + + `OR1200_OR32_MULI: + imm_signextend = 1'b1; + + + // l.maci + + `OR1200_OR32_MACI: + imm_signextend = 1'b1; + + + // SFXX insns with immediate + `OR1200_OR32_SFXXI: + imm_signextend = 1'b1; + + // Instructions with no or zero extended immediate + default: begin + imm_signextend = 1'b0; + end + +endcase + +end + +// +// LSU addr offset +// +always @(lsu_op or ex_insn) begin + lsu_addrofs[10:0] = ex_insn[10:0]; + case(lsu_op) // synopsys parallel_case + `OR1200_LSUOP_SB : + lsu_addrofs[31:11] = {{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}}, ex_insn[25:21]}; + `OR1200_LSUOP_SH : + lsu_addrofs[31:11] = {{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}}, ex_insn[25:21]}; + + `OR1200_LSUOP_SW : + lsu_addrofs[31:11] = {{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}},{{ex_insn[25]}}, ex_insn[25:21]}; + + default : + lsu_addrofs[31:11] = {{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}},{{ex_insn[15]}}, ex_insn[15:11]}; + endcase +end + +// +// Register file write address +// +always @(posedge clk) begin + if (rst) + rf_addrw <= 5'b00000; + else if (!ex_freeze & id_freeze) + rf_addrw <= 5'b00000; + else if (!ex_freeze) + case (pre_branch_op) // synopsys parallel_case +`OR1200_BRANCHOP_BAL: + rf_addrw <= 5'b01001; // link register r9 + `OR1200_BRANCHOP_JR: + rf_addrw <= 5'b01001; + default: + rf_addrw <= id_insn[25:21]; + endcase +end + +// +// rf_addrw in wb stage (used in forwarding logic) +// +always @(posedge clk ) begin + if (rst) + wb_rfaddrw <= 5'b00000; + else if (!wb_freeze) + wb_rfaddrw <= rf_addrw; +end + +// +// Instruction latch in id_insn +// +always @(posedge clk ) begin + if (rst) + id_insn <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (flushpipe) + id_insn <= {`OR1200_OR32_NOP, 26'h0410000}; // id_insn[16] must be 1 + else if (!id_freeze) begin + id_insn <= if_insn; + + end +end + +// +// Instruction latch in ex_insn +// +always @(posedge clk ) begin + if (rst) + ex_insn <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (!ex_freeze & id_freeze | flushpipe) + ex_insn <= {`OR1200_OR32_NOP, 26'h0410000}; // ex_insn[16] must be 1 + else if (!ex_freeze) begin + ex_insn <= id_insn; + end +end + +// +// Instruction latch in wb_insn +// +always @(posedge clk ) begin + if (rst) + wb_insn <= {`OR1200_OR32_NOP, 26'h0410000}; + else if (flushpipe) + wb_insn <= {`OR1200_OR32_NOP, 26'h0410000}; // wb_insn[16] must be 1 + else if (!wb_freeze) begin + wb_insn <= ex_insn; + end +end + +// +// Decode of sel_imm +// +always @(posedge clk ) begin + if (rst) + sel_imm <= 1'b0; + else if (!id_freeze) begin + case (if_insn[31:26]) // synopsys parallel_case + + // j.jalr + `OR1200_OR32_JALR: + sel_imm <= 1'b0; + + // l.jr + `OR1200_OR32_JR: + sel_imm <= 1'b0; + + // l.rfe + `OR1200_OR32_RFE: + sel_imm <= 1'b0; + + // l.mfspr + `OR1200_OR32_MFSPR: + sel_imm <= 1'b0; + + // l.mtspr + `OR1200_OR32_MTSPR: + sel_imm <= 1'b0; + + // l.sys, l.brk and all three sync insns + `OR1200_OR32_XSYNC: + sel_imm <= 1'b0; + + // l.mac/l.msb + + `OR1200_OR32_MACMSB: + sel_imm <= 1'b0; + + // l.sw + `OR1200_OR32_SW: + sel_imm <= 1'b0; + + // l.sb + `OR1200_OR32_SB: + sel_imm <= 1'b0; + + // l.sh + `OR1200_OR32_SH: + sel_imm <= 1'b0; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + sel_imm <= 1'b0; + + // SFXX instructions + `OR1200_OR32_SFXX: + sel_imm <= 1'b0; + + + // l.cust5 instructions + `OR1200_OR32_CUST5: + sel_imm <= 1'b0; + + + // l.nop + `OR1200_OR32_NOP: + sel_imm <= 1'b0; + + // All instructions with immediates + default: begin + sel_imm <= 1'b1; + end + + endcase + + end +end + +// +// Decode of except_illegal +// +always @(posedge clk ) begin + if (rst) + except_illegal <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + except_illegal <= 1'b0; + else if (!ex_freeze) begin + except_illegal <= 1'b1; + end +end + +// +// Decode of alu_op +// +always @(posedge clk ) begin + if (rst) + alu_op <= `OR1200_ALUOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + alu_op <= `OR1200_ALUOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.j + `OR1200_OR32_J: + alu_op <= `OR1200_ALUOP_IMM; + + // j.jal + `OR1200_OR32_JAL: + alu_op <= `OR1200_ALUOP_IMM; + + // l.bnf + `OR1200_OR32_BNF: + alu_op <= `OR1200_ALUOP_NOP; + + // l.bf + `OR1200_OR32_BF: + alu_op <= `OR1200_ALUOP_NOP; + + // l.movhi + `OR1200_OR32_MOVHI: + alu_op <= `OR1200_ALUOP_MOVHI; + + // l.mfspr + `OR1200_OR32_MFSPR: + alu_op <= `OR1200_ALUOP_MFSR; + + // l.mtspr + `OR1200_OR32_MTSPR: + alu_op <= `OR1200_ALUOP_MTSR; + + // l.addi + `OR1200_OR32_ADDI: + alu_op <= `OR1200_ALUOP_ADD; + + // l.addic + `OR1200_OR32_ADDIC: + alu_op <= `OR1200_ALUOP_ADDC; + + // l.andi + `OR1200_OR32_ANDI: + alu_op <= `OR1200_ALUOP_AND; + + // l.ori + `OR1200_OR32_ORI: + alu_op <= `OR1200_ALUOP_OR; + + // l.xori + `OR1200_OR32_XORI: + alu_op <= `OR1200_ALUOP_XOR; + + // l.muli + + `OR1200_OR32_MULI: + alu_op <= `OR1200_ALUOP_MUL; + + + // Shift and rotate insns with immediate + `OR1200_OR32_SH_ROTI: + alu_op <= `OR1200_ALUOP_SHROT; + + // SFXX insns with immediate + `OR1200_OR32_SFXXI: + alu_op <= `OR1200_ALUOP_COMP; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + alu_op <= id_insn[3:0]; + + // SFXX instructions + `OR1200_OR32_SFXX: + alu_op <= `OR1200_ALUOP_COMP; + + + // l.cust5 instructions + `OR1200_OR32_CUST5: + alu_op <= `OR1200_ALUOP_CUST5; + // Default + default: begin + alu_op <= `OR1200_ALUOP_NOP; + end + + endcase + + end +end + +// +// Decode of mac_op + +always @(posedge clk ) begin + if (rst) + mac_op <= `OR1200_MACOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + mac_op <= `OR1200_MACOP_NOP; + else if (!ex_freeze) + case (id_insn[31:26]) // synopsys parallel_case + + // l.maci + `OR1200_OR32_MACI: + mac_op <= `OR1200_MACOP_MAC; + + // l.nop + `OR1200_OR32_MACMSB: + mac_op <= id_insn[1:0]; + + // Illegal and OR1200 unsupported instructions + default: begin + mac_op <= `OR1200_MACOP_NOP; + end + + endcase + else + mac_op <= `OR1200_MACOP_NOP; +end + +// +// Decode of shrot_op +// +always @(posedge clk ) begin + if (rst) + shrot_op <= `OR1200_SHROTOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + shrot_op <= `OR1200_SHROTOP_NOP; + else if (!ex_freeze) begin + shrot_op <= id_insn[7:6]; + end +end + +// +// Decode of rfwb_op +// +always @(posedge clk ) begin + if (rst) + rfwb_op <= `OR1200_RFWBOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + rfwb_op <= `OR1200_RFWBOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // j.jal + `OR1200_OR32_JAL: + rfwb_op <= `OR1200_RFWBOP_LR; + + // j.jalr + `OR1200_OR32_JALR: + rfwb_op <= `OR1200_RFWBOP_LR; + + // l.movhi + `OR1200_OR32_MOVHI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.mfspr + `OR1200_OR32_MFSPR: + rfwb_op <= `OR1200_RFWBOP_SPRS; + + // l.lwz + `OR1200_OR32_LWZ: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lbz + `OR1200_OR32_LBZ: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lbs + `OR1200_OR32_LBS: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lhz + `OR1200_OR32_LHZ: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.lhs + `OR1200_OR32_LHS: + rfwb_op <= `OR1200_RFWBOP_LSU; + + // l.addi + `OR1200_OR32_ADDI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.addic + `OR1200_OR32_ADDIC: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.andi + `OR1200_OR32_ANDI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.ori + `OR1200_OR32_ORI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.xori + `OR1200_OR32_XORI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // l.muli + + `OR1200_OR32_MULI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + + // Shift and rotate insns with immediate + `OR1200_OR32_SH_ROTI: + rfwb_op <= `OR1200_RFWBOP_ALU; + + // ALU instructions except the one with immediate + `OR1200_OR32_ALU: + rfwb_op <= `OR1200_RFWBOP_ALU; + + + // l.cust5 instructions + `OR1200_OR32_CUST5: + rfwb_op <= `OR1200_RFWBOP_ALU; + + + // Instructions w/o register-file write-back + default: begin + rfwb_op <= `OR1200_RFWBOP_NOP; + end + + endcase + end +end + +// +// Decode of pre_branch_op +// +always @(posedge clk ) begin + if (rst) + pre_branch_op <= `OR1200_BRANCHOP_NOP; + else if (flushpipe) + pre_branch_op <= `OR1200_BRANCHOP_NOP; + else if (!id_freeze) begin + case (if_insn[31:26]) // synopsys parallel_case + + // l.j + `OR1200_OR32_J: + pre_branch_op <= `OR1200_BRANCHOP_BAL; + + // j.jal + `OR1200_OR32_JAL: + pre_branch_op <= `OR1200_BRANCHOP_BAL; + + // j.jalr + `OR1200_OR32_JALR: + pre_branch_op <= `OR1200_BRANCHOP_JR; + + // l.jr + `OR1200_OR32_JR: + pre_branch_op <= `OR1200_BRANCHOP_JR; + + // l.bnf + `OR1200_OR32_BNF: + pre_branch_op <= `OR1200_BRANCHOP_BNF; + + // l.bf + `OR1200_OR32_BF: + pre_branch_op <= `OR1200_BRANCHOP_BF; + + // l.rfe + `OR1200_OR32_RFE: + pre_branch_op <= `OR1200_BRANCHOP_RFE; + + // Non branch instructions + default: begin + pre_branch_op <= `OR1200_BRANCHOP_NOP; + end + endcase + end +end + +// +// Generation of branch_op +// +always @(posedge clk ) + if (rst) + branch_op <= `OR1200_BRANCHOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + branch_op <= `OR1200_BRANCHOP_NOP; + else if (!ex_freeze) + branch_op <= pre_branch_op; + +// +// Decode of lsu_op +// +always @(posedge clk ) begin + if (rst) + lsu_op <= `OR1200_LSUOP_NOP; + else if (!ex_freeze & id_freeze | flushpipe) + lsu_op <= `OR1200_LSUOP_NOP; + else if (!ex_freeze) begin + case (id_insn[31:26]) // synopsys parallel_case + + // l.lwz + `OR1200_OR32_LWZ: + lsu_op <= `OR1200_LSUOP_LWZ; + + // l.lbz + `OR1200_OR32_LBZ: + lsu_op <= `OR1200_LSUOP_LBZ; + + // l.lbs + `OR1200_OR32_LBS: + lsu_op <= `OR1200_LSUOP_LBS; + + // l.lhz + `OR1200_OR32_LHZ: + lsu_op <= `OR1200_LSUOP_LHZ; + + // l.lhs + `OR1200_OR32_LHS: + lsu_op <= `OR1200_LSUOP_LHS; + + // l.sw + `OR1200_OR32_SW: + lsu_op <= `OR1200_LSUOP_SW; + + // l.sb + `OR1200_OR32_SB: + lsu_op <= `OR1200_LSUOP_SB; + + // l.sh + `OR1200_OR32_SH: + lsu_op <= `OR1200_LSUOP_SH; + + // Non load/store instructions + default: begin + lsu_op <= `OR1200_LSUOP_NOP; + end + endcase + end +end + +// +// Decode of comp_op +// +always @(posedge clk ) begin + if (rst) begin + comp_op <= 4'b0000; + end else if (!ex_freeze & id_freeze | flushpipe) + comp_op <= 4'b0000; + else if (!ex_freeze) + comp_op <= id_insn[24:21]; +end + +// +// Decode of l.sys +// +always @(posedge clk ) begin + if (rst) + sig_syscall <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + sig_syscall <= 1'b0; + else if (!ex_freeze) begin + + sig_syscall <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000}); + end +end + +// +// Decode of l.trap +// +always @(posedge clk ) begin + if (rst) + sig_trap <= 1'b0; + else if (!ex_freeze & id_freeze | flushpipe) + sig_trap <= 1'b0; + else if (!ex_freeze) begin + + sig_trap <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010}) + | du_hwbkpt; + end +end + +endmodule + + +module or1200_rf( + // Clock and reset + clk, rst, + + // Write i/f + supv, wb_freeze, addrw, dataw,id_freeze, we, flushpipe, + + // Read i/f + addra, rda, dataa, addrb,rdb, datab, + // Debug + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o +); + +//parameter aw = `OR1200_OPERAND_WIDTH; +//parameter dw= `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Write i/f +// +input supv; +input wb_freeze; +input [`OR1200_REGFILE_ADDR_WIDTH-1:0] addrw; +input [`OR1200_OPERAND_WIDTH-1:0] dataw; +input we; +input flushpipe; + +// +// Read i/f +// +input id_freeze; +input [`OR1200_REGFILE_ADDR_WIDTH-1:0] addra; +input [`OR1200_REGFILE_ADDR_WIDTH-1:0] addrb; +output [`OR1200_OPERAND_WIDTH-1:0] dataa; +output [`OR1200_OPERAND_WIDTH-1:0] datab; +input rda; +input rdb; + +// +// SPR access for debugging purposes +// +input spr_cs; +input spr_write; +input [31:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// Internal wires and regs +// +wire [`OR1200_OPERAND_WIDTH-1:0] from_rfa; +wire [`OR1200_OPERAND_WIDTH-1:0] from_rfb; +reg [`OR1200_OPERAND_WIDTH:0] dataa_saved; +reg [`OR1200_OPERAND_WIDTH:0] datab_saved; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra; +wire [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; +wire [`OR1200_OPERAND_WIDTH-1:0] rf_dataw; +wire rf_we; +wire spr_valid; +wire rf_ena; +wire rf_enb; +reg rf_we_allow; + +// +// SPR access is valid when spr_cs is asserted and +// SPR address matches GPR addresses +// +assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF); + +// +// SPR data output is always from RF A +// +assign spr_dat_o = from_rfa; + +// +// Operand A comes from RF or from saved A register +// +assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa; + +// +// Operand B comes from RF or from saved B register +// +assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb; + +// +// RF A read address is either from SPRS or normal from CPU control +// +assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra; + +// +// RF write address is either from SPRS or normal from CPU control +// +assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw; + +// +// RF write data is either from SPRS or normal from CPU datapath +// +assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw; + +// +// RF write enable is either from SPRS or normal from CPU control +// +always @(posedge clk) + if (rst) + rf_we_allow <= 1'b1; + else if (~wb_freeze) + rf_we_allow <= ~flushpipe; + +assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw)); + +// +// CS RF A asserted when instruction reads operand A and ID stage +// is not stalled +// +assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils +// assign rf_ena = 1'b1; // does not work with single-stepping +//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils + +// +// CS RF B asserted when instruction reads operand B and ID stage +// is not stalled +// +assign rf_enb = rdb & ~id_freeze | spr_valid; +// assign rf_enb = 1'b1; +//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils + +// +// Stores operand from RF_A into temp reg when pipeline is frozen +// +always @(posedge clk ) + if (rst) begin + dataa_saved <=33'b000000000000000000000000000000000; + end + else if (id_freeze & !dataa_saved[32]) begin + dataa_saved <= {1'b1, from_rfa}; + end + else if (!id_freeze) + dataa_saved <=33'b000000000000000000000000000000000; + +// +// Stores operand from RF_B into temp reg when pipeline is frozen +// +always @(posedge clk) + if (rst) begin + datab_saved <= 33'b000000000000000000000000000000000; + end + else if (id_freeze & !datab_saved[32]) begin + datab_saved <= {1'b1, from_rfb}; + end + else if (!id_freeze) + datab_saved <= 33'b000000000000000000000000000000000; + + + + +// Black-box memory instead of the or1200 memory implementation + +wire const_one; +wire const_zero; +assign const_one = 1'b1; +assign const_zero = 1'b0; +wire [31:0] const_zero_data; +assign const_zero_data = 32'b00000000000000000000000000000000; +wire [31:0] dont_care_out; +wire [31:0] dont_care_out2; + +dual_port_ram rf_a( + + .clk (clk), + .we1(const_zero), + .we2(rf_we), + .data1(const_zero_data), + .data2(rf_dataw), + .out1(from_rfa), + .out2 (dont_care_out), + .addr1(rf_addra), + .addr2(rf_addrw)); +// +// Instantiation of register file two-port RAM A +// +/* +or1200_tpram_32x32 rf_a( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_ena), + .we_a(1'b0), + .oe_a(1'b1), + .addr_a(rf_addra), + .di_a(32'h00000000), + .do_a(from_rfa), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .oe_b(1'b0), + .addr_b(rf_addrw), + .di_b(rf_dataw), + .do_b() +); +*/ +// +// Instantiation of register file two-port RAM B +// + +dual_port_ram rf_b( + .clk (clk), + .we1(const_zero), + .we2(rf_we), + .data1(const_zero_data), + .data2(rf_dataw), + .out1(from_rfb), + .out2 (dont_care_out2), + .addr1(addrb), + .addr2(rf_addrw)); +/* +or1200_tpram_32x32 rf_b( + // Port A + .clk_a(clk), + .rst_a(rst), + .ce_a(rf_enb), + .we_a(1'b0), + .oe_a(1'b1), + .addr_a(addrb), + .di_a(32'h00000000), + .do_a(from_rfb), + + // Port B + .clk_b(clk), + .rst_b(rst), + .ce_b(rf_we), + .we_b(rf_we), + .oe_b(1'b0), + .addr_b(rf_addrw), + .di_b(rf_dataw), + .do_b() +); +*/ +wire unused; +assign unused = |spr_addr; +endmodule + + + +module or1200_operandmuxes( + // Clock and reset + clk, rst, + + // Internal i/f + id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw, + simm, sel_a, sel_b, operand_a, operand_b, muxed_b +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input clk; +input rst; +input id_freeze; +input ex_freeze; +input [`OR1200_OPERAND_WIDTH-1:0] rf_dataa; +input [`OR1200_OPERAND_WIDTH-1:0] rf_datab; +input [`OR1200_OPERAND_WIDTH-1:0] ex_forw; +input [`OR1200_OPERAND_WIDTH-1:0] wb_forw; +input [`OR1200_OPERAND_WIDTH-1:0] simm; +input [`OR1200_SEL_WIDTH-1:0] sel_a; +input [`OR1200_SEL_WIDTH-1:0] sel_b; +output [`OR1200_OPERAND_WIDTH-1:0] operand_a; +output [`OR1200_OPERAND_WIDTH-1:0] operand_b; +output [`OR1200_OPERAND_WIDTH-1:0] muxed_b; + +// +// Internal wires and regs +// +reg [`OR1200_OPERAND_WIDTH-1:0] operand_a; +reg [`OR1200_OPERAND_WIDTH-1:0] operand_b; +reg [`OR1200_OPERAND_WIDTH-1:0] muxed_a; +reg [`OR1200_OPERAND_WIDTH-1:0] muxed_b; +reg saved_a; +reg saved_b; + +// +// Operand A register +// +always @(posedge clk ) begin + if (rst) begin + operand_a <= 32'b0000000000000000000000000000; + saved_a <= 1'b0; + end else if (!ex_freeze && id_freeze && !saved_a) begin + operand_a <= muxed_a; + saved_a <= 1'b1; + end else if (!ex_freeze && !saved_a) begin + operand_a <= muxed_a; + end else if (!ex_freeze && !id_freeze) + saved_a <= 1'b0; +end + +// +// Operand B register +// +always @(posedge clk ) begin + if (rst) begin + operand_b <= 32'b0000000000000000000000000000; + saved_b <= 1'b0; + end else if (!ex_freeze && id_freeze && !saved_b) begin + operand_b <= muxed_b; + saved_b <= 1'b1; + end else if (!ex_freeze && !saved_b) begin + operand_b <= muxed_b; + end else if (!ex_freeze && !id_freeze) + saved_b <= 1'b0; +end + +// +// Forwarding logic for operand A register +// +always @(ex_forw or wb_forw or rf_dataa or sel_a) begin + + case (sel_a) + `OR1200_SEL_EX_FORW: + muxed_a = ex_forw; + `OR1200_SEL_WB_FORW: + muxed_a = wb_forw; + default: + muxed_a = rf_dataa; + endcase +end + +// +// Forwarding logic for operand B register +// +always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin + + case (sel_b) // synopsys parallel_case + + `OR1200_SEL_IMM: + muxed_b = simm; + `OR1200_SEL_EX_FORW: + muxed_b = ex_forw; + `OR1200_SEL_WB_FORW: + muxed_b = wb_forw; + default: + muxed_b = rf_datab; + endcase +end + +endmodule + + + + + +module or1200_alu( + a, b, mult_mac_result, macrc_op, + alu_op, shrot_op, comp_op, + cust5_op, cust5_limm, + result, flagforw, flag_we, + cyforw, cy_we, flag,k_carry +); + +// +// I/O +// +input [32-1:0] a; +input [32-1:0] b; +input [32-1:0] mult_mac_result; +input macrc_op; +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; +input [2-1:0] shrot_op; +input [4-1:0] comp_op; +input [4:0] cust5_op; +input [5:0] cust5_limm; +output [32-1:0] result; +output flagforw; +output flag_we; +output cyforw; +output cy_we; +input k_carry; +input flag; + +// +// Internal wires and regs +// +reg [32-1:0] result; +reg [32-1:0] shifted_rotated; +reg [32-1:0] result_cust5; +reg flagforw; +reg flagcomp; +reg flag_we; +reg cy_we; +wire [32-1:0] comp_a; +wire [32-1:0] comp_b; + +wire a_eq_b; +wire a_lt_b; + +wire [32-1:0] result_sum; + +wire [32-1:0] result_csum; +wire cy_csum; + +wire [32-1:0] result_and; +wire cy_sum; +reg cyforw; + +// +// Combinatorial logic +// +assign comp_a [31:3]= a[31] ^ comp_op[3]; +assign comp_a [2:0] = a[30:0]; + +assign comp_b [31:3] = b[31] ^ comp_op[3] ; +assign comp_b [2:0] = b[32-2:0]; + +assign a_eq_b = (comp_a == comp_b); +assign a_lt_b = (comp_a < comp_b); + +assign cy_sum= a + b; +assign result_sum = a+b; +assign cy_csum =a + b + {32'b00000000000000000000000000000000, k_carry}; +assign result_csum = a + b + {32'b00000000000000000000000000000000, k_carry}; + +assign result_and = a & b; + + + +// Central part of the ALU +// +always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) +begin + + case (alu_op) // synopsys parallel_case + + 4'b1111: begin + result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0; + end + `OR1200_ALUOP_CUST5 : begin + result = result_cust5; + end + `OR1200_ALUOP_SHROT : begin + result = shifted_rotated; + end + `OR1200_ALUOP_ADD : begin + result = result_sum; + end + + `OR1200_ALUOP_ADDC : begin + result = result_csum; + end + + `OR1200_ALUOP_SUB : begin + result = a - b; + end + `OR1200_ALUOP_XOR : begin + result = a ^ b; + end + `OR1200_ALUOP_OR : begin + result = a | b; + end + `OR1200_ALUOP_IMM : begin + result = b; + end + `OR1200_ALUOP_MOVHI : begin + if (macrc_op) begin + result = mult_mac_result; + end + else begin + result = b << 16; + end + end + + `OR1200_ALUOP_MUL : begin + result = mult_mac_result; + end + + 4'b1110: begin + result = flag ? a : b; + end + + default: + begin + result=result_and; + end + endcase +end + +// +// l.cust5 custom instructions +// +// Examples for move byte, set bit and clear bit +// +always @(cust5_op or cust5_limm or a or b) begin + case (cust5_op) // synopsys parallel_case + 5'h1 : begin + case (cust5_limm[1:0]) + 2'h0: result_cust5 = {a[31:8], b[7:0]}; + 2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]}; + 2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]}; + 2'h3: result_cust5 = {b[7:0], a[23:0]}; + endcase + end + 5'h2 : + result_cust5 = a | (1 << 4); + 5'h3 : + result_cust5 = a & (32'b11111111111111111111111111111111^ (cust5_limm)); +// +// *** Put here new l.cust5 custom instructions *** +// + default: begin + result_cust5 = a; + end + endcase +end + +// +// Generate flag and flag write enable +// +always @(alu_op or result_sum or result_and or flagcomp) begin + case (alu_op) // synopsys parallel_case + + `OR1200_ALUOP_ADD : begin + flagforw = (result_sum == 32'b00000000000000000000000000000000); + flag_we = 1'b1; + end + + `OR1200_ALUOP_ADDC : begin + flagforw = (result_csum == 32'b00000000000000000000000000000000); + flag_we = 1'b1; + end + + `OR1200_ALUOP_AND: begin + flagforw = (result_and == 32'b00000000000000000000000000000000); + flag_we = 1'b1; + end + + `OR1200_ALUOP_COMP: begin + flagforw = flagcomp; + flag_we = 1'b1; + end + default: begin + flagforw = 1'b0; + flag_we = 1'b0; + end + endcase +end + +// +// Generate SR[CY] write enable +// +always @(alu_op or cy_sum + + + ) begin + case (alu_op) // synopsys parallel_case + + `OR1200_ALUOP_ADD : begin + cyforw = cy_sum; + cy_we = 1'b1; + end + + `OR1200_ALUOP_ADDC: begin + cyforw = cy_csum; + cy_we = 1'b1; + end + + default: begin + cyforw = 1'b0; + cy_we = 1'b0; + end + endcase +end + +// +// Shifts and rotation +// +always @(shrot_op or a or b) begin + case (shrot_op) // synopsys parallel_case + 2'b00 : + shifted_rotated = (a << 2); + `OR1200_SHROTOP_SRL : + shifted_rotated = (a >> 2); + + + `OR1200_SHROTOP_ROR : + shifted_rotated = (a << 1'b1); + default: + shifted_rotated = (a << 1); + endcase +end + +// +// First type of compare implementation +// +always @(comp_op or a_eq_b or a_lt_b) begin + case(comp_op[2:0]) // synopsys parallel_case + `OR1200_COP_SFEQ: + flagcomp = a_eq_b; + `OR1200_COP_SFNE: + flagcomp = ~a_eq_b; + `OR1200_COP_SFGT: + flagcomp = ~(a_eq_b | a_lt_b); + `OR1200_COP_SFGE: + flagcomp = ~a_lt_b; + `OR1200_COP_SFLT: + flagcomp = a_lt_b; + `OR1200_COP_SFLE: + flagcomp = a_eq_b | a_lt_b; + default: + flagcomp = 1'b0; + endcase +end + +// + +endmodule + + + + +module or1200_mult_mac( + // Clock and reset + clk, rst, + + // Multiplier/MAC interface + ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r, + + // SPR interface + spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Multiplier/MAC interface +// +input ex_freeze; +input id_macrc_op; +input macrc_op; +input [`OR1200_OPERAND_WIDTH-1:0] a; +input [`OR1200_OPERAND_WIDTH-1:0] b; +input [`OR1200_MACOP_WIDTH-1:0] mac_op; +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; +output [`OR1200_OPERAND_WIDTH-1:0] result; +output mac_stall_r; + +// +// SPR interface +// +input spr_cs; +input spr_write; +input [31:0] spr_addr; +input [31:0] spr_dat_i; +output [31:0] spr_dat_o; + +// +// Internal wires and regs +// + +reg [`OR1200_OPERAND_WIDTH-1:0] result; +reg [2*`OR1200_OPERAND_WIDTH-1:0] mul_prod_r; + +wire [2*`OR1200_OPERAND_WIDTH-1:0] mul_prod; +wire [`OR1200_MACOP_WIDTH-1:0] mac_op; + +reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1; +reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2; +reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3; +reg mac_stall_r; +reg [2*`OR1200_OPERAND_WIDTH-1:0] mac_r; + +wire [`OR1200_OPERAND_WIDTH-1:0] x; +wire [`OR1200_OPERAND_WIDTH-1:0] y; +wire spr_maclo_we; +wire spr_machi_we; +wire alu_op_div_divu; +wire alu_op_div; +reg div_free; + +wire [`OR1200_OPERAND_WIDTH-1:0] div_tmp; +reg [5:0] div_cntr; + + +// +// Combinatorial logic +// + +assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR]; +assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR]; +assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32]; + +assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h00000000; +assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h00000000; +assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV); +assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU); +assign div_tmp = mul_prod_r[63:32] - y; + + + + +// +// Select result of current ALU operation to be forwarded +// to next instruction and to WB stage +// +always @(alu_op or mul_prod_r or mac_r or a or b) + case(alu_op) + + `OR1200_ALUOP_DIV: + result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0]; + `OR1200_ALUOP_DIVU: + begin + result = mul_prod_r[31:0]; + end + + `OR1200_ALUOP_MUL: begin + result = mul_prod_r[31:0]; + end + default: + + result = mac_r[31:0]; + + endcase + +// +// Instantiation of the multiplier +// + +// doing an implicit multiply here +assign mul_prod = x * y; +/* +or1200_gmultp2_32x32 or1200_gmultp2_32x32( + .X(x), + .Y(y), + .RST(rst), + .CLK(clk), + .P(mul_prod) +); +*/ + + +// +// Registered output from the multiplier and +// an optional divider +// +always @(posedge clk) + if (rst) begin + mul_prod_r <= 64'h0000000000000000; + div_free <= 1'b1; + + div_cntr <= 6'b000000; + + end + + else if (|div_cntr) begin + if (div_tmp[31]) + mul_prod_r <= {mul_prod_r[62:0], 1'b0}; + else + mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1}; + div_cntr <= div_cntr - 1'b1; + end + else if (alu_op_div_divu && div_free) begin + mul_prod_r <= {31'b0000000000000000000000000000000, x[31:0], 1'b0}; + div_cntr <= 6'b100000; + div_free <= 1'b0; + end + + else if (div_free | !ex_freeze) begin + mul_prod_r <= mul_prod[63:0]; + div_free <= 1'b1; + end + + +// Propagation of l.mac opcode +// +always @(posedge clk) + if (rst) + mac_op_r1 <= 2'b00; + else + mac_op_r1 <= mac_op; + +// +// Propagation of l.mac opcode +// +always @(posedge clk) + if (rst) + mac_op_r2 <= 2'b00; + else + mac_op_r2 <= mac_op_r1; + +// +// Propagation of l.mac opcode +// +always @(posedge clk ) + if (rst) + mac_op_r3 <= 2'b00; + else + mac_op_r3 <= mac_op_r2; + +// +// Implementation of MAC +// +always @(posedge clk) + if (rst) + mac_r <= 64'h0000000000000000; + + else if (spr_maclo_we) + mac_r[31:0] <= spr_dat_i; + else if (spr_machi_we) + mac_r[63:32] <= spr_dat_i; + + else if (mac_op_r3 == `OR1200_MACOP_MAC) + mac_r <= mac_r + mul_prod_r; + else if (mac_op_r3 == `OR1200_MACOP_MSB) + mac_r <= mac_r - mul_prod_r; + else if (macrc_op & !ex_freeze) + mac_r <= 64'h0000000000000000; + +// +// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions +// in EX stage (e.g. inside multiplier) +// This stall signal is also used by the divider. +// + +wire unused; +assign unused = |spr_addr; +always @( posedge clk) + if (rst) + mac_stall_r <= 1'b0; + else + mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op + + | (|div_cntr) + + ; + + + + +endmodule + + + + +module or1200_sprs( + // Clk & Rst + clk, rst, + + // Internal CPU interface + addrbase, addrofs, dat_i, alu_op, + flagforw, flag_we, flag, cyforw, cy_we, carry, to_wbmux, + + du_addr, du_dat_du, du_read, + du_write, du_dat_cpu, + + spr_addr,spr_dat_pic, spr_dat_tt, spr_dat_pm, + spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac, + spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_dat_o, spr_cs, spr_we, + + epcr_we, eear_we,esr_we, pc_we,epcr, eear, esr, except_started, + + sr_we, to_sr, sr,branch_op + +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O Ports +// + +// +// Internal CPU interface +// +input clk; // Clock +input rst; // Reset +input flagforw; // From ALU +input flag_we; // From ALU +output flag; // SR[F] +input cyforw; // From ALU +input cy_we; // From ALU +output carry; // SR[CY] +input [`OR1200_OPERAND_WIDTH-1:0] addrbase; // SPR base address +input [15:0] addrofs; // SPR offset +input [`OR1200_OPERAND_WIDTH-1:0] dat_i; // SPR write data +input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation +input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation +input [`OR1200_OPERAND_WIDTH-1:0] epcr; // EPCR0 +input [`OR1200_OPERAND_WIDTH-1:0] eear; // EEAR0 +input [`OR1200_SR_WIDTH-1:0] esr; // ESR0 +input except_started; // Exception was started +output [`OR1200_OPERAND_WIDTH-1:0] to_wbmux; // For l.mfspr +output epcr_we; // EPCR0 write enable +output eear_we; // EEAR0 write enable +output esr_we; // ESR0 write enable +output pc_we; // PC write enable +output sr_we; // Write enable SR +output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR +output [`OR1200_SR_WIDTH-1:0] sr; // SR +input [31:0] spr_dat_cfgr; // Data from CFGR +input [31:0] spr_dat_rf; // Data from RF +input [31:0] spr_dat_npc; // Data from NPC +input [31:0] spr_dat_ppc; // Data from PPC +input [31:0] spr_dat_mac; // Data from MAC + +// +// To/from other RISC units +// +input [31:0] spr_dat_pic; // Data from PIC +input [31:0] spr_dat_tt; // Data from TT +input [31:0] spr_dat_pm; // Data from PM +input [31:0] spr_dat_dmmu; // Data from DMMU +input [31:0] spr_dat_immu; // Data from IMMU +input [31:0] spr_dat_du; // Data from DU +output [31:0] spr_addr; // SPR Address +output [31:0] spr_dat_o; // Data to unit +output [31:0] spr_cs; // Unit select +output spr_we; // SPR write enable + +// +// To/from Debug Unit +// +input [`OR1200_OPERAND_WIDTH-1:0] du_addr; // Address +input [`OR1200_OPERAND_WIDTH-1:0] du_dat_du; // Data from DU to SPRS +input du_read; // Read qualifier +input du_write; // Write qualifier +output [`OR1200_OPERAND_WIDTH-1:0] du_dat_cpu; // Data from SPRS to DU + +// +// Internal regs & wires +// +reg [`OR1200_SR_WIDTH-1:0] sr; // SR +reg write_spr; // Write SPR +reg read_spr; // Read SPR +reg [`OR1200_OPERAND_WIDTH-1:0] to_wbmux; // For l.mfspr +wire cfgr_sel; // Select for cfg regs +wire rf_sel; // Select for RF +wire npc_sel; // Select for NPC +wire ppc_sel; // Select for PPC +wire sr_sel; // Select for SR +wire epcr_sel; // Select for EPCR0 +wire eear_sel; // Select for EEAR0 +wire esr_sel; // Select for ESR0 +wire [31:0] sys_data; // Read data from system SPRs +wire du_access; // Debug unit access +wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation +reg [31:0] unqualified_cs; // Unqualified chip selects + +// +// Decide if it is debug unit access +// +assign du_access = du_read | du_write; + +// +// Generate sprs opcode +// +assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op; + +// +// Generate SPR address from base address and offset +// OR from debug unit address +// +assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs}; + +// +// SPR is written by debug unit or by l.mtspr +// +assign spr_dat_o = du_write ? du_dat_du : dat_i; + +// +// debug unit data input: +// - write into debug unit SPRs by debug unit itself +// - read of SPRS by debug unit +// - write into debug unit SPRs by l.mtspr +// +assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i; + +// +// Write into SPRs when l.mtspr +// +assign spr_we = du_write | write_spr; + +// +// Qualify chip selects +// +assign spr_cs = unqualified_cs & {{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr},{read_spr | write_spr}}; + +// +// Decoding of groups +// +always @(spr_addr) + case (spr_addr[15:11]) + 5'b00000: unqualified_cs = 32'b00000000000000000000000000000001; + 5'b00001: unqualified_cs = 32'b00000000000000000000000000000010; + 5'b00010: unqualified_cs = 32'b00000000000000000000000000000100; + 5'b00011: unqualified_cs = 32'b00000000000000000000000000001000; + 5'b00100: unqualified_cs = 32'b00000000000000000000000000010000; + 5'b00101: unqualified_cs = 32'b00000000000000000000000000100000; + 5'b00110: unqualified_cs = 32'b00000000000000000000000001000000; + 5'b00111: unqualified_cs = 32'b00000000000000000000000010000000; + 5'b01000: unqualified_cs = 32'b00000000000000000000000100000000; + 5'b01001: unqualified_cs = 32'b00000000000000000000001000000000; + 5'b01010: unqualified_cs = 32'b00000000000000000000010000000000; + 5'b01011: unqualified_cs = 32'b00000000000000000000100000000000; + 5'b01100: unqualified_cs = 32'b00000000000000000001000000000000; + 5'b01101: unqualified_cs = 32'b00000000000000000010000000000000; + 5'b01110: unqualified_cs = 32'b00000000000000000100000000000000; + 5'b01111: unqualified_cs = 32'b00000000000000001000000000000000; + 5'b10000: unqualified_cs = 32'b00000000000000010000000000000000; + 5'b10001: unqualified_cs = 32'b00000000000000100000000000000000; + 5'b10010: unqualified_cs = 32'b00000000000001000000000000000000; + 5'b10011: unqualified_cs = 32'b00000000000010000000000000000000; + 5'b10100: unqualified_cs = 32'b00000000000100000000000000000000; + 5'b10101: unqualified_cs = 32'b00000000001000000000000000000000; + 5'b10110: unqualified_cs = 32'b00000000010000000000000000000000; + 5'b10111: unqualified_cs = 32'b00000000100000000000000000000000; + 5'b11000: unqualified_cs = 32'b00000001000000000000000000000000; + 5'b11001: unqualified_cs = 32'b00000010000000000000000000000000; + 5'b11010: unqualified_cs = 32'b00000100000000000000000000000000; + 5'b11011: unqualified_cs = 32'b00001000000000000000000000000000; + 5'b11100: unqualified_cs = 32'b00010000000000000000000000000000; + 5'b11101: unqualified_cs = 32'b00100000000000000000000000000000; + 5'b11110: unqualified_cs = 32'b01000000000000000000000000000000; + 5'b11111: unqualified_cs = 32'b10000000000000000000000000000000; + endcase + +// +// SPRs System Group +// + +// +// What to write into SR +// +assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] : + (write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}: + sr[`OR1200_SR_FO:`OR1200_SR_OV]; +assign to_sr[`OR1200_SR_CY] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] : + cy_we ? cyforw : + (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] : + sr[`OR1200_SR_CY]; +assign to_sr[`OR1200_SR_F] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] : + flag_we ? flagforw : + (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] : + sr[`OR1200_SR_F]; +assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] = + (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] : + (write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]: + sr[`OR1200_SR_CE:`OR1200_SR_SM]; + +// +// Selects for system SPRs +// +assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR)); +assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF)); +assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC)); +assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC)); +assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR)); +assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR)); +assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR)); +assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR)); + +// +// Write enables for system SPRs +// +assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we; +assign pc_we = (write_spr && (npc_sel | ppc_sel)); +assign epcr_we = (write_spr && epcr_sel); +assign eear_we = (write_spr && eear_sel); +assign esr_we = (write_spr && esr_sel); + +// +// Output from system SPRs +// +assign sys_data = (spr_dat_cfgr & {{read_spr & cfgr_sel}}) | + (spr_dat_rf & {{read_spr & rf_sel}}) | + (spr_dat_npc & {{read_spr & npc_sel}}) | + (spr_dat_ppc & {{read_spr & ppc_sel}}) | + ({{{16'b0000000000000000}},sr} & {{read_spr & sr_sel}}) | + (epcr & {{read_spr & epcr_sel}}) | + (eear & {{read_spr & eear_sel}}) | + ({{{16'b0000000000000000}},esr} & {{read_spr & esr_sel}}); + +// +// Flag alias +// +assign flag = sr[`OR1200_SR_F]; + +// +// Carry alias +// +assign carry = sr[`OR1200_SR_CY]; + +// +// Supervision register +// +always @(posedge clk) + if (rst) + sr <= {1'b1, `OR1200_SR_EPH_DEF, {{13'b0000000000000}}, 1'b1}; + else if (except_started) begin + sr[`OR1200_SR_SM] <= 1'b1; + sr[`OR1200_SR_TEE] <= 1'b0; + sr[`OR1200_SR_IEE] <= 1'b0; + sr[`OR1200_SR_DME] <= 1'b0; + sr[`OR1200_SR_IME] <= 1'b0; + end + else if (sr_we) + sr <= to_sr[`OR1200_SR_WIDTH-1:0]; + +// +// MTSPR/MFSPR interface +// +always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or + spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin + case (sprs_op) // synopsys parallel_case + `OR1200_ALUOP_MTSR : begin + write_spr = 1'b1; + read_spr = 1'b0; + to_wbmux = 32'b00000000000000000000000000000000; + end + `OR1200_ALUOP_MFSR : begin + case (spr_addr[15:11]) // synopsys parallel_case + `OR1200_SPR_GROUP_TT: + to_wbmux = spr_dat_tt; + `OR1200_SPR_GROUP_PIC: + to_wbmux = spr_dat_pic; + `OR1200_SPR_GROUP_PM: + to_wbmux = spr_dat_pm; + `OR1200_SPR_GROUP_DMMU: + to_wbmux = spr_dat_dmmu; + `OR1200_SPR_GROUP_IMMU: + to_wbmux = spr_dat_immu; + `OR1200_SPR_GROUP_MAC: + to_wbmux = spr_dat_mac; + `OR1200_SPR_GROUP_DU: + to_wbmux = spr_dat_du; + `OR1200_SPR_GROUP_SYS: + to_wbmux = sys_data; + default: + to_wbmux = 32'b00000000000000000000000000000000; + endcase + write_spr = 1'b0; + read_spr = 1'b1; + end + default : begin + write_spr = 1'b0; + read_spr = 1'b0; + to_wbmux = 32'b00000000000000000000000000000000; + end + endcase +end + +endmodule + + + + + +`define OR1200_NO_FREEZE 3'b000 +`define OR1200_FREEZE_BYDC 3'b001 +`define OR1200_FREEZE_BYMULTICYCLE 3'b010 +`define OR1200_WAIT_LSU_TO_FINISH 3'b011 +`define OR1200_WAIT_IC 3'b100 + +// +// Freeze logic (stalls CPU pipeline, ifetcher etc.) +// +module or1200_freeze( + // Clock and reset + clk, rst, + + // Internal i/f + multicycle, flushpipe, extend_flush, lsu_stall, if_stall, + lsu_unstall, + force_dslot_fetch, abort_ex, du_stall, mac_stall, + genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze, + icpu_ack_i, icpu_err_i +); + +// +// I/O +// +input clk; +input rst; +input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; +input flushpipe; +input extend_flush; +input lsu_stall; +input if_stall; +input lsu_unstall; +input force_dslot_fetch; +input abort_ex; +input du_stall; +input mac_stall; +output genpc_freeze; +output if_freeze; +output id_freeze; +output ex_freeze; +output wb_freeze; +input icpu_ack_i; +input icpu_err_i; + +// +// Internal wires and regs +// +wire multicycle_freeze; +reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt; +reg flushpipe_r; + +// +// Pipeline freeze +// +// Rules how to create freeze signals: +// 1. Not overwriting pipeline stages: +// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more +// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never +// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc. +// +// 2. Inserting NOPs in the middle of pipeline only if supported: +// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted. +// This way NOP is asserted from stage ID into EX stage. +// +//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall; +assign genpc_freeze = du_stall | flushpipe_r; +assign if_freeze = id_freeze | extend_flush; +//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall; +assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall; +assign ex_freeze = wb_freeze; +//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall; +assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex; + +// +// registered flushpipe +// +always @(posedge clk ) + if (rst) + flushpipe_r <= 1'b0; + else if (icpu_ack_i | icpu_err_i) +// else if (!if_stall) + flushpipe_r <= flushpipe; + else if (!flushpipe) + flushpipe_r <= 1'b0; + +// +// Multicycle freeze +// +assign multicycle_freeze = |multicycle_cnt; + +// +// Multicycle counter +// +always @(posedge clk ) + if (rst) + multicycle_cnt <= 2'b00; + else if (|multicycle_cnt) + multicycle_cnt <= multicycle_cnt - 2'b01; + else if (|multicycle & !ex_freeze) + multicycle_cnt <= multicycle; + +endmodule + + + + +`define OR1200_EXCEPTFSM_WIDTH 3 + +`define OR1200_EXCEPTFSM_IDLE 3'b000 +`define OR1200_EXCEPTFSM_FLU1 3'b001 +`define OR1200_EXCEPTFSM_FLU2 3'b010 +`define OR1200_EXCEPTFSM_FLU3 3'b011 +`define OR1200_EXCEPTFSM_FLU5 3'b101 +`define OR1200_EXCEPTFSM_FLU4 3'b100 + +// +// Exception recognition and sequencing +// + +module or1200_except( + // Clock and reset + clk, rst, + + // Internal i/f + sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault, + sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick, + branch_taken,icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, + genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall, + if_pc, id_pc, lr_sav, flushpipe, extend_flush, except_type, except_start, + except_started, except_stop, ex_void, + spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, + esr, lsu_addr, sr_we, to_sr, sr, abort_ex +); + +// +// I/O +// +input clk; +input rst; +input sig_ibuserr; +input sig_dbuserr; +input sig_illegal; +input sig_align; +input sig_range; +input sig_dtlbmiss; +input sig_dmmufault; +input sig_int; +input sig_syscall; +input sig_trap; +input sig_itlbmiss; +input sig_immufault; +input sig_tick; +input branch_taken; +input genpc_freeze; +input id_freeze; +input ex_freeze; +input wb_freeze; +input if_stall; +input [31:0] if_pc; +output [31:0] id_pc; +output [31:2] lr_sav; +input [31:0] datain; +input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; +input epcr_we; +input eear_we; +input esr_we; +input pc_we; +output [31:0] epcr; +output [31:0] eear; +output [`OR1200_SR_WIDTH-1:0] esr; +input [`OR1200_SR_WIDTH-1:0] to_sr; +input sr_we; +input [`OR1200_SR_WIDTH-1:0] sr; +input [31:0] lsu_addr; +output flushpipe; +output extend_flush; +output [`OR1200_EXCEPT_WIDTH-1:0] except_type; +output except_start; +output except_started; +output [12:0] except_stop; +input ex_void; +output [31:0] spr_dat_ppc; +output [31:0] spr_dat_npc; +output abort_ex; +input icpu_ack_i; +input icpu_err_i; +input dcpu_ack_i; +input dcpu_err_i; + +// +// Internal regs and wires +// +reg [`OR1200_EXCEPT_WIDTH-1:0] except_type; +reg [31:0] id_pc; +reg [31:0] ex_pc; +reg [31:0] wb_pc; +reg [31:0] epcr; +reg [31:0] eear; +reg [`OR1200_SR_WIDTH-1:0] esr; +reg [2:0] id_exceptflags; +reg [2:0] ex_exceptflags; +reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state; +reg extend_flush; +reg extend_flush_last; +reg ex_dslot; +reg delayed1_ex_dslot; +reg delayed2_ex_dslot; +wire except_started; +wire [12:0] except_trig; +wire except_flushpipe; +reg [2:0] delayed_iee; +reg [2:0] delayed_tee; +wire int_pending; +wire tick_pending; + +// +// Simple combinatorial logic +// +assign except_started = extend_flush & except_start; +assign lr_sav = ex_pc[31:2]; +assign spr_dat_ppc = wb_pc; +assign spr_dat_npc = ex_void ? id_pc : ex_pc; +assign except_start = (except_type != 4'b0000) & extend_flush; +assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we; +assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we; +assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions + +// +// Order defines exception detection priority +// +assign except_trig = { + tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE], + int_pending & ~du_dsr[`OR1200_DU_DSR_IE], + ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME], + ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE], + ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE], + sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE], + sig_align & ~du_dsr[`OR1200_DU_DSR_AE], + sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME], + sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE], + sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE], + sig_range & ~du_dsr[`OR1200_DU_DSR_RE], + sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze, + sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze + }; +assign except_stop = { + tick_pending & du_dsr[`OR1200_DU_DSR_TTE], + int_pending & du_dsr[`OR1200_DU_DSR_IE], + ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME], + ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE], + ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE], + sig_illegal & du_dsr[`OR1200_DU_DSR_IIE], + sig_align & du_dsr[`OR1200_DU_DSR_AE], + sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME], + sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE], + sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE], + sig_range & du_dsr[`OR1200_DU_DSR_RE], + sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze, + sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze + }; + +// +// PC and Exception flags pipelines +// +always @(posedge clk ) begin + if (rst) begin + id_pc <= 32'b00000000000000000000000000000000; + id_exceptflags <= 3'b000; + end + else if (flushpipe) begin + id_pc <= 32'h00000000; + id_exceptflags <= 3'b000; + end + else if (!id_freeze) begin + id_pc <= if_pc; + id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault }; + end +end + +// +// delayed_iee +// +// SR[IEE] should not enable interrupts right away +// when it is restored with l.rfe. Instead delayed_iee +// together with SR[IEE] enables interrupts once +// pipeline is again ready. +// +always @(posedge clk) + if (rst) + delayed_iee <= 3'b000; + else if (!sr[`OR1200_SR_IEE]) + delayed_iee <= 3'b000; + else + delayed_iee <= {delayed_iee[1:0], 1'b1}; + +// +// delayed_tee +// +// SR[TEE] should not enable tick exceptions right away +// when it is restored with l.rfe. Instead delayed_tee +// together with SR[TEE] enables tick exceptions once +// pipeline is again ready. +// +always @( posedge clk) + if (rst) + delayed_tee <= 3'b000; + else if (!sr[`OR1200_SR_TEE]) + delayed_tee <= 3'b000; + else + delayed_tee <= {delayed_tee[1:0], 1'b1}; + +// +// PC and Exception flags pipelines +// +always @(posedge clk ) begin + if (rst) begin + ex_dslot <= 1'b0; + ex_pc <= 32'd0; + ex_exceptflags <= 3'b000; + delayed1_ex_dslot <= 1'b0; + delayed2_ex_dslot <= 1'b0; + end + else if (flushpipe) begin + ex_dslot <= 1'b0; + ex_pc <= 32'h00000000; + ex_exceptflags <= 3'b000; + delayed1_ex_dslot <= 1'b0; + delayed2_ex_dslot <= 1'b0; + end + else if (!ex_freeze & id_freeze) begin + ex_dslot <= 1'b0; + ex_pc <= id_pc; + ex_exceptflags <= 3'b000; + delayed1_ex_dslot <= ex_dslot; + delayed2_ex_dslot <= delayed1_ex_dslot; + end + else if (!ex_freeze) begin + ex_dslot <= branch_taken; + ex_pc <= id_pc; + ex_exceptflags <= id_exceptflags; + delayed1_ex_dslot <= ex_dslot; + delayed2_ex_dslot <= delayed1_ex_dslot; + end +end + +// +// PC and Exception flags pipelines +// +always @(posedge clk ) begin + if (rst) begin + wb_pc <= 32'b00000000000000000000000000000000; + end + else if (!wb_freeze) begin + wb_pc <= ex_pc; + end +end + +// +// Flush pipeline +// +assign flushpipe = except_flushpipe | pc_we | extend_flush; + +// +// We have started execution of exception handler: +// 1. Asserted for 3 clock cycles +// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler +// +assign except_flushpipe = |except_trig & ~|state; + +// +// Exception FSM that sequences execution of exception handler +// +// except_type signals which exception handler we start fetching in: +// 1. Asserted in next clock cycle after exception is recognized +// +always @(posedge clk ) begin + if (rst) begin + state <= `OR1200_EXCEPTFSM_IDLE; + except_type <= 4'b0000; + extend_flush <= 1'b0; + epcr <= 32'b00000000000000000000000000000000; + eear <= 32'b00000000000000000000000000000000; + esr <= {{1'b1, 1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0},{1'b0}, {1'b1}}; + extend_flush_last <= 1'b0; + end + else begin + + case (state) + `OR1200_EXCEPTFSM_IDLE: + if (except_flushpipe) begin + state <= `OR1200_EXCEPTFSM_FLU1; + extend_flush <= 1'b1; + esr <= sr_we ? to_sr : sr; + + if (except_trig[12] == 1) + begin + except_type <= `OR1200_EXCEPT_TICK; + epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + else if (except_trig[12] == 0 && except_trig[11] == 0) + begin + except_type <= `OR1200_EXCEPT_INT; + epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + else if (except_trig[12] == 0 && except_trig[11] == 0 && except_trig[10] == 1) + begin + except_type <= `OR1200_EXCEPT_ITLBMISS; +// +// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?) +// eear <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// mmu-icdc-O2 ex_pc only OK when no ex_dslot eear <= ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// mmu-icdc-O2 ex_pc only OK when no ex_dslot epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + eear <= ex_dslot ? ex_pc : ex_pc; + epcr <= ex_dslot ? wb_pc : ex_pc; +// eear <= ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; +// epcr <= ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; + end + else + begin + except_type <= 4'b0000; + end + end + else if (pc_we) begin + state <= `OR1200_EXCEPTFSM_FLU1; + extend_flush <= 1'b1; + end + else begin + if (epcr_we) + epcr <= datain; + if (eear_we) + eear <= datain; + if (esr_we) + esr <= {1'b1, datain[`OR1200_SR_WIDTH-2:0]}; + end + `OR1200_EXCEPTFSM_FLU1: + if (icpu_ack_i | icpu_err_i | genpc_freeze) + state <= `OR1200_EXCEPTFSM_FLU2; + `OR1200_EXCEPTFSM_FLU2: + state <= `OR1200_EXCEPTFSM_FLU3; + `OR1200_EXCEPTFSM_FLU3: + begin + state <= `OR1200_EXCEPTFSM_FLU4; + end + `OR1200_EXCEPTFSM_FLU4: begin + state <= `OR1200_EXCEPTFSM_FLU5; + extend_flush <= 1'b0; + extend_flush_last <= 1'b0; // damjan + end + + default: begin + if (!if_stall && !id_freeze) begin + state <= `OR1200_EXCEPTFSM_IDLE; + except_type <= 4'b0000; + extend_flush_last <= 1'b0; + end + end + endcase + end +end + +wire unused; +assign unused = sig_range | sig_syscall | sig_trap | dcpu_ack_i| dcpu_err_i | du_dsr | lsu_addr; +endmodule + + + + + +module or1200_cfgr( + // RISC Internal Interface + spr_addr, spr_dat_o +); + +// +// RISC Internal Interface +// +input [31:0] spr_addr; // SPR Address +output [31:0] spr_dat_o; // SPR Read Data + +// +// Internal wires & registers +// +reg [31:0] spr_dat_o; // SPR Read Data + + + +// +// Implementation of VR, UPR and configuration registers +// +always @(spr_addr) + if (~|spr_addr[31:4]) + + case(spr_addr[3:0]) // synopsys parallel_case + `OR1200_SPRGRP_SYS_VR: begin + spr_dat_o[5:0] = `OR1200_VR_REV; + spr_dat_o[16:6] = `OR1200_VR_RES1; + spr_dat_o[23:17] = `OR1200_VR_CFG; + spr_dat_o[31:24] = `OR1200_VR_VER; + end + `OR1200_SPRGRP_SYS_UPR: begin + spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP; + spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP; + spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP; + spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP; + spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP; + spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP; + spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP; + spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP; + spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP; + spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP; + spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP; + spr_dat_o[23:11] = `OR1200_UPR_RES1; + spr_dat_o[31:24] = `OR1200_UPR_CUP; + end + `OR1200_SPRGRP_SYS_CPUCFGR: begin + spr_dat_o[3:0] = `OR1200_CPUCFGR_NSGF; + spr_dat_o[`OR1200_CPUCFGR_HGF_BITS] = `OR1200_CPUCFGR_HGF; + spr_dat_o[`OR1200_CPUCFGR_OB32S_BITS] = `OR1200_CPUCFGR_OB32S; + spr_dat_o[`OR1200_CPUCFGR_OB64S_BITS] = `OR1200_CPUCFGR_OB64S; + spr_dat_o[`OR1200_CPUCFGR_OF32S_BITS] = `OR1200_CPUCFGR_OF32S; + spr_dat_o[`OR1200_CPUCFGR_OF64S_BITS] = `OR1200_CPUCFGR_OF64S; + spr_dat_o[`OR1200_CPUCFGR_OV64S_BITS] = `OR1200_CPUCFGR_OV64S; + spr_dat_o[31:10] = `OR1200_CPUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DMMUCFGR: begin + spr_dat_o[1:0] = `OR1200_DMMUCFGR_NTW; + spr_dat_o[4:2] = `OR1200_DMMUCFGR_NTS; + spr_dat_o[7:5] = `OR1200_DMMUCFGR_NAE; + spr_dat_o[`OR1200_DMMUCFGR_CRI_BITS] = `OR1200_DMMUCFGR_CRI; + spr_dat_o[`OR1200_DMMUCFGR_PRI_BITS] = `OR1200_DMMUCFGR_PRI; + spr_dat_o[`OR1200_DMMUCFGR_TEIRI_BITS] = `OR1200_DMMUCFGR_TEIRI; + spr_dat_o[`OR1200_DMMUCFGR_HTR_BITS] = `OR1200_DMMUCFGR_HTR; + spr_dat_o[31:12] = `OR1200_DMMUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_IMMUCFGR: begin + spr_dat_o[1:0] = `OR1200_IMMUCFGR_NTW; + spr_dat_o[4:2] = `OR1200_IMMUCFGR_NTS; + spr_dat_o[7:5] = `OR1200_IMMUCFGR_NAE; + spr_dat_o[`OR1200_IMMUCFGR_CRI_BITS] = `OR1200_IMMUCFGR_CRI; + spr_dat_o[`OR1200_IMMUCFGR_PRI_BITS] = `OR1200_IMMUCFGR_PRI; + spr_dat_o[`OR1200_IMMUCFGR_TEIRI_BITS] = `OR1200_IMMUCFGR_TEIRI; + spr_dat_o[`OR1200_IMMUCFGR_HTR_BITS] = `OR1200_IMMUCFGR_HTR; + spr_dat_o[31:12] = `OR1200_IMMUCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DCCFGR: begin + spr_dat_o[2:0] = `OR1200_DCCFGR_NCW; + spr_dat_o[6:3] = `OR1200_DCCFGR_NCS; + spr_dat_o[`OR1200_DCCFGR_CBS_BITS] = `OR1200_DCCFGR_CBS; + spr_dat_o[`OR1200_DCCFGR_CWS_BITS] = `OR1200_DCCFGR_CWS; + spr_dat_o[`OR1200_DCCFGR_CCRI_BITS] = `OR1200_DCCFGR_CCRI; + spr_dat_o[`OR1200_DCCFGR_CBIRI_BITS] = `OR1200_DCCFGR_CBIRI; + spr_dat_o[`OR1200_DCCFGR_CBPRI_BITS] = `OR1200_DCCFGR_CBPRI; + spr_dat_o[`OR1200_DCCFGR_CBLRI_BITS] = `OR1200_DCCFGR_CBLRI; + spr_dat_o[`OR1200_DCCFGR_CBFRI_BITS] = `OR1200_DCCFGR_CBFRI; + spr_dat_o[`OR1200_DCCFGR_CBWBRI_BITS] = `OR1200_DCCFGR_CBWBRI; + spr_dat_o[31:15] = `OR1200_DCCFGR_RES1; + end + `OR1200_SPRGRP_SYS_ICCFGR: begin + spr_dat_o[2:0] = `OR1200_ICCFGR_NCW; + spr_dat_o[6:3] = `OR1200_ICCFGR_NCS; + spr_dat_o[`OR1200_ICCFGR_CBS_BITS] = `OR1200_ICCFGR_CBS; + spr_dat_o[`OR1200_ICCFGR_CWS_BITS] = `OR1200_ICCFGR_CWS; + spr_dat_o[`OR1200_ICCFGR_CCRI_BITS] = `OR1200_ICCFGR_CCRI; + spr_dat_o[`OR1200_ICCFGR_CBIRI_BITS] = `OR1200_ICCFGR_CBIRI; + spr_dat_o[`OR1200_ICCFGR_CBPRI_BITS] = `OR1200_ICCFGR_CBPRI; + spr_dat_o[`OR1200_ICCFGR_CBLRI_BITS] = `OR1200_ICCFGR_CBLRI; + spr_dat_o[`OR1200_ICCFGR_CBFRI_BITS] = `OR1200_ICCFGR_CBFRI; + spr_dat_o[`OR1200_ICCFGR_CBWBRI_BITS] = `OR1200_ICCFGR_CBWBRI; + spr_dat_o[31:15] = `OR1200_ICCFGR_RES1; + end + `OR1200_SPRGRP_SYS_DCFGR: begin + spr_dat_o[2:0] = `OR1200_DCFGR_NDP; + spr_dat_o[3] = `OR1200_DCFGR_WPCI; + spr_dat_o[31:4] = `OR1200_DCFGR_RES1; + end + default: spr_dat_o = 32'h00000000; + endcase + + + +// + +endmodule + +module or1200_wbmux( + // Clock and reset + clk, rst, + + // Internal i/f + wb_freeze, rfwb_op, + muxin_a, muxin_b, muxin_c, muxin_d, + muxout, muxreg, muxreg_valid +); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// + +// +// Clock and reset +// +input clk; +input rst; + +// +// Internal i/f +// +input wb_freeze; +input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; +input [32-1:0] muxin_a; +input [32-1:0] muxin_b; +input [32-1:0] muxin_c; +input [32-1:0] muxin_d; +output [32-1:0] muxout; +output [32-1:0] muxreg; +output muxreg_valid; + +// +// Internal wires and regs +// +reg [32-1:0] muxout; +reg [32-1:0] muxreg; +reg muxreg_valid; + +// +// Registered output from the write-back multiplexer +// +always @(posedge clk) begin + if (rst) begin + muxreg <= 32'b00000000000000000000000000000000; + muxreg_valid <= 1'b0; + end + else if (!wb_freeze) begin + muxreg <= muxout; + muxreg_valid <= rfwb_op[0]; + end +end + +// +// Write-back multiplexer +// +always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin + case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) + 2'b00: muxout = muxin_a; + 2'b01: begin + muxout = muxin_b; + end + 2'b10: begin + muxout = muxin_c; + end + 2'b11: begin + muxout = muxin_d + 32'b00000000000000000000000000001000; + end + endcase +end + +endmodule + + + +module or1200_lsu( + + // Internal i/f + addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall, + du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr, + + // External i/f to DC + dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o, + dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i +); + +//parameter dw = `OR1200_OPERAND_WIDTH; +//parameter aw = `OR1200_REGFILE_ADDR_WIDTH; + +// +// I/O +// + +// +// Internal i/f +// +input [31:0] addrbase; +input [31:0] addrofs; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [`OR1200_OPERAND_WIDTH-1:0] lsu_datain; +output [`OR1200_OPERAND_WIDTH-1:0] lsu_dataout; +output lsu_stall; +output lsu_unstall; +input du_stall; +output except_align; +output except_dtlbmiss; +output except_dmmufault; +output except_dbuserr; + +// +// External i/f to DC +// +output [31:0] dcpu_adr_o; +output dcpu_cycstb_o; +output dcpu_we_o; +output [3:0] dcpu_sel_o; +output [3:0] dcpu_tag_o; +output [31:0] dcpu_dat_o; +input [31:0] dcpu_dat_i; +input dcpu_ack_i; +input dcpu_rty_i; +input dcpu_err_i; +input [3:0] dcpu_tag_i; + +// +// Internal wires/regs +// +reg [3:0] dcpu_sel_o; + +// +// Internal I/F assignments +// +assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o; +assign lsu_unstall = dcpu_ack_i; +assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0] + | ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0]; +assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE); +assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE); +assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE); + +// +// External I/F assignments +// +assign dcpu_adr_o = addrbase + addrofs; +assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op; +assign dcpu_we_o = lsu_op[3]; +assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE; +always @(lsu_op or dcpu_adr_o) + case({lsu_op, dcpu_adr_o[1:0]}) + {`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111; + {`OR1200_LSUOP_LBZ, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000; + {`OR1200_LSUOP_LBZ, 2'b01}: dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100; + {`OR1200_LSUOP_LBZ, 2'b10}: dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010; + {`OR1200_LSUOP_LBZ, 2'b11}: dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001; + {`OR1200_LSUOP_LHZ, 2'b00}: dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100; + {`OR1200_LSUOP_LHZ, 2'b10}: dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011; + {`OR1200_LSUOP_LWZ, 2'b00}: dcpu_sel_o = 4'b1111; + {4'b1111, 2'b00} : dcpu_sel_o = 4'b1111; + default : dcpu_sel_o = 4'b0000; + endcase + +// +// Instantiation of Memory-to-regfile aligner +// +or1200_mem2reg or1200_mem2reg( + .addr(dcpu_adr_o[1:0]), + .lsu_op(lsu_op), + .memdata(dcpu_dat_i), + .regdata(lsu_dataout) +); + +// +// Instantiation of Regfile-to-memory aligner +// +or1200_reg2mem or1200_reg2mem( + .addr(dcpu_adr_o[1:0]), + .lsu_op(lsu_op), + .regdata(lsu_datain), + .memdata(dcpu_dat_o) +); + +endmodule + + + + +module or1200_reg2mem(addr, lsu_op, regdata, memdata); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [1:0] addr; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [32-1:0] regdata; +output [32-1:0] memdata; + +// +// Internal regs and wires +// +reg [7:0] memdata_hh; +reg [7:0] memdata_hl; +reg [7:0] memdata_lh; +reg [7:0] memdata_ll; + +assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll}; + +// +// Mux to memdata[31:24] +// +always @(lsu_op or addr or regdata) begin + case({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0]; + {`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8]; + default : memdata_hh = regdata[31:24]; + endcase +end + +// +// Mux to memdata[23:16] +// +always @(lsu_op or addr or regdata) begin + case({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16]; + default : memdata_hl = regdata[7:0]; + endcase +end + +// +// Mux to memdata[15:8] +// +always @(lsu_op or addr or regdata) begin + case({lsu_op, addr[1:0]}) // synopsys parallel_case + {`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0]; + default : memdata_lh = regdata[15:8]; + endcase +end + +// +// Mux to memdata[7:0] +// +always @(regdata) + memdata_ll = regdata[7:0]; + +endmodule + + + +module or1200_mem2reg(addr, lsu_op, memdata, regdata); + +//parameter width = `OR1200_OPERAND_WIDTH; + +// +// I/O +// +input [1:0] addr; +input [`OR1200_LSUOP_WIDTH-1:0] lsu_op; +input [32-1:0] memdata; +output [32-1:0] regdata; +wire [32-1:0] regdata; + +// +// In the past faster implementation of mem2reg (today probably slower) +// +reg [7:0] regdata_hh; +reg [7:0] regdata_hl; +reg [7:0] regdata_lh; +reg [7:0] regdata_ll; +reg [32-1:0] aligned; +reg [3:0] sel_byte0, sel_byte1, + sel_byte2, sel_byte3; + +assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll}; + +// +// Byte select 0 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b011, 2'b00}: // lbz/lbs 0 + sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3 + {3'b011, 2'b01}: +sel_byte0 = `OR1200_M2R_BYTE2; + {3'b101, 2'b00}: // lhz/lhs 0 + sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2 + {3'b011, 2'b10}: // lbz/lbs 2 + sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1 + default: // all other cases + sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0 + endcase +end + +// +// Byte select 1 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'b00}: // lbz + sel_byte1 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: // lbs 0 + sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: // lbs 2 + sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + {3'b100, 2'b00}: // lhz/lhs 0 + sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3 + default: // all other cases + sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1 + endcase +end + +// +// Byte select 2 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'b00}: +sel_byte2 = `OR1200_M2R_ZERO; // lbz + {3'b100, 2'b00}: // lhz + sel_byte2 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: + sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b101, 2'b00}: // lhs 0 + sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: + sel_byte2 = `OR1200_M2R_EXTB1; + {3'b101, 2'b10}: // lhs 0 + sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + default: // all other cases + sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2 + endcase +end + +// +// Byte select 3 +// +always @(addr or lsu_op) begin + case({lsu_op[2:0], addr}) // synopsys parallel_case + {3'b010, 2'b00}: + sel_byte3 = `OR1200_M2R_ZERO; // zero extend // lbz + {3'b100, 2'b00}: // lhz + sel_byte3 = `OR1200_M2R_ZERO; // zero extend + {3'b011, 2'b00}: +sel_byte3 = `OR1200_M2R_EXTB3; + {3'b101, 2'b00}: // lhs 0 + sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3 + {3'b011, 2'b01}: // lbs 1 + sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2 + {3'b011, 2'b10}: + sel_byte3 = `OR1200_M2R_EXTB1; + {3'b101, 2'b10}: // lhs 0 + sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1 + {3'b011, 2'b11}: // lbs 3 + sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0 + default: // all other cases + sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3 + endcase +end + +// +// Byte 0 +// +always @(sel_byte0 or memdata) + begin + case(sel_byte0) + `OR1200_M2R_BYTE0: begin + regdata_ll = memdata[7:0]; + end + `OR1200_M2R_BYTE1: begin + regdata_ll = memdata[15:8]; + end + `OR1200_M2R_BYTE2: begin + regdata_ll = memdata[23:16]; + end + + default: begin + + regdata_ll = memdata[31:24]; + end + endcase +end + +// +// Byte 1 +// +always @(sel_byte1 or memdata) begin + + case(sel_byte1) + + `OR1200_M2R_ZERO: begin + regdata_lh = 8'h00; + end + `OR1200_M2R_BYTE1: begin + regdata_lh = memdata[15:8]; + end + `OR1200_M2R_BYTE3: begin + regdata_lh = memdata[31:24]; + end + `OR1200_M2R_EXTB0: begin + regdata_lh = {{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_lh = {{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_lh = {{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]}}; + end + default: begin + + regdata_lh = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end + endcase +end + +// +// Byte 2 +// +always @(sel_byte2 or memdata) begin + + + case(sel_byte2) + + `OR1200_M2R_ZERO: begin + regdata_hl = 8'h00; + end + `OR1200_M2R_BYTE2: begin + regdata_hl = memdata[23:16]; + end + `OR1200_M2R_EXTB0: begin + regdata_hl = {{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_hl = {{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_hl = {{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]}}; + end + default: begin + regdata_hl = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end + endcase +end + +// +// Byte 3 +// +always @(sel_byte3 or memdata) begin + + case(sel_byte3) + `OR1200_M2R_ZERO: begin + regdata_hh = 8'h00; + end + `OR1200_M2R_BYTE3: begin + regdata_hh = memdata[31:24]; + end + `OR1200_M2R_EXTB0: begin + regdata_hh = {{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]},{memdata[7]}}; + end + `OR1200_M2R_EXTB1: begin + regdata_hh = {{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]},{memdata[15]}}; + end + `OR1200_M2R_EXTB2: begin + regdata_hh = {{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]},{memdata[23]}}; + end + `OR1200_M2R_EXTB3: begin + regdata_hh = {{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]},{memdata[31]}}; + end + endcase +end + +// +// Straightforward implementation of mem2reg +// + +// reg [32-1:0] regdata; + +// +// Alignment +// +always @(addr or memdata) begin + case(addr) + 2'b00: + aligned = memdata; + 2'b01: + aligned = {memdata[23:0], 8'b00000000}; + 2'b10: + aligned = {memdata[15:0], 16'b0000000000000000}; + 2'b11: + aligned = {memdata[7:0], 24'b000000000000000000000000}; + endcase +end + +// +// Bytes +// +/* +always @(lsu_op or aligned) begin + case(lsu_op) + `OR1200_LSUOP_LBZ: begin + regdata[7:0] = aligned[31:24]; + regdata[31:8] = 24'b000000000000000000000000; + end + `OR1200_LSUOP_LBS: begin + regdata[7:0] = aligned[31:24]; + regdata[31:8] = {24'b000000000000000000000000}; + end + `OR1200_LSUOP_LHZ: begin + regdata[15:0] = aligned[31:16]; + regdata[31:16] = 16'b0000000000000000; + end + `OR1200_LSUOP_LHS: begin + regdata[15:0] = aligned[31:16]; + regdata[31:16] = {16'b0000000000000000}; + end + default: + regdata = aligned; + endcase +end +*/ +wire[8:0] unused_signal; +assign unused_signal = lsu_op; +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v b/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v new file mode 100755 index 000000000..2aaeec7a6 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v @@ -0,0 +1,2976 @@ + module paj_raygentop_hierarchy_no_mem (rgwant_addr, rgwant_data, rgread_ready, rgaddr_ready, rgdata_ready, rgwant_read, rgdatain, rgdataout, rgaddrin, rgCont, rgStat, rgCfgData, rgwant_CfgData, rgCfgData_ready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, tm3_clk_v0, fbdata, fbdatavalid, fbnextscanline, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource); + + output rgwant_addr; + wire rgwant_addr; + output rgwant_data; + wire rgwant_data; + output rgread_ready; + wire rgread_ready; + input rgaddr_ready; + input rgdata_ready; + + input rgwant_read; + input[63:0] rgdatain; + output[63:0] rgdataout; + wire[63:0] rgdataout; + input[17:0] rgaddrin; + input[31:0] rgCont; + output[31:0] rgStat; + wire[31:0] rgStat; + input[31:0] rgCfgData; + output rgwant_CfgData; + wire rgwant_CfgData; + input rgCfgData_ready; + + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_xhdl0; + output[18:0] tm3_sram_addr; + wire[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + wire[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + wire[1:0] tm3_sram_oe; + output tm3_sram_adsp; + wire tm3_sram_adsp; + input tm3_clk_v0; + + output[63:0] fbdata; + wire[63:0] fbdata; + output fbdatavalid; + wire fbdatavalid; + input fbnextscanline; + output[1:0] raygroup01; + wire[1:0] raygroup01; + output raygroupvalid01; + wire raygroupvalid01; + input busy01; + output[1:0] raygroup10; + wire[1:0] raygroup10; + + output raygroupvalid10; + wire raygroupvalid10; + input busy10; + input globalreset; + output[31:0] rgData; + wire[31:0] rgData; + output[3:0] rgAddr; + wire[3:0] rgAddr; + output[2:0] rgWE; + wire[2:0] rgWE; + output rgAddrValid; + wire rgAddrValid; + + input rgDone; + input[31:0] rgResultData; + input rgResultReady; + input[1:0] rgResultSource; + + wire[2:0] statepeek2; + wire as01; + wire ack01; + + wire[3:0] addr01; + wire[47:0] dir01; + wire[47:0] dir; + wire[47:0] sramdatal; + wire wantDir; + wire dirReady; + wire dirReadyl; + wire[14:0] address; + wire[30:0] cyclecounter; + + wire nas01; + wire nas10; + wire go; + reg page; + wire[2:0] statepeekct; + // result Signals + wire valid01; + wire valid10; + wire[15:0] id01a; + wire[15:0] id01b; + wire[15:0] id01c; + wire[15:0] id10a; + + wire[15:0] id10b; + wire[15:0] id10c; + wire hit01a; + wire hit01b; + wire hit01c; + wire hit10a; + wire hit10b; + wire hit10c; + wire[7:0] u01a; + wire[7:0] u01b; + wire[7:0] u01c; + wire[7:0] v01a; + + wire[7:0] v01b; + wire[7:0] v01c; + wire[7:0] u10a; + wire[7:0] u10b; + wire[7:0] u10c; + wire[7:0] v10a; + wire[7:0] v10b; + wire[7:0] v10c; + wire wantwriteback; + wire writebackack; + wire[63:0] writebackdata; + wire[17:0] writebackaddr; + + wire[17:0] nextaddr01; + // Shading Signals + wire[63:0] shadedata; + wire[15:0] triID; + wire wantshadedata; + wire shadedataready; + // CfgData Signals + wire[27:0] origx; + wire[27:0] origy; + wire[27:0] origz; + wire[15:0] m11; + wire[15:0] m12; + + wire[15:0] m13; + wire[15:0] m21; + wire[15:0] m22; + wire[15:0] m23; + wire[15:0] m31; + wire[15:0] m32; + wire[15:0] m33; + wire[20:0] bkcolour; + // Texture signals + wire[20:0] texinfo; + wire[3:0] texaddr; + wire[63:0] texel; + + wire[17:0] texeladdr; + wire wanttexel; + wire texelready; + // Frame Buffer Read Signals + wire fbpage; + // debug signals + wire wantcfg; + wire debugglobalreset; + + assign rgwant_CfgData = wantcfg ; + + onlyonecycle onlyeonecycleinst (rgCont[0], go, globalreset, tm3_clk_v0); + + always @(posedge tm3_clk_v0) + begin + if (globalreset == 1'b1) + begin + page <= 1'b1 ; // Reset to 1 such that first flip sets to 0 + end + else + + begin + page <= ~page ; + end + end + assign fbpage = ~page ; + + matmult matmultinst(sramdatal[47:32], sramdatal[31:16], sramdatal[15:0], m11, m12, m13, m21, m22, m23, m31, m32, m33, dir[47:32], dir[31:16], dir[15:0], tm3_clk_v0); + + delay1x3 dir01delay(dirReady, dirReadyl, tm3_clk_v0); + rgconfigmemory ConfigMemoryInst (rgCfgData[31:28], rgCfgData[27:0], rgCfgData_ready, wantcfg, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, tm3_clk_v0); + + rgsramcontroller sramcont (rgwant_addr, rgaddr_ready, rgaddrin, rgwant_data, rgdata_ready, rgdatain, rgwant_read, rgread_ready, rgdataout, dirReady, wantDir, sramdatal, address, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, tm3_clk_v0); + raysend raysendinst (as01, ack01, addr01, dir01, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, tm3_clk_v0, statepeek2); + + raygencont raygencontinst(go, rgCont[15:1], rgStat[31], cyclecounter, nextaddr01, nas01, nas10, page, dirReadyl, wantDir, dir, address, as01, addr01, ack01, dir01, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, tm3_clk_v0, statepeekct); + resultrecieve resultrecieveinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, tm3_clk_v0); + assign debugglobalreset = globalreset | go ; + resultwriter resultwriteinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, nextaddr01, nas01, nas10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, writebackdata, writebackaddr, wantwriteback, writebackack, debugglobalreset, tm3_clk_v0); + assign rgStat[30:0] = cyclecounter ; + endmodule + + +module delay1x3 (datain, dataout, clk); + + input datain; + output dataout; + wire dataout; + input clk; + + reg buff0; + reg buff1; + reg buff2; + + assign dataout = buff2 ; + + always @(posedge clk) + begin +/* PAJ expanded for loop to hard definition the size of `depth */ + buff0 <= datain ; + buff1 <= buff0; + buff2 <= buff1; + end + endmodule + + + + + + + // A debugging circuit that allows a single cycle pulse to be + // generated by through the ports package + module onlyonecycle (trigger, output_xhdl0, globalreset, clk); + + input trigger; + output output_xhdl0; + reg output_xhdl0; + input globalreset; + input clk; + + reg[1:0] state; + reg[1:0] next_state; + reg count; + reg temp_count; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + count <= 0 ; + + end + else + begin + state <= next_state ; + count <= temp_count; + end + end + + always @(state or trigger or count) + begin + case (state) + 0 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + temp_count = 1 - 1 ; + end + 1 : + begin + output_xhdl0 = 1'b1 ; + if (count == 0) + begin + next_state = 2 ; + end + else + + begin + + next_state = 1 ; + end + temp_count = count - 1 ; + end + 2 : + begin + output_xhdl0 = 1'b0 ; + if (trigger == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + + end + end + endcase + end + endmodule + +module matmult (Ax, Ay, Az, m11, m12, m13, m21, m22, m23, m31, m32, m33, Cx, Cy, Cz, clk); + + input[16 - 1:0] Ax; + input[16 - 1:0] Ay; + input[16 - 1:0] Az; + input[16 - 1:0] m11; + input[16 - 1:0] m12; + + input[16 - 1:0] m13; + input[16 - 1:0] m21; + input[16 - 1:0] m22; + input[16 - 1:0] m23; + input[16 - 1:0] m31; + input[16 - 1:0] m32; + input[16 - 1:0] m33; + output[16 - 1:0] Cx; + reg[16 - 1:0] Cx; + output[16 - 1:0] Cy; + reg[16 - 1:0] Cy; + output[16 - 1:0] Cz; + + reg[16 - 1:0] Cz; + input clk; + + reg[16 + 16 - 1:0] am11; + reg[16 + 16 - 1:0] am12; + reg[16 + 16 - 1:0] am13; + reg[16 + 16 - 1:0] am21; + reg[16 + 16 - 1:0] am22; + reg[16 + 16 - 1:0] am23; + reg[16 + 16 - 1:0] am31; + reg[16 + 16 - 1:0] am32; + reg[16 + 16 - 1:0] am33; + + + always @(posedge clk) + begin + am11 <= Ax * m11 ; + am12 <= Ay * m12 ; + am13 <= Az * m13 ; + am21 <= Ax * m21 ; + am22 <= Ay * m22 ; + am23 <= Az * m23 ; + am31 <= Ax * m31 ; + am32 <= Ay * m32 ; + am33 <= Az * m33 ; + + // Cx <= (am11 + am12 + am13) (`widthA+`widthB-2 downto `widthB-1); + // Cy <= (am21 + am22 + am23) (`widthA+`widthB-2 downto `widthB-1); + // Cz <= (am31 + am32 + am33) (`widthA+`widthB-2 downto `widthB-1); + Cx <= (am11[16+16-2:16-1] + am12[16+16-2:16-1] + am13[16+16-2:16-1]) ; + Cy <= (am21[16+16-2:16-1] + am22[16+16-2:16-1] + am23[16+16-2:16-1]); + Cz <= (am31[16+16-2:16-1] + am32[16+16-2:16-1] + am33[16+16-2:16-1]) ; + end + endmodule + + + + +module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, clk); + + + input[3:0] CfgAddr; + input[27:0] CfgData; + input CfgData_Ready; + output want_CfgData; + reg want_CfgData; + output[27:0] origx; + reg[27:0] origx; + output[27:0] origy; + reg[27:0] origy; + output[27:0] origz; + reg[27:0] origz; + output[15:0] m11; + reg[15:0] m11; + output[15:0] m12; + reg[15:0] m12; + output[15:0] m13; + reg[15:0] m13; + output[15:0] m21; + reg[15:0] m21; + output[15:0] m22; + reg[15:0] m22; + output[15:0] m23; + reg[15:0] m23; + output[15:0] m31; + reg[15:0] m31; + output[15:0] m32; + reg[15:0] m32; + output[15:0] m33; + reg[15:0] m33; + output[20:0] bkcolour; + reg[20:0] bkcolour; + output[20:0] texinfo; + + wire[20:0] texinfo; + input globalreset; + input clk; + + reg state; + reg next_state; + wire we; + + reg[27:0] temp_origx; + reg[27:0] temp_origy; + reg[27:0] temp_origz; + reg[15:0] temp_m11; + reg[15:0] temp_m12; + reg[15:0] temp_m13; + reg[15:0] temp_m21; + reg[15:0] temp_m22; + reg[15:0] temp_m23; + reg[15:0] temp_m31; + reg[15:0] temp_m32; + reg[15:0] temp_m33; + reg[20:0] temp_bkcolour; + + // <> Can't find translated component 'spram'. Module name may not match + spram21x4 spraminst(we, texinfo, CfgData[20:0], clk); + assign we = ((CfgData_Ready == 1'b1) & (CfgAddr == 4'b1110)) ? 1'b1 : 1'b0 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + origx <= 0; + origy <= 0; + + origz <= 0; + m11 <= 1; + m12 <= 0; + m13 <= 0; + m21 <= 0; + m22 <= 1; + m23 <= 0; + m31 <= 0; + m32 <= 0; + m33 <= 1; + bkcolour <= 0; + end + else + begin + state <= next_state ; + origx <= temp_origx; + origy <= temp_origy; + origz <= temp_origz; + m11 <= temp_m11; + m12 <= temp_m12; + m13 <= temp_m13; + m21 <= temp_m21; + m22 <= temp_m22; + m23 <= temp_m23; + m31 <= temp_m31; + m32 <= temp_m32; + m33 <= temp_m33; + bkcolour <= bkcolour; + end + end + + always @(state or CfgData_Ready) + begin + case (state) + 0 : + begin + want_CfgData = 1'b1 ; + if (CfgData_Ready == 1'b1) + begin + next_state = 1 ; + end + + else + begin + next_state = 0 ; + end + + if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0001)) + begin + temp_origx = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0010)) + begin + temp_origy = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0011)) + begin + temp_origz = CfgData ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0100)) + begin + temp_m11 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0101)) + begin + temp_m12 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0110)) + begin + temp_m13 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0111)) + begin + temp_m21 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1000)) + begin + temp_m22 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1001)) + begin + temp_m23 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1010)) + begin + temp_m31 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1011)) + begin + temp_m32 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1100)) + begin + temp_m33 = CfgData[15:0] ; + end + else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1101)) + begin + temp_bkcolour = CfgData[20:0] ; + end + end + 1 : + begin + want_CfgData = 1'b0 ; + if (CfgData_Ready == 1'b0) + begin + next_state = 0 ; + end + + else + begin + next_state = 1 ; + end + end + endcase + end + endmodule + + + + module spram21x4 (we, dataout, datain, clk); + + input we; + output[21 - 1:0] dataout; + wire[21 - 1:0] dataout; + input[21 - 1:0] datain; + input clk; + + reg [7:0] addr; + + always @ (posedge clk) + begin + addr[0] <= we; + addr [1] <= addr[0]; + addr [2] <= addr[1]; + addr [3] <= addr[2]; + addr [4] <= addr[3]; + addr [5] <= addr[4]; + addr [6] <= addr[5]; + addr [7] <= addr[6]; + end +//changed to odin 2 ram specifications + +single_port_ram new_ram( + .clk (clk), + .we(we), + .data(datain), + .out(dataout), + .addr(addr) + ); + + + endmodule + + + + + + + + + + + + +module rgsramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, want_read, read_ready, dataout, dirReady, wantDir, sramdatal, addr, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk); + + output want_addr; + reg want_addr; + input addr_ready; + input[17:0] addrin; + output want_data; + reg want_data; + input data_ready; + input[63:0] datain; + input want_read; + output read_ready; + + reg read_ready; + output[63:0] dataout; + wire[63:0] dataout; + output dirReady; + reg dirReady; + input wantDir; + output[47:0] sramdatal; + reg[47:0] sramdatal; + output[14:0] addr; + wire[14:0] addr; + input wantwriteback; + output writebackack; + + reg writebackack; + input[63:0] writebackdata; + input[17:0] writebackaddr; + output[63:0] fbdata; + reg[63:0] fbdata; + input fbnextscanline; + output fbdatavalid; + reg fbdatavalid; + input fbpage; + output[63:0] shadedata; + wire[63:0] shadedata; + input[15:0] triID; + + input wantshadedata; + output shadedataready; + reg shadedataready; + input[17:0] texeladdr; + output[63:0] texel; + wire[63:0] texel; + input wanttexel; + output texelready; + reg texelready; + input[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_in; + output[63:0] tm3_sram_data_out; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + output[18:0] tm3_sram_addr; + reg[18:0] tm3_sram_addr; + output[7:0] tm3_sram_we; + reg[7:0] tm3_sram_we; + output[1:0] tm3_sram_oe; + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + reg[17:0] waddress; + reg[14:0] faddress; + reg[6:0] fcount; + reg fbdatavalidl; + + reg[17:0] temp_waddress; + reg[14:0] temp_faddress; + reg[6:0] temp_fcount; + reg temp_fbdatavalidl; + reg temp_texelready; + reg temp_shadedataready; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + assign dataout = tm3_sram_data_in ; + assign addr = tm3_sram_data_in[62:48] ; + assign shadedata = tm3_sram_data_in ; + assign texel = tm3_sram_data_in ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + + state <= 0 ; + waddress <= 0; + faddress <= 0; + fcount <= 7'b1101011 ; + fbdatavalid <= 1'b0 ; + fbdatavalidl <= 1'b0 ; + shadedataready <= 1'b0 ; + texelready <= 1'b0 ; + sramdatal <= 0; + fbdata <= 0; + end + else + + begin + state <= next_state ; + sramdatal <= tm3_sram_data_in[47:0] ; + fbdata <= tm3_sram_data_in ; + fbdatavalid <= fbdatavalidl ; + +fbdatavalidl <= temp_fbdatavalidl; +texelready <= temp_texelready; +shadedataready <= temp_shadedataready; +fcount <= temp_fcount; +faddress <= temp_faddress; +waddress <= temp_waddress; + + end + end + + always @(state or addr_ready or data_ready or waddress or datain or wantDir or + want_read or wantwriteback or writebackdata or writebackaddr or + fcount or fbpage or faddress or fbnextscanline or triID or wantshadedata or + wanttexel or texeladdr) + + begin + case (state) + + 0 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + if (addr_ready == 1'b1) + begin + next_state = 1 ; + end + else if (want_read == 1'b1) + begin + next_state = 2 ; + end + else if (data_ready == 1'b1) + begin + + next_state = 3 ; + end + else if (wantDir == 1'b1) + begin + next_state = 5 ; + end + else if (wantwriteback == 1'b1) + begin + next_state = 6 ; + end + else if (wantshadedata == 1'b1) + begin + + next_state = 9 ; + end + else if (wanttexel == 1'b1) + begin + next_state = 10 ; + end + else if (fcount != 0) + begin + next_state = 7 ; + end + else if (fbnextscanline == 1'b1) + begin + + next_state = 8 ; + end + else + begin + next_state = 0 ; + end + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (addr_ready == 1'b1) + + begin + temp_waddress = addrin ; + end + + end + 1 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + want_addr = 1'b0 ; + if (addr_ready == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 1 ; + end + end + 2 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + + read_ready = 1'b0 ; + if (want_read == 1'b0) + begin + next_state = 0 ; + end + else + begin + next_state = 2 ; + end + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (want_read == 1'b0) + begin + + temp_waddress = waddress + 1 ; + end + + end + 3 : + begin + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_data_xhdl0 = datain ; + tm3_sram_we = 8'b00000000 ; + + + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + want_data = 1'b0 ; + next_state = 4 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_waddress = waddress + 1 ; + + end + 4 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + if (data_ready == 1'b0) + begin + + next_state = 0 ; + end + else + begin + next_state = 4 ; + end + want_data = 1'b0 ; + end + + 5 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + writebackack = 1'b0 ; + + dirReady = 1'b1 ; + if (wantDir == 1'b0) + begin + next_state = 0 ; + + end + else + begin + next_state = 5 ; + end + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + if (wantDir == 1'b0) + begin + temp_waddress = waddress + 1 ; + end + + end + 6 : + begin + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + + tm3_sram_data_xhdl0 = writebackdata ; + tm3_sram_we = 8'b00000000 ; + tm3_sram_oe = 2'b11 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_addr = {1'b0, writebackaddr} ; + writebackack = 1'b1 ; + next_state = 0 ; + end + + 7 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b011, fbpage, faddress} ; + if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1)) + begin + next_state = 0 ; + + end + else + begin + next_state = 7 ; + end + + + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fbdatavalidl = 1'b1 ; + if (fcount != 0) + begin + temp_faddress = faddress + 1 ; + temp_fcount = fcount - 1 ; + end + + end + 8 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + tm3_sram_addr = {1'b0, waddress} ; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + next_state = 7 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b0 ; + temp_fcount = 7'b1101011 ; + if (faddress == 25680) + begin + temp_faddress = 0; + end + end + 9 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {3'b010, triID} ; + next_state = 0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_texelready = 1'b0 ; + temp_shadedataready = 1'b1 ; + end + + 10 : + begin + tm3_sram_we = 8'b11111111 ; + tm3_sram_oe = 2'b01 ; + tm3_sram_adsp = 1'b0 ; + tm3_sram_data_xhdl0 = 0; + want_addr = 1'b1 ; + want_data = 1'b1 ; + read_ready = 1'b1 ; + dirReady = 1'b0 ; + writebackack = 1'b0 ; + tm3_sram_addr = {1'b0, texeladdr} ; + next_state = 0 ; + + temp_fbdatavalidl = 1'b0 ; + temp_shadedataready = 1'b0 ; + temp_texelready = 1'b1 ; + end + endcase + end + endmodule + + + + + + + + + + + + + module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek); + + input as; + output ack; + reg ack; + input[3:0] addr; + input[47:0] dir; + input[27:0] origx; + input[27:0] origy; + input[27:0] origz; + output[31:0] rgData; + reg[31:0] rgData; + + output[3:0] rgAddr; + reg[3:0] rgAddr; + output[2:0] rgWE; + reg[2:0] rgWE; + output rgAddrValid; + reg rgAddrValid; + input rgDone; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + + reg[3:0] state; + reg[3:0] next_state; + + + + reg[31:0] temp_rgData; + reg[2:0] temp_rgWE; + reg temp_rgAddrValid; + reg temp_ack; + reg[3:0] temp_rgAddr; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + ack <= 1'b0 ; + rgWE <= 3'b000 ; + rgData <= 0; + rgAddrValid <= 1'b0 ; + rgAddr <= 0; + end + else + begin + state <= next_state ; + +rgData <= temp_rgData; +rgWE <= temp_rgWE; +rgAddrValid <= temp_rgAddrValid; +ack <= temp_ack; +rgAddr <= temp_rgAddr; + + end + end + + always @(state or ack or as or rgDone) + begin + + case (state) + 0 : + begin + if ((as == 1'b1) & (ack == 1'b0)) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b001 ; + + if ((as == 1'b1) & (ack == 1'b0)) + begin + temp_rgData = {4'b0000, origx} ; + temp_rgWE = 3'b001 ; + temp_rgAddrValid = 1'b1 ; + temp_rgAddr = addr ; + end + if (as == 1'b0 & ack == 1'b1) + begin + temp_ack = 1'b0 ; + end + + end + 1 : + begin + if (rgDone == 1'b1) + begin + next_state = 6 ; + end + else + begin + next_state = 1 ; + end + statepeek = 3'b010 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + 2 : + begin + if (rgDone == 1'b1) + begin + next_state = 7 ; + end + else + begin + next_state = 2 ; + end + statepeek = 3'b011 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + 3 : + begin + if (rgDone == 1'b1) + begin + next_state = 8 ; + end + else + begin + next_state = 3 ; + end + statepeek = 3'b100 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + 4 : + begin + if (rgDone == 1'b1) + begin + next_state = 9 ; + end + else + begin + next_state = 4 ; + end + statepeek = 3'b101 ; + + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + end + + 5 : + begin + if (rgDone == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 5 ; + end + statepeek = 3'b110 ; + + temp_ack = 1'b1 ; + if (rgDone == 1'b1) + begin + temp_rgAddrValid = 1'b0 ; + end + + end + + 6 : + begin + next_state = 2 ; + + temp_rgData = {4'b0000, origy} ; + temp_rgWE = 3'b010 ; + temp_rgAddrValid = 1'b1 ; + + end + 7 : + begin + next_state = 3 ; + + temp_rgData = {4'b0000, origz} ; + temp_rgWE = 3'b011 ; + temp_rgAddrValid = 1'b1 ; + end + 8 : + begin + next_state = 4 ; + + temp_rgData = {dir[31:16], dir[47:32]} ; + temp_rgWE = 3'b100 ; + temp_rgAddrValid = 1'b1 ; + end + 9 : + begin + next_state = 5 ; + + temp_rgData = {16'b0000000000000000, dir[15:0]} ; + temp_rgWE = 3'b101 ; + temp_rgAddrValid = 1'b1 ; + end + endcase + end + endmodule + + + + + + + + module raygencont (go, initcount, busyout, cycles, nextaddr, nas0, nas1, page, dirReady, wantDir, dirIn, addrIn, as, addr, ack, dir, raygroup0, raygroupvalid0, busy0, raygroup1, raygroupvalid1, busy1, globalreset, clk, statepeek); + + input go; + input[14:0] initcount; + output busyout; + wire busyout; + reg temp_busyout; + output[30:0] cycles; + reg[30:0] cycles; + output[17:0] nextaddr; + wire[17:0] nextaddr; + output nas0; + + wire nas0; + reg temp_nas0; + output nas1; + wire nas1; + reg temp_nas1; + input page; + input dirReady; + output wantDir; + reg wantDir; + input[47:0] dirIn; + input[14:0] addrIn; + output as; + reg as; + output[3:0] addr; + + reg[3:0] addr; + input ack; + output[47:0] dir; + reg[47:0] dir; + output[1:0] raygroup0; + wire[1:0] raygroup0; + output raygroupvalid0; + reg raygroupvalid0; + input busy0; + output[1:0] raygroup1; + wire[1:0] raygroup1; + output raygroupvalid1; + + reg raygroupvalid1; + input busy1; + input globalreset; + input clk; + output[2:0] statepeek; + reg[2:0] statepeek; + + + reg[2:0] state; + reg[2:0] next_state; + reg[14:0] count; + reg first; + reg[17:0] destaddr; + wire[1:0] busy; + reg[1:0] loaded; + reg[1:0] groupID; + reg active; + + reg[47:0] temp_dir; + reg[30:0] temp_cycles; + reg[1:0] temp_addr; + reg[1:0] temp_loaded; + reg[1:0] temp_groupID; + reg[14:0] temp_count; + reg temp_active; + reg temp_raygroupvalid1; + reg temp_raygroupvalid0; + + assign busy = {busy1, busy0} ; + + always @(posedge clk) + begin + + if (globalreset == 1'b1) + + begin + state <= 0 ; + cycles <= 0; + dir <= 0; + addr[1:0] <= 2'b00 ; + groupID <= 2'b00 ; + count <= 0; + first <= 1'b0 ; + destaddr <= 0; + raygroupvalid0 <= 1'b0 ; + raygroupvalid1 <= 1'b0 ; + loaded <= 2'b00 ; + + active <= 1'b0 ; + end + else + begin + addr[3:2] <= (active == 1'b0) ? {1'b0, groupID[0]} : {1'b1, groupID[1]} ; + addr[1:0] <= temp_addr[1:0]; + state <= next_state ; + + dir <= temp_dir; + cycles <= temp_cycles; + loaded <= temp_loaded; + groupID <= temp_groupID; + count <= temp_count; + active <= temp_active; + raygroupvalid0 <= temp_raygroupvalid0; + raygroupvalid1 <= temp_raygroupvalid1; + + end + end + + assign raygroup0 = {1'b0, groupID[0]} ; + assign raygroup1 = {1'b1, groupID[1]} ; + assign nextaddr = {2'b11, page, addrIn} ; + assign busyout = temp_busyout; + assign nas0 = temp_nas0; + assign nas1 = temp_nas1; + + always @(state or go or ack or busy or dirReady or addr or count or loaded) + begin + case (state) + 0 : + begin + as = 1'b0 ; + wantDir = 1'b0 ; + if (go == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b001 ; + temp_busyout = 1'b0; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + + if (go == 1'b1) + begin + temp_cycles = 0; + end + temp_addr[1:0] = 2'b00 ; + temp_loaded = 2'b00 ; + temp_groupID = 2'b00 ; + temp_count = initcount ; + temp_active = 1'b0 ; + + end + 1 : + begin + as = dirReady ; + wantDir = 1'b1 ; + if (dirReady == 1'b1) + begin + next_state = 2 ; + end + else + begin + next_state = 1 ; + end + statepeek = 3'b010 ; + temp_busyout = 1'b1; + if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0) + begin + temp_nas0 = 1'b1; + temp_nas1 = 1'b1; + end + + temp_dir = dirIn ; + if (dirReady == 1'b1 & addr[1:0] == 2'b10) + begin + if (active == 1'b0) + begin + temp_loaded[0] = 1'b1 ; + end + else + begin + temp_loaded[1] = 1'b1 ; + end + end + temp_cycles = cycles + 1 ; + + + end + 2 : + begin + wantDir = 1'b0 ; + as = 1'b1 ; + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + next_state = 1 ; + end + else if (ack == 1'b1) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (loaded != 2'b11) + begin + + next_state = 1 ; + end + else + begin + next_state = 2 ; + end + end + else + begin + next_state = 2 ; + end + statepeek = 3'b011 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((ack == 1'b1) & (addr[1:0] != 2'b10)) + begin + temp_addr[1:0] = addr[1:0] + 2'b01 ; + end + else if ((ack == 1'b1) & addr[1:0] == 2'b10) + begin + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + + temp_raygroupvalid1 = 1'b1 ; + end + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + temp_addr[1:0] = 2'b00 ; + end + end + + temp_cycles = cycles + 1 ; + end + 4 : + begin + if ((busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + next_state = 3 ; + end + else if (count > 0) + begin + + next_state = 1 ; + end + else + begin + next_state = 0 ; + end + statepeek = 3'b101 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[1]) == 1'b1) + begin + temp_groupID[1] = ~groupID[1] ; + temp_raygroupvalid1 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0) + begin + temp_raygroupvalid0 = 1'b1 ; + end + + else if ((loaded[0]) == 1'b0) + begin + temp_active = 1'b0 ; + end + else + begin + temp_active = 1'b1 ; + end + end + temp_loaded[1] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + temp_cycles = cycles + 1 ; + end + 3 : + begin + if ((busy[0]) == 1'b0) + begin + next_state = 3 ; + + end + else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + next_state = 4 ; + end + else if (count > 0) + begin + next_state = 1 ; + end + else + begin + next_state = 0 ; + + end + statepeek = 3'b100 ; + temp_busyout = 1'b1; + temp_nas0 = 1'b0; + temp_nas1 = 1'b0; + + if ((busy[0]) == 1'b1) + begin + temp_groupID[0] = ~groupID[0] ; + temp_raygroupvalid0 = 1'b0 ; + temp_count = count - 1 ; + if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0) + begin + temp_raygroupvalid1 = 1'b1 ; + + end + else if ((loaded[1]) == 1'b0) + begin + temp_active = 1'b1 ; + end + else + begin + temp_active = 1'b0 ; + end + end + temp_loaded[0] = 1'b0 ; + temp_addr[1:0] = 2'b00 ; + + + temp_cycles = cycles + 1 ; + end + endcase + end + endmodule + + + + + + + + + module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk); + + output valid01; + reg valid01; + output valid10; + reg valid10; + output[15:0] id01a; + reg[15:0] id01a; + output[15:0] id01b; + reg[15:0] id01b; + output[15:0] id01c; + reg[15:0] id01c; + + output[15:0] id10a; + reg[15:0] id10a; + output[15:0] id10b; + reg[15:0] id10b; + output[15:0] id10c; + reg[15:0] id10c; + output hit01a; + reg hit01a; + output hit01b; + reg hit01b; + output hit01c; + reg hit01c; + + output hit10a; + reg hit10a; + output hit10b; + reg hit10b; + output hit10c; + reg hit10c; + output[7:0] u01a; + reg[7:0] u01a; + output[7:0] u01b; + reg[7:0] u01b; + output[7:0] u01c; + reg[7:0] u01c; + + output[7:0] v01a; + reg[7:0] v01a; + output[7:0] v01b; + reg[7:0] v01b; + output[7:0] v01c; + reg[7:0] v01c; + output[7:0] u10a; + reg[7:0] u10a; + output[7:0] u10b; + reg[7:0] u10b; + output[7:0] u10c; + reg[7:0] u10c; + + output[7:0] v10a; + reg[7:0] v10a; + output[7:0] v10b; + reg[7:0] v10b; + output[7:0] v10c; + reg[7:0] v10c; + input[31:0] rgResultData; + input rgResultReady; + input[1:0] rgResultSource; + input globalreset; + input clk; + + reg temp_valid01; + reg temp_valid10; + reg[15:0] temp_id01a; + reg[15:0] temp_id01b; + reg[15:0] temp_id01c; + reg[15:0] temp_id10a; + reg[15:0] temp_id10b; + reg[15:0] temp_id10c; + reg temp_hit01a; + reg temp_hit01b; + reg temp_hit01c; + reg temp_hit10a; + reg temp_hit10b; + reg temp_hit10c; + reg[7:0] temp_u01a; + reg[7:0] temp_u01b; + reg[7:0] temp_u01c; + reg[7:0] temp_v01a; + reg[7:0] temp_v01b; + reg[7:0] temp_v01c; + reg[7:0] temp_u10a; + reg[7:0] temp_u10b; + reg[7:0] temp_u10c; + reg[7:0] temp_v10a; + reg[7:0] temp_v10b; + reg[7:0] temp_v10c; + + + reg[2:0] state; + reg[2:0] next_state; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + valid01 <= 1'b0 ; + valid10 <= 1'b0 ; + hit01a <= 1'b0 ; + hit01b <= 1'b0 ; + hit01c <= 1'b0 ; + hit10a <= 1'b0 ; + hit10b <= 1'b0 ; + hit10c <= 1'b0 ; + id01a <= 0; + + id01b <= 0; + id01c <= 0; + id10a <= 0; + id10b <= 0; + id10c <= 0; + u01a <= 0; + u01b <= 0; + u01c <= 0; + v01a <= 0; + v01b <= 0; + v01c <= 0; + u10a <= 0; + + u10b <= 0; + u10c <= 0; + v10a <= 0; + v10b <= 0; + v10c <= 0; + end + else + begin + state <= next_state ; + +valid01 <= temp_valid01; +valid10 <= temp_valid10; +id01a <= temp_id01a; +id01b <= temp_id01b; +id01c <= temp_id01c; +hit01a <= temp_hit01a; +hit01b <= temp_hit01b; +hit01c <= temp_hit01c; +u01a <= temp_u01a; +u01b <= temp_u01b; +u01c <= temp_u01c; +u10a <= temp_u10a; +u10b <= temp_u10b; +u10c <= temp_u10c; +v01a <= temp_v01a; +v01b <= temp_v01b; +v01c <= temp_v01c; +v10a <= temp_v10a; +v10b <= temp_v10b; +v10c <= temp_v10c; +hit10a <= temp_hit10a; +hit10b <= temp_hit10b; +hit10c <= temp_hit10c; + end + end + + + always @(state or rgResultReady or rgResultSource) + begin + case (state) + 0 : + begin + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + next_state = 1 ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + + next_state = 4 ; + end + else + begin + next_state = 0 ; + end + + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + if (rgResultReady == 1'b1 & rgResultSource == 2'b01) + begin + temp_id01a = rgResultData[31:16] ; + temp_id01b = rgResultData[15:0] ; + end + else if (rgResultReady == 1'b1 & rgResultSource == 2'b10) + begin + temp_id10a = rgResultData[31:16] ; + temp_id10b = rgResultData[15:0] ; + end + + end + + 1 : + begin + next_state = 2 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_id01c = rgResultData[15:0] ; + temp_hit01a = rgResultData[18] ; + temp_hit01b = rgResultData[17] ; + temp_hit01c = rgResultData[16] ; + + end + 2 : + + begin + next_state = 3 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_u01a = rgResultData[23:16] ; + temp_u01b = rgResultData[15:8] ; + temp_u01c = rgResultData[7:0] ; + + end + 3 : + begin + next_state = 0 ; + + temp_valid10 = 1'b0 ; + temp_v01a = rgResultData[23:16] ; + temp_v01b = rgResultData[15:8] ; + temp_v01c = rgResultData[7:0] ; + temp_valid01 = 1'b1 ; + + end + 4 : + begin + next_state = 5 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_id10c = rgResultData[15:0] ; + + temp_hit10a = rgResultData[18] ; + temp_hit10b = rgResultData[17] ; + temp_hit10c = rgResultData[16] ; + + end + 5 : + + begin + next_state = 6 ; + + temp_valid01 = 1'b0 ; + temp_valid10 = 1'b0 ; + temp_u10a = rgResultData[23:16] ; + temp_u10b = rgResultData[15:8] ; + temp_u10c = rgResultData[7:0] ; + + end + 6 : + begin + next_state = 0 ; + + temp_valid01 = 1'b0 ; + temp_v10a = rgResultData[23:16] ; + temp_v10b = rgResultData[15:8] ; + temp_v10c = rgResultData[7:0] ; + temp_valid10 = 1'b1 ; + + end + endcase + end + endmodule + + + + + + + + + + + + + + + + module resultwriter (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, addr, as01, as10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, dataout, addrout, write, ack, globalreset, clk); + + input valid01; + input valid10; + input[15:0] id01a; + input[15:0] id01b; + input[15:0] id01c; + input[15:0] id10a; + input[15:0] id10b; + input[15:0] id10c; + + input hit01a; + input hit01b; + input hit01c; + input hit10a; + input hit10b; + input hit10c; + input[7:0] u01a; + input[7:0] u01b; + input[7:0] u01c; + input[7:0] v01a; + input[7:0] v01b; + input[7:0] v01c; + + input[7:0] u10a; + input[7:0] u10b; + input[7:0] u10c; + input[7:0] v10a; + input[7:0] v10b; + input[7:0] v10c; + input[17:0] addr; + input as01; + input as10; + input[20:0] bkcolour; + input[63:0] shadedata; + output[15:0] triID; + + reg[15:0] triID; + output wantshadedata; + reg wantshadedata; + input shadedataready; + input[20:0] texinfo; + output[3:0] texaddr; + wire[3:0] texaddr; + output[17:0] texeladdr; + wire[17:0] texeladdr; + input[63:0] texel; + output wanttexel; + reg wanttexel; + + input texelready; + output[63:0] dataout; + // PAJ see lower note wire[63:0] dataout; + reg[63:0] dataout; + output[17:0] addrout; + wire[17:0] addrout; + output write; + wire write; + reg temp_write; + input ack; + input globalreset; + input clk; + + reg[3:0] state; + reg[3:0] next_state; + reg pending01; + reg pending10; + reg process01; + wire[17:0] addrout01; + wire[17:0] addrout10; + wire shiften01; + wire shiften10; + reg temp_shiften01; + reg temp_shiften10; + reg[20:0] shadedataa; + reg[20:0] shadedatab; + reg[20:0] shadedatac; + wire hita; + wire hitb; + wire hitc; + + reg[2:0] selectuv; + wire[6:0] blr; + wire[6:0] blg; + wire[6:0] blb; + reg texmap; + reg lmenable; + wire[1:0] texelselect; + wire[6:0] texelr; + wire[6:0] texelg; + wire[6:0] texelb; + reg[20:0] texinfol; + + reg temp_pending01; + reg temp_pending10; + reg temp_process01; + reg temp_texmap; + reg[20:0] temp_texinfol; + reg[20:0] temp_shadedataa; + reg[20:0] temp_shadedatab; + reg[20:0] temp_shadedatac; + + col16to21 col16to21inst (texel, texelselect, texelr, texelg, texelb); + linearmap linearmapinst (blb, blg, texinfol[17:0], texeladdr, texelselect, texinfol[20:18], lmenable, clk); + bilinearintrp bilinearimp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, shadedata[41:35], shadedata[62:56], shadedata[20:14], shadedata[34:28], shadedata[55:49], shadedata[13:7], shadedata[27:21], shadedata[48:42], shadedata[6:0], blr, blg, blb, clk); + fifo3 fifo3insta (addr, as01, addrout01, shiften01, globalreset, clk); + fifo3 fifo3instb (addr, as10, addrout10, shiften10, globalreset, clk); + assign hita = (hit01a & process01) | (hit10a & ~process01) ; + assign hitb = (hit01b & process01) | (hit10b & ~process01) ; + assign hitc = (hit01c & process01) | (hit10c & ~process01) ; + assign texaddr = shadedata[59:56] ; + assign shiften01 = temp_shiften01; + assign shiften10 = temp_shiften10; + assign write = temp_write; + + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + state <= 0 ; + pending01 <= 1'b0 ; + pending10 <= 1'b0 ; + shadedataa <= 0; + shadedatab <= 0; + shadedatac <= 0; + process01 <= 1'b0 ; + texmap <= 1'b0 ; + + texinfol <= 0; + end + else + begin + state <= next_state ; + +process01 <= temp_process01; +pending01 <= temp_pending01; +pending10 <= temp_pending10; +texmap <= temp_texmap; +texinfol <= temp_texinfol; +shadedataa <= temp_shadedataa; +shadedatab <= temp_shadedatab; +shadedatac <= temp_shadedatac; + + dataout <= {1'b0, + shadedataa[20], + shadedataa[19], + shadedataa[18], + shadedataa[17], + shadedataa[16], + shadedataa[15], + shadedataa[14], + shadedataa[13], + shadedataa[12], + shadedataa[11], + shadedataa[10], + shadedataa[9], + shadedataa[8], + shadedataa[7], + shadedataa[6], + shadedataa[5], + shadedataa[4], + shadedataa[3], + shadedataa[2], + shadedataa[1], + shadedataa[0], + shadedatab[20], + shadedatab[19], + shadedatab[18], + shadedatab[17], + shadedatab[16], + shadedatab[15], + shadedatab[14], + shadedatab[13], + shadedatab[12], + shadedatab[11], + shadedatab[10], + shadedatab[9], + shadedatab[8], + shadedatab[7], + shadedatab[6], + shadedatab[5], + shadedatab[4], + shadedatab[3], + shadedatab[2], + shadedatab[1], + shadedatab[0], + shadedatac[20], + shadedatac[19], + shadedatac[18], + shadedatac[17], + shadedatac[16], + shadedatac[15], + shadedatac[14], + shadedatac[13], + shadedatac[12], + shadedatac[11], + shadedatac[10], + shadedatac[9], + shadedatac[8], + shadedatac[7], + shadedatac[6], + shadedatac[5], + shadedatac[4], + shadedatac[3], + shadedatac[2], + shadedatac[1], + shadedatac[0]} ; + end +// end +// PAJ used to be assign, but weird error, so added as register assign dataout = {1'b0, + end + assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ; + + always @(state or process01 or pending10 or ack or shadedataready or id01a or + id01b or id01c or id10a or id10b or id10c or selectuv or hita or + hitb or hitc or shadedata or pending01 or texmap or texelready) + begin + case (state) + 0 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + if (pending01 == 1'b1 | pending10 == 1'b1) + begin + next_state = 2 ; + end + else + + begin + next_state = 0 ; + end + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_process01 = pending01 ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 2 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + if (process01 == 1'b1) + begin + triID = id01a ; + + end + else + begin + triID = id10a ; + end + if (shadedataready == 1'b1) + begin + if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 3 ; + end + else + + begin + next_state = 4 ; + end + end + else + begin + next_state = 2 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hita == 1'b1) + begin + temp_shadedataa = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedataa = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 3 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + + selectuv[1:0] = 2'b00 ; + next_state = 8 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + + end + 8 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b00 ; + lmenable = 1'b1 ; + if (texmap == 1'b1) + begin + + next_state = 11 ; + end + else + begin + next_state = 4 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedataa[6:0] = blb ; + temp_shadedataa[13:7] = blg ; + temp_shadedataa[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 11 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 4 ; + end + else + begin + next_state = 11 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedataa[6:0] = texelb ; + temp_shadedataa[13:7] = texelg ; + temp_shadedataa[20:14] = texelr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 12 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 5 ; + end + else + begin + next_state = 12 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedatab[6:0] = texelb ; + temp_shadedatab[13:7] = texelg ; + temp_shadedatab[20:14] = texelr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 13 : + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + + wanttexel = 1'b1 ; + if (texelready == 1'b1) + begin + next_state = 1 ; + end + else + begin + next_state = 13 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedatac[6:0] = texelb ; + temp_shadedatac[13:7] = texelg ; + temp_shadedatac[20:14] = texelr ; + + end + 6 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + next_state = 9 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 9 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + lmenable = 1'b1 ; + if (texmap == 1'b1) + begin + next_state = 12 ; + + end + else + begin + next_state = 5 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + temp_shadedatab[6:0] = blb ; + temp_shadedatab[13:7] = blg ; + temp_shadedatab[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 7 : + begin + wantshadedata = 1'b0 ; + triID = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + next_state = 10 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_texinfol = texinfo ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + + 10 : + begin + wantshadedata = 1'b0 ; + triID = 0; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (texmap == 1'b1) + begin + next_state = 13 ; + end + else + begin + next_state = 1 ; + end + + lmenable = 1'b1 ; + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + temp_shadedatac[6:0] = blb ; + temp_shadedatac[13:7] = blg ; + temp_shadedatac[20:14] = blr ; + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 4 : + begin + wantshadedata = 1'b0 ; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b01 ; + if (process01 == 1'b1) + begin + triID = id01b ; + end + else + begin + + triID = id10b ; + end + if (shadedataready == 1'b1) + begin + if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 6 ; + end + else + begin + next_state = 5 ; + end + + end + else + begin + next_state = 4 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hitb == 1'b1) + begin + temp_shadedatab = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatab = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 5 : + begin + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + wantshadedata = 1'b1 ; + selectuv[2] = ~process01 ; + selectuv[1:0] = 2'b10 ; + if (process01 == 1'b1) + + begin + triID = id01c ; + end + else + begin + triID = id10c ; + end + if (shadedataready == 1'b1) + begin + if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01)) + begin + next_state = 7 ; + + end + else + begin + next_state = 1 ; + end + end + else + begin + next_state = 5 ; + end + + if (valid01 == 1'b1) + begin + temp_pending01 = 1'b1 ; + end + if (valid10 == 1'b1) + begin + temp_pending10 = 1'b1 ; + end + + if (hitc == 1'b1) + begin + temp_shadedatac = shadedata[20:0] ; + temp_texmap = (~shadedata[63]) & shadedata[62] ; + end + else + begin + temp_shadedatac = bkcolour ; + end + + temp_shiften01 = 1'b0; + temp_shiften10 = 1'b0; + temp_write = 1'b0; + end + 1 : + + begin + wantshadedata = 1'b0 ; + triID = 0; + selectuv = 0; + lmenable = 1'b0 ; + wanttexel = 1'b0 ; + if (ack == 1'b1) + begin + next_state = 0 ; + end + else + begin + next_state = 1 ; + end + + if (ack == 1'b1 & process01 == 1'b1) + begin + temp_pending01 = 1'b0 ; + end + + else if (ack == 1'b1 & process01 == 1'b0) + begin + temp_pending10 = 1'b0 ; + end + + if (process01 == 1'b1 & ack == 1'b1) + begin + temp_shiften01 = 1'b1; + temp_shiften10 = 1'b1; + end + temp_write = 1'b1; + end + endcase + end + endmodule + ////////////////////////////////////////////////////////////////////////////////////////////// + // + // Verilog file generated by X-HDL - Revision 3.2.38 Jan. 9, 2004 + // Sun Feb 8 14:14:35 2004 + // + // Input file : G:/jamieson/VERILOG_BENCHMARKS/RAYTRACE/col16to21.vhd + // Design name : col16to21 + // Author : + // Company : + // + // Description : + // + // + ////////////////////////////////////////////////////////////////////////////////////////////// + // + module col16to21 (dataline, texelselect, r, g, b); + + input[63:0] dataline; + input[1:0] texelselect; + output[6:0] r; + wire[6:0] r; + output[6:0] g; + wire[6:0] g; + output[6:0] b; + wire[6:0] b; + + reg[15:0] col16; + + always @(dataline or texelselect) + begin + case (texelselect) + 2'b00 : + begin + col16 = dataline[15:0] ; + end + 2'b01 : + begin + col16 = dataline[31:16] ; + end + 2'b10 : + begin + col16 = dataline[47:32] ; + end + 2'b11 : + begin + col16 = dataline[63:48] ; + end + endcase + end + assign r = {col16[15:10], 1'b0} ; + assign g = {col16[9:5], 2'b00} ; + assign b = {col16[4:0], 2'b00} ; + endmodule + module linearmap (u, v, start, addr, texelselect, factor, enable, clk); + + input[6:0] u; + input[6:0] v; + input[17:0] start; + output[17:0] addr; + reg[17:0] addr; + output[1:0] texelselect; + wire[1:0] texelselect; + + input[2:0] factor; + input enable; + input clk; + + reg[6:0] ul; + reg[6:0] vl; + + assign texelselect = ul[1:0] ; + + always @(posedge clk) + begin + if (enable == 1'b1) + begin + ul <= u ; + vl <= v ; + end + else + begin + ul <= ul ; + vl <= vl ; + end + case (factor) + 3'b000 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({11'b00000000000, vl}) ; + end + 3'b001 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({10'b0000000000, vl, 1'b0}) ; + + end + 3'b010 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({9'b000000000, vl, 2'b00}) ; + end + 3'b011 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({8'b00000000, vl, 3'b000}) ; + end + 3'b100 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({7'b0000000, vl, 4'b0000}) ; + + end + 3'b101 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({6'b000000, vl, 5'b00000}) ; + end + 3'b110 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({5'b00000, vl, 6'b000000}) ; + end + 3'b111 : + begin + addr <= start + ({13'b0000000000000, ul[6:2]}) + ({4'b0000, vl, 7'b0000000}) ; + + end + endcase + end + endmodule + module bilinearintrp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, ru, rv, rw, gu, gv, gw, bu, bv, bw, r, g, b, clk); + + input[7:0] u01a; + input[7:0] u01b; + input[7:0] u01c; + input[7:0] v01a; + input[7:0] v01b; + input[7:0] v01c; + input[7:0] u10a; + input[7:0] u10b; + input[7:0] u10c; + input[7:0] v10a; + input[7:0] v10b; + input[7:0] v10c; + input[2:0] selectuv; + input[6:0] ru; + input[6:0] rv; + input[6:0] rw; + input[6:0] gu; + input[6:0] gv; + input[6:0] gw; + input[6:0] bu; + input[6:0] bv; + input[6:0] bw; + output[6:0] r; + wire[6:0] r; + output[6:0] g; + wire[6:0] g; + output[6:0] b; + wire[6:0] b; + input clk; + + reg[7:0] u; + reg[7:0] v; + reg[7:0] ul; + reg[7:0] vl; + reg[7:0] wl; + reg[14:0] i1b; + reg[14:0] i2b; + reg[14:0] i3b; + reg[14:0] i1g; + reg[14:0] i2g; + reg[14:0] i3g; + reg[14:0] i1r; + reg[14:0] i2r; + reg[14:0] i3r; + reg[6:0] rul; + reg[6:0] rvl; + reg[6:0] rwl; + reg[6:0] gul; + reg[6:0] gvl; + reg[6:0] gwl; + reg[6:0] bul; + reg[6:0] bvl; + reg[6:0] bwl; + + always @(selectuv or u01a or u01b or u01c or v01a or v01b or v01c or u10a or + u10b or u10c or v10a or v10b or v10c) + begin + case (selectuv) + 3'b000 : + begin + u = u01a ; + v = v01a ; + end + 3'b001 : + begin + u = u01b ; + v = v01b ; + end + 3'b010 : + begin + u = u01c ; + v = v01c ; + end + 3'b100 : + begin + u = u10a ; + v = v10a ; + end + 3'b101 : + begin + u = u10b ; + v = v10b ; + end + 3'b110 : + begin + u = u10c ; + v = v10c ; + end + default : + begin + u = 0; + v = 0; + end + endcase + end + + always @(posedge clk) + begin + wl <= 8'b11111111 - u - v ; + ul <= u ; + vl <= v ; + rul <= ru ; + rvl <= rv ; + rwl <= rw ; + gul <= gu ; + gvl <= gv ; + gwl <= gw ; + bul <= bu ; + bvl <= bv ; + bwl <= bw ; + i1r <= ul * rul ; + i2r <= vl * rvl ; + i3r <= wl * rwl ; + i1g <= ul * gul ; + i2g <= vl * gvl ; + i3g <= wl * gwl ; + i1b <= ul * bul ; + i2b <= vl * bvl ; + i3b <= wl * bwl ; + end + assign r = (i1r + i2r + i3r) ; + assign g = (i1g + i2g + i3g) ; + assign b = (i1b + i2b + i3b) ; + endmodule + + + +module fifo3 (datain, writeen, dataout, shiften, globalreset, clk); + + input[18 - 1:0] datain; + input writeen; + output[18 - 1:0] dataout; + wire[18 - 1:0] dataout; + input shiften; + input globalreset; + input clk; + + reg[18 - 1:0] data0; + reg[18 - 1:0] data1; + reg[18 - 1:0] data2; + + reg[1:0] pos; + + assign dataout = data0 ; + + always @(posedge clk) + begin + if (globalreset == 1'b1) + begin + pos <= 2'b00 ; + data0 <= 0 ; + data1 <= 0 ; + data2 <= 0 ; + end + else + begin + if (writeen == 1'b1 & shiften == 1'b1) + begin + case (pos) + 2'b00 : + begin + data0 <= 0 ; + data1 <= 0 ; + data2 <= 0 ; + end + + 2'b01 : + begin + data0 <= datain ; + data1 <= 0 ; + data2 <= 0 ; + end + 2'b10 : + begin + data0 <= data1 ; + data1 <= datain ; + data2 <= 0 ; + end + + 2'b11 : + begin + data0 <= data1 ; + data1 <= data2 ; + data2 <= datain ; + end + endcase + end + else if (shiften == 1'b1) + begin + data0 <= data1 ; + data1 <= data2 ; + pos <= pos - 1 ; + end + else if (writeen == 1'b1) + begin + case (pos) + 2'b00 : + begin + data0 <= datain ; + end + 2'b01 : + begin + data1 <= datain ; + end + 2'b10 : + begin + data2 <= datain ; + end + endcase + pos <= pos + 1 ; + end + end + end + endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/sha.v b/openfpga_flow/benchmarks/vtr_benchmark/sha.v new file mode 100755 index 000000000..fad9960bd --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/sha.v @@ -0,0 +1,2171 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SHA-160 //// +//// Secure Hash Algorithm (SHA-160) //// +//// //// +//// Author: marsgod //// +//// marsgod@opencores.org //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/sha_core/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002-2004 marsgod //// +//// marsgod@opencores.org //// +//// //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +`define SHA1_H0 32'h67452301 +`define SHA1_H1 32'hefcdab89 +`define SHA1_H2 32'h98badcfe +`define SHA1_H3 32'h10325476 +`define SHA1_H4 32'hc3d2e1f0 + +`define SHA1_K0 32'h5a827999 +`define SHA1_K1 32'h6ed9eba1 +`define SHA1_K2 32'h8f1bbcdc +`define SHA1_K3 32'hca62c1d6 + +module sha1 (clk_i, rst_i, text_i, text_o, cmd_i, cmd_w_i, cmd_o); + + input clk_i; // global clock input + input rst_i; // global reset input , active high + + input [31:0] text_i; // text input 32bit + output [31:0] text_o; // text output 32bit + + input [2:0] cmd_i; // command input + input cmd_w_i;// command input write enable + output [3:0] cmd_o; // command output(status) + + /* + cmd + Busy Round W R + + bit3 bit2 bit1 bit0 + Busy Round W R + + Busy: + 0 idle + 1 busy + + Round: + 0 first round + 1 internal round + + W: + 0 No-op + 1 write data + + R: + 0 No-op + 1 read data + + */ + + + reg [3:0] cmd; + wire [3:0] cmd_o; + + reg [31:0] text_o; + + reg [6:0] round; + wire [6:0] round_plus_1; + + reg [2:0] read_counter; + + reg [31:0] H0,H1,H2,H3,H4; + reg [31:0] W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14; + reg [31:0] Wt,Kt; + reg [31:0] A,B,C,D,E; + + reg busy; + + assign cmd_o = cmd; + always @ (posedge clk_i) + begin + if (rst_i) + cmd <= 4'b0000; + else + if (cmd_w_i) + cmd[2:0] <= cmd_i[2:0]; // busy bit can't write + else + begin + cmd[3] <= busy; // update busy bit + if (~busy) + cmd[1:0] <= 2'b00; // hardware auto clean R/W bits + end + end + + // Hash functions + wire [31:0] SHA1_f1_BCD,SHA1_f2_BCD,SHA1_f3_BCD,SHA1_Wt_1; + wire [31:0] SHA1_ft_BCD; + wire [31:0] next_Wt,next_A,next_C; + wire [159:0] SHA1_result; + + assign SHA1_f1_BCD = (B & C) ^ (~B & D); + assign SHA1_f2_BCD = B ^ C ^ D; + assign SHA1_f3_BCD = (B & C) ^ (C & D) ^ (B & D); + + assign SHA1_ft_BCD = (round < 7'b0100101) ? SHA1_f1_BCD : (round < 7'b101001) ? SHA1_f2_BCD : (round < 7'b1111101) ? SHA1_f3_BCD : SHA1_f2_BCD; + + // Odin II doesn't support binary operations inside concatenations presently. + //assign SHA1_Wt_1 = {W13 ^ W8 ^ W2 ^ W0}; + assign SHA1_Wt_1 = W13 ^ W8 ^ W2 ^ W0; + + assign next_Wt = {SHA1_Wt_1[30:0],SHA1_Wt_1[31]}; // NSA fix added + assign next_A = {A[26:0],A[31:27]} + SHA1_ft_BCD + E + Kt + Wt; + assign next_C = {B[1:0],B[31:2]}; + + assign SHA1_result = {A,B,C,D,E}; + + assign round_plus_1 = round + 1; + + //------------------------------------------------------------------ + // SHA round + //------------------------------------------------------------------ + always @(posedge clk_i) + begin + if (rst_i) + begin + round <= 7'b0000000; + busy <= 1'b0; + + W0 <= 32'b00000000000000000000000000000000; + W1 <= 32'b00000000000000000000000000000000; + W2 <= 32'b00000000000000000000000000000000; + W3 <= 32'b00000000000000000000000000000000; + W4 <= 32'b00000000000000000000000000000000; + W5 <= 32'b00000000000000000000000000000000; + W6 <= 32'b00000000000000000000000000000000; + W7 <= 32'b00000000000000000000000000000000; + W8 <= 32'b00000000000000000000000000000000; + W9 <= 32'b00000000000000000000000000000000; + W10 <= 32'b00000000000000000000000000000000; + W11 <= 32'b00000000000000000000000000000000; + W12 <= 32'b00000000000000000000000000000000; + W13 <= 32'b00000000000000000000000000000000; + W14 <= 32'b00000000000000000000000000000000; + Wt <= 32'b00000000000000000000000000000000; + + A <= 32'b00000000000000000000000000000000; + B <= 32'b00000000000000000000000000000000; + C <= 32'b00000000000000000000000000000000; + D <= 32'b00000000000000000000000000000000; + E <= 32'b00000000000000000000000000000000; + + H0 <= 32'b00000000000000000000000000000000; + H1 <= 32'b00000000000000000000000000000000; + H2 <= 32'b00000000000000000000000000000000; + H3 <= 32'b00000000000000000000000000000000; + H4 <= 32'b00000000000000000000000000000000; + + end + else + begin + case (round) + + 7'b0000000: + begin + if (cmd[1]) + begin + W0 <= text_i; + Wt <= text_i; + busy <= 1'b1; + round <= round_plus_1; + + case (cmd[2]) + 1'b0: // sha-1 first message + begin + A <= `SHA1_H0; + B <= `SHA1_H1; + C <= `SHA1_H2; + D <= `SHA1_H3; + E <= `SHA1_H4; + + H0 <= `SHA1_H0; + H1 <= `SHA1_H1; + H2 <= `SHA1_H2; + H3 <= `SHA1_H3; + H4 <= `SHA1_H4; + end + 1'b1: // sha-1 internal message + begin + H0 <= A; + H1 <= B; + H2 <= C; + H3 <= D; + H4 <= E; + end + endcase + end + else + begin // IDLE + round <= 7'b0000000; + end + end + 7'b0000001: + begin + W1 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000010: + begin + W2 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000011: + begin + W3 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000100: + begin + W4 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000101: + begin + W5 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000110: + begin + W6 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0000111: + begin + W7 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001000: + begin + W8 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001001: + begin + W9 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001010: + begin + W10 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001011: + begin + W11 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001100: + begin + W12 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001101: + begin + W13 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001110: + begin + W14 <= text_i; + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0001111: + begin + Wt <= text_i; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0010111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0011111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0100111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0101111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0110111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b0111111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1000111:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001000:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001001:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001010:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001011:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001100:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001101:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001110:begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1001111: + begin + W0 <= W1; + W1 <= W2; + W2 <= W3; + W3 <= W4; + W4 <= W5; + W5 <= W6; + W6 <= W7; + W7 <= W8; + W8 <= W9; + W9 <= W10; + W10 <= W11; + W11 <= W12; + W12 <= W13; + W13 <= W14; + W14 <= Wt; + Wt <= next_Wt; + + E <= D; + D <= C; + C <= next_C; + B <= A; + A <= next_A; + + round <= round_plus_1; + end + 7'b1010000: + begin + A <= next_A + H0; + B <= A + H1; + C <= next_C + H2; + D <= C + H3; + E <= D + H4; + round <= 7'b0000000; + busy <= 1'b0; + end + default: + begin + round <= 7'b0000000; + busy <= 1'b0; + end + endcase + end + end + + + //------------------------------------------------------------------ + // Kt generator + //------------------------------------------------------------------ + always @ (posedge clk_i) + begin + if (rst_i) + begin + Kt <= 32'b00000000000000000000000000000000; + end + else + begin + if (round < 7'b0100000) + Kt <= `SHA1_K0; + else + if (round < 7'b1010000) + Kt <= `SHA1_K1; + else + if (round < 7'b1111100) + Kt <= `SHA1_K2; + else + Kt <= `SHA1_K3; + end + end + + //------------------------------------------------------------------ + // read result + //------------------------------------------------------------------ + always @ (posedge clk_i) + begin + if (rst_i) + begin + text_o <= 32'b00000000000000000000000000000000; + read_counter <= 3'b000; + end + else + begin + if (cmd[0]) + begin + read_counter <= 3'b100; // sha-1 160/32=5 + end + else + begin + if (~busy) + begin + case (read_counter) + 3'b100: text_o <= SHA1_result[5*32-1:4*32]; + 3'b011: text_o <= SHA1_result[4*32-1:3*32]; + 3'b010: text_o <= SHA1_result[3*32-1:2*32]; + 3'b001: text_o <= SHA1_result[2*32-1:1*32]; + 3'b000: text_o <= SHA1_result[1*32-1:0*32]; + default:text_o <= 3'b000; + endcase + if (|read_counter) + read_counter <= read_counter - 7'b0000001; + end + else + begin + text_o <= 32'b00000000000000000000000000000000; + end + end + end + end + +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/spree.v b/openfpga_flow/benchmarks/vtr_benchmark/spree.v new file mode 100755 index 000000000..4497cd7aa --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/spree.v @@ -0,0 +1,3063 @@ +/**************************************************************************** + ISA definition file + + - The MIPS I ISA has a 6 bit opcode in the upper 6 bits. + - The opcode can also specify a "class". There are two classes: + 1. SPECIAL - look in lowest 6 bits to find operation + 2. REGIMM - look in [20:16] to find type of branch + +****************************************************************************/ + +/****** OPCODES - bits 31...26 *******/ + +`define VAL 31 + +`define WIDTH 32 +`define NUMREGS 32 +`define LOG2NUMREGS 5 +`define PC_WIDTH 30 +`define I_DATAWIDTH 32 +`define I_ADDRESSWIDTH 14 +`define I_SIZE 16384 + +`define D_ADDRESSWIDTH 32 +`define DM_DATAWIDTH 32 +`define DM_BYTEENAWIDTH 4 +`define DM_ADDRESSWIDTH 10 +`define DM_SIZE 16384 + + + +`define OP_SPECIAL 6'b000000 +`define OP_REGIMM 6'b000001 +`define OP_J 6'b000010 +`define OP_JAL 6'b000011 +`define OP_BEQ 6'b000100 +`define OP_BNE 6'b000101 +`define OP_BLEZ 6'b000110 +`define OP_BGTZ 6'b000111 + +`define OP_ADDI 6'b001000 +`define OP_ADDIU 6'b001001 +`define OP_SLTI 6'b001010 +`define OP_SLTIU 6'b001011 +`define OP_ANDI 6'b001100 +`define OP_ORI 6'b001101 +`define OP_XORI 6'b001110 +`define OP_LUI 6'b001111 + +`define OP_LB 6'b100000 +`define OP_LH 6'b100001 +`define OP_LWL 6'b100010 +`define OP_LW 6'b100011 +`define OP_LBU 6'b100100 +`define OP_LHU 6'b100101 +`define OP_LWR 6'b100110 + +`define OP_SB 6'b101100 +`define OP_SH 6'b101101 +`define OP_SWL 6'b101010 +`define OP_SW 6'b101111 +`define OP_SWR 6'b101110 + +/****** FUNCTION CLASS - bits 5...0 *******/ +`define FUNC_SLL 6'b000000 +`define FUNC_SRL 6'b000010 +`define FUNC_SRA 6'b000011 +`define FUNC_SLLV 6'b000100 +`define FUNC_SRLV 6'b000110 +`define FUNC_SRAV 6'b000111 + +`define FUNC_JR 6'b001110 +`define FUNC_JALR 6'b001111 + +`define FUNC_MFHI 6'b110100 +`define FUNC_MTHI 6'b110101 +`define FUNC_MFLO 6'b110110 +`define FUNC_MTLO 6'b110111 + +`define FUNC_MULT 6'b111100 +`define FUNC_MULTU 6'b111101 +`define FUNC_DIV 6'b111110 +`define FUNC_DIVU 6'b111111 + +`define FUNC_ADD 6'b100000 +`define FUNC_ADDU 6'b100001 +`define FUNC_SUB 6'b100010 +`define FUNC_SUBU 6'b100011 +`define FUNC_AND 6'b100100 +`define FUNC_OR 6'b100101 +`define FUNC_XOR 6'b100110 +`define FUNC_NOR 6'b100111 + +`define FUNC_SLT 6'b101010 +`define FUNC_SLTU 6'b101011 + +/****** REGIMM Class - bits 20...16 *******/ +`define FUNC_BLTZ 1'b0 +`define FUNC_BGEZ 1'b1 + +`define OP_COP2 6'b010010 +`define COP2_FUNC_CFC2 6'b111000 +`define COP2_FUNC_CTC2 6'b111010 +`define COP2_FUNC_MTC2 6'b111011 + +//`define FUNC_BLTZAL 5'b10000 +//`define FUNC_BGEZAL 5'b10001 + +/****** + * Original REGIMM class, compressed above to save decode logic +`define FUNC_BLTZ 5'b00000 +`define FUNC_BGEZ 5'b00001 +`define FUNC_BLTZAL 5'b10000 +`define FUNC_BGEZAL 5'b10001 +*/ + + +module system ( + clk, + resetn, + boot_iaddr, + boot_idata, + boot_iwe, + boot_daddr, + boot_ddata, + boot_dwe, + nop7_q +); + +/************************* IO Declarations *********************/ +input clk; +input resetn; +input [31:0] boot_iaddr; +input [31:0] boot_idata; +input boot_iwe; +input [31:0] boot_daddr; +input [31:0] boot_ddata; +input boot_dwe; +output [31:0] nop7_q; + + +/*********************** Signal Declarations *******************/ +wire branch_mispred; +wire stall_2nd_delayslot; +wire has_delayslot; +wire haz_zeroer0_q_pipereg5_q; +wire haz_zeroer_q_pipereg5_q; + // Datapath signals declarations +wire addersub_result_slt; +wire [ 31 : 0 ] addersub_result; +wire [ 31 : 0 ] reg_file_b_readdataout; +wire [ 31 : 0 ] reg_file_a_readdataout; +wire [ 31 : 0 ] mul_shift_result; +wire [ 31 : 0 ] mul_lo; +wire [ 31 : 0 ] mul_hi; +wire ctrl_mul_stalled; +wire [ 31 : 0 ] ifetch_pc_out; +wire [ 31 : 0 ] ifetch_instr; +wire [ 5 : 0 ] ifetch_opcode; +wire [ 5 : 0 ] ifetch_func; +wire [4 : 0 ] ifetch_rs; +wire [ 4 : 0 ] ifetch_rt; +wire [ 4 : 0 ] ifetch_rd; +wire [ 25 : 0 ] ifetch_instr_index; +wire [ 15 : 0 ] ifetch_offset; +wire [ 4 : 0 ] ifetch_sa; +wire [ 31 : 0 ] ifetch_next_pc; +wire [ 31 : 0 ] data_mem_d_loadresult; +wire ctrl_data_mem_stalled; +wire [ 31 : 0 ] logic_unit_result; +wire [ 31 : 0 ] pcadder_result; +wire [ 31 : 0 ] signext16_out; +wire [ 31 : 0 ] merge26lo_out; +wire [ 31 : 0 ] hi_reg_q; +wire branchresolve_eqz; +wire branchresolve_gez; +wire branchresolve_gtz; +wire branchresolve_lez; +wire branchresolve_ltz; +wire branchresolve_ne; +wire branchresolve_eq; +wire [ 31 : 0 ] lo_reg_q; +wire [ 31 : 0 ] const8_out; +wire [ 31 : 0 ] const9_out; +wire [ 31 : 0 ] const_out; +wire [ 31 : 0 ] pipereg_q; +wire [ 25 : 0 ] pipereg1_q; +wire [ 4 : 0 ] pipereg2_q; +wire [ 31 : 0 ] pipereg5_q; +wire [ 31 : 0 ] pipereg14_q; +wire [ 31 : 0 ] pipereg3_q; +wire [ 31 : 0 ] nop7_q; +wire [ 31 : 0 ] nop_q; +wire [ 31 : 0 ] nop10_q; +wire [ 31 : 0 ] nop6_q; +wire [ 31 : 0 ] zeroer_q; +wire [ 31 : 0 ] zeroer0_q; +wire [ 31 : 0 ] zeroer4_q; +wire [ 31 : 0 ] fakedelay_q; +wire [ 31 : 0 ] mux3to1_ifetch_load_data_out; +wire [ 31 : 0 ] mux2to1_mul_opA_out; +wire mux6to1_ifetch_load_out; +wire [ 4 : 0 ] mux3to1_mul_sa_out; +wire [ 31 : 0 ] mux2to1_addersub_opA_out; +wire [ 31 : 0 ] mux7to1_nop10_d_out; +wire [ 31 : 0 ] mux2to1_pipereg_d_out; +wire [ 31 : 0 ] mux3to1_nop6_d_out; +wire [ 31 : 0 ] mux3to1_zeroer4_d_out; +wire [ 5 : 0 ] pipereg11_q; +wire [ 31 : 0 ] mux2to1_nop_d_out; +wire pipereg16_q; +wire pipereg15_q; +wire [ 31 : 0 ] mux2to1_nop7_d_out; +wire [ 5 : 0 ] pipereg12_q; +wire [ 4 : 0 ] pipereg13_q; +/***************** Control Signals ***************/ + //Decoded Opcode signal declarations +reg ctrl_mux2to1_pipereg_d_sel; +reg [ 2 : 0 ] ctrl_mux7to1_nop10_d_sel; +reg ctrl_mux2to1_addersub_opA_sel; +reg [ 2 : 0 ] ctrl_mux6to1_ifetch_load_sel; +reg [ 1 : 0 ] ctrl_mux3to1_nop6_d_sel; +reg ctrl_mux2to1_mul_opA_sel; +reg [ 1 : 0 ] ctrl_mux3to1_mul_sa_sel; +reg [ 1 : 0 ] ctrl_mux3to1_ifetch_load_data_sel; +reg [ 1 : 0 ] ctrl_mux3to1_zeroer4_d_sel; +reg ctrl_zeroer4_en; +reg ctrl_zeroer0_en; +reg ctrl_zeroer_en; +reg [ 3 : 0 ] ctrl_data_mem_op; +reg [ 2 : 0 ] ctrl_addersub_op; +reg ctrl_ifetch_op; +reg [ 2 : 0 ] ctrl_mul_op; +reg [ 1 : 0 ] ctrl_logic_unit_op; + //Enable signal declarations +reg ctrl_hi_reg_en; +reg ctrl_lo_reg_en; +reg ctrl_branchresolve_en; +reg ctrl_reg_file_c_we; +reg ctrl_reg_file_b_en; +reg ctrl_reg_file_a_en; +reg ctrl_data_mem_en; +reg ctrl_ifetch_we; +reg ctrl_ifetch_en; +reg ctrl_mul_start; + //Other Signals +wire squash_stage2; +wire stall_out_stage2; +wire squash_stage1; +wire stall_out_stage1; +wire ctrl_pipereg16_squashn; +wire ctrl_pipereg15_squashn; +wire ctrl_pipereg14_squashn; +wire ctrl_pipereg_squashn; +wire ctrl_pipereg5_squashn; +wire ctrl_pipereg2_squashn; +wire ctrl_pipereg3_squashn; +wire ctrl_pipereg1_squashn; +wire ctrl_pipereg11_squashn; +wire ctrl_pipereg12_squashn; +wire ctrl_pipereg13_squashn; +wire ctrl_pipereg16_resetn; +wire ctrl_pipereg15_resetn; +wire ctrl_pipereg14_resetn; +wire ctrl_pipereg_resetn; +wire ctrl_pipereg5_resetn; +wire ctrl_pipereg2_resetn; +wire ctrl_pipereg3_resetn; +wire ctrl_pipereg1_resetn; +wire ctrl_pipereg11_resetn; +wire ctrl_pipereg12_resetn; +wire ctrl_pipereg13_resetn; +wire ctrl_pipereg16_en; +wire ctrl_pipereg15_en; +wire ctrl_pipereg14_en; +wire ctrl_pipereg_en; +wire ctrl_pipereg5_en; +wire ctrl_pipereg2_en; +wire ctrl_pipereg3_en; +wire ctrl_pipereg1_en; +wire ctrl_pipereg11_en; +wire ctrl_pipereg12_en; +wire ctrl_pipereg13_en; +wire crtl_ifetch_squashn; + +/****************************** Control **************************/ + //Decode Logic for Opcode and Multiplex Select signals +always@(posedge clk) +begin + // Initialize control opcodes to zero + + case (ifetch_opcode) + `OP_ADDI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_ADDIU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_ANDI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BEQ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BGTZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BLEZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_BNE: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_JAL: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + end + `OP_LB: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LBU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LH: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LHU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_LUI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + end + `OP_LW: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_ORI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_REGIMM: + case (ifetch_rt[0]) + `FUNC_BGEZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_BLTZ: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + endcase + `OP_SB: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SH: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SLTI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SLTIU: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_SPECIAL: + case (ifetch_func) + `FUNC_ADD: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_ADDU: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_AND: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_JALR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_JR: + ctrl_zeroer_en <= 1'b1; + `FUNC_MFHI: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + end + `FUNC_MFLO: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + end + `FUNC_MULT: + begin + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_MULTU: + begin + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_NOR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_OR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SLL: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + end + `FUNC_SLLV: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SLT: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SLTU: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SRA: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + end + `FUNC_SRAV: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SRL: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + end + `FUNC_SRLV: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SUB: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_SUBU: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `FUNC_XOR: + begin + ctrl_mux3to1_zeroer4_d_sel <= 2'b01; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + endcase + `OP_SW: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_zeroer0_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + `OP_XORI: + begin + ctrl_mux2to1_pipereg_d_sel <= 1'b1; + ctrl_mux3to1_zeroer4_d_sel <= 2'b10; + ctrl_zeroer4_en <= 1'b1; + ctrl_zeroer_en <= 1'b1; + end + endcase + + //Logic for enable signals in Pipe Stage 1 + ctrl_reg_file_b_en <= ~stall_out_stage2; + ctrl_reg_file_a_en <= ~stall_out_stage2; + ctrl_ifetch_en <= ~stall_out_stage2; + + //Decode Logic for Opcode and Multiplex Select signals + + + // Initialize control opcodes to zero + + + case (pipereg11_q) + `OP_ADDI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b011; + end + `OP_ADDIU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b001; + end + `OP_ANDI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_logic_unit_op <= 2'b00; + end + `OP_BEQ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b101; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_BGTZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b000; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_BLEZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b011; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_BNE: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b100; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `OP_J: + begin + ctrl_mux3to1_ifetch_load_data_sel<= 2'b01; + ctrl_ifetch_op <= 1'b1; + end + `OP_JAL: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b1; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b01; + ctrl_addersub_op <= 3'b001; + ctrl_ifetch_op <= 1'b1; + end + `OP_LB: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0111; + ctrl_addersub_op <= 3'b011; + end + `OP_LBU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0011; + ctrl_addersub_op <= 3'b011; + end + `OP_LH: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0101; + ctrl_addersub_op <= 3'b011; + end + `OP_LHU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0001; + ctrl_addersub_op <= 3'b011; + end + `OP_LUI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b01; + ctrl_mul_op <= 3'b000; + end + `OP_LW: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b010; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0000; + ctrl_addersub_op <= 3'b011; + end + `OP_ORI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_logic_unit_op <= 2'b01; + end + `OP_REGIMM: + case (pipereg13_q[0]) + `FUNC_BGEZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b001; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + `FUNC_BLTZ: + begin + ctrl_mux6to1_ifetch_load_sel <= 3'b010; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b10; + ctrl_ifetch_op <= 1'b0; + end + endcase + `OP_SB: + begin + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b0011; + ctrl_addersub_op <= 3'b011; + end + `OP_SH: + begin + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b1001; + ctrl_addersub_op <= 3'b011; + end + `OP_SLTI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b101; + end + `OP_SLTIU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_addersub_op <= 3'b100; + end + `OP_SPECIAL: + case (pipereg12_q) + `FUNC_ADD: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b011; + end + `FUNC_ADDU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b001; + end + `FUNC_AND: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b00; + end + `FUNC_JALR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b1; + ctrl_mux3to1_ifetch_load_data_sel<= 2'b00; + ctrl_addersub_op <= 3'b001; + ctrl_ifetch_op <= 1'b1; + end + `FUNC_JR: + begin + ctrl_mux3to1_ifetch_load_data_sel<= 2'b00; + ctrl_ifetch_op <= 1'b1; + end + `FUNC_MFHI: + ctrl_mux7to1_nop10_d_sel <= 3'b001; + `FUNC_MFLO: + ctrl_mux7to1_nop10_d_sel <= 3'b000; + `FUNC_MULT: + begin + ctrl_mux2to1_mul_opA_sel <= 1'b1; + ctrl_mul_op <= 3'b110; + end + `FUNC_MULTU: + begin + ctrl_mux2to1_mul_opA_sel <= 1'b1; + ctrl_mul_op <= 3'b100; + end + `FUNC_NOR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b11; + end + `FUNC_OR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b01; + end + `FUNC_SLL: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b00; + ctrl_mul_op <= 3'b000; + end + `FUNC_SLLV: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b10; + ctrl_mul_op <= 3'b000; + end + `FUNC_SLT: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b110; + end + `FUNC_SLTU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b101; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b100; + end + `FUNC_SRA: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b00; + ctrl_mul_op <= 3'b011; + end + `FUNC_SRAV: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b10; + ctrl_mul_op <= 3'b011; + end + `FUNC_SRL: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b00; + ctrl_mul_op <= 3'b001; + end + `FUNC_SRLV: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b011; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_mux2to1_mul_opA_sel <= 1'b0; + ctrl_mux3to1_mul_sa_sel <= 2'b10; + ctrl_mul_op <= 3'b001; + end + `FUNC_SUB: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b000; + end + `FUNC_SUBU: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b110; + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_addersub_op <= 3'b010; + end + `FUNC_XOR: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b01; + ctrl_logic_unit_op <= 2'b10; + end + endcase + `OP_SW: + begin + ctrl_mux2to1_addersub_opA_sel <= 1'b0; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_data_mem_op <= 4'b1000; + ctrl_addersub_op <= 3'b011; + end + `OP_XORI: + begin + ctrl_mux7to1_nop10_d_sel <= 3'b100; + ctrl_mux3to1_nop6_d_sel <= 2'b10; + ctrl_logic_unit_op <= 2'b10; + end + endcase + + + + //Logic for enable signals in Pipe Stage 2 + + + + case (pipereg11_q) + `OP_ADDI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_ADDIU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_ANDI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_BEQ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_BGTZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_BLEZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_BNE: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_J: + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_JAL: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `OP_LB: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LBU: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LH: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LHU: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_LUI: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `OP_LW: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_data_mem_en <=1'b1; + end + `OP_ORI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_REGIMM: + case (pipereg13_q[0]) + `FUNC_BGEZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `FUNC_BLTZ: + begin + ctrl_branchresolve_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + endcase + `OP_SB: + ctrl_data_mem_en <=1'b1; + `OP_SH: + ctrl_data_mem_en <=1'b1; + `OP_SLTI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_SLTIU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `OP_SPECIAL: + case (pipereg12_q) + `FUNC_ADD: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_ADDU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_AND: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_JALR: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + end + `FUNC_JR: + ctrl_ifetch_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_MFHI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_MFLO: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_MULT: + begin + ctrl_hi_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_lo_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_MULTU: + begin + ctrl_hi_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_lo_reg_en <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_NOR: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_OR: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SLL: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SLLV: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SLT: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SLTU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SRA: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SRAV: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SRL: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SRLV: + begin + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + ctrl_mul_start <=1'b1; + end + `FUNC_SUB: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_SUBU: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + `FUNC_XOR: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + endcase + `OP_SW: + ctrl_data_mem_en <=1'b1; + `OP_XORI: + ctrl_reg_file_c_we <=~ctrl_data_mem_stalled&~ctrl_mul_stalled; + endcase +end + +/********* Stall Network & PipeReg Control ********/ +assign stall_out_stage1 = stall_out_stage2; +assign ctrl_pipereg13_en = ~stall_out_stage1; +assign ctrl_pipereg12_en = ~stall_out_stage1; +assign ctrl_pipereg11_en = ~stall_out_stage1; +assign ctrl_pipereg1_en = ~stall_out_stage1; +assign ctrl_pipereg3_en = ~stall_out_stage1; +assign ctrl_pipereg2_en = ~stall_out_stage1; +assign ctrl_pipereg5_en = ~stall_out_stage1; +assign ctrl_pipereg_en = ~stall_out_stage1; +assign ctrl_pipereg14_en = ~stall_out_stage1; +assign ctrl_pipereg15_en = ~stall_out_stage1; +assign ctrl_pipereg16_en = ~stall_out_stage1; +assign stall_out_stage2 = ctrl_data_mem_stalled|ctrl_mul_stalled; +assign branch_mispred = (((ctrl_ifetch_op==1) || (ctrl_ifetch_op==0 && mux6to1_ifetch_load_out)) & ctrl_ifetch_we); +assign stall_2nd_delayslot = &has_delayslot; +assign has_delayslot = 0; +assign squash_stage1 = ((stall_out_stage1&~stall_out_stage2))|~resetn; +assign ctrl_pipereg13_resetn = ~squash_stage1; +assign ctrl_pipereg12_resetn = ~squash_stage1; +assign ctrl_pipereg11_resetn = ~squash_stage1; +assign ctrl_pipereg1_resetn = ~squash_stage1; +assign ctrl_pipereg3_resetn = ~squash_stage1; +assign ctrl_pipereg2_resetn = ~squash_stage1; +assign ctrl_pipereg5_resetn = ~squash_stage1; +assign ctrl_pipereg_resetn = ~squash_stage1; +assign ctrl_pipereg14_resetn = ~squash_stage1; +assign ctrl_pipereg15_resetn = ~squash_stage1; +assign ctrl_pipereg16_resetn = ~squash_stage1; +assign ctrl_pipereg16_squashn = 1'b1; +assign ctrl_pipereg15_squashn = 1'b1; +assign ctrl_pipereg14_squashn = 1'b1; +assign ctrl_pipereg_squashn = 1'b1; +assign ctrl_pipereg5_squashn = 1'b1; +assign ctrl_pipereg2_squashn = 1'b1; +assign ctrl_pipereg3_squashn = 1'b1; +assign ctrl_pipereg1_squashn = 1'b1; +assign ctrl_pipereg11_squashn = 1'b1; +assign ctrl_pipereg12_squashn = 1'b1; +assign ctrl_pipereg13_squashn = 1'b1; +assign ctrl_ifetch_squashn = 1'b1; +wire ctrl_ifetch_squashn; + +assign squash_stage2 = ((stall_out_stage2))|~resetn; + +/****************************** Datapath **************************/ +/******************** Hazard Detection Logic ***********************/ +assign haz_zeroer0_q_pipereg5_q = (zeroer0_q==pipereg5_q) && (|zeroer0_q); +assign haz_zeroer_q_pipereg5_q = (zeroer_q==pipereg5_q) && (|zeroer_q); +assign const8_out = 32'b00000000000000000000000000000000; +assign const9_out = 32'b00000000000000000000000000010000; +assign const_out = 32'b00000000000000000000000000011111; + + + + +/*************** DATAPATH COMPONENTS **************/ +addersub addersub ( + .opB(nop6_q), + .opA(mux2to1_addersub_opA_out), + .op(ctrl_addersub_op), + .result_slt(addersub_result_slt), + .result(addersub_result)); +// defparam + // addersub.WIDTH=32; + +reg_file reg_file ( + .clk(clk), + .resetn(resetn), + .c_writedatain(nop10_q), + .c_reg(pipereg5_q), + .b_reg(zeroer0_q), + .a_reg(zeroer_q), + .c_we(ctrl_reg_file_c_we), + .b_en(ctrl_reg_file_b_en), + .a_en(ctrl_reg_file_a_en), + .b_readdataout(reg_file_b_readdataout), + .a_readdataout(reg_file_a_readdataout)); + +mul mul ( + .clk(clk), + .resetn(resetn), + .sa(mux3to1_mul_sa_out), + .dst(pipereg5_q), + .opB(nop7_q), + .opA(mux2to1_mul_opA_out), + .op(ctrl_mul_op), + .start(ctrl_mul_start), + .stalled(ctrl_mul_stalled), + .shift_result(mul_shift_result), + .lo(mul_lo), + .hi(mul_hi)); +// defparam + // mul.WIDTH=32; + +ifetch ifetch ( + .clk(clk), + .resetn(resetn), + .boot_iaddr(boot_iaddr), + .boot_idata(boot_idata), + .boot_iwe(boot_iwe), + .load(mux6to1_ifetch_load_out), + .load_data(mux3to1_ifetch_load_data_out), + .op(ctrl_ifetch_op), + .we(ctrl_ifetch_we), + .squashn(ctrl_ifetch_squashn), + .en(ctrl_ifetch_en), + .pc_out(ifetch_pc_out), + .instr(ifetch_instr), + .opcode(ifetch_opcode), + .func(ifetch_func), + .rs(ifetch_rs), + .rt(ifetch_rt), + .rd(ifetch_rd), + .instr_index(ifetch_instr_index), + .offset(ifetch_offset), + .sa(ifetch_sa), + .next_pc(ifetch_next_pc)); + +data_mem data_mem ( + .clk(clk), + .resetn(resetn), + .stalled(ctrl_data_mem_stalled), + .d_writedata(nop7_q), + .d_address(addersub_result), + .op(ctrl_data_mem_op), + .d_loadresult(data_mem_d_loadresult)); + +logic_unit logic_unit ( + .opB(nop6_q), + .opA(nop_q), + .op(ctrl_logic_unit_op), + .result(logic_unit_result)); +// defparam + // logic_unit.WIDTH=32; + +pcadder pcadder ( + .offset(pipereg_q), + .pc(pipereg3_q), + .result(pcadder_result)); + +signext16 signext16 ( + .in(ifetch_offset), + .out(signext16_out)); + +merge26lo merge26lo ( + .in2(pipereg1_q), + .in1(pipereg3_q), + .out(merge26lo_out)); + +hi_reg hi_reg ( + .clk(clk), + .resetn(resetn), + .d(mul_hi), + .en(ctrl_hi_reg_en), + .q(hi_reg_q)); +// defparam +// hi_reg.WIDTH=32; + +branchresolve branchresolve ( + .rt(nop7_q), + .rs(nop_q), + .en(ctrl_branchresolve_en), + .eqz(branchresolve_eqz), + .gez(branchresolve_gez), + .gtz(branchresolve_gtz), + .lez(branchresolve_lez), + .ltz(branchresolve_ltz), + .ne(branchresolve_ne), + .eq(branchresolve_eq)); +// defparam +// branchresolve.WIDTH=32; + +lo_reg lo_reg ( + .clk(clk), + .resetn(resetn), + .d(mul_lo), + .en(ctrl_lo_reg_en), + .q(lo_reg_q)); +// defparam +// lo_reg.WIDTH=32; + +/* +const const8 ( + .out(const8_out)); +// defparam + // const8.WIDTH=32, + //const8.VAL=0; + +const const9 ( + .out(const9_out)); +// defparam + // const9.WIDTH=32, + //const9.VAL=16; + +const const ( + .out(const_out)); +// defparam + // const.WIDTH=32, + //const.VAL=31; + */ + +pipereg_w32 pipereg ( + .clk(clk), + .resetn(ctrl_pipereg_resetn), + .d(mux2to1_pipereg_d_out), + .squashn(ctrl_pipereg_squashn), + .en(ctrl_pipereg_en), + .q(pipereg_q)); +// defparam + // pipereg.WIDTH=32; + +pipereg_w26 pipereg1 ( + .clk(clk), + .resetn(ctrl_pipereg1_resetn), + .d(ifetch_instr_index), + .squashn(ctrl_pipereg1_squashn), + .en(ctrl_pipereg1_en), + .q(pipereg1_q)); +// defparam + // pipereg1.WIDTH=26; + +pipereg_w5 pipereg2 ( + .clk(clk), + .resetn(ctrl_pipereg2_resetn), + .d(ifetch_sa), + .squashn(ctrl_pipereg2_squashn), + .en(ctrl_pipereg2_en), + .q(pipereg2_q)); +// defparam + // pipereg2.WIDTH=5; + +pipereg_w5 pipereg5 ( + .clk(clk), + .resetn(ctrl_pipereg5_resetn), + .d(zeroer4_q), + .squashn(ctrl_pipereg5_squashn), + .en(ctrl_pipereg5_en), + .q(pipereg5_q)); + //defparam + //pipereg5.WIDTH=5; + +pipereg_w32 pipereg14 ( + .clk(clk), + .resetn(ctrl_pipereg14_resetn), + .d(nop10_q), + .squashn(ctrl_pipereg14_squashn), + .en(ctrl_pipereg14_en), + .q(pipereg14_q)); + //defparam + // pipereg14.WIDTH=32; + +pipereg_w32 pipereg3 ( + .clk(clk), + .resetn(ctrl_pipereg3_resetn), + .d(ifetch_pc_out), + .squashn(ctrl_pipereg3_squashn), + .en(ctrl_pipereg3_en), + .q(pipereg3_q)); +// defparam +// pipereg3.WIDTH=32; + +nop nop7 ( + .d(mux2to1_nop7_d_out), + .q(nop7_q)); + //defparam +// nop7.WIDTH=32; + +nop nop ( + .d(mux2to1_nop_d_out), + .q(nop_q)); + //defparam + // nop.WIDTH=32; + +nop nop10 ( + .d(mux7to1_nop10_d_out), + .q(nop10_q)); + //defparam + // nop10.WIDTH=32; + +nop nop6 ( + .d(mux3to1_nop6_d_out), + .q(nop6_q)); + //defparam + // nop6.WIDTH=32; + +zeroer zeroer ( + .d(ifetch_rs), + .en(ctrl_zeroer_en), + .q(zeroer_q)); + //defparam + // zeroer.WIDTH=5; + +zeroer zeroer0 ( + .d(ifetch_rt), + .en(ctrl_zeroer0_en), + .q(zeroer0_q)); + //defparam + // zeroer0.WIDTH=5; + +zeroer zeroer4 ( + .d(mux3to1_zeroer4_d_out), + .en(ctrl_zeroer4_en), + .q(zeroer4_q)); + //defparam + // zeroer4.WIDTH=5; + +fakedelay fakedelay ( + .clk(clk), + .d(ifetch_pc_out), + .q(fakedelay_q)); + //defparam + // fakedelay.WIDTH=32; + + // Multiplexor mux3to1_ifetch_load_data instantiation +assign mux3to1_ifetch_load_data_out = + (ctrl_mux3to1_ifetch_load_data_sel==2) ? pcadder_result : + (ctrl_mux3to1_ifetch_load_data_sel==1) ? merge26lo_out : + nop_q; + + // Multiplexor mux2to1_mul_opA instantiation +assign mux2to1_mul_opA_out = + (ctrl_mux2to1_mul_opA_sel==1) ? nop_q : + nop6_q; + + // Multiplexor mux6to1_ifetch_load instantiation +assign mux6to1_ifetch_load_out = + (ctrl_mux6to1_ifetch_load_sel==3'd5) ? branchresolve_eq : + (ctrl_mux6to1_ifetch_load_sel==3'd4) ? branchresolve_ne : + (ctrl_mux6to1_ifetch_load_sel==3'd3) ? branchresolve_lez : + (ctrl_mux6to1_ifetch_load_sel==3'd2) ? branchresolve_ltz : + (ctrl_mux6to1_ifetch_load_sel==3'd1) ? branchresolve_gez : + branchresolve_gtz; + + // Multiplexor mux3to1_mul_sa instantiation +assign mux3to1_mul_sa_out = + (ctrl_mux3to1_mul_sa_sel==2) ? nop_q : + (ctrl_mux3to1_mul_sa_sel==1) ? const9_out : + pipereg2_q; + + // Multiplexor mux2to1_addersub_opA instantiation +assign mux2to1_addersub_opA_out = + (ctrl_mux2to1_addersub_opA_sel==1) ? fakedelay_q : + nop_q; + + // Multiplexor mux7to1_nop10_d instantiation +assign mux7to1_nop10_d_out = + (ctrl_mux7to1_nop10_d_sel==3'd6) ? addersub_result : + (ctrl_mux7to1_nop10_d_sel==3'd5) ? addersub_result_slt : + (ctrl_mux7to1_nop10_d_sel==3'd4) ? logic_unit_result : + (ctrl_mux7to1_nop10_d_sel==3'd3) ? mul_shift_result : + (ctrl_mux7to1_nop10_d_sel==3'd2) ? data_mem_d_loadresult : + (ctrl_mux7to1_nop10_d_sel==3'd1) ? hi_reg_q : + lo_reg_q; + + // Multiplexor mux2to1_pipereg_d instantiation +assign mux2to1_pipereg_d_out = + (ctrl_mux2to1_pipereg_d_sel==1) ? ifetch_offset : + signext16_out; + + // Multiplexor mux3to1_nop6_d instantiation +assign mux3to1_nop6_d_out = + (ctrl_mux3to1_nop6_d_sel==2) ? pipereg_q : + (ctrl_mux3to1_nop6_d_sel==1) ? nop7_q : + const8_out; + + // Multiplexor mux3to1_zeroer4_d instantiation +assign mux3to1_zeroer4_d_out = + (ctrl_mux3to1_zeroer4_d_sel==2) ? ifetch_rt : + (ctrl_mux3to1_zeroer4_d_sel==1) ? ifetch_rd : + const_out; + +pipereg_w6 pipereg11 ( + .clk(clk), + .resetn(ctrl_pipereg11_resetn), + .d(ifetch_opcode), + .squashn(ctrl_pipereg11_squashn), + .en(ctrl_pipereg11_en), + .q(pipereg11_q)); + //defparam + // pipereg11.WIDTH=6; + + // Multiplexor mux2to1_nop_d instantiation +assign mux2to1_nop_d_out = + (pipereg15_q==1) ? pipereg14_q : + reg_file_a_readdataout; + +pipereg_w1 pipereg16 ( + .clk(clk), + .resetn(ctrl_pipereg16_resetn), + .d(haz_zeroer0_q_pipereg5_q), + .squashn(ctrl_pipereg16_squashn), + .en(ctrl_pipereg16_en), + .q(pipereg16_q)); + //defparam + // pipereg16.WIDTH=1; + +pipereg_w1 pipereg15 ( + .clk(clk), + .resetn(ctrl_pipereg15_resetn), + .d(haz_zeroer_q_pipereg5_q), + .squashn(ctrl_pipereg15_squashn), + .en(ctrl_pipereg15_en), + .q(pipereg15_q)); + //defparam + // pipereg15.WIDTH=1; + + // Multiplexor mux2to1_nop7_d instantiation +assign mux2to1_nop7_d_out = + (pipereg16_q==1) ? pipereg14_q : + reg_file_b_readdataout; + +pipereg_w6 pipereg12 ( + .clk(clk), + .resetn(ctrl_pipereg12_resetn), + .d(ifetch_func), + .squashn(ctrl_pipereg12_squashn), + .en(ctrl_pipereg12_en), + .q(pipereg12_q)); + //defparam + // pipereg12.WIDTH=6; + +pipereg_w5 pipereg13 ( + .clk(clk), + .resetn(ctrl_pipereg13_resetn), + .d(ifetch_rt), + .squashn(ctrl_pipereg13_squashn), + .en(ctrl_pipereg13_en), + .q(pipereg13_q)); + //defparam + // pipereg13.WIDTH=5; + + + +endmodule + +/**************************************************************************** + AddSub unit +- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU + + is_slt signext addsub + op[2] op[1] op[0] | Operation +0 0 0 0 SUBU +2 0 1 0 SUB +1 0 0 1 ADDU +3 0 1 1 ADD +4 1 0 0 SLTU +6 1 1 0 SLT + +****************************************************************************/ +module addersub ( + opB, + opA, + op, + result_slt, + result +); + +//parameter WIDTH=32; +//`DEFINE WIDTH 32 + + +input [31:0] opA; +input [31:0] opB; +//input carry_in; +input [2:0] op; +output result_slt; +output [31:0] result; + + + +wire [32:0] sum; + + +wire addsub; +wire useless; +assign useless = op[1] & op[2]; + + +assign addsub=op[0]; +wire not_addsub; +assign not_addsub = ~addsub; + +assign result=sum[31:0]; + +assign result_slt=sum[32]; + +dummy_add_sub adder32bit (opA,opB,not_addsub,sum); + + +// This is an LPM from Altera, replacing with a dummy one for now +/* +lpm_add_sub adder_inst( + .dataa({signext&opA[WIDTH-1],opA}), + .datab({signext&opB[WIDTH-1],opB}), + .cin(~addsub), + .add_sub(addsub), + .result(sum) + // synopsys translate_off + , + .cout (), + .clken (), + .clock (), + .overflow (), + .aclr () + // synopsys translate_on + ); +//defparam +// adder_inst.lpm_width=WIDTH+1, +// adder_inst.lpm_representation="SIGNED"; +*/ + +endmodule + + + + + +module dummy_add_sub ( + dataa, + datab, + cin, + result +); + +//this is goign to be UUUUGGGGGGLLLYYYYY +//probably going to do some serious timing violations +// but i'm sure it will be interesting for the packing problem +input [31:0] dataa; +input [31:0] datab; +input cin; +output [32:0] result; +// +wire [31:0] carry_from; +wire [31:0] sum; + + +full_adder bit0 (cin,dataa[0],datab[0],sum[0],carry_from [0]); +full_adder bit1 (carry_from [0],dataa[1],datab[1],sum[1],carry_from [1]); +full_adder bit2 (carry_from [1],dataa[2],datab[2],sum[2],carry_from [2]); +full_adder bit3 (carry_from [2],dataa[3],datab[3],sum[3],carry_from [3]); +full_adder bit4 (carry_from [3],dataa[4],datab[4],sum[4],carry_from [4]); +full_adder bit5 (carry_from [4],dataa[5],datab[5],sum[5],carry_from [5]); +full_adder bit6 (carry_from [5],dataa[6],datab[6],sum[6],carry_from [6]); +full_adder bit7 (carry_from [6],dataa[7],datab[7],sum[7],carry_from [7]); + +full_adder bit8 (carry_from [7],dataa[8],datab[8],sum[8],carry_from [8]); +full_adder bit9 (carry_from [8],dataa[9],datab[9],sum[9],carry_from [9]); +full_adder bit10 (carry_from [9],dataa[10],datab[10],sum[10],carry_from [10]); +full_adder bit11 (carry_from [10],dataa[11],datab[11],sum[11],carry_from [11]); +full_adder bit12 (carry_from [11],dataa[12],datab[12],sum[12],carry_from [12]); +full_adder bit13 (carry_from [12],dataa[13],datab[13],sum[13],carry_from [13]); +full_adder bit14 (carry_from [13],dataa[14],datab[14],sum[14],carry_from [14]); +full_adder bit15 (carry_from [14],dataa[15],datab[15],sum[15],carry_from [15]); + +full_adder bit16 (carry_from [15],dataa[16],datab[16],sum[16],carry_from [16]); +full_adder bit17 (carry_from [16],dataa[17],datab[17],sum[17],carry_from [17]); +full_adder bit18 (carry_from [17],dataa[18],datab[18],sum[18],carry_from [18]); +full_adder bit19 (carry_from [18],dataa[19],datab[19],sum[19],carry_from [19]); +full_adder bit20 (carry_from [19],dataa[20],datab[20],sum[20],carry_from [20]); +full_adder bit21 (carry_from [20],dataa[21],datab[21],sum[21],carry_from [21]); +full_adder bit22 (carry_from [21],dataa[22],datab[22],sum[22],carry_from [22]); +full_adder bit23 (carry_from [22],dataa[23],datab[23],sum[23],carry_from [23]); + +full_adder bit24 (carry_from [23],dataa[24],datab[24],sum[24],carry_from [24]); +full_adder bit25 (carry_from [24],dataa[25],datab[25],sum[25],carry_from [25]); +full_adder bit26 (carry_from [25],dataa[26],datab[26],sum[26],carry_from [26]); +full_adder bit27 (carry_from [26],dataa[27],datab[27],sum[27],carry_from [27]); +full_adder bit28 (carry_from [27],dataa[28],datab[28],sum[28],carry_from [28]); +full_adder bit29 (carry_from [28],dataa[29],datab[29],sum[29],carry_from [29]); +full_adder bit30 (carry_from [29],dataa[30],datab[30],sum[30],carry_from [30]); +full_adder bit31 (carry_from [30],dataa[31],datab[31],sum[31],carry_from [31]); + +assign result [31:0] = sum; +assign result [32] = carry_from [31]; + +endmodule + + +module full_adder (cin,x,y,s,cout); +input cin; +input x; +input y; +output s; +output cout; +assign s = x^y^cin; +assign cout = (x&y) | (x & cin) | (y&cin); +endmodule + +/**************************************************************************** + Register File + + - Has two read ports (a and b) and one write port (c) + - sel chooses the register to be read/written +****************************************************************************/ + +module reg_file( + clk, + resetn, + c_writedatain, + c_reg, + b_reg, + a_reg, + c_we, + b_en, + a_en, + b_readdataout, + a_readdataout +); +//parameter WIDTH=32; +//parameter NUMREGS=32; +//parameter LOG2NUMREGS=5; +input clk; +input resetn; + +input a_en; +input b_en; +input [31:0] c_writedatain; +input c_we; +input [31:0] a_reg; +input [31:0] b_reg; +input [31:0] c_reg; +output [31:0] a_readdataout; +output [31:0] b_readdataout; +reg [31:0] a_readdataout; +reg [31:0] b_readdataout; + + +wire [31:0] a_readdataout_temp; +wire [31:0] b_readdataout_temp; + + +assign b_readdataout = b_readdataout_temp; +assign a_readdataout = a_readdataout_temp; + +wire wren1; +assign wren1 = (c_we & (|c_reg)); +single_port_ram regfile1_replace ( + .clk (clk), + .we(wren1), + .data(c_writedatain), + .out(a_readdataout_temp), + .addr(c_reg[4:0]) +); + +//Reg file duplicated to avoid contention +//between 2 read and 1 write +//MORE MEMORY + +single_port_ram regfile2_replace( + .clk (clk), + .we(wren1), + .data(c_writedatain), + .out(b_readdataout_temp), + .addr(c_reg[4:0]) +); + +//Odin II does not recognize that address +//registers are being used to read and +//write data, so they are assigned to an +//unused wire which is later dropped by the +//optimizer. +wire useless_inputs; +//`a_reg` and `b_reg` were not used correctly in last version +//of `spree.v` according to the comment above this module. +//Investigate whether the comment or the code is wrong +assign useless_inputs = resetn & b_en & a_en & ( | a_reg ) & ( | b_reg ); +endmodule + +/**************************************************************************** + MUL/DIV unit + +Operation table + + op sign dir +4 1 0 x | MULTU +6 1 1 x | MULT +0 0 0 0 | ShiftLeft +1 0 0 1 | ShiftRightLogic +3 0 1 1 | ShiftRightArith +****************************************************************************/ +module mul( + clk, + resetn, + sa, + dst, + opB, + opA, + op, + start, + stalled, + shift_result, + lo, + hi +); + +input clk; +input resetn; + +input start; +output stalled; + +input [4:0] dst; + +input [31:0] opA; +input [31:0] opB; +input [4:0] sa; +input [2:0] op; + +output [31:0] shift_result; +output [31:0] hi; +output [31:0] lo; + +/********* Control Signals *********/ +wire is_signed; +wire dir; +wire is_mul; +assign is_mul=op[2]; // selects between opB and the computed shift amount +assign is_signed=op[1]; +assign dir=op[0]; // selects between 2^sa and 2^(32-sa) for right shift + +/********* Circuit Body *********/ +wire dum; +wire dum2; +wire dum3; +wire [32:0] opB_mux_out; +wire [4:0] left_sa; // Amount of left shift required for both left/right +reg [32:0] decoded_sa; +wire [31:0] result; +//assign opB_mux_out= (is_mul) ? {is_signed&opB[31],opB} : decoded_sa; +assign opB_mux_out = opB; + + + +dummy_mult fake_mult_one (opA,opB_mux_out, clk, resetn, result); +assign hi = result [15:8]; +assign lo = result [7:0]; +// Cannot support this now +/* +lpm_mult lpm_mult_component ( + .dataa ({is_signed&opA[31],opA}), + .datab (opB_mux_out), + .sum(), + .clock(clk), + .clken(), + .aclr(~resetn), + .result ({dum2,dum,hi,lo})); +defparam + lpm_mult_component.lpm_32a = 32+1, + lpm_mult_component.lpm_32b = 32+1, + lpm_mult_component.lpm_32p = 2*32+2, + lpm_mult_component.lpm_32s = 1, + lpm_mult_component.lpm_pipeline = 1, + lpm_mult_component.lpm_type = "LPM_MULT", + lpm_mult_component.lpm_representation = "SIGNED", + lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6"; +*/ +assign shift_result= (dir & |sa) ? hi : lo; + + +// 1 cycle stall state machine +wire or_dst; +wire start_and_ismul; +wire request; + +assign or_dst = |dst; +assign start_and_ismul = start & is_mul; +assign request = (or_dst & start & ~is_mul) | (start_and_ismul); +onecyclestall staller(request,clk,resetn,stalled); + + +endmodule + +module dummy_mult ( + opA, + opB_mux_out, + clk, + resetn, + result +); + +input [31:0] opA; +input [31:0] opB_mux_out; +input clk; +input resetn; +output[31:0] result; +reg [31:0] result; + + +always @ (posedge clk) +begin + if (resetn) + result <= 32'b00000000000000000000000000000000; + else + //multiplier by star symbol + //though this is probably supposed to be signed + result <= opA * opB_mux_out; +end +endmodule + + +/**************************************************************************** + Fetch Unit +op + 0 Conditional PC write + 1 UnConditional PC write + +****************************************************************************/ + +module ifetch( + clk, + resetn, + boot_iaddr, + boot_idata, + boot_iwe, + load, + load_data, + op, + we, + squashn, + en, + pc_out, + instr, + opcode, + func, + rs, + rt, + rd, + instr_index, + offset, + sa, + next_pc +); + +//parameter PC_WIDTH=30; +//parameter I_DATAWIDTH=32; +//parameter I_ADDRESSWIDTH=14; +//parameter I_SIZE=16384; + +input [31:0] boot_iaddr; +input [31:0] boot_idata; +input boot_iwe; + +input clk; +input resetn; +input en; // PC increment enable +input we; // PC write enable +input squashn;// squash fetch +input op; // determines if conditional or unconditional branch +input load; +input [`I_DATAWIDTH-1:0] load_data; +output [`I_DATAWIDTH-1:0] pc_out; // output pc + 1 shifted left 2 bits +output [`PC_WIDTH-1:0] next_pc; +output [31:26] opcode; +output [25:21] rs; +output [20:16] rt; +output [15:11] rd; +output [10:6] sa; +output [15:0] offset; +output [25:0] instr_index; +output [5:0] func; +output [`I_DATAWIDTH-1:0] instr; + + +wire [`PC_WIDTH-1:0] pc_plus_1; +wire [`PC_WIDTH-1:0] pc; +assign pc_plus_1 = pc; +wire ctrl_load; +wire out_of_sync; + +assign ctrl_load=(load&~op|op); +wire notresetn; +assign notresetn = ~resetn; +wire count_en; +assign count_en = (~ctrl_load)&~out_of_sync; +wire counter_en; +assign counter_en = en | we; +wire [32:2] reg_load_data; + +assign reg_load_data = load_data [31:2]; + +wire reg_d; +wire reg_en; +assign reg_d = (we&(~en)&(squashn)); +assign reg_en = en|we; + + +register_1bit sync_pcs_up( reg_d, clk, resetn,reg_en, out_of_sync); + +wire wren1; +assign wren1 = 1'b0; +wire [9:0] next_pc_wire; +assign next_pc_wire = next_pc [9:0]; + +wire [31:0]dummyout2; + +dual_port_ram imem_replace( + .clk (clk), + .we1(wren1), + .we2(boot_iwe), + .data1(load_data), + .data2(boot_idata), + .out1(instr), + .out2(dummyout2), + .addr1(next_pc_wire), + .addr2(boot_iaddr[9:0]) +); + +wire [31:0] dummyin1; +assign dummyin1 = 32'b00000000000000000000000000000000; + +dummy_counter pc_reg ((reg_load_data),(clk),(counter_en),(count_en),(notresetn),(ctrl_load),(pc)); +assign pc_out [31:2] = pc_plus_1; +assign pc_out [1:0] = 2'b00; + +assign next_pc = ctrl_load ? load_data[31:2] : pc_plus_1; +assign opcode=instr[31:26]; +assign rs=instr[25:21]; +assign rt=instr[20:16]; +assign rd=instr[15:11]; +assign sa=instr[10:6]; +assign offset=instr[15:0]; +assign instr_index=instr[25:0]; +assign func=instr[5:0]; + +//Odin II does not recognize that boot_iaddr +//is being used to write data when system +//is given 1'b1 on the boot_iwe wire so is +//is assigned to an unused wire which is +//later dropped by the optimizer. +wire NoUse; +assign NoUse = ( |boot_iaddr ); + +endmodule + + +module dummy_counter ( + data, + clock, + clk_en, + cnt_en, + aset, + sload, + q +); + +input [31:2] data; +input clock; +input clk_en; +input cnt_en; +input aset; +input sload; +output [`PC_WIDTH-1:0] q; +reg [`PC_WIDTH-1:0] q; + +wire [2:0] sload_cnten_aset; +assign sload_cnten_aset [0] = sload; +assign sload_cnten_aset [1] = cnt_en; +assign sload_cnten_aset [2] = aset; + +always @ (posedge clock) + +//if (cnt_en == 1) +//q <= q+1; +begin + +case (sload_cnten_aset) + 3'b000: + q <= q; + 3'b011: + q <= q; + 3'b110: + q <= q; + 3'b111: + q <= q; + 3'b101: + q <= q; + 3'b100: + q <= data; + 3'b010: + begin + if (clk_en) + q <= q+1; + else + q <= q; + end + 3'b001: + q <= 29'b00000000000000000000000000000; + default: + q <= q; +endcase +end +endmodule + + + + +module data_mem( + clk, + resetn, + stalled, + d_writedata, + d_address, + op, + d_loadresult +); + +input clk; +input resetn; +output stalled; + +input [`D_ADDRESSWIDTH-1:0] d_address; +input [3:0] op; +input [31:0] d_writedata; +output [`DM_DATAWIDTH-1:0] d_loadresult; + +wire [`DM_BYTEENAWIDTH-1:0] d_byteena; +wire [`DM_DATAWIDTH-1:0] d_readdatain; +wire [`DM_DATAWIDTH-1:0] d_writedatamem; + +wire d_write; +wire [1:0] d_address_latched; + +assign d_write=op[3]; + +wire [1:0] d_small_adr; +assign d_small_adr = d_address[1:0]; + +wire one; +assign one = 1'b1; + + +wire [1:0] d_adr_one_zero; +assign d_adr_one_zero = d_address [1:0]; + +wire [1:0] opsize; +assign opsize = op[1:0]; +wire opext; +assign opext = op[2]; + + +store_data_translator sdtrans_inst( + .write_data(d_writedata), + .d_address(d_adr_one_zero), + .store_size(op[1:0]), + .d_byteena(d_byteena), + .d_writedataout(d_writedatamem) +); + + + +load_data_translator ldtrans_inst( + .d_readdatain(d_readdatain), + .d_loadresult(d_loadresult) +); + + +wire dnot_address; +assign dnot_address = ~d_address[31]; +wire will_be_wren1; +assign will_be_wren1 = d_write&(dnot_address); + +wire [9:0] memaddr_wrd; + + +assign memaddr_wrd = d_address[`DM_ADDRESSWIDTH:2]; +single_port_ram dmem_replace( + .clk (clk), + .we(will_be_wren1), + .data(d_writedatamem), + .out(d_readdatain), + .addr(memaddr_wrd) +); +// 1 cycle stall state machine + +wire en_and_not_d_write; +assign en_and_not_d_write = ~d_write; +onecyclestall staller(en_and_not_d_write,clk,resetn,stalled); + +wire useless_inputs; +assign useless_inputs = |d_address; + +endmodule + +//temp in here + + + + +/**************************************************************************** + Store data translator + - moves store data to appropriate byte/halfword + - interfaces with altera blockrams +****************************************************************************/ +module store_data_translator( + write_data, // data in least significant position + d_address, + store_size, + d_byteena, + d_writedataout // shifted data to coincide with address +); + +//parameter WIDTH=32; + +input [31:0] write_data; +input [1:0] d_address; +input [1:0] store_size; +output [3:0] d_byteena; +output [31:0] d_writedataout; + +reg [3:0] d_byteena; +reg [31:0] d_writedataout; + +always @(write_data or d_address or store_size) +begin + case (store_size) + 2'b11: + case(d_address[1:0]) + 2'b00: + begin + d_byteena=4'b1000; + d_writedataout={write_data[7:0],24'b0}; + end + 2'b01: + begin + d_byteena=4'b0100; + d_writedataout={8'b0,write_data[7:0],16'b0}; + end + 2'b10: + begin + d_byteena=4'b0010; + d_writedataout={16'b0,write_data[7:0],8'b0}; + end + default: + begin + d_byteena=4'b0001; + d_writedataout={24'b0,write_data[7:0]}; + end + endcase + 2'b01: + case(d_address[1]) + 1'b0: + begin + d_byteena=4'b1100; + d_writedataout={write_data[15:0],16'b0}; + end + default: + begin + d_byteena=4'b0011; + d_writedataout={16'b0,write_data[15:0]}; + end + endcase + default: + begin + d_byteena=4'b1111; + d_writedataout=write_data; + end + endcase +end + +endmodule + +/**************************************************************************** + Load data translator + - moves read data to appropriate byte/halfword and zero/sign extends +****************************************************************************/ + +module load_data_translator( + d_readdatain, + d_loadresult +); + +//parameter WIDTH=32; + +input [31:0] d_readdatain; + +output [31:0] d_loadresult; + +wire d_adr_one; +assign d_adr_one = d_address [1]; +reg [31:0] d_loadresult; +reg sign; +wire [1:0] d_address; +assign d_address [1:0] =d_readdatain [25:24]; + + +//assume always full-word-access +always @(d_readdatain or d_address ) +begin + d_loadresult[31:0]=d_readdatain[31:0]; +end +/* +Odin II REFUSES TO ACKNOWLEDGE THAT SIGN EXTENDING IS NOT A COMBINATIONAL LOOP +always @(d_readdatain or d_address or load_size or load_sign_ext) +begin + case (load_size) + 2'b11: + begin + case (d_address) + 2'b00: + begin + d_loadresult[7:0]=d_readdatain[31:24]; + sign = d_readdatain[31]; + end + 2'b01: + begin + d_loadresult[7:0]=d_readdatain[23:16]; + sign = d_readdatain[23]; + end + 2'b10: + begin + d_loadresult[7:0]=d_readdatain[15:8]; + sign = d_readdatain[15]; + end + default: + begin + d_loadresult[7:0]=d_readdatain[7:0]; + sign = d_readdatain[7]; + end + endcase + // peter milankov note: do this by hand + // odin II does not support multiple concatenation + //d_loadresult[31:8]={24{load_sign_ext&d_loadresult[7]}}; + d_loadresult[31]= load_sign_ext&sign; + d_loadresult[30]= load_sign_ext&sign; + d_loadresult[29]= load_sign_ext&sign; + d_loadresult[28]= load_sign_ext&sign; + d_loadresult[27]= load_sign_ext&sign; + d_loadresult[26]= load_sign_ext&sign; + d_loadresult[25]= load_sign_ext&sign; + d_loadresult[24]= load_sign_ext&sign; + d_loadresult[23]= load_sign_ext&sign; + d_loadresult[22]= load_sign_ext&sign; + d_loadresult[21]= load_sign_ext&sign; + d_loadresult[20]= load_sign_ext&sign; + d_loadresult[19]= load_sign_ext&sign; + d_loadresult[18]= load_sign_ext&sign; + d_loadresult[17]= load_sign_ext&sign; + d_loadresult[16]= load_sign_ext&sign; + d_loadresult[15]= load_sign_ext&sign; + d_loadresult[14]= load_sign_ext&sign; + d_loadresult[13]= load_sign_ext&sign; + d_loadresult[12]= load_sign_ext&sign; + d_loadresult[11]= load_sign_ext&sign; + d_loadresult[10]= load_sign_ext&sign; + d_loadresult[9]= load_sign_ext&sign; + d_loadresult[8]= load_sign_ext&sign; + end + 2'b01: + begin + case (d_adr_one) + 1'b0: + begin + d_loadresult[15:0]=d_readdatain[31:16]; + sign = d_readdatain[31]; + end + default: + begin + d_loadresult[15:0]=d_readdatain[15:0]; + sign = d_readdatain[15]; + end + endcase +// peter milankov note sign extend is concat, do by hand + //d_loadresult[31:16]={16{load_sign_ext&d_loadresult[15]}}; + d_loadresult[31]= load_sign_ext&sign; + d_loadresult[30]= load_sign_ext&sign; + d_loadresult[29]= load_sign_ext&sign; + d_loadresult[28]= load_sign_ext&sign; + d_loadresult[27]= load_sign_ext&sign; + d_loadresult[26]= load_sign_ext&sign; + d_loadresult[25]= load_sign_ext&sign; + d_loadresult[24]= load_sign_ext&sign; + d_loadresult[23]= load_sign_ext&sign; + d_loadresult[22]= load_sign_ext&sign; + d_loadresult[21]= load_sign_ext&sign; + d_loadresult[20]= load_sign_ext&sign; + d_loadresult[19]= load_sign_ext&sign; + d_loadresult[18]= load_sign_ext&sign; + d_loadresult[17]= load_sign_ext&sign; + d_loadresult[16]= load_sign_ext&sign; + end + default: + d_loadresult[31:0]=d_readdatain[31:0]; + endcase +end +*/ +endmodule + +/**************************************************************************** + logic unit +- note ALU must be able to increment PC for JAL type instructions + +Operation Table + op + 0 AND + 1 OR + 2 XOR + 3 NOR +****************************************************************************/ +module logic_unit ( + opB, + opA, + op, + result +); + +//parameter WIDTH=32; + +input [31:0] opA; +input [31:0] opB; +input [1:0] op; +output [31:0] result; + +reg [31:0] logic_result; + +always@(opA or opB or op ) + case(op) + 2'b00: + logic_result=opA&opB; + 2'b01: + logic_result=opA|opB; + 2'b10: + logic_result=opA^opB; + 2'b11: + logic_result=~(opA|opB); + endcase + +assign result=logic_result; + + +endmodule + +module pcadder( + offset, + pc, + result +); + +//parameter PC_WIDTH=32; + + +input [31:0] pc; +input [31:0] offset; +output [31:0] result; + +wire dum; +wire useless_inputs; +assign useless_inputs = |offset; +assign {dum,result} = pc + {offset[31:0],2'b0}; + +endmodule + + +module signext16 (in, out); + +input [15:0] in; +output [31:0] out; + + +assign out [30]= in[15]; +assign out [31]= in[15]; +assign out [29]= in[15]; +assign out [28]= in[15]; +assign out [27]= in[15]; +assign out [26]= in[15]; +assign out [25]= in[15]; +assign out [24]= in[15]; +assign out [23]= in[15]; +assign out [22]= in[15]; +assign out [21]= in[15]; +assign out [20]= in[15]; +assign out [19]= in[15]; +assign out [18]= in[15]; +assign out [17]= in[15]; +assign out [16]= in[15]; +assign out [15:0] = in [15:0]; + +endmodule + + +module merge26lo(in2, in1, out); +input [31:0] in1; +input [25:0] in2; +output [31:0] out; + +//assign out[31:0]={in1[31:28],in2[25:0],2'b0}; + +assign out [31:28] = in1 [31:28]; +assign out [27:2] = in2 [25:0]; +assign out [1:0] = 2'b00; + + +wire useless_inputs; +assign useless_inputs = |in1 & |in2; +endmodule + +/**************************************************************************** + Generic Register +****************************************************************************/ +module lo_reg( + clk, + resetn, + d, + en, + q +); + +//parameter WIDTH=32; + + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk ) +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + +/**************************************************************************** + Generic Register +****************************************************************************/ +module hi_reg( + clk, + resetn, + d, + en, + q +); + +//parameter WIDTH=32; + + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk ) //used to be asynchronous reset +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + +/**************************************************************************** + Generic Register +****************************************************************************/ + +//`define WIDTH 32 +/* +module register(d,clk,resetn,en,q); +//parameter WIDTH=32; + + + + + + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk ) +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule +*/ +module register_1bit( + d, + clk, + resetn, + en, + q +); + +//parameter WIDTH=32; + +input clk; +input resetn; +input en; +input d; +output q; +reg q; + +always @(posedge clk ) +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + + +/**************************************************************************** + Generic Register - synchronous reset +****************************************************************************/ +/* +module register_sync(d,clk,resetn,en,q); +//parameter WIDTH=32; + +input clk; +input resetn; +input en; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule +*/ +/**************************************************************************** + Generic Pipelined Register + + - Special component, components starting with "pipereg" have + their enables treated independently of instructrions that use them. + - They are enabled whenever the stage is active and not stalled +****************************************************************************/ +/* +module pipereg(clk,resetn,d,squashn,en,q); +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule +*/ +module pipereg_w32( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + + +module pipereg_w26( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [25:0] d; +output [25:0] q; +reg [25:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + + +module pipereg_w6( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + begin + q[5:0]<=d; + q[31:6] <= 0; + + end +end + +endmodule + + +module pipereg_w5( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + begin + q[4:0]<=d; + q[31:5] <= 0; + + end +end + +endmodule + +module pipereg_w1( + clk, + resetn, + d, + squashn, + en, + q +); + +//parameter WIDTH=32; +//`define WIDTH 32 + +input clk; +input resetn; +input en; +input squashn; +input d; +output q; +reg q; + +always @(posedge clk) //synchronous reset +begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; +end + +endmodule + +/**************************************************************************** + Generic Pipelined Register 2 -OLD: If not enabled, queues squash + + - This piperegister stalls the reset signal as well +*/ +/* +module pipereg_full(d,clk,resetn,squashn,en,q); +//parameter WIDTH=32; + +input clk; +input resetn; +input en; +input squashn; +input [31:0] d; +output [31:0] q; +reg [31:0] q; +reg squash_save; + + always @(posedge clk) //synchronous reset + begin + if (resetn==0 || (squashn==0 && en==1) || (squash_save&en)) + q<=0; + else if (en==1) + q<=d; + end + + always @(posedge clk) + begin + if (resetn==1 && squashn==0 && en==0) + squash_save<=1; + else + squash_save<=0; + end +endmodule +*/ +/****************************************************************************/ + +/**************************************************************************** + One cycle Stall circuit +****************************************************************************/ +module onecyclestall( + request, + clk, + resetn, + stalled +); + +input request; +input clk; +input resetn; +output stalled; + + reg T,Tnext; + + // State machine for Stalling 1 cycle + always@(request or T) + begin + case(T) + 1'b0: Tnext=request; + 1'b1: Tnext=0; + endcase + end + always@(posedge clk) + if (~resetn) + T<=0; + else + T<=Tnext; + assign stalled=(request&~T); +endmodule + +/**************************************************************************** + + Multi cycle Stall circuit - with wait signal + + - One FF plus one 2:1 mux to stall 1st cycle on request, then wait + - this makes wait don't care for the first cycle +****************************************************************************/ +/* +module multicyclestall(request, devwait,clk,resetn,stalled); +input request; +input devwait; +input clk; +input resetn; +output stalled; + + reg T; + + always@(posedge clk) + if (~resetn) + T<=0; + else + T<=stalled; + + assign stalled=(T) ? devwait : request; +endmodule +*/ +/**************************************************************************** + One cycle - Pipeline delay register +****************************************************************************/ +/* +module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q); +//`define WIDTH 32 +//parameter WIDTH=32; +input [31:0] d; +input [4:0] dst; +input en; +input clk; +input resetn; +input squashn; +output stalled; +output [31:0] q; + + reg [31:0] q; + reg T,Tnext; + + // State machine for Stalling 1 cycle + always@(en or T or dst) + begin + case(T) + 0: Tnext=en&(|dst); + 1: Tnext=0; + endcase + end + always@(posedge clk) + if (~resetn) + T<=0; + else + T<=Tnext; + + always @(posedge clk) //synchronous reset + begin + if (resetn==0 || squashn==0) + q<=0; + else if (en==1) + q<=d; + end + + assign stalled=(en&~T&(|dst)); +endmodule +*/ + +/**************************************************************************** + Fake Delay +****************************************************************************/ +module fakedelay(clk,d,q); +//`define WIDTH 32 +//parameter WIDTH=32; +input [31:0] d; +input clk; +output [31:0] q; + +wire unused; +assign unused = clk; +assign q=d; + +endmodule + +/**************************************************************************** + Zeroer +****************************************************************************/ +module zeroer(d,en,q); +//parameter WIDTH=32; +//`define WIDTH 32 + +input en; +input [4:0] d; +output [31:0] q; +assign q[4:0]= (en) ? d : 0; +assign q [31:05] = 0; + +endmodule + +/**************************************************************************** + NOP - used to hack position of multiplexors +****************************************************************************/ +module nop(d,q); +//parameter WIDTH=32; +//`define WIDTH 32 + +input [31:0] d; +output [31:0] q; + + assign q=d; + +endmodule + +/**************************************************************************** + + Const +****************************************************************************/ + +/**************************************************************************** + Branch detector +****************************************************************************/ +/* +module branch_detector(opcode, func, is_branch); + + +input [5:0] opcode; +input [5:0] func; +output is_branch; + +wire is_special; + +assign is_special=!(|opcode); +assign is_branch=((!(|opcode[5:3])) && !is_special) || + ((is_special)&&(func[5:3]==3'b001)); + +endmodule +*/ +//`define WIDTH 32 + +module branchresolve ( + rt, + rs, + en, + eqz, + gez, + gtz, + lez, + ltz, + ne, + eq +); + +//parameter WIDTH=32; + +input en; +input [31:0] rs; +input [31:0] rt; +output eq; +output ne; +output ltz; +output lez; +output gtz; +output gez; +output eqz; + +assign eq=(en)&(rs==rt); +assign ne=(en)&~eq; +assign eqz=(en)&~(|rs); +assign ltz=(en)&rs[31]; +assign lez=(en)&rs[31] | eqz; +assign gtz=(en)&(~rs[31]) & ~eqz; +assign gez=(en)&(~rs[31]); + +endmodule + + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v new file mode 100755 index 000000000..14708a142 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v @@ -0,0 +1,3905 @@ +// Ahmad Darabiha +// last updated Aug, 2002 +// this is the design for chip#0 of +// the stereo vision system. +// this is the last stage which interpolates the results of correlation +// and after LPF it takes the Max and send the final results to chip #3 to +// be displayed on the monitor. + +module sv_chip0_hierarchy_no_mem (tm3_clk_v0, bus_word_1_1to0, bus_word_2_1to0, bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, counter_out_1to0, vidin_new_data_fifo, vidin_rgb_reg_fifo_left, vidin_rgb_reg_fifo_right, vidin_addr_reg_2to0, v_nd_s1_left_2to0, v_nd_s2_left_2to0 , v_nd_s4_left_2to0 , v_d_reg_s1_left_2to0 , v_d_reg_s2_left_2to0 , v_d_reg_s4_left_2to0 , v_nd_s1_right_2to0, v_nd_s2_right_2to0 , v_nd_s4_right_2to0 , v_d_reg_s1_right_2to0 , v_d_reg_s2_right_2to0 , v_d_reg_s4_right_2to0 , tm3_vidout_red,tm3_vidout_green,tm3_vidout_blue , tm3_vidout_clock,tm3_vidout_hsync,tm3_vidout_vsync,tm3_vidout_blank , x_in, y_in, depth_out, offchip_sram_data_in,offchip_sram_addr,offchip_sram_data_out,offchip_sram_we,offchip_sram_oe); + + + input tm3_clk_v0; + input [63:0]offchip_sram_data_in; + output [18:0]offchip_sram_addr; + output [63:0]offchip_sram_data_out; + output [7:0]offchip_sram_we; + output [1:0]offchip_sram_oe; + + wire[63:0] tm3_sram_data_in; + + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + reg[18:0] tm3_sram_addr; + + reg[7:0] tm3_sram_we; + + reg[1:0] tm3_sram_oe; + + reg tm3_sram_adsp; + input[7:0] bus_word_1_1to0; + input[7:0] bus_word_2_1to0; + input[7:0] bus_word_3_1to0; + input[7:0] bus_word_4_1to0; + input[7:0] bus_word_5_1to0; + input[7:0] bus_word_6_1to0; + input[2:0] counter_out_1to0; + input vidin_new_data_fifo; + input[7:0] vidin_rgb_reg_fifo_left; + input[7:0] vidin_rgb_reg_fifo_right; + input[3:0] vidin_addr_reg_2to0; + output v_nd_s1_left_2to0; + reg v_nd_s1_left_2to0; + output v_nd_s2_left_2to0; + reg v_nd_s2_left_2to0; + output v_nd_s4_left_2to0; + reg v_nd_s4_left_2to0; + output[7:0] v_d_reg_s1_left_2to0; + reg[7:0] v_d_reg_s1_left_2to0; + output[7:0] v_d_reg_s2_left_2to0; + reg[7:0] v_d_reg_s2_left_2to0; + output[7:0] v_d_reg_s4_left_2to0; + reg[7:0] v_d_reg_s4_left_2to0; + output v_nd_s1_right_2to0; + reg v_nd_s1_right_2to0; + output v_nd_s2_right_2to0; + reg v_nd_s2_right_2to0; + output v_nd_s4_right_2to0; + reg v_nd_s4_right_2to0; + output[7:0] v_d_reg_s1_right_2to0; + reg[7:0] v_d_reg_s1_right_2to0; + output[7:0] v_d_reg_s2_right_2to0; + reg[7:0] v_d_reg_s2_right_2to0; + output[7:0] v_d_reg_s4_right_2to0; + reg[7:0] v_d_reg_s4_right_2to0; + output[9:0] tm3_vidout_red; + reg[9:0] tm3_vidout_red; + output[9:0] tm3_vidout_green; + reg[9:0] tm3_vidout_green; + output[9:0] tm3_vidout_blue; + reg[9:0] tm3_vidout_blue; + output tm3_vidout_clock; + wire tm3_vidout_clock; + output tm3_vidout_hsync; + reg tm3_vidout_hsync; + output tm3_vidout_vsync; + reg tm3_vidout_vsync; + output tm3_vidout_blank; + reg tm3_vidout_blank; + input[15:0] x_in; + input[15:0] y_in; + output[15:0] depth_out; + reg[15:0] depth_out; + reg[15:0] x_reg_l; + reg[15:0] x_reg_r; + reg[15:0] y_reg_up; + reg[15:0] y_reg_dn; + reg[7:0] depth_out_reg; + reg[9:0] horiz; + reg[9:0] vert; + reg[63:0] vidin_data_buf_sc_1; + reg[55:0] vidin_data_buf_2_sc_1; + reg[18:0] vidin_addr_buf_sc_1; + reg[63:0] vidout_buf; + reg[63:0] vidin_data_buf_sc_2; + reg[55:0] vidin_data_buf_2_sc_2; + reg[18:0] vidin_addr_buf_sc_2; + reg[63:0] vidin_data_buf_sc_4; + reg[55:0] vidin_data_buf_2_sc_4; + reg[18:0] vidin_addr_buf_sc_4; + reg video_state; + reg vidin_new_data_scld_1_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_right_reg; + reg vidin_new_data_scld_2_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_right_reg; + reg vidin_new_data_scld_4_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_right_reg; + reg[18:0] vidin_addr_reg_2to3_reg; + wire[18:0] vidin_addr_reg; + wire svid_comp_switch_2to3; + wire vidin_new_data_scld_1_1to0; + wire vidin_new_data_scld_2_1to0; + wire vidin_new_data_scld_4_1to0; + wire[7:0] v_corr_200; + wire[7:0] v_corr_201; + wire[7:0] v_corr_202; + wire[7:0] v_corr_203; + wire[7:0] v_corr_204; + wire[7:0] v_corr_205; + wire[7:0] v_corr_206; + wire[7:0] v_corr_207; + wire[7:0] v_corr_208; + wire[7:0] v_corr_209; + wire[7:0] v_corr_2010; + wire[7:0] v_corr_2011; + wire[7:0] v_corr_2012; + wire[7:0] v_corr_2013; + wire[7:0] v_corr_2014; + wire[7:0] v_corr_2015; + wire[7:0] v_corr_2016; + wire[7:0] v_corr_2017; + wire[7:0] v_corr_2018; + wire[7:0] v_corr_2019; + wire[7:0] v_corr_2020; + wire[7:0] v_corr_100; + wire[7:0] v_corr_101; + wire[7:0] v_corr_102; + wire[7:0] v_corr_103; + wire[7:0] v_corr_104; + wire[7:0] v_corr_105; + wire[7:0] v_corr_106; + wire[7:0] v_corr_107; + wire[7:0] v_corr_108; + wire[7:0] v_corr_109; + wire[7:0] v_corr_1010; + wire[7:0] v_corr_50; + wire[7:0] v_corr_51; + wire[7:0] v_corr_52; + wire[7:0] v_corr_53; + wire[7:0] v_corr_54; + wire[7:0] v_corr_55; + wire[7:0] v_corr_20_fltr0; + wire[7:0] v_corr_20_fltr1; + wire[7:0] v_corr_20_fltr2; + wire[7:0] v_corr_20_fltr3; + wire[7:0] v_corr_20_fltr4; + wire[7:0] v_corr_20_fltr5; + wire[7:0] v_corr_20_fltr6; + wire[7:0] v_corr_20_fltr7; + wire[7:0] v_corr_20_fltr8; + wire[7:0] v_corr_20_fltr9; + wire[7:0] v_corr_20_fltr10; + wire[7:0] v_corr_20_fltr11; + wire[7:0] v_corr_20_fltr12; + wire[7:0] v_corr_20_fltr13; + wire[7:0] v_corr_20_fltr14; + wire[7:0] v_corr_20_fltr15; + wire[7:0] v_corr_20_fltr16; + wire[7:0] v_corr_20_fltr17; + wire[7:0] v_corr_20_fltr18; + wire[7:0] v_corr_20_fltr19; + wire[7:0] v_corr_20_fltr20; + wire[7:0] v_corr_10_fltr0; + wire[7:0] v_corr_10_fltr1; + wire[7:0] v_corr_10_fltr2; + wire[7:0] v_corr_10_fltr3; + wire[7:0] v_corr_10_fltr4; + wire[7:0] v_corr_10_fltr5; + wire[7:0] v_corr_10_fltr6; + wire[7:0] v_corr_10_fltr7; + wire[7:0] v_corr_10_fltr8; + wire[7:0] v_corr_10_fltr9; + wire[7:0] v_corr_10_fltr10; + wire[7:0] v_corr_5_fltr0; + wire[7:0] v_corr_5_fltr1; + wire[7:0] v_corr_5_fltr2; + wire[7:0] v_corr_5_fltr3; + wire[7:0] v_corr_5_fltr4; + wire[7:0] v_corr_5_fltr5; + wire[7:0] v_corr_20_fltr_x0; + wire[7:0] v_corr_20_fltr_x1; + wire[7:0] v_corr_20_fltr_x2; + wire[7:0] v_corr_20_fltr_x3; + wire[7:0] v_corr_20_fltr_x4; + wire[7:0] v_corr_20_fltr_x5; + wire[7:0] v_corr_20_fltr_x6; + wire[7:0] v_corr_20_fltr_x7; + wire[7:0] v_corr_20_fltr_x8; + wire[7:0] v_corr_20_fltr_x9; + wire[7:0] v_corr_20_fltr_x10; + wire[7:0] v_corr_20_fltr_x11; + wire[7:0] v_corr_20_fltr_x12; + wire[7:0] v_corr_20_fltr_x13; + wire[7:0] v_corr_20_fltr_x14; + wire[7:0] v_corr_20_fltr_x15; + wire[7:0] v_corr_20_fltr_x16; + wire[7:0] v_corr_20_fltr_x17; + wire[7:0] v_corr_20_fltr_x18; + wire[7:0] v_corr_20_fltr_x19; + wire[7:0] v_corr_20_fltr_x20; + wire[7:0] v_corr_10_fltr_x0; + wire[7:0] v_corr_10_fltr_x1; + wire[7:0] v_corr_10_fltr_x2; + wire[7:0] v_corr_10_fltr_x3; + wire[7:0] v_corr_10_fltr_x4; + wire[7:0] v_corr_10_fltr_x5; + wire[7:0] v_corr_10_fltr_x6; + wire[7:0] v_corr_10_fltr_x7; + wire[7:0] v_corr_10_fltr_x8; + wire[7:0] v_corr_10_fltr_x9; + wire[7:0] v_corr_10_fltr_x10; + wire[7:0] v_corr_5_fltr_x0; + wire[7:0] v_corr_5_fltr_x1; + wire[7:0] v_corr_5_fltr_x2; + wire[7:0] v_corr_5_fltr_x3; + wire[7:0] v_corr_5_fltr_x4; + wire[7:0] v_corr_5_fltr_x5; + wire[7:0] v_corr_20_fltr_h0; + wire[7:0] v_corr_20_fltr_h1; + wire[7:0] v_corr_20_fltr_h2; + wire[7:0] v_corr_20_fltr_h3; + wire[7:0] v_corr_20_fltr_h4; + wire[7:0] v_corr_20_fltr_h5; + wire[7:0] v_corr_20_fltr_h6; + wire[7:0] v_corr_20_fltr_h7; + wire[7:0] v_corr_20_fltr_h8; + wire[7:0] v_corr_20_fltr_h9; + wire[7:0] v_corr_20_fltr_h10; + wire[7:0] v_corr_20_fltr_h11; + wire[7:0] v_corr_20_fltr_h12; + wire[7:0] v_corr_20_fltr_h13; + wire[7:0] v_corr_20_fltr_h14; + wire[7:0] v_corr_20_fltr_h15; + wire[7:0] v_corr_20_fltr_h16; + wire[7:0] v_corr_20_fltr_h17; + wire[7:0] v_corr_20_fltr_h18; + wire[7:0] v_corr_20_fltr_h19; + wire[7:0] v_corr_20_fltr_h20; + wire[7:0] v_corr_10_fltr_h0; + wire[7:0] v_corr_10_fltr_h1; + wire[7:0] v_corr_10_fltr_h2; + wire[7:0] v_corr_10_fltr_h3; + wire[7:0] v_corr_10_fltr_h4; + wire[7:0] v_corr_10_fltr_h5; + wire[7:0] v_corr_10_fltr_h6; + wire[7:0] v_corr_10_fltr_h7; + wire[7:0] v_corr_10_fltr_h8; + wire[7:0] v_corr_10_fltr_h9; + wire[7:0] v_corr_10_fltr_h10; + wire[7:0] v_corr_5_fltr_h0; + wire[7:0] v_corr_5_fltr_h1; + wire[7:0] v_corr_5_fltr_h2; + wire[7:0] v_corr_5_fltr_h3; + wire[7:0] v_corr_5_fltr_h4; + wire[7:0] v_corr_5_fltr_h5; + wire[7:0] v_corr_20_fifo0; + wire[7:0] v_corr_20_fifo1; + wire[7:0] v_corr_20_fifo2; + wire[7:0] v_corr_20_fifo3; + wire[7:0] v_corr_20_fifo4; + wire[7:0] v_corr_20_fifo5; + wire[7:0] v_corr_20_fifo6; + wire[7:0] v_corr_20_fifo7; + wire[7:0] v_corr_20_fifo8; + wire[7:0] v_corr_20_fifo9; + wire[7:0] v_corr_20_fifo10; + wire[7:0] v_corr_20_fifo11; + wire[7:0] v_corr_20_fifo12; + wire[7:0] v_corr_20_fifo13; + wire[7:0] v_corr_20_fifo14; + wire[7:0] v_corr_20_fifo15; + wire[7:0] v_corr_20_fifo16; + wire[7:0] v_corr_20_fifo17; + wire[7:0] v_corr_20_fifo18; + wire[7:0] v_corr_20_fifo19; + wire[7:0] v_corr_20_fifo20; + wire[8:0] v_corr_10_fifo0; + wire[8:0] v_corr_10_fifo1; + wire[8:0] v_corr_10_fifo2; + wire[8:0] v_corr_10_fifo3; + wire[8:0] v_corr_10_fifo4; + wire[8:0] v_corr_10_fifo5; + wire[8:0] v_corr_10_fifo6; + wire[8:0] v_corr_10_fifo7; + wire[8:0] v_corr_10_fifo8; + wire[8:0] v_corr_10_fifo9; + wire[8:0] v_corr_10_fifo10; + wire[8:0] v_corr_10_fifo11; + wire[8:0] v_corr_10_fifo12; + wire[8:0] v_corr_10_fifo13; + wire[8:0] v_corr_10_fifo14; + wire[8:0] v_corr_10_fifo15; + wire[8:0] v_corr_10_fifo16; + wire[8:0] v_corr_10_fifo17; + wire[8:0] v_corr_10_fifo18; + wire[8:0] v_corr_10_fifo19; + wire[8:0] v_corr_10_fifo20; + wire[7:0] v_corr_20_fifo_x0; + wire[7:0] v_corr_20_fifo_x1; + wire[7:0] v_corr_20_fifo_x2; + wire[7:0] v_corr_20_fifo_x3; + wire[7:0] v_corr_20_fifo_x4; + wire[7:0] v_corr_20_fifo_x5; + wire[7:0] v_corr_20_fifo_x6; + wire[7:0] v_corr_20_fifo_x7; + wire[7:0] v_corr_20_fifo_x8; + wire[7:0] v_corr_20_fifo_x9; + wire[7:0] v_corr_20_fifo_x10; + wire[7:0] v_corr_20_fifo_x11; + wire[7:0] v_corr_20_fifo_x12; + wire[7:0] v_corr_20_fifo_x13; + wire[7:0] v_corr_20_fifo_x14; + wire[7:0] v_corr_20_fifo_x15; + wire[7:0] v_corr_20_fifo_x16; + wire[7:0] v_corr_20_fifo_x17; + wire[7:0] v_corr_20_fifo_x18; + wire[7:0] v_corr_20_fifo_x19; + wire[7:0] v_corr_20_fifo_x20; + wire[8:0] v_corr_10_fifo_x0; + wire[8:0] v_corr_10_fifo_x1; + wire[8:0] v_corr_10_fifo_x2; + wire[8:0] v_corr_10_fifo_x3; + wire[8:0] v_corr_10_fifo_x4; + wire[8:0] v_corr_10_fifo_x5; + wire[8:0] v_corr_10_fifo_x6; + wire[8:0] v_corr_10_fifo_x7; + wire[8:0] v_corr_10_fifo_x8; + wire[8:0] v_corr_10_fifo_x9; + wire[8:0] v_corr_10_fifo_x10; + wire[8:0] v_corr_10_fifo_x11; + wire[8:0] v_corr_10_fifo_x12; + wire[8:0] v_corr_10_fifo_x13; + wire[8:0] v_corr_10_fifo_x14; + wire[8:0] v_corr_10_fifo_x15; + wire[8:0] v_corr_10_fifo_x16; + wire[8:0] v_corr_10_fifo_x17; + wire[8:0] v_corr_10_fifo_x18; + wire[8:0] v_corr_10_fifo_x19; + wire[8:0] v_corr_10_fifo_x20; + wire[15:0] qs_4_out0; + wire[15:0] qs_4_out1; + wire[15:0] qs_4_out2; + wire[15:0] qs_4_out3; + wire[15:0] qs_4_out4; + wire[15:0] qs_4_out5; + wire[15:0] qs_4_out6; + wire[15:0] qs_4_out7; + wire[15:0] qs_4_out8; + wire[15:0] qs_4_out9; + wire[15:0] qs_4_out10; + wire[15:0] qs_4_out11; + wire[15:0] qs_4_out12; + wire[15:0] qs_4_out13; + wire[15:0] qs_4_out14; + wire[15:0] qs_4_out15; + wire[15:0] qs_4_out16; + wire[15:0] qs_4_out17; + wire[15:0] qs_4_out18; + wire[15:0] qs_4_out19; + wire[15:0] qs_4_out20; + wire[15:0] qs_2_out0; + wire[15:0] qs_2_out1; + wire[15:0] qs_2_out2; + wire[15:0] qs_2_out3; + wire[15:0] qs_2_out4; + wire[15:0] qs_2_out5; + wire[15:0] qs_2_out6; + wire[15:0] qs_2_out7; + wire[15:0] qs_2_out8; + wire[15:0] qs_2_out9; + wire[15:0] qs_2_out10; + wire[15:0] qs_2_out11; + wire[15:0] qs_2_out12; + wire[15:0] qs_2_out13; + wire[15:0] qs_2_out14; + wire[15:0] qs_2_out15; + wire[15:0] qs_2_out16; + wire[15:0] qs_2_out17; + wire[15:0] qs_2_out18; + wire[15:0] qs_2_out19; + wire[15:0] qs_2_out20; + wire[15:0] qs_4_out_x0; + wire[15:0] qs_4_out_x1; + wire[15:0] qs_4_out_x2; + wire[15:0] qs_4_out_x3; + wire[15:0] qs_4_out_x4; + wire[15:0] qs_4_out_x5; + wire[15:0] qs_4_out_x6; + wire[15:0] qs_4_out_x7; + wire[15:0] qs_4_out_x8; + wire[15:0] qs_4_out_x9; + wire[15:0] qs_4_out_x10; + wire[15:0] qs_4_out_x11; + wire[15:0] qs_4_out_x12; + wire[15:0] qs_4_out_x13; + wire[15:0] qs_4_out_x14; + wire[15:0] qs_4_out_x15; + wire[15:0] qs_4_out_x16; + wire[15:0] qs_4_out_x17; + wire[15:0] qs_4_out_x18; + wire[15:0] qs_4_out_x19; + wire[15:0] qs_4_out_x20; + wire[15:0] qs_2_out_x0; + wire[15:0] qs_2_out_x1; + wire[15:0] qs_2_out_x2; + wire[15:0] qs_2_out_x3; + wire[15:0] qs_2_out_x4; + wire[15:0] qs_2_out_x5; + wire[15:0] qs_2_out_x6; + wire[15:0] qs_2_out_x7; + wire[15:0] qs_2_out_x8; + wire[15:0] qs_2_out_x9; + wire[15:0] qs_2_out_x10; + wire[15:0] qs_2_out_x11; + wire[15:0] qs_2_out_x12; + wire[15:0] qs_2_out_x13; + wire[15:0] qs_2_out_x14; + wire[15:0] qs_2_out_x15; + wire[15:0] qs_2_out_x16; + wire[15:0] qs_2_out_x17; + wire[15:0] qs_2_out_x18; + wire[15:0] qs_2_out_x19; + wire[15:0] qs_2_out_x20; + wire rdy_4_out; + wire rdy_tmp3; + wire rdy_tmp2; + wire rdy_tmp1; + wire[7:0] max_data_out; + wire[4:0] max_indx_out; + wire v_nd_s1_left_2to0_tmp; + wire v_nd_s2_left_2to0_tmp; + wire v_nd_s4_left_2to0_tmp; + wire[7:0] v_d_reg_s1_left_2to0_tmp; + wire[7:0] v_d_reg_s2_left_2to0_tmp; + wire[7:0] v_d_reg_s4_left_2to0_tmp; + wire[7:0] v_d_reg_s1_left_2to0_fifo_tmp; + wire[7:0] v_d_reg_s2_left_2to0_fifo_tmp; + wire[7:0] v_d_reg_s4_left_2to0_fifo_tmp; + wire v_nd_s1_right_2to0_tmp; + wire v_nd_s2_right_2to0_tmp; + wire v_nd_s4_right_2to0_tmp; + wire[7:0] v_d_reg_s1_right_2to0_tmp; + wire[7:0] v_d_reg_s2_right_2to0_tmp; + wire[7:0] v_d_reg_s4_right_2to0_tmp; + wire[7:0] v_d_reg_s1_right_2to0_fifo_tmp; + wire[7:0] v_d_reg_s2_right_2to0_fifo_tmp; + wire[7:0] v_d_reg_s4_right_2to0_fifo_tmp; + wire[10:0] comb_out0; + wire[10:0] comb_out1; + wire[10:0] comb_out2; + wire[10:0] comb_out3; + wire[10:0] comb_out4; + wire[10:0] comb_out5; + wire[10:0] comb_out6; + wire[10:0] comb_out7; + wire[10:0] comb_out8; + wire[10:0] comb_out9; + wire[10:0] comb_out10; + wire[10:0] comb_out11; + wire[10:0] comb_out12; + wire[10:0] comb_out13; + wire[10:0] comb_out14; + wire[10:0] comb_out15; + wire[10:0] comb_out16; + wire[10:0] comb_out17; + wire[10:0] comb_out18; + wire[10:0] comb_out19; + wire[10:0] comb_out20; + // <> Unsupported Construct - attribute (source line 258) + // <> Unsupported Construct - attribute (source line 259)) + // <> Unsupported Construct - attribute (source line 273) + // <> Unsupported Construct - attribute (source line 274)) + + assign tm3_sram_data_in = offchip_sram_data_in; + assign offchip_sram_addr = tm3_sram_addr; + assign offchip_sram_data_out = tm3_sram_data_out; + assign offchip_sram_we = tm3_sram_we; + assign offchip_sram_oe = tm3_sram_oe; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + scaler scaler_inst_left (tm3_clk_v0, vidin_new_data_fifo, vidin_rgb_reg_fifo_left, vidin_addr_reg_2to0, v_nd_s1_left_2to0_tmp, v_nd_s2_left_2to0_tmp, v_nd_s4_left_2to0_tmp, v_d_reg_s1_left_2to0_tmp, v_d_reg_s2_left_2to0_tmp, v_d_reg_s4_left_2to0_tmp); + scaler scaler_inst_right (tm3_clk_v0, vidin_new_data_fifo, vidin_rgb_reg_fifo_right, vidin_addr_reg_2to0, v_nd_s1_right_2to0_tmp, v_nd_s2_right_2to0_tmp, v_nd_s4_right_2to0_tmp, v_d_reg_s1_right_2to0_tmp, v_d_reg_s2_right_2to0_tmp, v_d_reg_s4_right_2to0_tmp); + v_fltr_496 v_fltr_496_l_inst(tm3_clk_v0, v_nd_s1_left_2to0_tmp, v_d_reg_s1_left_2to0_tmp, v_d_reg_s1_left_2to0_fifo_tmp); + v_fltr_496 v_fltr_496_r_inst(tm3_clk_v0, v_nd_s1_right_2to0_tmp, v_d_reg_s1_right_2to0_tmp, v_d_reg_s1_right_2to0_fifo_tmp); + v_fltr_316 v_fltr_316_l_inst(tm3_clk_v0, v_nd_s2_left_2to0_tmp, v_d_reg_s2_left_2to0_tmp, v_d_reg_s2_left_2to0_fifo_tmp); + v_fltr_316 v_fltr_316_r_inst(tm3_clk_v0, v_nd_s2_right_2to0_tmp, v_d_reg_s2_right_2to0_tmp, v_d_reg_s2_right_2to0_fifo_tmp); + port_bus_1to0_1 port_bus_1to0_1_inst(tm3_clk_v0, vidin_addr_reg, svid_comp_switch_2to3, vidin_new_data_scld_1_1to0, + v_corr_200, v_corr_201, v_corr_202, v_corr_203, v_corr_204, v_corr_205, v_corr_206, v_corr_207, v_corr_208, v_corr_209, v_corr_2010, v_corr_2011, v_corr_2012, v_corr_2013, v_corr_2014, v_corr_2015, v_corr_2016, v_corr_2017, v_corr_2018, v_corr_2019, v_corr_2020, + vidin_new_data_scld_2_1to0, + v_corr_100, v_corr_101, v_corr_102, v_corr_103, v_corr_104, v_corr_105, v_corr_106, v_corr_107, v_corr_108, v_corr_109, v_corr_1010, + vidin_new_data_scld_4_1to0, + v_corr_50, v_corr_51, v_corr_52, v_corr_53, v_corr_54, v_corr_55, + bus_word_1_1to0, bus_word_2_1to0, bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, counter_out_1to0); + + lp_fltr inst_fir_1_0 (tm3_clk_v0, v_corr_200, v_corr_20_fltr_h0, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_1 (tm3_clk_v0, v_corr_201, v_corr_20_fltr_h1, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_2 (tm3_clk_v0, v_corr_202, v_corr_20_fltr_h2, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_3 (tm3_clk_v0, v_corr_203, v_corr_20_fltr_h3, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_4 (tm3_clk_v0, v_corr_204, v_corr_20_fltr_h4, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_5 (tm3_clk_v0, v_corr_205, v_corr_20_fltr_h5, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_6 (tm3_clk_v0, v_corr_206, v_corr_20_fltr_h6, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_7 (tm3_clk_v0, v_corr_207, v_corr_20_fltr_h7, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_8 (tm3_clk_v0, v_corr_208, v_corr_20_fltr_h8, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_9 (tm3_clk_v0, v_corr_209, v_corr_20_fltr_h9, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_10 (tm3_clk_v0, v_corr_2010, v_corr_20_fltr_h10, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_11 (tm3_clk_v0, v_corr_2011, v_corr_20_fltr_h11, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_12 (tm3_clk_v0, v_corr_2012, v_corr_20_fltr_h12, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_13 (tm3_clk_v0, v_corr_2013, v_corr_20_fltr_h13, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_14 (tm3_clk_v0, v_corr_2014, v_corr_20_fltr_h14, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_15 (tm3_clk_v0, v_corr_2015, v_corr_20_fltr_h15, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_16 (tm3_clk_v0, v_corr_2016, v_corr_20_fltr_h16, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_17 (tm3_clk_v0, v_corr_2017, v_corr_20_fltr_h17, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_18 (tm3_clk_v0, v_corr_2018, v_corr_20_fltr_h18, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_19 (tm3_clk_v0, v_corr_2019, v_corr_20_fltr_h19, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_1_20 (tm3_clk_v0, v_corr_2020, v_corr_20_fltr_h20, vidin_new_data_scld_1_1to0); + lp_fltr inst_fir_2_0 (tm3_clk_v0, v_corr_100, v_corr_10_fltr_h0, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_1 (tm3_clk_v0, v_corr_101, v_corr_10_fltr_h1, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_2 (tm3_clk_v0, v_corr_102, v_corr_10_fltr_h2, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_3 (tm3_clk_v0, v_corr_103, v_corr_10_fltr_h3, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_4 (tm3_clk_v0, v_corr_104, v_corr_10_fltr_h4, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_5 (tm3_clk_v0, v_corr_105, v_corr_10_fltr_h5, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_6 (tm3_clk_v0, v_corr_106, v_corr_10_fltr_h6, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_7 (tm3_clk_v0, v_corr_107, v_corr_10_fltr_h7, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_8 (tm3_clk_v0, v_corr_108, v_corr_10_fltr_h8, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_9 (tm3_clk_v0, v_corr_109, v_corr_10_fltr_h9, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_2_10 (tm3_clk_v0, v_corr_1010, v_corr_10_fltr_h10, vidin_new_data_scld_2_1to0); + lp_fltr inst_fir_4_0 (tm3_clk_v0, v_corr_50, v_corr_5_fltr_h0, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_1 (tm3_clk_v0, v_corr_51, v_corr_5_fltr_h1, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_2 (tm3_clk_v0, v_corr_52, v_corr_5_fltr_h2, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_3 (tm3_clk_v0, v_corr_53, v_corr_5_fltr_h3, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_4 (tm3_clk_v0, v_corr_54, v_corr_5_fltr_h4, vidin_new_data_scld_4_1to0); + lp_fltr inst_fir_4_5 (tm3_clk_v0, v_corr_55, v_corr_5_fltr_h5, vidin_new_data_scld_4_1to0); + lp_fltr_v1 inst_fir_v1_0 (tm3_clk_v0, v_corr_20_fltr_h0, v_corr_20_fltr_x0, v_corr_20_fltr0, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_1 (tm3_clk_v0, v_corr_20_fltr_h1, v_corr_20_fltr_x1, v_corr_20_fltr1, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_2 (tm3_clk_v0, v_corr_20_fltr_h2, v_corr_20_fltr_x2, v_corr_20_fltr2, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_3 (tm3_clk_v0, v_corr_20_fltr_h3, v_corr_20_fltr_x3, v_corr_20_fltr3, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_4 (tm3_clk_v0, v_corr_20_fltr_h4, v_corr_20_fltr_x4, v_corr_20_fltr4, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_5 (tm3_clk_v0, v_corr_20_fltr_h5, v_corr_20_fltr_x5, v_corr_20_fltr5, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_6 (tm3_clk_v0, v_corr_20_fltr_h6, v_corr_20_fltr_x6, v_corr_20_fltr6, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_7 (tm3_clk_v0, v_corr_20_fltr_h7, v_corr_20_fltr_x7, v_corr_20_fltr7, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_8 (tm3_clk_v0, v_corr_20_fltr_h8, v_corr_20_fltr_x8, v_corr_20_fltr8, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_9 (tm3_clk_v0, v_corr_20_fltr_h9, v_corr_20_fltr_x9, v_corr_20_fltr9, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_10 (tm3_clk_v0, v_corr_20_fltr_h10, v_corr_20_fltr_x10, v_corr_20_fltr10, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_11 (tm3_clk_v0, v_corr_20_fltr_h11, v_corr_20_fltr_x11, v_corr_20_fltr11, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_12 (tm3_clk_v0, v_corr_20_fltr_h12, v_corr_20_fltr_x12, v_corr_20_fltr12, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_13 (tm3_clk_v0, v_corr_20_fltr_h13, v_corr_20_fltr_x13, v_corr_20_fltr13, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_14 (tm3_clk_v0, v_corr_20_fltr_h14, v_corr_20_fltr_x14, v_corr_20_fltr14, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_15 (tm3_clk_v0, v_corr_20_fltr_h15, v_corr_20_fltr_x15, v_corr_20_fltr15, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_16 (tm3_clk_v0, v_corr_20_fltr_h16, v_corr_20_fltr_x16, v_corr_20_fltr16, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_17 (tm3_clk_v0, v_corr_20_fltr_h17, v_corr_20_fltr_x17, v_corr_20_fltr17, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_18 (tm3_clk_v0, v_corr_20_fltr_h18, v_corr_20_fltr_x18, v_corr_20_fltr18, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_19 (tm3_clk_v0, v_corr_20_fltr_h19, v_corr_20_fltr_x19, v_corr_20_fltr19, vidin_new_data_scld_1_1to0); + lp_fltr_v1 inst_fir_v1_20 (tm3_clk_v0, v_corr_20_fltr_h20, v_corr_20_fltr_x20, v_corr_20_fltr20, vidin_new_data_scld_1_1to0); + lp_fltr_v2 inst_fir_v2_0 (tm3_clk_v0, v_corr_10_fltr_h0, v_corr_10_fltr_x0, v_corr_10_fltr0, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_1 (tm3_clk_v0, v_corr_10_fltr_h1, v_corr_10_fltr_x1, v_corr_10_fltr1, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_2 (tm3_clk_v0, v_corr_10_fltr_h2, v_corr_10_fltr_x2, v_corr_10_fltr2, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_3 (tm3_clk_v0, v_corr_10_fltr_h3, v_corr_10_fltr_x3, v_corr_10_fltr3, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_4 (tm3_clk_v0, v_corr_10_fltr_h4, v_corr_10_fltr_x4, v_corr_10_fltr4, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_5 (tm3_clk_v0, v_corr_10_fltr_h5, v_corr_10_fltr_x5, v_corr_10_fltr5, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_6 (tm3_clk_v0, v_corr_10_fltr_h6, v_corr_10_fltr_x6, v_corr_10_fltr6, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_7 (tm3_clk_v0, v_corr_10_fltr_h7, v_corr_10_fltr_x7, v_corr_10_fltr7, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_8 (tm3_clk_v0, v_corr_10_fltr_h8, v_corr_10_fltr_x8, v_corr_10_fltr8, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_9 (tm3_clk_v0, v_corr_10_fltr_h9, v_corr_10_fltr_x9, v_corr_10_fltr9, vidin_new_data_scld_2_1to0); + lp_fltr_v2 inst_fir_v2_10 (tm3_clk_v0, v_corr_10_fltr_h10, v_corr_10_fltr_x10, v_corr_10_fltr10, vidin_new_data_scld_2_1to0); + lp_fltr_v4 inst_fir_v4_0 (tm3_clk_v0, v_corr_5_fltr_h0, v_corr_5_fltr_x0, v_corr_5_fltr0, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_1 (tm3_clk_v0, v_corr_5_fltr_h1, v_corr_5_fltr_x1, v_corr_5_fltr1, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_2 (tm3_clk_v0, v_corr_5_fltr_h2, v_corr_5_fltr_x2, v_corr_5_fltr2, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_3 (tm3_clk_v0, v_corr_5_fltr_h3, v_corr_5_fltr_x3, v_corr_5_fltr3, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_4 (tm3_clk_v0, v_corr_5_fltr_h4, v_corr_5_fltr_x4, v_corr_5_fltr4, vidin_new_data_scld_4_1to0); + lp_fltr_v4 inst_fir_v4_5 (tm3_clk_v0, v_corr_5_fltr_h5, v_corr_5_fltr_x5, v_corr_5_fltr5, vidin_new_data_scld_4_1to0); + + wrapper_qs_intr_5_20 wrapper_qs_intr_inst_5 (tm3_clk_v0, + v_corr_5_fltr0, + v_corr_5_fltr1, + v_corr_5_fltr2, + v_corr_5_fltr3, + v_corr_5_fltr4, + v_corr_5_fltr5, + vidin_new_data_scld_4_1to0, vidin_addr_reg, + qs_4_out0, + qs_4_out1, + qs_4_out2, + qs_4_out3, + qs_4_out4, + qs_4_out5, + qs_4_out6, + qs_4_out7, + qs_4_out8, + qs_4_out9, + qs_4_out10, + qs_4_out11, + qs_4_out12, + qs_4_out13, + qs_4_out14, + qs_4_out15, + qs_4_out16, + qs_4_out17, + qs_4_out18, + qs_4_out19, + qs_4_out20, + rdy_4_out); + wrapper_qs_intr_10_20 wrapper_qs_intr_inst_10 (tm3_clk_v0, + v_corr_10_fltr0, + v_corr_10_fltr1, + v_corr_10_fltr2, + v_corr_10_fltr3, + v_corr_10_fltr4, + v_corr_10_fltr5, + v_corr_10_fltr6, + v_corr_10_fltr7, + v_corr_10_fltr8, + v_corr_10_fltr9, + v_corr_10_fltr10, + vidin_new_data_scld_2_1to0, vidin_addr_reg, + qs_2_out0, + qs_2_out1, + qs_2_out2, + qs_2_out3, + qs_2_out4, + qs_2_out5, + qs_2_out6, + qs_2_out7, + qs_2_out8, + qs_2_out9, + qs_2_out10, + qs_2_out11, + qs_2_out12, + qs_2_out13, + qs_2_out14, + qs_2_out15, + qs_2_out16, + qs_2_out17, + qs_2_out18, + qs_2_out19, + qs_2_out20, + rdy_tmp3); + wrapper_qs_intr_5_20 wrapper_qs_intr_inst_5_more (tm3_clk_v0, + v_corr_5_fltr_x0, + v_corr_5_fltr_x1, + v_corr_5_fltr_x2, + v_corr_5_fltr_x3, + v_corr_5_fltr_x4, + v_corr_5_fltr_x5, + vidin_new_data_scld_4_1to0, vidin_addr_reg, + qs_4_out_x0, + qs_4_out_x1, + qs_4_out_x2, + qs_4_out_x3, + qs_4_out_x4, + qs_4_out_x5, + qs_4_out_x6, + qs_4_out_x7, + qs_4_out_x8, + qs_4_out_x9, + qs_4_out_x10, + qs_4_out_x11, + qs_4_out_x12, + qs_4_out_x13, + qs_4_out_x14, + qs_4_out_x15, + qs_4_out_x16, + qs_4_out_x17, + qs_4_out_x18, + qs_4_out_x19, + qs_4_out_x20, + rdy_tmp2); + wrapper_qs_intr_10_20 wrapper_qs_intr_inst_10_more (tm3_clk_v0, + v_corr_10_fltr_x0, + v_corr_10_fltr_x1, + v_corr_10_fltr_x2, + v_corr_10_fltr_x3, + v_corr_10_fltr_x4, + v_corr_10_fltr_x5, + v_corr_10_fltr_x6, + v_corr_10_fltr_x7, + v_corr_10_fltr_x8, + v_corr_10_fltr_x9, + v_corr_10_fltr_x10, + vidin_new_data_scld_2_1to0, vidin_addr_reg, + qs_2_out_x0, + qs_2_out_x1, + qs_2_out_x2, + qs_2_out_x3, + qs_2_out_x4, + qs_2_out_x5, + qs_2_out_x6, + qs_2_out_x7, + qs_2_out_x8, + qs_2_out_x9, + qs_2_out_x10, + qs_2_out_x11, + qs_2_out_x12, + qs_2_out_x13, + qs_2_out_x14, + qs_2_out_x15, + qs_2_out_x16, + qs_2_out_x17, + qs_2_out_x18, + qs_2_out_x19, + qs_2_out_x20, + rdy_tmp1); + + my_fifo_1 ints_fifo_1_gen_1_0 (tm3_clk_v0, v_corr_20_fltr0, v_corr_20_fifo0, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_1 (tm3_clk_v0, v_corr_20_fltr1, v_corr_20_fifo1, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_2 (tm3_clk_v0, v_corr_20_fltr2, v_corr_20_fifo2, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_3 (tm3_clk_v0, v_corr_20_fltr3, v_corr_20_fifo3, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_4 (tm3_clk_v0, v_corr_20_fltr4, v_corr_20_fifo4, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_5 (tm3_clk_v0, v_corr_20_fltr5, v_corr_20_fifo5, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_6 (tm3_clk_v0, v_corr_20_fltr6, v_corr_20_fifo6, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_7 (tm3_clk_v0, v_corr_20_fltr7, v_corr_20_fifo7, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_8 (tm3_clk_v0, v_corr_20_fltr8, v_corr_20_fifo8, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_9 (tm3_clk_v0, v_corr_20_fltr9, v_corr_20_fifo9, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_10 (tm3_clk_v0, v_corr_20_fltr10, v_corr_20_fifo10, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_11 (tm3_clk_v0, v_corr_20_fltr11, v_corr_20_fifo11, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_12 (tm3_clk_v0, v_corr_20_fltr12, v_corr_20_fifo12, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_13 (tm3_clk_v0, v_corr_20_fltr13, v_corr_20_fifo13, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_14 (tm3_clk_v0, v_corr_20_fltr14, v_corr_20_fifo14, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_15 (tm3_clk_v0, v_corr_20_fltr15, v_corr_20_fifo15, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_16 (tm3_clk_v0, v_corr_20_fltr16, v_corr_20_fifo16, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_17 (tm3_clk_v0, v_corr_20_fltr17, v_corr_20_fifo17, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_18 (tm3_clk_v0, v_corr_20_fltr18, v_corr_20_fifo18, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_19 (tm3_clk_v0, v_corr_20_fltr19, v_corr_20_fifo19, rdy_4_out); + my_fifo_1 ints_fifo_1_gen_1_20 (tm3_clk_v0, v_corr_20_fltr20, v_corr_20_fifo20, rdy_4_out); + // <> Can't find translated component 'my_fifo_2'. Module name may not match + my_fifo_2 ints_fifo_2_gen_1_0 (tm3_clk_v0, qs_2_out0[8:0], v_corr_10_fifo0, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_1 (tm3_clk_v0, qs_2_out1[8:0], v_corr_10_fifo1, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_2 (tm3_clk_v0, qs_2_out2[8:0], v_corr_10_fifo2, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_3 (tm3_clk_v0, qs_2_out3[8:0], v_corr_10_fifo3, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_4 (tm3_clk_v0, qs_2_out4[8:0], v_corr_10_fifo4, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_5 (tm3_clk_v0, qs_2_out5[8:0], v_corr_10_fifo5, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_6 (tm3_clk_v0, qs_2_out6[8:0], v_corr_10_fifo6, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_7 (tm3_clk_v0, qs_2_out7[8:0], v_corr_10_fifo7, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_8 (tm3_clk_v0, qs_2_out8[8:0], v_corr_10_fifo8, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_9 (tm3_clk_v0, qs_2_out9[8:0], v_corr_10_fifo9, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_10 (tm3_clk_v0, qs_2_out10[8:0], v_corr_10_fifo10, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_11 (tm3_clk_v0, qs_2_out11[8:0], v_corr_10_fifo11, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_12 (tm3_clk_v0, qs_2_out12[8:0], v_corr_10_fifo12, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_13 (tm3_clk_v0, qs_2_out13[8:0], v_corr_10_fifo13, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_14 (tm3_clk_v0, qs_2_out14[8:0], v_corr_10_fifo14, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_15 (tm3_clk_v0, qs_2_out15[8:0], v_corr_10_fifo15, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_16 (tm3_clk_v0, qs_2_out16[8:0], v_corr_10_fifo16, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_17 (tm3_clk_v0, qs_2_out17[8:0], v_corr_10_fifo17, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_18 (tm3_clk_v0, qs_2_out18[8:0], v_corr_10_fifo18, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_19 (tm3_clk_v0, qs_2_out19[8:0], v_corr_10_fifo19, rdy_4_out); + my_fifo_2 ints_fifo_2_gen_1_20 (tm3_clk_v0, qs_2_out20[8:0], v_corr_10_fifo20, rdy_4_out); + combine_res combine_res_inst_0 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo0, v_corr_10_fifo0, qs_4_out0[8:0], comb_out0); + combine_res combine_res_inst_1 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo1, v_corr_10_fifo1, qs_4_out0[8:0], comb_out1); + combine_res combine_res_inst_2 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo2, v_corr_10_fifo2, qs_4_out0[8:0], comb_out2); + combine_res combine_res_inst_3 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo3, v_corr_10_fifo3, qs_4_out0[8:0], comb_out3); + combine_res combine_res_inst_4 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo4, v_corr_10_fifo4, qs_4_out0[8:0], comb_out4); + combine_res combine_res_inst_5 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo5, v_corr_10_fifo5, qs_4_out0[8:0], comb_out5); + combine_res combine_res_inst_6 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo6, v_corr_10_fifo6, qs_4_out0[8:0], comb_out6); + combine_res combine_res_inst_7 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo7, v_corr_10_fifo7, qs_4_out0[8:0], comb_out7); + combine_res combine_res_inst_8 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo8, v_corr_10_fifo8, qs_4_out0[8:0], comb_out8); + combine_res combine_res_inst_9 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo9, v_corr_10_fifo9, qs_4_out0[8:0], comb_out9); + combine_res combine_res_inst_10 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo10, v_corr_10_fifo10, qs_4_out0[8:0], comb_out10); + combine_res combine_res_inst_11 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo11, v_corr_10_fifo11, qs_4_out0[8:0], comb_out11); + combine_res combine_res_inst_12 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo12, v_corr_10_fifo12, qs_4_out0[8:0], comb_out12); + combine_res combine_res_inst_13 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo13, v_corr_10_fifo13, qs_4_out0[8:0], comb_out13); + combine_res combine_res_inst_14 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo14, v_corr_10_fifo14, qs_4_out0[8:0], comb_out14); + combine_res combine_res_inst_15 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo15, v_corr_10_fifo15, qs_4_out0[8:0], comb_out15); + combine_res combine_res_inst_16 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo16, v_corr_10_fifo16, qs_4_out0[8:0], comb_out16); + combine_res combine_res_inst_17 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo17, v_corr_10_fifo17, qs_4_out0[8:0], comb_out17); + combine_res combine_res_inst_18 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo18, v_corr_10_fifo18, qs_4_out0[8:0], comb_out18); + combine_res combine_res_inst_19 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo19, v_corr_10_fifo19, qs_4_out0[8:0], comb_out19); + combine_res combine_res_inst_20 (tm3_clk_v0, rdy_4_out, v_corr_20_fifo20, v_corr_10_fifo20, qs_4_out0[8:0], comb_out20); + find_max find_max_inst (tm3_clk_v0, rdy_4_out, comb_out0, comb_out1, comb_out2, comb_out3, comb_out4, comb_out5, comb_out6, comb_out7, comb_out8, comb_out9, comb_out10, comb_out11, comb_out12, comb_out13, comb_out14, comb_out15, comb_out16, comb_out17, comb_out18, comb_out19, comb_out20, max_data_out, max_indx_out); + + always @(posedge tm3_clk_v0) + begin + vidin_new_data_scld_1_2to3_left_reg <= rdy_4_out ; + vidin_new_data_scld_2_2to3_left_reg <= rdy_4_out ; + vidin_new_data_scld_4_2to3_left_reg <= rdy_4_out ; + vidin_data_reg_scld_1_2to3_left_reg <= v_corr_20_fifo0 ; + + vidin_data_reg_scld_1_2to3_right_reg <= v_corr_10_fifo0[8:1] ; + vidin_data_reg_scld_2_2to3_left_reg <= qs_4_out0[8:1] ; + vidin_data_reg_scld_2_2to3_right_reg <= comb_out0[8:1] ; + vidin_data_reg_scld_4_2to3_left_reg <= comb_out4[8:1] ; + vidin_data_reg_scld_4_2to3_right_reg <= {max_indx_out, 3'b000} ; + if (vidin_addr_reg[8:0] >= 9'b001001000) + begin + vidin_addr_reg_2to3_reg <= vidin_addr_reg - 19'b0000000000001001000 ; + end + else + begin + vidin_addr_reg_2to3_reg <= vidin_addr_reg + 19'b0000000000100100000 ; + end + end + + always @(posedge tm3_clk_v0) + begin + v_nd_s1_left_2to0 <= v_nd_s1_left_2to0_tmp ; + v_nd_s2_left_2to0 <= v_nd_s2_left_2to0_tmp ; + v_nd_s4_left_2to0 <= v_nd_s4_left_2to0_tmp ; + v_nd_s1_right_2to0 <= v_nd_s1_right_2to0_tmp ; + v_nd_s2_right_2to0 <= v_nd_s2_right_2to0_tmp ; + v_nd_s4_right_2to0 <= v_nd_s4_right_2to0_tmp ; + if (v_nd_s1_left_2to0_tmp == 1'b1) + begin + v_d_reg_s1_left_2to0 <= v_d_reg_s1_left_2to0_fifo_tmp ; + v_d_reg_s1_right_2to0 <= v_d_reg_s1_right_2to0_fifo_tmp ; + end + if (v_nd_s2_left_2to0_tmp == 1'b1) + begin + v_d_reg_s2_left_2to0 <= v_d_reg_s2_left_2to0_fifo_tmp ; + v_d_reg_s2_right_2to0 <= v_d_reg_s2_right_2to0_fifo_tmp ; + end + if (v_nd_s4_left_2to0_tmp == 1'b1) + begin + v_d_reg_s4_left_2to0 <= v_d_reg_s4_left_2to0_tmp ; + v_d_reg_s4_right_2to0 <= v_d_reg_s4_right_2to0_tmp ; + end + end + assign tm3_vidout_clock = ~(video_state) ; + + always @(posedge tm3_clk_v0) + begin + x_reg_l <= x_in ; + y_reg_up <= y_in ; + x_reg_r <= x_in + 8 ; + y_reg_dn <= y_in + 8 ; + depth_out <= {8'b00000000, depth_out_reg} ; + video_state <= ~(video_state) ; + if (video_state == 1'b0) + begin + if (horiz == 800) + begin + horiz <= 10'b0000000000 ; + if (vert == 525) + begin + vert <= 10'b0000000000 ; + end + else + begin + vert <= vert + 1 ; + end + end + else + begin + horiz <= horiz + 1 ; + end + if ((vert >= 491) & (vert <= 493)) + begin + tm3_vidout_vsync <= 1'b1 ; + end + else + begin + tm3_vidout_vsync <= 1'b0 ; + end + if ((horiz >= 664) & (horiz <= 760)) + begin + tm3_vidout_hsync <= 1'b1 ; + end + else + begin + tm3_vidout_hsync <= 1'b0 ; + end + if ((horiz < 640) & (vert < 480)) + begin + tm3_vidout_blank <= 1'b1 ; + end + else + begin + tm3_vidout_blank <= 1'b0 ; + end + tm3_sram_adsp <= 1'b1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_data_xhdl0 <= 0; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[15:8] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[15:8], 2'b00} ; + tm3_vidout_green <= {vidout_buf[15:8], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[15:8], 2'b00} ; + end + end + 3'b001 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[23:16] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[23:16], 2'b00} ; + tm3_vidout_green <= {vidout_buf[23:16], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[23:16], 2'b00} ; + end + end + 3'b010 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[31:24] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[31:24], 2'b00} ; + tm3_vidout_green <= {vidout_buf[31:24], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[31:24], 2'b00} ; + end + end + 3'b011 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[39:32] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[39:32], 2'b00} ; + tm3_vidout_green <= {vidout_buf[39:32], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[39:32], 2'b00} ; + end + end + 3'b100 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[47:40] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[47:40], 2'b00} ; + tm3_vidout_green <= {vidout_buf[47:40], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[47:40], 2'b00} ; + end + end + 3'b101 : + begin + tm3_sram_oe <= 2'b10 ; + + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[55:48] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[55:48], 2'b00} ; + tm3_vidout_green <= {vidout_buf[55:48], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[55:48], 2'b00} ; + end + end + 3'b110 : + begin + tm3_sram_oe <= 2'b10 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[63:56] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[63:56], 2'b00} ; + tm3_vidout_green <= {vidout_buf[63:56], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[63:56], 2'b00} ; + end + end + 3'b111 : + begin + tm3_sram_oe <= 2'b11 ; + if ((horiz <= x_reg_r) & (horiz >= x_reg_l) & (vert <= y_reg_dn) & (vert >= y_reg_up)) + begin + tm3_vidout_red <= 10'b1111111111 ; + tm3_vidout_green <= 10'b0000000000 ; + tm3_vidout_blue <= 10'b0000000000 ; + depth_out_reg <= vidout_buf[7:0] ; + end + else + begin + tm3_vidout_red <= {vidout_buf[7:0], 2'b00} ; + tm3_vidout_green <= {vidout_buf[7:0], 2'b00} ; + tm3_vidout_blue <= {vidout_buf[7:0], 2'b00} ; + end + end + endcase + end + else + begin + tm3_sram_adsp <= 1'b0 ; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_2 ; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_2 ; + end + 3'b100 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_4 ; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_4 ; + + end + 3'b110 : + begin + tm3_sram_addr <= {5'b00101, vert[7:0], horiz[8:3]} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b111 : + begin + vidout_buf <= tm3_sram_data_in ; + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + default : + begin + tm3_sram_addr <= 19'b0000000000000000000 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0 ; + end + endcase + end + if (vidin_new_data_scld_1_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[2:0]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_left_reg ; + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_left_reg ; + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_left_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_left_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_left_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_2 <= {4'b0001, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_4 <= {4'b0010, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_right_reg ; + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_right_reg ; + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_right_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_right_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_right_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_2 <= {4'b0001, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + vidin_addr_buf_sc_4 <= {4'b0010, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + endcase + end + end +endmodule +module combine_res (clk, wen, din_1, din_2, din_3, dout); + + input clk; + input wen; + input[7:0] din_1; + input[8:0] din_2; + input[8:0] din_3; + output[10:0] dout; + reg[10:0] dout; + reg[8:0] din_1_reg; + reg[8:0] din_2_reg; + reg[8:0] din_3_reg; + reg[10:0] add_tmp; + reg[10:0] dout_reg; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + din_1_reg <= {din_1[7], din_1} ; + din_2_reg <= din_2 ; + din_3_reg <= din_3 ; + dout <= dout_reg ; + end + add_tmp <= ({din_1_reg[8], din_1_reg[8], din_1_reg}) + ({din_2_reg[8], din_2_reg[8], din_2_reg}) ; + dout_reg <= add_tmp + ({din_3_reg[8], din_3_reg[8], din_3_reg}) ; + end + endmodule +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.22 ,2001 +// By: Ahmad darabiha +module v_fltr_496 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out); + + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[7:0] vidin_out; + wire[7:0] vidin_out; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + wire[7:0] buff_out8; + wire[7:0] buff_out9; + wire[7:0] buff_out10; + wire[7:0] buff_out11; + + assign buff_out0 = vidin_in ; + + my_fifo_496 fifo0(tm3_clk_v0, buff_out0, buff_out1, vidin_new_data); + my_fifo_496 fifo1(tm3_clk_v0, buff_out1, buff_out2, vidin_new_data); + my_fifo_496 fifo2(tm3_clk_v0, buff_out2, buff_out3, vidin_new_data); + my_fifo_496 fifo3(tm3_clk_v0, buff_out3, buff_out4, vidin_new_data); + my_fifo_496 fifo4(tm3_clk_v0, buff_out4, buff_out5, vidin_new_data); + my_fifo_496 fifo5(tm3_clk_v0, buff_out5, buff_out6, vidin_new_data); + my_fifo_496 fifo6(tm3_clk_v0, buff_out6, buff_out7, vidin_new_data); + my_fifo_496 fifo7(tm3_clk_v0, buff_out7, buff_out8, vidin_new_data); + my_fifo_496 fifo8(tm3_clk_v0, buff_out8, buff_out9, vidin_new_data); + my_fifo_496 fifo9(tm3_clk_v0, buff_out9, buff_out10, vidin_new_data); + my_fifo_496 fifo10(tm3_clk_v0, buff_out10, buff_out11, vidin_new_data); + + my_fifo_496 more_inst (tm3_clk_v0, buff_out11, vidin_out, vidin_new_data); +endmodule +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.22 ,2001 +// By: Ahmad darabiha +module v_fltr_316 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out); + + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[7:0] vidin_out; + wire[7:0] vidin_out; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + + assign buff_out0 = vidin_in ; + + my_fifo_316 fifo0(tm3_clk_v0, buff_out0, buff_out1, vidin_new_data); + my_fifo_316 fifo1(tm3_clk_v0, buff_out1, buff_out2, vidin_new_data); + my_fifo_316 fifo2(tm3_clk_v0, buff_out2, buff_out3, vidin_new_data); + + my_fifo_316 more_inst (tm3_clk_v0, buff_out3, vidin_out, vidin_new_data); +endmodule + +module lp_fltr_v1 (clk, din, dout_1, dout_2, nd); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + output[8 - 1:0] dout_2; + reg[8 - 1:0] dout_2; + input nd; + + reg[8 - 1:0] din_1_reg; + wire[8 - 1:0] buff_out_1; + wire[8 - 1:0] buff_out_2; + reg[8 - 1:0] din_2_reg; + reg[8 - 1:0] din_3_reg; + reg[8 + 1:0] add_tmp_1; + reg[8 + 1:0] add_tmp_2; + + my_fifo_359 ints_fifo_1 (clk, din, buff_out_1, nd); + my_fifo_359 ints_fifo_2 (clk, buff_out_1, buff_out_2, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din ; + din_2_reg <= buff_out_1 ; + din_3_reg <= buff_out_2 ; + dout_1 <= din ; + dout_2 <= add_tmp_2[8 + 1:2] ; + end + add_tmp_1 <= ({din_3_reg[8 - 1], din_3_reg[8 - 1], din_3_reg}) + ({din_1_reg[8 - 1], din_1_reg[8 - 1], din_1_reg}) ; + add_tmp_2 <= add_tmp_1 + ({din_2_reg[8 - 1], din_2_reg, 1'b0}) ; + end +endmodule + + + + + +module lp_fltr_v2 (clk, din, dout_1, dout_2, nd); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + output[8 - 1:0] dout_2; + reg[8 - 1:0] dout_2; + input nd; + + reg[8 - 1:0] din_1_reg; + wire[8 - 1:0] buff_out_1; + wire[8 - 1:0] buff_out_2; + reg[8 - 1:0] din_2_reg; + reg[8 - 1:0] din_3_reg; + reg[8 + 1:0] add_tmp_1; + reg[8 + 1:0] add_tmp_2; + // <> Unsupported Construct - attribute (source line 31) + // <> Unsupported Construct - attribute (source line 32)) + + my_fifo_179 ints_fifo_1 (clk, din, buff_out_1, nd); + my_fifo_179 ints_fifo_2 (clk, buff_out_1, buff_out_2, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din ; + din_2_reg <= buff_out_1 ; + din_3_reg <= buff_out_2 ; + dout_1 <= din ; + dout_2 <= add_tmp_2[8 + 1:2] ; + end + add_tmp_1 <= ({din_3_reg[8 - 1], din_3_reg[8 - 1], din_3_reg}) + ({din_1_reg[8 - 1], din_1_reg[8 - 1], din_1_reg}) ; + add_tmp_2 <= add_tmp_1 + ({din_2_reg[8 - 1], din_2_reg, 1'b0}) ; + end +endmodule + +module lp_fltr_v4 (clk, din, dout_1, dout_2, nd); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + output[8 - 1:0] dout_2; + reg[8 - 1:0] dout_2; + input nd; + + reg[8 - 1:0] din_1_reg; + wire[8 - 1:0] buff_out_1; + wire[8 - 1:0] buff_out_2; + reg[8 - 1:0] din_2_reg; + reg[8 - 1:0] din_3_reg; + reg[8 + 1:0] add_tmp_1; + reg[8 + 1:0] add_tmp_2; + + my_fifo_89 ints_fifo_1 (clk, din, buff_out_1, nd); + my_fifo_89 ints_fifo_2 (clk, buff_out_1, buff_out_2, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din ; + din_2_reg <= buff_out_1 ; + din_3_reg <= buff_out_2 ; + dout_1 <= din ; + dout_2 <= add_tmp_2[8 + 1:2] ; + end + add_tmp_1 <= ({din_3_reg[8 - 1], din_3_reg[8 - 1], din_3_reg}) + ({din_1_reg[8 - 1], din_1_reg[8 - 1], din_1_reg}) ; + add_tmp_2 <= add_tmp_1 + ({din_2_reg[8 - 1], din_2_reg, 1'b0}) ; + end +endmodule + +module scaler ( + tm3_clk_v0, + vidin_new_data, + vidin_rgb_reg, + vidin_addr_reg, + vidin_new_data_scld_1, + vidin_new_data_scld_2, + vidin_new_data_scld_4, + vidin_gray_scld_1, + vidin_gray_scld_2, + vidin_gray_scld_4 +); + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_rgb_reg; + input[3:0] vidin_addr_reg; + output vidin_new_data_scld_1; + reg vidin_new_data_scld_1; + output vidin_new_data_scld_2; + reg vidin_new_data_scld_2; + output vidin_new_data_scld_4; + reg vidin_new_data_scld_4; + output[7:0] vidin_gray_scld_1; + reg[7:0] vidin_gray_scld_1; + output[7:0] vidin_gray_scld_2; + reg[7:0] vidin_gray_scld_2; + output[7:0] vidin_gray_scld_4; + reg[7:0] vidin_gray_scld_4; + + wire[7:0] v_fltr_sc_1; + wire[7:0] v_fltr_sc_2; + wire[7:0] v_fltr_sc_4; + wire[7:0] h_fltr_sc_1; + wire[7:0] h_fltr_sc_2; + wire[7:0] h_fltr_sc_4; + + scl_v_fltr scl_v_fltr_inst (tm3_clk_v0, vidin_new_data, vidin_rgb_reg, v_fltr_sc_1, v_fltr_sc_2, v_fltr_sc_4); + scl_h_fltr scl_h_fltr_inst (tm3_clk_v0, vidin_new_data, v_fltr_sc_1, v_fltr_sc_2, v_fltr_sc_4, h_fltr_sc_1, h_fltr_sc_2, h_fltr_sc_4); + + always @(posedge tm3_clk_v0) + begin + vidin_new_data_scld_1 <= vidin_new_data ; + if (vidin_new_data == 1'b1) + begin + vidin_gray_scld_1 <= h_fltr_sc_1 ; + if ((vidin_addr_reg[0]) == 1'b0 & (vidin_addr_reg[2]) == 1'b0) + begin + vidin_gray_scld_2 <= h_fltr_sc_2 ; + vidin_new_data_scld_2 <= 1'b1 ; + if ((vidin_addr_reg[1]) == 1'b0 & (vidin_addr_reg[3]) == 1'b0) + begin + vidin_gray_scld_4 <= h_fltr_sc_4 ; + vidin_new_data_scld_4 <= 1'b1 ; + end + else + begin + vidin_new_data_scld_4 <= 1'b0 ; + end + end + else + begin + vidin_new_data_scld_2 <= 1'b0; + vidin_new_data_scld_4 <= 1'b0; + end + end + else + begin + vidin_new_data_scld_2 <= 1'b0; + vidin_new_data_scld_4 <= 1'b0 ; + end + end +endmodule + + + + +module scl_v_fltr (clk, nd, d_in, d_out_1, d_out_2, d_out_4); + + // <> : Warning - included file work/basic_type does not exist - this may affect translation + + input clk; + input nd; + input[7:0] d_in; + output[7:0] d_out_1; + reg[7:0] d_out_1; + output[7:0] d_out_2; + reg[7:0] d_out_2; + output[7:0] d_out_4; + reg[7:0] d_out_4; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + reg[7:0] buff_out_reg0; + reg[7:0] buff_out_reg1; + reg[7:0] buff_out_reg2; + reg[7:0] buff_out_reg3; + reg[7:0] buff_out_reg4; + reg[7:0] buff_out_reg5; + reg[7:0] buff_out_reg6; + reg[7:0] buff_out_reg7; + reg[9:0] add_2_tmp_1; + reg[9:0] add_2_tmp_2; + reg[9:0] add_2_tmp; + reg[11:0] add_4_tmp_1; + reg[11:0] add_4_tmp_2; + reg[11:0] add_4_tmp_3; + reg[11:0] add_4_tmp_4; + reg[11:0] add_4_tmp_5; + reg[11:0] add_4_tmp_6; + reg[11:0] add_4_tmp_7; + reg[11:0] add_4_tmp_8; + reg[11:0] add_4_tmp; + // <> Unsupported Construct - attribute (source line 33) + // <> Unsupported Construct - attribute (source line 34)) + + assign buff_out0 = d_in ; + + my_fifo_496 ints_fifo_gen_0 (clk, buff_out0, buff_out1, nd); + my_fifo_496 ints_fifo_gen_1 (clk, buff_out1, buff_out2, nd); + my_fifo_496 ints_fifo_gen_2 (clk, buff_out2, buff_out3, nd); + my_fifo_496 ints_fifo_gen_3 (clk, buff_out3, buff_out4, nd); + my_fifo_496 ints_fifo_gen_4 (clk, buff_out4, buff_out5, nd); + my_fifo_496 ints_fifo_gen_5 (clk, buff_out5, buff_out6, nd); + my_fifo_496 ints_fifo_gen_6 (clk, buff_out6, buff_out7, nd); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + buff_out_reg1 <= buff_out1 ; + buff_out_reg2 <= buff_out2 ; + buff_out_reg3 <= buff_out3 ; + buff_out_reg4 <= buff_out4 ; + buff_out_reg5 <= buff_out5 ; + buff_out_reg6 <= buff_out6 ; + buff_out_reg7 <= buff_out7 ; + d_out_1 <= buff_out_reg1 ; + d_out_2 <= add_2_tmp[9:2] ; + d_out_4 <= add_4_tmp[11:4] ; + end + add_2_tmp_1 <= ({2'b00, buff_out_reg1}) + ({2'b00, buff_out_reg3}) ; + add_2_tmp_2 <= {1'b0, buff_out_reg2, 1'b0} ; + add_2_tmp <= add_2_tmp_1 + add_2_tmp_2 ; + add_4_tmp_1 <= ({4'b0000, buff_out_reg1}) + ({4'b0000, buff_out_reg7}) ; + add_4_tmp_2 <= ({3'b000, buff_out_reg2, 1'b0}) + ({3'b000, buff_out_reg6, 1'b0}) ; + add_4_tmp_3 <= ({3'b000, buff_out_reg3, 1'b0}) + ({3'b000, buff_out_reg5, 1'b0}) ; + add_4_tmp_4 <= ({4'b0000, buff_out_reg3}) + ({4'b0000, buff_out_reg5}) ; + add_4_tmp_5 <= ({2'b00, buff_out_reg4, 2'b00}) ; + add_4_tmp_6 <= add_4_tmp_1 + add_4_tmp_2 ; + add_4_tmp_7 <= add_4_tmp_3 + add_4_tmp_4 ; + add_4_tmp_8 <= add_4_tmp_5 + add_4_tmp_6 ; + add_4_tmp <= add_4_tmp_7 + add_4_tmp_8 ; + end +endmodule +module scl_h_fltr (clk, nd, d_in_1, d_in_2, d_in_4, d_out_1, d_out_2, d_out_4); + + input clk; + input nd; + input[7:0] d_in_1; + input[7:0] d_in_2; + input[7:0] d_in_4; + output[7:0] d_out_1; + reg[7:0] d_out_1; + output[7:0] d_out_2; + reg[7:0] d_out_2; + output[7:0] d_out_4; + reg[7:0] d_out_4; + + wire[7:0] buff_out_20; + wire[7:0] buff_out_21; + wire[7:0] buff_out_22; + wire[7:0] buff_out_23; + reg[7:0] buff_out_reg_21; + reg[7:0] buff_out_reg_22; + reg[7:0] buff_out_reg_23; + wire[7:0] buff_out_40; + wire[7:0] buff_out_41; + wire[7:0] buff_out_42; + wire[7:0] buff_out_43; + wire[7:0] buff_out_44; + wire[7:0] buff_out_45; + wire[7:0] buff_out_46; + wire[7:0] buff_out_47; + reg[7:0] buff_out_reg_41; + reg[7:0] buff_out_reg_42; + reg[7:0] buff_out_reg_43; + reg[7:0] buff_out_reg_44; + reg[7:0] buff_out_reg_45; + reg[7:0] buff_out_reg_46; + reg[7:0] buff_out_reg_47; + reg[9:0] add_2_tmp_1; + reg[9:0] add_2_tmp_2; + reg[9:0] add_2_tmp; + reg[11:0] add_4_tmp_1; + reg[11:0] add_4_tmp_2; + reg[11:0] add_4_tmp_3; + reg[11:0] add_4_tmp_4; + reg[11:0] add_4_tmp_5; + reg[11:0] add_4_tmp_6; + reg[11:0] add_4_tmp_7; + reg[11:0] add_4_tmp_8; + reg[11:0] add_4_tmp; + + assign buff_out_20 = d_in_2 ; + assign buff_out_40 = d_in_4 ; + + sh_reg_1 ints_sh_reg_2_0(clk, nd, buff_out_20, buff_out_21); + sh_reg_1 ints_sh_reg_2_1(clk, nd, buff_out_21, buff_out_22); + sh_reg_1 ints_sh_reg_2_2(clk, nd, buff_out_22, buff_out_23); + sh_reg_1 ints_sh_reg_4_0(clk, nd, buff_out_40, buff_out_41); + sh_reg_1 ints_sh_reg_4_1(clk, nd, buff_out_41, buff_out_42); + sh_reg_1 ints_sh_reg_4_2(clk, nd, buff_out_42, buff_out_43); + sh_reg_1 ints_sh_reg_4_3(clk, nd, buff_out_43, buff_out_44); + sh_reg_1 ints_sh_reg_4_4(clk, nd, buff_out_44, buff_out_45); + sh_reg_1 ints_sh_reg_4_5(clk, nd, buff_out_45, buff_out_46); + sh_reg_1 ints_sh_reg_4_6(clk, nd, buff_out_46, buff_out_47); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + buff_out_reg_41 <= buff_out_41 ; + buff_out_reg_42 <= buff_out_42 ; + buff_out_reg_43 <= buff_out_43 ; + buff_out_reg_44 <= buff_out_44 ; + buff_out_reg_45 <= buff_out_45 ; + buff_out_reg_46 <= buff_out_46 ; + buff_out_reg_47 <= buff_out_47 ; + buff_out_reg_21 <= buff_out_21 ; + buff_out_reg_22 <= buff_out_22 ; + buff_out_reg_23 <= buff_out_23 ; + d_out_1 <= d_in_1 ; + d_out_2 <= add_2_tmp[9:2] ; + d_out_4 <= add_4_tmp[11:4] ; + end + add_2_tmp_1 <= ({2'b00, buff_out_reg_21}) + ({2'b00, buff_out_reg_23}) ; + add_2_tmp_2 <= {1'b0, buff_out_reg_22, 1'b0} ; + add_2_tmp <= add_2_tmp_1 + add_2_tmp_2 ; + add_4_tmp_1 <= ({4'b0000, buff_out_reg_41}) + ({4'b0000, buff_out_reg_47}) ; + add_4_tmp_2 <= ({3'b000, buff_out_reg_42, 1'b0}) + ({3'b000, buff_out_reg_46, 1'b0}) ; + add_4_tmp_3 <= ({3'b000, buff_out_reg_43, 1'b0}) + ({3'b000, buff_out_reg_45, 1'b0}) ; + add_4_tmp_4 <= ({4'b0000, buff_out_reg_43}) + ({4'b0000, buff_out_reg_45}) ; + add_4_tmp_5 <= ({2'b00, buff_out_reg_44, 2'b00}) ; + add_4_tmp_6 <= add_4_tmp_1 + add_4_tmp_2 ; + add_4_tmp_7 <= add_4_tmp_3 + add_4_tmp_4 ; + add_4_tmp_8 <= add_4_tmp_5 + add_4_tmp_6 ; + add_4_tmp <= add_4_tmp_7 + add_4_tmp_8 ; + end +endmodule +// Discription: this block creates a simple +// shift register +// date: July 27 ,2002 +// By: Ahmad darabiha +// copy from sh_reg.vhd changed to only 1-in-1-out +module sh_reg_1 (clk, wen, din_1, dout_1); + + input clk; + input wen; + input[8 - 1:0] din_1; + output[8 - 1:0] dout_1; + reg[8 - 1:0] dout_1; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + dout_1 <= din_1 ; + end + end +endmodule +module wrapper_qs_intr_10_20 (clk, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + din8, + din9, + din10, +wen_4, addrin, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20, +rdy); + + input clk; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + input[7:0] din6; + input[7:0] din7; + input[7:0] din8; + input[7:0] din9; + input[7:0] din10; + input wen_4; + input[18:0] addrin; + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + wire[15:0] dout0; + wire[15:0] dout1; + wire[15:0] dout2; + wire[15:0] dout3; + wire[15:0] dout4; + wire[15:0] dout5; + wire[15:0] dout6; + wire[15:0] dout7; + wire[15:0] dout8; + wire[15:0] dout9; + wire[15:0] dout10; + wire[15:0] dout11; + wire[15:0] dout12; + wire[15:0] dout13; + wire[15:0] dout14; + wire[15:0] dout15; + wire[15:0] dout16; + wire[15:0] dout17; + wire[15:0] dout18; + wire[15:0] dout19; + wire[15:0] dout20; + output rdy; + wire rdy; + wire[15:0] dout_tmp0; + wire[15:0] dout_tmp1; + wire[15:0] dout_tmp2; + wire[15:0] dout_tmp3; + wire[15:0] dout_tmp4; + wire[15:0] dout_tmp5; + wire[15:0] dout_tmp6; + wire[15:0] dout_tmp7; + wire[15:0] dout_tmp8; + wire[15:0] dout_tmp9; + wire[15:0] dout_tmp10; + wire[15:0] dout_tmp11; + wire[15:0] dout_tmp12; + wire[15:0] dout_tmp13; + wire[15:0] dout_tmp14; + wire[15:0] dout_tmp15; + wire[15:0] dout_tmp16; + wire[15:0] dout_tmp17; + wire[15:0] dout_tmp18; + wire[15:0] dout_tmp19; + wire[15:0] dout_tmp20; + wire[7:0] addr_tmp; + wire[15:0] dout_tt; + + reg [15:0]tmy_ram0; + reg [15:0]tmy_ram1; + reg [15:0]tmy_ram2; + reg [15:0]tmy_ram3; + reg [15:0]tmy_ram4; + reg [15:0]tmy_ram5; + reg [15:0]tmy_ram6; + reg [15:0]tmy_ram7; + reg [15:0]tmy_ram8; + reg [15:0]tmy_ram9; + reg [15:0]tmy_ram10; + reg [15:0]tmy_ram11; + reg [15:0]tmy_ram12; + reg [15:0]tmy_ram13; + reg [15:0]tmy_ram14; + reg [15:0]tmy_ram15; + reg [15:0]tmy_ram16; + reg [15:0]tmy_ram17; + reg [15:0]tmy_ram18; + reg [15:0]tmy_ram19; + reg [15:0]tmy_ram20; + reg [15:0]my_ram0; + reg [15:0]my_ram1; + reg [15:0]my_ram2; + reg [15:0]my_ram3; + reg [15:0]my_ram4; + reg [15:0]my_ram5; + reg [15:0]my_ram6; + reg [15:0]my_ram7; + reg [15:0]my_ram8; + reg [15:0]my_ram9; + reg [15:0]my_ram10; + reg [15:0]my_ram11; + reg [15:0]my_ram12; + reg [15:0]my_ram13; + reg [15:0]my_ram14; + reg [15:0]my_ram15; + reg [15:0]my_ram16; + reg [15:0]my_ram17; + reg [15:0]my_ram18; + reg [15:0]my_ram19; + reg [15:0]my_ram20; + + assign rdy = 1'b1; + assign dout0 = my_ram0; + assign dout1 = my_ram1; + assign dout2 = my_ram2; + assign dout3 = my_ram3; + assign dout4 = my_ram4; + assign dout5 = my_ram5; + assign dout6 = my_ram6; + assign dout7 = my_ram7; + assign dout8 = my_ram8; + assign dout9 = my_ram9; + assign dout10 = my_ram10; + assign dout11 = my_ram11; + assign dout12 = my_ram12; + assign dout13 = my_ram13; + assign dout14 = my_ram14; + assign dout15 = my_ram15; + assign dout16 = my_ram16; + assign dout17 = my_ram17; + assign dout18 = my_ram18; + assign dout19 = my_ram19; + assign dout20 = my_ram20; + always @(posedge clk) + begin + if (wen_4 == 1'b1) + begin + tmy_ram0 <= dout_tmp0; + tmy_ram1 <= dout_tmp1; + tmy_ram2 <= dout_tmp2; + tmy_ram3 <= dout_tmp3; + tmy_ram4 <= dout_tmp4; + tmy_ram5 <= dout_tmp5; + tmy_ram6 <= dout_tmp6; + tmy_ram7 <= dout_tmp7; + tmy_ram8 <= dout_tmp8; + tmy_ram9 <= dout_tmp9; + tmy_ram10 <= dout_tmp10; + tmy_ram11 <= dout_tmp11; + tmy_ram12 <= dout_tmp12; + tmy_ram13 <= dout_tmp13; + tmy_ram14 <= dout_tmp14; + tmy_ram15 <= dout_tmp15; + tmy_ram16 <= dout_tmp16; + tmy_ram17 <= dout_tmp17; + tmy_ram18 <= dout_tmp18; + tmy_ram19 <= dout_tmp19; + tmy_ram20 <= dout_tmp20; + my_ram0 <= tmy_ram0; + my_ram1 <= tmy_ram1; + my_ram2 <= tmy_ram2; + my_ram3 <= tmy_ram3; + my_ram4 <= tmy_ram4; + my_ram5 <= tmy_ram5; + my_ram6 <= tmy_ram6; + my_ram7 <= tmy_ram7; + my_ram8 <= tmy_ram8; + my_ram9 <= tmy_ram9; + my_ram10 <= tmy_ram10; + my_ram11 <= tmy_ram11; + my_ram12 <= tmy_ram12; + my_ram13 <= tmy_ram13; + my_ram14 <= tmy_ram14; + my_ram15 <= tmy_ram15; + my_ram16 <= tmy_ram16; + my_ram17 <= tmy_ram17; + my_ram18 <= tmy_ram18; + my_ram19 <= tmy_ram19; + my_ram20 <= tmy_ram20; + end + end + + assign addr_tmp = addrin; + + quadintr_10_20 my_inst_quadintr(clk, wen_4, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + din8, + din9, + din10, + dout_tmp0, + dout_tmp1, + dout_tmp2, + dout_tmp3, + dout_tmp4, + dout_tmp5, + dout_tmp6, + dout_tmp7, + dout_tmp8, + dout_tmp9, + dout_tmp10, + dout_tmp11, + dout_tmp12, + dout_tmp13, + dout_tmp14, + dout_tmp15, + dout_tmp16, + dout_tmp17, + dout_tmp18, + dout_tmp19, + dout_tmp20); + +endmodule + + + +module wrapper_qs_intr_5_20 (clk, + din0, + din1, + din2, + din3, + din4, + din5, +wen_4, addrin, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20, +rdy); + + input clk; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + input wen_4; + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + wire[15:0] dout0; + wire[15:0] dout1; + wire[15:0] dout2; + wire[15:0] dout3; + wire[15:0] dout4; + wire[15:0] dout5; + wire[15:0] dout6; + wire[15:0] dout7; + wire[15:0] dout8; + wire[15:0] dout9; + wire[15:0] dout10; + wire[15:0] dout11; + wire[15:0] dout12; + wire[15:0] dout13; + wire[15:0] dout14; + wire[15:0] dout15; + wire[15:0] dout16; + wire[15:0] dout17; + wire[15:0] dout18; + wire[15:0] dout19; + wire[15:0] dout20; + input[18:0] addrin; + output rdy; + wire rdy; + wire[15:0] dout_tmp0; + wire[15:0] dout_tmp1; + wire[15:0] dout_tmp2; + wire[15:0] dout_tmp3; + wire[15:0] dout_tmp4; + wire[15:0] dout_tmp5; + wire[15:0] dout_tmp6; + wire[15:0] dout_tmp7; + wire[15:0] dout_tmp8; + wire[15:0] dout_tmp9; + wire[15:0] dout_tmp10; + wire[15:0] dout_tmp11; + wire[15:0] dout_tmp12; + wire[15:0] dout_tmp13; + wire[15:0] dout_tmp14; + wire[15:0] dout_tmp15; + wire[15:0] dout_tmp16; + wire[15:0] dout_tmp17; + wire[15:0] dout_tmp18; + wire[15:0] dout_tmp19; + wire[15:0] dout_tmp20; + wire[7:0] addr_tmp; + wire[15:0] dout_tt; + + reg [15:0]tmy_ram0; + reg [15:0]tmy_ram1; + reg [15:0]tmy_ram2; + reg [15:0]tmy_ram3; + reg [15:0]tmy_ram4; + reg [15:0]tmy_ram5; + reg [15:0]tmy_ram6; + reg [15:0]tmy_ram7; + reg [15:0]tmy_ram8; + reg [15:0]tmy_ram9; + reg [15:0]tmy_ram10; + reg [15:0]tmy_ram11; + reg [15:0]tmy_ram12; + reg [15:0]tmy_ram13; + reg [15:0]tmy_ram14; + reg [15:0]tmy_ram15; + reg [15:0]tmy_ram16; + reg [15:0]tmy_ram17; + reg [15:0]tmy_ram18; + reg [15:0]tmy_ram19; + reg [15:0]tmy_ram20; + reg [15:0]my_ram0; + reg [15:0]my_ram1; + reg [15:0]my_ram2; + reg [15:0]my_ram3; + reg [15:0]my_ram4; + reg [15:0]my_ram5; + reg [15:0]my_ram6; + reg [15:0]my_ram7; + reg [15:0]my_ram8; + reg [15:0]my_ram9; + reg [15:0]my_ram10; + reg [15:0]my_ram11; + reg [15:0]my_ram12; + reg [15:0]my_ram13; + reg [15:0]my_ram14; + reg [15:0]my_ram15; + reg [15:0]my_ram16; + reg [15:0]my_ram17; + reg [15:0]my_ram18; + reg [15:0]my_ram19; + reg [15:0]my_ram20; + + assign rdy = 1'b1; + assign dout0 = my_ram0; + assign dout1 = my_ram1; + assign dout2 = my_ram2; + assign dout3 = my_ram3; + assign dout4 = my_ram4; + assign dout5 = my_ram5; + assign dout6 = my_ram6; + assign dout7 = my_ram7; + assign dout8 = my_ram8; + assign dout9 = my_ram9; + assign dout10 = my_ram10; + assign dout11 = my_ram11; + assign dout12 = my_ram12; + assign dout13 = my_ram13; + assign dout14 = my_ram14; + assign dout15 = my_ram15; + assign dout16 = my_ram16; + assign dout17 = my_ram17; + assign dout18 = my_ram18; + assign dout19 = my_ram19; + assign dout20 = my_ram20; + always @(posedge clk) + begin + if (wen_4 == 1'b1) + begin + tmy_ram0 <= dout_tmp0; + tmy_ram1 <= dout_tmp1; + tmy_ram2 <= dout_tmp2; + tmy_ram3 <= dout_tmp3; + tmy_ram4 <= dout_tmp4; + tmy_ram5 <= dout_tmp5; + tmy_ram6 <= dout_tmp6; + tmy_ram7 <= dout_tmp7; + tmy_ram8 <= dout_tmp8; + tmy_ram9 <= dout_tmp9; + tmy_ram10 <= dout_tmp10; + tmy_ram11 <= dout_tmp11; + tmy_ram12 <= dout_tmp12; + tmy_ram13 <= dout_tmp13; + tmy_ram14 <= dout_tmp14; + tmy_ram15 <= dout_tmp15; + tmy_ram16 <= dout_tmp16; + tmy_ram17 <= dout_tmp17; + tmy_ram18 <= dout_tmp18; + tmy_ram19 <= dout_tmp19; + tmy_ram20 <= dout_tmp20; + my_ram0 <= tmy_ram0; + my_ram1 <= tmy_ram1; + my_ram2 <= tmy_ram2; + my_ram3 <= tmy_ram3; + my_ram4 <= tmy_ram4; + my_ram5 <= tmy_ram5; + my_ram6 <= tmy_ram6; + my_ram7 <= tmy_ram7; + my_ram8 <= tmy_ram8; + my_ram9 <= tmy_ram9; + my_ram10 <= tmy_ram10; + my_ram11 <= tmy_ram11; + my_ram12 <= tmy_ram12; + my_ram13 <= tmy_ram13; + my_ram14 <= tmy_ram14; + my_ram15 <= tmy_ram15; + my_ram16 <= tmy_ram16; + my_ram17 <= tmy_ram17; + my_ram18 <= tmy_ram18; + my_ram19 <= tmy_ram19; + my_ram20 <= tmy_ram20; + end + end + + assign addr_tmp = {1'b0, addrin} ; + + + quadintr_5_20 my_inst_quadintr(clk, wen_4, + din0, + din1, + din2, + din3, + din4, + din5, + dout_tmp0, + dout_tmp1, + dout_tmp2, + dout_tmp3, + dout_tmp4, + dout_tmp5, + dout_tmp6, + dout_tmp7, + dout_tmp8, + dout_tmp9, + dout_tmp10, + dout_tmp11, + dout_tmp12, + dout_tmp13, + dout_tmp14, + dout_tmp15, + dout_tmp16, + dout_tmp17, + dout_tmp18, + dout_tmp19, + dout_tmp20); +endmodule + + + +module quadintr_10_20 (clk, new_data, + din0, + din1, + din2, + din3, + din4, + din5, + din6, + din7, + din8, + din9, + din10, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20); + + + input clk; + input new_data; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + input[7:0] din6; + input[7:0] din7; + input[7:0] din8; + input[7:0] din9; + input[7:0] din10; + reg[7:0] dinr0; + reg[7:0] dinr1; + reg[7:0] dinr2; + reg[7:0] dinr3; + reg[7:0] dinr4; + reg[7:0] dinr5; + reg[7:0] dinr6; + reg[7:0] dinr7; + reg[7:0] dinr8; + reg[7:0] dinr9; + reg[7:0] dinr10; + + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + reg[15:0] dout0; + reg[15:0] dout1; + reg[15:0] dout2; + reg[15:0] dout3; + reg[15:0] dout4; + reg[15:0] dout5; + reg[15:0] dout6; + reg[15:0] dout7; + reg[15:0] dout8; + reg[15:0] dout9; + reg[15:0] dout10; + reg[15:0] dout11; + reg[15:0] dout12; + reg[15:0] dout13; + reg[15:0] dout14; + reg[15:0] dout15; + reg[15:0] dout16; + reg[15:0] dout17; + reg[15:0] dout18; + reg[15:0] dout19; + reg[15:0] dout20; + + reg[7:0] tmp_10; + reg[7:0] tmp_11; + reg[7:0] tmp_12; + reg[7:0] tmp_13; + reg[7:0] tmp_14; + reg[7:0] tmp_15; + reg[7:0] tmp_16; + reg[7:0] tmp_17; + reg[7:0] tmp_18; + reg[7:0] tmp_19; + reg[7:0] tmp_110; + reg[7:0] tmp_111; + reg[7:0] tmp_112; + reg[7:0] tmp_113; + reg[7:0] tmp_114; + reg[7:0] tmp_115; + reg[7:0] tmp_116; + reg[7:0] tmp_117; + reg[7:0] tmp_118; + reg[7:0] tmp_119; + reg[7:0] tmp_120; + reg[7:0] tmp_20; + reg[7:0] tmp_21; + reg[7:0] tmp_22; + reg[7:0] tmp_23; + reg[7:0] tmp_24; + reg[7:0] tmp_25; + reg[7:0] tmp_26; + reg[7:0] tmp_27; + reg[7:0] tmp_28; + reg[7:0] tmp_29; + reg[7:0] tmp_210; + reg[7:0] tmp_211; + reg[7:0] tmp_212; + reg[7:0] tmp_213; + reg[7:0] tmp_214; + reg[7:0] tmp_215; + reg[7:0] tmp_216; + reg[7:0] tmp_217; + reg[7:0] tmp_218; + reg[7:0] tmp_219; + reg[7:0] tmp_220; + reg[7:0] tmp_30; + reg[7:0] tmp_31; + reg[7:0] tmp_32; + reg[7:0] tmp_33; + reg[7:0] tmp_34; + reg[7:0] tmp_35; + reg[7:0] tmp_36; + reg[7:0] tmp_37; + reg[7:0] tmp_38; + reg[7:0] tmp_39; + reg[7:0] tmp_310; + reg[7:0] tmp_311; + reg[7:0] tmp_312; + reg[7:0] tmp_313; + reg[7:0] tmp_314; + reg[7:0] tmp_315; + reg[7:0] tmp_316; + reg[7:0] tmp_317; + reg[7:0] tmp_318; + reg[7:0] tmp_319; + reg[7:0] tmp_320; + reg[8:0] add_tmp0; + reg[8:0] add_tmp1; + reg[8:0] add_tmp2; + reg[8:0] add_tmp3; + reg[8:0] add_tmp4; + reg[8:0] add_tmp5; + reg[8:0] add_tmp6; + reg[8:0] add_tmp7; + reg[8:0] add_tmp8; + reg[8:0] add_tmp9; + reg[8:0] add_tmp10; + reg[8:0] add_tmp11; + reg[8:0] add_tmp12; + reg[8:0] add_tmp13; + reg[8:0] add_tmp14; + reg[8:0] add_tmp15; + reg[8:0] add_tmp16; + reg[8:0] add_tmp17; + reg[8:0] add_tmp18; + reg[8:0] add_tmp19; + reg[8:0] add_tmp20; + reg[8:0] doutr0; + reg[8:0] doutr1; + reg[8:0] doutr2; + reg[8:0] doutr3; + reg[8:0] doutr4; + reg[8:0] doutr5; + reg[8:0] doutr6; + reg[8:0] doutr7; + reg[8:0] doutr8; + reg[8:0] doutr9; + reg[8:0] doutr10; + reg[8:0] doutr11; + reg[8:0] doutr12; + reg[8:0] doutr13; + reg[8:0] doutr14; + reg[8:0] doutr15; + reg[8:0] doutr16; + reg[8:0] doutr17; + reg[8:0] doutr18; + reg[8:0] doutr19; + reg[8:0] doutr20; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + dinr0 <= din0; + dinr1 <= din1; + dinr2 <= din2; + dinr3 <= din3; + dinr4 <= din4; + dinr5 <= din5; + dinr6 <= din6; + dinr7 <= din7; + dinr8 <= din8; + dinr9 <= din9; + dinr10 <= din10; + + dout0[15:9] <= {doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8]}; + dout1[15:9] <= {doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8]}; + dout2[15:9] <= {doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8]}; + dout3[15:9] <= {doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8]}; + dout4[15:9] <= {doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8]}; + dout5[15:9] <= {doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8]}; + dout6[15:9] <= {doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8]}; + dout7[15:9] <= {doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8]}; + dout8[15:9] <= {doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8]}; + dout9[15:9] <= {doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8]}; + dout10[15:9] <= {doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8]}; + dout11[15:9] <= {doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8]}; + dout12[15:9] <= {doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8]}; + dout13[15:9] <= {doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8]}; + dout14[15:9] <= {doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8]}; + dout15[15:9] <= {doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8]}; + dout16[15:9] <= {doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8]}; + dout17[15:9] <= {doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8]}; + dout18[15:9] <= {doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8]}; + dout19[15:9] <= {doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8]}; + dout20[15:9] <= {doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8]}; + dout0[8:0] <= doutr0; + dout1[8:0] <= doutr1; + dout2[8:0] <= doutr2; + dout3[8:0] <= doutr3; + dout4[8:0] <= doutr4; + dout5[8:0] <= doutr5; + dout6[8:0] <= doutr6; + dout7[8:0] <= doutr7; + dout8[8:0] <= doutr8; + dout9[8:0] <= doutr9; + dout10[8:0] <= doutr10; + dout11[8:0] <= doutr11; + dout12[8:0] <= doutr12; + dout13[8:0] <= doutr13; + dout14[8:0] <= doutr14; + dout15[8:0] <= doutr15; + dout16[8:0] <= doutr16; + dout17[8:0] <= doutr17; + dout18[8:0] <= doutr18; + dout19[8:0] <= doutr19; + dout20[8:0] <= doutr20; + end + doutr0 <= {dinr0[8-1], dinr0}; + doutr2 <= {dinr1[8-1], dinr1}; + doutr4 <= {dinr2[8-1], dinr2}; + doutr6 <= {dinr3[8-1], dinr3}; + doutr8 <= {dinr4[8-1], dinr4}; + doutr10 <= {dinr5[8-1], dinr5}; + doutr12 <= {dinr6[8-1], dinr6}; + doutr14 <= {dinr7[8-1], dinr7}; + doutr16 <= {dinr8[8-1], dinr8}; + + tmp_11 <= {dinr0[8-1], dinr0[8-1], dinr0[8-1:2]} + {dinr0[8-1], dinr0[8-1], dinr0[8-1], dinr0[8-1:3]}; + tmp_13 <= {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1], dinr1[8-1:3]}; + tmp_15 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_17 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + tmp_19 <= {dinr4[8-1], dinr4[8-1], dinr4[8-1:2]} + {dinr4[8-1], dinr4[8-1], dinr4[8-1], dinr4[8-1:3]}; + tmp_111 <= {dinr5[8-1], dinr5[8-1], dinr5[8-1:2]} + {dinr5[8-1], dinr5[8-1], dinr5[8-1], dinr5[8-1:3]}; + tmp_113 <= {dinr6[8-1], dinr6[8-1], dinr6[8-1:2]} + {dinr6[8-1], dinr6[8-1], dinr6[8-1], dinr6[8-1:3]}; + tmp_115 <= {dinr7[8-1], dinr7[8-1], dinr7[8-1:2]} + {dinr7[8-1], dinr7[8-1], dinr7[8-1], dinr7[8-1:3]}; + tmp_117 <= {dinr8[8-1], dinr8[8-1], dinr8[8-1:2]} + {dinr8[8-1], dinr8[8-1], dinr8[8-1], dinr8[8-1:3]}; + + tmp_21 <= {dinr1[8-1], dinr1[8-1:1]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]}; + tmp_23 <= {dinr2[8-1], dinr2[8-1:1]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]}; + tmp_25 <= {dinr3[8-1], dinr3[8-1:1]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]}; + tmp_27 <= {dinr4[8-1], dinr4[8-1:1]} + {dinr4[8-1], dinr4[8-1], dinr4[8-1:2]}; + tmp_29 <= {dinr5[8-1], dinr5[8-1:1]} + {dinr5[8-1], dinr5[8-1], dinr5[8-1:2]}; + tmp_211 <= {dinr6[8-1], dinr6[8-1:1]} + {dinr6[8-1], dinr6[8-1], dinr6[8-1:2]}; + tmp_213 <= {dinr7[8-1], dinr7[8-1:1]} + {dinr7[8-1], dinr7[8-1], dinr7[8-1:2]}; + tmp_215 <= {dinr8[8-1], dinr8[8-1:1]} + {dinr8[8-1], dinr8[8-1], dinr8[8-1:2]}; + tmp_217 <= {dinr9[8-1], dinr9[8-1:1]} + {dinr9[8-1], dinr9[8-1], dinr9[8-1:2]}; + + tmp_31 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_33 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + tmp_35 <= {dinr4[8-1], dinr4[8-1], dinr4[8-1], dinr4[8-1:3]}; + tmp_37 <= {dinr5[8-1], dinr5[8-1], dinr5[8-1], dinr5[8-1:3]}; + tmp_39 <= {dinr6[8-1], dinr6[8-1], dinr6[8-1], dinr6[8-1:3]}; + tmp_311 <= {dinr7[8-1], dinr7[8-1], dinr7[8-1], dinr7[8-1:3]}; + tmp_313 <= {dinr8[8-1], dinr8[8-1], dinr8[8-1], dinr8[8-1:3]}; + tmp_315 <= {dinr9[8-1], dinr9[8-1], dinr9[8-1], dinr9[8-1:3]}; + tmp_317 <= {dinr10[8-1], dinr10[8-1], dinr10[8-1], dinr10[8-1:3]}; + + add_tmp1 <= {tmp_11[8-1], tmp_11} + {tmp_21[8-1], tmp_21}; + add_tmp3 <= {tmp_13[8-1], tmp_13} + {tmp_23[8-1], tmp_23}; + add_tmp5 <= {tmp_15[8-1], tmp_15} + {tmp_25[8-1], tmp_25}; + add_tmp7 <= {tmp_17[8-1], tmp_17} + {tmp_27[8-1], tmp_27}; + add_tmp9 <= {tmp_19[8-1], tmp_19} + {tmp_29[8-1], tmp_29}; + add_tmp11 <= {tmp_111[8-1], tmp_111} + {tmp_211[8-1], tmp_211}; + add_tmp13 <= {tmp_113[8-1], tmp_113} + {tmp_213[8-1], tmp_213}; + add_tmp15 <= {tmp_115[8-1], tmp_115} + {tmp_215[8-1], tmp_215}; + add_tmp17 <= {tmp_117[8-1], tmp_117} + {tmp_217[8-1], tmp_217}; + + doutr1 <= add_tmp1 - {tmp_31[8-1], tmp_31}; + doutr3 <= add_tmp3 - {tmp_33[8-1], tmp_33}; + doutr5 <= add_tmp5 - {tmp_35[8-1], tmp_35}; + doutr7 <= add_tmp7 - {tmp_37[8-1], tmp_37}; + doutr9 <= add_tmp9 - {tmp_39[8-1], tmp_39}; + doutr11 <= add_tmp11 - {tmp_311[8-1], tmp_311}; + doutr13 <= add_tmp13 - {tmp_313[8-1], tmp_313}; + doutr15 <= add_tmp15 - {tmp_315[8-1], tmp_315}; + doutr17 <= add_tmp17 - {tmp_317[8-1], tmp_317}; + + doutr18 <= {dinr9[8-1] , dinr9}; + + tmp_119 <= {dinr8[8-1], dinr8[8-1] , dinr8[8-1] , dinr8[8-1 : 3]}; + + tmp_219 <= {dinr9[8-1], dinr9[8-1 : 1]} + {dinr9[8-1], dinr9[8-1] , dinr9[8-1 : 2]}; + + tmp_319 <= {dinr10[8-1] , dinr10[8-1] , dinr10[8-1 : 2]} + {dinr10[8-1] , dinr10[8-1] , dinr10[8-1] , dinr10[8-1 : 3]}; + + add_tmp19 <= {tmp_219[8-1] , tmp_219} + {tmp_319[8-1] , tmp_319}; + + doutr19 <= add_tmp19 - {tmp_119[8-1] , tmp_119}; + + doutr20 <= {dinr10[8-1] , dinr10}; + end +endmodule + + + +module quadintr_5_20 (clk, new_data, + din0, + din1, + din2, + din3, + din4, + din5, + dout0, + dout1, + dout2, + dout3, + dout4, + dout5, + dout6, + dout7, + dout8, + dout9, + dout10, + dout11, + dout12, + dout13, + dout14, + dout15, + dout16, + dout17, + dout18, + dout19, + dout20); + + input clk; + input new_data; + input[7:0] din0; + input[7:0] din1; + input[7:0] din2; + input[7:0] din3; + input[7:0] din4; + input[7:0] din5; + reg[7:0] dinr0; + reg[7:0] dinr1; + reg[7:0] dinr2; + reg[7:0] dinr3; + reg[7:0] dinr4; + reg[7:0] dinr5; + output[15:0] dout0; + output[15:0] dout1; + output[15:0] dout2; + output[15:0] dout3; + output[15:0] dout4; + output[15:0] dout5; + output[15:0] dout6; + output[15:0] dout7; + output[15:0] dout8; + output[15:0] dout9; + output[15:0] dout10; + output[15:0] dout11; + output[15:0] dout12; + output[15:0] dout13; + output[15:0] dout14; + output[15:0] dout15; + output[15:0] dout16; + output[15:0] dout17; + output[15:0] dout18; + output[15:0] dout19; + output[15:0] dout20; + reg[15:0] dout0; + reg[15:0] dout1; + reg[15:0] dout2; + reg[15:0] dout3; + reg[15:0] dout4; + reg[15:0] dout5; + reg[15:0] dout6; + reg[15:0] dout7; + reg[15:0] dout8; + reg[15:0] dout9; + reg[15:0] dout10; + reg[15:0] dout11; + reg[15:0] dout12; + reg[15:0] dout13; + reg[15:0] dout14; + reg[15:0] dout15; + reg[15:0] dout16; + reg[15:0] dout17; + reg[15:0] dout18; + reg[15:0] dout19; + reg[15:0] dout20; + + reg[7:0] tmp_10; + reg[7:0] tmp_11; + reg[7:0] tmp_12; + reg[7:0] tmp_13; + reg[7:0] tmp_14; + reg[7:0] tmp_15; + reg[7:0] tmp_16; + reg[7:0] tmp_17; + reg[7:0] tmp_18; + reg[7:0] tmp_19; + reg[7:0] tmp_110; + reg[7:0] tmp_20; + reg[7:0] tmp_21; + reg[7:0] tmp_22; + reg[7:0] tmp_23; + reg[7:0] tmp_24; + reg[7:0] tmp_25; + reg[7:0] tmp_26; + reg[7:0] tmp_27; + reg[7:0] tmp_28; + reg[7:0] tmp_29; + reg[7:0] tmp_210; + reg[7:0] tmp_30; + reg[7:0] tmp_31; + reg[7:0] tmp_32; + reg[7:0] tmp_33; + reg[7:0] tmp_34; + reg[7:0] tmp_35; + reg[7:0] tmp_36; + reg[7:0] tmp_37; + reg[7:0] tmp_38; + reg[7:0] tmp_39; + reg[7:0] tmp_310; + reg[8:0] add_tmp0; + reg[8:0] add_tmp1; + reg[8:0] add_tmp2; + reg[8:0] add_tmp3; + reg[8:0] add_tmp4; + reg[8:0] add_tmp5; + reg[8:0] add_tmp6; + reg[8:0] add_tmp7; + reg[8:0] add_tmp8; + reg[8:0] add_tmp9; + reg[8:0] add_tmp10; + reg[8:0] doutr0; + reg[8:0] doutr1; + reg[8:0] doutr2; + reg[8:0] doutr3; + reg[8:0] doutr4; + reg[8:0] doutr5; + reg[8:0] doutr6; + reg[8:0] doutr7; + reg[8:0] doutr8; + reg[8:0] doutr9; + reg[8:0] doutr10; + reg[8:0] doutr11; + reg[8:0] doutr12; + reg[8:0] doutr13; + reg[8:0] doutr14; + reg[8:0] doutr15; + reg[8:0] doutr16; + reg[8:0] doutr17; + reg[8:0] doutr18; + reg[8:0] doutr19; + reg[8:0] doutr20; + + + reg[8:0] tmp_1_100; + reg[8:0] tmp_1_101; + reg[8:0] tmp_1_102; + reg[8:0] tmp_1_103; + reg[8:0] tmp_1_104; + reg[8:0] tmp_1_105; + reg[8:0] tmp_1_106; + reg[8:0] tmp_1_107; + reg[8:0] tmp_1_108; + reg[8:0] tmp_1_109; + reg[8:0] tmp_1_1010; + reg[8:0] tmp_1_1011; + reg[8:0] tmp_1_1012; + reg[8:0] tmp_1_1013; + reg[8:0] tmp_1_1014; + reg[8:0] tmp_1_1015; + reg[8:0] tmp_1_1016; + reg[8:0] tmp_1_1017; + reg[8:0] tmp_1_1018; + reg[8:0] tmp_1_1019; + reg[8:0] tmp_1_1020; + reg[8:0] tmp_2_100; + reg[8:0] tmp_2_101; + reg[8:0] tmp_2_102; + reg[8:0] tmp_2_103; + reg[8:0] tmp_2_104; + reg[8:0] tmp_2_105; + reg[8:0] tmp_2_106; + reg[8:0] tmp_2_107; + reg[8:0] tmp_2_108; + reg[8:0] tmp_2_109; + reg[8:0] tmp_2_1010; + reg[8:0] tmp_2_1011; + reg[8:0] tmp_2_1012; + reg[8:0] tmp_2_1013; + reg[8:0] tmp_2_1014; + reg[8:0] tmp_2_1015; + reg[8:0] tmp_2_1016; + reg[8:0] tmp_2_1017; + reg[8:0] tmp_2_1018; + reg[8:0] tmp_2_1019; + reg[8:0] tmp_2_1020; + reg[8:0] tmp_3_100; + reg[8:0] tmp_3_101; + reg[8:0] tmp_3_102; + reg[8:0] tmp_3_103; + reg[8:0] tmp_3_104; + reg[8:0] tmp_3_105; + reg[8:0] tmp_3_106; + reg[8:0] tmp_3_107; + reg[8:0] tmp_3_108; + reg[8:0] tmp_3_109; + reg[8:0] tmp_3_1010; + reg[8:0] tmp_3_1011; + reg[8:0] tmp_3_1012; + reg[8:0] tmp_3_1013; + reg[8:0] tmp_3_1014; + reg[8:0] tmp_3_1015; + reg[8:0] tmp_3_1016; + reg[8:0] tmp_3_1017; + reg[8:0] tmp_3_1018; + reg[8:0] tmp_3_1019; + reg[8:0] tmp_3_1020; + reg[8:0] add_tmp_100; + reg[8:0] add_tmp_101; + reg[8:0] add_tmp_102; + reg[8:0] add_tmp_103; + reg[8:0] add_tmp_104; + reg[8:0] add_tmp_105; + reg[8:0] add_tmp_106; + reg[8:0] add_tmp_107; + reg[8:0] add_tmp_108; + reg[8:0] add_tmp_109; + reg[8:0] add_tmp_1010; + reg[8:0] add_tmp_1011; + reg[8:0] add_tmp_1012; + reg[8:0] add_tmp_1013; + reg[8:0] add_tmp_1014; + reg[8:0] add_tmp_1015; + reg[8:0] add_tmp_1016; + reg[8:0] add_tmp_1017; + reg[8:0] add_tmp_1018; + reg[8:0] add_tmp_1019; + reg[8:0] add_tmp_1020; + + reg[8:0] doutr_100; + reg[8:0] doutr_101; + reg[8:0] doutr_102; + reg[8:0] doutr_103; + reg[8:0] doutr_104; + reg[8:0] doutr_105; + reg[8:0] doutr_106; + reg[8:0] doutr_107; + reg[8:0] doutr_108; + reg[8:0] doutr_109; + reg[8:0] doutr_1010; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + dinr0 <= din0; + dinr1 <= din1; + dinr2 <= din2; + dinr3 <= din3; + dinr4 <= din4; + dinr5 <= din5; + + dout0[15:9] <= {doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8],doutr0[8]}; + dout1[15:9] <= {doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8],doutr1[8]}; + dout2[15:9] <= {doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8],doutr2[8]}; + dout3[15:9] <= {doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8],doutr3[8]}; + dout4[15:9] <= {doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8],doutr4[8]}; + dout5[15:9] <= {doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8],doutr5[8]}; + dout6[15:9] <= {doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8],doutr6[8]}; + dout7[15:9] <= {doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8],doutr7[8]}; + dout8[15:9] <= {doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8],doutr8[8]}; + dout9[15:9] <= {doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8],doutr9[8]}; + dout10[15:9] <= {doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8],doutr10[8]}; + dout11[15:9] <= {doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8],doutr11[8]}; + dout12[15:9] <= {doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8],doutr12[8]}; + dout13[15:9] <= {doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8],doutr13[8]}; + dout14[15:9] <= {doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8],doutr14[8]}; + dout15[15:9] <= {doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8],doutr15[8]}; + dout16[15:9] <= {doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8],doutr16[8]}; + dout17[15:9] <= {doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8],doutr17[8]}; + dout18[15:9] <= {doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8],doutr18[8]}; + dout19[15:9] <= {doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8],doutr19[8]}; + dout20[15:9] <= {doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8],doutr20[8]}; + dout0[8:0] <= doutr0; + dout1[8:0] <= doutr1; + dout2[8:0] <= doutr2; + dout3[8:0] <= doutr3; + dout4[8:0] <= doutr4; + dout5[8:0] <= doutr5; + dout6[8:0] <= doutr6; + dout7[8:0] <= doutr7; + dout8[8:0] <= doutr8; + dout9[8:0] <= doutr9; + dout10[8:0] <= doutr10; + dout11[8:0] <= doutr11; + dout12[8:0] <= doutr12; + dout13[8:0] <= doutr13; + dout14[8:0] <= doutr14; + dout15[8:0] <= doutr15; + dout16[8:0] <= doutr16; + dout17[8:0] <= doutr17; + dout18[8:0] <= doutr18; + dout19[8:0] <= doutr19; + dout20[8:0] <= doutr20; + end + + doutr_100 <= {dinr0[8-1], dinr0}; + doutr_102 <= {dinr1[8-1], dinr1}; + doutr_104 <= {dinr2[8-1], dinr2}; + doutr_106 <= {dinr3[8-1], dinr3}; + + tmp_11 <= {dinr0[8-1], dinr0[8-1], dinr0[8-1:2]} + {dinr0[8-1], dinr0[8-1], dinr0[8-1], dinr0[8-1:3]}; + tmp_13 <= {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1], dinr1[8-1:3]}; + tmp_15 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_17 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + + tmp_21 <= {dinr1[8-1], dinr1[8-1:1]} + {dinr1[8-1], dinr1[8-1], dinr1[8-1:2]}; + tmp_23 <= {dinr2[8-1], dinr2[8-1:1]} + {dinr2[8-1], dinr2[8-1], dinr2[8-1:2]}; + tmp_25 <= {dinr3[8-1], dinr3[8-1:1]} + {dinr3[8-1], dinr3[8-1], dinr3[8-1:2]}; + tmp_27 <= {dinr4[8-1], dinr4[8-1:1]} + {dinr4[8-1], dinr4[8-1], dinr4[8-1:2]}; + + tmp_31 <= {dinr2[8-1], dinr2[8-1], dinr2[8-1], dinr2[8-1:3]}; + tmp_33 <= {dinr3[8-1], dinr3[8-1], dinr3[8-1], dinr3[8-1:3]}; + tmp_35 <= {dinr4[8-1], dinr4[8-1], dinr4[8-1], dinr4[8-1:3]}; + tmp_37 <= {dinr5[8-1], dinr5[8-1], dinr5[8-1], dinr5[8-1:3]}; + + add_tmp1 <= {tmp_11[8-1], tmp_11} + {tmp_21[8-1], tmp_21}; + add_tmp3 <= {tmp_13[8-1], tmp_13} + {tmp_23[8-1], tmp_23}; + add_tmp5 <= {tmp_15[8-1], tmp_15} + {tmp_25[8-1], tmp_25}; + add_tmp7 <= {tmp_17[8-1], tmp_17} + {tmp_27[8-1], tmp_27}; + + doutr_101 <= add_tmp1 - {tmp_31[8-1], tmp_31}; + doutr_103 <= add_tmp3 - {tmp_33[8-1], tmp_33}; + doutr_105 <= add_tmp5 - {tmp_35[8-1], tmp_35}; + doutr_107 <= add_tmp7 - {tmp_37[8-1], tmp_37}; + + doutr_108 <= {dinr4[8-1] , dinr4}; + + tmp_19 <= {dinr3[8-1], dinr3[8-1] , dinr3[8-1] , dinr3[8-1:3]}; + + tmp_29 <= {dinr4[8-1], dinr4[8-1:1]} + + {dinr4[8-1], dinr4[8-1] , dinr4[8-1:2]}; + + tmp_39 <= {dinr5[8-1] , dinr5[8-1] , dinr5[8-1:2]} + + {dinr5[8-1] , dinr5[8-1] , dinr5[8-1] , dinr5[8-1:3]}; + + add_tmp9 <= {tmp_29[8-1] , tmp_29} + + {tmp_39[8-1] , tmp_39}; + + doutr_109 <= add_tmp9 - {tmp_19[8-1] , tmp_19}; + + doutr_1010 <= {dinr5[8-1] , dinr5}; + + doutr0 <= doutr_100; + doutr2 <= doutr_101; + doutr4 <= doutr_102; + doutr6 <= doutr_103; + doutr8 <= doutr_104; + doutr10 <= doutr_105; + doutr12 <= doutr_106; + doutr14 <= doutr_107; + doutr16 <= doutr_108; + + tmp_1_101 <= {doutr_100[8] , doutr_100[8] , doutr_100[8:2]} + {doutr_100[8] , doutr_100[8] , doutr_100[8] , doutr_100[8:3]}; + tmp_1_103 <= {doutr_101[8] , doutr_101[8] , doutr_101[8:2]} + {doutr_101[8] , doutr_101[8] , doutr_101[8] , doutr_101[8:3]}; + tmp_1_105 <= {doutr_102[8] , doutr_102[8] , doutr_102[8:2]} + {doutr_102[8] , doutr_102[8] , doutr_102[8] , doutr_102[8:3]}; + tmp_1_107 <= {doutr_103[8] , doutr_103[8] , doutr_103[8:2]} + {doutr_103[8] , doutr_103[8] , doutr_103[8] , doutr_103[8:3]}; + tmp_1_109 <= {doutr_104[8] , doutr_104[8] , doutr_104[8:2]} + {doutr_104[8] , doutr_104[8] , doutr_104[8] , doutr_104[8:3]}; + tmp_1_1011 <= {doutr_105[8] , doutr_105[8] , doutr_105[8:2]} + {doutr_105[8] , doutr_105[8] , doutr_105[8] , doutr_105[8:3]}; + tmp_1_1013 <= {doutr_106[8] , doutr_106[8] , doutr_106[8:2]} + {doutr_106[8] , doutr_106[8] , doutr_106[8] , doutr_106[8:3]}; + tmp_1_1015 <= {doutr_107[8] , doutr_107[8] , doutr_107[8:2]} + {doutr_107[8] , doutr_107[8] , doutr_107[8] , doutr_107[8:3]}; + tmp_1_1017 <= {doutr_108[8] , doutr_108[8] , doutr_108[8:2]} + {doutr_108[8] , doutr_108[8] , doutr_108[8] , doutr_108[8:3]}; + + tmp_2_101 <= {doutr_101[8], doutr_101[8:1]} + {doutr_101[8], doutr_101[8] , doutr_101[8:2]}; + tmp_2_103 <= {doutr_102[8], doutr_102[8:1]} + {doutr_102[8], doutr_102[8] , doutr_102[8:2]}; + tmp_2_105 <= {doutr_103[8], doutr_103[8:1]} + {doutr_103[8], doutr_103[8] , doutr_103[8:2]}; + tmp_2_107 <= {doutr_104[8], doutr_104[8:1]} + {doutr_104[8], doutr_104[8] , doutr_104[8:2]}; + tmp_2_109 <= {doutr_105[8], doutr_105[8:1]} + {doutr_105[8], doutr_105[8] , doutr_105[8:2]}; + tmp_2_1011 <= {doutr_106[8], doutr_106[8:1]} + {doutr_106[8], doutr_106[8] , doutr_106[8:2]}; + tmp_2_1013 <= {doutr_107[8], doutr_107[8:1]} + {doutr_107[8], doutr_107[8] , doutr_107[8:2]}; + tmp_2_1015 <= {doutr_108[8], doutr_108[8:1]} + {doutr_108[8], doutr_108[8] , doutr_108[8:2]}; + tmp_2_1017 <= {doutr_109[8], doutr_109[8:1]} + {doutr_109[8], doutr_109[8] , doutr_109[8:2]}; + + tmp_3_101 <= {doutr_102[8], doutr_102[8] , doutr_102[8] , doutr_102[8:3]}; + tmp_3_103 <= {doutr_103[8], doutr_103[8] , doutr_103[8] , doutr_103[8:3]}; + tmp_3_105 <= {doutr_104[8], doutr_104[8] , doutr_104[8] , doutr_104[8:3]}; + tmp_3_107 <= {doutr_105[8], doutr_105[8] , doutr_105[8] , doutr_105[8:3]}; + tmp_3_109 <= {doutr_106[8], doutr_106[8] , doutr_106[8] , doutr_106[8:3]}; + tmp_3_1011 <= {doutr_107[8], doutr_107[8] , doutr_107[8] , doutr_107[8:3]}; + tmp_3_1013 <= {doutr_108[8], doutr_108[8] , doutr_108[8] , doutr_108[8:3]}; + tmp_3_1015 <= {doutr_109[8], doutr_109[8] , doutr_109[8] , doutr_109[8:3]}; + tmp_3_1017 <= {doutr_1010[8], doutr_1010[8] , doutr_1010[8] , doutr_1010[8:3]}; + + add_tmp_101 <= tmp_1_101 + tmp_2_101; + add_tmp_103 <= tmp_1_103 + tmp_2_103; + add_tmp_105 <= tmp_1_105 + tmp_2_105; + add_tmp_107 <= tmp_1_107 + tmp_2_107; + add_tmp_109 <= tmp_1_109 + tmp_2_109; + add_tmp_1011 <= tmp_1_1011 + tmp_2_1011; + add_tmp_1013 <= tmp_1_1013 + tmp_2_1013; + add_tmp_1015 <= tmp_1_1015 + tmp_2_1015; + add_tmp_1017 <= tmp_1_1017 + tmp_2_1017; + + doutr1 <= add_tmp_101 - tmp_3_101; + doutr3 <= add_tmp_103 - tmp_3_103; + doutr5 <= add_tmp_105 - tmp_3_105; + doutr7 <= add_tmp_107 - tmp_3_107; + doutr9 <= add_tmp_109 - tmp_3_109; + doutr11 <= add_tmp_1011 - tmp_3_1011; + doutr13 <= add_tmp_1013 - tmp_3_1013; + doutr15 <= add_tmp_1015 - tmp_3_1015; + doutr17 <= add_tmp_1017 - tmp_3_1017; + + doutr18 <= doutr_109; + + tmp_1_1019 <= {doutr_108[8], doutr_108[8] , doutr_108[8] , doutr_108[8:3]}; + + tmp_2_1019 <= {doutr_109[8], doutr_109[8:1]} + + {doutr_109[8], doutr_109[8] , doutr_109[8:2]}; + + tmp_3_1019 <= {doutr_1010[8] , doutr_1010[8] , doutr_1010[8:2]} + + {doutr_1010[8] , doutr_1010[8] , doutr_1010[8] , doutr_1010[8:3]}; + + add_tmp_1019 <= tmp_2_1019 + tmp_3_1019; + + doutr19 <= add_tmp_1019 - tmp_1_1019; + + doutr20 <= doutr_1010; + end +endmodule + + + +module find_max (clk, wen, + d_in0, + d_in1, + d_in2, + d_in3, + d_in4, + d_in5, + d_in6, + d_in7, + d_in8, + d_in9, + d_in10, + d_in11, + d_in12, + d_in13, + d_in14, + d_in15, + d_in16, + d_in17, + d_in18, + d_in19, + d_in20, +d_out, indx_out); + + input clk; + input wen; + input[10:0] d_in0; + input[10:0] d_in1; + input[10:0] d_in2; + input[10:0] d_in3; + input[10:0] d_in4; + input[10:0] d_in5; + input[10:0] d_in6; + input[10:0] d_in7; + input[10:0] d_in8; + input[10:0] d_in9; + input[10:0] d_in10; + input[10:0] d_in11; + input[10:0] d_in12; + input[10:0] d_in13; + input[10:0] d_in14; + input[10:0] d_in15; + input[10:0] d_in16; + input[10:0] d_in17; + input[10:0] d_in18; + input[10:0] d_in19; + input[10:0] d_in20; + reg[10:0] d_in_tmp0; + reg[10:0] d_in_tmp1; + reg[10:0] d_in_tmp2; + reg[10:0] d_in_tmp3; + reg[10:0] d_in_tmp4; + reg[10:0] d_in_tmp5; + reg[10:0] d_in_tmp6; + reg[10:0] d_in_tmp7; + reg[10:0] d_in_tmp8; + reg[10:0] d_in_tmp9; + reg[10:0] d_in_tmp10; + reg[10:0] d_in_tmp11; + reg[10:0] d_in_tmp12; + reg[10:0] d_in_tmp13; + reg[10:0] d_in_tmp14; + reg[10:0] d_in_tmp15; + reg[10:0] d_in_tmp16; + reg[10:0] d_in_tmp17; + reg[10:0] d_in_tmp18; + reg[10:0] d_in_tmp19; + reg[10:0] d_in_tmp20; + output[7:0] d_out; + reg[7:0] d_out; + output[4:0] indx_out; + reg[4:0] indx_out; + reg[10:0] res_1_1; + reg[10:0] res_1_2; + reg[10:0] res_1_3; + reg[10:0] res_1_4; + reg[10:0] res_1_5; + reg[10:0] res_1_6; + reg[10:0] res_1_7; + reg[10:0] res_1_8; + reg[10:0] res_1_9; + reg[10:0] res_1_10; + reg[10:0] res_1_11; + reg[10:0] res_2_1; + reg[10:0] res_2_2; + reg[10:0] res_2_3; + reg[10:0] res_2_4; + reg[10:0] res_2_5; + reg[10:0] res_2_6; + reg[10:0] res_3_1; + reg[10:0] res_3_2; + reg[10:0] res_3_3; + reg[10:0] res_4_1; + reg[10:0] res_4_2; + reg[10:0] res_5_1; + reg[4:0] indx_1_1; + reg[4:0] indx_1_2; + reg[4:0] indx_1_3; + reg[4:0] indx_1_4; + reg[4:0] indx_1_5; + reg[4:0] indx_1_6; + reg[4:0] indx_1_7; + reg[4:0] indx_1_8; + reg[4:0] indx_1_9; + reg[4:0] indx_1_10; + reg[4:0] indx_1_11; + reg[4:0] indx_2_1; + reg[4:0] indx_2_2; + reg[4:0] indx_2_3; + reg[4:0] indx_2_4; + reg[4:0] indx_2_5; + reg[4:0] indx_2_6; + reg[4:0] indx_3_1; + reg[4:0] indx_3_2; + reg[4:0] indx_3_3; + reg[4:0] indx_4_1; + reg[4:0] indx_4_2; + reg[4:0] indx_5_1; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + d_in_tmp0 <= d_in0 ; + d_in_tmp1 <= d_in1 ; + d_in_tmp2 <= d_in2 ; + d_in_tmp3 <= d_in3 ; + d_in_tmp4 <= d_in4 ; + d_in_tmp5<= d_in5 ; + d_in_tmp6 <= d_in6 ; + d_in_tmp7 <= d_in7 ; + d_in_tmp8 <= d_in8 ; + d_in_tmp9 <= d_in9 ; + d_in_tmp10 <= d_in10 ; + d_in_tmp11 <= d_in11 ; + d_in_tmp12 <= d_in12 ; + d_in_tmp13 <= d_in13 ; + d_in_tmp14 <= d_in14 ; + d_in_tmp15 <= d_in15; + d_in_tmp16 <= d_in16 ; + d_in_tmp17 <= d_in17 ; + d_in_tmp18 <= d_in18 ; + d_in_tmp19 <= d_in19 ; + d_in_tmp20 <= d_in20 ; + d_out <= res_5_1[10:3] ; + indx_out <= indx_5_1 ; + end + + if (d_in0 > d_in1) + begin + res_1_1 <= d_in0 ; + indx_1_1 <= 5'b00000 ; + end + else + begin + res_1_1 <= d_in1 ; + indx_1_1 <= 5'b00001 ; + end + if (d_in2 > d_in3) + begin + res_1_2 <= d_in2 ; + indx_1_2 <= 5'b00010 ; + end + else + begin + res_1_2 <= d_in3 ; + indx_1_2 <= 5'b00011 ; + end + if (d_in4 > d_in5) + begin + res_1_3 <= d_in4 ; + indx_1_3 <= 5'b00100 ; + end + else + begin + res_1_3 <= d_in5 ; + indx_1_3 <= 5'b00101 ; + end + if (d_in6 > d_in7) + begin + + res_1_4 <= d_in6 ; + indx_1_4 <= 5'b00110 ; + end + else + begin + res_1_4 <= d_in7 ; + indx_1_4 <= 5'b00111 ; + end + if (d_in8 > d_in9) + begin + res_1_5 <= d_in8 ; + indx_1_5 <= 5'b01000 ; + end + else + begin + res_1_5 <= d_in9 ; + indx_1_5 <= 5'b01001 ; + end + if (d_in10 > d_in11) + begin + res_1_6 <= d_in10 ; + indx_1_6 <= 5'b01010 ; + end + else + begin + res_1_6 <= d_in11 ; + indx_1_6 <= 5'b01011 ; + end + if (d_in12 > d_in13) + begin + res_1_7 <= d_in12 ; + indx_1_7 <= 5'b01100 ; + end + else + begin + res_1_7 <= d_in13 ; + indx_1_7 <= 5'b01101 ; + end + if (d_in14 > d_in15) + begin + res_1_8 <= d_in14 ; + indx_1_8 <= 5'b01110 ; + end + else + begin + res_1_8 <= d_in15 ; + indx_1_8 <= 5'b01111 ; + end + if (d_in16 > d_in17) + begin + res_1_9 <= d_in16 ; + indx_1_9 <= 5'b10000 ; + end + else + begin + res_1_9 <= d_in17 ; + indx_1_9 <= 5'b10001 ; + end + if (d_in18 > d_in19) + begin + res_1_10 <= d_in18 ; + indx_1_10 <= 5'b10010 ; + end + else + begin + res_1_10 <= d_in19 ; + indx_1_10 <= 5'b10011 ; + end + res_1_11 <= d_in20 ; + indx_1_11 <= 5'b10100 ; + if (res_1_1 > res_1_2) + begin + res_2_1 <= res_1_1 ; + indx_2_1 <= indx_1_1 ; + end + else + begin + res_2_1 <= res_1_2 ; + indx_2_1 <= indx_1_2 ; + end + if (res_1_3 > res_1_4) + begin + res_2_2 <= res_1_3 ; + indx_2_2 <= indx_1_3 ; + end + else + begin + res_2_2 <= res_1_4 ; + indx_2_2 <= indx_1_4 ; + end + if (res_1_5 > res_1_6) + begin + res_2_3 <= res_1_5 ; + indx_2_3 <= indx_1_5 ; + end + else + begin + res_2_3 <= res_1_6 ; + indx_2_3 <= indx_1_6 ; + end + if (res_1_7 > res_1_8) + begin + res_2_4 <= res_1_7 ; + indx_2_4 <= indx_1_7 ; + end + else + begin + res_2_4 <= res_1_8 ; + indx_2_4 <= indx_1_8 ; + end + if (res_1_9 > res_1_10) + begin + res_2_5 <= res_1_9 ; + indx_2_5 <= indx_1_9 ; + end + else + begin + res_2_5 <= res_1_10 ; + indx_2_5 <= indx_1_10 ; + end + res_2_6 <= res_1_11 ; + indx_2_6 <= indx_1_11 ; + if (res_2_1 > res_2_2) + begin + res_3_1 <= res_2_1 ; + indx_3_1 <= indx_2_1 ; + end + else + begin + res_3_1 <= res_2_2 ; + indx_3_1 <= indx_2_2 ; + end + if (res_2_3 > res_2_4) + begin + res_3_2 <= res_2_3 ; + indx_3_2 <= indx_2_3 ; + end + else + begin + res_3_2 <= res_2_4 ; + indx_3_2 <= indx_2_4 ; + end + if (res_2_5 > res_2_6) + begin + res_3_3 <= res_2_5 ; + indx_3_3 <= indx_2_5 ; + end + else + begin + res_3_3 <= res_2_6 ; + indx_3_3 <= indx_2_6 ; + end + if (res_3_1 > res_3_2) + begin + res_4_1 <= res_3_1 ; + indx_4_1 <= indx_3_1 ; + end + else + begin + res_4_1 <= res_3_2 ; + indx_4_1 <= indx_3_2 ; + end + res_4_2 <= res_3_3 ; + indx_4_2 <= indx_3_3 ; + if (res_4_1 > res_4_2) + begin + res_5_1 <= res_4_1 ; + indx_5_1 <= indx_4_1 ; + end + else + begin + res_5_1 <= res_4_2 ; + indx_5_1 <= indx_4_2 ; + end + end + endmodule + +module lp_fltr (clk, din, dout, ce); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input ce; + + reg[8 - 1:0] din_tmp_1; + reg[8 - 1:0] din_tmp_2; + reg[8 - 1:0] din_tmp_3; + reg[(8 + 2) - 1:0] sum_tmp_1; + reg[(8 + 2) - 1:0] sum_tmp_2; + reg[(8 + 2) - 1:0] sum_tmp_3; + reg[(8 + 2) - 1:0] add_tmp_1; + reg[(8 + 2) - 1:0] add_tmp_2; + + always @(posedge clk) + begin + if (ce == 1'b1) + begin + din_tmp_1 <= din ; + din_tmp_2 <= din_tmp_1 ; + din_tmp_3 <= din_tmp_2 ; + dout <= add_tmp_2[(8 + 2) - 1:2] ; + end + sum_tmp_1 <= {din_tmp_1[8 - 1], din_tmp_1[8 - 1], din_tmp_1} ; + sum_tmp_2 <= {din_tmp_2[8 - 1], din_tmp_2, 1'b0} ; + sum_tmp_3 <= {din_tmp_3[8 - 1], din_tmp_3[8 - 1], din_tmp_3} ; + add_tmp_1 <= sum_tmp_1 + sum_tmp_2 ; + add_tmp_2 <= add_tmp_1 + sum_tmp_3 ; + end +endmodule + + + + + +module port_bus_1to0_1 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_1to0, + v_corr_200, + v_corr_201, + v_corr_202, + v_corr_203, + v_corr_204, + v_corr_205, + v_corr_206, + v_corr_207, + v_corr_208, + v_corr_209, + v_corr_2010, + v_corr_2011, + v_corr_2012, + v_corr_2013, + v_corr_2014, + v_corr_2015, + v_corr_2016, + v_corr_2017, + v_corr_2018, + v_corr_2019, + v_corr_2020, +vidin_new_data_scld_2_1to0, + v_corr_100, + v_corr_101, + v_corr_102, + v_corr_103, + v_corr_104, + v_corr_105, + v_corr_106, + v_corr_107, + v_corr_108, + v_corr_109, + v_corr_1010, +vidin_new_data_scld_4_1to0, + v_corr_50, + v_corr_51, + v_corr_52, + v_corr_53, + v_corr_54, + v_corr_55, +bus_word_1, bus_word_2, bus_word_3, bus_word_4, bus_word_5, bus_word_6, counter_out); + + + input clk; + output[18:0] vidin_addr_reg; + reg[18:0] vidin_addr_reg; + output svid_comp_switch; + reg svid_comp_switch; + output vidin_new_data_scld_1_1to0; + reg vidin_new_data_scld_1_1to0; + output[7:0] v_corr_200; + output[7:0] v_corr_201; + output[7:0] v_corr_202; + output[7:0] v_corr_203; + output[7:0] v_corr_204; + output[7:0] v_corr_205; + output[7:0] v_corr_206; + output[7:0] v_corr_207; + output[7:0] v_corr_208; + output[7:0] v_corr_209; + output[7:0] v_corr_2010; + output[7:0] v_corr_2011; + output[7:0] v_corr_2012; + output[7:0] v_corr_2013; + output[7:0] v_corr_2014; + output[7:0] v_corr_2015; + output[7:0] v_corr_2016; + output[7:0] v_corr_2017; + output[7:0] v_corr_2018; + output[7:0] v_corr_2019; + output[7:0] v_corr_2020; + reg[7:0] v_corr_200; + reg[7:0] v_corr_201; + reg[7:0] v_corr_202; + reg[7:0] v_corr_203; + reg[7:0] v_corr_204; + reg[7:0] v_corr_205; + reg[7:0] v_corr_206; + reg[7:0] v_corr_207; + reg[7:0] v_corr_208; + reg[7:0] v_corr_209; + reg[7:0] v_corr_2010; + reg[7:0] v_corr_2011; + reg[7:0] v_corr_2012; + reg[7:0] v_corr_2013; + reg[7:0] v_corr_2014; + reg[7:0] v_corr_2015; + reg[7:0] v_corr_2016; + reg[7:0] v_corr_2017; + reg[7:0] v_corr_2018; + reg[7:0] v_corr_2019; + reg[7:0] v_corr_2020; + output vidin_new_data_scld_2_1to0; + reg vidin_new_data_scld_2_1to0; + output[7:0] v_corr_100; + output[7:0] v_corr_101; + output[7:0] v_corr_102; + output[7:0] v_corr_103; + output[7:0] v_corr_104; + output[7:0] v_corr_105; + output[7:0] v_corr_106; + output[7:0] v_corr_107; + output[7:0] v_corr_108; + output[7:0] v_corr_109; + output[7:0] v_corr_1010; + reg[7:0] v_corr_100; + reg[7:0] v_corr_101; + reg[7:0] v_corr_102; + reg[7:0] v_corr_103; + reg[7:0] v_corr_104; + reg[7:0] v_corr_105; + reg[7:0] v_corr_106; + reg[7:0] v_corr_107; + reg[7:0] v_corr_108; + reg[7:0] v_corr_109; + reg[7:0] v_corr_1010; + output vidin_new_data_scld_4_1to0; + reg vidin_new_data_scld_4_1to0; + output[7:0] v_corr_50; + output[7:0] v_corr_51; + output[7:0] v_corr_52; + output[7:0] v_corr_53; + output[7:0] v_corr_54; + output[7:0] v_corr_55; + reg[7:0] v_corr_50; + reg[7:0] v_corr_51; + reg[7:0] v_corr_52; + reg[7:0] v_corr_53; + reg[7:0] v_corr_54; + reg[7:0] v_corr_55; + input[7:0] bus_word_1; + input[7:0] bus_word_2; + input[7:0] bus_word_3; + input[7:0] bus_word_4; + input[7:0] bus_word_5; + input[7:0] bus_word_6; + input[2:0] counter_out; + + reg[7:0] bus_word_1_tmp; + reg[7:0] bus_word_2_tmp; + reg[7:0] bus_word_3_tmp; + reg[7:0] bus_word_4_tmp; + reg[7:0] bus_word_5_tmp; + reg[7:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; + wire vidin_new_data_scld_1_1to0_tmp; + wire vidin_new_data_scld_2_1to0_tmp; + wire vidin_new_data_scld_4_1to0_tmp; + reg[2:0] counter_out_tmp; + reg[7:0] v_corr_20_tmp0; + reg[7:0] v_corr_20_tmp1; + reg[7:0] v_corr_20_tmp2; + reg[7:0] v_corr_20_tmp3; + reg[7:0] v_corr_20_tmp4; + reg[7:0] v_corr_20_tmp5; + reg[7:0] v_corr_20_tmp6; + reg[7:0] v_corr_20_tmp7; + reg[7:0] v_corr_20_tmp8; + reg[7:0] v_corr_20_tmp9; + reg[7:0] v_corr_20_tmp10; + reg[7:0] v_corr_20_tmp11; + reg[7:0] v_corr_20_tmp12; + reg[7:0] v_corr_20_tmp13; + reg[7:0] v_corr_20_tmp14; + reg[7:0] v_corr_20_tmp15; + reg[7:0] v_corr_20_tmp16; + reg[7:0] v_corr_20_tmp17; + reg[7:0] v_corr_20_tmp18; + reg[7:0] v_corr_20_tmp19; + reg[7:0] v_corr_20_tmp20; + reg[7:0] v_corr_10_tmp0; + reg[7:0] v_corr_10_tmp1; + reg[7:0] v_corr_10_tmp2; + reg[7:0] v_corr_10_tmp3; + reg[7:0] v_corr_10_tmp4; + reg[7:0] v_corr_10_tmp5; + reg[7:0] v_corr_10_tmp6; + reg[7:0] v_corr_10_tmp7; + reg[7:0] v_corr_10_tmp8; + reg[7:0] v_corr_10_tmp9; + reg[7:0] v_corr_10_tmp10; + reg[7:0] v_corr_5_tmp0; + reg[7:0] v_corr_5_tmp1; + reg[7:0] v_corr_5_tmp2; + reg[7:0] v_corr_5_tmp3; + reg[7:0] v_corr_5_tmp4; + reg[7:0] v_corr_5_tmp5; + + always @(posedge clk) + begin + case (counter_out_tmp[2:0]) + 3'b001 : + begin + vidin_addr_reg_tmp[7:0] <= bus_word_1_tmp ; + vidin_addr_reg_tmp[15:8] <= bus_word_2_tmp ; + vidin_addr_reg_tmp[18:16] <= bus_word_3_tmp[7:5] ; + svid_comp_switch_tmp <= bus_word_3_tmp[4] ; + v_corr_5_tmp0 <= bus_word_4_tmp ; + v_corr_5_tmp1 <= bus_word_5_tmp ; + v_corr_5_tmp2 <= bus_word_6_tmp ; + end + 3'b010 : + begin + v_corr_5_tmp3 <= bus_word_1_tmp ; + v_corr_5_tmp4 <= bus_word_2_tmp ; + v_corr_5_tmp5 <= bus_word_3_tmp ; + v_corr_10_tmp0 <= bus_word_4_tmp ; + v_corr_10_tmp1 <= bus_word_5_tmp ; + v_corr_10_tmp2 <= bus_word_6_tmp ; + end + 3'b011 : + begin + v_corr_10_tmp3 <= bus_word_1_tmp ; + v_corr_10_tmp4 <= bus_word_2_tmp ; + v_corr_10_tmp5 <= bus_word_3_tmp ; + v_corr_10_tmp6 <= bus_word_4_tmp ; + v_corr_10_tmp7 <= bus_word_5_tmp ; + v_corr_10_tmp8 <= bus_word_6_tmp ; + end + 3'b100 : + begin + v_corr_10_tmp9 <= bus_word_1_tmp ; + v_corr_10_tmp10 <= bus_word_2_tmp ; + v_corr_20_tmp0 <= bus_word_3_tmp ; + v_corr_20_tmp1 <= bus_word_4_tmp ; + v_corr_20_tmp2 <= bus_word_5_tmp ; + v_corr_20_tmp3 <= bus_word_6_tmp ; + end + 3'b101 : + begin + v_corr_20_tmp4 <= bus_word_1_tmp ; + v_corr_20_tmp5 <= bus_word_2_tmp ; + v_corr_20_tmp6 <= bus_word_3_tmp ; + v_corr_20_tmp7 <= bus_word_4_tmp ; + v_corr_20_tmp8 <= bus_word_5_tmp ; + v_corr_20_tmp9 <= bus_word_6_tmp ; + end + 3'b110 : + begin + v_corr_20_tmp10 <= bus_word_1_tmp ; + v_corr_20_tmp11 <= bus_word_2_tmp ; + v_corr_20_tmp12 <= bus_word_3_tmp ; + v_corr_20_tmp13 <= bus_word_4_tmp ; + v_corr_20_tmp14 <= bus_word_5_tmp ; + v_corr_20_tmp15 <= bus_word_6_tmp ; + end + 3'b111 : + begin + v_corr_20_tmp16 <= bus_word_1_tmp ; + v_corr_20_tmp17 <= bus_word_2_tmp ; + v_corr_20_tmp18 <= bus_word_3_tmp ; + v_corr_20_tmp19 <= bus_word_4_tmp ; + v_corr_20_tmp20 <= bus_word_5_tmp ; + end + default : + begin + v_corr_20_tmp16 <= bus_word_1_tmp ; + v_corr_20_tmp17 <= bus_word_2_tmp ; + v_corr_20_tmp18 <= bus_word_3_tmp ; + v_corr_20_tmp19 <= bus_word_4_tmp ; + v_corr_20_tmp20 <= bus_word_5_tmp ; + end + endcase + end + + always @(posedge clk) + begin + counter_out_tmp <= counter_out ; + bus_word_1_tmp <= bus_word_1 ; + bus_word_2_tmp <= bus_word_2 ; + bus_word_3_tmp <= bus_word_3 ; + bus_word_4_tmp <= bus_word_4 ; + bus_word_5_tmp <= bus_word_5 ; + bus_word_6_tmp <= bus_word_6 ; + end + + always @(posedge clk) + begin + if (counter_out_tmp == 3'b001) + begin + vidin_addr_reg <= vidin_addr_reg_tmp ; + svid_comp_switch <= svid_comp_switch_tmp ; + if (vidin_addr_reg_tmp[8:0] != 9'b000000000) + begin + vidin_new_data_scld_1_1to0 <= 1'b1 ; + if ((vidin_addr_reg_tmp[0]) == 1'b0 & (vidin_addr_reg_tmp[9]) == 1'b0) + begin + vidin_new_data_scld_2_1to0 <= 1'b1 ; + if ((vidin_addr_reg_tmp[1]) == 1'b0 & (vidin_addr_reg_tmp[10]) == 1'b0) + begin + vidin_new_data_scld_4_1to0 <= 1'b1 ; + end + else + begin + vidin_new_data_scld_4_1to0 <= 1'b0 ; + end + end + else + begin + vidin_new_data_scld_2_1to0 <= 1'b0 ; + vidin_new_data_scld_4_1to0 <= 1'b0 ; + end + end + else + begin + vidin_new_data_scld_1_1to0 <= 1'b0 ; + vidin_new_data_scld_4_1to0 <= 1'b0 ; + vidin_new_data_scld_2_1to0 <= 1'b0 ; + end + v_corr_50 <= v_corr_5_tmp0 ; + v_corr_51 <= v_corr_5_tmp1 ; + v_corr_52 <= v_corr_5_tmp2 ; + v_corr_53 <= v_corr_5_tmp3 ; + v_corr_54 <= v_corr_5_tmp4 ; + v_corr_55 <= v_corr_5_tmp5 ; + v_corr_100 <= v_corr_10_tmp0 ; + v_corr_101 <= v_corr_10_tmp1 ; + v_corr_102 <= v_corr_10_tmp2 ; + v_corr_103 <= v_corr_10_tmp3 ; + v_corr_104 <= v_corr_10_tmp4 ; + v_corr_105 <= v_corr_10_tmp5 ; + v_corr_106 <= v_corr_10_tmp6 ; + v_corr_107 <= v_corr_10_tmp7 ; + v_corr_108 <= v_corr_10_tmp8 ; + v_corr_109 <= v_corr_10_tmp9 ; + v_corr_1010 <= v_corr_10_tmp10 ; + v_corr_200 <= v_corr_20_tmp0 ; + v_corr_201 <= v_corr_20_tmp1 ; + v_corr_202 <= v_corr_20_tmp2 ; + v_corr_203 <= v_corr_20_tmp3 ; + v_corr_204 <= v_corr_20_tmp4 ; + v_corr_205 <= v_corr_20_tmp5 ; + v_corr_206 <= v_corr_20_tmp6 ; + v_corr_207 <= v_corr_20_tmp7 ; + v_corr_208 <= v_corr_20_tmp8 ; + v_corr_209 <= v_corr_20_tmp9 ; + v_corr_2010 <= v_corr_20_tmp10 ; + v_corr_2011 <= v_corr_20_tmp11 ; + v_corr_2012 <= v_corr_20_tmp12 ; + v_corr_2013 <= v_corr_20_tmp13 ; + v_corr_2014 <= v_corr_20_tmp14 ; + v_corr_2015 <= v_corr_20_tmp15 ; + v_corr_2016 <= v_corr_20_tmp16 ; + v_corr_2017 <= v_corr_20_tmp17 ; + v_corr_2018 <= v_corr_20_tmp18 ; + v_corr_2019 <= v_corr_20_tmp19 ; + v_corr_2020 <= v_corr_20_tmp20 ; + end + else + begin + vidin_new_data_scld_1_1to0 <= 1'b0 ; + vidin_new_data_scld_2_1to0 <= 1'b0 ; + vidin_new_data_scld_4_1to0 <= 1'b0 ; + end + end +endmodule + + + +module my_fifo_496 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + // Fifo size log(FIFO_SIZE)/log2 + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_316 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_2 (clk, din, dout, rdy); + + + input clk; + input[9 - 1:0] din; + output[9 - 1:0] dout; + reg[9 - 1:0] dout; + input rdy; + + reg[9-1:0]buff1; + reg[9-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_1 (clk, din, dout, rdy); + + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_89 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_179 (clk, din, dout, rdy); + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule + +module my_fifo_359 (clk, din, dout, rdy); + + + input clk; + input[8 - 1:0] din; + output[8 - 1:0] dout; + reg[8 - 1:0] dout; + input rdy; + + reg[8-1:0]buff1; + reg[8-1:0]buff2; + + + always @(posedge clk) + begin + if (rdy == 1'b1) + begin + buff1 <= din; + dout <= buff2; + buff2 <= buff1; + + end + end +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v new file mode 100755 index 000000000..5a9765831 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v @@ -0,0 +1,2553 @@ +// created by Ahmad darabiha +// last updated Aug. 2002 +// this is the design for chip #1 of stereo +// vision system. this chip mainly performs the +// normalization and correlation in two orienations +// and 3 scales. + + +module sv_chip1_hierarchy_no_mem ( + tm3_clk_v0, bus_word_3_2to1, bus_word_4_2to1, bus_word_5_2to1, bus_word_6_2to1, counter_out_2to1, + bus_word_1_1to0, bus_word_2_1to0, bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, + counter_out_1to0,q, offchip_sram_data_in, offchip_sram_addr, offchip_sram_data_out, offchip_sram_we, offchip_sram_oe, rst +); + input [63:0]offchip_sram_data_in; + output [18:0]offchip_sram_addr; + output [63:0]offchip_sram_data_out; + output [7:0]offchip_sram_we; + output [1:0]offchip_sram_oe; + + input rst; + input tm3_clk_v0; + wire[63:0] tm3_sram_data_in; + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + output q; + assign q = |tm3_sram_data_in; + + reg[18:0] tm3_sram_addr; + + reg[7:0] tm3_sram_we; + + reg[1:0] tm3_sram_oe; + + reg tm3_sram_adsp; + input[15:0] bus_word_3_2to1; + input[15:0] bus_word_4_2to1; + input[15:0] bus_word_5_2to1; + input[15:0] bus_word_6_2to1; + input[2:0] counter_out_2to1; + output[7:0] bus_word_1_1to0; + wire[7:0] bus_word_1_1to0; + output[7:0] bus_word_2_1to0; + wire[7:0] bus_word_2_1to0; + output[7:0] bus_word_3_1to0; + wire[7:0] bus_word_3_1to0; + output[7:0] bus_word_4_1to0; + wire[7:0] bus_word_4_1to0; + output[7:0] bus_word_5_1to0; + wire[7:0] bus_word_5_1to0; + output[7:0] bus_word_6_1to0; + wire[7:0] bus_word_6_1to0; + output[2:0] counter_out_1to0; + wire[2:0] counter_out_1to0; + + reg[9:0] horiz; + reg[9:0] vert; + reg[63:0] vidin_data_buf_sc_1; + reg[55:0] vidin_data_buf_2_sc_1; + reg[18:0] vidin_addr_buf_sc_1; + reg[63:0] vidin_data_buf_sc_2; + reg[55:0] vidin_data_buf_2_sc_2; + reg[18:0] vidin_addr_buf_sc_2; + reg[63:0] vidin_data_buf_sc_4; + reg[55:0] vidin_data_buf_2_sc_4; + reg[18:0] vidin_addr_buf_sc_4; + reg video_state; + + reg vidin_new_data_scld_1_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_left_reg; + reg vidin_new_data_scld_2_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_left_reg; + reg vidin_new_data_scld_4_2to3_left_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_left_reg; + reg vidin_new_data_scld_1_2to3_right_reg; + reg[7:0] vidin_data_reg_scld_1_2to3_right_reg; + reg vidin_new_data_scld_2_2to3_right_reg; + reg[7:0] vidin_data_reg_scld_2_2to3_right_reg; + reg vidin_new_data_scld_4_2to3_right_reg; + reg[7:0] vidin_data_reg_scld_4_2to3_right_reg; + reg[18:0] vidin_addr_reg_2to3_reg; + wire vidin_new_data_scld_1_2to3_left; + wire[15:0] vidin_data_reg_scld_1_2to3_left_rz; + wire[15:0] vidin_data_reg_scld_1_2to3_left_iz; + wire[15:0] vidin_data_reg_scld_1_2to3_left_rp; + wire[15:0] vidin_data_reg_scld_1_2to3_left_ip; + wire[15:0] vidin_data_reg_scld_1_2to3_left_rn; + wire[15:0] vidin_data_reg_scld_1_2to3_left_in; + wire vidin_new_data_scld_2_2to3_left; + wire[15:0] vidin_data_reg_scld_2_2to3_left_rz; + wire[15:0] vidin_data_reg_scld_2_2to3_left_iz; + wire[15:0] vidin_data_reg_scld_2_2to3_left_rp; + wire[15:0] vidin_data_reg_scld_2_2to3_left_ip; + wire[15:0] vidin_data_reg_scld_2_2to3_left_rn; + wire[15:0] vidin_data_reg_scld_2_2to3_left_in; + wire vidin_new_data_scld_4_2to3_left; + wire[15:0] vidin_data_reg_scld_4_2to3_left_rz; + wire[15:0] vidin_data_reg_scld_4_2to3_left_iz; + wire[15:0] vidin_data_reg_scld_4_2to3_left_rp; + wire[15:0] vidin_data_reg_scld_4_2to3_left_ip; + wire[15:0] vidin_data_reg_scld_4_2to3_left_rn; + wire[15:0] vidin_data_reg_scld_4_2to3_left_in; + wire vidin_new_data_scld_1_2to3_right; + wire[15:0] vidin_data_reg_scld_1_2to3_right_rz; + wire[15:0] vidin_data_reg_scld_1_2to3_right_iz; + wire[15:0] vidin_data_reg_scld_1_2to3_right_rp; + wire[15:0] vidin_data_reg_scld_1_2to3_right_ip; + wire[15:0] vidin_data_reg_scld_1_2to3_right_rn; + wire[15:0] vidin_data_reg_scld_1_2to3_right_in; + wire vidin_new_data_scld_2_2to3_right; + wire[15:0] vidin_data_reg_scld_2_2to3_right_rz; + wire[15:0] vidin_data_reg_scld_2_2to3_right_iz; + wire[15:0] vidin_data_reg_scld_2_2to3_right_rp; + wire[15:0] vidin_data_reg_scld_2_2to3_right_ip; + wire[15:0] vidin_data_reg_scld_2_2to3_right_rn; + wire[15:0] vidin_data_reg_scld_2_2to3_right_in; + wire vidin_new_data_scld_4_2to3_right; + wire[15:0] vidin_data_reg_scld_4_2to3_right_rz; + wire[15:0] vidin_data_reg_scld_4_2to3_right_iz; + wire[15:0] vidin_data_reg_scld_4_2to3_right_rp; + wire[15:0] vidin_data_reg_scld_4_2to3_right_ip; + wire[15:0] vidin_data_reg_scld_4_2to3_right_rn; + wire[15:0] vidin_data_reg_scld_4_2to3_right_in; + wire[18:0] vidin_addr_reg_2to3; + wire svid_comp_switch_2to3; + wire[15:0] corr_out_1_p0; + wire[15:0] corr_out_1_p1; + wire[15:0] corr_out_1_p2; + wire[15:0] corr_out_1_p3; + wire[15:0] corr_out_1_p4; + wire[15:0] corr_out_1_p5; + wire[15:0] corr_out_1_p6; + wire[15:0] corr_out_1_p7; + wire[15:0] corr_out_1_p8; + wire[15:0] corr_out_1_p9; + wire[15:0] corr_out_1_p10; + wire[15:0] corr_out_1_p11; + wire[15:0] corr_out_1_p12; + wire[15:0] corr_out_1_p13; + wire[15:0] corr_out_1_p14; + wire[15:0] corr_out_1_p15; + wire[15:0] corr_out_1_p16; + wire[15:0] corr_out_1_p17; + wire[15:0] corr_out_1_p18; + wire[15:0] corr_out_1_p19; + wire[15:0] corr_out_1_p20; + wire[15:0] corr_out_1_n0; + wire[15:0] corr_out_1_n1; + wire[15:0] corr_out_1_n2; + wire[15:0] corr_out_1_n3; + wire[15:0] corr_out_1_n4; + wire[15:0] corr_out_1_n5; + wire[15:0] corr_out_1_n6; + wire[15:0] corr_out_1_n7; + wire[15:0] corr_out_1_n8; + wire[15:0] corr_out_1_n9; + wire[15:0] corr_out_1_n10; + wire[15:0] corr_out_1_n11; + wire[15:0] corr_out_1_n12; + wire[15:0] corr_out_1_n13; + wire[15:0] corr_out_1_n14; + wire[15:0] corr_out_1_n15; + wire[15:0] corr_out_1_n16; + wire[15:0] corr_out_1_n17; + wire[15:0] corr_out_1_n18; + wire[15:0] corr_out_1_n19; + wire[15:0] corr_out_1_n20; + reg[17:0] corr_out_10; + reg[17:0] corr_out_11; + reg[17:0] corr_out_12; + reg[17:0] corr_out_13; + reg[17:0] corr_out_14; + reg[17:0] corr_out_15; + reg[17:0] corr_out_16; + reg[17:0] corr_out_17; + reg[17:0] corr_out_18; + reg[17:0] corr_out_19; + reg[17:0] corr_out_110; + reg[17:0] corr_out_111; + reg[17:0] corr_out_112; + reg[17:0] corr_out_113; + reg[17:0] corr_out_114; + reg[17:0] corr_out_115; + reg[17:0] corr_out_116; + reg[17:0] corr_out_117; + reg[17:0] corr_out_118; + reg[17:0] corr_out_119; + reg[17:0] corr_out_120; + wire[15:0] corr_out_2_p0; + wire[15:0] corr_out_2_p1; + wire[15:0] corr_out_2_p2; + wire[15:0] corr_out_2_p3; + wire[15:0] corr_out_2_p4; + wire[15:0] corr_out_2_p5; + wire[15:0] corr_out_2_p6; + wire[15:0] corr_out_2_p7; + wire[15:0] corr_out_2_p8; + wire[15:0] corr_out_2_p9; + wire[15:0] corr_out_2_p10; + wire[15:0] corr_out_2_n0; + wire[15:0] corr_out_2_n1; + wire[15:0] corr_out_2_n2; + wire[15:0] corr_out_2_n3; + wire[15:0] corr_out_2_n4; + wire[15:0] corr_out_2_n5; + wire[15:0] corr_out_2_n6; + wire[15:0] corr_out_2_n7; + wire[15:0] corr_out_2_n8; + wire[15:0] corr_out_2_n9; + wire[15:0] corr_out_2_n10; + reg[17:0] corr_out_20; + reg[17:0] corr_out_21; + reg[17:0] corr_out_22; + reg[17:0] corr_out_23; + reg[17:0] corr_out_24; + reg[17:0] corr_out_25; + reg[17:0] corr_out_26; + reg[17:0] corr_out_27; + reg[17:0] corr_out_28; + reg[17:0] corr_out_29; + reg[17:0] corr_out_210; + wire[15:0] corr_out_4_p0; + wire[15:0] corr_out_4_p1; + wire[15:0] corr_out_4_p2; + wire[15:0] corr_out_4_p3; + wire[15:0] corr_out_4_p4; + wire[15:0] corr_out_4_p5; + wire[15:0] corr_out_4_n0; + wire[15:0] corr_out_4_n1; + wire[15:0] corr_out_4_n2; + wire[15:0] corr_out_4_n3; + wire[15:0] corr_out_4_n4; + wire[15:0] corr_out_4_n5; + reg[17:0] corr_out_40; + reg[17:0] corr_out_41; + reg[17:0] corr_out_42; + reg[17:0] corr_out_43; + reg[17:0] corr_out_44; + reg[17:0] corr_out_45; + + assign tm3_sram_data_in = offchip_sram_data_in; + assign offchip_sram_addr = tm3_sram_addr; + assign offchip_sram_data_out = tm3_sram_data_out; + assign offchip_sram_we = tm3_sram_we; + assign offchip_sram_oe = tm3_sram_oe; + + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + port_bus_2to1_1 port_bus_2to1_1_inst (tm3_clk_v0, vidin_addr_reg_2to3, svid_comp_switch_2to3, vidin_new_data_scld_1_2to3_left, + vidin_data_reg_scld_1_2to3_left_rp, vidin_data_reg_scld_1_2to3_left_ip, vidin_data_reg_scld_1_2to3_left_rn, + vidin_data_reg_scld_1_2to3_left_in, vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_left_rp, + vidin_data_reg_scld_2_2to3_left_ip, vidin_data_reg_scld_2_2to3_left_rn, vidin_data_reg_scld_2_2to3_left_in, + vidin_new_data_scld_4_2to3_left, vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, + vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, vidin_new_data_scld_1_2to3_right, + vidin_data_reg_scld_1_2to3_right_rp, vidin_data_reg_scld_1_2to3_right_ip, vidin_data_reg_scld_1_2to3_right_rn, + vidin_data_reg_scld_1_2to3_right_in, vidin_new_data_scld_2_2to3_right, vidin_data_reg_scld_2_2to3_right_rp, + vidin_data_reg_scld_2_2to3_right_ip, vidin_data_reg_scld_2_2to3_right_rn, vidin_data_reg_scld_2_2to3_right_in, + vidin_new_data_scld_4_2to3_right, vidin_data_reg_scld_4_2to3_right_rp, vidin_data_reg_scld_4_2to3_right_ip, + vidin_data_reg_scld_4_2to3_right_rn, vidin_data_reg_scld_4_2to3_right_in, bus_word_3_2to1, bus_word_4_2to1, + bus_word_5_2to1, bus_word_6_2to1, counter_out_2to1, rst); + + wrapper_norm_corr_20 wrapper_norm_corr_20_inst_p( + tm3_clk_v0, vidin_new_data_scld_1_2to3_left, vidin_data_reg_scld_1_2to3_right_rp, vidin_data_reg_scld_1_2to3_right_ip, vidin_data_reg_scld_1_2to3_left_rp, + vidin_data_reg_scld_1_2to3_left_ip, corr_out_1_p0, corr_out_1_p1, corr_out_1_p2, corr_out_1_p3, corr_out_1_p4, corr_out_1_p5, corr_out_1_p6, + corr_out_1_p7, corr_out_1_p8, corr_out_1_p9, corr_out_1_p10, corr_out_1_p11, corr_out_1_p12, corr_out_1_p13, corr_out_1_p14, corr_out_1_p15, + corr_out_1_p16, corr_out_1_p17, corr_out_1_p18, corr_out_1_p19, corr_out_1_p20 + ); + + wrapper_norm_corr_20 wrapper_norm_corr_20_inst_n(tm3_clk_v0, vidin_new_data_scld_1_2to3_left, vidin_data_reg_scld_1_2to3_right_rn, + vidin_data_reg_scld_1_2to3_right_in, vidin_data_reg_scld_1_2to3_left_rn, vidin_data_reg_scld_1_2to3_left_in, corr_out_1_n0, + corr_out_1_n1, corr_out_1_n2, corr_out_1_n3, corr_out_1_n4, corr_out_1_n5, corr_out_1_n6, corr_out_1_n7, corr_out_1_n8, + corr_out_1_n9, corr_out_1_n10, corr_out_1_n11, corr_out_1_n12, corr_out_1_n13, corr_out_1_n14, corr_out_1_n15, corr_out_1_n16, + corr_out_1_n17, corr_out_1_n18, corr_out_1_n19, corr_out_1_n20 + ); + + wrapper_norm_corr_10 wrapper_norm_corr_10_inst_p(tm3_clk_v0, vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_right_rp, + vidin_data_reg_scld_2_2to3_right_ip, vidin_data_reg_scld_2_2to3_left_rp, vidin_data_reg_scld_2_2to3_left_ip, corr_out_2_p0, + corr_out_2_p1, corr_out_2_p2, corr_out_2_p3, corr_out_2_p4, corr_out_2_p5, corr_out_2_p6, corr_out_2_p7, corr_out_2_p8, + corr_out_2_p9, corr_out_2_p10 + ); + + wrapper_norm_corr_10 wrapper_norm_corr_10_inst_n(tm3_clk_v0, vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_right_rn, + vidin_data_reg_scld_2_2to3_right_in, vidin_data_reg_scld_2_2to3_left_rn, vidin_data_reg_scld_2_2to3_left_in, corr_out_2_n0, + corr_out_2_n1, corr_out_2_n2, corr_out_2_n3, corr_out_2_n4, corr_out_2_n5, corr_out_2_n6, corr_out_2_n7, corr_out_2_n8, + corr_out_2_n9, corr_out_2_n10 + ); + + wrapper_norm_corr_5_seq wrapper_norm_corr_5_inst_p(tm3_clk_v0, vidin_new_data_scld_4_2to3_left, vidin_data_reg_scld_4_2to3_right_rp, + vidin_data_reg_scld_4_2to3_right_ip, vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, corr_out_4_p0, + corr_out_4_p1, corr_out_4_p2, corr_out_4_p3, corr_out_4_p4, corr_out_4_p5 + ); + + wrapper_norm_corr_5_seq wrapper_norm_corr_5_inst_n(tm3_clk_v0, vidin_new_data_scld_4_2to3_left, vidin_data_reg_scld_4_2to3_right_rn, + vidin_data_reg_scld_4_2to3_right_in, vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, corr_out_4_n0, + corr_out_4_n1, corr_out_4_n2, corr_out_4_n3, corr_out_4_n4, corr_out_4_n5); + + port_bus_1to0 port_bus_1to0_inst(tm3_clk_v0, vidin_addr_reg_2to3, svid_comp_switch_2to3, vidin_new_data_scld_1_2to3_left, + {corr_out_40[17], corr_out_40[15:9]}, {corr_out_41[17], corr_out_41[15:9]}, {corr_out_42[17], corr_out_42[15:9]}, + {corr_out_43[17], corr_out_43[15:9]}, {corr_out_44[17], corr_out_44[15:9]}, {corr_out_45[17], corr_out_45[15:9]}, + {corr_out_20[17], corr_out_20[15:9]}, {corr_out_21[17], corr_out_21[15:9]}, {corr_out_22[17], corr_out_22[15:9]}, + {corr_out_23[17], corr_out_23[15:9]}, {corr_out_24[17], corr_out_24[15:9]}, {corr_out_25[17], corr_out_25[15:9]}, + {corr_out_26[17], corr_out_26[15:9]}, {corr_out_27[17], corr_out_27[15:9]}, {corr_out_28[17], corr_out_28[15:9]}, + {corr_out_29[17], corr_out_29[15:9]}, {corr_out_210[17], corr_out_210[15:9]}, {corr_out_10[17], corr_out_10[15:9]}, + {corr_out_11[17], corr_out_11[15:9]}, {corr_out_12[17], corr_out_12[15:9]}, {corr_out_13[17], corr_out_13[15:9]}, + {corr_out_14[17], corr_out_14[15:9]}, {corr_out_15[17], corr_out_15[15:9]}, {corr_out_16[17], corr_out_16[15:9]}, + {corr_out_17[17], corr_out_17[15:9]}, {corr_out_18[17], corr_out_18[15:9]}, {corr_out_19[17], corr_out_19[15:9]}, + {corr_out_110[17], corr_out_110[15:9]}, {corr_out_111[17], corr_out_111[15:9]}, {corr_out_112[17], corr_out_112[15:9]}, + {corr_out_113[17], corr_out_113[15:9]}, {corr_out_114[17], corr_out_114[15:9]}, {corr_out_115[17], corr_out_115[15:9]}, + {corr_out_116[17], corr_out_116[15:9]}, {corr_out_117[17], corr_out_117[15:9]}, {corr_out_118[17], corr_out_118[15:9]}, + {corr_out_119[17], corr_out_119[15:9]}, {corr_out_120[17], corr_out_120[15:9]}, bus_word_1_1to0, bus_word_2_1to0, + bus_word_3_1to0, bus_word_4_1to0, bus_word_5_1to0, bus_word_6_1to0, counter_out_1to0, rst); + + always @(posedge tm3_clk_v0) + begin + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + corr_out_10 <= ({ corr_out_1_p0[15], corr_out_1_p0[15], corr_out_1_p0}) + ({corr_out_1_n0[15], corr_out_1_n0[15], corr_out_1_n0}) ; + corr_out_11 <= ({ corr_out_1_p1[15], corr_out_1_p1[15], corr_out_1_p1}) + ({corr_out_1_n1[15], corr_out_1_n1[15], corr_out_1_n1}) ; + corr_out_12 <= ({ corr_out_1_p2[15], corr_out_1_p2[15], corr_out_1_p2}) + ({corr_out_1_n2[15], corr_out_1_n2[15], corr_out_1_n2}) ; + corr_out_13 <= ({ corr_out_1_p3[15], corr_out_1_p3[15], corr_out_1_p3}) + ({corr_out_1_n3[15], corr_out_1_n3[15], corr_out_1_n3}) ; + corr_out_14 <= ({ corr_out_1_p4[15], corr_out_1_p4[15], corr_out_1_p4}) + ({corr_out_1_n4[15], corr_out_1_n4[15], corr_out_1_n4}) ; + corr_out_15 <= ({ corr_out_1_p5[15], corr_out_1_p5[15], corr_out_1_p5}) + ({corr_out_1_n5[15], corr_out_1_n5[15], corr_out_1_n5}) ; + corr_out_16 <= ({ corr_out_1_p6[15], corr_out_1_p6[15], corr_out_1_p6}) + ({corr_out_1_n6[15], corr_out_1_n6[15], corr_out_1_n6}) ; + corr_out_17 <= ({ corr_out_1_p7[15], corr_out_1_p7[15], corr_out_1_p7}) + ({corr_out_1_n7[15], corr_out_1_n7[15], corr_out_1_n7}) ; + corr_out_18 <= ({ corr_out_1_p8[15], corr_out_1_p8[15], corr_out_1_p8}) + ({corr_out_1_n8[15], corr_out_1_n8[15], corr_out_1_n8}) ; + corr_out_19 <= ({ corr_out_1_p9[15], corr_out_1_p9[15], corr_out_1_p9}) + ({corr_out_1_n9[15], corr_out_1_n9[15], corr_out_1_n9}) ; + corr_out_110 <= ({ corr_out_1_p10[15], corr_out_1_p10[15], corr_out_1_p10}) + ({corr_out_1_n10[15], corr_out_1_n10[15], corr_out_1_n10}) ; + corr_out_111 <= ({ corr_out_1_p11[15], corr_out_1_p11[15], corr_out_1_p11}) + ({corr_out_1_n11[15], corr_out_1_n11[15], corr_out_1_n11}) ; + corr_out_112 <= ({ corr_out_1_p12[15], corr_out_1_p12[15], corr_out_1_p12}) + ({corr_out_1_n12[15], corr_out_1_n12[15], corr_out_1_n12}) ; + corr_out_113 <= ({ corr_out_1_p13[15], corr_out_1_p13[15], corr_out_1_p13}) + ({corr_out_1_n13[15], corr_out_1_n13[15], corr_out_1_n13}) ; + corr_out_114 <= ({ corr_out_1_p14[15], corr_out_1_p14[15], corr_out_1_p14}) + ({corr_out_1_n14[15], corr_out_1_n14[15], corr_out_1_n14}) ; + corr_out_115 <= ({ corr_out_1_p15[15], corr_out_1_p15[15], corr_out_1_p15}) + ({corr_out_1_n15[15], corr_out_1_n15[15], corr_out_1_n15}) ; + corr_out_116 <= ({ corr_out_1_p16[15], corr_out_1_p16[15], corr_out_1_p16}) + ({corr_out_1_n16[15], corr_out_1_n16[15], corr_out_1_n16}) ; + corr_out_117 <= ({ corr_out_1_p17[15], corr_out_1_p17[15], corr_out_1_p17}) + ({corr_out_1_n17[15], corr_out_1_n17[15], corr_out_1_n17}) ; + corr_out_118 <= ({ corr_out_1_p18[15], corr_out_1_p18[15], corr_out_1_p18}) + ({corr_out_1_n18[15], corr_out_1_n18[15], corr_out_1_n18}) ; + corr_out_119 <= ({ corr_out_1_p19[15], corr_out_1_p19[15], corr_out_1_p19}) + ({corr_out_1_n19[15], corr_out_1_n19[15], corr_out_1_n19}) ; + corr_out_120 <= ({ corr_out_1_p20[15], corr_out_1_p20[15], corr_out_1_p20}) + ({corr_out_1_n20[15], corr_out_1_n20[15], corr_out_1_n20}) ; + end + else + begin + corr_out_10 <= corr_out_10; + corr_out_11 <= corr_out_11; + corr_out_12 <= corr_out_12; + corr_out_13 <= corr_out_13; + corr_out_14 <= corr_out_14; + corr_out_15 <= corr_out_15; + corr_out_16 <= corr_out_16; + corr_out_17 <= corr_out_17; + corr_out_18 <= corr_out_18; + corr_out_19 <= corr_out_19; + corr_out_110 <= corr_out_110; + corr_out_111 <= corr_out_111; + corr_out_112 <= corr_out_112; + corr_out_113 <= corr_out_113; + corr_out_114 <= corr_out_114; + corr_out_115 <= corr_out_115; + corr_out_116 <= corr_out_116; + corr_out_117 <= corr_out_117; + corr_out_118 <= corr_out_118; + corr_out_119 <= corr_out_119; + corr_out_120 <= corr_out_120; + end + end + + always @(posedge tm3_clk_v0) + begin + if (vidin_new_data_scld_2_2to3_left == 1'b1) + begin + corr_out_20 <= ({ corr_out_2_p0[15], corr_out_2_p0[15], corr_out_2_p0}) + ({corr_out_2_n0[15], corr_out_2_n0[15], corr_out_2_n0}) ; + corr_out_21 <= ({ corr_out_2_p1[15], corr_out_2_p1[15], corr_out_2_p1}) + ({corr_out_2_n1[15], corr_out_2_n1[15], corr_out_2_n1}) ; + corr_out_22 <= ({ corr_out_2_p2[15], corr_out_2_p2[15], corr_out_2_p2}) + ({corr_out_2_n2[15], corr_out_2_n2[15], corr_out_2_n2}) ; + corr_out_23 <= ({ corr_out_2_p3[15], corr_out_2_p3[15], corr_out_2_p3}) + ({corr_out_2_n3[15], corr_out_2_n3[15], corr_out_2_n3}) ; + corr_out_24 <= ({ corr_out_2_p4[15], corr_out_2_p4[15], corr_out_2_p4}) + ({corr_out_2_n4[15], corr_out_2_n4[15], corr_out_2_n4}) ; + corr_out_25 <= ({ corr_out_2_p5[15], corr_out_2_p5[15], corr_out_2_p5}) + ({corr_out_2_n5[15], corr_out_2_n5[15], corr_out_2_n5}) ; + corr_out_26 <= ({ corr_out_2_p6[15], corr_out_2_p6[15], corr_out_2_p6}) + ({corr_out_2_n6[15], corr_out_2_n6[15], corr_out_2_n6}) ; + corr_out_27 <= ({ corr_out_2_p7[15], corr_out_2_p7[15], corr_out_2_p7}) + ({corr_out_2_n7[15], corr_out_2_n7[15], corr_out_2_n7}) ; + corr_out_28 <= ({ corr_out_2_p8[15], corr_out_2_p8[15], corr_out_2_p8}) + ({corr_out_2_n8[15], corr_out_2_n8[15], corr_out_2_n8}) ; + corr_out_29 <= ({ corr_out_2_p9[15], corr_out_2_p9[15], corr_out_2_p9}) + ({corr_out_2_n9[15], corr_out_2_n9[15], corr_out_2_n9}) ; + corr_out_210 <= ({ corr_out_2_p10[15], corr_out_2_p10[15], corr_out_2_p10}) + ({corr_out_2_n10[15], corr_out_2_n10[15], corr_out_2_n10}) ; + end + else + begin + corr_out_20 <= corr_out_20; + corr_out_21 <= corr_out_21; + corr_out_22 <= corr_out_22; + corr_out_23 <= corr_out_23; + corr_out_24 <= corr_out_24; + corr_out_25 <= corr_out_25; + corr_out_26 <= corr_out_26; + corr_out_27 <= corr_out_27; + corr_out_28 <= corr_out_28; + corr_out_29 <= corr_out_29; + corr_out_210 <= corr_out_210; + end + end + + always @(posedge tm3_clk_v0) + begin + if (vidin_new_data_scld_2_2to3_left == 1'b1) + begin + corr_out_40 <= ({ corr_out_4_p0[15], corr_out_4_p0[15], corr_out_4_p0}) + ({corr_out_4_n0[15], corr_out_4_n0[15], corr_out_4_n0}) ; + corr_out_41 <= ({ corr_out_4_p1[15], corr_out_4_p1[15], corr_out_4_p1}) + ({corr_out_4_n1[15], corr_out_4_n1[15], corr_out_4_n1}) ; + corr_out_42 <= ({ corr_out_4_p2[15], corr_out_4_p2[15], corr_out_4_p2}) + ({corr_out_4_n2[15], corr_out_4_n2[15], corr_out_4_n2}) ; + corr_out_43 <= ({ corr_out_4_p3[15], corr_out_4_p3[15], corr_out_4_p3}) + ({corr_out_4_n3[15], corr_out_4_n3[15], corr_out_4_n3}) ; + corr_out_44 <= ({ corr_out_4_p4[15], corr_out_4_p4[15], corr_out_4_p4}) + ({corr_out_4_n4[15], corr_out_4_n4[15], corr_out_4_n4}) ; + corr_out_45 <= ({ corr_out_4_p5[15], corr_out_4_p5[15], corr_out_4_p5}) + ({corr_out_4_n5[15], corr_out_4_n5[15], corr_out_4_n5}) ; + end + else + begin + corr_out_40 <= corr_out_40; + corr_out_41 <= corr_out_41; + corr_out_42 <= corr_out_42; + corr_out_43 <= corr_out_43; + corr_out_44 <= corr_out_44; + corr_out_45 <= corr_out_45; + end + end + + always @(posedge tm3_clk_v0) + begin + vidin_new_data_scld_1_2to3_left_reg <= vidin_new_data_scld_1_2to3_left ; + vidin_data_reg_scld_1_2to3_left_reg <= vidin_data_reg_scld_1_2to3_left_rp[15:8] ; + vidin_new_data_scld_2_2to3_left_reg <= vidin_new_data_scld_2_2to3_left ; + vidin_data_reg_scld_2_2to3_left_reg <= vidin_data_reg_scld_2_2to3_left_rp[15:8] ; + vidin_new_data_scld_4_2to3_left_reg <= vidin_new_data_scld_4_2to3_left ; + vidin_data_reg_scld_4_2to3_left_reg <= vidin_data_reg_scld_4_2to3_left_rp[15:8] ; + vidin_new_data_scld_1_2to3_right_reg <= vidin_new_data_scld_1_2to3_right ; + vidin_data_reg_scld_1_2to3_right_reg <= vidin_data_reg_scld_1_2to3_right_rp[15:8] ; + vidin_new_data_scld_2_2to3_right_reg <= vidin_new_data_scld_2_2to3_right ; + vidin_data_reg_scld_2_2to3_right_reg <= vidin_data_reg_scld_2_2to3_right_rp[15:8] ; + vidin_new_data_scld_4_2to3_right_reg <= vidin_new_data_scld_4_2to3_right ; + vidin_data_reg_scld_4_2to3_right_reg <= vidin_data_reg_scld_4_2to3_right_rp[15:8] ; + vidin_addr_reg_2to3_reg <= vidin_addr_reg_2to3 ; + end + + always @(posedge tm3_clk_v0) + begin + if (rst) + begin + horiz <= 10'b0000000000; + vert <= 10'b0000000000; + video_state <= 1'b0; + tm3_sram_adsp <= 1'b0; + vidin_data_buf_2_sc_1 <= 0; + vidin_data_buf_2_sc_2 <= 0; + vidin_data_buf_2_sc_4 <= 0; + vidin_addr_buf_sc_1 <= 19'b0; + vidin_addr_buf_sc_2 <= 19'b0; + vidin_addr_buf_sc_4 <= 19'b0; + end + else + begin + video_state <= ~(video_state) ; + if (video_state == 1'b0) + begin + if (horiz == 800) + begin + horiz <= 10'b0000000000 ; + if (vert == 525) + begin + vert <= 10'b0000000000 ; + end + else + begin + vert <= vert + 1 ; + end + end + else + begin + horiz <= horiz + 1 ; + end + tm3_sram_adsp <= 1'b1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_data_xhdl0 <= 64'b0000000000000000000000000000000000000000000000000000000000000000; + tm3_sram_oe <= 2'b11 ; + end + else + begin + tm3_sram_adsp <= 1'b0 ; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_2[18:0]; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_2 ; + end + 3'b100 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_4[18:0]; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_4 ; + end + 3'b111 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_1[18:0]; + tm3_sram_we <= 8'b00000000 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + default : + begin + tm3_sram_addr <= 19'b0000000000000000000 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 64'b0000000000000000000000000000000000000000000000000000000000000000; + end + endcase + end + if (vidin_new_data_scld_1_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[2:0]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + + 4'b0101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_left_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_data_reg_scld_1_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_1 <= {vidin_data_reg_scld_1_2to3_right_reg, vidin_data_buf_2_sc_1[55:0]} ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[16:3]} ; + end + endcase + end + if (vidin_new_data_scld_2_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[3:1]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0100 : + + begin + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0101 : + begin + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_left_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_addr_buf_sc_2 <= {4'b0000, svid_comp_switch_2to3, 1'b0, vidin_addr_reg_2to3_reg[16:10], (6'b101101 + ({1'b0, vidin_addr_reg_2to3_reg[8:4]}))} ; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_2[7:0] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_2[15:8] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_2[23:16] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_2[31:24] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_2[39:32] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_2[47:40] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_2[55:48] <= vidin_data_reg_scld_2_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_2 <= {vidin_data_reg_scld_2_2to3_right_reg, vidin_data_buf_2_sc_2[55:0]} ; + vidin_addr_buf_sc_2 <= {4'b0000, svid_comp_switch_2to3, 1'b0, vidin_addr_reg_2to3_reg[16:10], (6'b101101 + ({1'b0, vidin_addr_reg_2to3_reg[8:4]}))} ; + end + endcase + end + if (vidin_new_data_scld_4_2to3_left_reg == 1'b1) + begin + case ({svid_comp_switch_2to3, vidin_addr_reg_2to3_reg[4:2]}) + 4'b0000 : + begin + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0001 : + begin + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0010 : + begin + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0011 : + begin + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0100 : + begin + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0101 : + begin + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0110 : + begin + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_left_reg ; + end + 4'b0111 : + begin + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_left_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_4 <= { + 4'b0000, svid_comp_switch_2to3, + (8'b10000000 + ({2'b00, vidin_addr_reg_2to3_reg[16:11]})), + (6'b101101 + ({2'b00, vidin_addr_reg_2to3_reg[8:5]})) + }; + end + 4'b1000 : + begin + vidin_data_buf_2_sc_4[7:0] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1001 : + begin + vidin_data_buf_2_sc_4[15:8] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1010 : + begin + vidin_data_buf_2_sc_4[23:16] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1011 : + begin + vidin_data_buf_2_sc_4[31:24] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1100 : + begin + vidin_data_buf_2_sc_4[39:32] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1101 : + begin + vidin_data_buf_2_sc_4[47:40] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1110 : + begin + vidin_data_buf_2_sc_4[55:48] <= vidin_data_reg_scld_4_2to3_right_reg ; + end + 4'b1111 : + begin + vidin_data_buf_sc_4 <= {vidin_data_reg_scld_4_2to3_right_reg, vidin_data_buf_2_sc_4[55:0]} ; + vidin_addr_buf_sc_4 <= {4'b0000, svid_comp_switch_2to3, (8'b10000000 + ({2'b00, vidin_addr_reg_2to3_reg[16:11]})), (6'b101101 + ({2'b00, vidin_addr_reg_2to3_reg[8:5]}))}; + end + endcase + end + end + end +endmodule +module port_bus_2to1_1 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_2to3_left, + vidin_data_reg_scld_1_2to3_left_rp, vidin_data_reg_scld_1_2to3_left_ip, + vidin_data_reg_scld_1_2to3_left_rn, vidin_data_reg_scld_1_2to3_left_in, + vidin_new_data_scld_2_2to3_left, vidin_data_reg_scld_2_2to3_left_rp, + vidin_data_reg_scld_2_2to3_left_ip, vidin_data_reg_scld_2_2to3_left_rn, + vidin_data_reg_scld_2_2to3_left_in, vidin_new_data_scld_4_2to3_left, + vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, + vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, + vidin_new_data_scld_1_2to3_right, vidin_data_reg_scld_1_2to3_right_rp, + vidin_data_reg_scld_1_2to3_right_ip, vidin_data_reg_scld_1_2to3_right_rn, + vidin_data_reg_scld_1_2to3_right_in, vidin_new_data_scld_2_2to3_right, + vidin_data_reg_scld_2_2to3_right_rp, vidin_data_reg_scld_2_2to3_right_ip, + vidin_data_reg_scld_2_2to3_right_rn, vidin_data_reg_scld_2_2to3_right_in, + vidin_new_data_scld_4_2to3_right, vidin_data_reg_scld_4_2to3_right_rp, + vidin_data_reg_scld_4_2to3_right_ip, vidin_data_reg_scld_4_2to3_right_rn, + vidin_data_reg_scld_4_2to3_right_in, bus_word_3, bus_word_4, bus_word_5, + bus_word_6, counter_out, rst); + input clk; + input rst; + output[18:0] vidin_addr_reg; + reg[18:0] vidin_addr_reg; + output svid_comp_switch; + reg svid_comp_switch; + output vidin_new_data_scld_1_2to3_left; + reg vidin_new_data_scld_1_2to3_left; + output[15:0] vidin_data_reg_scld_1_2to3_left_rp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rp; + output[15:0] vidin_data_reg_scld_1_2to3_left_ip; + reg[15:0] vidin_data_reg_scld_1_2to3_left_ip; + output[15:0] vidin_data_reg_scld_1_2to3_left_rn; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rn; + output[15:0] vidin_data_reg_scld_1_2to3_left_in; + reg[15:0] vidin_data_reg_scld_1_2to3_left_in; + output vidin_new_data_scld_2_2to3_left; + reg vidin_new_data_scld_2_2to3_left; + output[15:0] vidin_data_reg_scld_2_2to3_left_rp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rp; + output[15:0] vidin_data_reg_scld_2_2to3_left_ip; + reg[15:0] vidin_data_reg_scld_2_2to3_left_ip; + output[15:0] vidin_data_reg_scld_2_2to3_left_rn; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rn; + output[15:0] vidin_data_reg_scld_2_2to3_left_in; + reg[15:0] vidin_data_reg_scld_2_2to3_left_in; + output vidin_new_data_scld_4_2to3_left; + reg vidin_new_data_scld_4_2to3_left; + output[15:0] vidin_data_reg_scld_4_2to3_left_rp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rp; + output[15:0] vidin_data_reg_scld_4_2to3_left_ip; + reg[15:0] vidin_data_reg_scld_4_2to3_left_ip; + output[15:0] vidin_data_reg_scld_4_2to3_left_rn; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rn; + output[15:0] vidin_data_reg_scld_4_2to3_left_in; + reg[15:0] vidin_data_reg_scld_4_2to3_left_in; + output vidin_new_data_scld_1_2to3_right; + reg vidin_new_data_scld_1_2to3_right; + output[15:0] vidin_data_reg_scld_1_2to3_right_rp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rp; + output[15:0] vidin_data_reg_scld_1_2to3_right_ip; + reg[15:0] vidin_data_reg_scld_1_2to3_right_ip; + output[15:0] vidin_data_reg_scld_1_2to3_right_rn; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rn; + output[15:0] vidin_data_reg_scld_1_2to3_right_in; + reg[15:0] vidin_data_reg_scld_1_2to3_right_in; + output vidin_new_data_scld_2_2to3_right; + reg vidin_new_data_scld_2_2to3_right; + output[15:0] vidin_data_reg_scld_2_2to3_right_rp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rp; + output[15:0] vidin_data_reg_scld_2_2to3_right_ip; + reg[15:0] vidin_data_reg_scld_2_2to3_right_ip; + output[15:0] vidin_data_reg_scld_2_2to3_right_rn; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rn; + output[15:0] vidin_data_reg_scld_2_2to3_right_in; + + reg[15:0] vidin_data_reg_scld_2_2to3_right_in; + output vidin_new_data_scld_4_2to3_right; + reg vidin_new_data_scld_4_2to3_right; + output[15:0] vidin_data_reg_scld_4_2to3_right_rp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rp; + output[15:0] vidin_data_reg_scld_4_2to3_right_ip; + reg[15:0] vidin_data_reg_scld_4_2to3_right_ip; + output[15:0] vidin_data_reg_scld_4_2to3_right_rn; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rn; + output[15:0] vidin_data_reg_scld_4_2to3_right_in; + reg[15:0] vidin_data_reg_scld_4_2to3_right_in; + input[15:0] bus_word_3; + input[15:0] bus_word_4; + input[15:0] bus_word_5; + input[15:0] bus_word_6; + input[2:0] counter_out; + + reg[15:0] bus_word_3_tmp; + reg[15:0] bus_word_4_tmp; + reg[15:0] bus_word_5_tmp; + reg[15:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; +/* + reg vidin_new_data_scld_1_2to3_left_tmp; + reg vidin_new_data_scld_2_2to3_left_tmp; + reg vidin_new_data_scld_4_2to3_left_tmp; + reg vidin_new_data_scld_1_2to3_right_tmp; + reg vidin_new_data_scld_2_2to3_right_tmp; + reg vidin_new_data_scld_4_2to3_right_tmp; +*/ + reg[2:0] counter_out_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_in_tmp; + + always @(posedge clk) + begin + case (counter_out_tmp[2:0]) +// took out noop case 3'b000 + 3'b001 : + begin + vidin_addr_reg_tmp[15:0] <= bus_word_3_tmp ; + vidin_addr_reg_tmp[18:16] <= bus_word_4_tmp[15:13] ; + + svid_comp_switch_tmp <= bus_word_4_tmp[12] ; +/* + vidin_new_data_scld_1_2to3_left_tmp <= bus_word_4_tmp[11] ; + vidin_new_data_scld_2_2to3_left_tmp <= bus_word_4_tmp[10] ; + vidin_new_data_scld_4_2to3_left_tmp <= bus_word_4_tmp[9] ; + vidin_new_data_scld_1_2to3_right_tmp <= bus_word_4_tmp[8] ; + vidin_new_data_scld_2_2to3_right_tmp <= bus_word_4_tmp[7] ; + vidin_new_data_scld_4_2to3_right_tmp <= bus_word_4_tmp[6] ; +*/ + end + 3'b010 : + begin + vidin_data_reg_scld_1_2to3_left_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_1_2to3_left_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_1_2to3_left_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_1_2to3_left_in_tmp <= bus_word_6_tmp ; + end + 3'b011 : + begin + vidin_data_reg_scld_1_2to3_right_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_1_2to3_right_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_1_2to3_right_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_1_2to3_right_in_tmp <= bus_word_6_tmp ; + end + 3'b100 : + begin + vidin_data_reg_scld_2_2to3_left_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_2_2to3_left_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_2_2to3_left_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_2_2to3_left_in_tmp <= bus_word_6_tmp ; + end + 3'b101 : + begin + vidin_data_reg_scld_2_2to3_right_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_2_2to3_right_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_2_2to3_right_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_2_2to3_right_in_tmp <= bus_word_6_tmp ; + end + 3'b110 : + begin + vidin_data_reg_scld_4_2to3_left_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_4_2to3_left_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_4_2to3_left_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_4_2to3_left_in_tmp <= bus_word_6_tmp ; + end + 3'b111 : + begin + vidin_data_reg_scld_4_2to3_right_rp_tmp <= bus_word_3_tmp ; + vidin_data_reg_scld_4_2to3_right_ip_tmp <= bus_word_4_tmp ; + vidin_data_reg_scld_4_2to3_right_rn_tmp <= bus_word_5_tmp ; + vidin_data_reg_scld_4_2to3_right_in_tmp <= bus_word_6_tmp ; + end + default: + begin + vidin_data_reg_scld_4_2to3_right_rp_tmp <= 0; + vidin_data_reg_scld_4_2to3_right_ip_tmp <= 0; + vidin_data_reg_scld_4_2to3_right_rn_tmp <= 0; + vidin_data_reg_scld_4_2to3_right_in_tmp <= 0; + vidin_addr_reg_tmp <= 0; + svid_comp_switch_tmp <=0; + end + endcase + end + + always @(posedge clk) + begin + if (rst) + begin + counter_out_tmp <= 0; + bus_word_3_tmp <= 0; + bus_word_4_tmp <= 0; + bus_word_5_tmp <= 0; + bus_word_6_tmp <= 0; + end + else + begin + counter_out_tmp <= counter_out ; + bus_word_3_tmp <= bus_word_3 ; + bus_word_4_tmp <= bus_word_4 ; + bus_word_5_tmp <= bus_word_5 ; + bus_word_6_tmp <= bus_word_6 ; + end + end + + always @(posedge clk) + begin + if (counter_out_tmp == 3'b001) + begin + vidin_addr_reg <= vidin_addr_reg_tmp ; + svid_comp_switch <= svid_comp_switch_tmp ; + vidin_new_data_scld_1_2to3_left <= 1'b1 ; + if (((vidin_addr_reg_tmp[0]) == 1'b0) && ((vidin_addr_reg_tmp[9]) == 1'b0)) + begin + vidin_new_data_scld_2_2to3_left <= 1'b1 ; + if (((vidin_addr_reg_tmp[1]) == 1'b0) && ((vidin_addr_reg_tmp[10]) == 1'b0)) + begin + vidin_new_data_scld_4_2to3_left <= 1'b1 ; + end + else + begin + vidin_new_data_scld_4_2to3_left <= vidin_new_data_scld_4_2to3_left; + end + end + else + begin + vidin_new_data_scld_2_2to3_left <= vidin_new_data_scld_4_2to3_left ; + vidin_new_data_scld_4_2to3_left <= vidin_new_data_scld_4_2to3_left; + end + vidin_new_data_scld_1_2to3_right <= 1'b1 ; + vidin_new_data_scld_2_2to3_right <= 1'b1 ; + vidin_new_data_scld_4_2to3_right <= 1'b1 ; + vidin_data_reg_scld_1_2to3_left_rp <= vidin_data_reg_scld_1_2to3_left_rp_tmp ; + vidin_data_reg_scld_1_2to3_left_ip <= vidin_data_reg_scld_1_2to3_left_ip_tmp ; + vidin_data_reg_scld_1_2to3_left_rn <= vidin_data_reg_scld_1_2to3_left_rn_tmp ; + vidin_data_reg_scld_1_2to3_left_in <= vidin_data_reg_scld_1_2to3_left_in_tmp ; + vidin_data_reg_scld_2_2to3_left_rp <= vidin_data_reg_scld_2_2to3_left_rp_tmp ; + vidin_data_reg_scld_2_2to3_left_ip <= vidin_data_reg_scld_2_2to3_left_ip_tmp ; + vidin_data_reg_scld_2_2to3_left_rn <= vidin_data_reg_scld_2_2to3_left_rn_tmp ; + vidin_data_reg_scld_2_2to3_left_in <= vidin_data_reg_scld_2_2to3_left_in_tmp ; + vidin_data_reg_scld_4_2to3_left_rp <= vidin_data_reg_scld_4_2to3_left_rp_tmp ; + vidin_data_reg_scld_4_2to3_left_ip <= vidin_data_reg_scld_4_2to3_left_ip_tmp ; + vidin_data_reg_scld_4_2to3_left_rn <= vidin_data_reg_scld_4_2to3_left_rn_tmp ; + vidin_data_reg_scld_4_2to3_left_in <= vidin_data_reg_scld_4_2to3_left_in_tmp ; + vidin_data_reg_scld_1_2to3_right_rp <= vidin_data_reg_scld_1_2to3_right_rp_tmp ; + vidin_data_reg_scld_1_2to3_right_ip <= vidin_data_reg_scld_1_2to3_right_ip_tmp ; + vidin_data_reg_scld_1_2to3_right_rn <= vidin_data_reg_scld_1_2to3_right_rn_tmp ; + vidin_data_reg_scld_1_2to3_right_in <= vidin_data_reg_scld_1_2to3_right_in_tmp ; + vidin_data_reg_scld_2_2to3_right_rp <= vidin_data_reg_scld_2_2to3_right_rp_tmp ; + vidin_data_reg_scld_2_2to3_right_ip <= vidin_data_reg_scld_2_2to3_right_ip_tmp ; + vidin_data_reg_scld_2_2to3_right_rn <= vidin_data_reg_scld_2_2to3_right_rn_tmp ; + vidin_data_reg_scld_2_2to3_right_in <= vidin_data_reg_scld_2_2to3_right_in_tmp ; + vidin_data_reg_scld_4_2to3_right_rp <= vidin_data_reg_scld_4_2to3_right_rp_tmp ; + vidin_data_reg_scld_4_2to3_right_ip <= vidin_data_reg_scld_4_2to3_right_ip_tmp ; + vidin_data_reg_scld_4_2to3_right_rn <= vidin_data_reg_scld_4_2to3_right_rn_tmp ; + vidin_data_reg_scld_4_2to3_right_in <= vidin_data_reg_scld_4_2to3_right_in_tmp ; + end + else + begin + vidin_new_data_scld_1_2to3_left <= 1'b0 ; + vidin_new_data_scld_2_2to3_left <= 1'b0 ; + vidin_new_data_scld_4_2to3_left <= 1'b0 ; + vidin_new_data_scld_1_2to3_right <= 1'b0 ; + vidin_new_data_scld_2_2to3_right <= 1'b0 ; + vidin_new_data_scld_4_2to3_right <= 1'b0 ; + vidin_addr_reg <= vidin_addr_reg; + svid_comp_switch <= svid_comp_switch; + vidin_data_reg_scld_1_2to3_left_rp <= vidin_data_reg_scld_1_2to3_left_rp; + vidin_data_reg_scld_1_2to3_left_ip <= vidin_data_reg_scld_1_2to3_left_ip; + vidin_data_reg_scld_1_2to3_left_rn <= vidin_data_reg_scld_1_2to3_left_rn; + vidin_data_reg_scld_1_2to3_left_in <= vidin_data_reg_scld_1_2to3_left_in; + vidin_data_reg_scld_2_2to3_left_rp <= vidin_data_reg_scld_2_2to3_left_rp; + vidin_data_reg_scld_2_2to3_left_ip <= vidin_data_reg_scld_2_2to3_left_ip; + vidin_data_reg_scld_2_2to3_left_rn <= vidin_data_reg_scld_2_2to3_left_rn; + vidin_data_reg_scld_2_2to3_left_in <= vidin_data_reg_scld_2_2to3_left_in; + vidin_data_reg_scld_4_2to3_left_rp <= vidin_data_reg_scld_4_2to3_left_rp; + vidin_data_reg_scld_4_2to3_left_ip <= vidin_data_reg_scld_4_2to3_left_ip; + vidin_data_reg_scld_4_2to3_left_rn <= vidin_data_reg_scld_4_2to3_left_rn; + vidin_data_reg_scld_4_2to3_left_in <= vidin_data_reg_scld_4_2to3_left_in; + vidin_data_reg_scld_1_2to3_right_rp <= vidin_data_reg_scld_1_2to3_right_rp; + vidin_data_reg_scld_1_2to3_right_ip <= vidin_data_reg_scld_1_2to3_right_ip; + vidin_data_reg_scld_1_2to3_right_rn <= vidin_data_reg_scld_1_2to3_right_rn; + vidin_data_reg_scld_1_2to3_right_in <= vidin_data_reg_scld_1_2to3_right_in; + vidin_data_reg_scld_2_2to3_right_rp <= vidin_data_reg_scld_2_2to3_right_rp; + vidin_data_reg_scld_2_2to3_right_ip <= vidin_data_reg_scld_2_2to3_right_ip; + vidin_data_reg_scld_2_2to3_right_rn <= vidin_data_reg_scld_2_2to3_right_rn; + vidin_data_reg_scld_2_2to3_right_in <= vidin_data_reg_scld_2_2to3_right_in; + vidin_data_reg_scld_4_2to3_right_rp <= vidin_data_reg_scld_4_2to3_right_rp; + vidin_data_reg_scld_4_2to3_right_ip <= vidin_data_reg_scld_4_2to3_right_ip; + vidin_data_reg_scld_4_2to3_right_rn <= vidin_data_reg_scld_4_2to3_right_rn; + vidin_data_reg_scld_4_2to3_right_in <= vidin_data_reg_scld_4_2to3_right_in; + end + end +endmodule + +module wrapper_norm_corr_20 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10, corr_out_11, corr_out_12, corr_out_13, corr_out_14, corr_out_15, corr_out_16, corr_out_17, corr_out_18, corr_out_19, corr_out_20); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[15:0] d_l_1; + input[15:0] d_l_2; + input[15:0] d_r_1; + input[15:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + wire[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + wire[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + wire[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + wire[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + wire[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + wire[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + wire[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + wire[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + wire[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + wire[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + wire[2 * sh_reg_w - 1:0] corr_out_10; + output[2 * sh_reg_w - 1:0] corr_out_11; + wire[2 * sh_reg_w - 1:0] corr_out_11; + output[2 * sh_reg_w - 1:0] corr_out_12; + wire[2 * sh_reg_w - 1:0] corr_out_12; + output[2 * sh_reg_w - 1:0] corr_out_13; + wire[2 * sh_reg_w - 1:0] corr_out_13; + output[2 * sh_reg_w - 1:0] corr_out_14; + wire[2 * sh_reg_w - 1:0] corr_out_14; + output[2 * sh_reg_w - 1:0] corr_out_15; + wire[2 * sh_reg_w - 1:0] corr_out_15; + output[2 * sh_reg_w - 1:0] corr_out_16; + wire[2 * sh_reg_w - 1:0] corr_out_16; + output[2 * sh_reg_w - 1:0] corr_out_17; + wire[2 * sh_reg_w - 1:0] corr_out_17; + output[2 * sh_reg_w - 1:0] corr_out_18; + wire[2 * sh_reg_w - 1:0] corr_out_18; + output[2 * sh_reg_w - 1:0] corr_out_19; + wire[2 * sh_reg_w - 1:0] corr_out_19; + output[2 * sh_reg_w - 1:0] corr_out_20; + wire[2 * sh_reg_w - 1:0] corr_out_20; + + wire[sh_reg_w - 1:0] d_l_1_nrm; + wire[sh_reg_w - 1:0] d_l_2_nrm; + wire[sh_reg_w - 1:0] d_r_1_nrm; + wire[sh_reg_w - 1:0] d_r_2_nrm; + + wrapper_norm norm_inst_left(.clk(clk), .nd(wen), .din_1(d_l_1), .din_2(d_l_2), .dout_1(d_l_1_nrm), .dout_2(d_l_2_nrm)); + wrapper_norm norm_inst_right(.clk(clk), .nd(wen), .din_1(d_r_1), .din_2(d_r_2), .dout_1(d_r_1_nrm), .dout_2(d_r_2_nrm)); + wrapper_corr_20 corr_20_inst(.clk(clk), .wen(wen), .d_l_1(d_l_1_nrm), .d_l_2(d_l_2_nrm), .d_r_1(d_r_1_nrm), .d_r_2(d_r_2_nrm), .corr_out_0(corr_out_0), .corr_out_1(corr_out_1), .corr_out_2(corr_out_2), .corr_out_3(corr_out_3), .corr_out_4(corr_out_4), .corr_out_5(corr_out_5), .corr_out_6(corr_out_6), .corr_out_7(corr_out_7), .corr_out_8(corr_out_8), .corr_out_9(corr_out_9), .corr_out_10(corr_out_10), .corr_out_11(corr_out_11), .corr_out_12(corr_out_12), .corr_out_13(corr_out_13), .corr_out_14(corr_out_14), .corr_out_15(corr_out_15), .corr_out_16(corr_out_16), .corr_out_17(corr_out_17), .corr_out_18(corr_out_18), .corr_out_19(corr_out_19), .corr_out_20(corr_out_20)); +endmodule +module wrapper_corr_20 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10, corr_out_11, corr_out_12, corr_out_13, corr_out_14, corr_out_15, corr_out_16, corr_out_17, corr_out_18, corr_out_19, corr_out_20); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[7:0] d_l_1; + input[7:0] d_l_2; + input[7:0] d_r_1; + input[7:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + reg[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + reg[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + reg[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + reg[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + reg[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + reg[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + reg[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + reg[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + reg[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + reg[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + reg[2 * sh_reg_w - 1:0] corr_out_10; + output[2 * sh_reg_w - 1:0] corr_out_11; + reg[2 * sh_reg_w - 1:0] corr_out_11; + output[2 * sh_reg_w - 1:0] corr_out_12; + reg[2 * sh_reg_w - 1:0] corr_out_12; + output[2 * sh_reg_w - 1:0] corr_out_13; + reg[2 * sh_reg_w - 1:0] corr_out_13; + output[2 * sh_reg_w - 1:0] corr_out_14; + reg[2 * sh_reg_w - 1:0] corr_out_14; + output[2 * sh_reg_w - 1:0] corr_out_15; + reg[2 * sh_reg_w - 1:0] corr_out_15; + output[2 * sh_reg_w - 1:0] corr_out_16; + reg[2 * sh_reg_w - 1:0] corr_out_16; + output[2 * sh_reg_w - 1:0] corr_out_17; + reg[2 * sh_reg_w - 1:0] corr_out_17; + output[2 * sh_reg_w - 1:0] corr_out_18; + reg[2 * sh_reg_w - 1:0] corr_out_18; + output[2 * sh_reg_w - 1:0] corr_out_19; + reg[2 * sh_reg_w - 1:0] corr_out_19; + output[2 * sh_reg_w - 1:0] corr_out_20; + reg[2 * sh_reg_w - 1:0] corr_out_20; + + wire[sh_reg_w - 1:0] out_r1; + wire[sh_reg_w - 1:0] out_01; + + wire[sh_reg_w - 1:0] out_11; + wire[sh_reg_w - 1:0] out_21; + wire[sh_reg_w - 1:0] out_31; + wire[sh_reg_w - 1:0] out_41; + wire[sh_reg_w - 1:0] out_51; + wire[sh_reg_w - 1:0] out_61; + wire[sh_reg_w - 1:0] out_71; + wire[sh_reg_w - 1:0] out_81; + wire[sh_reg_w - 1:0] out_91; + wire[sh_reg_w - 1:0] out_101; + wire[sh_reg_w - 1:0] out_111; + wire[sh_reg_w - 1:0] out_121; + wire[sh_reg_w - 1:0] out_131; + wire[sh_reg_w - 1:0] out_141; + wire[sh_reg_w - 1:0] out_151; + wire[sh_reg_w - 1:0] out_161; + wire[sh_reg_w - 1:0] out_171; + wire[sh_reg_w - 1:0] out_181; + wire[sh_reg_w - 1:0] out_191; + wire[sh_reg_w - 1:0] out_201; + wire[sh_reg_w - 1:0] out_r2; + wire[sh_reg_w - 1:0] out_02; + wire[sh_reg_w - 1:0] out_12; + wire[sh_reg_w - 1:0] out_22; + wire[sh_reg_w - 1:0] out_32; + wire[sh_reg_w - 1:0] out_42; + wire[sh_reg_w - 1:0] out_52; + wire[sh_reg_w - 1:0] out_62; + wire[sh_reg_w - 1:0] out_72; + wire[sh_reg_w - 1:0] out_82; + wire[sh_reg_w - 1:0] out_92; + wire[sh_reg_w - 1:0] out_102; + wire[sh_reg_w - 1:0] out_112; + wire[sh_reg_w - 1:0] out_122; + wire[sh_reg_w - 1:0] out_132; + wire[sh_reg_w - 1:0] out_142; + wire[sh_reg_w - 1:0] out_152; + wire[sh_reg_w - 1:0] out_162; + wire[sh_reg_w - 1:0] out_172; + wire[sh_reg_w - 1:0] out_182; + wire[sh_reg_w - 1:0] out_192; + wire[sh_reg_w - 1:0] out_202; + wire[2 * sh_reg_w - 1:0] corr_out_0_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_1_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_2_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_3_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_4_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_5_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_6_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_7_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_8_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_9_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_10_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_11_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_12_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_13_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_14_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_15_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_16_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_17_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_18_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_19_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_20_tmp; + + sh_reg inst_sh_reg_r_1(clk, wen, d_r_1, d_r_2, out_r1, out_r2); + sh_reg inst_sh_reg_0(clk, wen, d_l_1, d_l_2, out_01, out_02); + sh_reg inst_sh_reg_1(clk, wen, out_01, out_02, out_11, out_12); + sh_reg inst_sh_reg_2(clk, wen, out_11, out_12, out_21, out_22); + sh_reg inst_sh_reg_3(clk, wen, out_21, out_22, out_31, out_32); + sh_reg inst_sh_reg_4(clk, wen, out_31, out_32, out_41, out_42); + sh_reg inst_sh_reg_5(clk, wen, out_41, out_42, out_51, out_52); + sh_reg inst_sh_reg_6(clk, wen, out_51, out_52, out_61, out_62); + sh_reg inst_sh_reg_7(clk, wen, out_61, out_62, out_71, out_72); + sh_reg inst_sh_reg_8(clk, wen, out_71, out_72, out_81, out_82); + sh_reg inst_sh_reg_9(clk, wen, out_81, out_82, out_91, out_92); + sh_reg inst_sh_reg_10(clk, wen, out_91, out_92, out_101, out_102); + sh_reg inst_sh_reg_11(clk, wen, out_101, out_102, out_111, out_112); + sh_reg inst_sh_reg_12(clk, wen, out_111, out_112, out_121, out_122); + sh_reg inst_sh_reg_13(clk, wen, out_121, out_122, out_131, out_132); + sh_reg inst_sh_reg_14(clk, wen, out_131, out_132, out_141, out_142); + sh_reg inst_sh_reg_15(clk, wen, out_141, out_142, out_151, out_152); + sh_reg inst_sh_reg_16(clk, wen, out_151, out_152, out_161, out_162); + sh_reg inst_sh_reg_17(clk, wen, out_161, out_162, out_171, out_172); + sh_reg inst_sh_reg_18(clk, wen, out_171, out_172, out_181, out_182); + sh_reg inst_sh_reg_19(clk, wen, out_181, out_182, out_191, out_192); + sh_reg inst_sh_reg_20(clk, wen, out_191, out_192, out_201, out_202); + corr inst_corr_0(clk, wen, out_01, out_02, out_r1, out_r2, corr_out_0_tmp); + corr inst_corr_1(clk, wen, out_11, out_12, out_r1, out_r2, corr_out_1_tmp); + corr inst_corr_2(clk, wen, out_21, out_22, out_r1, out_r2, corr_out_2_tmp); + corr inst_corr_3(clk, wen, out_31, out_32, out_r1, out_r2, corr_out_3_tmp); + corr inst_corr_4(clk, wen, out_41, out_42, out_r1, out_r2, corr_out_4_tmp); + corr inst_corr_5(clk, wen, out_51, out_52, out_r1, out_r2, corr_out_5_tmp); + corr inst_corr_6(clk, wen, out_61, out_62, out_r1, out_r2, corr_out_6_tmp); + corr inst_corr_7(clk, wen, out_71, out_72, out_r1, out_r2, corr_out_7_tmp); + corr inst_corr_8(clk, wen, out_81, out_82, out_r1, out_r2, corr_out_8_tmp); + corr inst_corr_9(clk, wen, out_91, out_92, out_r1, out_r2, corr_out_9_tmp); + corr inst_corr_10(clk, wen, out_101, out_102, out_r1, out_r2, corr_out_10_tmp); + corr inst_corr_11(clk, wen, out_111, out_112, out_r1, out_r2, corr_out_11_tmp); + corr inst_corr_12(clk, wen, out_121, out_122, out_r1, out_r2, corr_out_12_tmp); + corr inst_corr_13(clk, wen, out_131, out_132, out_r1, out_r2, corr_out_13_tmp); + corr inst_corr_14(clk, wen, out_141, out_142, out_r1, out_r2, corr_out_14_tmp); + corr inst_corr_15(clk, wen, out_151, out_152, out_r1, out_r2, corr_out_15_tmp); + corr inst_corr_16(clk, wen, out_161, out_162, out_r1, out_r2, corr_out_16_tmp); + corr inst_corr_17(clk, wen, out_171, out_172, out_r1, out_r2, corr_out_17_tmp); + corr inst_corr_18(clk, wen, out_181, out_182, out_r1, out_r2, corr_out_18_tmp); + corr inst_corr_19(clk, wen, out_191, out_192, out_r1, out_r2, corr_out_19_tmp); + corr inst_corr_20(clk, wen, out_201, out_202, out_r1, out_r2, corr_out_20_tmp); + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + corr_out_0 <= corr_out_0_tmp ; + corr_out_1 <= corr_out_1_tmp ; + corr_out_2 <= corr_out_2_tmp ; + corr_out_3 <= corr_out_3_tmp ; + corr_out_4 <= corr_out_4_tmp ; + corr_out_5 <= corr_out_5_tmp ; + corr_out_6 <= corr_out_6_tmp ; + corr_out_7 <= corr_out_7_tmp ; + corr_out_8 <= corr_out_8_tmp ; + corr_out_9 <= corr_out_9_tmp ; + corr_out_10 <= corr_out_10_tmp ; + corr_out_11 <= corr_out_11_tmp ; + corr_out_12 <= corr_out_12_tmp ; + corr_out_13 <= corr_out_13_tmp ; + corr_out_14 <= corr_out_14_tmp ; + corr_out_15 <= corr_out_15_tmp ; + corr_out_16 <= corr_out_16_tmp ; + corr_out_17 <= corr_out_17_tmp ; + corr_out_18 <= corr_out_18_tmp ; + corr_out_19 <= corr_out_19_tmp ; + corr_out_20 <= corr_out_20_tmp ; + end + else + begin + corr_out_0 <= corr_out_0; + corr_out_1 <= corr_out_1; + corr_out_2 <= corr_out_2; + corr_out_3 <= corr_out_3; + corr_out_4 <= corr_out_4; + corr_out_5 <= corr_out_5; + corr_out_6 <= corr_out_6; + corr_out_7 <= corr_out_7; + corr_out_8 <= corr_out_8; + corr_out_9 <= corr_out_9; + corr_out_10 <= corr_out_10; + corr_out_11 <= corr_out_11; + corr_out_12 <= corr_out_12; + corr_out_13 <= corr_out_13; + corr_out_14 <= corr_out_14; + corr_out_15 <= corr_out_15; + corr_out_16 <= corr_out_16; + corr_out_17 <= corr_out_17; + corr_out_18 <= corr_out_18; + corr_out_19 <= corr_out_19; + corr_out_20 <= corr_out_20; + end + end +endmodule +// Discription: this block creates a simple +// shift register +// date: Oct.7 ,2001 +// revised : April 8, 2002 +// By: Ahmad darabiha +module sh_reg (clk, wen, din_1, din_2, dout_1, dout_2); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[sh_reg_w - 1:0] din_1; + input[sh_reg_w - 1:0] din_2; + output[sh_reg_w - 1:0] dout_1; + reg[sh_reg_w - 1:0] dout_1; + output[sh_reg_w - 1:0] dout_2; + reg[sh_reg_w - 1:0] dout_2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + dout_1 <= din_1 ; + dout_2 <= din_2 ; + end + else + begin + dout_1 <= dout_1 ; + dout_2 <= dout_2 ; + end + end +endmodule +module corr (clk, new_data, in_l_re, in_l_im, in_r_re, in_r_im, corr_out); + + parameter sh_reg_w = 4'b1000; + input clk; + input new_data; + input[sh_reg_w - 1:0] in_l_re; + input[sh_reg_w - 1:0] in_l_im; + input[sh_reg_w - 1:0] in_r_re; + input[sh_reg_w - 1:0] in_r_im; + output[2 * sh_reg_w - 1:0] corr_out; + reg[2 * sh_reg_w - 1:0] corr_out; + wire[sh_reg_w - 1:0] in_l_re_reg; + wire[sh_reg_w - 1:0] in_l_im_reg; + wire[sh_reg_w - 1:0] in_r_re_reg; + wire[sh_reg_w - 1:0] in_r_im_reg; + reg[2 * sh_reg_w - 1:0] lrexrre_reg; + reg[2 * sh_reg_w - 1:0] limxrim_reg; + reg[2 * sh_reg_w - 1:0] corr_out_tmp; + + always @(posedge clk) + begin + // PAJ - edf xilinx files converted to multiply + lrexrre_reg <= in_l_re * in_r_re; + limxrim_reg <= in_l_im * in_r_im; + + if (new_data == 1'b1) + begin + corr_out <= corr_out_tmp ; + end + else + begin + corr_out <= corr_out; + end + corr_out_tmp <= lrexrre_reg + limxrim_reg ; + end + endmodule +module wrapper_norm (clk, nd, din_1, din_2, dout_1, dout_2); + + parameter sh_reg_w = 4'b1000; + input clk; + input nd; + input[15:0] din_1; + input[15:0] din_2; + output[sh_reg_w - 1:0] dout_1; + wire[sh_reg_w - 1:0] dout_1; + output[sh_reg_w - 1:0] dout_2; + wire[sh_reg_w - 1:0] dout_2; + + reg[15:0] din_1_reg; + reg[15:0] din_2_reg; + reg[15:0] din_1_tmp1; + reg[15:0] din_2_tmp1; + reg[15:0] din_1_tmp2; + reg[15:0] din_2_tmp2; + reg[15:0] addin_1; + reg[15:0] addin_2; + reg[16:0] add_out; + + my_wrapper_divider my_div_inst_1 (nd, clk, din_1_tmp2, add_out, dout_1); + my_wrapper_divider my_div_inst_2 (nd, clk, din_2_tmp2, add_out, dout_2); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din_1 ; + din_2_reg <= din_2 ; + end + else + begin + din_1_reg <= din_1_reg ; + din_2_reg <= din_2_reg; + end + din_1_tmp1 <= din_1_reg ; + din_1_tmp2 <= din_1_tmp1 ; + din_2_tmp1 <= din_2_reg ; + din_2_tmp2 <= din_2_tmp1 ; + if ((din_1_reg[15]) == 1'b0) + begin + addin_1 <= din_1_reg ; + end + else + begin + addin_1 <= 16'b0000000000000000 - din_1_reg ; + end + if ((din_2_reg[15]) == 1'b0) + begin + addin_2 <= din_2_reg + 16'b0000000000000001 ; + end + else + begin + addin_2 <= 16'b0000000000000001 - din_2_reg ; + end + add_out <= ({addin_1[15], addin_1}) + ({addin_2[15], addin_2}) ; + end +endmodule + + + + +module wrapper_norm_corr_10 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[15:0] d_l_1; + input[15:0] d_l_2; + input[15:0] d_r_1; + input[15:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + wire[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + wire[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + wire[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + wire[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + wire[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + wire[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + wire[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + wire[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + wire[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + wire[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + wire[2 * sh_reg_w - 1:0] corr_out_10; + + wire[sh_reg_w - 1:0] d_l_1_nrm; + wire[sh_reg_w - 1:0] d_l_2_nrm; + wire[sh_reg_w - 1:0] d_r_1_nrm; + wire[sh_reg_w - 1:0] d_r_2_nrm; + + wrapper_norm norm_inst_left(.clk(clk), .nd(wen), .din_1(d_l_1), .din_2(d_l_2), .dout_1(d_l_1_nrm), .dout_2(d_l_2_nrm)); + wrapper_norm norm_inst_right(.clk(clk), .nd(wen), .din_1(d_r_1), .din_2(d_r_2), .dout_1(d_r_1_nrm), .dout_2(d_r_2_nrm)); + wrapper_corr_10 corr_5_inst(.clk(clk), .wen(wen), .d_l_1(d_l_1_nrm), .d_l_2(d_l_2_nrm), .d_r_1(d_r_1_nrm), .d_r_2(d_r_2_nrm), .corr_out_0(corr_out_0), .corr_out_1(corr_out_1), .corr_out_2(corr_out_2), .corr_out_3(corr_out_3), .corr_out_4(corr_out_4), .corr_out_5(corr_out_5), .corr_out_6(corr_out_6), .corr_out_7(corr_out_7), .corr_out_8(corr_out_8), .corr_out_9(corr_out_9), .corr_out_10(corr_out_10)); +endmodule + + + + +module wrapper_corr_10 (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5, corr_out_6, corr_out_7, corr_out_8, corr_out_9, corr_out_10); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[7:0] d_l_1; + input[7:0] d_l_2; + input[7:0] d_r_1; + input[7:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + reg[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + reg[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + reg[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + reg[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + reg[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + reg[2 * sh_reg_w - 1:0] corr_out_5; + output[2 * sh_reg_w - 1:0] corr_out_6; + reg[2 * sh_reg_w - 1:0] corr_out_6; + output[2 * sh_reg_w - 1:0] corr_out_7; + reg[2 * sh_reg_w - 1:0] corr_out_7; + output[2 * sh_reg_w - 1:0] corr_out_8; + reg[2 * sh_reg_w - 1:0] corr_out_8; + output[2 * sh_reg_w - 1:0] corr_out_9; + reg[2 * sh_reg_w - 1:0] corr_out_9; + output[2 * sh_reg_w - 1:0] corr_out_10; + reg[2 * sh_reg_w - 1:0] corr_out_10; + + wire[sh_reg_w - 1:0] out_r1; + wire[sh_reg_w - 1:0] out_01; + wire[sh_reg_w - 1:0] out_11; + wire[sh_reg_w - 1:0] out_21; + wire[sh_reg_w - 1:0] out_31; + wire[sh_reg_w - 1:0] out_41; + wire[sh_reg_w - 1:0] out_51; + wire[sh_reg_w - 1:0] out_61; + wire[sh_reg_w - 1:0] out_71; + wire[sh_reg_w - 1:0] out_81; + wire[sh_reg_w - 1:0] out_91; + wire[sh_reg_w - 1:0] out_101; + wire[sh_reg_w - 1:0] out_r2; + wire[sh_reg_w - 1:0] out_02; + wire[sh_reg_w - 1:0] out_12; + wire[sh_reg_w - 1:0] out_22; + wire[sh_reg_w - 1:0] out_32; + wire[sh_reg_w - 1:0] out_42; + wire[sh_reg_w - 1:0] out_52; + wire[sh_reg_w - 1:0] out_62; + wire[sh_reg_w - 1:0] out_72; + wire[sh_reg_w - 1:0] out_82; + wire[sh_reg_w - 1:0] out_92; + + wire[sh_reg_w - 1:0] out_102; + wire[2 * sh_reg_w - 1:0] corr_out_0_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_1_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_2_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_3_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_4_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_5_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_6_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_7_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_8_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_9_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_10_tmp; + + sh_reg inst_sh_reg_r_1(clk, wen, d_r_1, d_r_2, out_r1, out_r2); + + sh_reg inst_sh_reg_0(clk, wen, d_l_1, d_l_2, out_01, out_02); + + sh_reg inst_sh_reg_1(clk, wen, out_01, out_02, out_11, out_12); + + sh_reg inst_sh_reg_2(clk, wen, out_11, out_12, out_21, out_22); + + sh_reg inst_sh_reg_3(clk, wen, out_21, out_22, out_31, out_32); + + sh_reg inst_sh_reg_4(clk, wen, out_31, out_32, out_41, out_42); + + sh_reg inst_sh_reg_5(clk, wen, out_41, out_42, out_51, out_52); + + sh_reg inst_sh_reg_6(clk, wen, out_51, out_52, out_61, out_62); + + sh_reg inst_sh_reg_7(clk, wen, out_61, out_62, out_71, out_72); + + sh_reg inst_sh_reg_8(clk, wen, out_71, out_72, out_81, out_82); + + sh_reg inst_sh_reg_9(clk, wen, out_81, out_82, out_91, out_92); + + sh_reg inst_sh_reg_10(clk, wen, out_91, out_92, out_101, out_102); + + corr inst_corr_0(clk, wen, out_01, out_02, out_r1, out_r2, corr_out_0_tmp); + + corr inst_corr_1(clk, wen, out_11, out_12, out_r1, out_r2, corr_out_1_tmp); + + corr inst_corr_2(clk, wen, out_21, out_22, out_r1, out_r2, corr_out_2_tmp); + + corr inst_corr_3(clk, wen, out_31, out_32, out_r1, out_r2, corr_out_3_tmp); + + corr inst_corr_4(clk, wen, out_41, out_42, out_r1, out_r2, corr_out_4_tmp); + + corr inst_corr_5(clk, wen, out_51, out_52, out_r1, out_r2, corr_out_5_tmp); + + corr inst_corr_6(clk, wen, out_61, out_62, out_r1, out_r2, corr_out_6_tmp); + + corr inst_corr_7(clk, wen, out_71, out_72, out_r1, out_r2, corr_out_7_tmp); + + corr inst_corr_8(clk, wen, out_81, out_82, out_r1, out_r2, corr_out_8_tmp); + + corr inst_corr_9(clk, wen, out_91, out_92, out_r1, out_r2, corr_out_9_tmp); + + corr inst_corr_10(clk, wen, out_101, out_102, out_r1, out_r2, corr_out_10_tmp); + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + corr_out_0 <= corr_out_0_tmp ; + corr_out_1 <= corr_out_1_tmp ; + corr_out_2 <= corr_out_2_tmp ; + corr_out_3 <= corr_out_3_tmp ; + corr_out_4 <= corr_out_4_tmp ; + corr_out_5 <= corr_out_5_tmp ; + corr_out_6 <= corr_out_6_tmp ; + corr_out_7 <= corr_out_7_tmp ; + corr_out_8 <= corr_out_8_tmp ; + corr_out_9 <= corr_out_9_tmp ; + corr_out_10 <= corr_out_10_tmp ; + end + else + begin + corr_out_0 <= corr_out_0; + corr_out_1 <= corr_out_1; + corr_out_2 <= corr_out_2; + corr_out_3 <= corr_out_3; + corr_out_4 <= corr_out_4; + corr_out_5 <= corr_out_5; + corr_out_6 <= corr_out_6; + corr_out_7 <= corr_out_7; + corr_out_8 <= corr_out_8; + corr_out_9 <= corr_out_9; + corr_out_10 <= corr_out_10; + end + + end +endmodule + + + +module wrapper_norm_corr_5_seq (clk, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5); + + parameter sh_reg_w = 4'b1000; + input clk; + input wen; + input[15:0] d_l_1; + input[15:0] d_l_2; + input[15:0] d_r_1; + input[15:0] d_r_2; + output[2 * sh_reg_w - 1:0] corr_out_0; + wire[2 * sh_reg_w - 1:0] corr_out_0; + output[2 * sh_reg_w - 1:0] corr_out_1; + wire[2 * sh_reg_w - 1:0] corr_out_1; + output[2 * sh_reg_w - 1:0] corr_out_2; + wire[2 * sh_reg_w - 1:0] corr_out_2; + output[2 * sh_reg_w - 1:0] corr_out_3; + wire[2 * sh_reg_w - 1:0] corr_out_3; + output[2 * sh_reg_w - 1:0] corr_out_4; + wire[2 * sh_reg_w - 1:0] corr_out_4; + output[2 * sh_reg_w - 1:0] corr_out_5; + wire[2 * sh_reg_w - 1:0] corr_out_5; + + wire[sh_reg_w - 1:0] d_l_1_nrm; + wire[sh_reg_w - 1:0] d_l_2_nrm; + wire[sh_reg_w - 1:0] d_r_1_nrm; + wire[sh_reg_w - 1:0] d_r_2_nrm; + + wrapper_norm_seq norm_inst_left(.clk(clk), .nd(wen), .din_1(d_l_1), .din_2(d_l_2), .dout_1(d_l_1_nrm), .dout_2(d_l_2_nrm)); + wrapper_norm_seq norm_inst_right(.clk(clk), .nd(wen), .din_1(d_r_1), .din_2(d_r_2), .dout_1(d_r_1_nrm), .dout_2(d_r_2_nrm)); + wrapper_corr_5_seq corr_5_inst (.tm3_clk_v0(clk), .wen(wen), .d_l_1(d_l_1_nrm), .d_l_2(d_l_2_nrm), .d_r_1(d_r_1_nrm), .d_r_2(d_r_2_nrm), .corr_out_0(corr_out_0), .corr_out_1(corr_out_1), .corr_out_2(corr_out_2), .corr_out_3(corr_out_3), .corr_out_4(corr_out_4), .corr_out_5(corr_out_5)); +endmodule + + + + +module wrapper_corr_5_seq (tm3_clk_v0, wen, d_l_1, d_l_2, d_r_1, d_r_2, corr_out_0, corr_out_1, corr_out_2, corr_out_3, corr_out_4, corr_out_5); + + parameter sh_reg_w = 4'b1000; + + input tm3_clk_v0; + input wen; + input[7:0] d_l_1; + input[7:0] d_l_2; + input[7:0] d_r_1; + input[7:0] d_r_2; + output[15:0] corr_out_0; + reg[15:0] corr_out_0; + output[15:0] corr_out_1; + reg[15:0] corr_out_1; + output[15:0] corr_out_2; + reg[15:0] corr_out_2; + output[15:0] corr_out_3; + reg[15:0] corr_out_3; + output[15:0] corr_out_4; + reg[15:0] corr_out_4; + output[15:0] corr_out_5; + reg[15:0] corr_out_5; + + wire[sh_reg_w - 1:0] out_r1; + wire[sh_reg_w - 1:0] out_01; + wire[sh_reg_w - 1:0] out_11; + wire[sh_reg_w - 1:0] out_21; + wire[sh_reg_w - 1:0] out_31; + wire[sh_reg_w - 1:0] out_41; + wire[sh_reg_w - 1:0] out_51; + wire[sh_reg_w - 1:0] out_r2; + wire[sh_reg_w - 1:0] out_02; + wire[sh_reg_w - 1:0] out_12; + wire[sh_reg_w - 1:0] out_22; + wire[sh_reg_w - 1:0] out_32; + wire[sh_reg_w - 1:0] out_42; + wire[sh_reg_w - 1:0] out_52; + wire[2 * sh_reg_w - 1:0] corr_out_0_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_1_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_2_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_3_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_4_tmp; + wire[2 * sh_reg_w - 1:0] corr_out_5_tmp; + + sh_reg inst_sh_reg_r_1(tm3_clk_v0, wen, d_r_1, d_r_2, out_r1, out_r2); + sh_reg inst_sh_reg_0(tm3_clk_v0, wen, d_l_1, d_l_2, out_01, out_02); + sh_reg inst_sh_reg_1(tm3_clk_v0, wen, out_01, out_02, out_11, out_12); + sh_reg inst_sh_reg_2(tm3_clk_v0, wen, out_11, out_12, out_21, out_22); + sh_reg inst_sh_reg_3(tm3_clk_v0, wen, out_21, out_22, out_31, out_32); + sh_reg inst_sh_reg_4(tm3_clk_v0, wen, out_31, out_32, out_41, out_42); + sh_reg inst_sh_reg_5(tm3_clk_v0, wen, out_41, out_42, out_51, out_52); + corr_seq inst_corr_0(tm3_clk_v0, wen, out_01, out_02, out_r1, out_r2, corr_out_0_tmp); + corr_seq inst_corr_1(tm3_clk_v0, wen, out_11, out_12, out_r1, out_r2, corr_out_1_tmp); + corr_seq inst_corr_2(tm3_clk_v0, wen, out_21, out_22, out_r1, out_r2, corr_out_2_tmp); + corr_seq inst_corr_3(tm3_clk_v0, wen, out_31, out_32, out_r1, out_r2, corr_out_3_tmp); + corr_seq inst_corr_4(tm3_clk_v0, wen, out_41, out_42, out_r1, out_r2, corr_out_4_tmp); + corr_seq inst_corr_5(tm3_clk_v0, wen, out_51, out_52, out_r1, out_r2, corr_out_5_tmp); + + always @(posedge tm3_clk_v0) + begin + if (wen == 1'b1) + begin + corr_out_0 <= corr_out_0_tmp ; + corr_out_1 <= corr_out_1_tmp ; + corr_out_2 <= corr_out_2_tmp ; + corr_out_3 <= corr_out_3_tmp ; + corr_out_4 <= corr_out_4_tmp ; + corr_out_5 <= corr_out_5_tmp ; + end + else + begin + corr_out_0 <= corr_out_0; + corr_out_1 <= corr_out_1; + corr_out_2 <= corr_out_2; + corr_out_3 <= corr_out_3; + corr_out_4 <= corr_out_4; + corr_out_5 <= corr_out_5; + end + end +endmodule + +module wrapper_norm_seq (clk, nd, din_1, din_2, dout_1, dout_2); + + parameter sh_reg_w = 4'b1000; + input clk; + input nd; + input[15:0] din_1; + input[15:0] din_2; + output[sh_reg_w - 1:0] dout_1; + wire[sh_reg_w - 1:0] dout_1; + output[sh_reg_w - 1:0] dout_2; + wire[sh_reg_w - 1:0] dout_2; + + reg[15:0] din_1_reg; + reg[15:0] din_2_reg; + reg[15:0] din_1_tmp1; + reg[15:0] din_2_tmp1; + reg[15:0] din_1_tmp2; + reg[15:0] din_2_tmp2; + reg[15:0] addin_1; + reg[15:0] addin_2; + reg[16:0] add_out; + + my_wrapper_divider my_div_inst_1 (nd, clk, din_1_tmp2, add_out, dout_1); + my_wrapper_divider my_div_inst_2 (nd, clk, din_2_tmp2, add_out, dout_2); + + always @(posedge clk) + begin + if (nd == 1'b1) + begin + din_1_reg <= din_1 ; + din_2_reg <= din_2 ; + end + else + begin + din_1_reg <= din_1_reg ; + din_2_reg <= din_2_reg ; + end + + din_1_tmp1 <= din_1_reg ; + din_1_tmp2 <= din_1_tmp1 ; + din_2_tmp1 <= din_2_reg ; + din_2_tmp2 <= din_2_tmp1 ; + + if ((din_1_reg[15]) == 1'b0) + begin + addin_1 <= din_1_reg ; + end + else + begin + addin_1 <= 16'b0000000000000000 - din_1_reg ; + end + + if ((din_2_reg[15]) == 1'b0) + begin + addin_2 <= din_2_reg + 16'b0000000000000001 ; + end + else + begin + addin_2 <= 16'b0000000000000001 - din_2_reg ; + end + + add_out <= ({addin_1[15], addin_1}) + ({addin_2[15], addin_2}) ; + end +endmodule + +module corr_seq (clk, new_data, in_l_re, in_l_im, in_r_re, in_r_im, corr_out); + + parameter sh_reg_w = 4'b1000; + input clk; + input new_data; + input[sh_reg_w - 1:0] in_l_re; + input[sh_reg_w - 1:0] in_l_im; + input[sh_reg_w - 1:0] in_r_re; + input[sh_reg_w - 1:0] in_r_im; + output[2 * sh_reg_w - 1:0] corr_out; + reg[2 * sh_reg_w - 1:0] corr_out; + reg[sh_reg_w - 1:0] in_l_re_reg; + reg[sh_reg_w - 1:0] in_l_im_reg; + reg[sh_reg_w - 1:0] in_r_re_reg; + reg[sh_reg_w - 1:0] in_r_im_reg; + reg[2 * sh_reg_w - 1:0] lrexrre_reg; + reg[2 * sh_reg_w - 1:0] limxrim_reg; + reg[2 * sh_reg_w - 1:0] corr_out_tmp; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + in_l_re_reg <= in_l_re ; + in_l_im_reg <= in_l_im ; + in_r_re_reg <= in_r_re ; + in_r_im_reg <= in_r_im ; + corr_out <= corr_out_tmp ; + end + else + begin + in_l_re_reg <= in_l_re_reg ; + in_l_im_reg <= in_l_im_reg ; + in_r_re_reg <= in_r_re_reg ; + in_r_im_reg <= in_r_im_reg ; + corr_out <= corr_out; + end + // PAJ - replaced by me, but called mult_slow + lrexrre_reg <= in_l_re_reg*in_r_re_reg ; + limxrim_reg <= in_l_im_reg*in_r_im_reg ; + corr_out_tmp <= lrexrre_reg + limxrim_reg ; + end + endmodule +module port_bus_1to0 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_2to3_left, v_corr_05_00, v_corr_05_01, v_corr_05_02, v_corr_05_03, v_corr_05_04, v_corr_05_05, v_corr_10_00, v_corr_10_01, v_corr_10_02, v_corr_10_03, v_corr_10_04, v_corr_10_05, v_corr_10_06, v_corr_10_07, v_corr_10_08, v_corr_10_09, v_corr_10_10, v_corr_20_00, v_corr_20_01, v_corr_20_02, v_corr_20_03, v_corr_20_04, v_corr_20_05, v_corr_20_06, v_corr_20_07, v_corr_20_08, v_corr_20_09, v_corr_20_10, v_corr_20_11, v_corr_20_12, v_corr_20_13, v_corr_20_14, v_corr_20_15, v_corr_20_16, v_corr_20_17, v_corr_20_18, v_corr_20_19, v_corr_20_20, bus_word_1, bus_word_2, bus_word_3, bus_word_4, bus_word_5, bus_word_6, counter_out, rst); + + parameter corr_res_w = 4'b1000; + input rst; + input clk; + input[18:0] vidin_addr_reg; + input svid_comp_switch; + input vidin_new_data_scld_1_2to3_left; + input[corr_res_w - 1:0] v_corr_05_00; + input[corr_res_w - 1:0] v_corr_05_01; + input[corr_res_w - 1:0] v_corr_05_02; + input[corr_res_w - 1:0] v_corr_05_03; + input[corr_res_w - 1:0] v_corr_05_04; + input[corr_res_w - 1:0] v_corr_05_05; + input[corr_res_w - 1:0] v_corr_10_00; + input[corr_res_w - 1:0] v_corr_10_01; + input[corr_res_w - 1:0] v_corr_10_02; + input[corr_res_w - 1:0] v_corr_10_03; + input[corr_res_w - 1:0] v_corr_10_04; + input[corr_res_w - 1:0] v_corr_10_05; + input[corr_res_w - 1:0] v_corr_10_06; + input[corr_res_w - 1:0] v_corr_10_07; + input[corr_res_w - 1:0] v_corr_10_08; + input[corr_res_w - 1:0] v_corr_10_09; + input[corr_res_w - 1:0] v_corr_10_10; + input[corr_res_w - 1:0] v_corr_20_00; + input[corr_res_w - 1:0] v_corr_20_01; + input[corr_res_w - 1:0] v_corr_20_02; + input[corr_res_w - 1:0] v_corr_20_03; + input[corr_res_w - 1:0] v_corr_20_04; + input[corr_res_w - 1:0] v_corr_20_05; + input[corr_res_w - 1:0] v_corr_20_06; + input[corr_res_w - 1:0] v_corr_20_07; + input[corr_res_w - 1:0] v_corr_20_08; + input[corr_res_w - 1:0] v_corr_20_09; + input[corr_res_w - 1:0] v_corr_20_10; + input[corr_res_w - 1:0] v_corr_20_11; + input[corr_res_w - 1:0] v_corr_20_12; + input[corr_res_w - 1:0] v_corr_20_13; + input[corr_res_w - 1:0] v_corr_20_14; + input[corr_res_w - 1:0] v_corr_20_15; + input[corr_res_w - 1:0] v_corr_20_16; + input[corr_res_w - 1:0] v_corr_20_17; + input[corr_res_w - 1:0] v_corr_20_18; + input[corr_res_w - 1:0] v_corr_20_19; + input[corr_res_w - 1:0] v_corr_20_20; + output[7:0] bus_word_1; + reg[7:0] bus_word_1; + output[7:0] bus_word_2; + reg[7:0] bus_word_2; + output[7:0] bus_word_3; + reg[7:0] bus_word_3; + output[7:0] bus_word_4; + reg[7:0] bus_word_4; + output[7:0] bus_word_5; + reg[7:0] bus_word_5; + output[7:0] bus_word_6; + reg[7:0] bus_word_6; + output[2:0] counter_out; + reg[2:0] counter_out; + + reg[7:0] bus_word_1_tmp; + reg[7:0] bus_word_2_tmp; + reg[7:0] bus_word_3_tmp; + reg[7:0] bus_word_4_tmp; + reg[7:0] bus_word_5_tmp; + reg[7:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; + wire vidin_new_data_scld_1_2to3_left_tmp; + reg[3:0] counter; + reg[2:0] counter_out_tmp; + reg[corr_res_w - 1:0] v_corr_05_00_tmp; + reg[corr_res_w - 1:0] v_corr_05_01_tmp; + reg[corr_res_w - 1:0] v_corr_05_02_tmp; + reg[corr_res_w - 1:0] v_corr_05_03_tmp; + reg[corr_res_w - 1:0] v_corr_05_04_tmp; + reg[corr_res_w - 1:0] v_corr_05_05_tmp; + reg[corr_res_w - 1:0] v_corr_10_00_tmp; + reg[corr_res_w - 1:0] v_corr_10_01_tmp; + reg[corr_res_w - 1:0] v_corr_10_02_tmp; + reg[corr_res_w - 1:0] v_corr_10_03_tmp; + reg[corr_res_w - 1:0] v_corr_10_04_tmp; + reg[corr_res_w - 1:0] v_corr_10_05_tmp; + reg[corr_res_w - 1:0] v_corr_10_06_tmp; + reg[corr_res_w - 1:0] v_corr_10_07_tmp; + reg[corr_res_w - 1:0] v_corr_10_08_tmp; + reg[corr_res_w - 1:0] v_corr_10_09_tmp; + reg[corr_res_w - 1:0] v_corr_10_10_tmp; + reg[corr_res_w - 1:0] v_corr_20_00_tmp; + reg[corr_res_w - 1:0] v_corr_20_01_tmp; + reg[corr_res_w - 1:0] v_corr_20_02_tmp; + reg[corr_res_w - 1:0] v_corr_20_03_tmp; + reg[corr_res_w - 1:0] v_corr_20_04_tmp; + reg[corr_res_w - 1:0] v_corr_20_05_tmp; + reg[corr_res_w - 1:0] v_corr_20_06_tmp; + reg[corr_res_w - 1:0] v_corr_20_07_tmp; + reg[corr_res_w - 1:0] v_corr_20_08_tmp; + reg[corr_res_w - 1:0] v_corr_20_09_tmp; + reg[corr_res_w - 1:0] v_corr_20_10_tmp; + reg[corr_res_w - 1:0] v_corr_20_11_tmp; + reg[corr_res_w - 1:0] v_corr_20_12_tmp; + reg[corr_res_w - 1:0] v_corr_20_13_tmp; + reg[corr_res_w - 1:0] v_corr_20_14_tmp; + reg[corr_res_w - 1:0] v_corr_20_15_tmp; + reg[corr_res_w - 1:0] v_corr_20_16_tmp; + reg[corr_res_w - 1:0] v_corr_20_17_tmp; + reg[corr_res_w - 1:0] v_corr_20_18_tmp; + reg[corr_res_w - 1:0] v_corr_20_19_tmp; + reg[corr_res_w - 1:0] v_corr_20_20_tmp; + + always @(posedge clk) + begin + if (rst) + begin + counter <= 0; + counter_out_tmp <= 3'b000 ; + bus_word_1_tmp <= 8'b00000000 ; + bus_word_2_tmp <= 8'b00000000 ; + bus_word_3_tmp <= 8'b00000000 ; + bus_word_4_tmp <= 8'b00000000 ; + bus_word_5_tmp <= 8'b00000000 ; + bus_word_6_tmp <= 8'b00000000 ; + end + else + begin + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + counter <= 4'b0001 ; + end + else + begin + if (counter == 4'b1000) + begin + counter <= 4'b1000 ; + end + else + begin + counter <= counter + 1 ; + end + end + case (counter[2:0]) + 3'b000 : + begin + counter_out_tmp <= 3'b000 ; + bus_word_1_tmp <= 8'b00000000 ; + bus_word_2_tmp <= 8'b00000000 ; + bus_word_3_tmp <= 8'b00000000 ; + bus_word_4_tmp <= 8'b00000000 ; + bus_word_5_tmp <= 8'b00000000 ; + bus_word_6_tmp <= 8'b00000000 ; + end + 3'b001 : + begin + counter_out_tmp <= 3'b001 ; + bus_word_1_tmp <= vidin_addr_reg_tmp[7:0] ; + bus_word_2_tmp <= vidin_addr_reg_tmp[15:8] ; + bus_word_3_tmp <= {vidin_addr_reg_tmp[18:16], svid_comp_switch_tmp, 4'b0000} ; + bus_word_4_tmp <= v_corr_05_00_tmp ; + bus_word_5_tmp <= v_corr_05_01_tmp ; + bus_word_6_tmp <= v_corr_05_02_tmp ; + end + 3'b010 : + begin + counter_out_tmp <= 3'b010 ; + bus_word_1_tmp <= v_corr_05_03_tmp ; + bus_word_2_tmp <= v_corr_05_04_tmp ; + bus_word_3_tmp <= v_corr_05_05_tmp ; + bus_word_4_tmp <= v_corr_10_00_tmp ; + bus_word_5_tmp <= v_corr_10_01_tmp ; + bus_word_6_tmp <= v_corr_10_02_tmp ; + end + 3'b011 : + begin + counter_out_tmp <= 3'b011 ; + bus_word_1_tmp <= v_corr_10_03_tmp ; + bus_word_2_tmp <= v_corr_10_04_tmp ; + bus_word_3_tmp <= v_corr_10_05_tmp ; + bus_word_4_tmp <= v_corr_10_06_tmp ; + bus_word_5_tmp <= v_corr_10_07_tmp ; + bus_word_6_tmp <= v_corr_10_08_tmp ; + end + 3'b100 : + begin + counter_out_tmp <= 3'b100 ; + bus_word_1_tmp <= v_corr_10_09_tmp ; + bus_word_2_tmp <= v_corr_10_10_tmp ; + bus_word_3_tmp <= v_corr_20_00_tmp ; + bus_word_4_tmp <= v_corr_20_01_tmp ; + bus_word_5_tmp <= v_corr_20_02_tmp ; + bus_word_6_tmp <= v_corr_20_03_tmp ; + end + 3'b101 : + + begin + counter_out_tmp <= 3'b101 ; + bus_word_1_tmp <= v_corr_20_04_tmp ; + bus_word_2_tmp <= v_corr_20_05_tmp ; + bus_word_3_tmp <= v_corr_20_06_tmp ; + bus_word_4_tmp <= v_corr_20_07_tmp ; + bus_word_5_tmp <= v_corr_20_08_tmp ; + bus_word_6_tmp <= v_corr_20_09_tmp ; + end + 3'b110 : + begin + counter_out_tmp <= 3'b110 ; + bus_word_1_tmp <= v_corr_20_10_tmp ; + bus_word_2_tmp <= v_corr_20_11_tmp ; + bus_word_3_tmp <= v_corr_20_12_tmp ; + bus_word_4_tmp <= v_corr_20_13_tmp ; + bus_word_5_tmp <= v_corr_20_14_tmp ; + bus_word_6_tmp <= v_corr_20_15_tmp ; + end + 3'b111 : + begin + counter_out_tmp <= 3'b111 ; + bus_word_1_tmp <= v_corr_20_16_tmp ; + bus_word_2_tmp <= v_corr_20_17_tmp ; + bus_word_3_tmp <= v_corr_20_18_tmp ; + bus_word_4_tmp <= v_corr_20_19_tmp ; + bus_word_5_tmp <= v_corr_20_20_tmp ; + bus_word_6_tmp <= 8'b00000000 ; + end + default : + begin + counter_out_tmp <= 3'b111 ; + bus_word_1_tmp <= v_corr_20_16_tmp ; + bus_word_2_tmp <= v_corr_20_17_tmp ; + bus_word_3_tmp <= v_corr_20_18_tmp ; + bus_word_4_tmp <= v_corr_20_19_tmp ; + bus_word_5_tmp <= v_corr_20_20_tmp ; + bus_word_6_tmp <= 8'b00000000 ; + end + endcase + end + end + + always @(posedge clk) + begin + if (rst) + begin + counter_out <= 0; + bus_word_1 <= 0; + bus_word_2 <= 0; + bus_word_3 <= 0; + bus_word_4 <= 0; + bus_word_5 <= 0; + bus_word_6 <= 0; + end + else + begin + counter_out <= counter_out_tmp ; + bus_word_1 <= bus_word_1_tmp ; + bus_word_2 <= bus_word_2_tmp ; + bus_word_3 <= bus_word_3_tmp ; + bus_word_4 <= bus_word_4_tmp ; + bus_word_5 <= bus_word_5_tmp ; + bus_word_6 <= bus_word_6_tmp ; + end + + + if (rst) + begin + vidin_addr_reg_tmp <= 0; + svid_comp_switch_tmp <= 0; + v_corr_05_00_tmp <= 0 ; + v_corr_05_01_tmp <= 0 ; + v_corr_05_02_tmp <= 0 ; + v_corr_05_03_tmp <= 0; + v_corr_05_04_tmp <= 0 ; + v_corr_05_05_tmp <= 0 ; + v_corr_10_00_tmp <= 0 ; + v_corr_10_01_tmp <= 0 ; + v_corr_10_02_tmp <= 0 ; + v_corr_10_03_tmp <= 0 ; + v_corr_10_04_tmp <= 0 ; + v_corr_10_05_tmp <= 0 ; + v_corr_10_06_tmp <= 0 ; + v_corr_10_07_tmp <= 0; + v_corr_10_08_tmp <= 0; + v_corr_10_09_tmp <= 0; + v_corr_10_10_tmp <= 0; + v_corr_20_00_tmp <= 0; + v_corr_20_01_tmp <= 0; + v_corr_20_02_tmp <= 0; + v_corr_20_03_tmp <= 0; + v_corr_20_04_tmp <= 0; + v_corr_20_05_tmp <= 0; + v_corr_20_06_tmp <= 0; + v_corr_20_07_tmp <= 0; + v_corr_20_08_tmp <= 0; + v_corr_20_09_tmp <= 0; + v_corr_20_10_tmp <= 0; + v_corr_20_11_tmp <= 0; + v_corr_20_12_tmp <= 0; + v_corr_20_13_tmp <= 0; + v_corr_20_14_tmp <= 0; + v_corr_20_15_tmp <= 0; + v_corr_20_16_tmp <= 0; + v_corr_20_17_tmp <= 0; + v_corr_20_18_tmp <= 0; + v_corr_20_19_tmp <= 0; + v_corr_20_20_tmp <= 0; + end + else if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + vidin_addr_reg_tmp <= vidin_addr_reg ; + svid_comp_switch_tmp <= svid_comp_switch ; + v_corr_05_00_tmp <= v_corr_05_00 ; + v_corr_05_01_tmp <= v_corr_05_01 ; + v_corr_05_02_tmp <= v_corr_05_02 ; + v_corr_05_03_tmp <= v_corr_05_03 ; + v_corr_05_04_tmp <= v_corr_05_04 ; + v_corr_05_05_tmp <= v_corr_05_05 ; + v_corr_10_00_tmp <= v_corr_10_00 ; + v_corr_10_01_tmp <= v_corr_10_01 ; + v_corr_10_02_tmp <= v_corr_10_02 ; + v_corr_10_03_tmp <= v_corr_10_03 ; + v_corr_10_04_tmp <= v_corr_10_04 ; + v_corr_10_05_tmp <= v_corr_10_05 ; + v_corr_10_06_tmp <= v_corr_10_06 ; + v_corr_10_07_tmp <= v_corr_10_07 ; + v_corr_10_08_tmp <= v_corr_10_08 ; + v_corr_10_09_tmp <= v_corr_10_09 ; + v_corr_10_10_tmp <= v_corr_10_10 ; + v_corr_20_00_tmp <= v_corr_20_00 ; + v_corr_20_01_tmp <= v_corr_20_01 ; + v_corr_20_02_tmp <= v_corr_20_02 ; + v_corr_20_03_tmp <= v_corr_20_03 ; + v_corr_20_04_tmp <= v_corr_20_04 ; + v_corr_20_05_tmp <= v_corr_20_05 ; + v_corr_20_06_tmp <= v_corr_20_06 ; + v_corr_20_07_tmp <= v_corr_20_07 ; + v_corr_20_08_tmp <= v_corr_20_08 ; + v_corr_20_09_tmp <= v_corr_20_09 ; + v_corr_20_10_tmp <= v_corr_20_10 ; + v_corr_20_11_tmp <= v_corr_20_11 ; + v_corr_20_12_tmp <= v_corr_20_12 ; + v_corr_20_13_tmp <= v_corr_20_13 ; + v_corr_20_14_tmp <= v_corr_20_14 ; + v_corr_20_15_tmp <= v_corr_20_15 ; + v_corr_20_16_tmp <= v_corr_20_16 ; + v_corr_20_17_tmp <= v_corr_20_17 ; + v_corr_20_18_tmp <= v_corr_20_18 ; + v_corr_20_19_tmp <= v_corr_20_19 ; + v_corr_20_20_tmp <= v_corr_20_20 ; + end + else + begin + vidin_addr_reg_tmp <= vidin_addr_reg_tmp ; + svid_comp_switch_tmp <= svid_comp_switch_tmp ; + v_corr_05_00_tmp <= v_corr_05_00_tmp ; + v_corr_05_01_tmp <= v_corr_05_01_tmp ; + v_corr_05_02_tmp <= v_corr_05_02_tmp ; + v_corr_05_03_tmp <= v_corr_05_03_tmp ; + v_corr_05_04_tmp <= v_corr_05_04_tmp ; + v_corr_05_05_tmp <= v_corr_05_05_tmp ; + v_corr_10_00_tmp <= v_corr_10_00_tmp ; + v_corr_10_01_tmp <= v_corr_10_01_tmp ; + v_corr_10_02_tmp <= v_corr_10_02_tmp ; + v_corr_10_03_tmp <= v_corr_10_03_tmp ; + v_corr_10_04_tmp <= v_corr_10_04_tmp ; + v_corr_10_05_tmp <= v_corr_10_05_tmp ; + v_corr_10_06_tmp <= v_corr_10_06_tmp ; + v_corr_10_07_tmp <= v_corr_10_07_tmp ; + v_corr_10_08_tmp <= v_corr_10_08_tmp ; + v_corr_10_09_tmp <= v_corr_10_09_tmp ; + v_corr_10_10_tmp <= v_corr_10_10_tmp ; + v_corr_20_00_tmp <= v_corr_20_00_tmp ; + v_corr_20_01_tmp <= v_corr_20_01_tmp ; + v_corr_20_02_tmp <= v_corr_20_02_tmp ; + v_corr_20_03_tmp <= v_corr_20_03_tmp ; + v_corr_20_04_tmp <= v_corr_20_04_tmp ; + v_corr_20_05_tmp <= v_corr_20_05_tmp ; + v_corr_20_06_tmp <= v_corr_20_06_tmp ; + v_corr_20_07_tmp <= v_corr_20_07_tmp ; + v_corr_20_08_tmp <= v_corr_20_08_tmp ; + v_corr_20_09_tmp <= v_corr_20_09_tmp ; + v_corr_20_10_tmp <= v_corr_20_10_tmp ; + v_corr_20_11_tmp <= v_corr_20_11_tmp ; + v_corr_20_12_tmp <= v_corr_20_12_tmp ; + v_corr_20_13_tmp <= v_corr_20_13_tmp ; + v_corr_20_14_tmp <= v_corr_20_14_tmp ; + v_corr_20_15_tmp <= v_corr_20_15_tmp ; + v_corr_20_16_tmp <= v_corr_20_16_tmp ; + v_corr_20_17_tmp <= v_corr_20_17_tmp ; + v_corr_20_18_tmp <= v_corr_20_18_tmp ; + v_corr_20_19_tmp <= v_corr_20_19_tmp ; + v_corr_20_20_tmp <= v_corr_20_20_tmp ; + end + end +endmodule +module my_wrapper_divider(rst, clk, data_in_a, data_in_b, data_out); + parameter INPUT_WIDTH_A = 5'b10000; + parameter INPUT_WIDTH_B = 5'b10001; + parameter OUTPUT_WIDTH = 4'b1000; + + parameter S1 = 2'b00; + parameter S2 = 2'b01; + parameter S3 = 2'b10; + parameter S4 = 2'b11; + + input rst; + input clk; + input [INPUT_WIDTH_A-1:0]data_in_a; + input [INPUT_WIDTH_B-1:0]data_in_b; + output [OUTPUT_WIDTH-1:0]data_out; + wire [OUTPUT_WIDTH-1:0]data_out; + + wire [OUTPUT_WIDTH-1:0]Remainder; + + reg start, LA, EB; + wire Done; + reg[1:0] y, Y; + + my_divider my_divider_inst(clk, rst, start, LA, EB, data_in_a, data_in_b, Remainder, data_out, Done); + + always @(posedge clk) + begin + if (rst == 0) + y <= S1; + else + y <= Y; + end + + always @(y) + begin + case (y) + S1 : + begin + LA = 0; + EB = 0; + start = 0; + Y = S2; + end + S2 : + begin + LA = 1; + EB = 1; + start = 0; + Y = S3; + end + S3 : + begin + LA = 0; + EB = 0; + start = 1; + Y = S4; + end + S4 : + begin + LA = 0; + EB = 0; + start = 0; + if (Done == 1'b1) + begin + Y = S1; + end + else + begin + Y = S4; + end + end + endcase + end +endmodule + +module my_divider(clk, rst, start, LA, EB, data_in_a, data_in_b, Remainder, data_out, Done); + + parameter INPUT_WIDTH_A = 5'b10000; + parameter INPUT_WIDTH_B = 5'b10001; + parameter OUTPUT_WIDTH = 4'b1000; + parameter LOGN = 3'b100; + + parameter S1 = 2'b00; + parameter S2 = 2'b01; + parameter S3 = 2'b10; + + input clk; + input [INPUT_WIDTH_A-1:0]data_in_a; + input [INPUT_WIDTH_B-1:0]data_in_b; + input rst; + input start; + input LA; + input EB; + output [OUTPUT_WIDTH-1:0]data_out; + wire [OUTPUT_WIDTH-1:0]data_out; + output [OUTPUT_WIDTH-1:0]Remainder; + reg [OUTPUT_WIDTH-1:0]Remainder; + output Done; + reg Done; + + wire Cout, zero; + wire [INPUT_WIDTH_A-1:0] Sum; + reg [1:0] y, Y; + reg [LOGN-1:0] Count; + reg EA, Rsel, LR, ER, ER0, LC, EC; + reg [INPUT_WIDTH_B-1:0] RegB; + reg [INPUT_WIDTH_A-1:0] DataA; + reg ff0; + + always @(start or y or zero) + begin + case(y) + S1: + begin + if (start == 0) + Y = S1; + else + Y = S2; + end + S2: + begin + if (zero == 0) + Y = S2; + else + Y = S3; + end + S3: + begin + if (start == 1) + Y = S3; + else + Y = S1; + end + default: + begin + Y = 2'b00; + end + endcase + end + + always @(posedge clk) + begin + if (rst == 0) + y <= S1; + else + y <= Y; + end + + always @(y or start or Cout or zero) + begin + case (y) + S1: + begin + LC = 1; + ER = 1; + EC = 0; + Rsel = 0; + Done = 0; + if (start == 0) + begin + LR = 1; + ER0 = 1; + EA = 0; + end + else + begin + LR = 0; + EA = 1; + ER0 = 1; + end + end + S2: + begin + LC = 0; + ER = 1; + Rsel = 1; + Done = 0; + ER0 = 1; + EA = 1; + if (Cout) + LR = 1; + else + LR = 0; + if (zero == 0) + EC = 1; + else + EC = 0; + end + S3: + begin + Done = 1; + LR = 0; + LC = 0; + ER = 0; + EC = 0; + Rsel = 0; + ER0 = 0; + EA = 0; + end + default: + begin + Done = 0; + LR = 0; + LC = 0; + ER = 0; + EC = 0; + Rsel = 0; + ER0 = 0; + EA = 0; + end + endcase + end + + always @(posedge clk) + begin + if (rst == 1) + begin + RegB <= 0; + Remainder <= 0; + DataA <= 0; + ff0 <= 0; + Count <= 0; + end + else + begin + if (EB == 1) + begin + RegB <= data_in_b; + end + else + begin + RegB <= RegB; + end + + if (LR == 1) + begin + Remainder <= Rsel ? Sum : 0; + end + else if (ER == 1) + begin + Remainder <= (Remainder << 1) | ff0; + end + else + begin + Remainder <= Remainder; + end + + if (LA == 1) + begin + DataA <= data_in_a; + end + else if (EA == 1) + begin + DataA <= (DataA << 1) | Cout; + end + else + begin + DataA <= DataA; + end + + if (ER0 == 1) + begin + ff0 <= DataA[INPUT_WIDTH_A-1]; + end + else + begin + ff0 <= 0; + end + + if (LC == 1) + begin + Count <= 0; + end + else if (EC == 1) + begin + Count <= Count + 1; + end + else + begin + Count <= Count; + end + end + end + + assign zero = (Count == 0); + assign Sum = {Remainder, ff0} + (~RegB + 1); + assign Cout = Sum[INPUT_WIDTH_A-1:0]; + assign data_out = DataA; + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v new file mode 100755 index 000000000..dba6741aa --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v @@ -0,0 +1,1846 @@ +module sv_chip2_hierarchy_no_mem (reset, tm3_clk_v0, vidin_new_data, vidin_rgb_reg, vidin_addr_reg, svid_comp_switch, counter_out_2to1, bus_word_3_2to1, bus_word_4_2to1, bus_word_5_2to1, bus_word_6_2to1, vidin_new_data_fifo, vidin_rgb_reg_fifo_left, vidin_rgb_reg_fifo_right, vidin_addr_reg_2to0, v_nd_s1_left_2to0, v_nd_s2_left_2to0 , v_nd_s4_left_2to0 , v_d_reg_s1_left_2to0 , v_d_reg_s2_left_2to0 , v_d_reg_s4_left_2to0 , v_nd_s1_right_2to0, v_nd_s2_right_2to0 , v_nd_s4_right_2to0 , v_d_reg_s1_right_2to0 , v_d_reg_s2_right_2to0 , v_d_reg_s4_right_2to0,offchip_sram_data_in,offchip_sram_addr,offchip_sram_data_out,offchip_sram_we,offchip_sram_oe,tm3_sram_adsp); + + input [63:0]offchip_sram_data_in; + output [18:0]offchip_sram_addr; + output [63:0]offchip_sram_data_out; + output [7:0]offchip_sram_we; + output [1:0]offchip_sram_oe; + + input reset; + input tm3_clk_v0; + + wire[63:0] tm3_sram_data_in; + + wire[63:0] tm3_sram_data_out; + reg[63:0] tm3_sram_data_xhdl0; + + reg[18:0] tm3_sram_addr; + + reg[7:0] tm3_sram_we; + + reg[1:0] tm3_sram_oe; + output tm3_sram_adsp; + reg tm3_sram_adsp; + input vidin_new_data; + input[7:0] vidin_rgb_reg; + input[18:0] vidin_addr_reg; + input svid_comp_switch; + output[2:0] counter_out_2to1; + wire[2:0] counter_out_2to1; + output[15:0] bus_word_3_2to1; + wire[15:0] bus_word_3_2to1; + output[15:0] bus_word_4_2to1; + wire[15:0] bus_word_4_2to1; + output[15:0] bus_word_5_2to1; + wire[15:0] bus_word_5_2to1; + output[15:0] bus_word_6_2to1; + wire[15:0] bus_word_6_2to1; + output vidin_new_data_fifo; + reg vidin_new_data_fifo; + output[7:0] vidin_rgb_reg_fifo_left; + reg[7:0] vidin_rgb_reg_fifo_left; + output[7:0] vidin_rgb_reg_fifo_right; + reg[7:0] vidin_rgb_reg_fifo_right; + output[3:0] vidin_addr_reg_2to0; + reg[3:0] vidin_addr_reg_2to0; + input v_nd_s1_left_2to0; + input v_nd_s2_left_2to0; + input v_nd_s4_left_2to0; + input[7:0] v_d_reg_s1_left_2to0; + input[7:0] v_d_reg_s2_left_2to0; + input[7:0] v_d_reg_s4_left_2to0; + input v_nd_s1_right_2to0; + input v_nd_s2_right_2to0; + input v_nd_s4_right_2to0; + input[7:0] v_d_reg_s1_right_2to0; + input[7:0] v_d_reg_s2_right_2to0; + input[7:0] v_d_reg_s4_right_2to0; + + wire v_nd_s1; + wire vidin_new_data_v_fltr; + reg[9:0] horiz; + reg[9:0] vert; + reg[63:0] vidin_data_buf_sc_1; + reg[55:0] vidin_data_buf_2_sc_1; + reg[18:0] vidin_addr_buf_sc_1; + reg[13:0] vidin_addr_buf_sc_1_fifo; + wire[18:0] vidin_addr_reg_scld; + reg video_state; + wire[7:0] vidin_gray_scld_1; + reg[63:0] vidout_buf_fifo_1_left; + reg[63:0] vidout_buf_fifo_1_right; + reg[7:0] vidin_rgb_reg_tmp; + reg[7:0] vidin_data_buf_fifo_sc_1_l; + reg[7:0] vidin_data_buf_fifo_sc_1_r; + reg[63:0] vidout_buf_fifo_2_1_left; + reg[63:0] vidout_buf_fifo_2_1_right; + wire vidin_new_data_tmp; + reg[18:0] vidin_addr_reg_reg; + reg v_nd_s1_left; + reg v_nd_s1_right; + reg v_nd_s2_left; + reg v_nd_s2_right; + reg v_nd_s4_left; + reg v_nd_s4_right; + reg[7:0] v_d_reg_s1_left; + reg[7:0] v_d_reg_s1_right; + reg[7:0] v_d_reg_s2_left; + reg[7:0] v_d_reg_s2_right; + reg[7:0] v_d_reg_s4_left; + reg[7:0] v_d_reg_s4_right; + wire[15:0] vidin_v_out_1_f1_left; + wire[15:0] vidin_v_out_1_f2_left; + wire[15:0] vidin_v_out_1_f3_left; + wire[15:0] vidin_v_out_1_h1_left; + wire[15:0] vidin_v_out_1_h2_left; + wire[15:0] vidin_v_out_1_h3_left; + wire[15:0] vidin_v_out_1_h4_left; + wire[15:0] vidin_v_out_2_f1_left; + wire[15:0] vidin_v_out_2_f2_left; + wire[15:0] vidin_v_out_2_f3_left; + wire[15:0] vidin_v_out_2_h1_left; + wire[15:0] vidin_v_out_2_h2_left; + wire[15:0] vidin_v_out_2_h3_left; + wire[15:0] vidin_v_out_2_h4_left; + wire[15:0] vidin_v_out_4_f1_left; + wire[15:0] vidin_v_out_4_f2_left; + wire[15:0] vidin_v_out_4_f3_left; + wire[15:0] vidin_v_out_4_h1_left; + wire[15:0] vidin_v_out_4_h2_left; + wire[15:0] vidin_v_out_4_h3_left; + wire[15:0] vidin_v_out_4_h4_left; + wire[15:0] vidin_v_out_1_f1_right; + wire[15:0] vidin_v_out_1_f2_right; + wire[15:0] vidin_v_out_1_f3_right; + wire[15:0] vidin_v_out_1_h1_right; + wire[15:0] vidin_v_out_1_h2_right; + wire[15:0] vidin_v_out_1_h3_right; + wire[15:0] vidin_v_out_1_h4_right; + wire[15:0] vidin_v_out_2_f1_right; + wire[15:0] vidin_v_out_2_f2_right; + wire[15:0] vidin_v_out_2_f3_right; + wire[15:0] vidin_v_out_2_h1_right; + wire[15:0] vidin_v_out_2_h2_right; + wire[15:0] vidin_v_out_2_h3_right; + wire[15:0] vidin_v_out_2_h4_right; + wire[15:0] vidin_v_out_4_f1_right; + wire[15:0] vidin_v_out_4_f2_right; + wire[15:0] vidin_v_out_4_f3_right; + wire[15:0] vidin_v_out_4_h1_right; + wire[15:0] vidin_v_out_4_h2_right; + wire[15:0] vidin_v_out_4_h3_right; + wire[15:0] vidin_v_out_4_h4_right; + wire[7:0] v_d_reg_s1_2to3_left; + wire[7:0] v_d_reg_s2_2to3_left; + wire[7:0] v_d_reg_s4_2to3_left; + wire[7:0] v_d_reg_s1_2to3_right; + wire[7:0] v_d_reg_s2_2to3_right; + wire[7:0] v_d_reg_s4_2to3_right; + reg[18:0] vidin_addr_reg_2to3; + reg svid_comp_switch_2to3; + wire[15:0] real_z_4_left; + wire[15:0] imag_z_4_left; + wire[15:0] real_p_4_left; + wire[15:0] imag_p_4_left; + wire[15:0] real_n_4_left; + wire[15:0] imag_n_4_left; + wire[15:0] real_z_4_right; + wire[15:0] imag_z_4_right; + wire[15:0] real_p_4_right; + wire[15:0] imag_p_4_right; + wire[15:0] real_n_4_right; + wire[15:0] imag_n_4_right; + wire[15:0] real_z_2_left; + wire[15:0] imag_z_2_left; + wire[15:0] real_p_2_left; + wire[15:0] imag_p_2_left; + wire[15:0] real_n_2_left; + wire[15:0] imag_n_2_left; + wire[15:0] real_z_2_right; + wire[15:0] imag_z_2_right; + wire[15:0] real_p_2_right; + wire[15:0] imag_p_2_right; + wire[15:0] real_n_2_right; + wire[15:0] imag_n_2_right; + wire[15:0] real_z_1_left; + wire[15:0] imag_z_1_left; + wire[15:0] real_p_1_left; + wire[15:0] imag_p_1_left; + wire[15:0] real_n_1_left; + wire[15:0] imag_n_1_left; + wire[15:0] real_z_1_right; + wire[15:0] imag_z_1_right; + wire[15:0] real_p_1_right; + wire[15:0] imag_p_1_right; + wire[15:0] real_n_1_right; + wire[15:0] imag_n_1_right; + + assign tm3_sram_data_in = offchip_sram_data_in; + assign offchip_sram_addr = tm3_sram_addr; + assign offchip_sram_data_out = tm3_sram_data_out; + assign offchip_sram_we = tm3_sram_we; + assign offchip_sram_oe = tm3_sram_oe; + assign tm3_sram_data_out = tm3_sram_data_xhdl0; + + v_fltr_496x7 v_fltr_1_left(tm3_clk_v0, v_nd_s1_left, v_d_reg_s1_left, vidin_v_out_1_f1_left, vidin_v_out_1_f2_left, vidin_v_out_1_f3_left, vidin_v_out_1_h1_left, vidin_v_out_1_h2_left, vidin_v_out_1_h3_left, vidin_v_out_1_h4_left); + v_fltr_316x7 v_fltr_2_left(tm3_clk_v0, v_nd_s2_left, v_d_reg_s2_left, vidin_v_out_2_f1_left, vidin_v_out_2_f2_left, vidin_v_out_2_f3_left, vidin_v_out_2_h1_left, vidin_v_out_2_h2_left, vidin_v_out_2_h3_left, vidin_v_out_2_h4_left); + v_fltr_226x7 v_fltr_4_left(tm3_clk_v0, v_nd_s4_left, v_d_reg_s4_left, vidin_v_out_4_f1_left, vidin_v_out_4_f2_left, vidin_v_out_4_f3_left, vidin_v_out_4_h1_left, vidin_v_out_4_h2_left, vidin_v_out_4_h3_left, vidin_v_out_4_h4_left); + h_fltr h_fltr_1_left (tm3_clk_v0, v_nd_s1_left, vidin_v_out_1_f1_left, vidin_v_out_1_f2_left, vidin_v_out_1_f3_left, vidin_v_out_1_h1_left, vidin_v_out_1_h2_left, vidin_v_out_1_h3_left, vidin_v_out_1_h4_left, real_z_1_left, imag_z_1_left, real_p_1_left, imag_p_1_left, real_n_1_left, imag_n_1_left); + h_fltr h_fltr_2_left (tm3_clk_v0, v_nd_s2_left, vidin_v_out_2_f1_left, vidin_v_out_2_f2_left, vidin_v_out_2_f3_left, vidin_v_out_2_h1_left, vidin_v_out_2_h2_left, vidin_v_out_2_h3_left, vidin_v_out_2_h4_left, real_z_2_left, imag_z_2_left, real_p_2_left, imag_p_2_left, real_n_2_left, imag_n_2_left); + h_fltr h_fltr_4_left (tm3_clk_v0, v_nd_s4_left, vidin_v_out_4_f1_left, vidin_v_out_4_f2_left, vidin_v_out_4_f3_left, vidin_v_out_4_h1_left, vidin_v_out_4_h2_left, vidin_v_out_4_h3_left, vidin_v_out_4_h4_left, real_z_4_left, imag_z_4_left, real_p_4_left, imag_p_4_left, real_n_4_left, imag_n_4_left); + + v_fltr_496x7 v_fltr_1_right(tm3_clk_v0, v_nd_s1_right, v_d_reg_s1_right, vidin_v_out_1_f1_right, vidin_v_out_1_f2_right, vidin_v_out_1_f3_right, vidin_v_out_1_h1_right, vidin_v_out_1_h2_right, vidin_v_out_1_h3_right, vidin_v_out_1_h4_right); + v_fltr_316x7 v_fltr_2_right(tm3_clk_v0, v_nd_s2_right, v_d_reg_s2_right, vidin_v_out_2_f1_right, vidin_v_out_2_f2_right, vidin_v_out_2_f3_right, vidin_v_out_2_h1_right, vidin_v_out_2_h2_right, vidin_v_out_2_h3_right, vidin_v_out_2_h4_right); + v_fltr_226x7 v_fltr_4_right(tm3_clk_v0, v_nd_s4_right, v_d_reg_s4_right, vidin_v_out_4_f1_right, vidin_v_out_4_f2_right, vidin_v_out_4_f3_right, vidin_v_out_4_h1_right, vidin_v_out_4_h2_right, vidin_v_out_4_h3_right, vidin_v_out_4_h4_right); + h_fltr h_fltr_1_right (tm3_clk_v0, v_nd_s1_right, vidin_v_out_1_f1_right, vidin_v_out_1_f2_right, vidin_v_out_1_f3_right, vidin_v_out_1_h1_right, vidin_v_out_1_h2_right, vidin_v_out_1_h3_right, vidin_v_out_1_h4_right, real_z_1_right, imag_z_1_right, real_p_1_right, imag_p_1_right, real_n_1_right, imag_n_1_right); + h_fltr h_fltr_2_right (tm3_clk_v0, v_nd_s2_right, vidin_v_out_2_f1_right, vidin_v_out_2_f2_right, vidin_v_out_2_f3_right, vidin_v_out_2_h1_right, vidin_v_out_2_h2_right, vidin_v_out_2_h3_right, vidin_v_out_2_h4_right, real_z_2_right, imag_z_2_right, real_p_2_right, imag_p_2_right, real_n_2_right, imag_n_2_right); + h_fltr h_fltr_4_right (tm3_clk_v0, v_nd_s4_right, vidin_v_out_4_f1_right, vidin_v_out_4_f2_right, vidin_v_out_4_f3_right, vidin_v_out_4_h1_right, vidin_v_out_4_h2_right, vidin_v_out_4_h3_right, vidin_v_out_4_h4_right, real_z_4_right, imag_z_4_right, real_p_4_right, imag_p_4_right, real_n_4_right, imag_n_4_right); + + port_bus_2to1 port_bus_2to1_inst (tm3_clk_v0, vidin_addr_reg_2to3, svid_comp_switch_2to3, v_nd_s1_left, real_p_1_left, imag_p_1_left, real_n_1_left, imag_n_1_left, real_p_2_left, imag_p_2_left, real_n_2_left, imag_n_2_left, real_p_4_left, imag_p_4_left, real_n_4_left, imag_n_4_left, real_p_1_right, imag_p_1_right, real_n_1_right, imag_n_1_right, real_p_2_right, imag_p_2_right, real_n_2_right, imag_n_2_right, real_p_4_right, imag_p_4_right, real_n_4_right, imag_n_4_right, bus_word_3_2to1, bus_word_4_2to1, bus_word_5_2to1, bus_word_6_2to1, counter_out_2to1); + + always @(posedge tm3_clk_v0) + begin + if (reset == 1'b0) + begin + video_state <= 1'b0; + tm3_sram_adsp <= 1'b0 ; + horiz <= 10'b0000000000; + vert <= 10'b0000000000 ; + end + else + begin + video_state <= ~(video_state) ; + if (video_state == 1'b0) + begin + tm3_sram_data_xhdl0 <= 64'b0; + + if (horiz == 800) + begin + horiz <= 10'b0000000000 ; + if (vert == 525) + begin + vert <= 10'b0000000000 ; + end + else + begin + vert <= vert + 1 ; + end + end + else + begin + horiz <= horiz + 1 ; + end + tm3_sram_adsp <= 1'b1; + tm3_sram_we <= 8'b11111111; + + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_oe <= 2'b10 ; + end + 3'b001 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b010 : + begin + tm3_sram_oe <= 2'b10 ; + end + 3'b011 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b100 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b101 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b110 : + begin + tm3_sram_oe <= 2'b11 ; + end + 3'b111 : + begin + tm3_sram_oe <= 2'b11 ; + end + endcase + end + else + begin + tm3_sram_adsp <= 1'b0 ; + case (horiz[2:0]) + 3'b000 : + begin + tm3_sram_addr <= {5'b00000, vidin_addr_buf_sc_1_fifo} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b001 : + begin + vidout_buf_fifo_1_left <= tm3_sram_data_in ; + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + 3'b010 : + begin + tm3_sram_addr <= {5'b00001, vidin_addr_buf_sc_1_fifo} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b011 : + begin + vidout_buf_fifo_1_right <= tm3_sram_data_in ; + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + 3'b100 : + begin + tm3_sram_addr <= {5'b00000, vidin_addr_buf_sc_1_fifo} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + 3'b101 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + 3'b110 : + begin + if ((vert[8]) == 1'b0) + begin + tm3_sram_addr <= {5'b00000, vert[7:0], horiz[8:3]} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + else + begin + tm3_sram_addr <= {5'b00001, vert[7:0], horiz[8:3]} ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= 0; + end + end + 3'b111 : + begin + tm3_sram_addr <= vidin_addr_buf_sc_1 ; + tm3_sram_we <= 8'b11111111 ; + tm3_sram_oe <= 2'b11 ; + tm3_sram_data_xhdl0 <= vidin_data_buf_sc_1 ; + end + endcase + end + if (vidin_new_data_fifo == 1'b1) + begin + case (vidin_addr_reg_reg[2:0]) + 3'b000 : + begin + vidin_data_buf_2_sc_1[7:0] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[7:0] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[7:0] ; + end + 3'b001 : + begin + vidin_data_buf_2_sc_1[15:8] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[15:8] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[15:8] ; + end + 3'b010 : + begin + vidin_data_buf_2_sc_1[23:16] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[23:16] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[23:16] ; + end + 3'b011 : + begin + vidin_data_buf_2_sc_1[31:24] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[31:24] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[31:24] ; + end + 3'b100 : + begin + vidin_data_buf_2_sc_1[39:32] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[39:32] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[39:32] ; + end + 3'b101 : + begin + vidin_data_buf_2_sc_1[47:40] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[47:40] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[47:40] ; + end + 3'b110 : + begin + vidin_data_buf_2_sc_1[55:48] <= vidin_rgb_reg_tmp ; + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[55:48] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[55:48] ; + end + 3'b111 : + begin + vidin_data_buf_sc_1 <= {vidin_rgb_reg_tmp, vidin_data_buf_2_sc_1[55:0]} ; + vidout_buf_fifo_2_1_left <= vidout_buf_fifo_1_left ; + vidout_buf_fifo_2_1_right <= vidout_buf_fifo_1_right ; + + vidin_data_buf_fifo_sc_1_l <= vidout_buf_fifo_2_1_left[63:56] ; + vidin_data_buf_fifo_sc_1_r <= vidout_buf_fifo_2_1_right[63:56] ; + vidin_addr_buf_sc_1 <= {4'b0000, svid_comp_switch, vidin_addr_reg_reg[16:3]} ; + if (vidin_addr_reg_reg[8:3] == 43) + begin + vidin_addr_buf_sc_1_fifo <= {(vidin_addr_reg_reg[16:9] + 8'b00000001), 6'b000000} ; + end + else + begin + if (vidin_addr_reg_reg[8:3] == 44) + begin + vidin_addr_buf_sc_1_fifo <= {(vidin_addr_reg_reg[16:9] + 8'b00000001), 6'b000001} ; + end + else + begin + vidin_addr_buf_sc_1_fifo <= (vidin_addr_reg_reg[16:3]) + 2 ; + end + end + end + endcase + end + end +end + +always @(posedge tm3_clk_v0) + begin + vidin_rgb_reg_tmp <= vidin_rgb_reg ; + vidin_addr_reg_2to3 <= vidin_addr_reg ; + vidin_addr_reg_reg <= vidin_addr_reg ; + vidin_addr_reg_2to0 <= {vidin_addr_reg[1:0], vidin_addr_reg[10:9]} ; + vidin_new_data_fifo <= vidin_new_data ; + svid_comp_switch_2to3 <= svid_comp_switch ; + vidin_rgb_reg_fifo_left <= vidin_data_buf_fifo_sc_1_l ; + vidin_rgb_reg_fifo_right <= vidin_data_buf_fifo_sc_1_r ; + v_nd_s1_left <= v_nd_s1_left_2to0 ; + v_nd_s2_left <= v_nd_s2_left_2to0 ; + v_nd_s4_left <= v_nd_s4_left_2to0 ; + v_d_reg_s1_left <= v_d_reg_s1_left_2to0 ; + v_d_reg_s2_left <= v_d_reg_s2_left_2to0 ; + v_d_reg_s4_left <= v_d_reg_s4_left_2to0 ; + v_nd_s1_right <= v_nd_s1_right_2to0 ; + v_nd_s2_right <= v_nd_s2_right_2to0 ; + v_nd_s4_right <= v_nd_s4_right_2to0 ; + v_d_reg_s1_right <= v_d_reg_s1_right_2to0 ; + v_d_reg_s2_right <= v_d_reg_s2_right_2to0 ; + v_d_reg_s4_right <= v_d_reg_s4_right_2to0 ; + end +endmodule + + + +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.7 ,2001 +// By: Ahmad darabiha +module h_fltr (tm3_clk_v0, vidin_new_data, vidin_in_f1, vidin_in_f2, vidin_in_f3, vidin_in_h1, vidin_in_h2, vidin_in_h3, vidin_in_h4, real_z_reg, imag_z_reg, real_p_reg, imag_p_reg, real_n_reg, imag_n_reg); + + input tm3_clk_v0; + input vidin_new_data; + input[15:0] vidin_in_f1; + input[15:0] vidin_in_f2; + input[15:0] vidin_in_f3; + input[15:0] vidin_in_h1; + input[15:0] vidin_in_h2; + input[15:0] vidin_in_h3; + input[15:0] vidin_in_h4; + output[15:0] real_z_reg; + reg[15:0] real_z_reg; + output[15:0] imag_z_reg; + reg[15:0] imag_z_reg; + output[15:0] real_p_reg; + reg[15:0] real_p_reg; + output[15:0] imag_p_reg; + reg[15:0] imag_p_reg; + output[15:0] real_n_reg; + reg[15:0] real_n_reg; + output[15:0] imag_n_reg; + reg[15:0] imag_n_reg; + + wire[27:0] vidin_out_temp_f1; + reg[27:0] vidin_out_reg_f1; + wire my_fir_rdy_f1; + wire[27:0] vidin_out_temp_f2; + reg[27:0] vidin_out_reg_f2; + wire my_fir_rdy_f2; + wire[27:0] vidin_out_temp_f3; + reg[27:0] vidin_out_reg_f3; + wire my_fir_rdy_f3; + wire[27:0] vidin_out_temp_h1; + reg[27:0] vidin_out_reg_h1; + wire my_fir_rdy_h1; + wire[27:0] vidin_out_temp_h2; + reg[27:0] vidin_out_reg_h2; + wire my_fir_rdy_h2; + wire[27:0] vidin_out_temp_h3; + reg[27:0] vidin_out_reg_h3; + wire my_fir_rdy_h3; + wire[27:0] vidin_out_temp_h4; + reg[27:0] vidin_out_reg_h4; + wire my_fir_rdy_h4; + wire[28:0] sum_tmp_1; + wire[28:0] sum_tmp_2; + + wire[28:0] sum_tmp_3; + wire[28:0] sum_tmp_4; + wire[30:0] sum_tmp_5; + wire[15:0] real_p; + wire[15:0] imag_p; + wire[15:0] real_z; + wire[15:0] imag_z; + wire[15:0] real_n; + wire[15:0] imag_n; + wire[16:0] tmp; + + my_fir_f1 your_instance_name_f1 (tm3_clk_v0, vidin_new_data, my_fir_rdy_f1, vidin_in_f2, vidin_out_temp_f1); + my_fir_f2 your_instance_name_f2 (tm3_clk_v0, vidin_new_data, my_fir_rdy_f2, vidin_in_f1, vidin_out_temp_f2); + my_fir_f3 your_instance_name_f3 (tm3_clk_v0, vidin_new_data, my_fir_rdy_f3, vidin_in_f3, vidin_out_temp_f3); + my_fir_h1 your_instance_name_h1 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h1, vidin_in_h2, vidin_out_temp_h1); + my_fir_h2 your_instance_name_h2 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h2, vidin_in_h1, vidin_out_temp_h2); + my_fir_h3 your_instance_name_h3 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h3, vidin_in_h4, vidin_out_temp_h3); + my_fir_h4 your_instance_name_h4 (tm3_clk_v0, vidin_new_data, my_fir_rdy_h4, vidin_in_h3, vidin_out_temp_h4); + steer_fltr my_steer_fltr_inst (tm3_clk_v0, vidin_new_data, vidin_out_reg_f1, vidin_out_reg_f2, vidin_out_reg_f3, vidin_out_reg_h1, vidin_out_reg_h2, vidin_out_reg_h3, vidin_out_reg_h4, real_z, imag_z, real_p, imag_p, real_n, imag_n); + + always @(posedge tm3_clk_v0) + begin + if (my_fir_rdy_f1 == 1'b1) + begin + vidin_out_reg_f1 <= vidin_out_temp_f1 ; + end + if (my_fir_rdy_f2 == 1'b1) + begin + vidin_out_reg_f2 <= vidin_out_temp_f2 ; + end + if (my_fir_rdy_f3 == 1'b1) + begin + vidin_out_reg_f3 <= vidin_out_temp_f3 ; + end + if (my_fir_rdy_h1 == 1'b1) + begin + vidin_out_reg_h1 <= vidin_out_temp_h1 ; + end + if (my_fir_rdy_h2 == 1'b1) + begin + vidin_out_reg_h2 <= vidin_out_temp_h2 ; + end + if (my_fir_rdy_h3 == 1'b1) + begin + vidin_out_reg_h3 <= vidin_out_temp_h3 ; + + end + if (my_fir_rdy_h4 == 1'b1) + begin + vidin_out_reg_h4 <= vidin_out_temp_h4 ; + end + end + + always @(posedge tm3_clk_v0) + begin + real_z_reg <= real_z ; + imag_z_reg <= imag_z ; + real_p_reg <= real_p ; + imag_p_reg <= imag_p ; + real_n_reg <= real_n ; + imag_n_reg <= imag_n ; + end +endmodule +module steer_fltr (clk, new_data, f1, f2, f3, h1, h2, h3, h4, re_z, im_z, re_p, im_p, re_n, im_n); + + input clk; + input new_data; + input[27:0] f1; + input[27:0] f2; + input[27:0] f3; + input[27:0] h1; + input[27:0] h2; + input[27:0] h3; + input[27:0] h4; + output[15:0] re_z; + reg[15:0] re_z; + output[15:0] im_z; + reg[15:0] im_z; + output[15:0] re_p; + reg[15:0] re_p; + output[15:0] im_p; + reg[15:0] im_p; + output[15:0] re_n; + reg[15:0] re_n; + output[15:0] im_n; + reg[15:0] im_n; + + reg[27:0] f1_reg; + reg[27:0] f2_reg; + reg[27:0] f3_reg; + reg[27:0] h1_reg; + reg[27:0] h2_reg; + reg[27:0] h3_reg; + reg[27:0] h4_reg; + reg[28:0] re_z_tmp_1; + reg[28:0] im_z_tmp_1; + reg[28:0] re_p_tmp_1; + reg[28:0] re_p_tmp_2; + reg[28:0] re_p_tmp_3; + reg[28:0] im_p_tmp_1; + reg[28:0] im_p_tmp_2; + reg[28:0] im_p_tmp_3; + reg[28:0] im_p_tmp_4; + reg[30:0] re_z_tmp; + reg[30:0] im_z_tmp; + reg[30:0] re_p_tmp; + reg[30:0] im_p_tmp; + reg[30:0] re_n_tmp; + reg[30:0] im_n_tmp; + + always @(posedge clk) + begin + if (new_data == 1'b1) + begin + f1_reg <= f1 ; + f2_reg <= f2 ; + f3_reg <= f3 ; + h1_reg <= h1 ; + h2_reg <= h2 ; + h3_reg <= h3 ; + h4_reg <= h4 ; + end + end + + always @(posedge clk) + begin + re_z_tmp_1 <= {f1_reg[27], f1_reg} ; + im_z_tmp_1 <= {h1_reg[27], h1_reg} ; + re_p_tmp_1 <= {f1_reg[27], f1_reg[27], f1_reg[27:1]} ; + re_p_tmp_2 <= {f3_reg[27], f3_reg[27:0]} ; + re_p_tmp_3 <= {f2_reg[27], f2_reg[27], f2_reg[27:1]} ; + im_p_tmp_1 <= ({h1_reg[27], h1_reg[27], h1_reg[27], h1_reg[27:2]}) + ({h1_reg[27], h1_reg[27], h1_reg[27], h1_reg[27], h1_reg[27:3]}) ; + im_p_tmp_2 <= ({h4_reg[27], h4_reg}) + ({h4_reg[27], h4_reg[27], h4_reg[27], h4_reg[27], h4_reg[27], h4_reg[27:4]}) ; + im_p_tmp_3 <= ({h3_reg[27], h3_reg}) + ({h3_reg[27], h3_reg[27], h3_reg[27], h3_reg[27], h3_reg[27], h3_reg[27:4]}) ; + im_p_tmp_4 <= ({h2_reg[27], h2_reg[27], h2_reg[27], h2_reg[27:2]}) + ({h2_reg[27], h2_reg[27], h2_reg[27], h2_reg[27], h2_reg[27:3]}) ; + re_z_tmp <= {re_z_tmp_1[28], re_z_tmp_1[28], re_z_tmp_1} ; + im_z_tmp <= {im_z_tmp_1[28], im_z_tmp_1[28], im_z_tmp_1} ; + re_p_tmp <= ({re_p_tmp_1[28], re_p_tmp_1[28], re_p_tmp_1}) - ({re_p_tmp_2[28], re_p_tmp_2[28], re_p_tmp_2}) + ({re_p_tmp_3[28], re_p_tmp_3[28], re_p_tmp_3}) ; + im_p_tmp <= ({im_p_tmp_1[28], im_p_tmp_1[28], im_p_tmp_1}) - ({im_p_tmp_2[28], im_p_tmp_2[28], im_p_tmp_2}) + ({im_p_tmp_3[28], im_p_tmp_3[28], im_p_tmp_3}) - ({im_p_tmp_4[28], im_p_tmp_4[28], im_p_tmp_4}) ; + re_n_tmp <= ({re_p_tmp_1[28], re_p_tmp_1[28], re_p_tmp_1}) + ({re_p_tmp_2[28], re_p_tmp_2[28], re_p_tmp_2}) + ({re_p_tmp_3[28], re_p_tmp_3[28], re_p_tmp_3}) ; + im_n_tmp <= ({im_p_tmp_1[28], im_p_tmp_1[28], im_p_tmp_1}) + ({im_p_tmp_2[28], im_p_tmp_2[28], im_p_tmp_2}) + ({im_p_tmp_3[28], im_p_tmp_3[28], im_p_tmp_3}) + ({im_p_tmp_4[28], im_p_tmp_4[28], im_p_tmp_4}) ; + re_z <= re_z_tmp[30:15] ; + im_z <= im_z_tmp[30:15] ; + re_p <= re_p_tmp[30:15] ; + im_p <= im_p_tmp[30:15] ; + re_n <= re_n_tmp[30:15] ; + im_n <= im_n_tmp[30:15] ; + end +endmodule + + + + +// Discription: this block creates a long fifo +// of lengh of one line and then applies the +// the first and last byte of the fifo into a +// that finally creates horizontal edge detection +// filter. +// note: it uses fifo component to implement the fifo +// date: Oct.22 ,2001 +// By: Ahmad darabiha +module v_fltr_496x7 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out_f1, vidin_out_f2, vidin_out_f3, vidin_out_h1, vidin_out_h2, vidin_out_h3, vidin_out_h4); // PAJ var never used, vidin_out_or); + + parameter horiz_length = 9'b111110000; + parameter vert_length = 3'b111; // PAJ constant for all + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[15:0] vidin_out_f1; + wire[15:0] vidin_out_f1; + output[15:0] vidin_out_f2; + wire[15:0] vidin_out_f2; + output[15:0] vidin_out_f3; + wire[15:0] vidin_out_f3; + output[15:0] vidin_out_h1; + wire[15:0] vidin_out_h1; + output[15:0] vidin_out_h2; + wire[15:0] vidin_out_h2; + output[15:0] vidin_out_h3; + wire[15:0] vidin_out_h3; + output[15:0] vidin_out_h4; + wire[15:0] vidin_out_h4; +// output[7:0] vidin_out_or; +// reg[7:0] vidin_out_or; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + + fifo496 fifo0(tm3_clk_v0, vidin_new_data, buff_out0, buff_out1); + fifo496 fifo1(tm3_clk_v0, vidin_new_data, buff_out1, buff_out2); + fifo496 fifo2(tm3_clk_v0, vidin_new_data, buff_out2, buff_out3); + fifo496 fifo3(tm3_clk_v0, vidin_new_data, buff_out3, buff_out4); + fifo496 fifo4(tm3_clk_v0, vidin_new_data, buff_out4, buff_out5); + fifo496 fifo5(tm3_clk_v0, vidin_new_data, buff_out5, buff_out6); + fifo496 fifo6(tm3_clk_v0, vidin_new_data, buff_out6, buff_out7); + + fltr_compute_f1 inst_fltr_compute_f1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f1); + fltr_compute_f2 inst_fltr_compute_f2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f2); + fltr_compute_f3 inst_fltr_compute_f3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f3); + fltr_compute_h1 inst_fltr_compute_h1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h1); + fltr_compute_h2 inst_fltr_compute_h2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h2); + fltr_compute_h3 inst_fltr_compute_h3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h3); + fltr_compute_h4 inst_fltr_compute_h4 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h4); + + assign buff_out0 = vidin_in ; +/* + always @(posedge tm3_clk_v0) + begin + buff_out0 <= vidin_in ; + //vidin_out_or <= buff_out6; + end +*/ +endmodule +module v_fltr_316x7 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out_f1, vidin_out_f2, vidin_out_f3, vidin_out_h1, vidin_out_h2, vidin_out_h3, vidin_out_h4); // PAJ var never used, vidin_out_or); + + parameter horiz_length = 9'b100111100; + parameter vert_length = 3'b111; // PAJ constant for all + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[15:0] vidin_out_f1; + wire[15:0] vidin_out_f1; + output[15:0] vidin_out_f2; + wire[15:0] vidin_out_f2; + output[15:0] vidin_out_f3; + wire[15:0] vidin_out_f3; + output[15:0] vidin_out_h1; + wire[15:0] vidin_out_h1; + output[15:0] vidin_out_h2; + wire[15:0] vidin_out_h2; + output[15:0] vidin_out_h3; + wire[15:0] vidin_out_h3; + output[15:0] vidin_out_h4; + wire[15:0] vidin_out_h4; +// output[7:0] vidin_out_or; +// reg[7:0] vidin_out_or; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + + fifo316 fifo0(tm3_clk_v0, vidin_new_data, buff_out0, buff_out1); + fifo316 fifo1(tm3_clk_v0, vidin_new_data, buff_out1, buff_out2); + fifo316 fifo2(tm3_clk_v0, vidin_new_data, buff_out2, buff_out3); + fifo316 fifo3(tm3_clk_v0, vidin_new_data, buff_out3, buff_out4); + fifo316 fifo4(tm3_clk_v0, vidin_new_data, buff_out4, buff_out5); + fifo316 fifo5(tm3_clk_v0, vidin_new_data, buff_out5, buff_out6); + fifo316 fifo6(tm3_clk_v0, vidin_new_data, buff_out6, buff_out7); + + fltr_compute_f1 inst_fltr_compute_f1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f1); + fltr_compute_f2 inst_fltr_compute_f2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f2); + fltr_compute_f3 inst_fltr_compute_f3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f3); + fltr_compute_h1 inst_fltr_compute_h1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h1); + fltr_compute_h2 inst_fltr_compute_h2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h2); + fltr_compute_h3 inst_fltr_compute_h3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h3); + fltr_compute_h4 inst_fltr_compute_h4 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h4); + + assign buff_out0 = vidin_in ; +/* + always @(posedge tm3_clk_v0) + begin + buff_out0 <= vidin_in ; + //vidin_out_or <= buff_out6; + end +*/ +endmodule +module v_fltr_226x7 (tm3_clk_v0, vidin_new_data, vidin_in, vidin_out_f1, vidin_out_f2, vidin_out_f3, vidin_out_h1, vidin_out_h2, vidin_out_h3, vidin_out_h4); // PAJ var never used, vidin_out_or); + + parameter horiz_length = 8'b11100010; + parameter vert_length = 3'b111; // PAJ constant for all + + input tm3_clk_v0; + input vidin_new_data; + input[7:0] vidin_in; + output[15:0] vidin_out_f1; + wire[15:0] vidin_out_f1; + output[15:0] vidin_out_f2; + wire[15:0] vidin_out_f2; + output[15:0] vidin_out_f3; + wire[15:0] vidin_out_f3; + output[15:0] vidin_out_h1; + wire[15:0] vidin_out_h1; + output[15:0] vidin_out_h2; + wire[15:0] vidin_out_h2; + output[15:0] vidin_out_h3; + wire[15:0] vidin_out_h3; + output[15:0] vidin_out_h4; + wire[15:0] vidin_out_h4; +// output[7:0] vidin_out_or; +// reg[7:0] vidin_out_or; + + wire[7:0] buff_out0; + wire[7:0] buff_out1; + wire[7:0] buff_out2; + wire[7:0] buff_out3; + wire[7:0] buff_out4; + wire[7:0] buff_out5; + wire[7:0] buff_out6; + wire[7:0] buff_out7; + + fifo226 fifo0(tm3_clk_v0, vidin_new_data, buff_out0, buff_out1); + fifo226 fifo1(tm3_clk_v0, vidin_new_data, buff_out1, buff_out2); + fifo226 fifo2(tm3_clk_v0, vidin_new_data, buff_out2, buff_out3); + fifo226 fifo3(tm3_clk_v0, vidin_new_data, buff_out3, buff_out4); + fifo226 fifo4(tm3_clk_v0, vidin_new_data, buff_out4, buff_out5); + fifo226 fifo5(tm3_clk_v0, vidin_new_data, buff_out5, buff_out6); + fifo226 fifo6(tm3_clk_v0, vidin_new_data, buff_out6, buff_out7); + + fltr_compute_f1 inst_fltr_compute_f1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f1); + fltr_compute_f2 inst_fltr_compute_f2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f2); + fltr_compute_f3 inst_fltr_compute_f3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_f3); + fltr_compute_h1 inst_fltr_compute_h1 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h1); + fltr_compute_h2 inst_fltr_compute_h2 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h2); + fltr_compute_h3 inst_fltr_compute_h3 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h3); + fltr_compute_h4 inst_fltr_compute_h4 (tm3_clk_v0, {buff_out1, buff_out2, buff_out3, buff_out4, buff_out5, buff_out6, buff_out7}, vidin_out_h4); + + assign buff_out0 = vidin_in ; +/* + always @(posedge tm3_clk_v0) + begin + buff_out0 <= vidin_in ; + //vidin_out_or <= buff_out6; + end +*/ +endmodule +module fltr_compute_f1 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b11101; + q2 <= din[47:40] * 7'b1100101; + q3 <= din[39:32] * 5'b10001; + q4 <= din[31:24] * 9'b100010101; + q5 <= din[23:16] * 5'b10001; + q6 <= din[15:8] * 7'b1100101; + q7 <= din[7:0] * 5'b11101; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + endmodule +module fltr_compute_f2 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 3'b100; + q2 <= din[47:40] * 6'b101010; + q3 <= din[39:32] * 8'b10100011; + q4 <= din[31:24] * 8'b11111111; + q5 <= din[23:16] * 8'b10100011; + q6 <= din[15:8] * 6'b101010; + q7 <= din[7:0] * 3'b100; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + endmodule + + + + + + + + + +module fltr_compute_f3 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b10100; + q2 <= din[47:40] * 8'b10110011; + q3 <= din[39:32] * 9'b101101100; + q4 <= din[31:24] * 16'b0000000000000000; + q5 <= din[23:16] * 9'b101101100; + q6 <= din[15:8] * 8'b10110011; + q7 <= din[7:0] * 5'b10100; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + + endmodule +module fltr_compute_h1 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b10001; + q2 <= din[47:40] * 5'b11001; + q3 <= din[39:32] * 8'b11000001; + q4 <= din[31:24] * 16'b0000000000000000; + q5 <= din[23:16] * 8'b11000001; + q6 <= din[15:8] * 5'b11001; + q7 <= din[7:0] * 5'b10001; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end + endmodule + + +module fltr_compute_h2 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 3'b100; + q2 <= din[47:40] * 6'b101010; + q3 <= din[39:32] * 8'b10100011; + q4 <= din[31:24] * 8'b11111111; + q5 <= din[23:16] * 8'b10100011; + q6 <= din[15:8] * 6'b101010; + q7 <= din[7:0] * 3'b100; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end +endmodule + + + + + + + +module fltr_compute_h3 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 5'b10111; + q2 <= din[47:40] * 7'b1001000; + q3 <= din[39:32] * 8'b10010011; + q4 <= din[31:24] * 16'b0000000000000000; + q5 <= din[23:16] * 8'b10010011; + q6 <= din[15:8] * 7'b1001000; + q7 <= din[7:0] * 5'b10111; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end +endmodule + + + + +module fltr_compute_h4 (clk, din, dout); + + input clk; + input[55:0] din; + output[15:0] dout; + reg[15:0] dout; + + reg[16:0] q1; + reg[16:0] q2; + reg[16:0] q3; + reg[16:0] q4; + reg[16:0] q5; + reg[16:0] q6; + reg[16:0] q7; + reg[19:0] d_out_tmp; + + always @(posedge clk) + begin + // PAJ - grabbed these from the mult_const declarations + q1 <= din[55:48] * 4'b1110; + q2 <= din[47:40] * 6'b101011; + q3 <= din[39:32] * 7'b1010000; + q4 <= din[31:24] * 9'b101000100; + q5 <= din[23:16] * 7'b1010000; + q6 <= din[15:8] * 6'b101011; + q7 <= din[7:0] * 4'b1110; + + d_out_tmp <= ({q1[16], q1[16], q1[16], q1}) + ({q2[16], q2[16], q2[16], q2}) + ({q3[16], q3[16], q3[16], q3}) + ({q4[16], q4[16], q4[16], q4}) + ({q5[16], q5[16], q5[16], q5}) + ({q6[16], q6[16], q6[16], q6}) + ({q7[16], q7[16], q7[16], q7}); + dout <= d_out_tmp[18:3] ; + end +endmodule + + + + + + +// Discription: this block creates a long fifo + + // of lengh of the specified length as an input + // parameter and with a specified width + + // date: Oct.7 ,2001 + // By: Ahmad darabiha + + `define WIDTH_4B 4'b1000 + + +module fifo496 (clk, wen, din, dout); + +// parameter WIDTH = 4'b1000; + + input clk; + input wen; + input[`WIDTH_4B - 1:0] din; + + + + + + + + + + + + + + + + + + output[`WIDTH_4B - 1:0] dout; + reg[`WIDTH_4B - 1:0] dout; + + reg[`WIDTH_4B-1:0]buff1; + reg[`WIDTH_4B-1:0]buff2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + buff1 <= din; + buff2 <= buff1; + dout <= buff2; + end + end +endmodule + +module fifo316 (clk, wen, din, dout); + +// parameter `WIDTH = 4'b1000; + + input clk; + input wen; + input[`WIDTH_4B - 1:0] din; + output[`WIDTH_4B - 1:0] dout; + reg[`WIDTH_4B - 1:0] dout; + + reg[`WIDTH_4B-1:0]buff1; + reg[`WIDTH_4B-1:0]buff2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + buff1 <= din; + buff2 <= buff1; + dout <= buff2; + end + end +endmodule + +module fifo226 (clk, wen, din, dout); + +// parameter `WIDTH = 4'b1000; + + input clk; + input wen; + input[`WIDTH_4B - 1:0] din; + output[`WIDTH_4B - 1:0] dout; + reg[`WIDTH_4B - 1:0] dout; + + reg[`WIDTH_4B-1:0]buff1; + reg[`WIDTH_4B-1:0]buff2; + + always @(posedge clk) + begin + if (wen == 1'b1) + begin + buff1 <= din; + buff2 <= buff1; + dout <= buff2; + end + end +endmodule + +module port_bus_2to1 (clk, vidin_addr_reg, svid_comp_switch, vidin_new_data_scld_1_2to3_left, + vidin_data_reg_scld_1_2to3_left_rp, vidin_data_reg_scld_1_2to3_left_ip, + vidin_data_reg_scld_1_2to3_left_rn, vidin_data_reg_scld_1_2to3_left_in, + vidin_data_reg_scld_2_2to3_left_rp, vidin_data_reg_scld_2_2to3_left_ip, + vidin_data_reg_scld_2_2to3_left_rn, vidin_data_reg_scld_2_2to3_left_in, + vidin_data_reg_scld_4_2to3_left_rp, vidin_data_reg_scld_4_2to3_left_ip, + vidin_data_reg_scld_4_2to3_left_rn, vidin_data_reg_scld_4_2to3_left_in, + vidin_data_reg_scld_1_2to3_right_rp, vidin_data_reg_scld_1_2to3_right_ip, + vidin_data_reg_scld_1_2to3_right_rn, vidin_data_reg_scld_1_2to3_right_in, + vidin_data_reg_scld_2_2to3_right_rp, vidin_data_reg_scld_2_2to3_right_ip, + vidin_data_reg_scld_2_2to3_right_rn, vidin_data_reg_scld_2_2to3_right_in, + vidin_data_reg_scld_4_2to3_right_rp, vidin_data_reg_scld_4_2to3_right_ip, + vidin_data_reg_scld_4_2to3_right_rn, vidin_data_reg_scld_4_2to3_right_in, + bus_word_3, bus_word_4, bus_word_5, bus_word_6, counter_out); + input clk; + input[18:0] vidin_addr_reg; + input svid_comp_switch; + input vidin_new_data_scld_1_2to3_left; + input[15:0] vidin_data_reg_scld_1_2to3_left_rp; + input[15:0] vidin_data_reg_scld_1_2to3_left_ip; + input[15:0] vidin_data_reg_scld_1_2to3_left_rn; + input[15:0] vidin_data_reg_scld_1_2to3_left_in; + input[15:0] vidin_data_reg_scld_2_2to3_left_rp; + input[15:0] vidin_data_reg_scld_2_2to3_left_ip; + input[15:0] vidin_data_reg_scld_2_2to3_left_rn; + input[15:0] vidin_data_reg_scld_2_2to3_left_in; + input[15:0] vidin_data_reg_scld_4_2to3_left_rp; + input[15:0] vidin_data_reg_scld_4_2to3_left_ip; + input[15:0] vidin_data_reg_scld_4_2to3_left_rn; + input[15:0] vidin_data_reg_scld_4_2to3_left_in; + input[15:0] vidin_data_reg_scld_1_2to3_right_rp; + input[15:0] vidin_data_reg_scld_1_2to3_right_ip; + input[15:0] vidin_data_reg_scld_1_2to3_right_rn; + input[15:0] vidin_data_reg_scld_1_2to3_right_in; + input[15:0] vidin_data_reg_scld_2_2to3_right_rp; + input[15:0] vidin_data_reg_scld_2_2to3_right_ip; + input[15:0] vidin_data_reg_scld_2_2to3_right_rn; + input[15:0] vidin_data_reg_scld_2_2to3_right_in; + input[15:0] vidin_data_reg_scld_4_2to3_right_rp; + input[15:0] vidin_data_reg_scld_4_2to3_right_ip; + input[15:0] vidin_data_reg_scld_4_2to3_right_rn; + input[15:0] vidin_data_reg_scld_4_2to3_right_in; + output[15:0] bus_word_3; + reg[15:0] bus_word_3; + output[15:0] bus_word_4; + reg[15:0] bus_word_4; + output[15:0] bus_word_5; + reg[15:0] bus_word_5; + output[15:0] bus_word_6; + reg[15:0] bus_word_6; + output[2:0] counter_out; + reg[2:0] counter_out; + + reg[15:0] bus_word_3_tmp; + reg[15:0] bus_word_4_tmp; + reg[15:0] bus_word_5_tmp; + reg[15:0] bus_word_6_tmp; + reg[18:0] vidin_addr_reg_tmp; + reg svid_comp_switch_tmp; + wire vidin_new_data_scld_1_2to3_left_tmp; + wire vidin_new_data_scld_2_2to3_left_tmp; + wire vidin_new_data_scld_4_2to3_left_tmp; + wire vidin_new_data_scld_1_2to3_right_tmp; + wire vidin_new_data_scld_2_2to3_right_tmp; + wire vidin_new_data_scld_4_2to3_right_tmp; + reg[3:0] counter; + reg[2:0] counter_out_tmp; + + reg[15:0] vidin_data_reg_scld_1_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rp_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_ip_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_rn_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_left_in_tmp; + reg[15:0] vidin_data_reg_scld_1_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_2_2to3_right_in_tmp; + reg[15:0] vidin_data_reg_scld_4_2to3_right_in_tmp; + + always @(posedge clk) + begin + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + counter <= 4'b0001 ; + end + else + begin + case (counter) + 4'b0000 : + begin + counter <= 4'b1000 ; + end + 4'b0001 : + begin + counter <= 4'b0010 ; + end + 4'b0010 : + begin + counter <= 4'b0011 ; + end + 4'b0011 : + begin + counter <= 4'b0100 ; + end + 4'b0100 : + begin + counter <= 4'b0101 ; + end + 4'b0101 : + begin + counter <= 4'b0110 ; + end + 4'b0110 : + begin + counter <= 4'b0111 ; + end + 4'b0111 : + begin + counter <= 4'b1000 ; + end + 4'b1000 : + begin + counter <= 4'b1000 ; + end + default : + begin + counter <= 4'b1000 ; + end + endcase + end + end + + always @(posedge clk) + begin + case (counter[2:0]) + 3'b000 : + begin + counter_out_tmp <= 3'b000 ; + bus_word_3_tmp <= 16'b0000000000000000 ; + bus_word_4_tmp <= 16'b0000000000000000 ; + bus_word_5_tmp <= 16'b0000000000000000 ; + bus_word_6_tmp <= 16'b0000000000000000 ; + end + 3'b001 : + begin + counter_out_tmp <= 3'b001 ; + bus_word_3_tmp <= vidin_addr_reg_tmp[15:0] ; + bus_word_4_tmp <= {vidin_addr_reg_tmp[18:16], svid_comp_switch_tmp, 12'b000000000000} ; + bus_word_5_tmp <= 16'b0000000000000000 ; + bus_word_6_tmp <= 16'b0000000000000000 ; + end + 3'b010 : + begin + counter_out_tmp <= 3'b010 ; + bus_word_3_tmp <= vidin_data_reg_scld_1_2to3_left_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_1_2to3_left_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_1_2to3_left_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_1_2to3_left_in_tmp ; + end + 3'b011 : + begin + counter_out_tmp <= 3'b011 ; + bus_word_3_tmp <= vidin_data_reg_scld_1_2to3_right_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_1_2to3_right_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_1_2to3_right_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_1_2to3_right_in_tmp ; + end + 3'b100 : + begin + counter_out_tmp <= 3'b100 ; + bus_word_3_tmp <= vidin_data_reg_scld_2_2to3_left_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_2_2to3_left_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_2_2to3_left_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_2_2to3_left_in_tmp ; + end + 3'b101 : + begin + counter_out_tmp <= 3'b101 ; + bus_word_3_tmp <= vidin_data_reg_scld_2_2to3_right_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_2_2to3_right_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_2_2to3_right_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_2_2to3_right_in_tmp ; + end + + 3'b110 : + begin + counter_out_tmp <= 3'b110 ; + bus_word_3_tmp <= vidin_data_reg_scld_4_2to3_left_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_4_2to3_left_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_4_2to3_left_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_4_2to3_left_in_tmp ; + end + 3'b111 : + begin + counter_out_tmp <= 3'b111 ; + bus_word_3_tmp <= vidin_data_reg_scld_4_2to3_right_rp_tmp ; + bus_word_4_tmp <= vidin_data_reg_scld_4_2to3_right_ip_tmp ; + bus_word_5_tmp <= vidin_data_reg_scld_4_2to3_right_rn_tmp ; + bus_word_6_tmp <= vidin_data_reg_scld_4_2to3_right_in_tmp ; + end + endcase + end + + always @(posedge clk) + begin + counter_out <= counter_out_tmp ; + bus_word_3 <= bus_word_3_tmp ; + bus_word_4 <= bus_word_4_tmp ; + bus_word_5 <= bus_word_5_tmp ; + bus_word_6 <= bus_word_6_tmp ; + if (vidin_new_data_scld_1_2to3_left == 1'b1) + begin + vidin_addr_reg_tmp <= vidin_addr_reg ; + svid_comp_switch_tmp <= svid_comp_switch ; + vidin_data_reg_scld_1_2to3_left_rp_tmp <= vidin_data_reg_scld_1_2to3_left_rp ; + vidin_data_reg_scld_2_2to3_left_rp_tmp <= vidin_data_reg_scld_2_2to3_left_rp ; + vidin_data_reg_scld_4_2to3_left_rp_tmp <= vidin_data_reg_scld_4_2to3_left_rp ; + vidin_data_reg_scld_1_2to3_right_rp_tmp <= vidin_data_reg_scld_1_2to3_right_rp ; + vidin_data_reg_scld_2_2to3_right_rp_tmp <= vidin_data_reg_scld_2_2to3_right_rp ; + vidin_data_reg_scld_4_2to3_right_rp_tmp <= vidin_data_reg_scld_4_2to3_right_rp ; + vidin_data_reg_scld_1_2to3_left_ip_tmp <= vidin_data_reg_scld_1_2to3_left_ip ; + vidin_data_reg_scld_2_2to3_left_ip_tmp <= vidin_data_reg_scld_2_2to3_left_ip ; + vidin_data_reg_scld_4_2to3_left_ip_tmp <= vidin_data_reg_scld_4_2to3_left_ip ; + vidin_data_reg_scld_1_2to3_right_ip_tmp <= vidin_data_reg_scld_1_2to3_right_ip ; + vidin_data_reg_scld_2_2to3_right_ip_tmp <= vidin_data_reg_scld_2_2to3_right_ip ; + vidin_data_reg_scld_4_2to3_right_ip_tmp <= vidin_data_reg_scld_4_2to3_right_ip ; + vidin_data_reg_scld_1_2to3_left_rn_tmp <= vidin_data_reg_scld_1_2to3_left_rn ; + vidin_data_reg_scld_2_2to3_left_rn_tmp <= vidin_data_reg_scld_2_2to3_left_rn ; + vidin_data_reg_scld_4_2to3_left_rn_tmp <= vidin_data_reg_scld_4_2to3_left_rn ; + vidin_data_reg_scld_1_2to3_right_rn_tmp <= vidin_data_reg_scld_1_2to3_right_rn ; + vidin_data_reg_scld_2_2to3_right_rn_tmp <= vidin_data_reg_scld_2_2to3_right_rn ; + vidin_data_reg_scld_4_2to3_right_rn_tmp <= vidin_data_reg_scld_4_2to3_right_rn ; + vidin_data_reg_scld_1_2to3_left_in_tmp <= vidin_data_reg_scld_1_2to3_left_in ; + vidin_data_reg_scld_2_2to3_left_in_tmp <= vidin_data_reg_scld_2_2to3_left_in ; + vidin_data_reg_scld_4_2to3_left_in_tmp <= vidin_data_reg_scld_4_2to3_left_in ; + vidin_data_reg_scld_1_2to3_right_in_tmp <= vidin_data_reg_scld_1_2to3_right_in ; + vidin_data_reg_scld_2_2to3_right_in_tmp <= vidin_data_reg_scld_2_2to3_right_in ; + vidin_data_reg_scld_4_2to3_right_in_tmp <= vidin_data_reg_scld_4_2to3_right_in ; + end + end +endmodule + + +`define COEF0_b 29 + `define COEF1_b 101 +// `define COEF2_b -15 +// `define COEF3_b -235 +// `define COEF4_b -15 + `define COEF2_b 15 + `define COEF3_b 235 + `define COEF4_b 15 + `define COEF5_b 101 + `define COEF6_b 29 + + `define WIDTH_5B 5'b10000 + +module my_fir_f1 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=29,101,-15,-235,-15,101,29; + + //parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_b) + + (n_delay_reg1 * `COEF1_b) + + (n_delay_reg2 * `COEF2_b) + + (n_delay_reg3 * `COEF3_b) + + (n_delay_reg4 * `COEF4_b) + + (n_delay_reg5 * `COEF5_b) + + (n_delay_reg6 * `COEF6_b); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + `define COEF0_c 4 + `define COEF1_c 42 + `define COEF2_c 163 + `define COEF3_c 255 + `define COEF4_c 163 + `define COEF5_c 42 + `define COEF6_c 4 + +module my_fir_f2 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=4,42,163,255,163,42,4; + + +// parameter WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_c) + + (n_delay_reg1 * `COEF1_c) + + (n_delay_reg2 * `COEF2_c) + + (n_delay_reg3 * `COEF3_c) + + (n_delay_reg4 * `COEF4_c) + + (n_delay_reg5 * `COEF5_c) + + (n_delay_reg6 * `COEF6_c); + + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + +// `define COEF0_d -12 +// `define COEF1_d -77 +// `define COEF2_d -148 + `define COEF0_d 12 + `define COEF1_d 77 + `define COEF2_d 148 + `define COEF3_d 0 + `define COEF4_d 148 + `define COEF5_d 77 + `define COEF6_d 12 + +module my_fir_f3 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-12,-77,-148,0,148,77,12; + +// parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_d) + + (n_delay_reg1 * `COEF1_d) + + (n_delay_reg2 * `COEF2_d) + + (n_delay_reg4 * `COEF4_d) + + (n_delay_reg5 * `COEF5_d) + + (n_delay_reg6 * `COEF6_d); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + + `define COEF0_1 15 +//`define COEF0_1 -15 + `define COEF1_1 25 + `define COEF2_1 193 + `define COEF3_1 0 +// `define COEF4_1 -193 +// `define COEF5_1 -25 + `define COEF4_1 193 + `define COEF5_1 25 + `define COEF6_1 15 + +module my_fir_h1 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-15,25,193,0,-193,-25,15; + + +// parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_1) + + (n_delay_reg1 * `COEF1_1) + + (n_delay_reg2 * `COEF2_1) + + (n_delay_reg4 * `COEF4_1) + + (n_delay_reg5 * `COEF5_1) + + (n_delay_reg6 * `COEF6_1); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + + `define COEF0_2 4 + `define COEF1_2 42 + `define COEF2_2 163 + `define COEF3_2 255 + `define COEF4_2 163 + `define COEF5_2 42 + `define COEF6_2 4 + +module my_fir_h2 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=4,42,163,255,163,42,4; + +// parameter `WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_2) + + (n_delay_reg1 * `COEF1_2) + + (n_delay_reg2 * `COEF2_2) + + (n_delay_reg3 * `COEF3_2) + + (n_delay_reg4 * `COEF4_2) + + (n_delay_reg5 * `COEF5_2) + + (n_delay_reg6 * `COEF6_2); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + +// `define COEF0_3 -9 +// `define COEF1_3 -56 +// `define COEF2_3 -109 + `define COEF0_3 9 + `define COEF1_3 56 + `define COEF2_3 109 + `define COEF3_3 0 + `define COEF4_3 109 + `define COEF5_3 56 + `define COEF6_3 9 + + +module my_fir_h3 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-9,-56,-109,0,109,56,9; +// parameter WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_3) + + (n_delay_reg1 * `COEF1_3) + + (n_delay_reg2 * `COEF2_3) + + (n_delay_reg4 * `COEF4_3) + + (n_delay_reg5 * `COEF5_3) + + (n_delay_reg6 * `COEF6_3); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + +// `define COEF0_4 -9 +// `define COEF1_4 -56 +// `define COEF2_4 -109 + `define COEF0_4 9 + `define COEF1_4 56 + `define COEF2_4 109 + `define COEF3_4 0 + `define COEF4_4 109 + `define COEF5_4 56 + `define COEF6_4 9 + + +module my_fir_h4 (clk, new_data_rdy, output_data_ready, din, dout); + +//coefdata=-9,-56,-109,0,109,56,9; + // parameter WIDTH = 5'b10000; + + input clk; + input[`WIDTH_5B - 1:0] din; + output[28 - 1:0] dout; + reg[28 - 1:0] dout; + input new_data_rdy; + output output_data_ready; + reg output_data_ready; + + reg[`WIDTH_5B - 1:0]n_delay_reg1; + reg[`WIDTH_5B - 1:0]n_delay_reg2; + reg[`WIDTH_5B - 1:0]n_delay_reg3; + reg[`WIDTH_5B - 1:0]n_delay_reg4; + reg[`WIDTH_5B - 1:0]n_delay_reg5; + reg[`WIDTH_5B - 1:0]n_delay_reg6; + + always @(posedge clk) + begin + if (new_data_rdy == 1'b1) + begin + n_delay_reg1 <= din; + n_delay_reg2 <= n_delay_reg1; + n_delay_reg3 <= n_delay_reg2; + n_delay_reg4 <= n_delay_reg3; + n_delay_reg5 <= n_delay_reg4; + n_delay_reg6 <= n_delay_reg5; + + output_data_ready <= 1'b1; + dout <= (din * `COEF0_4) + + (n_delay_reg1 * `COEF1_4) + + (n_delay_reg2 * `COEF2_4) + + (n_delay_reg4 * `COEF4_4) + + (n_delay_reg5 * `COEF5_4) + + (n_delay_reg6 * `COEF6_4); + end + else + begin + output_data_ready <= 1'b0; + end + end +endmodule + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v b/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v new file mode 100755 index 000000000..1b3e343a2 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v @@ -0,0 +1,1054 @@ +// originally created by Marcus van Ierssel +// modified by Ahmad Darabiha, Feb. 2002 +// this circuit receives the rgbvideo signal +// from video input and send it to chip #2 +// for buffring and processing. +module sv_chip3_hierarchy_no_mem (tm3_clk_v0, tm3_clk_v2, tm3_vidin_llc, tm3_vidin_vs, tm3_vidin_href, tm3_vidin_cref, tm3_vidin_rts0, tm3_vidin_vpo, tm3_vidin_sda, tm3_vidin_scl, vidin_new_data, vidin_rgb_reg, vidin_addr_reg); + + input tm3_clk_v0; + input tm3_clk_v2; + input tm3_vidin_llc; + input tm3_vidin_vs; + input tm3_vidin_href; + input tm3_vidin_cref; + input tm3_vidin_rts0; + input[15:0] tm3_vidin_vpo; + output tm3_vidin_sda; + wire tm3_vidin_sda; + reg tm3_vidin_sda_xhdl0; + output tm3_vidin_scl; + reg tm3_vidin_scl; + output vidin_new_data; + reg vidin_new_data; + output[7:0] vidin_rgb_reg; + reg[7:0] vidin_rgb_reg; + output[18:0] vidin_addr_reg; + reg[18:0] vidin_addr_reg; + + reg temp_reg1; + reg temp_reg2; + reg[9:0] horiz; + reg[7:0] vert; + reg creg1; + reg creg2; + reg creg3; + reg[18:0] vidin_addr_reg1; + reg[23:0] vidin_rgb_reg1; + reg[23:0] vidin_rgb_reg2; + parameter[4:0] reg_prog1 = 5'b00001; + parameter[4:0] reg_prog2 = 5'b00010; + parameter[4:0] reg_prog3 = 5'b00011; + parameter[4:0] reg_prog4 = 5'b00100; + parameter[4:0] reg_prog5 = 5'b00101; + parameter[4:0] reg_prog6 = 5'b00110; + parameter[4:0] reg_prog7 = 5'b00111; + parameter[4:0] reg_prog8 = 5'b01000; + parameter[4:0] reg_prog9 = 5'b01001; + parameter[4:0] reg_prog10 = 5'b01010; + parameter[4:0] reg_prog11 = 5'b01011; + parameter[4:0] reg_prog12 = 5'b01100; + parameter[4:0] reg_prog13 = 5'b01101; + parameter[4:0] reg_prog14 = 5'b01110; + parameter[4:0] reg_prog15 = 5'b01111; + parameter[4:0] reg_prog16 = 5'b10000; + parameter[4:0] reg_prog17 = 5'b10001; + parameter[4:0] reg_prog18 = 5'b10010; + parameter[4:0] reg_prog19 = 5'b10011; + parameter[4:0] reg_prog20 = 5'b10100; + parameter[4:0] reg_prog21 = 5'b10101; + parameter[4:0] reg_prog22 = 5'b10110; + parameter[4:0] reg_prog23 = 5'b10111; + parameter[4:0] reg_prog24 = 5'b11000; + parameter[4:0] reg_prog25 = 5'b11001; + parameter[4:0] reg_prog26 = 5'b11010; + parameter[4:0] reg_prog_end = 5'b11011; + reg rst; + reg rst_done; + reg[7:0] iicaddr; + reg[7:0] iicdata; +// wire vidin_llc; +// wire vidin_llc_int; + reg[6:0] iic_state; + reg iic_stop; + reg iic_start; + reg[4:0] reg_prog_state; + reg[4:0] reg_prog_nextstate; + + assign tm3_vidin_sda = tm3_vidin_sda_xhdl0; + + // ibuf ibuf_inst (tm3_vidin_llc, vidin_llc_int); +// bufg bufg_inst (vidin_llc_int, vidin_llc); + + // PAJ double clock is trouble...always @(vidin_llc) + always @(posedge tm3_clk_v0) + begin + if (tm3_vidin_href == 1'b0) + begin + horiz <= 10'b0000000000 ; + end + else + begin + if (tm3_vidin_cref == 1'b0) + begin + horiz <= horiz + 1 ; + end + end + if (tm3_vidin_vs == 1'b1) + begin + vert <= 8'b00000000 ; + end + else + begin + if ((tm3_vidin_href == 1'b0) & (horiz != 10'b0000000000)) + begin + vert <= vert + 1 ; + end + end + if (tm3_vidin_cref == 1'b1) + begin + vidin_rgb_reg1[23:19] <= tm3_vidin_vpo[15:11] ; + vidin_rgb_reg1[15:13] <= tm3_vidin_vpo[10:8] ; + vidin_rgb_reg1[18:16] <= tm3_vidin_vpo[7:5] ; + vidin_rgb_reg1[9:8] <= tm3_vidin_vpo[4:3] ; + vidin_rgb_reg1[2:0] <= tm3_vidin_vpo[2:0] ; + vidin_rgb_reg2 <= vidin_rgb_reg1 ; + end + else + begin + vidin_rgb_reg1[12:10] <= tm3_vidin_vpo[7:5] ; + vidin_rgb_reg1[7:3] <= tm3_vidin_vpo[4:0] ; + vidin_addr_reg1 <= {vert, tm3_vidin_rts0, horiz} ; + end + end + + always @(posedge tm3_clk_v0) + begin + creg1 <= tm3_vidin_cref ; + creg2 <= creg1 ; + creg3 <= creg2 ; + if ((creg2 == 1'b0) & (creg3 == 1'b1) & ((vidin_addr_reg1[10]) == 1'b0) & ((vidin_addr_reg1[0]) == 1'b0)) + begin + vidin_new_data <= 1'b1 ; + vidin_rgb_reg <= vidin_rgb_reg2[7:0] ; + vidin_addr_reg <= {({2'b00, vidin_addr_reg1[18:11]}), vidin_addr_reg1[9:1]} ; + end + else + begin + vidin_new_data <= 1'b0 ; + end + end + + always @(posedge tm3_clk_v2) + begin + // A: Worked around scope issue by moving iic_stop into every case. + case (iic_state) + 7'b0000000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0000100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0000101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0000110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0000111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0001000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0001011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0001101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0001111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0010000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0010011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0010110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0010111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0011001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[7] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0011100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0011110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[6] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0011111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[5] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0100010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[4] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0100101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0100111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[3] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0101000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[2] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0101011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[1] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0101110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0101111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[0] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0110001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicaddr[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0110100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0110110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[7] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0110111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[7] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[6] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0111010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[6] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[5] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b0111101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[5] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b0111111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[4] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1000000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[4] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[3] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1000011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[3] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[2] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1000110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[2] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1000111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[1] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1001001 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[1] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001010 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001011 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[0] ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1001100 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= iicdata[0] ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001101 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1001110 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1001111 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b0 ; + end + 7'b1010000 : + begin + iic_stop <= 1'b0 ; + tm3_vidin_sda_xhdl0 <= 1'b0 ; + tm3_vidin_scl <= 1'b1 ; + end + 7'b1010001 : + begin + iic_stop <= 1'b1 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + default : + begin + iic_stop <= 1'b1 ; + tm3_vidin_sda_xhdl0 <= 1'b1 ; + tm3_vidin_scl <= 1'b1 ; + end + endcase + end + + always @(reg_prog_state or iic_stop) + begin + case (reg_prog_state) + reg_prog1 : + begin + rst_done = 1'b1 ; + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog2 ; + end + else + begin + reg_prog_nextstate = reg_prog1 ; + end + + end + reg_prog2 : + begin + iicaddr = 8'b00000010 ; + iicdata = {5'b11000, 3'b000} ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog3 ; + end + else + begin + reg_prog_nextstate = reg_prog2 ; + end + end + reg_prog3 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog4 ; + end + else + begin + reg_prog_nextstate = reg_prog3 ; + end + end + reg_prog4 : + begin + iicaddr = 8'b00000011 ; + iicdata = 8'b00100011 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog5 ; + end + else + begin + reg_prog_nextstate = reg_prog4 ; + end + end + reg_prog5 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog6 ; + end + else + begin + reg_prog_nextstate = reg_prog5 ; + end + end + reg_prog6 : + begin + iicaddr = 8'b00000110 ; + iicdata = 8'b11101011 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog7 ; + end + else + begin + + reg_prog_nextstate = reg_prog6 ; + end + end + reg_prog7 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog8 ; + end + else + begin + reg_prog_nextstate = reg_prog7 ; + end + end + reg_prog8 : + begin + iicaddr = 8'b00000111 ; + iicdata = 8'b11100000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog9 ; + end + else + begin + reg_prog_nextstate = reg_prog8 ; + end + end + reg_prog9 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog10 ; + end + else + begin + reg_prog_nextstate = reg_prog9 ; + end + end + reg_prog10 : + begin + iicaddr = 8'b00001000 ; + iicdata = 8'b10000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog11 ; + end + else + begin + reg_prog_nextstate = reg_prog10 ; + end + end + reg_prog11 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog12 ; + end + + else + begin + reg_prog_nextstate = reg_prog11 ; + end + end + reg_prog12 : + begin + iicaddr = 8'b00001001 ; + iicdata = 8'b00000001 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog13 ; + end + else + begin + reg_prog_nextstate = reg_prog12 ; + end + end + reg_prog13 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog14 ; + end + else + begin + reg_prog_nextstate = reg_prog13 ; + end + end + reg_prog14 : + begin + iicaddr = 8'b00001010 ; + iicdata = 8'b10000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog15 ; + end + else + begin + reg_prog_nextstate = reg_prog14 ; + end + end + reg_prog15 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog16 ; + end + else + begin + reg_prog_nextstate = reg_prog15 ; + end + end + reg_prog16 : + begin + iicaddr = 8'b00001011 ; + iicdata = 8'b01000111 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + + begin + reg_prog_nextstate = reg_prog17 ; + end + else + begin + reg_prog_nextstate = reg_prog16 ; + end + end + reg_prog17 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog18 ; + end + else + begin + reg_prog_nextstate = reg_prog17 ; + end + end + reg_prog18 : + begin + iicaddr = 8'b00001100 ; + iicdata = 8'b01000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog19 ; + end + else + begin + reg_prog_nextstate = reg_prog18 ; + end + end + reg_prog19 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog20 ; + end + else + begin + reg_prog_nextstate = reg_prog19 ; + end + end + reg_prog20 : + begin + iicaddr = 8'b00001110 ; + iicdata = 8'b00000001 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog21 ; + end + else + begin + reg_prog_nextstate = reg_prog20 ; + end + end + reg_prog21 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog22 ; + end + else + begin + reg_prog_nextstate = reg_prog21 ; + end + end + reg_prog22 : + begin + iicaddr = 8'b00010000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog23 ; + end + else + begin + reg_prog_nextstate = reg_prog22 ; + end + end + reg_prog23 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog24 ; + end + else + begin + reg_prog_nextstate = reg_prog23 ; + end + end + reg_prog24 : + begin + iicaddr = 8'b00010001 ; + iicdata = 8'b00011100 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog25 ; + end + else + begin + reg_prog_nextstate = reg_prog24 ; + end + end + reg_prog25 : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b1 ; + if (iic_stop == 1'b0) + begin + reg_prog_nextstate = reg_prog26 ; + end + else + begin + reg_prog_nextstate = reg_prog25 ; + end + end + reg_prog26 : + begin + iicaddr = 8'b00010010 ; + iicdata = 8'b00001001 ; + iic_start = 1'b0 ; + if (iic_stop == 1'b1) + begin + reg_prog_nextstate = reg_prog_end ; + end + else + begin + reg_prog_nextstate = reg_prog26 ; + end + end + reg_prog_end : + begin + iicaddr = 8'b00000000 ; + iicdata = 8'b00000000 ; + iic_start = 1'b0 ; + reg_prog_nextstate = reg_prog_end ; + end + endcase + end + + always @(posedge tm3_clk_v2) + begin + if (rst_done == 1'b1) + begin + rst <= 1'b1 ; + end + temp_reg1 <= tm3_vidin_rts0 ; + temp_reg2 <= temp_reg1 ; + if (rst == 1'b0) + begin + reg_prog_state <= reg_prog1 ; + end + else if ((temp_reg1 == 1'b0) & (temp_reg2 == 1'b1)) + begin + reg_prog_state <= reg_prog1 ; + end + else + begin + reg_prog_state <= reg_prog_nextstate ; + end + if (iic_stop == 1'b0) + begin + iic_state <= iic_state + 1 ; + end + else if (iic_start == 1'b1) + begin + iic_state <= 7'b0000001 ; + end + end +endmodule + + + diff --git a/openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v b/openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v new file mode 100644 index 000000000..718cd3671 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/tpu.16x16.int8.v @@ -0,0 +1,5711 @@ +`timescale 1ns / 1ps + +/////////////////////////////////// +// Overview +/////////////////////////////////// +//This design is based on the architecture from Google's TPU v1 [1]. At its heart, +//it uses a 16x16 matrix multiplication unit, instead of a 256x256 matrix multiplication +//unit used by the TPU. The design uses int8 precision. This systolic matrix multiplication +//unit is a output stationary unit, compared to weight stationary architecture used in the TPU. +//The activations are stored in RAM block A, whereas the weights are stored in RAM block B. +//Control and configuration are done through an APB interface, instead of a PCIe interface on +//the TPU. The normalization block applies the mean and variance values to the output of the +//matrix multiplication unit. Pooling unit supports 3 pooling windows - 1x1, 2x2 and 4x4. +//The activation unit supports two activation functions - rectified linear unit (ReLU) and +//the hyperbolic tangent (TanH). The activation unit is the last unit before the results +//are written back to RAM block A, from where they can be read again into the matrix +//multiplication unit for the next layer. +// +//[1] Jouppi et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017 + +////////////////////////////////////// +// Module hierarchy +////////////////////////////////////// +// top (the top level design) +// |--- ram matrix_A (the RAM that stores matrix A (activations)) +// |--- ram matrix_B (the RAM that stores matrix B (weights)) +// |--- control u_control (the state machine that controls the operation) +// |--- cfg u_cfg (unit to configure/observe registers using an APB interface) +// |--- matmul_16x16_systolic u_matmul (systolic 16x16 matrix multiplication unit) +// | |--- output_logic (contains logic to shift out the outputs of matmul) +// | |--- systolic_data_setup (contains logic to shift in the inputs of the matmul) +// | |--- systolic_pe_matrix (16x16 matrix of processing elements) +// | |--- processing_element (one processing element) +// | |--- seq_mac (mac block inside each processing element) +// | |--- qmult (multiplier inside each mac) +// | |--- qadd (adder inside each mac) +// |--- norm u_norm (normalization block; applies mean and variance) +// |--- pool u_pool (block that performs pooling) +// |--- activation u_activation(block that applies activation - relu or tanh) + +////////////////////////////////////// +// Tested architectures +////////////////////////////////////// +// This design has been tested with: +// 1. The VTR flagship 40nm architecture. Example: arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +// Properties of this design on this architecture: +// Critical path delay: 8.32 ns +// Clock frequency: 120.19 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 1.97532e+08 MWTAs +// Resource usage: 1556 LBs, 8 RAMs, 276 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3200 sec +// 2. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/stratix10_arch.xml +// Properties of this design on this architecture: +// Critical path delay: 9.24 ns +// Clock frequency: 108.17 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 4.95598e+07 MWTAs +// Resource usage: 1477 LBs, 14 RAMs, 280 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 3400 sec + +////////////////////////////////////// +// Parameters +////////////////////////////////////// + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 16x16 matrix with a 16x16 matrix. +`define DESIGN_SIZE 16 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 16 +`define MASK_WIDTH 16 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 16 bytes of memory (i.e. 16 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +// Register specification +///////////////////////////////////////////////// + +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//This used to be a normal signal, but changing it to a `define. +//That's because it's not required to be a variable in this design. +//And ODIN doesn't seem to propagate constants properly. +`define final_mat_mul_size 16 + +///////////////////////////////////// +// Matrix multiplication unit +//////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020-09-27 21:12:45.762386 +// Design Name: +// Module Name: matmul_16x16_systolic +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module matmul_16x16_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + +final_mat_mul_size, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + ((final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] b1_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_1; +wire [`DWIDTH-1:0] b2_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_1; +wire [`DWIDTH-1:0] b3_data_delayed_2; +wire [`DWIDTH-1:0] b3_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_1; +wire [`DWIDTH-1:0] b4_data_delayed_2; +wire [`DWIDTH-1:0] b4_data_delayed_3; +wire [`DWIDTH-1:0] b4_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_1; +wire [`DWIDTH-1:0] b5_data_delayed_2; +wire [`DWIDTH-1:0] b5_data_delayed_3; +wire [`DWIDTH-1:0] b5_data_delayed_4; +wire [`DWIDTH-1:0] b5_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_1; +wire [`DWIDTH-1:0] b6_data_delayed_2; +wire [`DWIDTH-1:0] b6_data_delayed_3; +wire [`DWIDTH-1:0] b6_data_delayed_4; +wire [`DWIDTH-1:0] b6_data_delayed_5; +wire [`DWIDTH-1:0] b6_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_1; +wire [`DWIDTH-1:0] b7_data_delayed_2; +wire [`DWIDTH-1:0] b7_data_delayed_3; +wire [`DWIDTH-1:0] b7_data_delayed_4; +wire [`DWIDTH-1:0] b7_data_delayed_5; +wire [`DWIDTH-1:0] b7_data_delayed_6; +wire [`DWIDTH-1:0] b7_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_1; +wire [`DWIDTH-1:0] b8_data_delayed_2; +wire [`DWIDTH-1:0] b8_data_delayed_3; +wire [`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.final_mat_mul_size(final_mat_mul_size), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), + +.final_mat_mul_size(final_mat_mul_size), + .matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC6_0(matrixC6_0), +.matrixC6_1(matrixC6_1), +.matrixC6_2(matrixC6_2), +.matrixC6_3(matrixC6_3), +.matrixC6_4(matrixC6_4), +.matrixC6_5(matrixC6_5), +.matrixC6_6(matrixC6_6), +.matrixC6_7(matrixC6_7), +.matrixC6_8(matrixC6_8), +.matrixC6_9(matrixC6_9), +.matrixC6_10(matrixC6_10), +.matrixC6_11(matrixC6_11), +.matrixC6_12(matrixC6_12), +.matrixC6_13(matrixC6_13), +.matrixC6_14(matrixC6_14), +.matrixC6_15(matrixC6_15), +.matrixC7_0(matrixC7_0), +.matrixC7_1(matrixC7_1), +.matrixC7_2(matrixC7_2), +.matrixC7_3(matrixC7_3), +.matrixC7_4(matrixC7_4), +.matrixC7_5(matrixC7_5), +.matrixC7_6(matrixC7_6), +.matrixC7_7(matrixC7_7), +.matrixC7_8(matrixC7_8), +.matrixC7_9(matrixC7_9), +.matrixC7_10(matrixC7_10), +.matrixC7_11(matrixC7_11), +.matrixC7_12(matrixC7_12), +.matrixC7_13(matrixC7_13), +.matrixC7_14(matrixC7_14), +.matrixC7_15(matrixC7_15), +.matrixC8_0(matrixC8_0), +.matrixC8_1(matrixC8_1), +.matrixC8_2(matrixC8_2), +.matrixC8_3(matrixC8_3), +.matrixC8_4(matrixC8_4), +.matrixC8_5(matrixC8_5), +.matrixC8_6(matrixC8_6), +.matrixC8_7(matrixC8_7), +.matrixC8_8(matrixC8_8), +.matrixC8_9(matrixC8_9), +.matrixC8_10(matrixC8_10), +.matrixC8_11(matrixC8_11), +.matrixC8_12(matrixC8_12), +.matrixC8_13(matrixC8_13), +.matrixC8_14(matrixC8_14), +.matrixC8_15(matrixC8_15), +.matrixC9_0(matrixC9_0), +.matrixC9_1(matrixC9_1), +.matrixC9_2(matrixC9_2), +.matrixC9_3(matrixC9_3), +.matrixC9_4(matrixC9_4), +.matrixC9_5(matrixC9_5), +.matrixC9_6(matrixC9_6), +.matrixC9_7(matrixC9_7), +.matrixC9_8(matrixC9_8), +.matrixC9_9(matrixC9_9), +.matrixC9_10(matrixC9_10), +.matrixC9_11(matrixC9_11), +.matrixC9_12(matrixC9_12), +.matrixC9_13(matrixC9_13), +.matrixC9_14(matrixC9_14), +.matrixC9_15(matrixC9_15), +.matrixC10_0(matrixC10_0), +.matrixC10_1(matrixC10_1), +.matrixC10_2(matrixC10_2), +.matrixC10_3(matrixC10_3), +.matrixC10_4(matrixC10_4), +.matrixC10_5(matrixC10_5), +.matrixC10_6(matrixC10_6), +.matrixC10_7(matrixC10_7), +.matrixC10_8(matrixC10_8), +.matrixC10_9(matrixC10_9), +.matrixC10_10(matrixC10_10), +.matrixC10_11(matrixC10_11), +.matrixC10_12(matrixC10_12), +.matrixC10_13(matrixC10_13), +.matrixC10_14(matrixC10_14), +.matrixC10_15(matrixC10_15), +.matrixC11_0(matrixC11_0), +.matrixC11_1(matrixC11_1), +.matrixC11_2(matrixC11_2), +.matrixC11_3(matrixC11_3), +.matrixC11_4(matrixC11_4), +.matrixC11_5(matrixC11_5), +.matrixC11_6(matrixC11_6), +.matrixC11_7(matrixC11_7), +.matrixC11_8(matrixC11_8), +.matrixC11_9(matrixC11_9), +.matrixC11_10(matrixC11_10), +.matrixC11_11(matrixC11_11), +.matrixC11_12(matrixC11_12), +.matrixC11_13(matrixC11_13), +.matrixC11_14(matrixC11_14), +.matrixC11_15(matrixC11_15), +.matrixC12_0(matrixC12_0), +.matrixC12_1(matrixC12_1), +.matrixC12_2(matrixC12_2), +.matrixC12_3(matrixC12_3), +.matrixC12_4(matrixC12_4), +.matrixC12_5(matrixC12_5), +.matrixC12_6(matrixC12_6), +.matrixC12_7(matrixC12_7), +.matrixC12_8(matrixC12_8), +.matrixC12_9(matrixC12_9), +.matrixC12_10(matrixC12_10), +.matrixC12_11(matrixC12_11), +.matrixC12_12(matrixC12_12), +.matrixC12_13(matrixC12_13), +.matrixC12_14(matrixC12_14), +.matrixC12_15(matrixC12_15), +.matrixC13_0(matrixC13_0), +.matrixC13_1(matrixC13_1), +.matrixC13_2(matrixC13_2), +.matrixC13_3(matrixC13_3), +.matrixC13_4(matrixC13_4), +.matrixC13_5(matrixC13_5), +.matrixC13_6(matrixC13_6), +.matrixC13_7(matrixC13_7), +.matrixC13_8(matrixC13_8), +.matrixC13_9(matrixC13_9), +.matrixC13_10(matrixC13_10), +.matrixC13_11(matrixC13_11), +.matrixC13_12(matrixC13_12), +.matrixC13_13(matrixC13_13), +.matrixC13_14(matrixC13_14), +.matrixC13_15(matrixC13_15), +.matrixC14_0(matrixC14_0), +.matrixC14_1(matrixC14_1), +.matrixC14_2(matrixC14_2), +.matrixC14_3(matrixC14_3), +.matrixC14_4(matrixC14_4), +.matrixC14_5(matrixC14_5), +.matrixC14_6(matrixC14_6), +.matrixC14_7(matrixC14_7), +.matrixC14_8(matrixC14_8), +.matrixC14_9(matrixC14_9), +.matrixC14_10(matrixC14_10), +.matrixC14_11(matrixC14_11), +.matrixC14_12(matrixC14_12), +.matrixC14_13(matrixC14_13), +.matrixC14_14(matrixC14_14), +.matrixC14_15(matrixC14_15), +.matrixC15_0(matrixC15_0), +.matrixC15_1(matrixC15_1), +.matrixC15_2(matrixC15_2), +.matrixC15_3(matrixC15_3), +.matrixC15_4(matrixC15_4), +.matrixC15_5(matrixC15_5), +.matrixC15_6(matrixC15_6), +.matrixC15_7(matrixC15_7), +.matrixC15_8(matrixC15_8), +.matrixC15_9(matrixC15_9), +.matrixC15_10(matrixC15_10), +.matrixC15_11(matrixC15_11), +.matrixC15_12(matrixC15_12), +.matrixC15_13(matrixC15_13), +.matrixC15_14(matrixC15_14), +.matrixC15_15(matrixC15_15), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, + +final_mat_mul_size, + matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; + +input [7:0] final_mat_mul_size; + input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == ((final_mat_mul_size<<2) - final_mat_mul_size - 1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +integer counter; +reg [16*`DWIDTH-1:0] c_data_out; +reg [16*`DWIDTH-1:0] c_data_out_1; +reg [16*`DWIDTH-1:0] c_data_out_2; +reg [16*`DWIDTH-1:0] c_data_out_3; +reg [16*`DWIDTH-1:0] c_data_out_4; +reg [16*`DWIDTH-1:0] c_data_out_5; +reg [16*`DWIDTH-1:0] c_data_out_6; +reg [16*`DWIDTH-1:0] c_data_out_7; +reg [16*`DWIDTH-1:0] c_data_out_8; +reg [16*`DWIDTH-1:0] c_data_out_9; +reg [16*`DWIDTH-1:0] c_data_out_10; +reg [16*`DWIDTH-1:0] c_data_out_11; +reg [16*`DWIDTH-1:0] c_data_out_12; +reg [16*`DWIDTH-1:0] c_data_out_13; +reg [16*`DWIDTH-1:0] c_data_out_14; +reg [16*`DWIDTH-1:0] c_data_out_15; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_1 <= {matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_2 <= {matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_3 <= {matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_4 <= {matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_5 <= {matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_6 <= {matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_7 <= {matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_8 <= {matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_9 <= {matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_10 <= {matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_11 <= {matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_12 <= {matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_13 <= {matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_14 <= {matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_15 <= {matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +final_mat_mul_size, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] final_mat_mul_size; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+final_mat_mul_size)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +assign a_data_out = {a15_15to15_16,a14_15to14_16,a13_15to13_16,a12_15to12_16,a11_15to11_16,a10_15to10_16,a9_15to9_16,a8_15to8_16,a7_15to7_16,a6_15to6_16,a5_15to5_16,a4_15to4_16,a3_15to3_16,a2_15to2_16,a1_15to1_16,a0_15to0_16}; +assign b_data_out = {b15_15to16_15,b15_14to16_14,b15_13to16_13,b15_12to16_12,b15_11to16_11,b15_10to16_10,b15_9to16_9,b15_8to16_8,b15_7to16_7,b15_6to16_6,b15_5to16_5,b15_4to16_4,b15_3to16_3,b15_2to16_2,b15_1to16_1,b15_0to16_0}; + +endmodule + +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +//we just truncate the higher bits of the product +//assign add_out = mul_out + out; +qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); + +always @(posedge clk) begin + if (reset) begin + out_temp <= 0; + end else begin + out_temp <= add_out; + end +end + +//down cast the result +assign out = + (out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + +endmodule + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule + + +////////////////////////////////////////////// +// Configuration block +////////////////////////////////////////////// + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols, + output reg [`MASK_WIDTH-1:0] validity_mask_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= `DESIGN_SIZE; + address_stride_b <= `DESIGN_SIZE; + address_stride_c <= `DESIGN_SIZE; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + + +//////////////////////////////////////////////// +// Normalization block +//////////////////////////////////////////////// + +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_norm, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data; +reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data; +reg done_norm_internal; +reg norm_in_progress; +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available_flopped; +assign out_data = (enable_norm) ? out_data_internal : inp_data_flopped; +assign done_norm = (enable_norm) ? done_norm_internal : 1'b1; + +//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul. +//on each clock edge, if in_data_available is 1, then we will normalize the inputs. + +//the code uses the funky part-select syntax. example: +//wire [7:0] byteN = word[byte_num*8 +: 8]; +//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available +//+: indicates the part-select increases from the starting point +//-: indicates the part-select decreases from the starting point +//another example: +//loc = 3; +//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4]; + +reg [31:0] cycle_count; +reg [31:0] i; +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end else if (in_data_available || norm_in_progress) begin + cycle_count = cycle_count + 1; + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (validity_mask[i] == 1'b1) begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH] - mean); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var); + end + else begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH]); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH]); + end + end + + //Out data is available starting with the second clock cycle because + //in the first cycle, we only apply the mean. + if(cycle_count==2) begin + out_data_available_internal <= 1; + end + + //When we've normalized values N times, where N is the matmul + //size, that means we're done. But there is one additional cycle + //that is taken in the beginning (when we are applying the mean to the first + //column of data). We can call this the Initiation Interval of the pipeline. + //So, for a 4x4 matmul, this block takes 5 cycles. + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_norm_internal <= 1'b1; + norm_in_progress <= 0; + end + else begin + norm_in_progress <= 1; + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + end +end + +assign out_data_internal = variance_applied_data; + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`DESIGN_SIZE*`DWIDTH-1:0] d0; +input [`DESIGN_SIZE*`DWIDTH-1:0] d1; +input [`DESIGN_SIZE-1:0] we0; +input [`DESIGN_SIZE-1:0] we1; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1; +input clk; + +`ifdef SIMULATION + +reg [7:0] ram[((1<<`AWIDTH)-1):0]; +reg [31:0] i; + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q0[i*`DWIDTH +: `DWIDTH] <= ram[addr0+i]; + end +end + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q1[i*`DWIDTH +: `DWIDTH] <= ram[addr1+i]; + end +end + +`else +//BRAMs available in VTR FPGA architectures have one bit write-enables. +//So let's combine multiple bits into 1. We don't have a usecase of +//writing/not-writing only parts of the word anyway. +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + + +endmodule + +//////////////////////////////////////////////// +// Control unit +//////////////////////////////////////////////// + +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////// +// Pooling block +//////////////////////////////////////////////// + +module pool( + input enable_pool, + input in_data_available, + input [`MAX_BITS_POOL-1:0] pool_window_size, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_pool, + input clk, + input reset +); + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp; +reg done_pool_temp; +reg out_data_available_temp; +reg [31:0] i,j; +reg [31:0] cycle_count; + +always @(posedge clk) begin + if (reset || ~enable_pool || ~in_data_available) begin + out_data_temp <= 0; + done_pool_temp <= 0; + out_data_available_temp <= 0; + cycle_count <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end + + else if (in_data_available) begin + cycle_count = cycle_count + 1; + out_data_available_temp <= 1; + + case (pool_window_size) + 1: begin + out_data_temp <= inp_data; + end + 2: begin + for (i = 0; i < `DESIGN_SIZE/2; i = i + 8) begin + out_data_temp[ i +: 8] <= (inp_data[i*2 +: 8] + inp_data[i*2 + 8 +: 8]) >> 1; + end + end + 4: begin + for (i = 0; i < `DESIGN_SIZE/4; i = i + 8) begin + //TODO: If 3 adders are the critical path, break into 2 cycles + out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2; + end + end + endcase + + if(cycle_count==`DESIGN_SIZE) begin + done_pool_temp <= 1'b1; + end + end +end + +assign out_data = enable_pool ? out_data_temp : inp_data_flopped; +assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped; +assign done_pool = enable_pool ? done_pool_temp : 1'b1; + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + +//////////////////////////////////////////////// +// Activation block +//////////////////////////////////////////////// + +module activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_activation, + input clk, + input reset +); + +reg done_activation_internal; +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] slope_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] relu_applied_data_internal; +reg [31:0] i; +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [(`DESIGN_SIZE*4)-1:0] address; +reg [(`DESIGN_SIZE*8)-1:0] data_slope; +reg [(`DESIGN_SIZE*8)-1:0] data_slope_flopped; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_delayed; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_flopped; + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +always @(posedge clk) begin + if (reset) begin + inp_data_flopped <= 0; + data_slope_flopped <= 0; + end else begin + inp_data_flopped <= inp_data; + data_slope_flopped <= data_slope; + end +end + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data_flopped; +assign done_activation = enable_activation ? done_activation_internal : 1'b1; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available_flopped; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + in_data_available_flopped <= in_data_available; + end else if(in_data_available || activation_in_progress) begin + cycle_count = cycle_count + 1; + + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= data_slope_flopped[i*8 +: 8] * inp_data_flopped[i*`DWIDTH +:`DWIDTH]; + data_intercept_flopped[i*8 +: 8] <= data_intercept[i*8 +: 8]; + data_intercept_delayed[i*8 +: 8] <= data_intercept_flopped[i*8 +: 8]; + intercept_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] + data_intercept_delayed[i*8 +: 8]; + end else begin // ReLU + relu_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= inp_data[i*`DWIDTH] ? {`DWIDTH{1'b0}} : inp_data[i*`DWIDTH +:`DWIDTH]; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==3) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==(`DESIGN_SIZE+2)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +assign out_data_internal = (activation_type) ? intercept_applied_data_internal : relu_applied_data_internal; + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_slope[i*8+:8] = 8'd0; + 4'b0001: data_slope[i*8+:8] = 8'd0; + 4'b0010: data_slope[i*8+:8] = 8'd2; + 4'b0011: data_slope[i*8+:8] = 8'd3; + 4'b0100: data_slope[i*8+:8] = 8'd4; + 4'b0101: data_slope[i*8+:8] = 8'd0; + 4'b0110: data_slope[i*8+:8] = 8'd4; + 4'b0111: data_slope[i*8+:8] = 8'd3; + 4'b1000: data_slope[i*8+:8] = 8'd2; + 4'b1001: data_slope[i*8+:8] = 8'd0; + 4'b1010: data_slope[i*8+:8] = 8'd0; + default: data_slope[i*8+:8] = 8'd0; + endcase + end +end + +//LUT for the intercept +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_intercept[i*8+:8] = 8'd127; + 4'b0001: data_intercept[i*8+:8] = 8'd99; + 4'b0010: data_intercept[i*8+:8] = 8'd46; + 4'b0011: data_intercept[i*8+:8] = 8'd18; + 4'b0100: data_intercept[i*8+:8] = 8'd0; + 4'b0101: data_intercept[i*8+:8] = 8'd0; + 4'b0110: data_intercept[i*8+:8] = 8'd0; + 4'b0111: data_intercept[i*8+:8] = -8'd18; + 4'b1000: data_intercept[i*8+:8] = -8'd46; + 4'b1001: data_intercept[i*8+:8] = -8'd99; + 4'b1010: data_intercept[i*8+:8] = -8'd127; + default: data_intercept[i*8+:8] = 8'd0; + endcase + end +end + +//Logic to find address +always @(inp_data) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if((inp_data[i*`DWIDTH +:`DWIDTH])>=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + + +////////////////////////////////////////////////////// +// Top module +////////////////////////////////////////////////////// + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] norm_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols; +wire [`MASK_WIDTH-1:0] validity_mask_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +matmul_16x16_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .final_mat_mul_size(8'd16), + .a_loc(8'd0), + .b_loc(8'd0) +); + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(matmul_c_data_available), + .inp_data(matmul_c_data_out), + .out_data(norm_data_out), + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pool u_pool( + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + .pool_window_size(pool_window_size), + .inp_data(norm_data_out), + .out_data(pool_data_out), + .out_data_available(pool_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_pool(done_pool), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(pool_out_data_available), + .inp_data(pool_data_out), + .out_data(activation_data_out), + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. +always @(posedge clk) begin + if (reset) begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (activation_out_data_available) begin + bram_wdata_a <= activation_data_out; + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= activation_out_data_available; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end +end + +endmodule diff --git a/openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v b/openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v new file mode 100644 index 000000000..1e3f32683 --- /dev/null +++ b/openfpga_flow/benchmarks/vtr_benchmark/tpu.32x32.int8.v @@ -0,0 +1,15437 @@ +`timescale 1ns / 1ps + +/////////////////////////////////// +// Overview +/////////////////////////////////// +//This design is based on the architecture from Google's TPU v1 [1]. At its heart, +//it uses a 32x32 matrix multiplication unit, instead of a 256x256 matrix multiplication +//unit used by the TPU. The design uses int8 precision. This systolic matrix multiplication +//unit is a output stationary unit, compared to weight stationary architecture used in the TPU. +//The activations are stored in RAM block A, whereas the weights are stored in RAM block B. +//Control and configuration are done through an APB interface, instead of a PCIe interface on +//the TPU. The normalization block applies the mean and variance values to the output of the +//matrix multiplication unit. Pooling unit supports 3 pooling windows - 1x1, 2x2 and 4x4. +//The activation unit supports two activation functions - rectified linear unit (ReLU) and +//the hyperbolic tangent (TanH). The activation unit is the last unit before the results +//are written back to RAM block A, from where they can be read again into the matrix +//multiplication unit for the next layer. +// +//[1] Jouppi et. al., In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017 + +////////////////////////////////////// +// Module hierarchy +////////////////////////////////////// +// top (the top level design) +// |--- ram matrix_A (the RAM that stores matrix A (activations)) +// |--- ram matrix_B (the RAM that stores matrix B (weights)) +// |--- control u_control (the state machine that controls the operation) +// |--- cfg u_cfg (unit to configure/observe registers using an APB interface) +// |--- matmul_32x32_systolic u_matmul (systolic 32x32 matrix multiplication unit) +// | |--- output_logic (contains logic to shift out the outputs of matmul) +// | |--- systolic_data_setup (contains logic to shift in the inputs of the matmul) +// | |--- systolic_pe_matrix (32x32 matrix of processing elements) +// | |--- processing_element (one processing element) +// | |--- seq_mac (mac block inside each processing element) +// | |--- qmult (multiplier inside each mac) +// | |--- qadd (adder inside each mac) +// |--- norm u_norm (normalization block; applies mean and variance) +// |--- pool u_pool (block that performs pooling) +// |--- activation u_activation(block that applies activation - relu or tanh) + +////////////////////////////////////// +// Tested architectures +////////////////////////////////////// +// This design has been tested with: +// 1. The VTR flagship 40nm architecture. Example: arch/timing/k6_frac_N10_frac_chain_mem32K_40nm.xml +// Properties of this design on this architecture: +// Critical path delay: 11.79 ns +// Clock frequency: 84.76 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 7.07642e+08 MWTAs +// Resource usage: 5150 LBs, 16 RAMs, 1064 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 11500 sec +// 2. 22nm architectures generated from COFFE. Example: arch/COFFE_22nm/stratix10_arch.xml +// Properties of this design on this architecture: +// Critical path delay: 12.92 ns +// Clock frequency: 77.39 MHz +// Critical path: Includes the multiplier in the MAC in a PE and inter-CLB routing +// Logic area (used): 1.72408e+08 MWTAs +// Resource usage: 5033 LBs, 26 RAMs, 1072 Multipliers +// Runtime (on Intel Xeon E5-2430 2.5GHz with single thread): 12500 sec + +////////////////////////////////////// +// Parameters +////////////////////////////////////// + +//The width of the data. This design uses int8 precision. So, DWIDTH is 8 +//To change to a floating point 16 version, change this to 16 and also +//change the datapath components (like adder and multiplier) to be floating point. +`define DWIDTH 8 + +//This is the size of the matrix multiplier unit. In this design, we have a systolic +//matrix multiplication unit that can multiply 32x32 matrix with a 32x32 matrix. +`define DESIGN_SIZE 32 +`define LOG2_DESIGN_SIZE 5 +`define MAT_MUL_SIZE 32 +`define MASK_WIDTH 32 +`define LOG2_MAT_MUL_SIZE 5 + +//This it the size of the address bus, or the depth of the RAM. Each location of +//the RAM is DWIDTH * MAT_MUL_SIZE wide. So, in this design, we use a total of +//1024 * 32 bytes of memory (i.e. 32 KB). +`define AWIDTH 10 + +//This is the number of clock cycles spent in the mac block +`define NUM_CYCLES_IN_MAC 3 + +//This defines the latency of accessing data from a block ram +`define MEM_ACCESS_LATENCY 1 + +//Data width and address width of the APB interface for registers +`define REG_DATAWIDTH 32 +`define REG_ADDRWIDTH 8 + +//Width of the stride for each column in the matrices (same as ram address width) +`define ADDR_STRIDE_WIDTH 16 + +//Number of bits to specify the pooling window. We support 3 sizes. +`define MAX_BITS_POOL 3 + +///////////////////////////////////////////////// +// Register specification +///////////////////////////////////////////////// + +//--------------------------------------- +//Addr 0 : Register with enables for various blocks. +//Includes mode of operation (convolution or fully_connected) +//--------------------------------------- +`define REG_ENABLES_ADDR 32'h0 +//Bit 0: enable_matmul +//Bit 1: enable_norm +//Bit 2: enable_pool +//Bit 3: enable_activation +//Bit 31: enable_conv_mode + +//--------------------------------------- +//Addr 4: Register that triggers the whole TPU +//--------------------------------------- +`define REG_STDN_TPU_ADDR 32'h4 +//Bit 0: start_tpu +//Bit 31: done_tpu + +//--------------------------------------- +//Addr 8: Register that stores the mean of the values +//--------------------------------------- +`define REG_MEAN_ADDR 32'h8 +//Bit 7:0: mean + +//--------------------------------------- +//Addr A: Register that stores the inverse variance of the values +//--------------------------------------- +`define REG_INV_VAR_ADDR 32'hA +//Bit 7:0: inv_var + +//--------------------------------------- +//Addr E: Register that stores the starting address of matrix A in BRAM A. +//In fully-connected mode, this register should be programmed with the +//address of the matrix being currently multiplied. That is, the +//address of the matrix of the matmul. So, this register will be +//programmed every time the matmul is kicked off during accumulation stages. +//Use the STRIDE registers to tell the matmul to increment addresses. +//In convolution mode, this register should be programmed with the +//address of the input activation matrix. No need to configure +//this every time the matmul is kicked off for accmulation. Just program it +//once it the beginning. Address increments are handled automatically . +//--------------------------------------- +`define REG_MATRIX_A_ADDR 32'he +//Bit `AWIDTH-1:0 address_mat_a + +//--------------------------------------- +//Addr 12: Register that stores the starting address of matrix B in BRAM B. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_B_ADDR 32'h12 +//Bit `AWIDTH-1:0 address_mat_b + +//--------------------------------------- +//Addr 16: Register that stores the starting address of matrix C in BRAM C. +//See detailed note on the usage of this register in REG_MATRIX_A_ADDR. +//--------------------------------------- +`define REG_MATRIX_C_ADDR 32'h16 +//Bit `AWIDTH-1:0 address_mat_c + +//--------------------------------------- +//Addr 24: Register that controls the accumulation logic +//--------------------------------------- +`define REG_ACCUM_ACTIONS_ADDR 32'h24 +//Bit 0 save_output_to_accumulator +//Bit 1 add_accumulator_to_output + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 28: Register that stores the stride that should be taken to address +//elements in matrix A, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix A in the vertical +//direction. +//--------------------------------------- +`define REG_MATRIX_A_STRIDE_ADDR 32'h28 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_a + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 32: Register that stores the stride that should be taken to address +//elements in matrix B, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix B in the horizontal +//direction. +//--------------------------------------- +`define REG_MATRIX_B_STRIDE_ADDR 32'h32 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_b + +//--------------------------------------- +//(Only applicable in fully-connected mode) +//Addr 36: Register that stores the stride that should be taken to address +//elements in matrix C, after every MAT_MUL_SIZE worth of data has been fetched. +//See the diagram in "Meeting-16" notes in the EE382V project Onenote notebook. +//This stride is applied when incrementing addresses for matrix C in the vertical +//direction (this is generally same as address_stride_a). +//--------------------------------------- +`define REG_MATRIX_C_STRIDE_ADDR 32'h36 +//Bit `ADDR_STRIDE_WIDTH-1:0 address_stride_c + +//--------------------------------------- +//Addr 3A: Register that controls the activation block. Currently, the available +//settings are the selector of activation function that will be used. There are +//two options: ReLU and TanH. To use ReLU, clear the LSB of this register. To +//use TanH, set the LSB of this register. +//--------------------------------------- +`define REG_ACTIVATION_CSR_ADDR 32'h3A + +//--------------------------------------- +//Addr 3E: Register defining pooling window size +//--------------------------------------- +`define REG_POOL_WINDOW_ADDR 32'h3E +//Bit `MAX_BITS_POOL-1:0 pool window size + +//--------------------------------------- +//Addr 40: Register defining convolution parameters - 1 +//---------------------------------------- +`define REG_CONV_PARAMS_1_ADDR 32'h40 +//Bits filter_height (R) 3:0 +//Bits filter width (S) 7:4 +//Bits stride_horizontal 11:8 +//Bits stride_vertical 15:12 +//Bits pad_left 19:16 +//Bits pad_right 23:20 +//Bits pad_top 27:24 +//Bits pad_bottom 31:28 + +//--------------------------------------- +//Addr 44: Register defining convolution parameters - 2 +//---------------------------------------- +`define REG_CONV_PARAMS_2_ADDR 32'h44 +//Bits num_channels_input (C) 15:0 +//Bits num_channels_output (K) 31:16 + +//--------------------------------------- +//Addr 48: Register defining convolution parameters - 3 +//---------------------------------------- +`define REG_CONV_PARAMS_3_ADDR 32'h48 +//Bits input_image_height (H) 15:0 +//Bits input_image_width (W) 31:16 + +//--------------------------------------- +//Addr 4C: Register defining convolution parameters - 4 +//---------------------------------------- +`define REG_CONV_PARAMS_4_ADDR 32'h4C +//Bits output_image_height (P) 15:0 +//Bits output_image_width (Q) 31:16 + +//--------------------------------------- +//Addr 50: Register defining batch size +//---------------------------------------- +`define REG_BATCH_SIZE_ADDR 32'h50 +//Bits 31:0 batch_size (number of images, N) + +//--------------------------------------- +//Addresses 54,58,5C: Registers that stores the mask of which parts of the matrices are valid. +// +//Some examples where this is useful: +//1. Input matrix is smaller than the matmul. +// Say we want to multiply a 6x6 using an 8x8 matmul. +// The matmul still operates on the whole 8x8 part, so we need +// to ensure that there are 0s in the BRAMs in the invalid parts. +// But the mask is used by the blocks other than matmul. For ex, +// norm block will use the mask to avoid applying mean and variance +// to invalid parts (so tha they stay 0). +//2. When we start with large matrices, the size of the matrices can +// reduce to something less than the matmul size because of pooling. +// In that case for the next layer, we need to tell blocks like norm, +// what is valid and what is not. +// +//Note: This masks is applied to both x and y directions and also +//applied to both input matrices - A and B. +//--------------------------------------- +`define REG_VALID_MASK_A_ROWS_ADDR 32'h20 +`define REG_VALID_MASK_A_COLS_ADDR 32'h54 +`define REG_VALID_MASK_B_ROWS_ADDR 32'h5c +`define REG_VALID_MASK_B_COLS_ADDR 32'h58 +//Bit `MASK_WIDTH-1:0 validity_mask + +//This used to be a normal signal, but changing it to a `define. +//That's because it's not required to be a variable in this design. +//And ODIN doesn't seem to propagate constants properly. +`define final_mat_mul_size 32 + +///////////////////////////////////// +// Matrix multiplication unit +//////////////////////////////////// + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020-09-27 21:12:45.762386 +// Design Name: +// Module Name: matmul_32x32_systolic +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module matmul_32x32_systolic( + clk, + reset, + pe_reset, + start_mat_mul, + done_mat_mul, + address_mat_a, + address_mat_b, + address_mat_c, + address_stride_a, + address_stride_b, + address_stride_c, + a_data, + b_data, + a_data_in, //Data values coming in from previous matmul - systolic connections + b_data_in, + c_data_in, //Data values coming in from previous matmul - systolic shifting + c_data_out, //Data values going out to next matmul - systolic shifting + a_data_out, + b_data_out, + a_addr, + b_addr, + c_addr, + c_data_available, + + validity_mask_a_rows, + validity_mask_a_cols, + validity_mask_b_rows, + validity_mask_b_cols, + + final_mat_mul_size, + + a_loc, + b_loc +); + + input clk; + input reset; + input pe_reset; + input start_mat_mul; + output done_mat_mul; + input [`AWIDTH-1:0] address_mat_a; + input [`AWIDTH-1:0] address_mat_b; + input [`AWIDTH-1:0] address_mat_c; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; + input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_in; + input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; + output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + output [`AWIDTH-1:0] a_addr; + output [`AWIDTH-1:0] b_addr; + output [`AWIDTH-1:0] c_addr; + output c_data_available; + + input [`MASK_WIDTH-1:0] validity_mask_a_rows; + input [`MASK_WIDTH-1:0] validity_mask_a_cols; + input [`MASK_WIDTH-1:0] validity_mask_b_rows; + input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +//7:0 is okay here. We aren't going to make a matmul larger than 128x128 +//In fact, these will get optimized out by the synthesis tool, because +//we hardcode them at the instantiation level. + input [7:0] final_mat_mul_size; + + input [7:0] a_loc; + input [7:0] b_loc; + +////////////////////////////////////////////////////////////////////////// +// Logic for clock counting and when to assert done +////////////////////////////////////////////////////////////////////////// + +reg done_mat_mul; +//This is 7 bits because the expectation is that clock count will be pretty +//small. For large matmuls, this will need to increased to have more bits. +//In general, a systolic multiplier takes 4*N-2+P cycles, where N is the size +//of the matmul and P is the number of pipleine stages in the MAC block. +reg [7:0] clk_cnt; + +//Finding out number of cycles to assert matmul done. +//When we have to save the outputs to accumulators, then we don't need to +//shift out data. So, we can assert done_mat_mul early. +//In the normal case, we have to include the time to shift out the results. +//Note: the count expression used to contain "4*final_mat_mul_size", but +//to avoid multiplication, we now use "final_mat_mul_size<<2" +wire [7:0] clk_cnt_for_done; + +assign clk_cnt_for_done = + ((`final_mat_mul_size<<2) - 2 + `NUM_CYCLES_IN_MAC); + +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + clk_cnt <= 0; + done_mat_mul <= 0; + end + else if (clk_cnt == clk_cnt_for_done) begin + done_mat_mul <= 1; + clk_cnt <= clk_cnt + 1; + + end + else if (done_mat_mul == 0) begin + clk_cnt <= clk_cnt + 1; + + end + else begin + done_mat_mul <= 0; + clk_cnt <= clk_cnt + 1; + end +end +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; +wire [`DWIDTH-1:0] a1_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_1; +wire [`DWIDTH-1:0] a2_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_1; +wire [`DWIDTH-1:0] a3_data_delayed_2; +wire [`DWIDTH-1:0] a3_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_1; +wire [`DWIDTH-1:0] a4_data_delayed_2; +wire [`DWIDTH-1:0] a4_data_delayed_3; +wire [`DWIDTH-1:0] a4_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_1; +wire [`DWIDTH-1:0] a5_data_delayed_2; +wire [`DWIDTH-1:0] a5_data_delayed_3; +wire [`DWIDTH-1:0] a5_data_delayed_4; +wire [`DWIDTH-1:0] a5_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_1; +wire [`DWIDTH-1:0] a6_data_delayed_2; +wire [`DWIDTH-1:0] a6_data_delayed_3; +wire [`DWIDTH-1:0] a6_data_delayed_4; +wire [`DWIDTH-1:0] a6_data_delayed_5; +wire [`DWIDTH-1:0] a6_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_1; +wire [`DWIDTH-1:0] a7_data_delayed_2; +wire [`DWIDTH-1:0] a7_data_delayed_3; +wire [`DWIDTH-1:0] a7_data_delayed_4; +wire [`DWIDTH-1:0] a7_data_delayed_5; +wire [`DWIDTH-1:0] a7_data_delayed_6; +wire [`DWIDTH-1:0] a7_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_1; +wire [`DWIDTH-1:0] a8_data_delayed_2; +wire [`DWIDTH-1:0] a8_data_delayed_3; +wire [`DWIDTH-1:0] a8_data_delayed_4; +wire [`DWIDTH-1:0] a8_data_delayed_5; +wire [`DWIDTH-1:0] a8_data_delayed_6; +wire [`DWIDTH-1:0] a8_data_delayed_7; +wire [`DWIDTH-1:0] a8_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_1; +wire [`DWIDTH-1:0] a9_data_delayed_2; +wire [`DWIDTH-1:0] a9_data_delayed_3; +wire [`DWIDTH-1:0] a9_data_delayed_4; +wire [`DWIDTH-1:0] a9_data_delayed_5; +wire [`DWIDTH-1:0] a9_data_delayed_6; +wire [`DWIDTH-1:0] a9_data_delayed_7; +wire [`DWIDTH-1:0] a9_data_delayed_8; +wire [`DWIDTH-1:0] a9_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_1; +wire [`DWIDTH-1:0] a10_data_delayed_2; +wire [`DWIDTH-1:0] a10_data_delayed_3; +wire [`DWIDTH-1:0] a10_data_delayed_4; +wire [`DWIDTH-1:0] a10_data_delayed_5; +wire [`DWIDTH-1:0] a10_data_delayed_6; +wire [`DWIDTH-1:0] a10_data_delayed_7; +wire [`DWIDTH-1:0] a10_data_delayed_8; +wire [`DWIDTH-1:0] a10_data_delayed_9; +wire [`DWIDTH-1:0] a10_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_1; +wire [`DWIDTH-1:0] a11_data_delayed_2; +wire [`DWIDTH-1:0] a11_data_delayed_3; +wire [`DWIDTH-1:0] a11_data_delayed_4; +wire [`DWIDTH-1:0] a11_data_delayed_5; +wire [`DWIDTH-1:0] a11_data_delayed_6; +wire [`DWIDTH-1:0] a11_data_delayed_7; +wire [`DWIDTH-1:0] a11_data_delayed_8; +wire [`DWIDTH-1:0] a11_data_delayed_9; +wire [`DWIDTH-1:0] a11_data_delayed_10; +wire [`DWIDTH-1:0] a11_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_1; +wire [`DWIDTH-1:0] a12_data_delayed_2; +wire [`DWIDTH-1:0] a12_data_delayed_3; +wire [`DWIDTH-1:0] a12_data_delayed_4; +wire [`DWIDTH-1:0] a12_data_delayed_5; +wire [`DWIDTH-1:0] a12_data_delayed_6; +wire [`DWIDTH-1:0] a12_data_delayed_7; +wire [`DWIDTH-1:0] a12_data_delayed_8; +wire [`DWIDTH-1:0] a12_data_delayed_9; +wire [`DWIDTH-1:0] a12_data_delayed_10; +wire [`DWIDTH-1:0] a12_data_delayed_11; +wire [`DWIDTH-1:0] a12_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_1; +wire [`DWIDTH-1:0] a13_data_delayed_2; +wire [`DWIDTH-1:0] a13_data_delayed_3; +wire [`DWIDTH-1:0] a13_data_delayed_4; +wire [`DWIDTH-1:0] a13_data_delayed_5; +wire [`DWIDTH-1:0] a13_data_delayed_6; +wire [`DWIDTH-1:0] a13_data_delayed_7; +wire [`DWIDTH-1:0] a13_data_delayed_8; +wire [`DWIDTH-1:0] a13_data_delayed_9; +wire [`DWIDTH-1:0] a13_data_delayed_10; +wire [`DWIDTH-1:0] a13_data_delayed_11; +wire [`DWIDTH-1:0] a13_data_delayed_12; +wire [`DWIDTH-1:0] a13_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_1; +wire [`DWIDTH-1:0] a14_data_delayed_2; +wire [`DWIDTH-1:0] a14_data_delayed_3; +wire [`DWIDTH-1:0] a14_data_delayed_4; +wire [`DWIDTH-1:0] a14_data_delayed_5; +wire [`DWIDTH-1:0] a14_data_delayed_6; +wire [`DWIDTH-1:0] a14_data_delayed_7; +wire [`DWIDTH-1:0] a14_data_delayed_8; +wire [`DWIDTH-1:0] a14_data_delayed_9; +wire [`DWIDTH-1:0] a14_data_delayed_10; +wire [`DWIDTH-1:0] a14_data_delayed_11; +wire [`DWIDTH-1:0] a14_data_delayed_12; +wire [`DWIDTH-1:0] a14_data_delayed_13; +wire [`DWIDTH-1:0] a14_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_1; +wire [`DWIDTH-1:0] a15_data_delayed_2; +wire [`DWIDTH-1:0] a15_data_delayed_3; +wire [`DWIDTH-1:0] a15_data_delayed_4; +wire [`DWIDTH-1:0] a15_data_delayed_5; +wire [`DWIDTH-1:0] a15_data_delayed_6; +wire [`DWIDTH-1:0] a15_data_delayed_7; +wire [`DWIDTH-1:0] a15_data_delayed_8; +wire [`DWIDTH-1:0] a15_data_delayed_9; +wire [`DWIDTH-1:0] a15_data_delayed_10; +wire [`DWIDTH-1:0] a15_data_delayed_11; +wire [`DWIDTH-1:0] a15_data_delayed_12; +wire [`DWIDTH-1:0] a15_data_delayed_13; +wire [`DWIDTH-1:0] a15_data_delayed_14; +wire [`DWIDTH-1:0] a15_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_1; +wire [`DWIDTH-1:0] a16_data_delayed_2; +wire [`DWIDTH-1:0] a16_data_delayed_3; +wire [`DWIDTH-1:0] a16_data_delayed_4; +wire [`DWIDTH-1:0] a16_data_delayed_5; +wire [`DWIDTH-1:0] a16_data_delayed_6; +wire [`DWIDTH-1:0] a16_data_delayed_7; +wire [`DWIDTH-1:0] a16_data_delayed_8; +wire [`DWIDTH-1:0] a16_data_delayed_9; +wire [`DWIDTH-1:0] a16_data_delayed_10; +wire [`DWIDTH-1:0] a16_data_delayed_11; +wire [`DWIDTH-1:0] a16_data_delayed_12; +wire [`DWIDTH-1:0] a16_data_delayed_13; +wire [`DWIDTH-1:0] a16_data_delayed_14; +wire [`DWIDTH-1:0] a16_data_delayed_15; +wire [`DWIDTH-1:0] a16_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_1; +wire [`DWIDTH-1:0] a17_data_delayed_2; +wire [`DWIDTH-1:0] a17_data_delayed_3; +wire [`DWIDTH-1:0] a17_data_delayed_4; +wire [`DWIDTH-1:0] a17_data_delayed_5; +wire [`DWIDTH-1:0] a17_data_delayed_6; +wire [`DWIDTH-1:0] a17_data_delayed_7; +wire [`DWIDTH-1:0] a17_data_delayed_8; +wire [`DWIDTH-1:0] a17_data_delayed_9; +wire [`DWIDTH-1:0] a17_data_delayed_10; +wire [`DWIDTH-1:0] a17_data_delayed_11; +wire [`DWIDTH-1:0] a17_data_delayed_12; +wire [`DWIDTH-1:0] a17_data_delayed_13; +wire [`DWIDTH-1:0] a17_data_delayed_14; +wire [`DWIDTH-1:0] a17_data_delayed_15; +wire [`DWIDTH-1:0] a17_data_delayed_16; +wire [`DWIDTH-1:0] a17_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_1; +wire [`DWIDTH-1:0] a18_data_delayed_2; +wire [`DWIDTH-1:0] a18_data_delayed_3; +wire [`DWIDTH-1:0] a18_data_delayed_4; +wire [`DWIDTH-1:0] a18_data_delayed_5; +wire [`DWIDTH-1:0] a18_data_delayed_6; +wire [`DWIDTH-1:0] a18_data_delayed_7; +wire [`DWIDTH-1:0] a18_data_delayed_8; +wire [`DWIDTH-1:0] a18_data_delayed_9; +wire [`DWIDTH-1:0] a18_data_delayed_10; +wire [`DWIDTH-1:0] a18_data_delayed_11; +wire [`DWIDTH-1:0] a18_data_delayed_12; +wire [`DWIDTH-1:0] a18_data_delayed_13; +wire [`DWIDTH-1:0] a18_data_delayed_14; +wire [`DWIDTH-1:0] a18_data_delayed_15; +wire [`DWIDTH-1:0] a18_data_delayed_16; +wire [`DWIDTH-1:0] a18_data_delayed_17; +wire [`DWIDTH-1:0] a18_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_1; +wire [`DWIDTH-1:0] a19_data_delayed_2; +wire [`DWIDTH-1:0] a19_data_delayed_3; +wire [`DWIDTH-1:0] a19_data_delayed_4; +wire [`DWIDTH-1:0] a19_data_delayed_5; +wire [`DWIDTH-1:0] a19_data_delayed_6; +wire [`DWIDTH-1:0] a19_data_delayed_7; +wire [`DWIDTH-1:0] a19_data_delayed_8; +wire [`DWIDTH-1:0] a19_data_delayed_9; +wire [`DWIDTH-1:0] a19_data_delayed_10; +wire [`DWIDTH-1:0] a19_data_delayed_11; +wire [`DWIDTH-1:0] a19_data_delayed_12; +wire [`DWIDTH-1:0] a19_data_delayed_13; +wire [`DWIDTH-1:0] a19_data_delayed_14; +wire [`DWIDTH-1:0] a19_data_delayed_15; +wire [`DWIDTH-1:0] a19_data_delayed_16; +wire [`DWIDTH-1:0] a19_data_delayed_17; +wire [`DWIDTH-1:0] a19_data_delayed_18; +wire [`DWIDTH-1:0] a19_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_1; +wire [`DWIDTH-1:0] a20_data_delayed_2; +wire [`DWIDTH-1:0] a20_data_delayed_3; +wire [`DWIDTH-1:0] a20_data_delayed_4; +wire [`DWIDTH-1:0] a20_data_delayed_5; +wire [`DWIDTH-1:0] a20_data_delayed_6; +wire [`DWIDTH-1:0] a20_data_delayed_7; +wire [`DWIDTH-1:0] a20_data_delayed_8; +wire [`DWIDTH-1:0] a20_data_delayed_9; +wire [`DWIDTH-1:0] a20_data_delayed_10; +wire [`DWIDTH-1:0] a20_data_delayed_11; +wire [`DWIDTH-1:0] a20_data_delayed_12; +wire [`DWIDTH-1:0] a20_data_delayed_13; +wire [`DWIDTH-1:0] a20_data_delayed_14; +wire [`DWIDTH-1:0] a20_data_delayed_15; +wire [`DWIDTH-1:0] a20_data_delayed_16; +wire [`DWIDTH-1:0] a20_data_delayed_17; +wire [`DWIDTH-1:0] a20_data_delayed_18; +wire [`DWIDTH-1:0] a20_data_delayed_19; +wire [`DWIDTH-1:0] a20_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_1; +wire [`DWIDTH-1:0] a21_data_delayed_2; +wire [`DWIDTH-1:0] a21_data_delayed_3; +wire [`DWIDTH-1:0] a21_data_delayed_4; +wire [`DWIDTH-1:0] a21_data_delayed_5; +wire [`DWIDTH-1:0] a21_data_delayed_6; +wire [`DWIDTH-1:0] a21_data_delayed_7; +wire [`DWIDTH-1:0] a21_data_delayed_8; +wire [`DWIDTH-1:0] a21_data_delayed_9; +wire [`DWIDTH-1:0] a21_data_delayed_10; +wire [`DWIDTH-1:0] a21_data_delayed_11; +wire [`DWIDTH-1:0] a21_data_delayed_12; +wire [`DWIDTH-1:0] a21_data_delayed_13; +wire [`DWIDTH-1:0] a21_data_delayed_14; +wire [`DWIDTH-1:0] a21_data_delayed_15; +wire [`DWIDTH-1:0] a21_data_delayed_16; +wire [`DWIDTH-1:0] a21_data_delayed_17; +wire [`DWIDTH-1:0] a21_data_delayed_18; +wire [`DWIDTH-1:0] a21_data_delayed_19; +wire [`DWIDTH-1:0] a21_data_delayed_20; +wire [`DWIDTH-1:0] a21_data_delayed_21; +wire [`DWIDTH-1:0] a22_data_delayed_1; +wire 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[`DWIDTH-1:0] b8_data_delayed_4; +wire [`DWIDTH-1:0] b8_data_delayed_5; +wire [`DWIDTH-1:0] b8_data_delayed_6; +wire [`DWIDTH-1:0] b8_data_delayed_7; +wire [`DWIDTH-1:0] b8_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_1; +wire [`DWIDTH-1:0] b9_data_delayed_2; +wire [`DWIDTH-1:0] b9_data_delayed_3; +wire [`DWIDTH-1:0] b9_data_delayed_4; +wire [`DWIDTH-1:0] b9_data_delayed_5; +wire [`DWIDTH-1:0] b9_data_delayed_6; +wire [`DWIDTH-1:0] b9_data_delayed_7; +wire [`DWIDTH-1:0] b9_data_delayed_8; +wire [`DWIDTH-1:0] b9_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_1; +wire [`DWIDTH-1:0] b10_data_delayed_2; +wire [`DWIDTH-1:0] b10_data_delayed_3; +wire [`DWIDTH-1:0] b10_data_delayed_4; +wire [`DWIDTH-1:0] b10_data_delayed_5; +wire [`DWIDTH-1:0] b10_data_delayed_6; +wire [`DWIDTH-1:0] b10_data_delayed_7; +wire [`DWIDTH-1:0] b10_data_delayed_8; +wire [`DWIDTH-1:0] b10_data_delayed_9; +wire [`DWIDTH-1:0] b10_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_1; +wire [`DWIDTH-1:0] b11_data_delayed_2; +wire [`DWIDTH-1:0] b11_data_delayed_3; +wire [`DWIDTH-1:0] b11_data_delayed_4; +wire [`DWIDTH-1:0] b11_data_delayed_5; +wire [`DWIDTH-1:0] b11_data_delayed_6; +wire [`DWIDTH-1:0] b11_data_delayed_7; +wire [`DWIDTH-1:0] b11_data_delayed_8; +wire [`DWIDTH-1:0] b11_data_delayed_9; +wire [`DWIDTH-1:0] b11_data_delayed_10; +wire [`DWIDTH-1:0] b11_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_1; +wire [`DWIDTH-1:0] b12_data_delayed_2; +wire [`DWIDTH-1:0] b12_data_delayed_3; +wire [`DWIDTH-1:0] b12_data_delayed_4; +wire [`DWIDTH-1:0] b12_data_delayed_5; +wire [`DWIDTH-1:0] b12_data_delayed_6; +wire [`DWIDTH-1:0] b12_data_delayed_7; +wire [`DWIDTH-1:0] b12_data_delayed_8; +wire [`DWIDTH-1:0] b12_data_delayed_9; +wire [`DWIDTH-1:0] b12_data_delayed_10; +wire [`DWIDTH-1:0] b12_data_delayed_11; +wire [`DWIDTH-1:0] b12_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_1; +wire [`DWIDTH-1:0] b13_data_delayed_2; +wire [`DWIDTH-1:0] b13_data_delayed_3; +wire [`DWIDTH-1:0] b13_data_delayed_4; +wire [`DWIDTH-1:0] b13_data_delayed_5; +wire [`DWIDTH-1:0] b13_data_delayed_6; +wire [`DWIDTH-1:0] b13_data_delayed_7; +wire [`DWIDTH-1:0] b13_data_delayed_8; +wire [`DWIDTH-1:0] b13_data_delayed_9; +wire [`DWIDTH-1:0] b13_data_delayed_10; +wire [`DWIDTH-1:0] b13_data_delayed_11; +wire [`DWIDTH-1:0] b13_data_delayed_12; +wire [`DWIDTH-1:0] b13_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_1; +wire [`DWIDTH-1:0] b14_data_delayed_2; +wire [`DWIDTH-1:0] b14_data_delayed_3; +wire [`DWIDTH-1:0] b14_data_delayed_4; +wire [`DWIDTH-1:0] b14_data_delayed_5; +wire [`DWIDTH-1:0] b14_data_delayed_6; +wire [`DWIDTH-1:0] b14_data_delayed_7; +wire [`DWIDTH-1:0] b14_data_delayed_8; +wire [`DWIDTH-1:0] b14_data_delayed_9; +wire [`DWIDTH-1:0] b14_data_delayed_10; +wire [`DWIDTH-1:0] b14_data_delayed_11; +wire [`DWIDTH-1:0] b14_data_delayed_12; +wire [`DWIDTH-1:0] b14_data_delayed_13; +wire [`DWIDTH-1:0] b14_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_1; +wire [`DWIDTH-1:0] b15_data_delayed_2; +wire [`DWIDTH-1:0] b15_data_delayed_3; +wire [`DWIDTH-1:0] b15_data_delayed_4; +wire [`DWIDTH-1:0] b15_data_delayed_5; +wire [`DWIDTH-1:0] b15_data_delayed_6; +wire [`DWIDTH-1:0] b15_data_delayed_7; +wire [`DWIDTH-1:0] b15_data_delayed_8; +wire [`DWIDTH-1:0] b15_data_delayed_9; +wire [`DWIDTH-1:0] b15_data_delayed_10; +wire [`DWIDTH-1:0] b15_data_delayed_11; +wire [`DWIDTH-1:0] b15_data_delayed_12; +wire [`DWIDTH-1:0] b15_data_delayed_13; +wire [`DWIDTH-1:0] b15_data_delayed_14; +wire [`DWIDTH-1:0] b15_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_1; +wire [`DWIDTH-1:0] b16_data_delayed_2; +wire [`DWIDTH-1:0] b16_data_delayed_3; +wire [`DWIDTH-1:0] b16_data_delayed_4; +wire [`DWIDTH-1:0] b16_data_delayed_5; +wire [`DWIDTH-1:0] b16_data_delayed_6; +wire [`DWIDTH-1:0] b16_data_delayed_7; +wire [`DWIDTH-1:0] b16_data_delayed_8; +wire [`DWIDTH-1:0] b16_data_delayed_9; +wire [`DWIDTH-1:0] b16_data_delayed_10; +wire [`DWIDTH-1:0] b16_data_delayed_11; +wire [`DWIDTH-1:0] b16_data_delayed_12; +wire [`DWIDTH-1:0] b16_data_delayed_13; +wire [`DWIDTH-1:0] b16_data_delayed_14; +wire [`DWIDTH-1:0] b16_data_delayed_15; +wire [`DWIDTH-1:0] b16_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_1; +wire [`DWIDTH-1:0] b17_data_delayed_2; +wire [`DWIDTH-1:0] b17_data_delayed_3; +wire [`DWIDTH-1:0] b17_data_delayed_4; +wire [`DWIDTH-1:0] b17_data_delayed_5; +wire [`DWIDTH-1:0] b17_data_delayed_6; +wire [`DWIDTH-1:0] b17_data_delayed_7; +wire [`DWIDTH-1:0] b17_data_delayed_8; +wire [`DWIDTH-1:0] b17_data_delayed_9; +wire [`DWIDTH-1:0] b17_data_delayed_10; +wire [`DWIDTH-1:0] b17_data_delayed_11; +wire [`DWIDTH-1:0] b17_data_delayed_12; +wire [`DWIDTH-1:0] b17_data_delayed_13; +wire [`DWIDTH-1:0] b17_data_delayed_14; +wire [`DWIDTH-1:0] b17_data_delayed_15; +wire [`DWIDTH-1:0] b17_data_delayed_16; +wire [`DWIDTH-1:0] b17_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_1; +wire [`DWIDTH-1:0] b18_data_delayed_2; +wire [`DWIDTH-1:0] b18_data_delayed_3; +wire [`DWIDTH-1:0] b18_data_delayed_4; +wire [`DWIDTH-1:0] b18_data_delayed_5; +wire [`DWIDTH-1:0] b18_data_delayed_6; +wire [`DWIDTH-1:0] b18_data_delayed_7; +wire [`DWIDTH-1:0] b18_data_delayed_8; +wire [`DWIDTH-1:0] b18_data_delayed_9; +wire [`DWIDTH-1:0] b18_data_delayed_10; +wire [`DWIDTH-1:0] b18_data_delayed_11; +wire [`DWIDTH-1:0] b18_data_delayed_12; +wire [`DWIDTH-1:0] b18_data_delayed_13; +wire [`DWIDTH-1:0] b18_data_delayed_14; +wire [`DWIDTH-1:0] b18_data_delayed_15; +wire [`DWIDTH-1:0] b18_data_delayed_16; +wire [`DWIDTH-1:0] b18_data_delayed_17; +wire [`DWIDTH-1:0] b18_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_1; +wire [`DWIDTH-1:0] b19_data_delayed_2; +wire [`DWIDTH-1:0] b19_data_delayed_3; +wire [`DWIDTH-1:0] b19_data_delayed_4; +wire [`DWIDTH-1:0] b19_data_delayed_5; +wire [`DWIDTH-1:0] b19_data_delayed_6; +wire [`DWIDTH-1:0] b19_data_delayed_7; +wire [`DWIDTH-1:0] b19_data_delayed_8; +wire [`DWIDTH-1:0] b19_data_delayed_9; +wire [`DWIDTH-1:0] b19_data_delayed_10; +wire [`DWIDTH-1:0] b19_data_delayed_11; +wire [`DWIDTH-1:0] b19_data_delayed_12; +wire [`DWIDTH-1:0] b19_data_delayed_13; +wire [`DWIDTH-1:0] b19_data_delayed_14; +wire [`DWIDTH-1:0] b19_data_delayed_15; +wire [`DWIDTH-1:0] b19_data_delayed_16; +wire [`DWIDTH-1:0] b19_data_delayed_17; +wire [`DWIDTH-1:0] b19_data_delayed_18; +wire [`DWIDTH-1:0] b19_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_1; +wire [`DWIDTH-1:0] b20_data_delayed_2; +wire [`DWIDTH-1:0] b20_data_delayed_3; +wire [`DWIDTH-1:0] b20_data_delayed_4; +wire [`DWIDTH-1:0] b20_data_delayed_5; +wire [`DWIDTH-1:0] b20_data_delayed_6; +wire [`DWIDTH-1:0] b20_data_delayed_7; +wire [`DWIDTH-1:0] b20_data_delayed_8; +wire [`DWIDTH-1:0] b20_data_delayed_9; +wire [`DWIDTH-1:0] b20_data_delayed_10; +wire [`DWIDTH-1:0] b20_data_delayed_11; +wire [`DWIDTH-1:0] b20_data_delayed_12; +wire [`DWIDTH-1:0] b20_data_delayed_13; +wire [`DWIDTH-1:0] b20_data_delayed_14; +wire [`DWIDTH-1:0] b20_data_delayed_15; +wire [`DWIDTH-1:0] b20_data_delayed_16; +wire [`DWIDTH-1:0] b20_data_delayed_17; +wire [`DWIDTH-1:0] b20_data_delayed_18; +wire [`DWIDTH-1:0] b20_data_delayed_19; +wire [`DWIDTH-1:0] b20_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_1; +wire [`DWIDTH-1:0] b21_data_delayed_2; +wire [`DWIDTH-1:0] b21_data_delayed_3; +wire [`DWIDTH-1:0] b21_data_delayed_4; +wire [`DWIDTH-1:0] b21_data_delayed_5; +wire [`DWIDTH-1:0] b21_data_delayed_6; +wire [`DWIDTH-1:0] b21_data_delayed_7; +wire [`DWIDTH-1:0] b21_data_delayed_8; +wire [`DWIDTH-1:0] b21_data_delayed_9; +wire [`DWIDTH-1:0] b21_data_delayed_10; +wire [`DWIDTH-1:0] b21_data_delayed_11; +wire [`DWIDTH-1:0] b21_data_delayed_12; +wire [`DWIDTH-1:0] b21_data_delayed_13; +wire [`DWIDTH-1:0] b21_data_delayed_14; +wire [`DWIDTH-1:0] b21_data_delayed_15; +wire [`DWIDTH-1:0] b21_data_delayed_16; +wire [`DWIDTH-1:0] b21_data_delayed_17; +wire [`DWIDTH-1:0] b21_data_delayed_18; +wire [`DWIDTH-1:0] b21_data_delayed_19; +wire [`DWIDTH-1:0] b21_data_delayed_20; +wire [`DWIDTH-1:0] b21_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_1; +wire [`DWIDTH-1:0] b22_data_delayed_2; +wire [`DWIDTH-1:0] b22_data_delayed_3; +wire [`DWIDTH-1:0] b22_data_delayed_4; +wire [`DWIDTH-1:0] b22_data_delayed_5; +wire [`DWIDTH-1:0] b22_data_delayed_6; +wire [`DWIDTH-1:0] b22_data_delayed_7; +wire [`DWIDTH-1:0] b22_data_delayed_8; +wire [`DWIDTH-1:0] b22_data_delayed_9; +wire [`DWIDTH-1:0] b22_data_delayed_10; +wire [`DWIDTH-1:0] b22_data_delayed_11; +wire [`DWIDTH-1:0] b22_data_delayed_12; +wire [`DWIDTH-1:0] b22_data_delayed_13; +wire [`DWIDTH-1:0] b22_data_delayed_14; +wire [`DWIDTH-1:0] b22_data_delayed_15; +wire [`DWIDTH-1:0] b22_data_delayed_16; +wire [`DWIDTH-1:0] b22_data_delayed_17; +wire [`DWIDTH-1:0] b22_data_delayed_18; +wire [`DWIDTH-1:0] b22_data_delayed_19; +wire [`DWIDTH-1:0] b22_data_delayed_20; +wire [`DWIDTH-1:0] b22_data_delayed_21; +wire [`DWIDTH-1:0] b22_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_1; +wire [`DWIDTH-1:0] b23_data_delayed_2; +wire [`DWIDTH-1:0] b23_data_delayed_3; +wire [`DWIDTH-1:0] b23_data_delayed_4; +wire [`DWIDTH-1:0] b23_data_delayed_5; +wire [`DWIDTH-1:0] b23_data_delayed_6; +wire [`DWIDTH-1:0] b23_data_delayed_7; +wire [`DWIDTH-1:0] b23_data_delayed_8; +wire [`DWIDTH-1:0] b23_data_delayed_9; +wire [`DWIDTH-1:0] b23_data_delayed_10; +wire [`DWIDTH-1:0] b23_data_delayed_11; +wire [`DWIDTH-1:0] b23_data_delayed_12; +wire [`DWIDTH-1:0] b23_data_delayed_13; +wire [`DWIDTH-1:0] b23_data_delayed_14; +wire [`DWIDTH-1:0] b23_data_delayed_15; +wire [`DWIDTH-1:0] b23_data_delayed_16; +wire [`DWIDTH-1:0] b23_data_delayed_17; +wire [`DWIDTH-1:0] b23_data_delayed_18; +wire [`DWIDTH-1:0] b23_data_delayed_19; +wire [`DWIDTH-1:0] b23_data_delayed_20; +wire [`DWIDTH-1:0] b23_data_delayed_21; +wire [`DWIDTH-1:0] b23_data_delayed_22; +wire [`DWIDTH-1:0] b23_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_1; +wire [`DWIDTH-1:0] b24_data_delayed_2; +wire [`DWIDTH-1:0] b24_data_delayed_3; +wire [`DWIDTH-1:0] b24_data_delayed_4; +wire [`DWIDTH-1:0] b24_data_delayed_5; +wire [`DWIDTH-1:0] b24_data_delayed_6; +wire [`DWIDTH-1:0] b24_data_delayed_7; +wire [`DWIDTH-1:0] b24_data_delayed_8; +wire [`DWIDTH-1:0] b24_data_delayed_9; +wire [`DWIDTH-1:0] b24_data_delayed_10; +wire [`DWIDTH-1:0] b24_data_delayed_11; +wire [`DWIDTH-1:0] b24_data_delayed_12; +wire [`DWIDTH-1:0] b24_data_delayed_13; +wire [`DWIDTH-1:0] b24_data_delayed_14; +wire [`DWIDTH-1:0] b24_data_delayed_15; +wire [`DWIDTH-1:0] b24_data_delayed_16; +wire [`DWIDTH-1:0] b24_data_delayed_17; +wire [`DWIDTH-1:0] b24_data_delayed_18; +wire [`DWIDTH-1:0] b24_data_delayed_19; +wire [`DWIDTH-1:0] b24_data_delayed_20; +wire [`DWIDTH-1:0] b24_data_delayed_21; +wire [`DWIDTH-1:0] b24_data_delayed_22; +wire [`DWIDTH-1:0] b24_data_delayed_23; +wire [`DWIDTH-1:0] b24_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_1; +wire [`DWIDTH-1:0] b25_data_delayed_2; +wire [`DWIDTH-1:0] b25_data_delayed_3; +wire [`DWIDTH-1:0] b25_data_delayed_4; +wire [`DWIDTH-1:0] b25_data_delayed_5; +wire [`DWIDTH-1:0] b25_data_delayed_6; +wire [`DWIDTH-1:0] b25_data_delayed_7; +wire [`DWIDTH-1:0] b25_data_delayed_8; +wire [`DWIDTH-1:0] b25_data_delayed_9; +wire [`DWIDTH-1:0] b25_data_delayed_10; +wire [`DWIDTH-1:0] b25_data_delayed_11; +wire [`DWIDTH-1:0] b25_data_delayed_12; +wire [`DWIDTH-1:0] b25_data_delayed_13; +wire [`DWIDTH-1:0] b25_data_delayed_14; +wire [`DWIDTH-1:0] b25_data_delayed_15; +wire [`DWIDTH-1:0] b25_data_delayed_16; +wire [`DWIDTH-1:0] b25_data_delayed_17; +wire [`DWIDTH-1:0] b25_data_delayed_18; +wire [`DWIDTH-1:0] b25_data_delayed_19; +wire [`DWIDTH-1:0] b25_data_delayed_20; +wire [`DWIDTH-1:0] b25_data_delayed_21; +wire [`DWIDTH-1:0] b25_data_delayed_22; +wire [`DWIDTH-1:0] b25_data_delayed_23; +wire [`DWIDTH-1:0] b25_data_delayed_24; +wire [`DWIDTH-1:0] b25_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_1; +wire [`DWIDTH-1:0] b26_data_delayed_2; +wire [`DWIDTH-1:0] b26_data_delayed_3; +wire [`DWIDTH-1:0] b26_data_delayed_4; +wire [`DWIDTH-1:0] b26_data_delayed_5; +wire [`DWIDTH-1:0] b26_data_delayed_6; +wire [`DWIDTH-1:0] b26_data_delayed_7; +wire [`DWIDTH-1:0] b26_data_delayed_8; +wire [`DWIDTH-1:0] b26_data_delayed_9; +wire [`DWIDTH-1:0] b26_data_delayed_10; +wire [`DWIDTH-1:0] b26_data_delayed_11; +wire [`DWIDTH-1:0] b26_data_delayed_12; +wire [`DWIDTH-1:0] b26_data_delayed_13; +wire [`DWIDTH-1:0] b26_data_delayed_14; +wire [`DWIDTH-1:0] b26_data_delayed_15; +wire [`DWIDTH-1:0] b26_data_delayed_16; +wire [`DWIDTH-1:0] b26_data_delayed_17; +wire [`DWIDTH-1:0] b26_data_delayed_18; +wire [`DWIDTH-1:0] b26_data_delayed_19; +wire [`DWIDTH-1:0] b26_data_delayed_20; +wire [`DWIDTH-1:0] b26_data_delayed_21; +wire [`DWIDTH-1:0] b26_data_delayed_22; +wire [`DWIDTH-1:0] b26_data_delayed_23; +wire [`DWIDTH-1:0] b26_data_delayed_24; +wire [`DWIDTH-1:0] b26_data_delayed_25; +wire [`DWIDTH-1:0] b26_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_1; +wire [`DWIDTH-1:0] b27_data_delayed_2; +wire [`DWIDTH-1:0] b27_data_delayed_3; +wire [`DWIDTH-1:0] b27_data_delayed_4; +wire [`DWIDTH-1:0] b27_data_delayed_5; +wire [`DWIDTH-1:0] b27_data_delayed_6; +wire [`DWIDTH-1:0] b27_data_delayed_7; +wire [`DWIDTH-1:0] b27_data_delayed_8; +wire [`DWIDTH-1:0] b27_data_delayed_9; +wire [`DWIDTH-1:0] b27_data_delayed_10; +wire [`DWIDTH-1:0] b27_data_delayed_11; +wire [`DWIDTH-1:0] b27_data_delayed_12; +wire [`DWIDTH-1:0] b27_data_delayed_13; +wire [`DWIDTH-1:0] b27_data_delayed_14; +wire [`DWIDTH-1:0] b27_data_delayed_15; +wire [`DWIDTH-1:0] b27_data_delayed_16; +wire [`DWIDTH-1:0] b27_data_delayed_17; +wire [`DWIDTH-1:0] b27_data_delayed_18; +wire [`DWIDTH-1:0] b27_data_delayed_19; +wire [`DWIDTH-1:0] b27_data_delayed_20; +wire [`DWIDTH-1:0] b27_data_delayed_21; +wire [`DWIDTH-1:0] b27_data_delayed_22; +wire [`DWIDTH-1:0] b27_data_delayed_23; +wire [`DWIDTH-1:0] b27_data_delayed_24; +wire [`DWIDTH-1:0] b27_data_delayed_25; +wire [`DWIDTH-1:0] b27_data_delayed_26; +wire [`DWIDTH-1:0] b27_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_1; +wire [`DWIDTH-1:0] b28_data_delayed_2; +wire [`DWIDTH-1:0] b28_data_delayed_3; +wire [`DWIDTH-1:0] b28_data_delayed_4; +wire [`DWIDTH-1:0] b28_data_delayed_5; +wire [`DWIDTH-1:0] b28_data_delayed_6; +wire [`DWIDTH-1:0] b28_data_delayed_7; +wire [`DWIDTH-1:0] b28_data_delayed_8; +wire [`DWIDTH-1:0] b28_data_delayed_9; +wire [`DWIDTH-1:0] b28_data_delayed_10; +wire [`DWIDTH-1:0] b28_data_delayed_11; +wire [`DWIDTH-1:0] b28_data_delayed_12; +wire [`DWIDTH-1:0] b28_data_delayed_13; +wire [`DWIDTH-1:0] b28_data_delayed_14; +wire [`DWIDTH-1:0] b28_data_delayed_15; +wire [`DWIDTH-1:0] b28_data_delayed_16; +wire [`DWIDTH-1:0] b28_data_delayed_17; +wire [`DWIDTH-1:0] b28_data_delayed_18; +wire [`DWIDTH-1:0] b28_data_delayed_19; +wire [`DWIDTH-1:0] b28_data_delayed_20; +wire [`DWIDTH-1:0] b28_data_delayed_21; +wire [`DWIDTH-1:0] b28_data_delayed_22; +wire [`DWIDTH-1:0] b28_data_delayed_23; +wire [`DWIDTH-1:0] b28_data_delayed_24; +wire [`DWIDTH-1:0] b28_data_delayed_25; +wire [`DWIDTH-1:0] b28_data_delayed_26; +wire [`DWIDTH-1:0] b28_data_delayed_27; +wire [`DWIDTH-1:0] b28_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_1; +wire [`DWIDTH-1:0] b29_data_delayed_2; +wire [`DWIDTH-1:0] b29_data_delayed_3; +wire [`DWIDTH-1:0] b29_data_delayed_4; +wire [`DWIDTH-1:0] b29_data_delayed_5; +wire [`DWIDTH-1:0] b29_data_delayed_6; +wire [`DWIDTH-1:0] b29_data_delayed_7; +wire [`DWIDTH-1:0] b29_data_delayed_8; +wire [`DWIDTH-1:0] b29_data_delayed_9; +wire [`DWIDTH-1:0] b29_data_delayed_10; +wire [`DWIDTH-1:0] b29_data_delayed_11; +wire [`DWIDTH-1:0] b29_data_delayed_12; +wire [`DWIDTH-1:0] b29_data_delayed_13; +wire [`DWIDTH-1:0] b29_data_delayed_14; +wire [`DWIDTH-1:0] b29_data_delayed_15; +wire [`DWIDTH-1:0] b29_data_delayed_16; +wire [`DWIDTH-1:0] b29_data_delayed_17; +wire [`DWIDTH-1:0] b29_data_delayed_18; +wire [`DWIDTH-1:0] b29_data_delayed_19; +wire [`DWIDTH-1:0] b29_data_delayed_20; +wire [`DWIDTH-1:0] b29_data_delayed_21; +wire [`DWIDTH-1:0] b29_data_delayed_22; +wire [`DWIDTH-1:0] b29_data_delayed_23; +wire [`DWIDTH-1:0] b29_data_delayed_24; +wire [`DWIDTH-1:0] b29_data_delayed_25; +wire [`DWIDTH-1:0] b29_data_delayed_26; +wire [`DWIDTH-1:0] b29_data_delayed_27; +wire [`DWIDTH-1:0] b29_data_delayed_28; +wire [`DWIDTH-1:0] b29_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_1; +wire [`DWIDTH-1:0] b30_data_delayed_2; +wire [`DWIDTH-1:0] b30_data_delayed_3; +wire [`DWIDTH-1:0] b30_data_delayed_4; +wire [`DWIDTH-1:0] b30_data_delayed_5; +wire [`DWIDTH-1:0] b30_data_delayed_6; +wire [`DWIDTH-1:0] b30_data_delayed_7; +wire [`DWIDTH-1:0] b30_data_delayed_8; +wire [`DWIDTH-1:0] b30_data_delayed_9; +wire [`DWIDTH-1:0] b30_data_delayed_10; +wire [`DWIDTH-1:0] b30_data_delayed_11; +wire [`DWIDTH-1:0] b30_data_delayed_12; +wire [`DWIDTH-1:0] b30_data_delayed_13; +wire [`DWIDTH-1:0] b30_data_delayed_14; +wire [`DWIDTH-1:0] b30_data_delayed_15; +wire [`DWIDTH-1:0] b30_data_delayed_16; +wire [`DWIDTH-1:0] b30_data_delayed_17; +wire [`DWIDTH-1:0] b30_data_delayed_18; +wire [`DWIDTH-1:0] b30_data_delayed_19; +wire [`DWIDTH-1:0] b30_data_delayed_20; +wire [`DWIDTH-1:0] b30_data_delayed_21; +wire [`DWIDTH-1:0] b30_data_delayed_22; +wire [`DWIDTH-1:0] b30_data_delayed_23; +wire [`DWIDTH-1:0] b30_data_delayed_24; +wire [`DWIDTH-1:0] b30_data_delayed_25; +wire [`DWIDTH-1:0] b30_data_delayed_26; +wire [`DWIDTH-1:0] b30_data_delayed_27; +wire [`DWIDTH-1:0] b30_data_delayed_28; +wire [`DWIDTH-1:0] b30_data_delayed_29; +wire [`DWIDTH-1:0] b30_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_1; +wire [`DWIDTH-1:0] b31_data_delayed_2; +wire [`DWIDTH-1:0] b31_data_delayed_3; +wire [`DWIDTH-1:0] b31_data_delayed_4; +wire [`DWIDTH-1:0] b31_data_delayed_5; +wire [`DWIDTH-1:0] b31_data_delayed_6; +wire [`DWIDTH-1:0] b31_data_delayed_7; +wire [`DWIDTH-1:0] b31_data_delayed_8; +wire [`DWIDTH-1:0] b31_data_delayed_9; +wire [`DWIDTH-1:0] b31_data_delayed_10; +wire [`DWIDTH-1:0] b31_data_delayed_11; +wire [`DWIDTH-1:0] b31_data_delayed_12; +wire [`DWIDTH-1:0] b31_data_delayed_13; +wire [`DWIDTH-1:0] b31_data_delayed_14; +wire [`DWIDTH-1:0] b31_data_delayed_15; +wire [`DWIDTH-1:0] b31_data_delayed_16; +wire [`DWIDTH-1:0] b31_data_delayed_17; +wire [`DWIDTH-1:0] b31_data_delayed_18; +wire [`DWIDTH-1:0] b31_data_delayed_19; +wire [`DWIDTH-1:0] b31_data_delayed_20; +wire [`DWIDTH-1:0] b31_data_delayed_21; +wire [`DWIDTH-1:0] b31_data_delayed_22; +wire [`DWIDTH-1:0] b31_data_delayed_23; +wire [`DWIDTH-1:0] b31_data_delayed_24; +wire [`DWIDTH-1:0] b31_data_delayed_25; +wire [`DWIDTH-1:0] b31_data_delayed_26; +wire [`DWIDTH-1:0] b31_data_delayed_27; +wire [`DWIDTH-1:0] b31_data_delayed_28; +wire [`DWIDTH-1:0] b31_data_delayed_29; +wire [`DWIDTH-1:0] b31_data_delayed_30; +wire [`DWIDTH-1:0] b31_data_delayed_31; + + +////////////////////////////////////////////////////////////////////////// +// Instantiation of systolic data setup +////////////////////////////////////////////////////////////////////////// +systolic_data_setup u_systolic_data_setup( +.clk(clk), +.reset(reset), +.start_mat_mul(start_mat_mul), +.a_addr(a_addr), +.b_addr(b_addr), +.address_mat_a(address_mat_a), +.address_mat_b(address_mat_b), +.address_stride_a(address_stride_a), +.address_stride_b(address_stride_b), +.a_data(a_data), +.b_data(b_data), +.clk_cnt(clk_cnt), +.a0_data(a0_data), +.b0_data(b0_data), +.a1_data_delayed_1(a1_data_delayed_1), +.b1_data_delayed_1(b1_data_delayed_1), +.a2_data_delayed_2(a2_data_delayed_2), +.b2_data_delayed_2(b2_data_delayed_2), +.a3_data_delayed_3(a3_data_delayed_3), +.b3_data_delayed_3(b3_data_delayed_3), +.a4_data_delayed_4(a4_data_delayed_4), +.b4_data_delayed_4(b4_data_delayed_4), +.a5_data_delayed_5(a5_data_delayed_5), +.b5_data_delayed_5(b5_data_delayed_5), +.a6_data_delayed_6(a6_data_delayed_6), +.b6_data_delayed_6(b6_data_delayed_6), +.a7_data_delayed_7(a7_data_delayed_7), +.b7_data_delayed_7(b7_data_delayed_7), +.a8_data_delayed_8(a8_data_delayed_8), +.b8_data_delayed_8(b8_data_delayed_8), +.a9_data_delayed_9(a9_data_delayed_9), +.b9_data_delayed_9(b9_data_delayed_9), +.a10_data_delayed_10(a10_data_delayed_10), +.b10_data_delayed_10(b10_data_delayed_10), +.a11_data_delayed_11(a11_data_delayed_11), +.b11_data_delayed_11(b11_data_delayed_11), +.a12_data_delayed_12(a12_data_delayed_12), +.b12_data_delayed_12(b12_data_delayed_12), +.a13_data_delayed_13(a13_data_delayed_13), +.b13_data_delayed_13(b13_data_delayed_13), +.a14_data_delayed_14(a14_data_delayed_14), +.b14_data_delayed_14(b14_data_delayed_14), +.a15_data_delayed_15(a15_data_delayed_15), +.b15_data_delayed_15(b15_data_delayed_15), +.a16_data_delayed_16(a16_data_delayed_16), +.b16_data_delayed_16(b16_data_delayed_16), +.a17_data_delayed_17(a17_data_delayed_17), +.b17_data_delayed_17(b17_data_delayed_17), +.a18_data_delayed_18(a18_data_delayed_18), +.b18_data_delayed_18(b18_data_delayed_18), +.a19_data_delayed_19(a19_data_delayed_19), +.b19_data_delayed_19(b19_data_delayed_19), +.a20_data_delayed_20(a20_data_delayed_20), +.b20_data_delayed_20(b20_data_delayed_20), +.a21_data_delayed_21(a21_data_delayed_21), +.b21_data_delayed_21(b21_data_delayed_21), +.a22_data_delayed_22(a22_data_delayed_22), +.b22_data_delayed_22(b22_data_delayed_22), +.a23_data_delayed_23(a23_data_delayed_23), +.b23_data_delayed_23(b23_data_delayed_23), +.a24_data_delayed_24(a24_data_delayed_24), +.b24_data_delayed_24(b24_data_delayed_24), +.a25_data_delayed_25(a25_data_delayed_25), +.b25_data_delayed_25(b25_data_delayed_25), +.a26_data_delayed_26(a26_data_delayed_26), +.b26_data_delayed_26(b26_data_delayed_26), +.a27_data_delayed_27(a27_data_delayed_27), +.b27_data_delayed_27(b27_data_delayed_27), +.a28_data_delayed_28(a28_data_delayed_28), +.b28_data_delayed_28(b28_data_delayed_28), +.a29_data_delayed_29(a29_data_delayed_29), +.b29_data_delayed_29(b29_data_delayed_29), +.a30_data_delayed_30(a30_data_delayed_30), +.b30_data_delayed_30(b30_data_delayed_30), +.a31_data_delayed_31(a31_data_delayed_31), +.b31_data_delayed_31(b31_data_delayed_31), + +.validity_mask_a_rows(validity_mask_a_rows), +.validity_mask_a_cols(validity_mask_a_cols), +.validity_mask_b_rows(validity_mask_b_rows), +.validity_mask_b_cols(validity_mask_b_cols), + +.final_mat_mul_size(final_mat_mul_size), + +.a_loc(a_loc), +.b_loc(b_loc) +); + +////////////////////////////////////////////////////////////////////////// +// Logic to mux data_in coming from neighboring matmuls +////////////////////////////////////////////////////////////////////////// +wire [`DWIDTH-1:0] a0; +wire [`DWIDTH-1:0] a1; +wire [`DWIDTH-1:0] a2; +wire [`DWIDTH-1:0] a3; +wire [`DWIDTH-1:0] a4; +wire [`DWIDTH-1:0] a5; +wire [`DWIDTH-1:0] a6; +wire [`DWIDTH-1:0] a7; +wire [`DWIDTH-1:0] a8; +wire [`DWIDTH-1:0] a9; +wire [`DWIDTH-1:0] a10; +wire [`DWIDTH-1:0] a11; +wire [`DWIDTH-1:0] a12; +wire [`DWIDTH-1:0] a13; +wire [`DWIDTH-1:0] a14; +wire [`DWIDTH-1:0] a15; +wire [`DWIDTH-1:0] a16; +wire [`DWIDTH-1:0] a17; +wire [`DWIDTH-1:0] a18; +wire [`DWIDTH-1:0] a19; +wire [`DWIDTH-1:0] a20; +wire [`DWIDTH-1:0] a21; +wire [`DWIDTH-1:0] a22; +wire [`DWIDTH-1:0] a23; +wire [`DWIDTH-1:0] a24; +wire [`DWIDTH-1:0] a25; +wire [`DWIDTH-1:0] a26; +wire [`DWIDTH-1:0] a27; +wire [`DWIDTH-1:0] a28; +wire [`DWIDTH-1:0] a29; +wire [`DWIDTH-1:0] a30; +wire [`DWIDTH-1:0] a31; +wire [`DWIDTH-1:0] b0; +wire [`DWIDTH-1:0] b1; +wire [`DWIDTH-1:0] b2; +wire [`DWIDTH-1:0] b3; +wire [`DWIDTH-1:0] b4; +wire [`DWIDTH-1:0] b5; +wire [`DWIDTH-1:0] b6; +wire [`DWIDTH-1:0] b7; +wire [`DWIDTH-1:0] b8; +wire [`DWIDTH-1:0] b9; +wire [`DWIDTH-1:0] b10; +wire [`DWIDTH-1:0] b11; +wire [`DWIDTH-1:0] b12; +wire [`DWIDTH-1:0] b13; +wire [`DWIDTH-1:0] b14; +wire [`DWIDTH-1:0] b15; +wire [`DWIDTH-1:0] b16; +wire [`DWIDTH-1:0] b17; +wire [`DWIDTH-1:0] b18; +wire [`DWIDTH-1:0] b19; +wire [`DWIDTH-1:0] b20; +wire [`DWIDTH-1:0] b21; +wire [`DWIDTH-1:0] b22; +wire [`DWIDTH-1:0] b23; +wire [`DWIDTH-1:0] b24; +wire [`DWIDTH-1:0] b25; +wire [`DWIDTH-1:0] b26; +wire [`DWIDTH-1:0] b27; +wire [`DWIDTH-1:0] b28; +wire [`DWIDTH-1:0] b29; +wire [`DWIDTH-1:0] b30; +wire [`DWIDTH-1:0] b31; + +wire [`DWIDTH-1:0] a0_data_in; +wire [`DWIDTH-1:0] a1_data_in; +wire [`DWIDTH-1:0] a2_data_in; +wire [`DWIDTH-1:0] a3_data_in; +wire [`DWIDTH-1:0] a4_data_in; +wire [`DWIDTH-1:0] a5_data_in; +wire [`DWIDTH-1:0] a6_data_in; +wire [`DWIDTH-1:0] a7_data_in; +wire [`DWIDTH-1:0] a8_data_in; +wire [`DWIDTH-1:0] a9_data_in; +wire [`DWIDTH-1:0] a10_data_in; +wire [`DWIDTH-1:0] a11_data_in; +wire [`DWIDTH-1:0] a12_data_in; +wire [`DWIDTH-1:0] a13_data_in; +wire [`DWIDTH-1:0] a14_data_in; +wire [`DWIDTH-1:0] a15_data_in; +wire [`DWIDTH-1:0] a16_data_in; +wire [`DWIDTH-1:0] a17_data_in; +wire [`DWIDTH-1:0] a18_data_in; +wire [`DWIDTH-1:0] a19_data_in; +wire [`DWIDTH-1:0] a20_data_in; +wire [`DWIDTH-1:0] a21_data_in; +wire [`DWIDTH-1:0] a22_data_in; +wire [`DWIDTH-1:0] a23_data_in; +wire [`DWIDTH-1:0] a24_data_in; +wire [`DWIDTH-1:0] a25_data_in; +wire [`DWIDTH-1:0] a26_data_in; +wire [`DWIDTH-1:0] a27_data_in; +wire [`DWIDTH-1:0] a28_data_in; +wire [`DWIDTH-1:0] a29_data_in; +wire [`DWIDTH-1:0] a30_data_in; +wire [`DWIDTH-1:0] a31_data_in; + +assign a0_data_in = a_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign a1_data_in = a_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign a2_data_in = a_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign a3_data_in = a_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign a4_data_in = a_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign a5_data_in = a_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign a6_data_in = a_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign a7_data_in = a_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign a8_data_in = a_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign a9_data_in = a_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign a10_data_in = a_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign a11_data_in = a_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign a12_data_in = a_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign a13_data_in = a_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign a14_data_in = a_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign a15_data_in = a_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign a16_data_in = a_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign a17_data_in = a_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign a18_data_in = a_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign a19_data_in = a_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign a20_data_in = a_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign a21_data_in = a_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign a22_data_in = a_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign a23_data_in = a_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign a24_data_in = a_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign a25_data_in = a_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign a26_data_in = a_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign a27_data_in = a_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign a28_data_in = a_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign a29_data_in = a_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign a30_data_in = a_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign a31_data_in = a_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +wire [`DWIDTH-1:0] b0_data_in; +wire [`DWIDTH-1:0] b1_data_in; +wire [`DWIDTH-1:0] b2_data_in; +wire [`DWIDTH-1:0] b3_data_in; +wire [`DWIDTH-1:0] b4_data_in; +wire [`DWIDTH-1:0] b5_data_in; +wire [`DWIDTH-1:0] b6_data_in; +wire [`DWIDTH-1:0] b7_data_in; +wire [`DWIDTH-1:0] b8_data_in; +wire [`DWIDTH-1:0] b9_data_in; +wire [`DWIDTH-1:0] b10_data_in; +wire [`DWIDTH-1:0] b11_data_in; +wire [`DWIDTH-1:0] b12_data_in; +wire [`DWIDTH-1:0] b13_data_in; +wire [`DWIDTH-1:0] b14_data_in; +wire [`DWIDTH-1:0] b15_data_in; +wire [`DWIDTH-1:0] b16_data_in; +wire [`DWIDTH-1:0] b17_data_in; +wire [`DWIDTH-1:0] b18_data_in; +wire [`DWIDTH-1:0] b19_data_in; +wire [`DWIDTH-1:0] b20_data_in; +wire [`DWIDTH-1:0] b21_data_in; +wire [`DWIDTH-1:0] b22_data_in; +wire [`DWIDTH-1:0] b23_data_in; +wire [`DWIDTH-1:0] b24_data_in; +wire [`DWIDTH-1:0] b25_data_in; +wire [`DWIDTH-1:0] b26_data_in; +wire [`DWIDTH-1:0] b27_data_in; +wire [`DWIDTH-1:0] b28_data_in; +wire [`DWIDTH-1:0] b29_data_in; +wire [`DWIDTH-1:0] b30_data_in; +wire [`DWIDTH-1:0] b31_data_in; + +assign b0_data_in = b_data_in[1*`DWIDTH-1:0*`DWIDTH]; +assign b1_data_in = b_data_in[2*`DWIDTH-1:1*`DWIDTH]; +assign b2_data_in = b_data_in[3*`DWIDTH-1:2*`DWIDTH]; +assign b3_data_in = b_data_in[4*`DWIDTH-1:3*`DWIDTH]; +assign b4_data_in = b_data_in[5*`DWIDTH-1:4*`DWIDTH]; +assign b5_data_in = b_data_in[6*`DWIDTH-1:5*`DWIDTH]; +assign b6_data_in = b_data_in[7*`DWIDTH-1:6*`DWIDTH]; +assign b7_data_in = b_data_in[8*`DWIDTH-1:7*`DWIDTH]; +assign b8_data_in = b_data_in[9*`DWIDTH-1:8*`DWIDTH]; +assign b9_data_in = b_data_in[10*`DWIDTH-1:9*`DWIDTH]; +assign b10_data_in = b_data_in[11*`DWIDTH-1:10*`DWIDTH]; +assign b11_data_in = b_data_in[12*`DWIDTH-1:11*`DWIDTH]; +assign b12_data_in = b_data_in[13*`DWIDTH-1:12*`DWIDTH]; +assign b13_data_in = b_data_in[14*`DWIDTH-1:13*`DWIDTH]; +assign b14_data_in = b_data_in[15*`DWIDTH-1:14*`DWIDTH]; +assign b15_data_in = b_data_in[16*`DWIDTH-1:15*`DWIDTH]; +assign b16_data_in = b_data_in[17*`DWIDTH-1:16*`DWIDTH]; +assign b17_data_in = b_data_in[18*`DWIDTH-1:17*`DWIDTH]; +assign b18_data_in = b_data_in[19*`DWIDTH-1:18*`DWIDTH]; +assign b19_data_in = b_data_in[20*`DWIDTH-1:19*`DWIDTH]; +assign b20_data_in = b_data_in[21*`DWIDTH-1:20*`DWIDTH]; +assign b21_data_in = b_data_in[22*`DWIDTH-1:21*`DWIDTH]; +assign b22_data_in = b_data_in[23*`DWIDTH-1:22*`DWIDTH]; +assign b23_data_in = b_data_in[24*`DWIDTH-1:23*`DWIDTH]; +assign b24_data_in = b_data_in[25*`DWIDTH-1:24*`DWIDTH]; +assign b25_data_in = b_data_in[26*`DWIDTH-1:25*`DWIDTH]; +assign b26_data_in = b_data_in[27*`DWIDTH-1:26*`DWIDTH]; +assign b27_data_in = b_data_in[28*`DWIDTH-1:27*`DWIDTH]; +assign b28_data_in = b_data_in[29*`DWIDTH-1:28*`DWIDTH]; +assign b29_data_in = b_data_in[30*`DWIDTH-1:29*`DWIDTH]; +assign b30_data_in = b_data_in[31*`DWIDTH-1:30*`DWIDTH]; +assign b31_data_in = b_data_in[32*`DWIDTH-1:31*`DWIDTH]; + +assign a0 = (b_loc==0) ? a0_data : a0_data_in; +assign a1 = (b_loc==0) ? a1_data_delayed_1 : a1_data_in; +assign a2 = (b_loc==0) ? a2_data_delayed_2 : a2_data_in; +assign a3 = (b_loc==0) ? a3_data_delayed_3 : a3_data_in; +assign a4 = (b_loc==0) ? a4_data_delayed_4 : a4_data_in; +assign a5 = (b_loc==0) ? a5_data_delayed_5 : a5_data_in; +assign a6 = (b_loc==0) ? a6_data_delayed_6 : a6_data_in; +assign a7 = (b_loc==0) ? a7_data_delayed_7 : a7_data_in; +assign a8 = (b_loc==0) ? a8_data_delayed_8 : a8_data_in; +assign a9 = (b_loc==0) ? a9_data_delayed_9 : a9_data_in; +assign a10 = (b_loc==0) ? a10_data_delayed_10 : a10_data_in; +assign a11 = (b_loc==0) ? a11_data_delayed_11 : a11_data_in; +assign a12 = (b_loc==0) ? a12_data_delayed_12 : a12_data_in; +assign a13 = (b_loc==0) ? a13_data_delayed_13 : a13_data_in; +assign a14 = (b_loc==0) ? a14_data_delayed_14 : a14_data_in; +assign a15 = (b_loc==0) ? a15_data_delayed_15 : a15_data_in; +assign a16 = (b_loc==0) ? a16_data_delayed_16 : a16_data_in; +assign a17 = (b_loc==0) ? a17_data_delayed_17 : a17_data_in; +assign a18 = (b_loc==0) ? a18_data_delayed_18 : a18_data_in; +assign a19 = (b_loc==0) ? a19_data_delayed_19 : a19_data_in; +assign a20 = (b_loc==0) ? a20_data_delayed_20 : a20_data_in; +assign a21 = (b_loc==0) ? a21_data_delayed_21 : a21_data_in; +assign a22 = (b_loc==0) ? a22_data_delayed_22 : a22_data_in; +assign a23 = (b_loc==0) ? a23_data_delayed_23 : a23_data_in; +assign a24 = (b_loc==0) ? a24_data_delayed_24 : a24_data_in; +assign a25 = (b_loc==0) ? a25_data_delayed_25 : a25_data_in; +assign a26 = (b_loc==0) ? a26_data_delayed_26 : a26_data_in; +assign a27 = (b_loc==0) ? a27_data_delayed_27 : a27_data_in; +assign a28 = (b_loc==0) ? a28_data_delayed_28 : a28_data_in; +assign a29 = (b_loc==0) ? a29_data_delayed_29 : a29_data_in; +assign a30 = (b_loc==0) ? a30_data_delayed_30 : a30_data_in; +assign a31 = (b_loc==0) ? a31_data_delayed_31 : a31_data_in; + +assign b0 = (a_loc==0) ? b0_data : b0_data_in; +assign b1 = (a_loc==0) ? b1_data_delayed_1 : b1_data_in; +assign b2 = (a_loc==0) ? b2_data_delayed_2 : b2_data_in; +assign b3 = (a_loc==0) ? b3_data_delayed_3 : b3_data_in; +assign b4 = (a_loc==0) ? b4_data_delayed_4 : b4_data_in; +assign b5 = (a_loc==0) ? b5_data_delayed_5 : b5_data_in; +assign b6 = (a_loc==0) ? b6_data_delayed_6 : b6_data_in; +assign b7 = (a_loc==0) ? b7_data_delayed_7 : b7_data_in; +assign b8 = (a_loc==0) ? b8_data_delayed_8 : b8_data_in; +assign b9 = (a_loc==0) ? b9_data_delayed_9 : b9_data_in; +assign b10 = (a_loc==0) ? b10_data_delayed_10 : b10_data_in; +assign b11 = (a_loc==0) ? b11_data_delayed_11 : b11_data_in; +assign b12 = (a_loc==0) ? b12_data_delayed_12 : b12_data_in; +assign b13 = (a_loc==0) ? b13_data_delayed_13 : b13_data_in; +assign b14 = (a_loc==0) ? b14_data_delayed_14 : b14_data_in; +assign b15 = (a_loc==0) ? b15_data_delayed_15 : b15_data_in; +assign b16 = (a_loc==0) ? b16_data_delayed_16 : b16_data_in; +assign b17 = (a_loc==0) ? b17_data_delayed_17 : b17_data_in; +assign b18 = (a_loc==0) ? b18_data_delayed_18 : b18_data_in; +assign b19 = (a_loc==0) ? b19_data_delayed_19 : b19_data_in; +assign b20 = (a_loc==0) ? b20_data_delayed_20 : b20_data_in; +assign b21 = (a_loc==0) ? b21_data_delayed_21 : b21_data_in; +assign b22 = (a_loc==0) ? b22_data_delayed_22 : b22_data_in; +assign b23 = (a_loc==0) ? b23_data_delayed_23 : b23_data_in; +assign b24 = (a_loc==0) ? b24_data_delayed_24 : b24_data_in; +assign b25 = (a_loc==0) ? b25_data_delayed_25 : b25_data_in; +assign b26 = (a_loc==0) ? b26_data_delayed_26 : b26_data_in; +assign b27 = (a_loc==0) ? b27_data_delayed_27 : b27_data_in; +assign b28 = (a_loc==0) ? b28_data_delayed_28 : b28_data_in; +assign b29 = (a_loc==0) ? b29_data_delayed_29 : b29_data_in; +assign b30 = (a_loc==0) ? b30_data_delayed_30 : b30_data_in; +assign b31 = (a_loc==0) ? b31_data_delayed_31 : b31_data_in; + +wire [`DWIDTH-1:0] matrixC0_0; +wire [`DWIDTH-1:0] matrixC0_1; +wire [`DWIDTH-1:0] matrixC0_2; +wire [`DWIDTH-1:0] matrixC0_3; +wire [`DWIDTH-1:0] matrixC0_4; +wire [`DWIDTH-1:0] matrixC0_5; +wire [`DWIDTH-1:0] matrixC0_6; +wire [`DWIDTH-1:0] matrixC0_7; +wire [`DWIDTH-1:0] matrixC0_8; +wire [`DWIDTH-1:0] matrixC0_9; +wire [`DWIDTH-1:0] matrixC0_10; +wire [`DWIDTH-1:0] matrixC0_11; +wire [`DWIDTH-1:0] matrixC0_12; +wire [`DWIDTH-1:0] matrixC0_13; +wire [`DWIDTH-1:0] matrixC0_14; +wire [`DWIDTH-1:0] matrixC0_15; +wire [`DWIDTH-1:0] matrixC0_16; +wire [`DWIDTH-1:0] matrixC0_17; +wire [`DWIDTH-1:0] matrixC0_18; +wire [`DWIDTH-1:0] matrixC0_19; +wire [`DWIDTH-1:0] matrixC0_20; +wire [`DWIDTH-1:0] matrixC0_21; +wire [`DWIDTH-1:0] matrixC0_22; +wire [`DWIDTH-1:0] matrixC0_23; +wire [`DWIDTH-1:0] matrixC0_24; +wire [`DWIDTH-1:0] matrixC0_25; +wire [`DWIDTH-1:0] matrixC0_26; +wire [`DWIDTH-1:0] matrixC0_27; +wire [`DWIDTH-1:0] matrixC0_28; +wire [`DWIDTH-1:0] matrixC0_29; +wire [`DWIDTH-1:0] matrixC0_30; +wire [`DWIDTH-1:0] matrixC0_31; +wire [`DWIDTH-1:0] matrixC1_0; +wire [`DWIDTH-1:0] matrixC1_1; +wire [`DWIDTH-1:0] matrixC1_2; +wire [`DWIDTH-1:0] matrixC1_3; +wire [`DWIDTH-1:0] matrixC1_4; +wire [`DWIDTH-1:0] matrixC1_5; +wire [`DWIDTH-1:0] matrixC1_6; +wire [`DWIDTH-1:0] matrixC1_7; +wire [`DWIDTH-1:0] matrixC1_8; +wire [`DWIDTH-1:0] matrixC1_9; +wire [`DWIDTH-1:0] matrixC1_10; +wire [`DWIDTH-1:0] matrixC1_11; +wire [`DWIDTH-1:0] matrixC1_12; +wire [`DWIDTH-1:0] matrixC1_13; +wire [`DWIDTH-1:0] matrixC1_14; +wire [`DWIDTH-1:0] matrixC1_15; +wire [`DWIDTH-1:0] matrixC1_16; +wire [`DWIDTH-1:0] matrixC1_17; +wire [`DWIDTH-1:0] matrixC1_18; +wire [`DWIDTH-1:0] matrixC1_19; +wire [`DWIDTH-1:0] matrixC1_20; +wire [`DWIDTH-1:0] matrixC1_21; +wire [`DWIDTH-1:0] matrixC1_22; +wire [`DWIDTH-1:0] matrixC1_23; +wire [`DWIDTH-1:0] matrixC1_24; +wire [`DWIDTH-1:0] matrixC1_25; +wire [`DWIDTH-1:0] matrixC1_26; +wire [`DWIDTH-1:0] matrixC1_27; +wire [`DWIDTH-1:0] matrixC1_28; +wire [`DWIDTH-1:0] matrixC1_29; +wire [`DWIDTH-1:0] matrixC1_30; +wire [`DWIDTH-1:0] matrixC1_31; +wire [`DWIDTH-1:0] matrixC2_0; +wire [`DWIDTH-1:0] matrixC2_1; +wire [`DWIDTH-1:0] matrixC2_2; +wire [`DWIDTH-1:0] matrixC2_3; +wire [`DWIDTH-1:0] matrixC2_4; +wire [`DWIDTH-1:0] matrixC2_5; +wire [`DWIDTH-1:0] matrixC2_6; +wire [`DWIDTH-1:0] matrixC2_7; +wire [`DWIDTH-1:0] matrixC2_8; +wire [`DWIDTH-1:0] matrixC2_9; +wire [`DWIDTH-1:0] matrixC2_10; +wire [`DWIDTH-1:0] matrixC2_11; +wire [`DWIDTH-1:0] matrixC2_12; +wire [`DWIDTH-1:0] matrixC2_13; +wire [`DWIDTH-1:0] matrixC2_14; +wire [`DWIDTH-1:0] matrixC2_15; +wire [`DWIDTH-1:0] matrixC2_16; +wire [`DWIDTH-1:0] matrixC2_17; +wire [`DWIDTH-1:0] matrixC2_18; +wire [`DWIDTH-1:0] matrixC2_19; +wire [`DWIDTH-1:0] matrixC2_20; +wire [`DWIDTH-1:0] matrixC2_21; +wire [`DWIDTH-1:0] matrixC2_22; +wire [`DWIDTH-1:0] matrixC2_23; +wire [`DWIDTH-1:0] matrixC2_24; +wire [`DWIDTH-1:0] matrixC2_25; +wire [`DWIDTH-1:0] matrixC2_26; +wire [`DWIDTH-1:0] matrixC2_27; +wire [`DWIDTH-1:0] matrixC2_28; +wire [`DWIDTH-1:0] matrixC2_29; +wire [`DWIDTH-1:0] matrixC2_30; +wire [`DWIDTH-1:0] matrixC2_31; +wire [`DWIDTH-1:0] matrixC3_0; +wire [`DWIDTH-1:0] matrixC3_1; +wire [`DWIDTH-1:0] matrixC3_2; +wire [`DWIDTH-1:0] matrixC3_3; +wire [`DWIDTH-1:0] matrixC3_4; +wire [`DWIDTH-1:0] matrixC3_5; +wire [`DWIDTH-1:0] matrixC3_6; +wire [`DWIDTH-1:0] matrixC3_7; +wire [`DWIDTH-1:0] matrixC3_8; +wire [`DWIDTH-1:0] matrixC3_9; +wire [`DWIDTH-1:0] matrixC3_10; +wire [`DWIDTH-1:0] matrixC3_11; +wire [`DWIDTH-1:0] matrixC3_12; +wire [`DWIDTH-1:0] matrixC3_13; +wire [`DWIDTH-1:0] matrixC3_14; +wire [`DWIDTH-1:0] matrixC3_15; +wire [`DWIDTH-1:0] matrixC3_16; +wire [`DWIDTH-1:0] matrixC3_17; +wire [`DWIDTH-1:0] matrixC3_18; +wire [`DWIDTH-1:0] matrixC3_19; +wire [`DWIDTH-1:0] matrixC3_20; +wire [`DWIDTH-1:0] matrixC3_21; +wire [`DWIDTH-1:0] matrixC3_22; +wire [`DWIDTH-1:0] matrixC3_23; +wire [`DWIDTH-1:0] matrixC3_24; +wire [`DWIDTH-1:0] matrixC3_25; +wire [`DWIDTH-1:0] matrixC3_26; +wire [`DWIDTH-1:0] matrixC3_27; +wire [`DWIDTH-1:0] matrixC3_28; +wire [`DWIDTH-1:0] matrixC3_29; +wire [`DWIDTH-1:0] matrixC3_30; +wire [`DWIDTH-1:0] matrixC3_31; +wire [`DWIDTH-1:0] matrixC4_0; +wire [`DWIDTH-1:0] matrixC4_1; +wire [`DWIDTH-1:0] matrixC4_2; +wire [`DWIDTH-1:0] matrixC4_3; +wire [`DWIDTH-1:0] matrixC4_4; +wire [`DWIDTH-1:0] matrixC4_5; +wire [`DWIDTH-1:0] matrixC4_6; +wire [`DWIDTH-1:0] matrixC4_7; +wire [`DWIDTH-1:0] matrixC4_8; +wire [`DWIDTH-1:0] matrixC4_9; +wire [`DWIDTH-1:0] matrixC4_10; +wire [`DWIDTH-1:0] matrixC4_11; +wire [`DWIDTH-1:0] matrixC4_12; +wire [`DWIDTH-1:0] matrixC4_13; +wire [`DWIDTH-1:0] matrixC4_14; +wire [`DWIDTH-1:0] matrixC4_15; +wire [`DWIDTH-1:0] matrixC4_16; +wire [`DWIDTH-1:0] matrixC4_17; +wire [`DWIDTH-1:0] matrixC4_18; +wire [`DWIDTH-1:0] matrixC4_19; +wire [`DWIDTH-1:0] matrixC4_20; +wire [`DWIDTH-1:0] matrixC4_21; +wire [`DWIDTH-1:0] matrixC4_22; +wire [`DWIDTH-1:0] matrixC4_23; +wire [`DWIDTH-1:0] matrixC4_24; +wire [`DWIDTH-1:0] matrixC4_25; +wire [`DWIDTH-1:0] matrixC4_26; +wire [`DWIDTH-1:0] matrixC4_27; +wire [`DWIDTH-1:0] matrixC4_28; +wire [`DWIDTH-1:0] matrixC4_29; +wire [`DWIDTH-1:0] matrixC4_30; +wire [`DWIDTH-1:0] matrixC4_31; +wire [`DWIDTH-1:0] matrixC5_0; +wire [`DWIDTH-1:0] matrixC5_1; +wire [`DWIDTH-1:0] matrixC5_2; +wire [`DWIDTH-1:0] matrixC5_3; +wire [`DWIDTH-1:0] matrixC5_4; +wire [`DWIDTH-1:0] matrixC5_5; +wire [`DWIDTH-1:0] matrixC5_6; +wire [`DWIDTH-1:0] matrixC5_7; +wire [`DWIDTH-1:0] matrixC5_8; +wire [`DWIDTH-1:0] matrixC5_9; +wire [`DWIDTH-1:0] matrixC5_10; +wire [`DWIDTH-1:0] matrixC5_11; +wire [`DWIDTH-1:0] matrixC5_12; +wire [`DWIDTH-1:0] matrixC5_13; +wire [`DWIDTH-1:0] matrixC5_14; +wire [`DWIDTH-1:0] matrixC5_15; +wire [`DWIDTH-1:0] matrixC5_16; +wire [`DWIDTH-1:0] matrixC5_17; +wire [`DWIDTH-1:0] matrixC5_18; +wire [`DWIDTH-1:0] matrixC5_19; +wire [`DWIDTH-1:0] matrixC5_20; +wire [`DWIDTH-1:0] matrixC5_21; +wire [`DWIDTH-1:0] matrixC5_22; +wire [`DWIDTH-1:0] matrixC5_23; +wire [`DWIDTH-1:0] matrixC5_24; +wire [`DWIDTH-1:0] matrixC5_25; +wire [`DWIDTH-1:0] matrixC5_26; +wire [`DWIDTH-1:0] matrixC5_27; +wire [`DWIDTH-1:0] matrixC5_28; +wire [`DWIDTH-1:0] matrixC5_29; +wire [`DWIDTH-1:0] matrixC5_30; +wire [`DWIDTH-1:0] matrixC5_31; +wire [`DWIDTH-1:0] matrixC6_0; +wire [`DWIDTH-1:0] matrixC6_1; +wire [`DWIDTH-1:0] matrixC6_2; +wire [`DWIDTH-1:0] matrixC6_3; +wire [`DWIDTH-1:0] matrixC6_4; +wire [`DWIDTH-1:0] matrixC6_5; +wire [`DWIDTH-1:0] matrixC6_6; +wire [`DWIDTH-1:0] matrixC6_7; +wire [`DWIDTH-1:0] matrixC6_8; +wire [`DWIDTH-1:0] matrixC6_9; +wire [`DWIDTH-1:0] matrixC6_10; +wire [`DWIDTH-1:0] matrixC6_11; +wire [`DWIDTH-1:0] matrixC6_12; +wire [`DWIDTH-1:0] matrixC6_13; +wire [`DWIDTH-1:0] matrixC6_14; +wire [`DWIDTH-1:0] matrixC6_15; +wire [`DWIDTH-1:0] matrixC6_16; +wire [`DWIDTH-1:0] matrixC6_17; +wire [`DWIDTH-1:0] matrixC6_18; +wire [`DWIDTH-1:0] matrixC6_19; +wire [`DWIDTH-1:0] matrixC6_20; +wire [`DWIDTH-1:0] matrixC6_21; +wire [`DWIDTH-1:0] matrixC6_22; +wire [`DWIDTH-1:0] matrixC6_23; +wire [`DWIDTH-1:0] matrixC6_24; +wire [`DWIDTH-1:0] matrixC6_25; +wire [`DWIDTH-1:0] matrixC6_26; +wire [`DWIDTH-1:0] matrixC6_27; +wire [`DWIDTH-1:0] matrixC6_28; +wire [`DWIDTH-1:0] matrixC6_29; +wire [`DWIDTH-1:0] matrixC6_30; +wire [`DWIDTH-1:0] matrixC6_31; +wire [`DWIDTH-1:0] matrixC7_0; +wire [`DWIDTH-1:0] matrixC7_1; +wire [`DWIDTH-1:0] matrixC7_2; +wire [`DWIDTH-1:0] matrixC7_3; +wire [`DWIDTH-1:0] matrixC7_4; +wire [`DWIDTH-1:0] matrixC7_5; +wire [`DWIDTH-1:0] matrixC7_6; +wire [`DWIDTH-1:0] matrixC7_7; +wire [`DWIDTH-1:0] matrixC7_8; +wire [`DWIDTH-1:0] matrixC7_9; +wire [`DWIDTH-1:0] matrixC7_10; +wire [`DWIDTH-1:0] matrixC7_11; +wire [`DWIDTH-1:0] matrixC7_12; +wire [`DWIDTH-1:0] matrixC7_13; +wire [`DWIDTH-1:0] matrixC7_14; +wire [`DWIDTH-1:0] matrixC7_15; +wire [`DWIDTH-1:0] matrixC7_16; +wire [`DWIDTH-1:0] matrixC7_17; +wire [`DWIDTH-1:0] matrixC7_18; +wire [`DWIDTH-1:0] matrixC7_19; +wire [`DWIDTH-1:0] matrixC7_20; +wire [`DWIDTH-1:0] matrixC7_21; +wire [`DWIDTH-1:0] matrixC7_22; +wire [`DWIDTH-1:0] matrixC7_23; +wire [`DWIDTH-1:0] matrixC7_24; +wire [`DWIDTH-1:0] matrixC7_25; +wire [`DWIDTH-1:0] matrixC7_26; +wire [`DWIDTH-1:0] matrixC7_27; +wire [`DWIDTH-1:0] matrixC7_28; +wire [`DWIDTH-1:0] matrixC7_29; +wire [`DWIDTH-1:0] matrixC7_30; +wire [`DWIDTH-1:0] matrixC7_31; +wire [`DWIDTH-1:0] matrixC8_0; +wire [`DWIDTH-1:0] matrixC8_1; +wire [`DWIDTH-1:0] matrixC8_2; +wire [`DWIDTH-1:0] matrixC8_3; +wire [`DWIDTH-1:0] matrixC8_4; +wire [`DWIDTH-1:0] matrixC8_5; +wire [`DWIDTH-1:0] matrixC8_6; +wire [`DWIDTH-1:0] matrixC8_7; +wire [`DWIDTH-1:0] matrixC8_8; +wire [`DWIDTH-1:0] matrixC8_9; +wire [`DWIDTH-1:0] matrixC8_10; +wire [`DWIDTH-1:0] matrixC8_11; +wire [`DWIDTH-1:0] matrixC8_12; +wire [`DWIDTH-1:0] matrixC8_13; +wire [`DWIDTH-1:0] matrixC8_14; +wire [`DWIDTH-1:0] matrixC8_15; +wire [`DWIDTH-1:0] matrixC8_16; +wire [`DWIDTH-1:0] matrixC8_17; +wire [`DWIDTH-1:0] matrixC8_18; +wire [`DWIDTH-1:0] matrixC8_19; +wire [`DWIDTH-1:0] matrixC8_20; +wire [`DWIDTH-1:0] matrixC8_21; +wire [`DWIDTH-1:0] matrixC8_22; +wire [`DWIDTH-1:0] matrixC8_23; +wire [`DWIDTH-1:0] matrixC8_24; +wire [`DWIDTH-1:0] matrixC8_25; +wire [`DWIDTH-1:0] matrixC8_26; +wire [`DWIDTH-1:0] matrixC8_27; +wire [`DWIDTH-1:0] matrixC8_28; +wire [`DWIDTH-1:0] matrixC8_29; +wire [`DWIDTH-1:0] matrixC8_30; +wire [`DWIDTH-1:0] matrixC8_31; +wire [`DWIDTH-1:0] matrixC9_0; +wire [`DWIDTH-1:0] matrixC9_1; +wire [`DWIDTH-1:0] matrixC9_2; +wire [`DWIDTH-1:0] matrixC9_3; +wire [`DWIDTH-1:0] matrixC9_4; +wire [`DWIDTH-1:0] matrixC9_5; +wire [`DWIDTH-1:0] matrixC9_6; +wire [`DWIDTH-1:0] matrixC9_7; +wire [`DWIDTH-1:0] matrixC9_8; +wire [`DWIDTH-1:0] matrixC9_9; +wire [`DWIDTH-1:0] matrixC9_10; +wire [`DWIDTH-1:0] matrixC9_11; +wire [`DWIDTH-1:0] matrixC9_12; +wire [`DWIDTH-1:0] matrixC9_13; +wire [`DWIDTH-1:0] matrixC9_14; +wire [`DWIDTH-1:0] matrixC9_15; +wire [`DWIDTH-1:0] matrixC9_16; +wire [`DWIDTH-1:0] matrixC9_17; +wire [`DWIDTH-1:0] matrixC9_18; +wire [`DWIDTH-1:0] matrixC9_19; +wire [`DWIDTH-1:0] matrixC9_20; +wire [`DWIDTH-1:0] matrixC9_21; +wire [`DWIDTH-1:0] matrixC9_22; +wire [`DWIDTH-1:0] matrixC9_23; +wire [`DWIDTH-1:0] matrixC9_24; +wire [`DWIDTH-1:0] matrixC9_25; +wire [`DWIDTH-1:0] matrixC9_26; +wire [`DWIDTH-1:0] matrixC9_27; +wire [`DWIDTH-1:0] matrixC9_28; +wire [`DWIDTH-1:0] matrixC9_29; +wire [`DWIDTH-1:0] matrixC9_30; +wire [`DWIDTH-1:0] matrixC9_31; +wire [`DWIDTH-1:0] matrixC10_0; +wire [`DWIDTH-1:0] matrixC10_1; +wire [`DWIDTH-1:0] matrixC10_2; +wire [`DWIDTH-1:0] matrixC10_3; +wire [`DWIDTH-1:0] matrixC10_4; +wire [`DWIDTH-1:0] matrixC10_5; +wire [`DWIDTH-1:0] matrixC10_6; +wire [`DWIDTH-1:0] matrixC10_7; +wire [`DWIDTH-1:0] matrixC10_8; +wire [`DWIDTH-1:0] matrixC10_9; +wire [`DWIDTH-1:0] matrixC10_10; +wire [`DWIDTH-1:0] matrixC10_11; +wire [`DWIDTH-1:0] matrixC10_12; +wire [`DWIDTH-1:0] matrixC10_13; +wire [`DWIDTH-1:0] matrixC10_14; +wire [`DWIDTH-1:0] matrixC10_15; +wire [`DWIDTH-1:0] matrixC10_16; +wire [`DWIDTH-1:0] matrixC10_17; +wire [`DWIDTH-1:0] matrixC10_18; +wire [`DWIDTH-1:0] matrixC10_19; +wire [`DWIDTH-1:0] matrixC10_20; +wire [`DWIDTH-1:0] matrixC10_21; +wire [`DWIDTH-1:0] matrixC10_22; +wire [`DWIDTH-1:0] matrixC10_23; +wire [`DWIDTH-1:0] matrixC10_24; +wire [`DWIDTH-1:0] matrixC10_25; +wire [`DWIDTH-1:0] matrixC10_26; +wire [`DWIDTH-1:0] matrixC10_27; +wire [`DWIDTH-1:0] matrixC10_28; +wire [`DWIDTH-1:0] matrixC10_29; +wire [`DWIDTH-1:0] matrixC10_30; +wire [`DWIDTH-1:0] matrixC10_31; +wire [`DWIDTH-1:0] matrixC11_0; +wire [`DWIDTH-1:0] matrixC11_1; +wire [`DWIDTH-1:0] matrixC11_2; +wire [`DWIDTH-1:0] matrixC11_3; +wire [`DWIDTH-1:0] matrixC11_4; +wire [`DWIDTH-1:0] matrixC11_5; +wire [`DWIDTH-1:0] matrixC11_6; +wire [`DWIDTH-1:0] matrixC11_7; +wire [`DWIDTH-1:0] matrixC11_8; +wire [`DWIDTH-1:0] matrixC11_9; +wire [`DWIDTH-1:0] matrixC11_10; +wire [`DWIDTH-1:0] matrixC11_11; +wire [`DWIDTH-1:0] matrixC11_12; +wire [`DWIDTH-1:0] matrixC11_13; +wire [`DWIDTH-1:0] matrixC11_14; +wire [`DWIDTH-1:0] matrixC11_15; +wire [`DWIDTH-1:0] matrixC11_16; +wire [`DWIDTH-1:0] matrixC11_17; +wire [`DWIDTH-1:0] matrixC11_18; +wire [`DWIDTH-1:0] matrixC11_19; +wire [`DWIDTH-1:0] matrixC11_20; +wire [`DWIDTH-1:0] matrixC11_21; +wire [`DWIDTH-1:0] matrixC11_22; +wire [`DWIDTH-1:0] matrixC11_23; +wire [`DWIDTH-1:0] matrixC11_24; +wire [`DWIDTH-1:0] matrixC11_25; +wire [`DWIDTH-1:0] matrixC11_26; +wire [`DWIDTH-1:0] matrixC11_27; +wire [`DWIDTH-1:0] matrixC11_28; +wire [`DWIDTH-1:0] matrixC11_29; +wire [`DWIDTH-1:0] matrixC11_30; +wire [`DWIDTH-1:0] matrixC11_31; +wire [`DWIDTH-1:0] matrixC12_0; +wire [`DWIDTH-1:0] matrixC12_1; +wire [`DWIDTH-1:0] matrixC12_2; +wire [`DWIDTH-1:0] matrixC12_3; +wire [`DWIDTH-1:0] matrixC12_4; +wire [`DWIDTH-1:0] matrixC12_5; +wire [`DWIDTH-1:0] matrixC12_6; +wire [`DWIDTH-1:0] matrixC12_7; +wire [`DWIDTH-1:0] matrixC12_8; +wire [`DWIDTH-1:0] matrixC12_9; +wire [`DWIDTH-1:0] matrixC12_10; +wire [`DWIDTH-1:0] matrixC12_11; +wire [`DWIDTH-1:0] matrixC12_12; +wire [`DWIDTH-1:0] matrixC12_13; +wire [`DWIDTH-1:0] matrixC12_14; +wire [`DWIDTH-1:0] matrixC12_15; +wire [`DWIDTH-1:0] matrixC12_16; +wire [`DWIDTH-1:0] matrixC12_17; +wire [`DWIDTH-1:0] matrixC12_18; +wire [`DWIDTH-1:0] matrixC12_19; +wire [`DWIDTH-1:0] matrixC12_20; +wire [`DWIDTH-1:0] matrixC12_21; +wire [`DWIDTH-1:0] matrixC12_22; +wire [`DWIDTH-1:0] matrixC12_23; +wire [`DWIDTH-1:0] matrixC12_24; +wire [`DWIDTH-1:0] matrixC12_25; +wire [`DWIDTH-1:0] matrixC12_26; +wire [`DWIDTH-1:0] matrixC12_27; +wire [`DWIDTH-1:0] matrixC12_28; +wire [`DWIDTH-1:0] matrixC12_29; +wire [`DWIDTH-1:0] matrixC12_30; +wire [`DWIDTH-1:0] matrixC12_31; +wire [`DWIDTH-1:0] matrixC13_0; +wire [`DWIDTH-1:0] matrixC13_1; +wire [`DWIDTH-1:0] matrixC13_2; +wire [`DWIDTH-1:0] matrixC13_3; +wire [`DWIDTH-1:0] matrixC13_4; +wire [`DWIDTH-1:0] matrixC13_5; +wire [`DWIDTH-1:0] matrixC13_6; +wire [`DWIDTH-1:0] matrixC13_7; +wire [`DWIDTH-1:0] matrixC13_8; +wire [`DWIDTH-1:0] matrixC13_9; +wire [`DWIDTH-1:0] matrixC13_10; +wire [`DWIDTH-1:0] matrixC13_11; +wire [`DWIDTH-1:0] matrixC13_12; +wire [`DWIDTH-1:0] matrixC13_13; +wire [`DWIDTH-1:0] matrixC13_14; +wire [`DWIDTH-1:0] matrixC13_15; +wire [`DWIDTH-1:0] matrixC13_16; +wire [`DWIDTH-1:0] matrixC13_17; +wire [`DWIDTH-1:0] matrixC13_18; +wire [`DWIDTH-1:0] matrixC13_19; +wire [`DWIDTH-1:0] matrixC13_20; +wire [`DWIDTH-1:0] matrixC13_21; +wire [`DWIDTH-1:0] matrixC13_22; +wire [`DWIDTH-1:0] matrixC13_23; +wire [`DWIDTH-1:0] matrixC13_24; +wire [`DWIDTH-1:0] matrixC13_25; +wire [`DWIDTH-1:0] matrixC13_26; +wire [`DWIDTH-1:0] matrixC13_27; +wire [`DWIDTH-1:0] matrixC13_28; +wire [`DWIDTH-1:0] matrixC13_29; +wire [`DWIDTH-1:0] matrixC13_30; +wire [`DWIDTH-1:0] matrixC13_31; +wire [`DWIDTH-1:0] matrixC14_0; +wire [`DWIDTH-1:0] matrixC14_1; +wire [`DWIDTH-1:0] matrixC14_2; +wire [`DWIDTH-1:0] matrixC14_3; +wire [`DWIDTH-1:0] matrixC14_4; +wire [`DWIDTH-1:0] matrixC14_5; +wire [`DWIDTH-1:0] matrixC14_6; +wire [`DWIDTH-1:0] matrixC14_7; +wire [`DWIDTH-1:0] matrixC14_8; +wire [`DWIDTH-1:0] matrixC14_9; +wire [`DWIDTH-1:0] matrixC14_10; +wire [`DWIDTH-1:0] matrixC14_11; +wire [`DWIDTH-1:0] matrixC14_12; +wire [`DWIDTH-1:0] matrixC14_13; +wire [`DWIDTH-1:0] matrixC14_14; +wire [`DWIDTH-1:0] matrixC14_15; +wire [`DWIDTH-1:0] matrixC14_16; +wire [`DWIDTH-1:0] matrixC14_17; +wire [`DWIDTH-1:0] matrixC14_18; +wire [`DWIDTH-1:0] matrixC14_19; +wire [`DWIDTH-1:0] matrixC14_20; +wire [`DWIDTH-1:0] matrixC14_21; +wire [`DWIDTH-1:0] matrixC14_22; +wire [`DWIDTH-1:0] matrixC14_23; +wire [`DWIDTH-1:0] matrixC14_24; +wire [`DWIDTH-1:0] matrixC14_25; +wire [`DWIDTH-1:0] matrixC14_26; +wire [`DWIDTH-1:0] matrixC14_27; +wire [`DWIDTH-1:0] matrixC14_28; +wire [`DWIDTH-1:0] matrixC14_29; +wire [`DWIDTH-1:0] matrixC14_30; +wire [`DWIDTH-1:0] matrixC14_31; +wire [`DWIDTH-1:0] matrixC15_0; +wire [`DWIDTH-1:0] matrixC15_1; +wire [`DWIDTH-1:0] matrixC15_2; +wire [`DWIDTH-1:0] matrixC15_3; +wire [`DWIDTH-1:0] matrixC15_4; +wire [`DWIDTH-1:0] matrixC15_5; +wire [`DWIDTH-1:0] matrixC15_6; +wire [`DWIDTH-1:0] matrixC15_7; +wire [`DWIDTH-1:0] matrixC15_8; +wire [`DWIDTH-1:0] matrixC15_9; +wire [`DWIDTH-1:0] matrixC15_10; +wire [`DWIDTH-1:0] matrixC15_11; +wire [`DWIDTH-1:0] matrixC15_12; +wire [`DWIDTH-1:0] matrixC15_13; +wire [`DWIDTH-1:0] matrixC15_14; +wire [`DWIDTH-1:0] matrixC15_15; +wire [`DWIDTH-1:0] matrixC15_16; +wire [`DWIDTH-1:0] matrixC15_17; +wire [`DWIDTH-1:0] matrixC15_18; +wire [`DWIDTH-1:0] matrixC15_19; +wire [`DWIDTH-1:0] matrixC15_20; +wire [`DWIDTH-1:0] matrixC15_21; +wire [`DWIDTH-1:0] matrixC15_22; +wire [`DWIDTH-1:0] matrixC15_23; +wire [`DWIDTH-1:0] matrixC15_24; +wire [`DWIDTH-1:0] matrixC15_25; +wire [`DWIDTH-1:0] matrixC15_26; +wire [`DWIDTH-1:0] matrixC15_27; +wire [`DWIDTH-1:0] matrixC15_28; +wire [`DWIDTH-1:0] matrixC15_29; +wire [`DWIDTH-1:0] matrixC15_30; +wire [`DWIDTH-1:0] matrixC15_31; +wire [`DWIDTH-1:0] matrixC16_0; +wire [`DWIDTH-1:0] matrixC16_1; +wire [`DWIDTH-1:0] matrixC16_2; +wire [`DWIDTH-1:0] matrixC16_3; +wire [`DWIDTH-1:0] matrixC16_4; +wire [`DWIDTH-1:0] matrixC16_5; +wire [`DWIDTH-1:0] matrixC16_6; +wire [`DWIDTH-1:0] matrixC16_7; +wire [`DWIDTH-1:0] matrixC16_8; +wire [`DWIDTH-1:0] matrixC16_9; +wire [`DWIDTH-1:0] matrixC16_10; +wire [`DWIDTH-1:0] matrixC16_11; +wire [`DWIDTH-1:0] matrixC16_12; +wire [`DWIDTH-1:0] matrixC16_13; +wire [`DWIDTH-1:0] matrixC16_14; +wire [`DWIDTH-1:0] matrixC16_15; +wire [`DWIDTH-1:0] matrixC16_16; +wire [`DWIDTH-1:0] matrixC16_17; +wire [`DWIDTH-1:0] matrixC16_18; +wire [`DWIDTH-1:0] matrixC16_19; +wire [`DWIDTH-1:0] matrixC16_20; +wire [`DWIDTH-1:0] matrixC16_21; +wire [`DWIDTH-1:0] matrixC16_22; +wire [`DWIDTH-1:0] matrixC16_23; +wire [`DWIDTH-1:0] matrixC16_24; +wire [`DWIDTH-1:0] matrixC16_25; +wire [`DWIDTH-1:0] matrixC16_26; +wire [`DWIDTH-1:0] matrixC16_27; +wire [`DWIDTH-1:0] matrixC16_28; +wire [`DWIDTH-1:0] matrixC16_29; +wire [`DWIDTH-1:0] matrixC16_30; +wire [`DWIDTH-1:0] matrixC16_31; +wire [`DWIDTH-1:0] matrixC17_0; +wire [`DWIDTH-1:0] matrixC17_1; +wire [`DWIDTH-1:0] matrixC17_2; +wire [`DWIDTH-1:0] matrixC17_3; +wire [`DWIDTH-1:0] matrixC17_4; +wire [`DWIDTH-1:0] matrixC17_5; +wire [`DWIDTH-1:0] matrixC17_6; +wire [`DWIDTH-1:0] matrixC17_7; +wire [`DWIDTH-1:0] matrixC17_8; +wire [`DWIDTH-1:0] matrixC17_9; +wire [`DWIDTH-1:0] matrixC17_10; +wire [`DWIDTH-1:0] matrixC17_11; +wire [`DWIDTH-1:0] matrixC17_12; +wire [`DWIDTH-1:0] matrixC17_13; +wire [`DWIDTH-1:0] matrixC17_14; +wire [`DWIDTH-1:0] matrixC17_15; +wire [`DWIDTH-1:0] matrixC17_16; +wire [`DWIDTH-1:0] matrixC17_17; +wire [`DWIDTH-1:0] matrixC17_18; +wire [`DWIDTH-1:0] matrixC17_19; +wire [`DWIDTH-1:0] matrixC17_20; +wire [`DWIDTH-1:0] matrixC17_21; +wire [`DWIDTH-1:0] matrixC17_22; +wire [`DWIDTH-1:0] matrixC17_23; +wire [`DWIDTH-1:0] matrixC17_24; +wire [`DWIDTH-1:0] matrixC17_25; +wire [`DWIDTH-1:0] matrixC17_26; +wire [`DWIDTH-1:0] matrixC17_27; +wire [`DWIDTH-1:0] matrixC17_28; +wire [`DWIDTH-1:0] matrixC17_29; +wire [`DWIDTH-1:0] matrixC17_30; +wire [`DWIDTH-1:0] matrixC17_31; +wire [`DWIDTH-1:0] matrixC18_0; +wire [`DWIDTH-1:0] matrixC18_1; +wire [`DWIDTH-1:0] matrixC18_2; +wire [`DWIDTH-1:0] matrixC18_3; +wire [`DWIDTH-1:0] matrixC18_4; +wire [`DWIDTH-1:0] matrixC18_5; +wire [`DWIDTH-1:0] matrixC18_6; +wire [`DWIDTH-1:0] matrixC18_7; +wire [`DWIDTH-1:0] matrixC18_8; +wire [`DWIDTH-1:0] matrixC18_9; +wire [`DWIDTH-1:0] matrixC18_10; +wire [`DWIDTH-1:0] matrixC18_11; +wire [`DWIDTH-1:0] matrixC18_12; +wire [`DWIDTH-1:0] matrixC18_13; +wire [`DWIDTH-1:0] matrixC18_14; +wire [`DWIDTH-1:0] matrixC18_15; +wire [`DWIDTH-1:0] matrixC18_16; +wire [`DWIDTH-1:0] matrixC18_17; +wire [`DWIDTH-1:0] matrixC18_18; +wire [`DWIDTH-1:0] matrixC18_19; +wire [`DWIDTH-1:0] matrixC18_20; +wire [`DWIDTH-1:0] matrixC18_21; +wire [`DWIDTH-1:0] matrixC18_22; +wire [`DWIDTH-1:0] matrixC18_23; +wire [`DWIDTH-1:0] matrixC18_24; +wire [`DWIDTH-1:0] matrixC18_25; +wire [`DWIDTH-1:0] matrixC18_26; +wire [`DWIDTH-1:0] matrixC18_27; +wire [`DWIDTH-1:0] matrixC18_28; +wire [`DWIDTH-1:0] matrixC18_29; +wire [`DWIDTH-1:0] matrixC18_30; +wire [`DWIDTH-1:0] matrixC18_31; +wire [`DWIDTH-1:0] matrixC19_0; +wire [`DWIDTH-1:0] matrixC19_1; +wire [`DWIDTH-1:0] matrixC19_2; +wire [`DWIDTH-1:0] matrixC19_3; +wire [`DWIDTH-1:0] matrixC19_4; +wire [`DWIDTH-1:0] matrixC19_5; +wire [`DWIDTH-1:0] matrixC19_6; +wire [`DWIDTH-1:0] matrixC19_7; +wire [`DWIDTH-1:0] matrixC19_8; +wire [`DWIDTH-1:0] matrixC19_9; +wire [`DWIDTH-1:0] matrixC19_10; +wire [`DWIDTH-1:0] matrixC19_11; +wire [`DWIDTH-1:0] matrixC19_12; +wire [`DWIDTH-1:0] matrixC19_13; +wire [`DWIDTH-1:0] matrixC19_14; +wire [`DWIDTH-1:0] matrixC19_15; +wire [`DWIDTH-1:0] matrixC19_16; +wire [`DWIDTH-1:0] matrixC19_17; +wire [`DWIDTH-1:0] matrixC19_18; +wire [`DWIDTH-1:0] matrixC19_19; +wire [`DWIDTH-1:0] matrixC19_20; +wire [`DWIDTH-1:0] matrixC19_21; +wire [`DWIDTH-1:0] matrixC19_22; +wire [`DWIDTH-1:0] matrixC19_23; +wire [`DWIDTH-1:0] matrixC19_24; +wire [`DWIDTH-1:0] matrixC19_25; +wire [`DWIDTH-1:0] matrixC19_26; +wire [`DWIDTH-1:0] matrixC19_27; +wire [`DWIDTH-1:0] matrixC19_28; +wire [`DWIDTH-1:0] matrixC19_29; +wire [`DWIDTH-1:0] matrixC19_30; +wire [`DWIDTH-1:0] matrixC19_31; +wire [`DWIDTH-1:0] matrixC20_0; +wire [`DWIDTH-1:0] matrixC20_1; +wire [`DWIDTH-1:0] matrixC20_2; +wire [`DWIDTH-1:0] matrixC20_3; +wire [`DWIDTH-1:0] matrixC20_4; +wire [`DWIDTH-1:0] matrixC20_5; +wire [`DWIDTH-1:0] matrixC20_6; +wire [`DWIDTH-1:0] matrixC20_7; +wire [`DWIDTH-1:0] matrixC20_8; +wire [`DWIDTH-1:0] matrixC20_9; +wire [`DWIDTH-1:0] matrixC20_10; +wire [`DWIDTH-1:0] matrixC20_11; +wire [`DWIDTH-1:0] matrixC20_12; +wire [`DWIDTH-1:0] matrixC20_13; +wire [`DWIDTH-1:0] matrixC20_14; +wire [`DWIDTH-1:0] matrixC20_15; +wire [`DWIDTH-1:0] matrixC20_16; +wire [`DWIDTH-1:0] matrixC20_17; +wire [`DWIDTH-1:0] matrixC20_18; +wire [`DWIDTH-1:0] matrixC20_19; +wire [`DWIDTH-1:0] matrixC20_20; +wire [`DWIDTH-1:0] matrixC20_21; +wire [`DWIDTH-1:0] matrixC20_22; +wire [`DWIDTH-1:0] matrixC20_23; +wire [`DWIDTH-1:0] matrixC20_24; +wire [`DWIDTH-1:0] matrixC20_25; +wire [`DWIDTH-1:0] matrixC20_26; +wire [`DWIDTH-1:0] matrixC20_27; +wire [`DWIDTH-1:0] matrixC20_28; +wire [`DWIDTH-1:0] matrixC20_29; +wire [`DWIDTH-1:0] matrixC20_30; +wire [`DWIDTH-1:0] matrixC20_31; +wire [`DWIDTH-1:0] matrixC21_0; +wire [`DWIDTH-1:0] matrixC21_1; +wire [`DWIDTH-1:0] matrixC21_2; +wire [`DWIDTH-1:0] matrixC21_3; +wire [`DWIDTH-1:0] matrixC21_4; +wire [`DWIDTH-1:0] matrixC21_5; +wire [`DWIDTH-1:0] matrixC21_6; +wire [`DWIDTH-1:0] matrixC21_7; +wire [`DWIDTH-1:0] matrixC21_8; +wire [`DWIDTH-1:0] matrixC21_9; +wire [`DWIDTH-1:0] matrixC21_10; +wire [`DWIDTH-1:0] matrixC21_11; +wire [`DWIDTH-1:0] matrixC21_12; +wire [`DWIDTH-1:0] matrixC21_13; +wire [`DWIDTH-1:0] matrixC21_14; +wire [`DWIDTH-1:0] matrixC21_15; +wire [`DWIDTH-1:0] matrixC21_16; +wire [`DWIDTH-1:0] matrixC21_17; +wire [`DWIDTH-1:0] matrixC21_18; +wire [`DWIDTH-1:0] matrixC21_19; +wire [`DWIDTH-1:0] matrixC21_20; +wire [`DWIDTH-1:0] matrixC21_21; +wire [`DWIDTH-1:0] matrixC21_22; +wire [`DWIDTH-1:0] matrixC21_23; +wire [`DWIDTH-1:0] matrixC21_24; +wire [`DWIDTH-1:0] matrixC21_25; +wire [`DWIDTH-1:0] matrixC21_26; +wire [`DWIDTH-1:0] matrixC21_27; +wire [`DWIDTH-1:0] matrixC21_28; +wire [`DWIDTH-1:0] matrixC21_29; +wire [`DWIDTH-1:0] matrixC21_30; +wire [`DWIDTH-1:0] matrixC21_31; +wire [`DWIDTH-1:0] matrixC22_0; +wire [`DWIDTH-1:0] matrixC22_1; +wire [`DWIDTH-1:0] matrixC22_2; +wire [`DWIDTH-1:0] matrixC22_3; +wire [`DWIDTH-1:0] matrixC22_4; +wire [`DWIDTH-1:0] matrixC22_5; +wire [`DWIDTH-1:0] matrixC22_6; +wire [`DWIDTH-1:0] matrixC22_7; +wire [`DWIDTH-1:0] matrixC22_8; +wire [`DWIDTH-1:0] matrixC22_9; +wire [`DWIDTH-1:0] matrixC22_10; +wire [`DWIDTH-1:0] matrixC22_11; +wire [`DWIDTH-1:0] matrixC22_12; +wire [`DWIDTH-1:0] matrixC22_13; +wire [`DWIDTH-1:0] matrixC22_14; +wire [`DWIDTH-1:0] matrixC22_15; +wire [`DWIDTH-1:0] matrixC22_16; +wire [`DWIDTH-1:0] matrixC22_17; +wire [`DWIDTH-1:0] matrixC22_18; +wire [`DWIDTH-1:0] matrixC22_19; +wire [`DWIDTH-1:0] matrixC22_20; +wire [`DWIDTH-1:0] matrixC22_21; +wire [`DWIDTH-1:0] matrixC22_22; +wire [`DWIDTH-1:0] matrixC22_23; +wire [`DWIDTH-1:0] matrixC22_24; +wire [`DWIDTH-1:0] matrixC22_25; +wire [`DWIDTH-1:0] matrixC22_26; +wire [`DWIDTH-1:0] matrixC22_27; +wire [`DWIDTH-1:0] matrixC22_28; +wire [`DWIDTH-1:0] matrixC22_29; +wire [`DWIDTH-1:0] matrixC22_30; +wire [`DWIDTH-1:0] matrixC22_31; +wire [`DWIDTH-1:0] matrixC23_0; +wire [`DWIDTH-1:0] matrixC23_1; +wire [`DWIDTH-1:0] matrixC23_2; +wire [`DWIDTH-1:0] matrixC23_3; +wire [`DWIDTH-1:0] matrixC23_4; +wire [`DWIDTH-1:0] matrixC23_5; +wire [`DWIDTH-1:0] matrixC23_6; +wire [`DWIDTH-1:0] matrixC23_7; +wire [`DWIDTH-1:0] matrixC23_8; +wire [`DWIDTH-1:0] matrixC23_9; +wire [`DWIDTH-1:0] matrixC23_10; +wire [`DWIDTH-1:0] matrixC23_11; +wire [`DWIDTH-1:0] matrixC23_12; +wire [`DWIDTH-1:0] matrixC23_13; +wire [`DWIDTH-1:0] matrixC23_14; +wire [`DWIDTH-1:0] matrixC23_15; +wire [`DWIDTH-1:0] matrixC23_16; +wire [`DWIDTH-1:0] matrixC23_17; +wire [`DWIDTH-1:0] matrixC23_18; +wire [`DWIDTH-1:0] matrixC23_19; +wire [`DWIDTH-1:0] matrixC23_20; +wire [`DWIDTH-1:0] matrixC23_21; +wire [`DWIDTH-1:0] matrixC23_22; +wire [`DWIDTH-1:0] matrixC23_23; +wire [`DWIDTH-1:0] matrixC23_24; +wire [`DWIDTH-1:0] matrixC23_25; +wire [`DWIDTH-1:0] matrixC23_26; +wire [`DWIDTH-1:0] matrixC23_27; +wire [`DWIDTH-1:0] matrixC23_28; +wire [`DWIDTH-1:0] matrixC23_29; +wire [`DWIDTH-1:0] matrixC23_30; +wire [`DWIDTH-1:0] matrixC23_31; +wire [`DWIDTH-1:0] matrixC24_0; +wire [`DWIDTH-1:0] matrixC24_1; +wire [`DWIDTH-1:0] matrixC24_2; +wire [`DWIDTH-1:0] matrixC24_3; +wire [`DWIDTH-1:0] matrixC24_4; +wire [`DWIDTH-1:0] matrixC24_5; +wire [`DWIDTH-1:0] matrixC24_6; +wire [`DWIDTH-1:0] matrixC24_7; +wire [`DWIDTH-1:0] matrixC24_8; +wire [`DWIDTH-1:0] matrixC24_9; +wire [`DWIDTH-1:0] matrixC24_10; +wire [`DWIDTH-1:0] matrixC24_11; +wire [`DWIDTH-1:0] matrixC24_12; +wire [`DWIDTH-1:0] matrixC24_13; +wire [`DWIDTH-1:0] matrixC24_14; +wire [`DWIDTH-1:0] matrixC24_15; +wire [`DWIDTH-1:0] matrixC24_16; +wire [`DWIDTH-1:0] matrixC24_17; +wire [`DWIDTH-1:0] matrixC24_18; +wire [`DWIDTH-1:0] matrixC24_19; +wire [`DWIDTH-1:0] matrixC24_20; +wire [`DWIDTH-1:0] matrixC24_21; +wire [`DWIDTH-1:0] matrixC24_22; +wire [`DWIDTH-1:0] matrixC24_23; +wire [`DWIDTH-1:0] matrixC24_24; +wire [`DWIDTH-1:0] matrixC24_25; +wire [`DWIDTH-1:0] matrixC24_26; +wire [`DWIDTH-1:0] matrixC24_27; +wire [`DWIDTH-1:0] matrixC24_28; +wire [`DWIDTH-1:0] matrixC24_29; +wire [`DWIDTH-1:0] matrixC24_30; +wire [`DWIDTH-1:0] matrixC24_31; +wire [`DWIDTH-1:0] matrixC25_0; +wire [`DWIDTH-1:0] matrixC25_1; +wire [`DWIDTH-1:0] matrixC25_2; +wire [`DWIDTH-1:0] matrixC25_3; +wire [`DWIDTH-1:0] matrixC25_4; +wire [`DWIDTH-1:0] matrixC25_5; +wire [`DWIDTH-1:0] matrixC25_6; +wire [`DWIDTH-1:0] matrixC25_7; +wire [`DWIDTH-1:0] matrixC25_8; +wire [`DWIDTH-1:0] matrixC25_9; +wire [`DWIDTH-1:0] matrixC25_10; +wire [`DWIDTH-1:0] matrixC25_11; +wire [`DWIDTH-1:0] matrixC25_12; +wire [`DWIDTH-1:0] matrixC25_13; +wire [`DWIDTH-1:0] matrixC25_14; +wire [`DWIDTH-1:0] matrixC25_15; +wire [`DWIDTH-1:0] matrixC25_16; +wire [`DWIDTH-1:0] matrixC25_17; +wire [`DWIDTH-1:0] matrixC25_18; +wire [`DWIDTH-1:0] matrixC25_19; +wire [`DWIDTH-1:0] matrixC25_20; +wire [`DWIDTH-1:0] matrixC25_21; +wire [`DWIDTH-1:0] matrixC25_22; +wire [`DWIDTH-1:0] matrixC25_23; +wire [`DWIDTH-1:0] matrixC25_24; +wire [`DWIDTH-1:0] matrixC25_25; +wire [`DWIDTH-1:0] matrixC25_26; +wire [`DWIDTH-1:0] matrixC25_27; +wire [`DWIDTH-1:0] matrixC25_28; +wire [`DWIDTH-1:0] matrixC25_29; +wire [`DWIDTH-1:0] matrixC25_30; +wire [`DWIDTH-1:0] matrixC25_31; +wire [`DWIDTH-1:0] matrixC26_0; +wire [`DWIDTH-1:0] matrixC26_1; +wire [`DWIDTH-1:0] matrixC26_2; +wire [`DWIDTH-1:0] matrixC26_3; +wire [`DWIDTH-1:0] matrixC26_4; +wire [`DWIDTH-1:0] matrixC26_5; +wire [`DWIDTH-1:0] matrixC26_6; +wire [`DWIDTH-1:0] matrixC26_7; +wire [`DWIDTH-1:0] matrixC26_8; +wire [`DWIDTH-1:0] matrixC26_9; +wire [`DWIDTH-1:0] matrixC26_10; +wire [`DWIDTH-1:0] matrixC26_11; +wire [`DWIDTH-1:0] matrixC26_12; +wire [`DWIDTH-1:0] matrixC26_13; +wire [`DWIDTH-1:0] matrixC26_14; +wire [`DWIDTH-1:0] matrixC26_15; +wire [`DWIDTH-1:0] matrixC26_16; +wire [`DWIDTH-1:0] matrixC26_17; +wire [`DWIDTH-1:0] matrixC26_18; +wire [`DWIDTH-1:0] matrixC26_19; +wire [`DWIDTH-1:0] matrixC26_20; +wire [`DWIDTH-1:0] matrixC26_21; +wire [`DWIDTH-1:0] matrixC26_22; +wire [`DWIDTH-1:0] matrixC26_23; +wire [`DWIDTH-1:0] matrixC26_24; +wire [`DWIDTH-1:0] matrixC26_25; +wire [`DWIDTH-1:0] matrixC26_26; +wire [`DWIDTH-1:0] matrixC26_27; +wire [`DWIDTH-1:0] matrixC26_28; +wire [`DWIDTH-1:0] matrixC26_29; +wire [`DWIDTH-1:0] matrixC26_30; +wire [`DWIDTH-1:0] matrixC26_31; +wire [`DWIDTH-1:0] matrixC27_0; +wire [`DWIDTH-1:0] matrixC27_1; +wire [`DWIDTH-1:0] matrixC27_2; +wire [`DWIDTH-1:0] matrixC27_3; +wire [`DWIDTH-1:0] matrixC27_4; +wire [`DWIDTH-1:0] matrixC27_5; +wire [`DWIDTH-1:0] matrixC27_6; +wire [`DWIDTH-1:0] matrixC27_7; +wire [`DWIDTH-1:0] matrixC27_8; +wire [`DWIDTH-1:0] matrixC27_9; +wire [`DWIDTH-1:0] matrixC27_10; +wire [`DWIDTH-1:0] matrixC27_11; +wire [`DWIDTH-1:0] matrixC27_12; +wire [`DWIDTH-1:0] matrixC27_13; +wire [`DWIDTH-1:0] matrixC27_14; +wire [`DWIDTH-1:0] matrixC27_15; +wire [`DWIDTH-1:0] matrixC27_16; +wire [`DWIDTH-1:0] matrixC27_17; +wire [`DWIDTH-1:0] matrixC27_18; +wire [`DWIDTH-1:0] matrixC27_19; +wire [`DWIDTH-1:0] matrixC27_20; +wire [`DWIDTH-1:0] matrixC27_21; +wire [`DWIDTH-1:0] matrixC27_22; +wire [`DWIDTH-1:0] matrixC27_23; +wire [`DWIDTH-1:0] matrixC27_24; +wire [`DWIDTH-1:0] matrixC27_25; +wire [`DWIDTH-1:0] matrixC27_26; +wire [`DWIDTH-1:0] matrixC27_27; +wire [`DWIDTH-1:0] matrixC27_28; +wire [`DWIDTH-1:0] matrixC27_29; +wire [`DWIDTH-1:0] matrixC27_30; +wire [`DWIDTH-1:0] matrixC27_31; +wire [`DWIDTH-1:0] matrixC28_0; +wire [`DWIDTH-1:0] matrixC28_1; +wire [`DWIDTH-1:0] matrixC28_2; +wire [`DWIDTH-1:0] matrixC28_3; +wire [`DWIDTH-1:0] matrixC28_4; +wire [`DWIDTH-1:0] matrixC28_5; +wire [`DWIDTH-1:0] matrixC28_6; +wire [`DWIDTH-1:0] matrixC28_7; +wire [`DWIDTH-1:0] matrixC28_8; +wire [`DWIDTH-1:0] matrixC28_9; +wire [`DWIDTH-1:0] matrixC28_10; +wire [`DWIDTH-1:0] matrixC28_11; +wire [`DWIDTH-1:0] matrixC28_12; +wire [`DWIDTH-1:0] matrixC28_13; +wire [`DWIDTH-1:0] matrixC28_14; +wire [`DWIDTH-1:0] matrixC28_15; +wire [`DWIDTH-1:0] matrixC28_16; +wire [`DWIDTH-1:0] matrixC28_17; +wire [`DWIDTH-1:0] matrixC28_18; +wire [`DWIDTH-1:0] matrixC28_19; +wire [`DWIDTH-1:0] matrixC28_20; +wire [`DWIDTH-1:0] matrixC28_21; +wire [`DWIDTH-1:0] matrixC28_22; +wire [`DWIDTH-1:0] matrixC28_23; +wire [`DWIDTH-1:0] matrixC28_24; +wire [`DWIDTH-1:0] matrixC28_25; +wire [`DWIDTH-1:0] matrixC28_26; +wire [`DWIDTH-1:0] matrixC28_27; +wire [`DWIDTH-1:0] matrixC28_28; +wire [`DWIDTH-1:0] matrixC28_29; +wire [`DWIDTH-1:0] matrixC28_30; +wire [`DWIDTH-1:0] matrixC28_31; +wire [`DWIDTH-1:0] matrixC29_0; +wire [`DWIDTH-1:0] matrixC29_1; +wire [`DWIDTH-1:0] matrixC29_2; +wire [`DWIDTH-1:0] matrixC29_3; +wire [`DWIDTH-1:0] matrixC29_4; +wire [`DWIDTH-1:0] matrixC29_5; +wire [`DWIDTH-1:0] matrixC29_6; +wire [`DWIDTH-1:0] matrixC29_7; +wire [`DWIDTH-1:0] matrixC29_8; +wire [`DWIDTH-1:0] matrixC29_9; +wire [`DWIDTH-1:0] matrixC29_10; +wire [`DWIDTH-1:0] matrixC29_11; +wire [`DWIDTH-1:0] matrixC29_12; +wire [`DWIDTH-1:0] matrixC29_13; +wire [`DWIDTH-1:0] matrixC29_14; +wire [`DWIDTH-1:0] matrixC29_15; +wire [`DWIDTH-1:0] matrixC29_16; +wire [`DWIDTH-1:0] matrixC29_17; +wire [`DWIDTH-1:0] matrixC29_18; +wire [`DWIDTH-1:0] matrixC29_19; +wire [`DWIDTH-1:0] matrixC29_20; +wire [`DWIDTH-1:0] matrixC29_21; +wire [`DWIDTH-1:0] matrixC29_22; +wire [`DWIDTH-1:0] matrixC29_23; +wire [`DWIDTH-1:0] matrixC29_24; +wire [`DWIDTH-1:0] matrixC29_25; +wire [`DWIDTH-1:0] matrixC29_26; +wire [`DWIDTH-1:0] matrixC29_27; +wire [`DWIDTH-1:0] matrixC29_28; +wire [`DWIDTH-1:0] matrixC29_29; +wire [`DWIDTH-1:0] matrixC29_30; +wire [`DWIDTH-1:0] matrixC29_31; +wire [`DWIDTH-1:0] matrixC30_0; +wire [`DWIDTH-1:0] matrixC30_1; +wire [`DWIDTH-1:0] matrixC30_2; +wire [`DWIDTH-1:0] matrixC30_3; +wire [`DWIDTH-1:0] matrixC30_4; +wire [`DWIDTH-1:0] matrixC30_5; +wire [`DWIDTH-1:0] matrixC30_6; +wire [`DWIDTH-1:0] matrixC30_7; +wire [`DWIDTH-1:0] matrixC30_8; +wire [`DWIDTH-1:0] matrixC30_9; +wire [`DWIDTH-1:0] matrixC30_10; +wire [`DWIDTH-1:0] matrixC30_11; +wire [`DWIDTH-1:0] matrixC30_12; +wire [`DWIDTH-1:0] matrixC30_13; +wire [`DWIDTH-1:0] matrixC30_14; +wire [`DWIDTH-1:0] matrixC30_15; +wire [`DWIDTH-1:0] matrixC30_16; +wire [`DWIDTH-1:0] matrixC30_17; +wire [`DWIDTH-1:0] matrixC30_18; +wire [`DWIDTH-1:0] matrixC30_19; +wire [`DWIDTH-1:0] matrixC30_20; +wire [`DWIDTH-1:0] matrixC30_21; +wire [`DWIDTH-1:0] matrixC30_22; +wire [`DWIDTH-1:0] matrixC30_23; +wire [`DWIDTH-1:0] matrixC30_24; +wire [`DWIDTH-1:0] matrixC30_25; +wire [`DWIDTH-1:0] matrixC30_26; +wire [`DWIDTH-1:0] matrixC30_27; +wire [`DWIDTH-1:0] matrixC30_28; +wire [`DWIDTH-1:0] matrixC30_29; +wire [`DWIDTH-1:0] matrixC30_30; +wire [`DWIDTH-1:0] matrixC30_31; +wire [`DWIDTH-1:0] matrixC31_0; +wire [`DWIDTH-1:0] matrixC31_1; +wire [`DWIDTH-1:0] matrixC31_2; +wire [`DWIDTH-1:0] matrixC31_3; +wire [`DWIDTH-1:0] matrixC31_4; +wire [`DWIDTH-1:0] matrixC31_5; +wire [`DWIDTH-1:0] matrixC31_6; +wire [`DWIDTH-1:0] matrixC31_7; +wire [`DWIDTH-1:0] matrixC31_8; +wire [`DWIDTH-1:0] matrixC31_9; +wire [`DWIDTH-1:0] matrixC31_10; +wire [`DWIDTH-1:0] matrixC31_11; +wire [`DWIDTH-1:0] matrixC31_12; +wire [`DWIDTH-1:0] matrixC31_13; +wire [`DWIDTH-1:0] matrixC31_14; +wire [`DWIDTH-1:0] matrixC31_15; +wire [`DWIDTH-1:0] matrixC31_16; +wire [`DWIDTH-1:0] matrixC31_17; +wire [`DWIDTH-1:0] matrixC31_18; +wire [`DWIDTH-1:0] matrixC31_19; +wire [`DWIDTH-1:0] matrixC31_20; +wire [`DWIDTH-1:0] matrixC31_21; +wire [`DWIDTH-1:0] matrixC31_22; +wire [`DWIDTH-1:0] matrixC31_23; +wire [`DWIDTH-1:0] matrixC31_24; +wire [`DWIDTH-1:0] matrixC31_25; +wire [`DWIDTH-1:0] matrixC31_26; +wire [`DWIDTH-1:0] matrixC31_27; +wire [`DWIDTH-1:0] matrixC31_28; +wire [`DWIDTH-1:0] matrixC31_29; +wire [`DWIDTH-1:0] matrixC31_30; +wire [`DWIDTH-1:0] matrixC31_31; + +wire row_latch_en; +////////////////////////////////////////////////////////////////////////// +// Instantiation of the output logic +////////////////////////////////////////////////////////////////////////// +output_logic u_output_logic( +.start_mat_mul(start_mat_mul), +.done_mat_mul(done_mat_mul), +.address_mat_c(address_mat_c), +.address_stride_c(address_stride_c), +.c_data_out(c_data_out), +.c_data_in(c_data_in), +.c_addr(c_addr), +.c_data_available(c_data_available), +.clk_cnt(clk_cnt), +.row_latch_en(row_latch_en), +.final_mat_mul_size(final_mat_mul_size), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), +.matrixC0_14(matrixC0_14), +.matrixC0_15(matrixC0_15), +.matrixC0_16(matrixC0_16), +.matrixC0_17(matrixC0_17), +.matrixC0_18(matrixC0_18), +.matrixC0_19(matrixC0_19), +.matrixC0_20(matrixC0_20), +.matrixC0_21(matrixC0_21), +.matrixC0_22(matrixC0_22), +.matrixC0_23(matrixC0_23), +.matrixC0_24(matrixC0_24), +.matrixC0_25(matrixC0_25), +.matrixC0_26(matrixC0_26), +.matrixC0_27(matrixC0_27), +.matrixC0_28(matrixC0_28), +.matrixC0_29(matrixC0_29), +.matrixC0_30(matrixC0_30), +.matrixC0_31(matrixC0_31), +.matrixC1_0(matrixC1_0), +.matrixC1_1(matrixC1_1), +.matrixC1_2(matrixC1_2), +.matrixC1_3(matrixC1_3), +.matrixC1_4(matrixC1_4), +.matrixC1_5(matrixC1_5), +.matrixC1_6(matrixC1_6), +.matrixC1_7(matrixC1_7), +.matrixC1_8(matrixC1_8), +.matrixC1_9(matrixC1_9), +.matrixC1_10(matrixC1_10), +.matrixC1_11(matrixC1_11), +.matrixC1_12(matrixC1_12), +.matrixC1_13(matrixC1_13), +.matrixC1_14(matrixC1_14), +.matrixC1_15(matrixC1_15), +.matrixC1_16(matrixC1_16), +.matrixC1_17(matrixC1_17), +.matrixC1_18(matrixC1_18), +.matrixC1_19(matrixC1_19), +.matrixC1_20(matrixC1_20), +.matrixC1_21(matrixC1_21), +.matrixC1_22(matrixC1_22), +.matrixC1_23(matrixC1_23), +.matrixC1_24(matrixC1_24), +.matrixC1_25(matrixC1_25), +.matrixC1_26(matrixC1_26), +.matrixC1_27(matrixC1_27), +.matrixC1_28(matrixC1_28), +.matrixC1_29(matrixC1_29), +.matrixC1_30(matrixC1_30), +.matrixC1_31(matrixC1_31), +.matrixC2_0(matrixC2_0), +.matrixC2_1(matrixC2_1), +.matrixC2_2(matrixC2_2), +.matrixC2_3(matrixC2_3), +.matrixC2_4(matrixC2_4), +.matrixC2_5(matrixC2_5), +.matrixC2_6(matrixC2_6), +.matrixC2_7(matrixC2_7), +.matrixC2_8(matrixC2_8), +.matrixC2_9(matrixC2_9), +.matrixC2_10(matrixC2_10), +.matrixC2_11(matrixC2_11), +.matrixC2_12(matrixC2_12), +.matrixC2_13(matrixC2_13), +.matrixC2_14(matrixC2_14), +.matrixC2_15(matrixC2_15), +.matrixC2_16(matrixC2_16), +.matrixC2_17(matrixC2_17), +.matrixC2_18(matrixC2_18), +.matrixC2_19(matrixC2_19), +.matrixC2_20(matrixC2_20), +.matrixC2_21(matrixC2_21), +.matrixC2_22(matrixC2_22), +.matrixC2_23(matrixC2_23), +.matrixC2_24(matrixC2_24), +.matrixC2_25(matrixC2_25), +.matrixC2_26(matrixC2_26), +.matrixC2_27(matrixC2_27), +.matrixC2_28(matrixC2_28), +.matrixC2_29(matrixC2_29), +.matrixC2_30(matrixC2_30), +.matrixC2_31(matrixC2_31), +.matrixC3_0(matrixC3_0), +.matrixC3_1(matrixC3_1), +.matrixC3_2(matrixC3_2), +.matrixC3_3(matrixC3_3), +.matrixC3_4(matrixC3_4), +.matrixC3_5(matrixC3_5), +.matrixC3_6(matrixC3_6), +.matrixC3_7(matrixC3_7), +.matrixC3_8(matrixC3_8), +.matrixC3_9(matrixC3_9), +.matrixC3_10(matrixC3_10), +.matrixC3_11(matrixC3_11), +.matrixC3_12(matrixC3_12), +.matrixC3_13(matrixC3_13), +.matrixC3_14(matrixC3_14), +.matrixC3_15(matrixC3_15), +.matrixC3_16(matrixC3_16), +.matrixC3_17(matrixC3_17), +.matrixC3_18(matrixC3_18), +.matrixC3_19(matrixC3_19), +.matrixC3_20(matrixC3_20), +.matrixC3_21(matrixC3_21), +.matrixC3_22(matrixC3_22), +.matrixC3_23(matrixC3_23), +.matrixC3_24(matrixC3_24), +.matrixC3_25(matrixC3_25), +.matrixC3_26(matrixC3_26), +.matrixC3_27(matrixC3_27), +.matrixC3_28(matrixC3_28), +.matrixC3_29(matrixC3_29), +.matrixC3_30(matrixC3_30), +.matrixC3_31(matrixC3_31), +.matrixC4_0(matrixC4_0), +.matrixC4_1(matrixC4_1), +.matrixC4_2(matrixC4_2), +.matrixC4_3(matrixC4_3), +.matrixC4_4(matrixC4_4), +.matrixC4_5(matrixC4_5), +.matrixC4_6(matrixC4_6), +.matrixC4_7(matrixC4_7), +.matrixC4_8(matrixC4_8), +.matrixC4_9(matrixC4_9), +.matrixC4_10(matrixC4_10), +.matrixC4_11(matrixC4_11), +.matrixC4_12(matrixC4_12), +.matrixC4_13(matrixC4_13), +.matrixC4_14(matrixC4_14), +.matrixC4_15(matrixC4_15), +.matrixC4_16(matrixC4_16), +.matrixC4_17(matrixC4_17), +.matrixC4_18(matrixC4_18), +.matrixC4_19(matrixC4_19), +.matrixC4_20(matrixC4_20), +.matrixC4_21(matrixC4_21), +.matrixC4_22(matrixC4_22), +.matrixC4_23(matrixC4_23), +.matrixC4_24(matrixC4_24), +.matrixC4_25(matrixC4_25), +.matrixC4_26(matrixC4_26), +.matrixC4_27(matrixC4_27), +.matrixC4_28(matrixC4_28), +.matrixC4_29(matrixC4_29), +.matrixC4_30(matrixC4_30), +.matrixC4_31(matrixC4_31), +.matrixC5_0(matrixC5_0), +.matrixC5_1(matrixC5_1), +.matrixC5_2(matrixC5_2), +.matrixC5_3(matrixC5_3), +.matrixC5_4(matrixC5_4), +.matrixC5_5(matrixC5_5), +.matrixC5_6(matrixC5_6), +.matrixC5_7(matrixC5_7), +.matrixC5_8(matrixC5_8), +.matrixC5_9(matrixC5_9), +.matrixC5_10(matrixC5_10), +.matrixC5_11(matrixC5_11), +.matrixC5_12(matrixC5_12), +.matrixC5_13(matrixC5_13), +.matrixC5_14(matrixC5_14), +.matrixC5_15(matrixC5_15), +.matrixC5_16(matrixC5_16), +.matrixC5_17(matrixC5_17), +.matrixC5_18(matrixC5_18), +.matrixC5_19(matrixC5_19), +.matrixC5_20(matrixC5_20), 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+.matrixC20_25(matrixC20_25), +.matrixC20_26(matrixC20_26), +.matrixC20_27(matrixC20_27), +.matrixC20_28(matrixC20_28), +.matrixC20_29(matrixC20_29), +.matrixC20_30(matrixC20_30), +.matrixC20_31(matrixC20_31), +.matrixC21_0(matrixC21_0), +.matrixC21_1(matrixC21_1), +.matrixC21_2(matrixC21_2), +.matrixC21_3(matrixC21_3), +.matrixC21_4(matrixC21_4), +.matrixC21_5(matrixC21_5), +.matrixC21_6(matrixC21_6), +.matrixC21_7(matrixC21_7), +.matrixC21_8(matrixC21_8), +.matrixC21_9(matrixC21_9), +.matrixC21_10(matrixC21_10), +.matrixC21_11(matrixC21_11), +.matrixC21_12(matrixC21_12), +.matrixC21_13(matrixC21_13), +.matrixC21_14(matrixC21_14), +.matrixC21_15(matrixC21_15), +.matrixC21_16(matrixC21_16), +.matrixC21_17(matrixC21_17), +.matrixC21_18(matrixC21_18), +.matrixC21_19(matrixC21_19), +.matrixC21_20(matrixC21_20), +.matrixC21_21(matrixC21_21), +.matrixC21_22(matrixC21_22), +.matrixC21_23(matrixC21_23), +.matrixC21_24(matrixC21_24), +.matrixC21_25(matrixC21_25), +.matrixC21_26(matrixC21_26), +.matrixC21_27(matrixC21_27), +.matrixC21_28(matrixC21_28), +.matrixC21_29(matrixC21_29), +.matrixC21_30(matrixC21_30), +.matrixC21_31(matrixC21_31), +.matrixC22_0(matrixC22_0), +.matrixC22_1(matrixC22_1), +.matrixC22_2(matrixC22_2), +.matrixC22_3(matrixC22_3), +.matrixC22_4(matrixC22_4), +.matrixC22_5(matrixC22_5), +.matrixC22_6(matrixC22_6), +.matrixC22_7(matrixC22_7), +.matrixC22_8(matrixC22_8), +.matrixC22_9(matrixC22_9), +.matrixC22_10(matrixC22_10), +.matrixC22_11(matrixC22_11), +.matrixC22_12(matrixC22_12), +.matrixC22_13(matrixC22_13), +.matrixC22_14(matrixC22_14), +.matrixC22_15(matrixC22_15), +.matrixC22_16(matrixC22_16), +.matrixC22_17(matrixC22_17), +.matrixC22_18(matrixC22_18), +.matrixC22_19(matrixC22_19), +.matrixC22_20(matrixC22_20), +.matrixC22_21(matrixC22_21), +.matrixC22_22(matrixC22_22), +.matrixC22_23(matrixC22_23), +.matrixC22_24(matrixC22_24), +.matrixC22_25(matrixC22_25), +.matrixC22_26(matrixC22_26), +.matrixC22_27(matrixC22_27), +.matrixC22_28(matrixC22_28), +.matrixC22_29(matrixC22_29), +.matrixC22_30(matrixC22_30), +.matrixC22_31(matrixC22_31), +.matrixC23_0(matrixC23_0), +.matrixC23_1(matrixC23_1), +.matrixC23_2(matrixC23_2), +.matrixC23_3(matrixC23_3), +.matrixC23_4(matrixC23_4), +.matrixC23_5(matrixC23_5), +.matrixC23_6(matrixC23_6), +.matrixC23_7(matrixC23_7), +.matrixC23_8(matrixC23_8), +.matrixC23_9(matrixC23_9), +.matrixC23_10(matrixC23_10), +.matrixC23_11(matrixC23_11), +.matrixC23_12(matrixC23_12), +.matrixC23_13(matrixC23_13), +.matrixC23_14(matrixC23_14), +.matrixC23_15(matrixC23_15), +.matrixC23_16(matrixC23_16), +.matrixC23_17(matrixC23_17), +.matrixC23_18(matrixC23_18), +.matrixC23_19(matrixC23_19), +.matrixC23_20(matrixC23_20), +.matrixC23_21(matrixC23_21), +.matrixC23_22(matrixC23_22), +.matrixC23_23(matrixC23_23), +.matrixC23_24(matrixC23_24), +.matrixC23_25(matrixC23_25), +.matrixC23_26(matrixC23_26), +.matrixC23_27(matrixC23_27), +.matrixC23_28(matrixC23_28), +.matrixC23_29(matrixC23_29), +.matrixC23_30(matrixC23_30), +.matrixC23_31(matrixC23_31), +.matrixC24_0(matrixC24_0), +.matrixC24_1(matrixC24_1), +.matrixC24_2(matrixC24_2), +.matrixC24_3(matrixC24_3), +.matrixC24_4(matrixC24_4), +.matrixC24_5(matrixC24_5), +.matrixC24_6(matrixC24_6), +.matrixC24_7(matrixC24_7), +.matrixC24_8(matrixC24_8), +.matrixC24_9(matrixC24_9), +.matrixC24_10(matrixC24_10), +.matrixC24_11(matrixC24_11), +.matrixC24_12(matrixC24_12), +.matrixC24_13(matrixC24_13), +.matrixC24_14(matrixC24_14), +.matrixC24_15(matrixC24_15), +.matrixC24_16(matrixC24_16), +.matrixC24_17(matrixC24_17), +.matrixC24_18(matrixC24_18), +.matrixC24_19(matrixC24_19), +.matrixC24_20(matrixC24_20), +.matrixC24_21(matrixC24_21), +.matrixC24_22(matrixC24_22), +.matrixC24_23(matrixC24_23), +.matrixC24_24(matrixC24_24), +.matrixC24_25(matrixC24_25), +.matrixC24_26(matrixC24_26), +.matrixC24_27(matrixC24_27), +.matrixC24_28(matrixC24_28), +.matrixC24_29(matrixC24_29), +.matrixC24_30(matrixC24_30), +.matrixC24_31(matrixC24_31), +.matrixC25_0(matrixC25_0), +.matrixC25_1(matrixC25_1), +.matrixC25_2(matrixC25_2), +.matrixC25_3(matrixC25_3), +.matrixC25_4(matrixC25_4), +.matrixC25_5(matrixC25_5), +.matrixC25_6(matrixC25_6), +.matrixC25_7(matrixC25_7), +.matrixC25_8(matrixC25_8), +.matrixC25_9(matrixC25_9), +.matrixC25_10(matrixC25_10), +.matrixC25_11(matrixC25_11), +.matrixC25_12(matrixC25_12), +.matrixC25_13(matrixC25_13), +.matrixC25_14(matrixC25_14), +.matrixC25_15(matrixC25_15), +.matrixC25_16(matrixC25_16), +.matrixC25_17(matrixC25_17), +.matrixC25_18(matrixC25_18), +.matrixC25_19(matrixC25_19), +.matrixC25_20(matrixC25_20), +.matrixC25_21(matrixC25_21), +.matrixC25_22(matrixC25_22), +.matrixC25_23(matrixC25_23), +.matrixC25_24(matrixC25_24), +.matrixC25_25(matrixC25_25), +.matrixC25_26(matrixC25_26), +.matrixC25_27(matrixC25_27), +.matrixC25_28(matrixC25_28), +.matrixC25_29(matrixC25_29), +.matrixC25_30(matrixC25_30), +.matrixC25_31(matrixC25_31), +.matrixC26_0(matrixC26_0), +.matrixC26_1(matrixC26_1), +.matrixC26_2(matrixC26_2), +.matrixC26_3(matrixC26_3), +.matrixC26_4(matrixC26_4), +.matrixC26_5(matrixC26_5), +.matrixC26_6(matrixC26_6), +.matrixC26_7(matrixC26_7), +.matrixC26_8(matrixC26_8), +.matrixC26_9(matrixC26_9), +.matrixC26_10(matrixC26_10), +.matrixC26_11(matrixC26_11), +.matrixC26_12(matrixC26_12), +.matrixC26_13(matrixC26_13), +.matrixC26_14(matrixC26_14), +.matrixC26_15(matrixC26_15), +.matrixC26_16(matrixC26_16), +.matrixC26_17(matrixC26_17), +.matrixC26_18(matrixC26_18), +.matrixC26_19(matrixC26_19), +.matrixC26_20(matrixC26_20), +.matrixC26_21(matrixC26_21), +.matrixC26_22(matrixC26_22), +.matrixC26_23(matrixC26_23), +.matrixC26_24(matrixC26_24), +.matrixC26_25(matrixC26_25), +.matrixC26_26(matrixC26_26), +.matrixC26_27(matrixC26_27), +.matrixC26_28(matrixC26_28), +.matrixC26_29(matrixC26_29), +.matrixC26_30(matrixC26_30), +.matrixC26_31(matrixC26_31), +.matrixC27_0(matrixC27_0), +.matrixC27_1(matrixC27_1), +.matrixC27_2(matrixC27_2), +.matrixC27_3(matrixC27_3), +.matrixC27_4(matrixC27_4), +.matrixC27_5(matrixC27_5), +.matrixC27_6(matrixC27_6), +.matrixC27_7(matrixC27_7), +.matrixC27_8(matrixC27_8), +.matrixC27_9(matrixC27_9), +.matrixC27_10(matrixC27_10), +.matrixC27_11(matrixC27_11), +.matrixC27_12(matrixC27_12), +.matrixC27_13(matrixC27_13), +.matrixC27_14(matrixC27_14), +.matrixC27_15(matrixC27_15), +.matrixC27_16(matrixC27_16), +.matrixC27_17(matrixC27_17), +.matrixC27_18(matrixC27_18), +.matrixC27_19(matrixC27_19), +.matrixC27_20(matrixC27_20), +.matrixC27_21(matrixC27_21), +.matrixC27_22(matrixC27_22), +.matrixC27_23(matrixC27_23), +.matrixC27_24(matrixC27_24), +.matrixC27_25(matrixC27_25), +.matrixC27_26(matrixC27_26), +.matrixC27_27(matrixC27_27), +.matrixC27_28(matrixC27_28), +.matrixC27_29(matrixC27_29), +.matrixC27_30(matrixC27_30), +.matrixC27_31(matrixC27_31), +.matrixC28_0(matrixC28_0), +.matrixC28_1(matrixC28_1), +.matrixC28_2(matrixC28_2), +.matrixC28_3(matrixC28_3), +.matrixC28_4(matrixC28_4), +.matrixC28_5(matrixC28_5), +.matrixC28_6(matrixC28_6), +.matrixC28_7(matrixC28_7), +.matrixC28_8(matrixC28_8), +.matrixC28_9(matrixC28_9), +.matrixC28_10(matrixC28_10), +.matrixC28_11(matrixC28_11), +.matrixC28_12(matrixC28_12), +.matrixC28_13(matrixC28_13), +.matrixC28_14(matrixC28_14), +.matrixC28_15(matrixC28_15), +.matrixC28_16(matrixC28_16), +.matrixC28_17(matrixC28_17), +.matrixC28_18(matrixC28_18), +.matrixC28_19(matrixC28_19), +.matrixC28_20(matrixC28_20), +.matrixC28_21(matrixC28_21), +.matrixC28_22(matrixC28_22), +.matrixC28_23(matrixC28_23), +.matrixC28_24(matrixC28_24), +.matrixC28_25(matrixC28_25), +.matrixC28_26(matrixC28_26), +.matrixC28_27(matrixC28_27), +.matrixC28_28(matrixC28_28), +.matrixC28_29(matrixC28_29), +.matrixC28_30(matrixC28_30), +.matrixC28_31(matrixC28_31), +.matrixC29_0(matrixC29_0), +.matrixC29_1(matrixC29_1), +.matrixC29_2(matrixC29_2), +.matrixC29_3(matrixC29_3), +.matrixC29_4(matrixC29_4), +.matrixC29_5(matrixC29_5), +.matrixC29_6(matrixC29_6), +.matrixC29_7(matrixC29_7), +.matrixC29_8(matrixC29_8), +.matrixC29_9(matrixC29_9), +.matrixC29_10(matrixC29_10), +.matrixC29_11(matrixC29_11), +.matrixC29_12(matrixC29_12), +.matrixC29_13(matrixC29_13), +.matrixC29_14(matrixC29_14), +.matrixC29_15(matrixC29_15), +.matrixC29_16(matrixC29_16), +.matrixC29_17(matrixC29_17), +.matrixC29_18(matrixC29_18), +.matrixC29_19(matrixC29_19), +.matrixC29_20(matrixC29_20), +.matrixC29_21(matrixC29_21), +.matrixC29_22(matrixC29_22), +.matrixC29_23(matrixC29_23), +.matrixC29_24(matrixC29_24), +.matrixC29_25(matrixC29_25), +.matrixC29_26(matrixC29_26), +.matrixC29_27(matrixC29_27), +.matrixC29_28(matrixC29_28), +.matrixC29_29(matrixC29_29), +.matrixC29_30(matrixC29_30), +.matrixC29_31(matrixC29_31), +.matrixC30_0(matrixC30_0), +.matrixC30_1(matrixC30_1), +.matrixC30_2(matrixC30_2), +.matrixC30_3(matrixC30_3), +.matrixC30_4(matrixC30_4), +.matrixC30_5(matrixC30_5), +.matrixC30_6(matrixC30_6), +.matrixC30_7(matrixC30_7), +.matrixC30_8(matrixC30_8), +.matrixC30_9(matrixC30_9), +.matrixC30_10(matrixC30_10), +.matrixC30_11(matrixC30_11), +.matrixC30_12(matrixC30_12), +.matrixC30_13(matrixC30_13), +.matrixC30_14(matrixC30_14), +.matrixC30_15(matrixC30_15), +.matrixC30_16(matrixC30_16), +.matrixC30_17(matrixC30_17), +.matrixC30_18(matrixC30_18), +.matrixC30_19(matrixC30_19), +.matrixC30_20(matrixC30_20), +.matrixC30_21(matrixC30_21), +.matrixC30_22(matrixC30_22), +.matrixC30_23(matrixC30_23), +.matrixC30_24(matrixC30_24), +.matrixC30_25(matrixC30_25), +.matrixC30_26(matrixC30_26), +.matrixC30_27(matrixC30_27), +.matrixC30_28(matrixC30_28), +.matrixC30_29(matrixC30_29), +.matrixC30_30(matrixC30_30), +.matrixC30_31(matrixC30_31), +.matrixC31_0(matrixC31_0), +.matrixC31_1(matrixC31_1), +.matrixC31_2(matrixC31_2), +.matrixC31_3(matrixC31_3), +.matrixC31_4(matrixC31_4), +.matrixC31_5(matrixC31_5), +.matrixC31_6(matrixC31_6), +.matrixC31_7(matrixC31_7), +.matrixC31_8(matrixC31_8), +.matrixC31_9(matrixC31_9), +.matrixC31_10(matrixC31_10), +.matrixC31_11(matrixC31_11), +.matrixC31_12(matrixC31_12), +.matrixC31_13(matrixC31_13), +.matrixC31_14(matrixC31_14), +.matrixC31_15(matrixC31_15), +.matrixC31_16(matrixC31_16), +.matrixC31_17(matrixC31_17), +.matrixC31_18(matrixC31_18), +.matrixC31_19(matrixC31_19), +.matrixC31_20(matrixC31_20), +.matrixC31_21(matrixC31_21), +.matrixC31_22(matrixC31_22), +.matrixC31_23(matrixC31_23), +.matrixC31_24(matrixC31_24), +.matrixC31_25(matrixC31_25), +.matrixC31_26(matrixC31_26), +.matrixC31_27(matrixC31_27), +.matrixC31_28(matrixC31_28), +.matrixC31_29(matrixC31_29), +.matrixC31_30(matrixC31_30), +.matrixC31_31(matrixC31_31), + +.clk(clk), +.reset(reset) +); + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +systolic_pe_matrix u_systolic_pe_matrix( +.clk(clk), +.reset(reset), +.pe_reset(pe_reset), +.a0(a0), +.a1(a1), +.a2(a2), +.a3(a3), +.a4(a4), +.a5(a5), +.a6(a6), +.a7(a7), +.a8(a8), +.a9(a9), +.a10(a10), +.a11(a11), +.a12(a12), +.a13(a13), +.a14(a14), +.a15(a15), +.a16(a16), +.a17(a17), +.a18(a18), +.a19(a19), +.a20(a20), +.a21(a21), +.a22(a22), +.a23(a23), +.a24(a24), +.a25(a25), +.a26(a26), +.a27(a27), +.a28(a28), +.a29(a29), +.a30(a30), +.a31(a31), +.b0(b0), +.b1(b1), +.b2(b2), +.b3(b3), +.b4(b4), +.b5(b5), +.b6(b6), +.b7(b7), +.b8(b8), +.b9(b9), +.b10(b10), +.b11(b11), +.b12(b12), +.b13(b13), +.b14(b14), +.b15(b15), +.b16(b16), +.b17(b17), +.b18(b18), +.b19(b19), +.b20(b20), +.b21(b21), +.b22(b22), +.b23(b23), +.b24(b24), +.b25(b25), +.b26(b26), +.b27(b27), +.b28(b28), +.b29(b29), +.b30(b30), +.b31(b31), +.matrixC0_0(matrixC0_0), +.matrixC0_1(matrixC0_1), +.matrixC0_2(matrixC0_2), +.matrixC0_3(matrixC0_3), +.matrixC0_4(matrixC0_4), +.matrixC0_5(matrixC0_5), +.matrixC0_6(matrixC0_6), +.matrixC0_7(matrixC0_7), +.matrixC0_8(matrixC0_8), +.matrixC0_9(matrixC0_9), +.matrixC0_10(matrixC0_10), +.matrixC0_11(matrixC0_11), +.matrixC0_12(matrixC0_12), +.matrixC0_13(matrixC0_13), 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+.matrixC17_31(matrixC17_31), +.matrixC18_0(matrixC18_0), +.matrixC18_1(matrixC18_1), +.matrixC18_2(matrixC18_2), +.matrixC18_3(matrixC18_3), +.matrixC18_4(matrixC18_4), +.matrixC18_5(matrixC18_5), +.matrixC18_6(matrixC18_6), +.matrixC18_7(matrixC18_7), +.matrixC18_8(matrixC18_8), +.matrixC18_9(matrixC18_9), +.matrixC18_10(matrixC18_10), +.matrixC18_11(matrixC18_11), +.matrixC18_12(matrixC18_12), +.matrixC18_13(matrixC18_13), +.matrixC18_14(matrixC18_14), +.matrixC18_15(matrixC18_15), +.matrixC18_16(matrixC18_16), +.matrixC18_17(matrixC18_17), +.matrixC18_18(matrixC18_18), +.matrixC18_19(matrixC18_19), +.matrixC18_20(matrixC18_20), +.matrixC18_21(matrixC18_21), +.matrixC18_22(matrixC18_22), +.matrixC18_23(matrixC18_23), +.matrixC18_24(matrixC18_24), +.matrixC18_25(matrixC18_25), +.matrixC18_26(matrixC18_26), +.matrixC18_27(matrixC18_27), +.matrixC18_28(matrixC18_28), +.matrixC18_29(matrixC18_29), +.matrixC18_30(matrixC18_30), +.matrixC18_31(matrixC18_31), +.matrixC19_0(matrixC19_0), +.matrixC19_1(matrixC19_1), +.matrixC19_2(matrixC19_2), +.matrixC19_3(matrixC19_3), +.matrixC19_4(matrixC19_4), +.matrixC19_5(matrixC19_5), +.matrixC19_6(matrixC19_6), +.matrixC19_7(matrixC19_7), +.matrixC19_8(matrixC19_8), +.matrixC19_9(matrixC19_9), +.matrixC19_10(matrixC19_10), +.matrixC19_11(matrixC19_11), +.matrixC19_12(matrixC19_12), +.matrixC19_13(matrixC19_13), +.matrixC19_14(matrixC19_14), +.matrixC19_15(matrixC19_15), +.matrixC19_16(matrixC19_16), +.matrixC19_17(matrixC19_17), +.matrixC19_18(matrixC19_18), +.matrixC19_19(matrixC19_19), +.matrixC19_20(matrixC19_20), +.matrixC19_21(matrixC19_21), +.matrixC19_22(matrixC19_22), +.matrixC19_23(matrixC19_23), +.matrixC19_24(matrixC19_24), +.matrixC19_25(matrixC19_25), +.matrixC19_26(matrixC19_26), +.matrixC19_27(matrixC19_27), +.matrixC19_28(matrixC19_28), +.matrixC19_29(matrixC19_29), +.matrixC19_30(matrixC19_30), +.matrixC19_31(matrixC19_31), +.matrixC20_0(matrixC20_0), +.matrixC20_1(matrixC20_1), +.matrixC20_2(matrixC20_2), +.matrixC20_3(matrixC20_3), +.matrixC20_4(matrixC20_4), +.matrixC20_5(matrixC20_5), +.matrixC20_6(matrixC20_6), +.matrixC20_7(matrixC20_7), +.matrixC20_8(matrixC20_8), +.matrixC20_9(matrixC20_9), +.matrixC20_10(matrixC20_10), +.matrixC20_11(matrixC20_11), +.matrixC20_12(matrixC20_12), +.matrixC20_13(matrixC20_13), +.matrixC20_14(matrixC20_14), +.matrixC20_15(matrixC20_15), +.matrixC20_16(matrixC20_16), +.matrixC20_17(matrixC20_17), +.matrixC20_18(matrixC20_18), +.matrixC20_19(matrixC20_19), +.matrixC20_20(matrixC20_20), +.matrixC20_21(matrixC20_21), +.matrixC20_22(matrixC20_22), +.matrixC20_23(matrixC20_23), +.matrixC20_24(matrixC20_24), +.matrixC20_25(matrixC20_25), +.matrixC20_26(matrixC20_26), +.matrixC20_27(matrixC20_27), +.matrixC20_28(matrixC20_28), +.matrixC20_29(matrixC20_29), +.matrixC20_30(matrixC20_30), +.matrixC20_31(matrixC20_31), +.matrixC21_0(matrixC21_0), +.matrixC21_1(matrixC21_1), +.matrixC21_2(matrixC21_2), +.matrixC21_3(matrixC21_3), +.matrixC21_4(matrixC21_4), +.matrixC21_5(matrixC21_5), +.matrixC21_6(matrixC21_6), +.matrixC21_7(matrixC21_7), +.matrixC21_8(matrixC21_8), +.matrixC21_9(matrixC21_9), +.matrixC21_10(matrixC21_10), +.matrixC21_11(matrixC21_11), +.matrixC21_12(matrixC21_12), +.matrixC21_13(matrixC21_13), +.matrixC21_14(matrixC21_14), +.matrixC21_15(matrixC21_15), +.matrixC21_16(matrixC21_16), +.matrixC21_17(matrixC21_17), +.matrixC21_18(matrixC21_18), +.matrixC21_19(matrixC21_19), +.matrixC21_20(matrixC21_20), +.matrixC21_21(matrixC21_21), +.matrixC21_22(matrixC21_22), +.matrixC21_23(matrixC21_23), +.matrixC21_24(matrixC21_24), +.matrixC21_25(matrixC21_25), +.matrixC21_26(matrixC21_26), +.matrixC21_27(matrixC21_27), +.matrixC21_28(matrixC21_28), +.matrixC21_29(matrixC21_29), +.matrixC21_30(matrixC21_30), +.matrixC21_31(matrixC21_31), +.matrixC22_0(matrixC22_0), +.matrixC22_1(matrixC22_1), +.matrixC22_2(matrixC22_2), +.matrixC22_3(matrixC22_3), +.matrixC22_4(matrixC22_4), +.matrixC22_5(matrixC22_5), +.matrixC22_6(matrixC22_6), +.matrixC22_7(matrixC22_7), +.matrixC22_8(matrixC22_8), +.matrixC22_9(matrixC22_9), +.matrixC22_10(matrixC22_10), +.matrixC22_11(matrixC22_11), +.matrixC22_12(matrixC22_12), +.matrixC22_13(matrixC22_13), +.matrixC22_14(matrixC22_14), +.matrixC22_15(matrixC22_15), +.matrixC22_16(matrixC22_16), +.matrixC22_17(matrixC22_17), +.matrixC22_18(matrixC22_18), +.matrixC22_19(matrixC22_19), +.matrixC22_20(matrixC22_20), +.matrixC22_21(matrixC22_21), +.matrixC22_22(matrixC22_22), +.matrixC22_23(matrixC22_23), +.matrixC22_24(matrixC22_24), +.matrixC22_25(matrixC22_25), +.matrixC22_26(matrixC22_26), +.matrixC22_27(matrixC22_27), +.matrixC22_28(matrixC22_28), +.matrixC22_29(matrixC22_29), +.matrixC22_30(matrixC22_30), +.matrixC22_31(matrixC22_31), +.matrixC23_0(matrixC23_0), +.matrixC23_1(matrixC23_1), +.matrixC23_2(matrixC23_2), +.matrixC23_3(matrixC23_3), +.matrixC23_4(matrixC23_4), +.matrixC23_5(matrixC23_5), +.matrixC23_6(matrixC23_6), +.matrixC23_7(matrixC23_7), +.matrixC23_8(matrixC23_8), +.matrixC23_9(matrixC23_9), +.matrixC23_10(matrixC23_10), +.matrixC23_11(matrixC23_11), +.matrixC23_12(matrixC23_12), +.matrixC23_13(matrixC23_13), +.matrixC23_14(matrixC23_14), +.matrixC23_15(matrixC23_15), +.matrixC23_16(matrixC23_16), +.matrixC23_17(matrixC23_17), +.matrixC23_18(matrixC23_18), +.matrixC23_19(matrixC23_19), +.matrixC23_20(matrixC23_20), +.matrixC23_21(matrixC23_21), +.matrixC23_22(matrixC23_22), +.matrixC23_23(matrixC23_23), +.matrixC23_24(matrixC23_24), +.matrixC23_25(matrixC23_25), +.matrixC23_26(matrixC23_26), +.matrixC23_27(matrixC23_27), +.matrixC23_28(matrixC23_28), +.matrixC23_29(matrixC23_29), +.matrixC23_30(matrixC23_30), +.matrixC23_31(matrixC23_31), +.matrixC24_0(matrixC24_0), +.matrixC24_1(matrixC24_1), +.matrixC24_2(matrixC24_2), +.matrixC24_3(matrixC24_3), +.matrixC24_4(matrixC24_4), +.matrixC24_5(matrixC24_5), +.matrixC24_6(matrixC24_6), +.matrixC24_7(matrixC24_7), +.matrixC24_8(matrixC24_8), +.matrixC24_9(matrixC24_9), +.matrixC24_10(matrixC24_10), +.matrixC24_11(matrixC24_11), +.matrixC24_12(matrixC24_12), +.matrixC24_13(matrixC24_13), +.matrixC24_14(matrixC24_14), +.matrixC24_15(matrixC24_15), +.matrixC24_16(matrixC24_16), +.matrixC24_17(matrixC24_17), +.matrixC24_18(matrixC24_18), +.matrixC24_19(matrixC24_19), +.matrixC24_20(matrixC24_20), +.matrixC24_21(matrixC24_21), +.matrixC24_22(matrixC24_22), +.matrixC24_23(matrixC24_23), +.matrixC24_24(matrixC24_24), +.matrixC24_25(matrixC24_25), +.matrixC24_26(matrixC24_26), +.matrixC24_27(matrixC24_27), +.matrixC24_28(matrixC24_28), +.matrixC24_29(matrixC24_29), +.matrixC24_30(matrixC24_30), +.matrixC24_31(matrixC24_31), +.matrixC25_0(matrixC25_0), +.matrixC25_1(matrixC25_1), +.matrixC25_2(matrixC25_2), +.matrixC25_3(matrixC25_3), +.matrixC25_4(matrixC25_4), +.matrixC25_5(matrixC25_5), +.matrixC25_6(matrixC25_6), +.matrixC25_7(matrixC25_7), +.matrixC25_8(matrixC25_8), +.matrixC25_9(matrixC25_9), +.matrixC25_10(matrixC25_10), +.matrixC25_11(matrixC25_11), +.matrixC25_12(matrixC25_12), +.matrixC25_13(matrixC25_13), +.matrixC25_14(matrixC25_14), +.matrixC25_15(matrixC25_15), +.matrixC25_16(matrixC25_16), +.matrixC25_17(matrixC25_17), +.matrixC25_18(matrixC25_18), +.matrixC25_19(matrixC25_19), +.matrixC25_20(matrixC25_20), +.matrixC25_21(matrixC25_21), +.matrixC25_22(matrixC25_22), +.matrixC25_23(matrixC25_23), +.matrixC25_24(matrixC25_24), +.matrixC25_25(matrixC25_25), +.matrixC25_26(matrixC25_26), +.matrixC25_27(matrixC25_27), +.matrixC25_28(matrixC25_28), +.matrixC25_29(matrixC25_29), +.matrixC25_30(matrixC25_30), +.matrixC25_31(matrixC25_31), +.matrixC26_0(matrixC26_0), +.matrixC26_1(matrixC26_1), +.matrixC26_2(matrixC26_2), +.matrixC26_3(matrixC26_3), +.matrixC26_4(matrixC26_4), +.matrixC26_5(matrixC26_5), +.matrixC26_6(matrixC26_6), +.matrixC26_7(matrixC26_7), +.matrixC26_8(matrixC26_8), +.matrixC26_9(matrixC26_9), +.matrixC26_10(matrixC26_10), +.matrixC26_11(matrixC26_11), +.matrixC26_12(matrixC26_12), +.matrixC26_13(matrixC26_13), +.matrixC26_14(matrixC26_14), +.matrixC26_15(matrixC26_15), +.matrixC26_16(matrixC26_16), +.matrixC26_17(matrixC26_17), +.matrixC26_18(matrixC26_18), +.matrixC26_19(matrixC26_19), +.matrixC26_20(matrixC26_20), +.matrixC26_21(matrixC26_21), +.matrixC26_22(matrixC26_22), +.matrixC26_23(matrixC26_23), +.matrixC26_24(matrixC26_24), +.matrixC26_25(matrixC26_25), +.matrixC26_26(matrixC26_26), +.matrixC26_27(matrixC26_27), +.matrixC26_28(matrixC26_28), +.matrixC26_29(matrixC26_29), +.matrixC26_30(matrixC26_30), +.matrixC26_31(matrixC26_31), +.matrixC27_0(matrixC27_0), +.matrixC27_1(matrixC27_1), +.matrixC27_2(matrixC27_2), +.matrixC27_3(matrixC27_3), +.matrixC27_4(matrixC27_4), +.matrixC27_5(matrixC27_5), +.matrixC27_6(matrixC27_6), +.matrixC27_7(matrixC27_7), +.matrixC27_8(matrixC27_8), +.matrixC27_9(matrixC27_9), +.matrixC27_10(matrixC27_10), +.matrixC27_11(matrixC27_11), +.matrixC27_12(matrixC27_12), +.matrixC27_13(matrixC27_13), +.matrixC27_14(matrixC27_14), +.matrixC27_15(matrixC27_15), +.matrixC27_16(matrixC27_16), +.matrixC27_17(matrixC27_17), +.matrixC27_18(matrixC27_18), +.matrixC27_19(matrixC27_19), +.matrixC27_20(matrixC27_20), +.matrixC27_21(matrixC27_21), +.matrixC27_22(matrixC27_22), +.matrixC27_23(matrixC27_23), +.matrixC27_24(matrixC27_24), +.matrixC27_25(matrixC27_25), +.matrixC27_26(matrixC27_26), +.matrixC27_27(matrixC27_27), +.matrixC27_28(matrixC27_28), +.matrixC27_29(matrixC27_29), +.matrixC27_30(matrixC27_30), +.matrixC27_31(matrixC27_31), +.matrixC28_0(matrixC28_0), +.matrixC28_1(matrixC28_1), +.matrixC28_2(matrixC28_2), +.matrixC28_3(matrixC28_3), +.matrixC28_4(matrixC28_4), +.matrixC28_5(matrixC28_5), +.matrixC28_6(matrixC28_6), +.matrixC28_7(matrixC28_7), +.matrixC28_8(matrixC28_8), +.matrixC28_9(matrixC28_9), +.matrixC28_10(matrixC28_10), +.matrixC28_11(matrixC28_11), +.matrixC28_12(matrixC28_12), +.matrixC28_13(matrixC28_13), +.matrixC28_14(matrixC28_14), +.matrixC28_15(matrixC28_15), +.matrixC28_16(matrixC28_16), +.matrixC28_17(matrixC28_17), +.matrixC28_18(matrixC28_18), +.matrixC28_19(matrixC28_19), +.matrixC28_20(matrixC28_20), +.matrixC28_21(matrixC28_21), +.matrixC28_22(matrixC28_22), +.matrixC28_23(matrixC28_23), +.matrixC28_24(matrixC28_24), +.matrixC28_25(matrixC28_25), +.matrixC28_26(matrixC28_26), +.matrixC28_27(matrixC28_27), +.matrixC28_28(matrixC28_28), +.matrixC28_29(matrixC28_29), +.matrixC28_30(matrixC28_30), +.matrixC28_31(matrixC28_31), +.matrixC29_0(matrixC29_0), +.matrixC29_1(matrixC29_1), +.matrixC29_2(matrixC29_2), +.matrixC29_3(matrixC29_3), +.matrixC29_4(matrixC29_4), +.matrixC29_5(matrixC29_5), +.matrixC29_6(matrixC29_6), +.matrixC29_7(matrixC29_7), +.matrixC29_8(matrixC29_8), +.matrixC29_9(matrixC29_9), +.matrixC29_10(matrixC29_10), +.matrixC29_11(matrixC29_11), +.matrixC29_12(matrixC29_12), +.matrixC29_13(matrixC29_13), +.matrixC29_14(matrixC29_14), +.matrixC29_15(matrixC29_15), +.matrixC29_16(matrixC29_16), +.matrixC29_17(matrixC29_17), +.matrixC29_18(matrixC29_18), +.matrixC29_19(matrixC29_19), +.matrixC29_20(matrixC29_20), +.matrixC29_21(matrixC29_21), +.matrixC29_22(matrixC29_22), +.matrixC29_23(matrixC29_23), +.matrixC29_24(matrixC29_24), +.matrixC29_25(matrixC29_25), +.matrixC29_26(matrixC29_26), +.matrixC29_27(matrixC29_27), +.matrixC29_28(matrixC29_28), +.matrixC29_29(matrixC29_29), +.matrixC29_30(matrixC29_30), +.matrixC29_31(matrixC29_31), +.matrixC30_0(matrixC30_0), +.matrixC30_1(matrixC30_1), +.matrixC30_2(matrixC30_2), +.matrixC30_3(matrixC30_3), +.matrixC30_4(matrixC30_4), +.matrixC30_5(matrixC30_5), +.matrixC30_6(matrixC30_6), +.matrixC30_7(matrixC30_7), +.matrixC30_8(matrixC30_8), +.matrixC30_9(matrixC30_9), +.matrixC30_10(matrixC30_10), +.matrixC30_11(matrixC30_11), +.matrixC30_12(matrixC30_12), +.matrixC30_13(matrixC30_13), +.matrixC30_14(matrixC30_14), +.matrixC30_15(matrixC30_15), +.matrixC30_16(matrixC30_16), +.matrixC30_17(matrixC30_17), +.matrixC30_18(matrixC30_18), +.matrixC30_19(matrixC30_19), +.matrixC30_20(matrixC30_20), +.matrixC30_21(matrixC30_21), +.matrixC30_22(matrixC30_22), +.matrixC30_23(matrixC30_23), +.matrixC30_24(matrixC30_24), +.matrixC30_25(matrixC30_25), +.matrixC30_26(matrixC30_26), +.matrixC30_27(matrixC30_27), +.matrixC30_28(matrixC30_28), +.matrixC30_29(matrixC30_29), +.matrixC30_30(matrixC30_30), +.matrixC30_31(matrixC30_31), +.matrixC31_0(matrixC31_0), +.matrixC31_1(matrixC31_1), +.matrixC31_2(matrixC31_2), +.matrixC31_3(matrixC31_3), +.matrixC31_4(matrixC31_4), +.matrixC31_5(matrixC31_5), +.matrixC31_6(matrixC31_6), +.matrixC31_7(matrixC31_7), +.matrixC31_8(matrixC31_8), +.matrixC31_9(matrixC31_9), +.matrixC31_10(matrixC31_10), +.matrixC31_11(matrixC31_11), +.matrixC31_12(matrixC31_12), +.matrixC31_13(matrixC31_13), +.matrixC31_14(matrixC31_14), +.matrixC31_15(matrixC31_15), +.matrixC31_16(matrixC31_16), +.matrixC31_17(matrixC31_17), +.matrixC31_18(matrixC31_18), +.matrixC31_19(matrixC31_19), +.matrixC31_20(matrixC31_20), +.matrixC31_21(matrixC31_21), +.matrixC31_22(matrixC31_22), +.matrixC31_23(matrixC31_23), +.matrixC31_24(matrixC31_24), +.matrixC31_25(matrixC31_25), +.matrixC31_26(matrixC31_26), +.matrixC31_27(matrixC31_27), +.matrixC31_28(matrixC31_28), +.matrixC31_29(matrixC31_29), +.matrixC31_30(matrixC31_30), +.matrixC31_31(matrixC31_31), + +.a_data_out(a_data_out), +.b_data_out(b_data_out) +); + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Output logic +////////////////////////////////////////////////////////////////////////// +module output_logic( +start_mat_mul, +done_mat_mul, +address_mat_c, +address_stride_c, +c_data_in, +c_data_out, //Data values going out to next matmul - systolic shifting +c_addr, +c_data_available, +clk_cnt, +row_latch_en, +final_mat_mul_size, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC0_20, +matrixC0_21, +matrixC0_22, +matrixC0_23, +matrixC0_24, +matrixC0_25, +matrixC0_26, +matrixC0_27, +matrixC0_28, +matrixC0_29, +matrixC0_30, +matrixC0_31, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC1_20, +matrixC1_21, +matrixC1_22, +matrixC1_23, +matrixC1_24, +matrixC1_25, +matrixC1_26, +matrixC1_27, +matrixC1_28, +matrixC1_29, +matrixC1_30, +matrixC1_31, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC2_20, +matrixC2_21, +matrixC2_22, +matrixC2_23, +matrixC2_24, +matrixC2_25, +matrixC2_26, +matrixC2_27, +matrixC2_28, +matrixC2_29, +matrixC2_30, +matrixC2_31, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC3_20, +matrixC3_21, +matrixC3_22, +matrixC3_23, +matrixC3_24, +matrixC3_25, +matrixC3_26, +matrixC3_27, +matrixC3_28, +matrixC3_29, +matrixC3_30, +matrixC3_31, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC4_20, +matrixC4_21, +matrixC4_22, +matrixC4_23, +matrixC4_24, +matrixC4_25, +matrixC4_26, +matrixC4_27, +matrixC4_28, +matrixC4_29, +matrixC4_30, +matrixC4_31, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC5_20, +matrixC5_21, +matrixC5_22, +matrixC5_23, +matrixC5_24, +matrixC5_25, +matrixC5_26, +matrixC5_27, +matrixC5_28, +matrixC5_29, +matrixC5_30, +matrixC5_31, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC6_20, +matrixC6_21, +matrixC6_22, +matrixC6_23, +matrixC6_24, +matrixC6_25, +matrixC6_26, +matrixC6_27, +matrixC6_28, +matrixC6_29, +matrixC6_30, +matrixC6_31, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC7_20, +matrixC7_21, +matrixC7_22, +matrixC7_23, +matrixC7_24, +matrixC7_25, +matrixC7_26, +matrixC7_27, +matrixC7_28, +matrixC7_29, +matrixC7_30, +matrixC7_31, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC8_20, +matrixC8_21, +matrixC8_22, +matrixC8_23, +matrixC8_24, +matrixC8_25, +matrixC8_26, +matrixC8_27, +matrixC8_28, +matrixC8_29, +matrixC8_30, +matrixC8_31, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC9_20, +matrixC9_21, +matrixC9_22, +matrixC9_23, +matrixC9_24, +matrixC9_25, +matrixC9_26, +matrixC9_27, +matrixC9_28, +matrixC9_29, +matrixC9_30, +matrixC9_31, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC10_20, +matrixC10_21, +matrixC10_22, +matrixC10_23, +matrixC10_24, +matrixC10_25, +matrixC10_26, +matrixC10_27, +matrixC10_28, +matrixC10_29, +matrixC10_30, +matrixC10_31, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC11_20, +matrixC11_21, +matrixC11_22, +matrixC11_23, +matrixC11_24, +matrixC11_25, +matrixC11_26, +matrixC11_27, +matrixC11_28, +matrixC11_29, +matrixC11_30, +matrixC11_31, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC12_20, +matrixC12_21, +matrixC12_22, +matrixC12_23, +matrixC12_24, +matrixC12_25, +matrixC12_26, +matrixC12_27, +matrixC12_28, +matrixC12_29, +matrixC12_30, +matrixC12_31, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC13_20, +matrixC13_21, +matrixC13_22, +matrixC13_23, +matrixC13_24, +matrixC13_25, +matrixC13_26, +matrixC13_27, +matrixC13_28, +matrixC13_29, +matrixC13_30, +matrixC13_31, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC14_20, +matrixC14_21, +matrixC14_22, +matrixC14_23, +matrixC14_24, +matrixC14_25, +matrixC14_26, +matrixC14_27, +matrixC14_28, +matrixC14_29, +matrixC14_30, +matrixC14_31, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC15_20, +matrixC15_21, +matrixC15_22, +matrixC15_23, +matrixC15_24, +matrixC15_25, +matrixC15_26, +matrixC15_27, +matrixC15_28, +matrixC15_29, +matrixC15_30, +matrixC15_31, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC16_20, +matrixC16_21, +matrixC16_22, +matrixC16_23, +matrixC16_24, +matrixC16_25, +matrixC16_26, +matrixC16_27, +matrixC16_28, +matrixC16_29, +matrixC16_30, +matrixC16_31, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC17_20, +matrixC17_21, +matrixC17_22, +matrixC17_23, +matrixC17_24, +matrixC17_25, +matrixC17_26, +matrixC17_27, +matrixC17_28, +matrixC17_29, +matrixC17_30, +matrixC17_31, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC18_20, +matrixC18_21, +matrixC18_22, +matrixC18_23, +matrixC18_24, +matrixC18_25, +matrixC18_26, +matrixC18_27, +matrixC18_28, +matrixC18_29, +matrixC18_30, +matrixC18_31, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, +matrixC19_20, +matrixC19_21, +matrixC19_22, +matrixC19_23, +matrixC19_24, +matrixC19_25, +matrixC19_26, +matrixC19_27, +matrixC19_28, +matrixC19_29, +matrixC19_30, +matrixC19_31, +matrixC20_0, +matrixC20_1, +matrixC20_2, +matrixC20_3, +matrixC20_4, +matrixC20_5, +matrixC20_6, +matrixC20_7, +matrixC20_8, +matrixC20_9, +matrixC20_10, +matrixC20_11, +matrixC20_12, +matrixC20_13, +matrixC20_14, +matrixC20_15, +matrixC20_16, +matrixC20_17, +matrixC20_18, +matrixC20_19, +matrixC20_20, +matrixC20_21, +matrixC20_22, +matrixC20_23, +matrixC20_24, +matrixC20_25, +matrixC20_26, +matrixC20_27, +matrixC20_28, +matrixC20_29, +matrixC20_30, +matrixC20_31, +matrixC21_0, +matrixC21_1, +matrixC21_2, +matrixC21_3, +matrixC21_4, +matrixC21_5, +matrixC21_6, +matrixC21_7, +matrixC21_8, +matrixC21_9, +matrixC21_10, +matrixC21_11, +matrixC21_12, +matrixC21_13, +matrixC21_14, +matrixC21_15, +matrixC21_16, +matrixC21_17, +matrixC21_18, +matrixC21_19, +matrixC21_20, +matrixC21_21, +matrixC21_22, +matrixC21_23, +matrixC21_24, +matrixC21_25, +matrixC21_26, +matrixC21_27, +matrixC21_28, +matrixC21_29, +matrixC21_30, +matrixC21_31, +matrixC22_0, +matrixC22_1, +matrixC22_2, +matrixC22_3, +matrixC22_4, +matrixC22_5, +matrixC22_6, +matrixC22_7, +matrixC22_8, +matrixC22_9, +matrixC22_10, +matrixC22_11, +matrixC22_12, +matrixC22_13, +matrixC22_14, +matrixC22_15, +matrixC22_16, +matrixC22_17, +matrixC22_18, +matrixC22_19, +matrixC22_20, +matrixC22_21, +matrixC22_22, +matrixC22_23, +matrixC22_24, +matrixC22_25, +matrixC22_26, +matrixC22_27, +matrixC22_28, +matrixC22_29, +matrixC22_30, +matrixC22_31, +matrixC23_0, +matrixC23_1, +matrixC23_2, +matrixC23_3, +matrixC23_4, +matrixC23_5, +matrixC23_6, +matrixC23_7, +matrixC23_8, +matrixC23_9, +matrixC23_10, +matrixC23_11, +matrixC23_12, +matrixC23_13, +matrixC23_14, +matrixC23_15, +matrixC23_16, +matrixC23_17, +matrixC23_18, +matrixC23_19, +matrixC23_20, +matrixC23_21, +matrixC23_22, +matrixC23_23, +matrixC23_24, +matrixC23_25, +matrixC23_26, +matrixC23_27, +matrixC23_28, +matrixC23_29, +matrixC23_30, +matrixC23_31, +matrixC24_0, +matrixC24_1, +matrixC24_2, +matrixC24_3, +matrixC24_4, +matrixC24_5, +matrixC24_6, +matrixC24_7, +matrixC24_8, +matrixC24_9, +matrixC24_10, +matrixC24_11, +matrixC24_12, +matrixC24_13, +matrixC24_14, +matrixC24_15, +matrixC24_16, +matrixC24_17, +matrixC24_18, +matrixC24_19, +matrixC24_20, +matrixC24_21, +matrixC24_22, +matrixC24_23, +matrixC24_24, +matrixC24_25, +matrixC24_26, +matrixC24_27, +matrixC24_28, +matrixC24_29, +matrixC24_30, +matrixC24_31, +matrixC25_0, +matrixC25_1, +matrixC25_2, +matrixC25_3, +matrixC25_4, +matrixC25_5, +matrixC25_6, +matrixC25_7, +matrixC25_8, +matrixC25_9, +matrixC25_10, +matrixC25_11, +matrixC25_12, +matrixC25_13, +matrixC25_14, +matrixC25_15, +matrixC25_16, +matrixC25_17, +matrixC25_18, +matrixC25_19, +matrixC25_20, +matrixC25_21, +matrixC25_22, +matrixC25_23, +matrixC25_24, +matrixC25_25, +matrixC25_26, +matrixC25_27, +matrixC25_28, +matrixC25_29, +matrixC25_30, +matrixC25_31, +matrixC26_0, +matrixC26_1, +matrixC26_2, +matrixC26_3, +matrixC26_4, +matrixC26_5, +matrixC26_6, +matrixC26_7, +matrixC26_8, +matrixC26_9, +matrixC26_10, +matrixC26_11, +matrixC26_12, +matrixC26_13, +matrixC26_14, +matrixC26_15, +matrixC26_16, +matrixC26_17, +matrixC26_18, +matrixC26_19, +matrixC26_20, +matrixC26_21, +matrixC26_22, +matrixC26_23, +matrixC26_24, +matrixC26_25, +matrixC26_26, +matrixC26_27, +matrixC26_28, +matrixC26_29, +matrixC26_30, +matrixC26_31, +matrixC27_0, +matrixC27_1, +matrixC27_2, +matrixC27_3, +matrixC27_4, +matrixC27_5, +matrixC27_6, +matrixC27_7, +matrixC27_8, +matrixC27_9, +matrixC27_10, +matrixC27_11, +matrixC27_12, +matrixC27_13, +matrixC27_14, +matrixC27_15, +matrixC27_16, +matrixC27_17, +matrixC27_18, +matrixC27_19, +matrixC27_20, +matrixC27_21, +matrixC27_22, +matrixC27_23, +matrixC27_24, +matrixC27_25, +matrixC27_26, +matrixC27_27, +matrixC27_28, +matrixC27_29, +matrixC27_30, +matrixC27_31, +matrixC28_0, +matrixC28_1, +matrixC28_2, +matrixC28_3, +matrixC28_4, +matrixC28_5, +matrixC28_6, +matrixC28_7, +matrixC28_8, +matrixC28_9, +matrixC28_10, +matrixC28_11, +matrixC28_12, +matrixC28_13, +matrixC28_14, +matrixC28_15, +matrixC28_16, +matrixC28_17, +matrixC28_18, +matrixC28_19, +matrixC28_20, +matrixC28_21, +matrixC28_22, +matrixC28_23, +matrixC28_24, +matrixC28_25, +matrixC28_26, +matrixC28_27, +matrixC28_28, +matrixC28_29, +matrixC28_30, +matrixC28_31, +matrixC29_0, +matrixC29_1, +matrixC29_2, +matrixC29_3, +matrixC29_4, +matrixC29_5, +matrixC29_6, +matrixC29_7, +matrixC29_8, +matrixC29_9, +matrixC29_10, +matrixC29_11, +matrixC29_12, +matrixC29_13, +matrixC29_14, +matrixC29_15, +matrixC29_16, +matrixC29_17, +matrixC29_18, +matrixC29_19, +matrixC29_20, +matrixC29_21, +matrixC29_22, +matrixC29_23, +matrixC29_24, +matrixC29_25, +matrixC29_26, +matrixC29_27, +matrixC29_28, +matrixC29_29, +matrixC29_30, +matrixC29_31, +matrixC30_0, +matrixC30_1, +matrixC30_2, +matrixC30_3, +matrixC30_4, +matrixC30_5, +matrixC30_6, +matrixC30_7, +matrixC30_8, +matrixC30_9, +matrixC30_10, +matrixC30_11, +matrixC30_12, +matrixC30_13, +matrixC30_14, +matrixC30_15, +matrixC30_16, +matrixC30_17, +matrixC30_18, +matrixC30_19, +matrixC30_20, +matrixC30_21, +matrixC30_22, +matrixC30_23, +matrixC30_24, +matrixC30_25, +matrixC30_26, +matrixC30_27, +matrixC30_28, +matrixC30_29, +matrixC30_30, +matrixC30_31, +matrixC31_0, +matrixC31_1, +matrixC31_2, +matrixC31_3, +matrixC31_4, +matrixC31_5, +matrixC31_6, +matrixC31_7, +matrixC31_8, +matrixC31_9, +matrixC31_10, +matrixC31_11, +matrixC31_12, +matrixC31_13, +matrixC31_14, +matrixC31_15, +matrixC31_16, +matrixC31_17, +matrixC31_18, +matrixC31_19, +matrixC31_20, +matrixC31_21, +matrixC31_22, +matrixC31_23, +matrixC31_24, +matrixC31_25, +matrixC31_26, +matrixC31_27, +matrixC31_28, +matrixC31_29, +matrixC31_30, +matrixC31_31, + +clk, +reset +); + +input clk; +input reset; +input start_mat_mul; +input done_mat_mul; +input [`AWIDTH-1:0] address_mat_c; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_in; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] c_data_out; +output [`AWIDTH-1:0] c_addr; +output c_data_available; +input [7:0] clk_cnt; +output row_latch_en; + +input [7:0] final_mat_mul_size; +input [`DWIDTH-1:0] matrixC0_0; +input [`DWIDTH-1:0] matrixC0_1; +input [`DWIDTH-1:0] matrixC0_2; +input [`DWIDTH-1:0] matrixC0_3; +input [`DWIDTH-1:0] matrixC0_4; +input [`DWIDTH-1:0] matrixC0_5; +input [`DWIDTH-1:0] matrixC0_6; +input [`DWIDTH-1:0] matrixC0_7; +input [`DWIDTH-1:0] matrixC0_8; +input [`DWIDTH-1:0] matrixC0_9; +input [`DWIDTH-1:0] matrixC0_10; +input [`DWIDTH-1:0] matrixC0_11; +input [`DWIDTH-1:0] matrixC0_12; +input [`DWIDTH-1:0] matrixC0_13; +input [`DWIDTH-1:0] matrixC0_14; +input [`DWIDTH-1:0] matrixC0_15; +input [`DWIDTH-1:0] matrixC0_16; +input [`DWIDTH-1:0] matrixC0_17; +input [`DWIDTH-1:0] matrixC0_18; +input [`DWIDTH-1:0] matrixC0_19; +input [`DWIDTH-1:0] matrixC0_20; +input [`DWIDTH-1:0] matrixC0_21; +input [`DWIDTH-1:0] matrixC0_22; +input [`DWIDTH-1:0] matrixC0_23; +input [`DWIDTH-1:0] matrixC0_24; +input [`DWIDTH-1:0] matrixC0_25; +input [`DWIDTH-1:0] matrixC0_26; +input [`DWIDTH-1:0] matrixC0_27; +input [`DWIDTH-1:0] matrixC0_28; +input [`DWIDTH-1:0] matrixC0_29; +input [`DWIDTH-1:0] matrixC0_30; +input [`DWIDTH-1:0] matrixC0_31; +input [`DWIDTH-1:0] matrixC1_0; +input [`DWIDTH-1:0] matrixC1_1; +input [`DWIDTH-1:0] matrixC1_2; +input [`DWIDTH-1:0] matrixC1_3; +input [`DWIDTH-1:0] matrixC1_4; +input [`DWIDTH-1:0] matrixC1_5; +input [`DWIDTH-1:0] matrixC1_6; +input [`DWIDTH-1:0] matrixC1_7; +input [`DWIDTH-1:0] matrixC1_8; +input [`DWIDTH-1:0] matrixC1_9; +input [`DWIDTH-1:0] matrixC1_10; +input [`DWIDTH-1:0] matrixC1_11; +input [`DWIDTH-1:0] matrixC1_12; +input [`DWIDTH-1:0] matrixC1_13; +input [`DWIDTH-1:0] matrixC1_14; +input [`DWIDTH-1:0] matrixC1_15; +input [`DWIDTH-1:0] matrixC1_16; +input [`DWIDTH-1:0] matrixC1_17; +input [`DWIDTH-1:0] matrixC1_18; +input [`DWIDTH-1:0] matrixC1_19; +input [`DWIDTH-1:0] matrixC1_20; +input [`DWIDTH-1:0] matrixC1_21; +input [`DWIDTH-1:0] matrixC1_22; +input [`DWIDTH-1:0] matrixC1_23; +input [`DWIDTH-1:0] matrixC1_24; +input [`DWIDTH-1:0] matrixC1_25; +input [`DWIDTH-1:0] matrixC1_26; +input [`DWIDTH-1:0] matrixC1_27; +input [`DWIDTH-1:0] matrixC1_28; +input [`DWIDTH-1:0] matrixC1_29; +input [`DWIDTH-1:0] matrixC1_30; +input [`DWIDTH-1:0] matrixC1_31; +input [`DWIDTH-1:0] matrixC2_0; +input [`DWIDTH-1:0] matrixC2_1; +input [`DWIDTH-1:0] matrixC2_2; +input [`DWIDTH-1:0] matrixC2_3; +input [`DWIDTH-1:0] matrixC2_4; +input [`DWIDTH-1:0] matrixC2_5; +input [`DWIDTH-1:0] matrixC2_6; +input [`DWIDTH-1:0] matrixC2_7; +input [`DWIDTH-1:0] matrixC2_8; +input [`DWIDTH-1:0] matrixC2_9; +input [`DWIDTH-1:0] matrixC2_10; +input [`DWIDTH-1:0] matrixC2_11; +input [`DWIDTH-1:0] matrixC2_12; +input [`DWIDTH-1:0] matrixC2_13; +input [`DWIDTH-1:0] matrixC2_14; +input [`DWIDTH-1:0] matrixC2_15; +input [`DWIDTH-1:0] matrixC2_16; +input [`DWIDTH-1:0] matrixC2_17; +input [`DWIDTH-1:0] matrixC2_18; +input [`DWIDTH-1:0] matrixC2_19; +input [`DWIDTH-1:0] matrixC2_20; +input [`DWIDTH-1:0] matrixC2_21; +input [`DWIDTH-1:0] matrixC2_22; +input [`DWIDTH-1:0] matrixC2_23; +input [`DWIDTH-1:0] matrixC2_24; +input [`DWIDTH-1:0] matrixC2_25; +input [`DWIDTH-1:0] matrixC2_26; +input [`DWIDTH-1:0] matrixC2_27; +input [`DWIDTH-1:0] matrixC2_28; +input [`DWIDTH-1:0] matrixC2_29; +input [`DWIDTH-1:0] matrixC2_30; +input [`DWIDTH-1:0] matrixC2_31; +input [`DWIDTH-1:0] matrixC3_0; +input [`DWIDTH-1:0] matrixC3_1; +input [`DWIDTH-1:0] matrixC3_2; +input [`DWIDTH-1:0] matrixC3_3; +input [`DWIDTH-1:0] matrixC3_4; +input [`DWIDTH-1:0] matrixC3_5; +input [`DWIDTH-1:0] matrixC3_6; +input [`DWIDTH-1:0] matrixC3_7; +input [`DWIDTH-1:0] matrixC3_8; +input [`DWIDTH-1:0] matrixC3_9; +input [`DWIDTH-1:0] matrixC3_10; +input [`DWIDTH-1:0] matrixC3_11; +input [`DWIDTH-1:0] matrixC3_12; +input [`DWIDTH-1:0] matrixC3_13; +input [`DWIDTH-1:0] matrixC3_14; +input [`DWIDTH-1:0] matrixC3_15; +input [`DWIDTH-1:0] matrixC3_16; +input [`DWIDTH-1:0] matrixC3_17; +input [`DWIDTH-1:0] matrixC3_18; +input [`DWIDTH-1:0] matrixC3_19; +input [`DWIDTH-1:0] matrixC3_20; +input [`DWIDTH-1:0] matrixC3_21; +input [`DWIDTH-1:0] matrixC3_22; +input [`DWIDTH-1:0] matrixC3_23; +input [`DWIDTH-1:0] matrixC3_24; +input [`DWIDTH-1:0] matrixC3_25; +input [`DWIDTH-1:0] matrixC3_26; +input [`DWIDTH-1:0] matrixC3_27; +input [`DWIDTH-1:0] matrixC3_28; +input [`DWIDTH-1:0] matrixC3_29; +input [`DWIDTH-1:0] matrixC3_30; +input [`DWIDTH-1:0] matrixC3_31; +input [`DWIDTH-1:0] matrixC4_0; +input [`DWIDTH-1:0] matrixC4_1; +input [`DWIDTH-1:0] matrixC4_2; +input [`DWIDTH-1:0] matrixC4_3; +input [`DWIDTH-1:0] matrixC4_4; +input [`DWIDTH-1:0] matrixC4_5; +input [`DWIDTH-1:0] matrixC4_6; +input [`DWIDTH-1:0] matrixC4_7; +input [`DWIDTH-1:0] matrixC4_8; +input [`DWIDTH-1:0] matrixC4_9; +input [`DWIDTH-1:0] matrixC4_10; +input [`DWIDTH-1:0] matrixC4_11; +input [`DWIDTH-1:0] matrixC4_12; +input [`DWIDTH-1:0] matrixC4_13; +input [`DWIDTH-1:0] matrixC4_14; +input [`DWIDTH-1:0] matrixC4_15; +input [`DWIDTH-1:0] matrixC4_16; +input [`DWIDTH-1:0] matrixC4_17; +input [`DWIDTH-1:0] matrixC4_18; +input [`DWIDTH-1:0] matrixC4_19; +input [`DWIDTH-1:0] matrixC4_20; +input [`DWIDTH-1:0] matrixC4_21; +input [`DWIDTH-1:0] matrixC4_22; +input [`DWIDTH-1:0] matrixC4_23; +input [`DWIDTH-1:0] matrixC4_24; +input [`DWIDTH-1:0] matrixC4_25; +input [`DWIDTH-1:0] matrixC4_26; +input [`DWIDTH-1:0] matrixC4_27; +input [`DWIDTH-1:0] matrixC4_28; +input [`DWIDTH-1:0] matrixC4_29; +input [`DWIDTH-1:0] matrixC4_30; +input [`DWIDTH-1:0] matrixC4_31; +input [`DWIDTH-1:0] matrixC5_0; +input [`DWIDTH-1:0] matrixC5_1; +input [`DWIDTH-1:0] matrixC5_2; +input [`DWIDTH-1:0] matrixC5_3; +input [`DWIDTH-1:0] matrixC5_4; +input [`DWIDTH-1:0] matrixC5_5; +input [`DWIDTH-1:0] matrixC5_6; +input [`DWIDTH-1:0] matrixC5_7; +input [`DWIDTH-1:0] matrixC5_8; +input [`DWIDTH-1:0] matrixC5_9; +input [`DWIDTH-1:0] matrixC5_10; +input [`DWIDTH-1:0] matrixC5_11; +input [`DWIDTH-1:0] matrixC5_12; +input [`DWIDTH-1:0] matrixC5_13; +input [`DWIDTH-1:0] matrixC5_14; +input [`DWIDTH-1:0] matrixC5_15; +input [`DWIDTH-1:0] matrixC5_16; +input [`DWIDTH-1:0] matrixC5_17; +input [`DWIDTH-1:0] matrixC5_18; +input [`DWIDTH-1:0] matrixC5_19; +input [`DWIDTH-1:0] matrixC5_20; +input [`DWIDTH-1:0] matrixC5_21; +input [`DWIDTH-1:0] matrixC5_22; +input [`DWIDTH-1:0] matrixC5_23; +input [`DWIDTH-1:0] matrixC5_24; +input [`DWIDTH-1:0] matrixC5_25; +input [`DWIDTH-1:0] matrixC5_26; +input [`DWIDTH-1:0] matrixC5_27; +input [`DWIDTH-1:0] matrixC5_28; +input [`DWIDTH-1:0] matrixC5_29; +input [`DWIDTH-1:0] matrixC5_30; +input [`DWIDTH-1:0] matrixC5_31; +input [`DWIDTH-1:0] matrixC6_0; +input [`DWIDTH-1:0] matrixC6_1; +input [`DWIDTH-1:0] matrixC6_2; +input [`DWIDTH-1:0] matrixC6_3; +input [`DWIDTH-1:0] matrixC6_4; +input [`DWIDTH-1:0] matrixC6_5; +input [`DWIDTH-1:0] matrixC6_6; +input [`DWIDTH-1:0] matrixC6_7; +input [`DWIDTH-1:0] matrixC6_8; +input [`DWIDTH-1:0] matrixC6_9; +input [`DWIDTH-1:0] matrixC6_10; +input [`DWIDTH-1:0] matrixC6_11; +input [`DWIDTH-1:0] matrixC6_12; +input [`DWIDTH-1:0] matrixC6_13; +input [`DWIDTH-1:0] matrixC6_14; +input [`DWIDTH-1:0] matrixC6_15; +input [`DWIDTH-1:0] matrixC6_16; +input [`DWIDTH-1:0] matrixC6_17; +input [`DWIDTH-1:0] matrixC6_18; +input [`DWIDTH-1:0] matrixC6_19; +input [`DWIDTH-1:0] matrixC6_20; +input [`DWIDTH-1:0] matrixC6_21; +input [`DWIDTH-1:0] matrixC6_22; +input [`DWIDTH-1:0] matrixC6_23; +input [`DWIDTH-1:0] matrixC6_24; +input [`DWIDTH-1:0] matrixC6_25; +input [`DWIDTH-1:0] matrixC6_26; +input [`DWIDTH-1:0] matrixC6_27; +input [`DWIDTH-1:0] matrixC6_28; +input [`DWIDTH-1:0] matrixC6_29; +input [`DWIDTH-1:0] matrixC6_30; +input [`DWIDTH-1:0] matrixC6_31; +input [`DWIDTH-1:0] matrixC7_0; +input [`DWIDTH-1:0] matrixC7_1; +input [`DWIDTH-1:0] matrixC7_2; +input [`DWIDTH-1:0] matrixC7_3; +input [`DWIDTH-1:0] matrixC7_4; +input [`DWIDTH-1:0] matrixC7_5; +input [`DWIDTH-1:0] matrixC7_6; +input [`DWIDTH-1:0] matrixC7_7; +input [`DWIDTH-1:0] matrixC7_8; +input [`DWIDTH-1:0] matrixC7_9; +input [`DWIDTH-1:0] matrixC7_10; +input [`DWIDTH-1:0] matrixC7_11; +input [`DWIDTH-1:0] matrixC7_12; +input [`DWIDTH-1:0] matrixC7_13; +input [`DWIDTH-1:0] matrixC7_14; +input [`DWIDTH-1:0] matrixC7_15; +input [`DWIDTH-1:0] matrixC7_16; +input [`DWIDTH-1:0] matrixC7_17; +input [`DWIDTH-1:0] matrixC7_18; +input [`DWIDTH-1:0] matrixC7_19; +input [`DWIDTH-1:0] matrixC7_20; +input [`DWIDTH-1:0] matrixC7_21; +input [`DWIDTH-1:0] matrixC7_22; +input [`DWIDTH-1:0] matrixC7_23; +input [`DWIDTH-1:0] matrixC7_24; +input [`DWIDTH-1:0] matrixC7_25; +input [`DWIDTH-1:0] matrixC7_26; +input [`DWIDTH-1:0] matrixC7_27; +input [`DWIDTH-1:0] matrixC7_28; +input [`DWIDTH-1:0] matrixC7_29; +input [`DWIDTH-1:0] matrixC7_30; +input [`DWIDTH-1:0] matrixC7_31; +input [`DWIDTH-1:0] matrixC8_0; +input [`DWIDTH-1:0] matrixC8_1; +input [`DWIDTH-1:0] matrixC8_2; +input [`DWIDTH-1:0] matrixC8_3; +input [`DWIDTH-1:0] matrixC8_4; +input [`DWIDTH-1:0] matrixC8_5; +input [`DWIDTH-1:0] matrixC8_6; +input [`DWIDTH-1:0] matrixC8_7; +input [`DWIDTH-1:0] matrixC8_8; +input [`DWIDTH-1:0] matrixC8_9; +input [`DWIDTH-1:0] matrixC8_10; +input [`DWIDTH-1:0] matrixC8_11; +input [`DWIDTH-1:0] matrixC8_12; +input [`DWIDTH-1:0] matrixC8_13; +input [`DWIDTH-1:0] matrixC8_14; +input [`DWIDTH-1:0] matrixC8_15; +input [`DWIDTH-1:0] matrixC8_16; +input [`DWIDTH-1:0] matrixC8_17; +input [`DWIDTH-1:0] matrixC8_18; +input [`DWIDTH-1:0] matrixC8_19; +input [`DWIDTH-1:0] matrixC8_20; +input [`DWIDTH-1:0] matrixC8_21; +input [`DWIDTH-1:0] matrixC8_22; +input [`DWIDTH-1:0] matrixC8_23; +input [`DWIDTH-1:0] matrixC8_24; +input [`DWIDTH-1:0] matrixC8_25; +input [`DWIDTH-1:0] matrixC8_26; +input [`DWIDTH-1:0] matrixC8_27; +input [`DWIDTH-1:0] matrixC8_28; +input [`DWIDTH-1:0] matrixC8_29; +input [`DWIDTH-1:0] matrixC8_30; +input [`DWIDTH-1:0] matrixC8_31; +input [`DWIDTH-1:0] matrixC9_0; +input [`DWIDTH-1:0] matrixC9_1; +input [`DWIDTH-1:0] matrixC9_2; +input [`DWIDTH-1:0] matrixC9_3; +input [`DWIDTH-1:0] matrixC9_4; +input [`DWIDTH-1:0] matrixC9_5; +input [`DWIDTH-1:0] matrixC9_6; +input [`DWIDTH-1:0] matrixC9_7; +input [`DWIDTH-1:0] matrixC9_8; +input [`DWIDTH-1:0] matrixC9_9; +input [`DWIDTH-1:0] matrixC9_10; +input [`DWIDTH-1:0] matrixC9_11; +input [`DWIDTH-1:0] matrixC9_12; +input [`DWIDTH-1:0] matrixC9_13; +input [`DWIDTH-1:0] matrixC9_14; +input [`DWIDTH-1:0] matrixC9_15; +input [`DWIDTH-1:0] matrixC9_16; +input [`DWIDTH-1:0] matrixC9_17; +input [`DWIDTH-1:0] matrixC9_18; +input [`DWIDTH-1:0] matrixC9_19; +input [`DWIDTH-1:0] matrixC9_20; +input [`DWIDTH-1:0] matrixC9_21; +input [`DWIDTH-1:0] matrixC9_22; +input [`DWIDTH-1:0] matrixC9_23; +input [`DWIDTH-1:0] matrixC9_24; +input [`DWIDTH-1:0] matrixC9_25; +input [`DWIDTH-1:0] matrixC9_26; +input [`DWIDTH-1:0] matrixC9_27; +input [`DWIDTH-1:0] matrixC9_28; +input [`DWIDTH-1:0] matrixC9_29; +input [`DWIDTH-1:0] matrixC9_30; +input [`DWIDTH-1:0] matrixC9_31; +input [`DWIDTH-1:0] matrixC10_0; +input [`DWIDTH-1:0] matrixC10_1; +input [`DWIDTH-1:0] matrixC10_2; +input [`DWIDTH-1:0] matrixC10_3; +input [`DWIDTH-1:0] matrixC10_4; +input [`DWIDTH-1:0] matrixC10_5; +input [`DWIDTH-1:0] matrixC10_6; +input [`DWIDTH-1:0] matrixC10_7; +input [`DWIDTH-1:0] matrixC10_8; +input [`DWIDTH-1:0] matrixC10_9; +input [`DWIDTH-1:0] matrixC10_10; +input [`DWIDTH-1:0] matrixC10_11; +input [`DWIDTH-1:0] matrixC10_12; +input [`DWIDTH-1:0] matrixC10_13; +input [`DWIDTH-1:0] matrixC10_14; +input [`DWIDTH-1:0] matrixC10_15; +input [`DWIDTH-1:0] matrixC10_16; +input [`DWIDTH-1:0] matrixC10_17; +input [`DWIDTH-1:0] matrixC10_18; +input [`DWIDTH-1:0] matrixC10_19; +input [`DWIDTH-1:0] matrixC10_20; +input [`DWIDTH-1:0] matrixC10_21; +input [`DWIDTH-1:0] matrixC10_22; +input [`DWIDTH-1:0] matrixC10_23; +input [`DWIDTH-1:0] matrixC10_24; +input [`DWIDTH-1:0] matrixC10_25; +input [`DWIDTH-1:0] matrixC10_26; +input [`DWIDTH-1:0] matrixC10_27; +input [`DWIDTH-1:0] matrixC10_28; +input [`DWIDTH-1:0] matrixC10_29; +input [`DWIDTH-1:0] matrixC10_30; +input [`DWIDTH-1:0] matrixC10_31; +input [`DWIDTH-1:0] matrixC11_0; +input [`DWIDTH-1:0] matrixC11_1; +input [`DWIDTH-1:0] matrixC11_2; +input [`DWIDTH-1:0] matrixC11_3; +input [`DWIDTH-1:0] matrixC11_4; +input [`DWIDTH-1:0] matrixC11_5; +input [`DWIDTH-1:0] matrixC11_6; +input [`DWIDTH-1:0] matrixC11_7; +input [`DWIDTH-1:0] matrixC11_8; +input [`DWIDTH-1:0] matrixC11_9; +input [`DWIDTH-1:0] matrixC11_10; +input [`DWIDTH-1:0] matrixC11_11; +input [`DWIDTH-1:0] matrixC11_12; +input [`DWIDTH-1:0] matrixC11_13; +input [`DWIDTH-1:0] matrixC11_14; +input [`DWIDTH-1:0] matrixC11_15; +input [`DWIDTH-1:0] matrixC11_16; +input [`DWIDTH-1:0] matrixC11_17; +input [`DWIDTH-1:0] matrixC11_18; +input [`DWIDTH-1:0] matrixC11_19; +input [`DWIDTH-1:0] matrixC11_20; +input [`DWIDTH-1:0] matrixC11_21; +input [`DWIDTH-1:0] matrixC11_22; +input [`DWIDTH-1:0] matrixC11_23; +input [`DWIDTH-1:0] matrixC11_24; +input [`DWIDTH-1:0] matrixC11_25; +input [`DWIDTH-1:0] matrixC11_26; +input [`DWIDTH-1:0] matrixC11_27; +input [`DWIDTH-1:0] matrixC11_28; +input [`DWIDTH-1:0] matrixC11_29; +input [`DWIDTH-1:0] matrixC11_30; +input [`DWIDTH-1:0] matrixC11_31; +input [`DWIDTH-1:0] matrixC12_0; +input [`DWIDTH-1:0] matrixC12_1; +input [`DWIDTH-1:0] matrixC12_2; +input [`DWIDTH-1:0] matrixC12_3; +input [`DWIDTH-1:0] matrixC12_4; +input [`DWIDTH-1:0] matrixC12_5; +input [`DWIDTH-1:0] matrixC12_6; +input [`DWIDTH-1:0] matrixC12_7; +input [`DWIDTH-1:0] matrixC12_8; +input [`DWIDTH-1:0] matrixC12_9; +input [`DWIDTH-1:0] matrixC12_10; +input [`DWIDTH-1:0] matrixC12_11; +input [`DWIDTH-1:0] matrixC12_12; +input [`DWIDTH-1:0] matrixC12_13; +input [`DWIDTH-1:0] matrixC12_14; +input [`DWIDTH-1:0] matrixC12_15; +input [`DWIDTH-1:0] matrixC12_16; +input [`DWIDTH-1:0] matrixC12_17; +input [`DWIDTH-1:0] matrixC12_18; +input [`DWIDTH-1:0] matrixC12_19; +input [`DWIDTH-1:0] matrixC12_20; +input [`DWIDTH-1:0] matrixC12_21; +input [`DWIDTH-1:0] matrixC12_22; +input [`DWIDTH-1:0] matrixC12_23; +input [`DWIDTH-1:0] matrixC12_24; +input [`DWIDTH-1:0] matrixC12_25; +input [`DWIDTH-1:0] matrixC12_26; +input [`DWIDTH-1:0] matrixC12_27; +input [`DWIDTH-1:0] matrixC12_28; +input [`DWIDTH-1:0] matrixC12_29; +input [`DWIDTH-1:0] matrixC12_30; +input [`DWIDTH-1:0] matrixC12_31; +input [`DWIDTH-1:0] matrixC13_0; +input [`DWIDTH-1:0] matrixC13_1; +input [`DWIDTH-1:0] matrixC13_2; +input [`DWIDTH-1:0] matrixC13_3; +input [`DWIDTH-1:0] matrixC13_4; +input [`DWIDTH-1:0] matrixC13_5; +input [`DWIDTH-1:0] matrixC13_6; +input [`DWIDTH-1:0] matrixC13_7; +input [`DWIDTH-1:0] matrixC13_8; +input [`DWIDTH-1:0] matrixC13_9; +input [`DWIDTH-1:0] matrixC13_10; +input [`DWIDTH-1:0] matrixC13_11; +input [`DWIDTH-1:0] matrixC13_12; +input [`DWIDTH-1:0] matrixC13_13; +input [`DWIDTH-1:0] matrixC13_14; +input [`DWIDTH-1:0] matrixC13_15; +input [`DWIDTH-1:0] matrixC13_16; +input [`DWIDTH-1:0] matrixC13_17; +input [`DWIDTH-1:0] matrixC13_18; +input [`DWIDTH-1:0] matrixC13_19; +input [`DWIDTH-1:0] matrixC13_20; +input [`DWIDTH-1:0] matrixC13_21; +input [`DWIDTH-1:0] matrixC13_22; +input [`DWIDTH-1:0] matrixC13_23; +input [`DWIDTH-1:0] matrixC13_24; +input [`DWIDTH-1:0] matrixC13_25; +input [`DWIDTH-1:0] matrixC13_26; +input [`DWIDTH-1:0] matrixC13_27; +input [`DWIDTH-1:0] matrixC13_28; +input [`DWIDTH-1:0] matrixC13_29; +input [`DWIDTH-1:0] matrixC13_30; +input [`DWIDTH-1:0] matrixC13_31; +input [`DWIDTH-1:0] matrixC14_0; +input [`DWIDTH-1:0] matrixC14_1; +input [`DWIDTH-1:0] matrixC14_2; +input [`DWIDTH-1:0] matrixC14_3; +input [`DWIDTH-1:0] matrixC14_4; +input [`DWIDTH-1:0] matrixC14_5; +input [`DWIDTH-1:0] matrixC14_6; +input [`DWIDTH-1:0] matrixC14_7; +input [`DWIDTH-1:0] matrixC14_8; +input [`DWIDTH-1:0] matrixC14_9; +input [`DWIDTH-1:0] matrixC14_10; +input [`DWIDTH-1:0] matrixC14_11; +input [`DWIDTH-1:0] matrixC14_12; +input [`DWIDTH-1:0] matrixC14_13; +input [`DWIDTH-1:0] matrixC14_14; +input [`DWIDTH-1:0] matrixC14_15; +input [`DWIDTH-1:0] matrixC14_16; +input [`DWIDTH-1:0] matrixC14_17; +input [`DWIDTH-1:0] matrixC14_18; +input [`DWIDTH-1:0] matrixC14_19; +input [`DWIDTH-1:0] matrixC14_20; +input [`DWIDTH-1:0] matrixC14_21; +input [`DWIDTH-1:0] matrixC14_22; +input [`DWIDTH-1:0] matrixC14_23; +input [`DWIDTH-1:0] matrixC14_24; +input [`DWIDTH-1:0] matrixC14_25; +input [`DWIDTH-1:0] matrixC14_26; +input [`DWIDTH-1:0] matrixC14_27; +input [`DWIDTH-1:0] matrixC14_28; +input [`DWIDTH-1:0] matrixC14_29; +input [`DWIDTH-1:0] matrixC14_30; +input [`DWIDTH-1:0] matrixC14_31; +input [`DWIDTH-1:0] matrixC15_0; +input [`DWIDTH-1:0] matrixC15_1; +input [`DWIDTH-1:0] matrixC15_2; +input [`DWIDTH-1:0] matrixC15_3; +input [`DWIDTH-1:0] matrixC15_4; +input [`DWIDTH-1:0] matrixC15_5; +input [`DWIDTH-1:0] matrixC15_6; +input [`DWIDTH-1:0] matrixC15_7; +input [`DWIDTH-1:0] matrixC15_8; +input [`DWIDTH-1:0] matrixC15_9; +input [`DWIDTH-1:0] matrixC15_10; +input [`DWIDTH-1:0] matrixC15_11; +input [`DWIDTH-1:0] matrixC15_12; +input [`DWIDTH-1:0] matrixC15_13; +input [`DWIDTH-1:0] matrixC15_14; +input [`DWIDTH-1:0] matrixC15_15; +input [`DWIDTH-1:0] matrixC15_16; +input [`DWIDTH-1:0] matrixC15_17; +input [`DWIDTH-1:0] matrixC15_18; +input [`DWIDTH-1:0] matrixC15_19; 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+input [`DWIDTH-1:0] matrixC26_12; +input [`DWIDTH-1:0] matrixC26_13; +input [`DWIDTH-1:0] matrixC26_14; +input [`DWIDTH-1:0] matrixC26_15; +input [`DWIDTH-1:0] matrixC26_16; +input [`DWIDTH-1:0] matrixC26_17; +input [`DWIDTH-1:0] matrixC26_18; +input [`DWIDTH-1:0] matrixC26_19; +input [`DWIDTH-1:0] matrixC26_20; +input [`DWIDTH-1:0] matrixC26_21; +input [`DWIDTH-1:0] matrixC26_22; +input [`DWIDTH-1:0] matrixC26_23; +input [`DWIDTH-1:0] matrixC26_24; +input [`DWIDTH-1:0] matrixC26_25; +input [`DWIDTH-1:0] matrixC26_26; +input [`DWIDTH-1:0] matrixC26_27; +input [`DWIDTH-1:0] matrixC26_28; +input [`DWIDTH-1:0] matrixC26_29; +input [`DWIDTH-1:0] matrixC26_30; +input [`DWIDTH-1:0] matrixC26_31; +input [`DWIDTH-1:0] matrixC27_0; +input [`DWIDTH-1:0] matrixC27_1; +input [`DWIDTH-1:0] matrixC27_2; +input [`DWIDTH-1:0] matrixC27_3; +input [`DWIDTH-1:0] matrixC27_4; +input [`DWIDTH-1:0] matrixC27_5; +input [`DWIDTH-1:0] matrixC27_6; +input [`DWIDTH-1:0] matrixC27_7; +input [`DWIDTH-1:0] matrixC27_8; +input [`DWIDTH-1:0] matrixC27_9; +input [`DWIDTH-1:0] matrixC27_10; +input [`DWIDTH-1:0] matrixC27_11; +input [`DWIDTH-1:0] matrixC27_12; +input [`DWIDTH-1:0] matrixC27_13; +input [`DWIDTH-1:0] matrixC27_14; +input [`DWIDTH-1:0] matrixC27_15; +input [`DWIDTH-1:0] matrixC27_16; +input [`DWIDTH-1:0] matrixC27_17; +input [`DWIDTH-1:0] matrixC27_18; +input [`DWIDTH-1:0] matrixC27_19; +input [`DWIDTH-1:0] matrixC27_20; +input [`DWIDTH-1:0] matrixC27_21; +input [`DWIDTH-1:0] matrixC27_22; +input [`DWIDTH-1:0] matrixC27_23; +input [`DWIDTH-1:0] matrixC27_24; +input [`DWIDTH-1:0] matrixC27_25; +input [`DWIDTH-1:0] matrixC27_26; +input [`DWIDTH-1:0] matrixC27_27; +input [`DWIDTH-1:0] matrixC27_28; +input [`DWIDTH-1:0] matrixC27_29; +input [`DWIDTH-1:0] matrixC27_30; +input [`DWIDTH-1:0] matrixC27_31; +input [`DWIDTH-1:0] matrixC28_0; +input [`DWIDTH-1:0] matrixC28_1; +input [`DWIDTH-1:0] matrixC28_2; +input [`DWIDTH-1:0] matrixC28_3; +input [`DWIDTH-1:0] matrixC28_4; +input [`DWIDTH-1:0] matrixC28_5; +input [`DWIDTH-1:0] matrixC28_6; +input [`DWIDTH-1:0] matrixC28_7; +input [`DWIDTH-1:0] matrixC28_8; +input [`DWIDTH-1:0] matrixC28_9; +input [`DWIDTH-1:0] matrixC28_10; +input [`DWIDTH-1:0] matrixC28_11; +input [`DWIDTH-1:0] matrixC28_12; +input [`DWIDTH-1:0] matrixC28_13; +input [`DWIDTH-1:0] matrixC28_14; +input [`DWIDTH-1:0] matrixC28_15; +input [`DWIDTH-1:0] matrixC28_16; +input [`DWIDTH-1:0] matrixC28_17; +input [`DWIDTH-1:0] matrixC28_18; +input [`DWIDTH-1:0] matrixC28_19; +input [`DWIDTH-1:0] matrixC28_20; +input [`DWIDTH-1:0] matrixC28_21; +input [`DWIDTH-1:0] matrixC28_22; +input [`DWIDTH-1:0] matrixC28_23; +input [`DWIDTH-1:0] matrixC28_24; +input [`DWIDTH-1:0] matrixC28_25; +input [`DWIDTH-1:0] matrixC28_26; +input [`DWIDTH-1:0] matrixC28_27; +input [`DWIDTH-1:0] matrixC28_28; +input [`DWIDTH-1:0] matrixC28_29; +input [`DWIDTH-1:0] matrixC28_30; +input [`DWIDTH-1:0] matrixC28_31; +input [`DWIDTH-1:0] matrixC29_0; +input [`DWIDTH-1:0] matrixC29_1; +input [`DWIDTH-1:0] matrixC29_2; +input [`DWIDTH-1:0] matrixC29_3; +input [`DWIDTH-1:0] matrixC29_4; +input [`DWIDTH-1:0] matrixC29_5; +input [`DWIDTH-1:0] matrixC29_6; +input [`DWIDTH-1:0] matrixC29_7; +input [`DWIDTH-1:0] matrixC29_8; +input [`DWIDTH-1:0] matrixC29_9; +input [`DWIDTH-1:0] matrixC29_10; +input [`DWIDTH-1:0] matrixC29_11; +input [`DWIDTH-1:0] matrixC29_12; +input [`DWIDTH-1:0] matrixC29_13; +input [`DWIDTH-1:0] matrixC29_14; +input [`DWIDTH-1:0] matrixC29_15; +input [`DWIDTH-1:0] matrixC29_16; +input [`DWIDTH-1:0] matrixC29_17; +input [`DWIDTH-1:0] matrixC29_18; +input [`DWIDTH-1:0] matrixC29_19; +input [`DWIDTH-1:0] matrixC29_20; +input [`DWIDTH-1:0] matrixC29_21; +input [`DWIDTH-1:0] matrixC29_22; +input [`DWIDTH-1:0] matrixC29_23; +input [`DWIDTH-1:0] matrixC29_24; +input [`DWIDTH-1:0] matrixC29_25; +input [`DWIDTH-1:0] matrixC29_26; +input [`DWIDTH-1:0] matrixC29_27; +input [`DWIDTH-1:0] matrixC29_28; +input [`DWIDTH-1:0] matrixC29_29; +input [`DWIDTH-1:0] matrixC29_30; +input [`DWIDTH-1:0] matrixC29_31; +input [`DWIDTH-1:0] matrixC30_0; +input [`DWIDTH-1:0] matrixC30_1; +input [`DWIDTH-1:0] matrixC30_2; +input [`DWIDTH-1:0] matrixC30_3; +input [`DWIDTH-1:0] matrixC30_4; +input [`DWIDTH-1:0] matrixC30_5; +input [`DWIDTH-1:0] matrixC30_6; +input [`DWIDTH-1:0] matrixC30_7; +input [`DWIDTH-1:0] matrixC30_8; +input [`DWIDTH-1:0] matrixC30_9; +input [`DWIDTH-1:0] matrixC30_10; +input [`DWIDTH-1:0] matrixC30_11; +input [`DWIDTH-1:0] matrixC30_12; +input [`DWIDTH-1:0] matrixC30_13; +input [`DWIDTH-1:0] matrixC30_14; +input [`DWIDTH-1:0] matrixC30_15; +input [`DWIDTH-1:0] matrixC30_16; +input [`DWIDTH-1:0] matrixC30_17; +input [`DWIDTH-1:0] matrixC30_18; +input [`DWIDTH-1:0] matrixC30_19; +input [`DWIDTH-1:0] matrixC30_20; +input [`DWIDTH-1:0] matrixC30_21; +input [`DWIDTH-1:0] matrixC30_22; +input [`DWIDTH-1:0] matrixC30_23; +input [`DWIDTH-1:0] matrixC30_24; +input [`DWIDTH-1:0] matrixC30_25; +input [`DWIDTH-1:0] matrixC30_26; +input [`DWIDTH-1:0] matrixC30_27; +input [`DWIDTH-1:0] matrixC30_28; +input [`DWIDTH-1:0] matrixC30_29; +input [`DWIDTH-1:0] matrixC30_30; +input [`DWIDTH-1:0] matrixC30_31; +input [`DWIDTH-1:0] matrixC31_0; +input [`DWIDTH-1:0] matrixC31_1; +input [`DWIDTH-1:0] matrixC31_2; +input [`DWIDTH-1:0] matrixC31_3; +input [`DWIDTH-1:0] matrixC31_4; +input [`DWIDTH-1:0] matrixC31_5; +input [`DWIDTH-1:0] matrixC31_6; +input [`DWIDTH-1:0] matrixC31_7; +input [`DWIDTH-1:0] matrixC31_8; +input [`DWIDTH-1:0] matrixC31_9; +input [`DWIDTH-1:0] matrixC31_10; +input [`DWIDTH-1:0] matrixC31_11; +input [`DWIDTH-1:0] matrixC31_12; +input [`DWIDTH-1:0] matrixC31_13; +input [`DWIDTH-1:0] matrixC31_14; +input [`DWIDTH-1:0] matrixC31_15; +input [`DWIDTH-1:0] matrixC31_16; +input [`DWIDTH-1:0] matrixC31_17; +input [`DWIDTH-1:0] matrixC31_18; +input [`DWIDTH-1:0] matrixC31_19; +input [`DWIDTH-1:0] matrixC31_20; +input [`DWIDTH-1:0] matrixC31_21; +input [`DWIDTH-1:0] matrixC31_22; +input [`DWIDTH-1:0] matrixC31_23; +input [`DWIDTH-1:0] matrixC31_24; +input [`DWIDTH-1:0] matrixC31_25; +input [`DWIDTH-1:0] matrixC31_26; +input [`DWIDTH-1:0] matrixC31_27; +input [`DWIDTH-1:0] matrixC31_28; +input [`DWIDTH-1:0] matrixC31_29; +input [`DWIDTH-1:0] matrixC31_30; +input [`DWIDTH-1:0] matrixC31_31; +wire row_latch_en; + + +////////////////////////////////////////////////////////////////////////// +// Logic to capture matrix C data from the PEs and shift it out +////////////////////////////////////////////////////////////////////////// +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + (a_loc+b_loc) * `BB_MAT_MUL_SIZE + 10 + `NUM_CYCLES_IN_MAC - 1)); +//Writing the line above to avoid multiplication: +//assign row_latch_en = (clk_cnt==(`MAT_MUL_SIZE + ((a_loc+b_loc) << `LOG2_MAT_MUL_SIZE) + 10 + `NUM_CYCLES_IN_MAC - 1)); + +assign row_latch_en = + ((clk_cnt == ((`final_mat_mul_size<<2) - `final_mat_mul_size - 1 +`NUM_CYCLES_IN_MAC))); + +reg c_data_available; +reg [`AWIDTH-1:0] c_addr; +reg start_capturing_c_data; +reg [31:0] counter; +reg [32*`DWIDTH-1:0] c_data_out; +reg [32*`DWIDTH-1:0] c_data_out_1; +reg [32*`DWIDTH-1:0] c_data_out_2; +reg [32*`DWIDTH-1:0] c_data_out_3; +reg [32*`DWIDTH-1:0] c_data_out_4; +reg [32*`DWIDTH-1:0] c_data_out_5; +reg [32*`DWIDTH-1:0] c_data_out_6; +reg [32*`DWIDTH-1:0] c_data_out_7; +reg [32*`DWIDTH-1:0] c_data_out_8; +reg [32*`DWIDTH-1:0] c_data_out_9; +reg [32*`DWIDTH-1:0] c_data_out_10; +reg [32*`DWIDTH-1:0] c_data_out_11; +reg [32*`DWIDTH-1:0] c_data_out_12; +reg [32*`DWIDTH-1:0] c_data_out_13; +reg [32*`DWIDTH-1:0] c_data_out_14; +reg [32*`DWIDTH-1:0] c_data_out_15; +reg [32*`DWIDTH-1:0] c_data_out_16; +reg [32*`DWIDTH-1:0] c_data_out_17; +reg [32*`DWIDTH-1:0] c_data_out_18; +reg [32*`DWIDTH-1:0] c_data_out_19; +reg [32*`DWIDTH-1:0] c_data_out_20; +reg [32*`DWIDTH-1:0] c_data_out_21; +reg [32*`DWIDTH-1:0] c_data_out_22; +reg [32*`DWIDTH-1:0] c_data_out_23; +reg [32*`DWIDTH-1:0] c_data_out_24; +reg [32*`DWIDTH-1:0] c_data_out_25; +reg [32*`DWIDTH-1:0] c_data_out_26; +reg [32*`DWIDTH-1:0] c_data_out_27; +reg [32*`DWIDTH-1:0] c_data_out_28; +reg [32*`DWIDTH-1:0] c_data_out_29; +reg [32*`DWIDTH-1:0] c_data_out_30; +reg [32*`DWIDTH-1:0] c_data_out_31; +wire condition_to_start_shifting_output; +assign condition_to_start_shifting_output = + row_latch_en ; + + +//For larger matmuls, this logic will have more entries in the case statement +always @(posedge clk) begin + if (reset | ~start_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + counter <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + c_data_out_20 <= 0; + c_data_out_21 <= 0; + c_data_out_22 <= 0; + c_data_out_23 <= 0; + c_data_out_24 <= 0; + c_data_out_25 <= 0; + c_data_out_26 <= 0; + c_data_out_27 <= 0; + c_data_out_28 <= 0; + c_data_out_29 <= 0; + c_data_out_30 <= 0; + c_data_out_31 <= 0; + end else if (condition_to_start_shifting_output) begin + start_capturing_c_data <= 1'b1; + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + c_data_out <= {matrixC31_31, matrixC30_31, matrixC29_31, matrixC28_31, matrixC27_31, matrixC26_31, matrixC25_31, matrixC24_31, matrixC23_31, matrixC22_31, matrixC21_31, matrixC20_31, matrixC19_31, matrixC18_31, matrixC17_31, matrixC16_31, matrixC15_31, matrixC14_31, matrixC13_31, matrixC12_31, matrixC11_31, matrixC10_31, matrixC9_31, matrixC8_31, matrixC7_31, matrixC6_31, matrixC5_31, matrixC4_31, matrixC3_31, matrixC2_31, matrixC1_31, matrixC0_31}; + c_data_out_1 <= {matrixC31_30, matrixC30_30, matrixC29_30, matrixC28_30, matrixC27_30, matrixC26_30, matrixC25_30, matrixC24_30, matrixC23_30, matrixC22_30, matrixC21_30, matrixC20_30, matrixC19_30, matrixC18_30, matrixC17_30, matrixC16_30, matrixC15_30, matrixC14_30, matrixC13_30, matrixC12_30, matrixC11_30, matrixC10_30, matrixC9_30, matrixC8_30, matrixC7_30, matrixC6_30, matrixC5_30, matrixC4_30, matrixC3_30, matrixC2_30, matrixC1_30, matrixC0_30}; + c_data_out_2 <= {matrixC31_29, matrixC30_29, matrixC29_29, matrixC28_29, matrixC27_29, matrixC26_29, matrixC25_29, matrixC24_29, matrixC23_29, matrixC22_29, matrixC21_29, matrixC20_29, matrixC19_29, matrixC18_29, matrixC17_29, matrixC16_29, matrixC15_29, matrixC14_29, matrixC13_29, matrixC12_29, matrixC11_29, matrixC10_29, matrixC9_29, matrixC8_29, matrixC7_29, matrixC6_29, matrixC5_29, matrixC4_29, matrixC3_29, matrixC2_29, matrixC1_29, matrixC0_29}; + c_data_out_3 <= {matrixC31_28, matrixC30_28, matrixC29_28, matrixC28_28, matrixC27_28, matrixC26_28, matrixC25_28, matrixC24_28, matrixC23_28, matrixC22_28, matrixC21_28, matrixC20_28, matrixC19_28, matrixC18_28, matrixC17_28, matrixC16_28, matrixC15_28, matrixC14_28, matrixC13_28, matrixC12_28, matrixC11_28, matrixC10_28, matrixC9_28, matrixC8_28, matrixC7_28, matrixC6_28, matrixC5_28, matrixC4_28, matrixC3_28, matrixC2_28, matrixC1_28, matrixC0_28}; + c_data_out_4 <= {matrixC31_27, matrixC30_27, matrixC29_27, matrixC28_27, matrixC27_27, matrixC26_27, matrixC25_27, matrixC24_27, matrixC23_27, matrixC22_27, matrixC21_27, matrixC20_27, matrixC19_27, matrixC18_27, matrixC17_27, matrixC16_27, matrixC15_27, matrixC14_27, matrixC13_27, matrixC12_27, matrixC11_27, matrixC10_27, matrixC9_27, matrixC8_27, matrixC7_27, matrixC6_27, matrixC5_27, matrixC4_27, matrixC3_27, matrixC2_27, matrixC1_27, matrixC0_27}; + c_data_out_5 <= {matrixC31_26, matrixC30_26, matrixC29_26, matrixC28_26, matrixC27_26, matrixC26_26, matrixC25_26, matrixC24_26, matrixC23_26, matrixC22_26, matrixC21_26, matrixC20_26, matrixC19_26, matrixC18_26, matrixC17_26, matrixC16_26, matrixC15_26, matrixC14_26, matrixC13_26, matrixC12_26, matrixC11_26, matrixC10_26, matrixC9_26, matrixC8_26, matrixC7_26, matrixC6_26, matrixC5_26, matrixC4_26, matrixC3_26, matrixC2_26, matrixC1_26, matrixC0_26}; + c_data_out_6 <= {matrixC31_25, matrixC30_25, matrixC29_25, matrixC28_25, matrixC27_25, matrixC26_25, matrixC25_25, matrixC24_25, matrixC23_25, matrixC22_25, matrixC21_25, matrixC20_25, matrixC19_25, matrixC18_25, matrixC17_25, matrixC16_25, matrixC15_25, matrixC14_25, matrixC13_25, matrixC12_25, matrixC11_25, matrixC10_25, matrixC9_25, matrixC8_25, matrixC7_25, matrixC6_25, matrixC5_25, matrixC4_25, matrixC3_25, matrixC2_25, matrixC1_25, matrixC0_25}; + c_data_out_7 <= {matrixC31_24, matrixC30_24, matrixC29_24, matrixC28_24, matrixC27_24, matrixC26_24, matrixC25_24, matrixC24_24, matrixC23_24, matrixC22_24, matrixC21_24, matrixC20_24, matrixC19_24, matrixC18_24, matrixC17_24, matrixC16_24, matrixC15_24, matrixC14_24, matrixC13_24, matrixC12_24, matrixC11_24, matrixC10_24, matrixC9_24, matrixC8_24, matrixC7_24, matrixC6_24, matrixC5_24, matrixC4_24, matrixC3_24, matrixC2_24, matrixC1_24, matrixC0_24}; + c_data_out_8 <= {matrixC31_23, matrixC30_23, matrixC29_23, matrixC28_23, matrixC27_23, matrixC26_23, matrixC25_23, matrixC24_23, matrixC23_23, matrixC22_23, matrixC21_23, matrixC20_23, matrixC19_23, matrixC18_23, matrixC17_23, matrixC16_23, matrixC15_23, matrixC14_23, matrixC13_23, matrixC12_23, matrixC11_23, matrixC10_23, matrixC9_23, matrixC8_23, matrixC7_23, matrixC6_23, matrixC5_23, matrixC4_23, matrixC3_23, matrixC2_23, matrixC1_23, matrixC0_23}; + c_data_out_9 <= {matrixC31_22, matrixC30_22, matrixC29_22, matrixC28_22, matrixC27_22, matrixC26_22, matrixC25_22, matrixC24_22, matrixC23_22, matrixC22_22, matrixC21_22, matrixC20_22, matrixC19_22, matrixC18_22, matrixC17_22, matrixC16_22, matrixC15_22, matrixC14_22, matrixC13_22, matrixC12_22, matrixC11_22, matrixC10_22, matrixC9_22, matrixC8_22, matrixC7_22, matrixC6_22, matrixC5_22, matrixC4_22, matrixC3_22, matrixC2_22, matrixC1_22, matrixC0_22}; + c_data_out_10 <= {matrixC31_21, matrixC30_21, matrixC29_21, matrixC28_21, matrixC27_21, matrixC26_21, matrixC25_21, matrixC24_21, matrixC23_21, matrixC22_21, matrixC21_21, matrixC20_21, matrixC19_21, matrixC18_21, matrixC17_21, matrixC16_21, matrixC15_21, matrixC14_21, matrixC13_21, matrixC12_21, matrixC11_21, matrixC10_21, matrixC9_21, matrixC8_21, matrixC7_21, matrixC6_21, matrixC5_21, matrixC4_21, matrixC3_21, matrixC2_21, matrixC1_21, matrixC0_21}; + c_data_out_11 <= {matrixC31_20, matrixC30_20, matrixC29_20, matrixC28_20, matrixC27_20, matrixC26_20, matrixC25_20, matrixC24_20, matrixC23_20, matrixC22_20, matrixC21_20, matrixC20_20, matrixC19_20, matrixC18_20, matrixC17_20, matrixC16_20, matrixC15_20, matrixC14_20, matrixC13_20, matrixC12_20, matrixC11_20, matrixC10_20, matrixC9_20, matrixC8_20, matrixC7_20, matrixC6_20, matrixC5_20, matrixC4_20, matrixC3_20, matrixC2_20, matrixC1_20, matrixC0_20}; + c_data_out_12 <= {matrixC31_19, matrixC30_19, matrixC29_19, matrixC28_19, matrixC27_19, matrixC26_19, matrixC25_19, matrixC24_19, matrixC23_19, matrixC22_19, matrixC21_19, matrixC20_19, matrixC19_19, matrixC18_19, matrixC17_19, matrixC16_19, matrixC15_19, matrixC14_19, matrixC13_19, matrixC12_19, matrixC11_19, matrixC10_19, matrixC9_19, matrixC8_19, matrixC7_19, matrixC6_19, matrixC5_19, matrixC4_19, matrixC3_19, matrixC2_19, matrixC1_19, matrixC0_19}; + c_data_out_13 <= {matrixC31_18, matrixC30_18, matrixC29_18, matrixC28_18, matrixC27_18, matrixC26_18, matrixC25_18, matrixC24_18, matrixC23_18, matrixC22_18, matrixC21_18, matrixC20_18, matrixC19_18, matrixC18_18, matrixC17_18, matrixC16_18, matrixC15_18, matrixC14_18, matrixC13_18, matrixC12_18, matrixC11_18, matrixC10_18, matrixC9_18, matrixC8_18, matrixC7_18, matrixC6_18, matrixC5_18, matrixC4_18, matrixC3_18, matrixC2_18, matrixC1_18, matrixC0_18}; + c_data_out_14 <= {matrixC31_17, matrixC30_17, matrixC29_17, matrixC28_17, matrixC27_17, matrixC26_17, matrixC25_17, matrixC24_17, matrixC23_17, matrixC22_17, matrixC21_17, matrixC20_17, matrixC19_17, matrixC18_17, matrixC17_17, matrixC16_17, matrixC15_17, matrixC14_17, matrixC13_17, matrixC12_17, matrixC11_17, matrixC10_17, matrixC9_17, matrixC8_17, matrixC7_17, matrixC6_17, matrixC5_17, matrixC4_17, matrixC3_17, matrixC2_17, matrixC1_17, matrixC0_17}; + c_data_out_15 <= {matrixC31_16, matrixC30_16, matrixC29_16, matrixC28_16, matrixC27_16, matrixC26_16, matrixC25_16, matrixC24_16, matrixC23_16, matrixC22_16, matrixC21_16, matrixC20_16, matrixC19_16, matrixC18_16, matrixC17_16, matrixC16_16, matrixC15_16, matrixC14_16, matrixC13_16, matrixC12_16, matrixC11_16, matrixC10_16, matrixC9_16, matrixC8_16, matrixC7_16, matrixC6_16, matrixC5_16, matrixC4_16, matrixC3_16, matrixC2_16, matrixC1_16, matrixC0_16}; + c_data_out_16 <= {matrixC31_15, matrixC30_15, matrixC29_15, matrixC28_15, matrixC27_15, matrixC26_15, matrixC25_15, matrixC24_15, matrixC23_15, matrixC22_15, matrixC21_15, matrixC20_15, matrixC19_15, matrixC18_15, matrixC17_15, matrixC16_15, matrixC15_15, matrixC14_15, matrixC13_15, matrixC12_15, matrixC11_15, matrixC10_15, matrixC9_15, matrixC8_15, matrixC7_15, matrixC6_15, matrixC5_15, matrixC4_15, matrixC3_15, matrixC2_15, matrixC1_15, matrixC0_15}; + c_data_out_17 <= {matrixC31_14, matrixC30_14, matrixC29_14, matrixC28_14, matrixC27_14, matrixC26_14, matrixC25_14, matrixC24_14, matrixC23_14, matrixC22_14, matrixC21_14, matrixC20_14, matrixC19_14, matrixC18_14, matrixC17_14, matrixC16_14, matrixC15_14, matrixC14_14, matrixC13_14, matrixC12_14, matrixC11_14, matrixC10_14, matrixC9_14, matrixC8_14, matrixC7_14, matrixC6_14, matrixC5_14, matrixC4_14, matrixC3_14, matrixC2_14, matrixC1_14, matrixC0_14}; + c_data_out_18 <= {matrixC31_13, matrixC30_13, matrixC29_13, matrixC28_13, matrixC27_13, matrixC26_13, matrixC25_13, matrixC24_13, matrixC23_13, matrixC22_13, matrixC21_13, matrixC20_13, matrixC19_13, matrixC18_13, matrixC17_13, matrixC16_13, matrixC15_13, matrixC14_13, matrixC13_13, matrixC12_13, matrixC11_13, matrixC10_13, matrixC9_13, matrixC8_13, matrixC7_13, matrixC6_13, matrixC5_13, matrixC4_13, matrixC3_13, matrixC2_13, matrixC1_13, matrixC0_13}; + c_data_out_19 <= {matrixC31_12, matrixC30_12, matrixC29_12, matrixC28_12, matrixC27_12, matrixC26_12, matrixC25_12, matrixC24_12, matrixC23_12, matrixC22_12, matrixC21_12, matrixC20_12, matrixC19_12, matrixC18_12, matrixC17_12, matrixC16_12, matrixC15_12, matrixC14_12, matrixC13_12, matrixC12_12, matrixC11_12, matrixC10_12, matrixC9_12, matrixC8_12, matrixC7_12, matrixC6_12, matrixC5_12, matrixC4_12, matrixC3_12, matrixC2_12, matrixC1_12, matrixC0_12}; + c_data_out_20 <= {matrixC31_11, matrixC30_11, matrixC29_11, matrixC28_11, matrixC27_11, matrixC26_11, matrixC25_11, matrixC24_11, matrixC23_11, matrixC22_11, matrixC21_11, matrixC20_11, matrixC19_11, matrixC18_11, matrixC17_11, matrixC16_11, matrixC15_11, matrixC14_11, matrixC13_11, matrixC12_11, matrixC11_11, matrixC10_11, matrixC9_11, matrixC8_11, matrixC7_11, matrixC6_11, matrixC5_11, matrixC4_11, matrixC3_11, matrixC2_11, matrixC1_11, matrixC0_11}; + c_data_out_21 <= {matrixC31_10, matrixC30_10, matrixC29_10, matrixC28_10, matrixC27_10, matrixC26_10, matrixC25_10, matrixC24_10, matrixC23_10, matrixC22_10, matrixC21_10, matrixC20_10, matrixC19_10, matrixC18_10, matrixC17_10, matrixC16_10, matrixC15_10, matrixC14_10, matrixC13_10, matrixC12_10, matrixC11_10, matrixC10_10, matrixC9_10, matrixC8_10, matrixC7_10, matrixC6_10, matrixC5_10, matrixC4_10, matrixC3_10, matrixC2_10, matrixC1_10, matrixC0_10}; + c_data_out_22 <= {matrixC31_9, matrixC30_9, matrixC29_9, matrixC28_9, matrixC27_9, matrixC26_9, matrixC25_9, matrixC24_9, matrixC23_9, matrixC22_9, matrixC21_9, matrixC20_9, matrixC19_9, matrixC18_9, matrixC17_9, matrixC16_9, matrixC15_9, matrixC14_9, matrixC13_9, matrixC12_9, matrixC11_9, matrixC10_9, matrixC9_9, matrixC8_9, matrixC7_9, matrixC6_9, matrixC5_9, matrixC4_9, matrixC3_9, matrixC2_9, matrixC1_9, matrixC0_9}; + c_data_out_23 <= {matrixC31_8, matrixC30_8, matrixC29_8, matrixC28_8, matrixC27_8, matrixC26_8, matrixC25_8, matrixC24_8, matrixC23_8, matrixC22_8, matrixC21_8, matrixC20_8, matrixC19_8, matrixC18_8, matrixC17_8, matrixC16_8, matrixC15_8, matrixC14_8, matrixC13_8, matrixC12_8, matrixC11_8, matrixC10_8, matrixC9_8, matrixC8_8, matrixC7_8, matrixC6_8, matrixC5_8, matrixC4_8, matrixC3_8, matrixC2_8, matrixC1_8, matrixC0_8}; + c_data_out_24 <= {matrixC31_7, matrixC30_7, matrixC29_7, matrixC28_7, matrixC27_7, matrixC26_7, matrixC25_7, matrixC24_7, matrixC23_7, matrixC22_7, matrixC21_7, matrixC20_7, matrixC19_7, matrixC18_7, matrixC17_7, matrixC16_7, matrixC15_7, matrixC14_7, matrixC13_7, matrixC12_7, matrixC11_7, matrixC10_7, matrixC9_7, matrixC8_7, matrixC7_7, matrixC6_7, matrixC5_7, matrixC4_7, matrixC3_7, matrixC2_7, matrixC1_7, matrixC0_7}; + c_data_out_25 <= {matrixC31_6, matrixC30_6, matrixC29_6, matrixC28_6, matrixC27_6, matrixC26_6, matrixC25_6, matrixC24_6, matrixC23_6, matrixC22_6, matrixC21_6, matrixC20_6, matrixC19_6, matrixC18_6, matrixC17_6, matrixC16_6, matrixC15_6, matrixC14_6, matrixC13_6, matrixC12_6, matrixC11_6, matrixC10_6, matrixC9_6, matrixC8_6, matrixC7_6, matrixC6_6, matrixC5_6, matrixC4_6, matrixC3_6, matrixC2_6, matrixC1_6, matrixC0_6}; + c_data_out_26 <= {matrixC31_5, matrixC30_5, matrixC29_5, matrixC28_5, matrixC27_5, matrixC26_5, matrixC25_5, matrixC24_5, matrixC23_5, matrixC22_5, matrixC21_5, matrixC20_5, matrixC19_5, matrixC18_5, matrixC17_5, matrixC16_5, matrixC15_5, matrixC14_5, matrixC13_5, matrixC12_5, matrixC11_5, matrixC10_5, matrixC9_5, matrixC8_5, matrixC7_5, matrixC6_5, matrixC5_5, matrixC4_5, matrixC3_5, matrixC2_5, matrixC1_5, matrixC0_5}; + c_data_out_27 <= {matrixC31_4, matrixC30_4, matrixC29_4, matrixC28_4, matrixC27_4, matrixC26_4, matrixC25_4, matrixC24_4, matrixC23_4, matrixC22_4, matrixC21_4, matrixC20_4, matrixC19_4, matrixC18_4, matrixC17_4, matrixC16_4, matrixC15_4, matrixC14_4, matrixC13_4, matrixC12_4, matrixC11_4, matrixC10_4, matrixC9_4, matrixC8_4, matrixC7_4, matrixC6_4, matrixC5_4, matrixC4_4, matrixC3_4, matrixC2_4, matrixC1_4, matrixC0_4}; + c_data_out_28 <= {matrixC31_3, matrixC30_3, matrixC29_3, matrixC28_3, matrixC27_3, matrixC26_3, matrixC25_3, matrixC24_3, matrixC23_3, matrixC22_3, matrixC21_3, matrixC20_3, matrixC19_3, matrixC18_3, matrixC17_3, matrixC16_3, matrixC15_3, matrixC14_3, matrixC13_3, matrixC12_3, matrixC11_3, matrixC10_3, matrixC9_3, matrixC8_3, matrixC7_3, matrixC6_3, matrixC5_3, matrixC4_3, matrixC3_3, matrixC2_3, matrixC1_3, matrixC0_3}; + c_data_out_29 <= {matrixC31_2, matrixC30_2, matrixC29_2, matrixC28_2, matrixC27_2, matrixC26_2, matrixC25_2, matrixC24_2, matrixC23_2, matrixC22_2, matrixC21_2, matrixC20_2, matrixC19_2, matrixC18_2, matrixC17_2, matrixC16_2, matrixC15_2, matrixC14_2, matrixC13_2, matrixC12_2, matrixC11_2, matrixC10_2, matrixC9_2, matrixC8_2, matrixC7_2, matrixC6_2, matrixC5_2, matrixC4_2, matrixC3_2, matrixC2_2, matrixC1_2, matrixC0_2}; + c_data_out_30 <= {matrixC31_1, matrixC30_1, matrixC29_1, matrixC28_1, matrixC27_1, matrixC26_1, matrixC25_1, matrixC24_1, matrixC23_1, matrixC22_1, matrixC21_1, matrixC20_1, matrixC19_1, matrixC18_1, matrixC17_1, matrixC16_1, matrixC15_1, matrixC14_1, matrixC13_1, matrixC12_1, matrixC11_1, matrixC10_1, matrixC9_1, matrixC8_1, matrixC7_1, matrixC6_1, matrixC5_1, matrixC4_1, matrixC3_1, matrixC2_1, matrixC1_1, matrixC0_1}; + c_data_out_31 <= {matrixC31_0, matrixC30_0, matrixC29_0, matrixC28_0, matrixC27_0, matrixC26_0, matrixC25_0, matrixC24_0, matrixC23_0, matrixC22_0, matrixC21_0, matrixC20_0, matrixC19_0, matrixC18_0, matrixC17_0, matrixC16_0, matrixC15_0, matrixC14_0, matrixC13_0, matrixC12_0, matrixC11_0, matrixC10_0, matrixC9_0, matrixC8_0, matrixC7_0, matrixC6_0, matrixC5_0, matrixC4_0, matrixC3_0, matrixC2_0, matrixC1_0, matrixC0_0}; + + counter <= counter + 1; + end else if (done_mat_mul) begin + start_capturing_c_data <= 1'b0; + c_data_available <= 1'b0; + c_addr <= address_mat_c + address_stride_c; + c_data_out <= 0; + + c_data_out_1 <= 0; + c_data_out_2 <= 0; + c_data_out_3 <= 0; + c_data_out_4 <= 0; + c_data_out_5 <= 0; + c_data_out_6 <= 0; + c_data_out_7 <= 0; + c_data_out_8 <= 0; + c_data_out_9 <= 0; + c_data_out_10 <= 0; + c_data_out_11 <= 0; + c_data_out_12 <= 0; + c_data_out_13 <= 0; + c_data_out_14 <= 0; + c_data_out_15 <= 0; + c_data_out_16 <= 0; + c_data_out_17 <= 0; + c_data_out_18 <= 0; + c_data_out_19 <= 0; + c_data_out_20 <= 0; + c_data_out_21 <= 0; + c_data_out_22 <= 0; + c_data_out_23 <= 0; + c_data_out_24 <= 0; + c_data_out_25 <= 0; + c_data_out_26 <= 0; + c_data_out_27 <= 0; + c_data_out_28 <= 0; + c_data_out_29 <= 0; + c_data_out_30 <= 0; + c_data_out_31 <= 0; + end + else if (counter >= `MAT_MUL_SIZE) begin + c_data_out <= c_data_out_1; + c_addr <= c_addr - address_stride_c; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_out_20; + c_data_out_20 <= c_data_out_21; + c_data_out_21 <= c_data_out_22; + c_data_out_22 <= c_data_out_23; + c_data_out_23 <= c_data_out_24; + c_data_out_24 <= c_data_out_25; + c_data_out_25 <= c_data_out_26; + c_data_out_26 <= c_data_out_27; + c_data_out_27 <= c_data_out_28; + c_data_out_28 <= c_data_out_29; + c_data_out_29 <= c_data_out_30; + c_data_out_30 <= c_data_out_31; + c_data_out_31 <= c_data_in; + end + else if (start_capturing_c_data) begin + c_data_available <= 1'b1; + c_addr <= c_addr - address_stride_c; + counter <= counter + 1; + c_data_out <= c_data_out_1; + + c_data_out_1 <= c_data_out_2; + c_data_out_2 <= c_data_out_3; + c_data_out_3 <= c_data_out_4; + c_data_out_4 <= c_data_out_5; + c_data_out_5 <= c_data_out_6; + c_data_out_6 <= c_data_out_7; + c_data_out_7 <= c_data_out_8; + c_data_out_8 <= c_data_out_9; + c_data_out_9 <= c_data_out_10; + c_data_out_10 <= c_data_out_11; + c_data_out_11 <= c_data_out_12; + c_data_out_12 <= c_data_out_13; + c_data_out_13 <= c_data_out_14; + c_data_out_14 <= c_data_out_15; + c_data_out_15 <= c_data_out_16; + c_data_out_16 <= c_data_out_17; + c_data_out_17 <= c_data_out_18; + c_data_out_18 <= c_data_out_19; + c_data_out_19 <= c_data_out_20; + c_data_out_20 <= c_data_out_21; + c_data_out_21 <= c_data_out_22; + c_data_out_22 <= c_data_out_23; + c_data_out_23 <= c_data_out_24; + c_data_out_24 <= c_data_out_25; + c_data_out_25 <= c_data_out_26; + c_data_out_26 <= c_data_out_27; + c_data_out_27 <= c_data_out_28; + c_data_out_28 <= c_data_out_29; + c_data_out_29 <= c_data_out_30; + c_data_out_30 <= c_data_out_31; + c_data_out_31 <= c_data_in; + end +end + +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolic data setup +////////////////////////////////////////////////////////////////////////// +module systolic_data_setup( +clk, +reset, +start_mat_mul, +a_addr, +b_addr, +address_mat_a, +address_mat_b, +address_stride_a, +address_stride_b, +a_data, +b_data, +clk_cnt, +a0_data, +b0_data, +a1_data_delayed_1, +b1_data_delayed_1, +a2_data_delayed_2, +b2_data_delayed_2, +a3_data_delayed_3, +b3_data_delayed_3, +a4_data_delayed_4, +b4_data_delayed_4, +a5_data_delayed_5, +b5_data_delayed_5, +a6_data_delayed_6, +b6_data_delayed_6, +a7_data_delayed_7, +b7_data_delayed_7, +a8_data_delayed_8, +b8_data_delayed_8, +a9_data_delayed_9, +b9_data_delayed_9, +a10_data_delayed_10, +b10_data_delayed_10, +a11_data_delayed_11, +b11_data_delayed_11, +a12_data_delayed_12, +b12_data_delayed_12, +a13_data_delayed_13, +b13_data_delayed_13, +a14_data_delayed_14, +b14_data_delayed_14, +a15_data_delayed_15, +b15_data_delayed_15, +a16_data_delayed_16, +b16_data_delayed_16, +a17_data_delayed_17, +b17_data_delayed_17, +a18_data_delayed_18, +b18_data_delayed_18, +a19_data_delayed_19, +b19_data_delayed_19, +a20_data_delayed_20, +b20_data_delayed_20, +a21_data_delayed_21, +b21_data_delayed_21, +a22_data_delayed_22, +b22_data_delayed_22, +a23_data_delayed_23, +b23_data_delayed_23, +a24_data_delayed_24, +b24_data_delayed_24, +a25_data_delayed_25, +b25_data_delayed_25, +a26_data_delayed_26, +b26_data_delayed_26, +a27_data_delayed_27, +b27_data_delayed_27, +a28_data_delayed_28, +b28_data_delayed_28, +a29_data_delayed_29, +b29_data_delayed_29, +a30_data_delayed_30, +b30_data_delayed_30, +a31_data_delayed_31, +b31_data_delayed_31, + +validity_mask_a_rows, +validity_mask_a_cols, +validity_mask_b_rows, +validity_mask_b_cols, + +final_mat_mul_size, + +a_loc, +b_loc +); + +input clk; +input reset; +input start_mat_mul; +output [`AWIDTH-1:0] a_addr; +output [`AWIDTH-1:0] b_addr; +input [`AWIDTH-1:0] address_mat_a; +input [`AWIDTH-1:0] address_mat_b; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +input [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data; +input [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data; +input [7:0] clk_cnt; +output [`DWIDTH-1:0] a0_data; +output [`DWIDTH-1:0] b0_data; +output [`DWIDTH-1:0] a1_data_delayed_1; +output [`DWIDTH-1:0] b1_data_delayed_1; +output [`DWIDTH-1:0] a2_data_delayed_2; +output [`DWIDTH-1:0] b2_data_delayed_2; +output [`DWIDTH-1:0] a3_data_delayed_3; +output [`DWIDTH-1:0] b3_data_delayed_3; +output [`DWIDTH-1:0] a4_data_delayed_4; +output [`DWIDTH-1:0] b4_data_delayed_4; +output [`DWIDTH-1:0] a5_data_delayed_5; +output [`DWIDTH-1:0] b5_data_delayed_5; +output [`DWIDTH-1:0] a6_data_delayed_6; +output [`DWIDTH-1:0] b6_data_delayed_6; +output [`DWIDTH-1:0] a7_data_delayed_7; +output [`DWIDTH-1:0] b7_data_delayed_7; +output [`DWIDTH-1:0] a8_data_delayed_8; +output [`DWIDTH-1:0] b8_data_delayed_8; +output [`DWIDTH-1:0] a9_data_delayed_9; +output [`DWIDTH-1:0] b9_data_delayed_9; +output [`DWIDTH-1:0] a10_data_delayed_10; +output [`DWIDTH-1:0] b10_data_delayed_10; +output [`DWIDTH-1:0] a11_data_delayed_11; +output [`DWIDTH-1:0] b11_data_delayed_11; +output [`DWIDTH-1:0] a12_data_delayed_12; +output [`DWIDTH-1:0] b12_data_delayed_12; +output [`DWIDTH-1:0] a13_data_delayed_13; +output [`DWIDTH-1:0] b13_data_delayed_13; +output [`DWIDTH-1:0] a14_data_delayed_14; +output [`DWIDTH-1:0] b14_data_delayed_14; +output [`DWIDTH-1:0] a15_data_delayed_15; +output [`DWIDTH-1:0] b15_data_delayed_15; +output [`DWIDTH-1:0] a16_data_delayed_16; +output [`DWIDTH-1:0] b16_data_delayed_16; +output [`DWIDTH-1:0] a17_data_delayed_17; +output [`DWIDTH-1:0] b17_data_delayed_17; +output [`DWIDTH-1:0] a18_data_delayed_18; +output [`DWIDTH-1:0] b18_data_delayed_18; +output [`DWIDTH-1:0] a19_data_delayed_19; +output [`DWIDTH-1:0] b19_data_delayed_19; +output [`DWIDTH-1:0] a20_data_delayed_20; +output [`DWIDTH-1:0] b20_data_delayed_20; +output [`DWIDTH-1:0] a21_data_delayed_21; +output [`DWIDTH-1:0] b21_data_delayed_21; +output [`DWIDTH-1:0] a22_data_delayed_22; +output [`DWIDTH-1:0] b22_data_delayed_22; +output [`DWIDTH-1:0] a23_data_delayed_23; +output [`DWIDTH-1:0] b23_data_delayed_23; +output [`DWIDTH-1:0] a24_data_delayed_24; +output [`DWIDTH-1:0] b24_data_delayed_24; +output [`DWIDTH-1:0] a25_data_delayed_25; +output [`DWIDTH-1:0] b25_data_delayed_25; +output [`DWIDTH-1:0] a26_data_delayed_26; +output [`DWIDTH-1:0] b26_data_delayed_26; +output [`DWIDTH-1:0] a27_data_delayed_27; +output [`DWIDTH-1:0] b27_data_delayed_27; +output [`DWIDTH-1:0] a28_data_delayed_28; +output [`DWIDTH-1:0] b28_data_delayed_28; +output [`DWIDTH-1:0] a29_data_delayed_29; +output [`DWIDTH-1:0] b29_data_delayed_29; +output [`DWIDTH-1:0] a30_data_delayed_30; +output [`DWIDTH-1:0] b30_data_delayed_30; +output [`DWIDTH-1:0] a31_data_delayed_31; +output [`DWIDTH-1:0] b31_data_delayed_31; + +input [`MASK_WIDTH-1:0] validity_mask_a_rows; +input [`MASK_WIDTH-1:0] validity_mask_a_cols; +input [`MASK_WIDTH-1:0] validity_mask_b_rows; +input [`MASK_WIDTH-1:0] validity_mask_b_cols; + +input [7:0] final_mat_mul_size; + +input [7:0] a_loc; +input [7:0] b_loc; +wire [`DWIDTH-1:0] a0_data; +wire [`DWIDTH-1:0] a1_data; +wire [`DWIDTH-1:0] a2_data; +wire [`DWIDTH-1:0] a3_data; +wire [`DWIDTH-1:0] a4_data; +wire [`DWIDTH-1:0] a5_data; +wire [`DWIDTH-1:0] a6_data; +wire [`DWIDTH-1:0] a7_data; +wire [`DWIDTH-1:0] a8_data; +wire [`DWIDTH-1:0] a9_data; +wire [`DWIDTH-1:0] a10_data; +wire [`DWIDTH-1:0] a11_data; +wire [`DWIDTH-1:0] a12_data; +wire [`DWIDTH-1:0] a13_data; +wire [`DWIDTH-1:0] a14_data; +wire [`DWIDTH-1:0] a15_data; +wire [`DWIDTH-1:0] a16_data; +wire [`DWIDTH-1:0] a17_data; +wire [`DWIDTH-1:0] a18_data; +wire [`DWIDTH-1:0] a19_data; +wire [`DWIDTH-1:0] a20_data; +wire [`DWIDTH-1:0] a21_data; +wire [`DWIDTH-1:0] a22_data; +wire [`DWIDTH-1:0] a23_data; +wire [`DWIDTH-1:0] a24_data; +wire [`DWIDTH-1:0] a25_data; +wire [`DWIDTH-1:0] a26_data; +wire [`DWIDTH-1:0] a27_data; +wire [`DWIDTH-1:0] a28_data; +wire [`DWIDTH-1:0] a29_data; +wire [`DWIDTH-1:0] a30_data; +wire [`DWIDTH-1:0] a31_data; +wire [`DWIDTH-1:0] b0_data; +wire [`DWIDTH-1:0] b1_data; +wire [`DWIDTH-1:0] b2_data; +wire [`DWIDTH-1:0] b3_data; +wire [`DWIDTH-1:0] b4_data; +wire [`DWIDTH-1:0] b5_data; +wire [`DWIDTH-1:0] b6_data; +wire [`DWIDTH-1:0] b7_data; +wire [`DWIDTH-1:0] b8_data; +wire [`DWIDTH-1:0] b9_data; +wire [`DWIDTH-1:0] b10_data; +wire [`DWIDTH-1:0] b11_data; +wire [`DWIDTH-1:0] b12_data; +wire [`DWIDTH-1:0] b13_data; +wire [`DWIDTH-1:0] b14_data; +wire [`DWIDTH-1:0] b15_data; +wire [`DWIDTH-1:0] b16_data; +wire [`DWIDTH-1:0] b17_data; +wire [`DWIDTH-1:0] b18_data; +wire [`DWIDTH-1:0] b19_data; +wire [`DWIDTH-1:0] b20_data; +wire [`DWIDTH-1:0] b21_data; +wire [`DWIDTH-1:0] b22_data; +wire [`DWIDTH-1:0] b23_data; +wire [`DWIDTH-1:0] b24_data; +wire [`DWIDTH-1:0] b25_data; +wire [`DWIDTH-1:0] b26_data; +wire [`DWIDTH-1:0] b27_data; +wire [`DWIDTH-1:0] b28_data; +wire [`DWIDTH-1:0] b29_data; +wire [`DWIDTH-1:0] b30_data; +wire [`DWIDTH-1:0] b31_data; + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM A +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] a_addr; +reg a_mem_access; //flag that tells whether the matmul is trying to access memory or not + +always @(posedge clk) begin + //(clk_cnt >= a_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if (reset || ~start_mat_mul || (clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= address_mat_a-address_stride_a; + + a_mem_access <= 0; + end + //else if ((clk_cnt >= a_loc*`MAT_MUL_SIZE) && (clk_cnt < a_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (a_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (a_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + a_addr <= a_addr + address_stride_a; + + a_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM A +////////////////////////////////////////////////////////////////////////// +reg [7:0] a_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + a_mem_access_counter <= 0; + end + else if (a_mem_access == 1) begin + a_mem_access_counter <= a_mem_access_counter + 1; + end + else begin + a_mem_access_counter <= 0; + end +end + +wire a_data_valid; //flag that tells whether the data from memory is valid +assign a_data_valid = + ((validity_mask_a_cols[0]==1'b0 && a_mem_access_counter==1) || + (validity_mask_a_cols[1]==1'b0 && a_mem_access_counter==2) || + (validity_mask_a_cols[2]==1'b0 && a_mem_access_counter==3) || + (validity_mask_a_cols[3]==1'b0 && a_mem_access_counter==4) || + (validity_mask_a_cols[4]==1'b0 && a_mem_access_counter==5) || + (validity_mask_a_cols[5]==1'b0 && a_mem_access_counter==6) || + (validity_mask_a_cols[6]==1'b0 && a_mem_access_counter==7) || + (validity_mask_a_cols[7]==1'b0 && a_mem_access_counter==8) || + (validity_mask_a_cols[8]==1'b0 && a_mem_access_counter==9) || + (validity_mask_a_cols[9]==1'b0 && a_mem_access_counter==10) || + (validity_mask_a_cols[10]==1'b0 && a_mem_access_counter==11) || + (validity_mask_a_cols[11]==1'b0 && a_mem_access_counter==12) || + (validity_mask_a_cols[12]==1'b0 && a_mem_access_counter==13) || + (validity_mask_a_cols[13]==1'b0 && a_mem_access_counter==14) || + (validity_mask_a_cols[14]==1'b0 && a_mem_access_counter==15) || + (validity_mask_a_cols[15]==1'b0 && a_mem_access_counter==16) || + (validity_mask_a_cols[16]==1'b0 && a_mem_access_counter==17) || + (validity_mask_a_cols[17]==1'b0 && a_mem_access_counter==18) || + (validity_mask_a_cols[18]==1'b0 && a_mem_access_counter==19) || + (validity_mask_a_cols[19]==1'b0 && a_mem_access_counter==20) || + (validity_mask_a_cols[20]==1'b0 && a_mem_access_counter==21) || + (validity_mask_a_cols[21]==1'b0 && a_mem_access_counter==22) || + (validity_mask_a_cols[22]==1'b0 && a_mem_access_counter==23) || + (validity_mask_a_cols[23]==1'b0 && a_mem_access_counter==24) || + (validity_mask_a_cols[24]==1'b0 && a_mem_access_counter==25) || + (validity_mask_a_cols[25]==1'b0 && a_mem_access_counter==26) || + (validity_mask_a_cols[26]==1'b0 && a_mem_access_counter==27) || + (validity_mask_a_cols[27]==1'b0 && a_mem_access_counter==28) || + (validity_mask_a_cols[28]==1'b0 && a_mem_access_counter==29) || + (validity_mask_a_cols[29]==1'b0 && a_mem_access_counter==30) || + (validity_mask_a_cols[30]==1'b0 && a_mem_access_counter==31) || + (validity_mask_a_cols[31]==1'b0 && a_mem_access_counter==32)) ? + + 1'b0 : (a_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM A (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign a0_data = a_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[0]}}; +assign a1_data = a_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[1]}}; +assign a2_data = a_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[2]}}; +assign a3_data = a_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[3]}}; +assign a4_data = a_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[4]}}; +assign a5_data = a_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[5]}}; +assign a6_data = a_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[6]}}; +assign a7_data = a_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[7]}}; +assign a8_data = a_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[8]}}; +assign a9_data = a_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[9]}}; +assign a10_data = a_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[10]}}; +assign a11_data = a_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[11]}}; +assign a12_data = a_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[12]}}; +assign a13_data = a_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[13]}}; +assign a14_data = a_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[14]}}; +assign a15_data = a_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[15]}}; +assign a16_data = a_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[16]}}; +assign a17_data = a_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[17]}}; +assign a18_data = a_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[18]}}; +assign a19_data = a_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[19]}}; +assign a20_data = a_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[20]}}; +assign a21_data = a_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[21]}}; +assign a22_data = a_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[22]}}; +assign a23_data = a_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[23]}}; +assign a24_data = a_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[24]}}; +assign a25_data = a_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[25]}}; +assign a26_data = a_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[26]}}; +assign a27_data = a_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[27]}}; +assign a28_data = a_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[28]}}; +assign a29_data = a_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[29]}}; +assign a30_data = a_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[30]}}; +assign a31_data = a_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{a_data_valid}} & {`DWIDTH{validity_mask_a_rows[31]}}; + +reg [`DWIDTH-1:0] a1_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_1; +reg [`DWIDTH-1:0] a2_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_1; +reg [`DWIDTH-1:0] a3_data_delayed_2; +reg [`DWIDTH-1:0] a3_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_1; +reg [`DWIDTH-1:0] a4_data_delayed_2; +reg [`DWIDTH-1:0] a4_data_delayed_3; +reg [`DWIDTH-1:0] a4_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_1; +reg [`DWIDTH-1:0] a5_data_delayed_2; +reg [`DWIDTH-1:0] a5_data_delayed_3; +reg [`DWIDTH-1:0] a5_data_delayed_4; +reg [`DWIDTH-1:0] a5_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_1; +reg [`DWIDTH-1:0] a6_data_delayed_2; +reg [`DWIDTH-1:0] a6_data_delayed_3; +reg [`DWIDTH-1:0] a6_data_delayed_4; +reg [`DWIDTH-1:0] a6_data_delayed_5; +reg [`DWIDTH-1:0] a6_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_1; +reg [`DWIDTH-1:0] a7_data_delayed_2; +reg [`DWIDTH-1:0] a7_data_delayed_3; +reg [`DWIDTH-1:0] a7_data_delayed_4; +reg [`DWIDTH-1:0] a7_data_delayed_5; +reg [`DWIDTH-1:0] a7_data_delayed_6; +reg [`DWIDTH-1:0] a7_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_1; +reg [`DWIDTH-1:0] a8_data_delayed_2; +reg [`DWIDTH-1:0] a8_data_delayed_3; +reg [`DWIDTH-1:0] a8_data_delayed_4; +reg [`DWIDTH-1:0] a8_data_delayed_5; +reg [`DWIDTH-1:0] a8_data_delayed_6; +reg [`DWIDTH-1:0] a8_data_delayed_7; +reg [`DWIDTH-1:0] a8_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_1; +reg [`DWIDTH-1:0] a9_data_delayed_2; +reg [`DWIDTH-1:0] a9_data_delayed_3; +reg [`DWIDTH-1:0] a9_data_delayed_4; +reg [`DWIDTH-1:0] a9_data_delayed_5; +reg [`DWIDTH-1:0] a9_data_delayed_6; +reg [`DWIDTH-1:0] a9_data_delayed_7; +reg [`DWIDTH-1:0] a9_data_delayed_8; +reg [`DWIDTH-1:0] a9_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_1; +reg [`DWIDTH-1:0] a10_data_delayed_2; +reg [`DWIDTH-1:0] a10_data_delayed_3; +reg [`DWIDTH-1:0] a10_data_delayed_4; +reg [`DWIDTH-1:0] a10_data_delayed_5; +reg [`DWIDTH-1:0] a10_data_delayed_6; +reg [`DWIDTH-1:0] a10_data_delayed_7; +reg [`DWIDTH-1:0] a10_data_delayed_8; +reg [`DWIDTH-1:0] a10_data_delayed_9; +reg [`DWIDTH-1:0] a10_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_1; +reg [`DWIDTH-1:0] a11_data_delayed_2; +reg [`DWIDTH-1:0] a11_data_delayed_3; +reg [`DWIDTH-1:0] a11_data_delayed_4; +reg [`DWIDTH-1:0] a11_data_delayed_5; +reg [`DWIDTH-1:0] a11_data_delayed_6; +reg [`DWIDTH-1:0] a11_data_delayed_7; +reg [`DWIDTH-1:0] a11_data_delayed_8; +reg [`DWIDTH-1:0] a11_data_delayed_9; +reg [`DWIDTH-1:0] a11_data_delayed_10; +reg [`DWIDTH-1:0] a11_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_1; +reg [`DWIDTH-1:0] a12_data_delayed_2; +reg [`DWIDTH-1:0] a12_data_delayed_3; +reg [`DWIDTH-1:0] a12_data_delayed_4; +reg [`DWIDTH-1:0] a12_data_delayed_5; +reg [`DWIDTH-1:0] a12_data_delayed_6; +reg [`DWIDTH-1:0] a12_data_delayed_7; +reg [`DWIDTH-1:0] a12_data_delayed_8; +reg [`DWIDTH-1:0] a12_data_delayed_9; +reg [`DWIDTH-1:0] a12_data_delayed_10; +reg [`DWIDTH-1:0] a12_data_delayed_11; +reg [`DWIDTH-1:0] a12_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_1; +reg [`DWIDTH-1:0] a13_data_delayed_2; +reg [`DWIDTH-1:0] a13_data_delayed_3; +reg [`DWIDTH-1:0] a13_data_delayed_4; +reg [`DWIDTH-1:0] a13_data_delayed_5; +reg [`DWIDTH-1:0] a13_data_delayed_6; +reg [`DWIDTH-1:0] a13_data_delayed_7; +reg [`DWIDTH-1:0] a13_data_delayed_8; +reg [`DWIDTH-1:0] a13_data_delayed_9; +reg [`DWIDTH-1:0] a13_data_delayed_10; +reg [`DWIDTH-1:0] a13_data_delayed_11; +reg [`DWIDTH-1:0] a13_data_delayed_12; +reg [`DWIDTH-1:0] a13_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_1; +reg [`DWIDTH-1:0] a14_data_delayed_2; +reg [`DWIDTH-1:0] a14_data_delayed_3; +reg [`DWIDTH-1:0] a14_data_delayed_4; +reg [`DWIDTH-1:0] a14_data_delayed_5; +reg [`DWIDTH-1:0] a14_data_delayed_6; +reg [`DWIDTH-1:0] a14_data_delayed_7; +reg [`DWIDTH-1:0] a14_data_delayed_8; +reg [`DWIDTH-1:0] a14_data_delayed_9; +reg [`DWIDTH-1:0] a14_data_delayed_10; +reg [`DWIDTH-1:0] a14_data_delayed_11; +reg [`DWIDTH-1:0] a14_data_delayed_12; +reg [`DWIDTH-1:0] a14_data_delayed_13; +reg [`DWIDTH-1:0] a14_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_1; +reg [`DWIDTH-1:0] a15_data_delayed_2; +reg [`DWIDTH-1:0] a15_data_delayed_3; +reg [`DWIDTH-1:0] a15_data_delayed_4; +reg [`DWIDTH-1:0] a15_data_delayed_5; +reg [`DWIDTH-1:0] a15_data_delayed_6; +reg [`DWIDTH-1:0] a15_data_delayed_7; +reg [`DWIDTH-1:0] a15_data_delayed_8; +reg [`DWIDTH-1:0] a15_data_delayed_9; +reg [`DWIDTH-1:0] a15_data_delayed_10; +reg [`DWIDTH-1:0] a15_data_delayed_11; +reg [`DWIDTH-1:0] a15_data_delayed_12; +reg [`DWIDTH-1:0] a15_data_delayed_13; +reg [`DWIDTH-1:0] a15_data_delayed_14; +reg [`DWIDTH-1:0] a15_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_1; +reg [`DWIDTH-1:0] a16_data_delayed_2; +reg [`DWIDTH-1:0] a16_data_delayed_3; +reg [`DWIDTH-1:0] a16_data_delayed_4; +reg [`DWIDTH-1:0] a16_data_delayed_5; +reg [`DWIDTH-1:0] a16_data_delayed_6; +reg [`DWIDTH-1:0] a16_data_delayed_7; +reg [`DWIDTH-1:0] a16_data_delayed_8; +reg [`DWIDTH-1:0] a16_data_delayed_9; +reg [`DWIDTH-1:0] a16_data_delayed_10; +reg [`DWIDTH-1:0] a16_data_delayed_11; +reg [`DWIDTH-1:0] a16_data_delayed_12; +reg [`DWIDTH-1:0] a16_data_delayed_13; +reg [`DWIDTH-1:0] a16_data_delayed_14; +reg [`DWIDTH-1:0] a16_data_delayed_15; +reg [`DWIDTH-1:0] a16_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_1; +reg [`DWIDTH-1:0] a17_data_delayed_2; +reg [`DWIDTH-1:0] a17_data_delayed_3; +reg [`DWIDTH-1:0] a17_data_delayed_4; +reg [`DWIDTH-1:0] a17_data_delayed_5; +reg [`DWIDTH-1:0] a17_data_delayed_6; +reg [`DWIDTH-1:0] a17_data_delayed_7; +reg [`DWIDTH-1:0] a17_data_delayed_8; +reg [`DWIDTH-1:0] a17_data_delayed_9; +reg [`DWIDTH-1:0] a17_data_delayed_10; +reg [`DWIDTH-1:0] a17_data_delayed_11; +reg [`DWIDTH-1:0] a17_data_delayed_12; +reg [`DWIDTH-1:0] a17_data_delayed_13; +reg [`DWIDTH-1:0] a17_data_delayed_14; +reg [`DWIDTH-1:0] a17_data_delayed_15; +reg [`DWIDTH-1:0] a17_data_delayed_16; +reg [`DWIDTH-1:0] a17_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_1; +reg [`DWIDTH-1:0] a18_data_delayed_2; +reg [`DWIDTH-1:0] a18_data_delayed_3; +reg [`DWIDTH-1:0] a18_data_delayed_4; +reg [`DWIDTH-1:0] a18_data_delayed_5; +reg [`DWIDTH-1:0] a18_data_delayed_6; +reg [`DWIDTH-1:0] a18_data_delayed_7; +reg [`DWIDTH-1:0] a18_data_delayed_8; +reg [`DWIDTH-1:0] a18_data_delayed_9; +reg [`DWIDTH-1:0] a18_data_delayed_10; +reg [`DWIDTH-1:0] a18_data_delayed_11; +reg [`DWIDTH-1:0] a18_data_delayed_12; +reg [`DWIDTH-1:0] a18_data_delayed_13; +reg [`DWIDTH-1:0] a18_data_delayed_14; +reg [`DWIDTH-1:0] a18_data_delayed_15; +reg [`DWIDTH-1:0] a18_data_delayed_16; +reg [`DWIDTH-1:0] a18_data_delayed_17; +reg [`DWIDTH-1:0] a18_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_1; +reg [`DWIDTH-1:0] a19_data_delayed_2; +reg [`DWIDTH-1:0] a19_data_delayed_3; +reg [`DWIDTH-1:0] a19_data_delayed_4; +reg [`DWIDTH-1:0] a19_data_delayed_5; +reg [`DWIDTH-1:0] a19_data_delayed_6; +reg [`DWIDTH-1:0] a19_data_delayed_7; +reg [`DWIDTH-1:0] a19_data_delayed_8; +reg [`DWIDTH-1:0] a19_data_delayed_9; +reg [`DWIDTH-1:0] a19_data_delayed_10; +reg [`DWIDTH-1:0] a19_data_delayed_11; +reg [`DWIDTH-1:0] a19_data_delayed_12; +reg [`DWIDTH-1:0] a19_data_delayed_13; +reg [`DWIDTH-1:0] a19_data_delayed_14; +reg [`DWIDTH-1:0] a19_data_delayed_15; +reg [`DWIDTH-1:0] a19_data_delayed_16; +reg [`DWIDTH-1:0] a19_data_delayed_17; +reg [`DWIDTH-1:0] a19_data_delayed_18; +reg [`DWIDTH-1:0] a19_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_1; +reg [`DWIDTH-1:0] a20_data_delayed_2; +reg [`DWIDTH-1:0] a20_data_delayed_3; +reg [`DWIDTH-1:0] a20_data_delayed_4; +reg [`DWIDTH-1:0] a20_data_delayed_5; +reg [`DWIDTH-1:0] a20_data_delayed_6; +reg [`DWIDTH-1:0] a20_data_delayed_7; +reg [`DWIDTH-1:0] a20_data_delayed_8; +reg [`DWIDTH-1:0] a20_data_delayed_9; +reg [`DWIDTH-1:0] a20_data_delayed_10; +reg [`DWIDTH-1:0] a20_data_delayed_11; +reg [`DWIDTH-1:0] a20_data_delayed_12; +reg [`DWIDTH-1:0] a20_data_delayed_13; +reg [`DWIDTH-1:0] a20_data_delayed_14; +reg [`DWIDTH-1:0] a20_data_delayed_15; +reg [`DWIDTH-1:0] a20_data_delayed_16; +reg [`DWIDTH-1:0] a20_data_delayed_17; +reg [`DWIDTH-1:0] a20_data_delayed_18; +reg [`DWIDTH-1:0] a20_data_delayed_19; +reg [`DWIDTH-1:0] a20_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_1; +reg [`DWIDTH-1:0] a21_data_delayed_2; +reg [`DWIDTH-1:0] a21_data_delayed_3; +reg [`DWIDTH-1:0] a21_data_delayed_4; +reg [`DWIDTH-1:0] a21_data_delayed_5; +reg [`DWIDTH-1:0] a21_data_delayed_6; +reg [`DWIDTH-1:0] a21_data_delayed_7; +reg [`DWIDTH-1:0] a21_data_delayed_8; +reg [`DWIDTH-1:0] a21_data_delayed_9; +reg [`DWIDTH-1:0] a21_data_delayed_10; +reg [`DWIDTH-1:0] a21_data_delayed_11; +reg [`DWIDTH-1:0] a21_data_delayed_12; +reg [`DWIDTH-1:0] a21_data_delayed_13; +reg [`DWIDTH-1:0] a21_data_delayed_14; +reg [`DWIDTH-1:0] a21_data_delayed_15; +reg [`DWIDTH-1:0] a21_data_delayed_16; +reg [`DWIDTH-1:0] a21_data_delayed_17; +reg [`DWIDTH-1:0] a21_data_delayed_18; +reg [`DWIDTH-1:0] a21_data_delayed_19; +reg [`DWIDTH-1:0] a21_data_delayed_20; +reg [`DWIDTH-1:0] a21_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_1; +reg [`DWIDTH-1:0] a22_data_delayed_2; +reg [`DWIDTH-1:0] a22_data_delayed_3; +reg [`DWIDTH-1:0] a22_data_delayed_4; +reg [`DWIDTH-1:0] a22_data_delayed_5; +reg [`DWIDTH-1:0] a22_data_delayed_6; +reg [`DWIDTH-1:0] a22_data_delayed_7; +reg [`DWIDTH-1:0] a22_data_delayed_8; +reg [`DWIDTH-1:0] a22_data_delayed_9; +reg [`DWIDTH-1:0] a22_data_delayed_10; +reg [`DWIDTH-1:0] a22_data_delayed_11; +reg [`DWIDTH-1:0] a22_data_delayed_12; +reg [`DWIDTH-1:0] a22_data_delayed_13; +reg [`DWIDTH-1:0] a22_data_delayed_14; +reg [`DWIDTH-1:0] a22_data_delayed_15; +reg [`DWIDTH-1:0] a22_data_delayed_16; +reg [`DWIDTH-1:0] a22_data_delayed_17; +reg [`DWIDTH-1:0] a22_data_delayed_18; +reg [`DWIDTH-1:0] a22_data_delayed_19; +reg [`DWIDTH-1:0] a22_data_delayed_20; +reg [`DWIDTH-1:0] a22_data_delayed_21; +reg [`DWIDTH-1:0] a22_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_1; +reg [`DWIDTH-1:0] a23_data_delayed_2; +reg [`DWIDTH-1:0] a23_data_delayed_3; +reg [`DWIDTH-1:0] a23_data_delayed_4; +reg [`DWIDTH-1:0] a23_data_delayed_5; +reg [`DWIDTH-1:0] a23_data_delayed_6; +reg [`DWIDTH-1:0] a23_data_delayed_7; +reg [`DWIDTH-1:0] a23_data_delayed_8; +reg [`DWIDTH-1:0] a23_data_delayed_9; +reg [`DWIDTH-1:0] a23_data_delayed_10; +reg [`DWIDTH-1:0] a23_data_delayed_11; +reg [`DWIDTH-1:0] a23_data_delayed_12; +reg [`DWIDTH-1:0] a23_data_delayed_13; +reg [`DWIDTH-1:0] a23_data_delayed_14; +reg [`DWIDTH-1:0] a23_data_delayed_15; +reg [`DWIDTH-1:0] a23_data_delayed_16; +reg [`DWIDTH-1:0] a23_data_delayed_17; +reg [`DWIDTH-1:0] a23_data_delayed_18; +reg [`DWIDTH-1:0] a23_data_delayed_19; +reg [`DWIDTH-1:0] a23_data_delayed_20; +reg [`DWIDTH-1:0] a23_data_delayed_21; +reg [`DWIDTH-1:0] a23_data_delayed_22; +reg [`DWIDTH-1:0] a23_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_1; +reg [`DWIDTH-1:0] a24_data_delayed_2; +reg [`DWIDTH-1:0] a24_data_delayed_3; +reg [`DWIDTH-1:0] a24_data_delayed_4; +reg [`DWIDTH-1:0] a24_data_delayed_5; +reg [`DWIDTH-1:0] a24_data_delayed_6; +reg [`DWIDTH-1:0] a24_data_delayed_7; +reg [`DWIDTH-1:0] a24_data_delayed_8; +reg [`DWIDTH-1:0] a24_data_delayed_9; +reg [`DWIDTH-1:0] a24_data_delayed_10; +reg [`DWIDTH-1:0] a24_data_delayed_11; +reg [`DWIDTH-1:0] a24_data_delayed_12; +reg [`DWIDTH-1:0] a24_data_delayed_13; +reg [`DWIDTH-1:0] a24_data_delayed_14; +reg [`DWIDTH-1:0] a24_data_delayed_15; +reg [`DWIDTH-1:0] a24_data_delayed_16; +reg [`DWIDTH-1:0] a24_data_delayed_17; +reg [`DWIDTH-1:0] a24_data_delayed_18; +reg [`DWIDTH-1:0] a24_data_delayed_19; +reg [`DWIDTH-1:0] a24_data_delayed_20; +reg [`DWIDTH-1:0] a24_data_delayed_21; +reg [`DWIDTH-1:0] a24_data_delayed_22; +reg [`DWIDTH-1:0] a24_data_delayed_23; +reg [`DWIDTH-1:0] a24_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_1; +reg [`DWIDTH-1:0] a25_data_delayed_2; +reg [`DWIDTH-1:0] a25_data_delayed_3; +reg [`DWIDTH-1:0] a25_data_delayed_4; +reg [`DWIDTH-1:0] a25_data_delayed_5; +reg [`DWIDTH-1:0] a25_data_delayed_6; +reg [`DWIDTH-1:0] a25_data_delayed_7; +reg [`DWIDTH-1:0] a25_data_delayed_8; +reg [`DWIDTH-1:0] a25_data_delayed_9; +reg [`DWIDTH-1:0] a25_data_delayed_10; +reg [`DWIDTH-1:0] a25_data_delayed_11; +reg [`DWIDTH-1:0] a25_data_delayed_12; +reg [`DWIDTH-1:0] a25_data_delayed_13; +reg [`DWIDTH-1:0] a25_data_delayed_14; +reg [`DWIDTH-1:0] a25_data_delayed_15; +reg [`DWIDTH-1:0] a25_data_delayed_16; +reg [`DWIDTH-1:0] a25_data_delayed_17; +reg [`DWIDTH-1:0] a25_data_delayed_18; +reg [`DWIDTH-1:0] a25_data_delayed_19; +reg [`DWIDTH-1:0] a25_data_delayed_20; +reg [`DWIDTH-1:0] a25_data_delayed_21; +reg [`DWIDTH-1:0] a25_data_delayed_22; +reg [`DWIDTH-1:0] a25_data_delayed_23; +reg [`DWIDTH-1:0] a25_data_delayed_24; +reg [`DWIDTH-1:0] a25_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_1; +reg [`DWIDTH-1:0] a26_data_delayed_2; +reg [`DWIDTH-1:0] a26_data_delayed_3; +reg [`DWIDTH-1:0] a26_data_delayed_4; +reg [`DWIDTH-1:0] a26_data_delayed_5; +reg [`DWIDTH-1:0] a26_data_delayed_6; +reg [`DWIDTH-1:0] a26_data_delayed_7; +reg [`DWIDTH-1:0] a26_data_delayed_8; +reg [`DWIDTH-1:0] a26_data_delayed_9; +reg [`DWIDTH-1:0] a26_data_delayed_10; +reg [`DWIDTH-1:0] a26_data_delayed_11; +reg [`DWIDTH-1:0] a26_data_delayed_12; +reg [`DWIDTH-1:0] a26_data_delayed_13; +reg [`DWIDTH-1:0] a26_data_delayed_14; +reg [`DWIDTH-1:0] a26_data_delayed_15; +reg [`DWIDTH-1:0] a26_data_delayed_16; +reg [`DWIDTH-1:0] a26_data_delayed_17; +reg [`DWIDTH-1:0] a26_data_delayed_18; +reg [`DWIDTH-1:0] a26_data_delayed_19; +reg [`DWIDTH-1:0] a26_data_delayed_20; +reg [`DWIDTH-1:0] a26_data_delayed_21; +reg [`DWIDTH-1:0] a26_data_delayed_22; +reg [`DWIDTH-1:0] a26_data_delayed_23; +reg [`DWIDTH-1:0] a26_data_delayed_24; +reg [`DWIDTH-1:0] a26_data_delayed_25; +reg [`DWIDTH-1:0] a26_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_1; +reg [`DWIDTH-1:0] a27_data_delayed_2; +reg [`DWIDTH-1:0] a27_data_delayed_3; +reg [`DWIDTH-1:0] a27_data_delayed_4; +reg [`DWIDTH-1:0] a27_data_delayed_5; +reg [`DWIDTH-1:0] a27_data_delayed_6; +reg [`DWIDTH-1:0] a27_data_delayed_7; +reg [`DWIDTH-1:0] a27_data_delayed_8; +reg [`DWIDTH-1:0] a27_data_delayed_9; +reg [`DWIDTH-1:0] a27_data_delayed_10; +reg [`DWIDTH-1:0] a27_data_delayed_11; +reg [`DWIDTH-1:0] a27_data_delayed_12; +reg [`DWIDTH-1:0] a27_data_delayed_13; +reg [`DWIDTH-1:0] a27_data_delayed_14; +reg [`DWIDTH-1:0] a27_data_delayed_15; +reg [`DWIDTH-1:0] a27_data_delayed_16; +reg [`DWIDTH-1:0] a27_data_delayed_17; +reg [`DWIDTH-1:0] a27_data_delayed_18; +reg [`DWIDTH-1:0] a27_data_delayed_19; +reg [`DWIDTH-1:0] a27_data_delayed_20; +reg [`DWIDTH-1:0] a27_data_delayed_21; +reg [`DWIDTH-1:0] a27_data_delayed_22; +reg [`DWIDTH-1:0] a27_data_delayed_23; +reg [`DWIDTH-1:0] a27_data_delayed_24; +reg [`DWIDTH-1:0] a27_data_delayed_25; +reg [`DWIDTH-1:0] a27_data_delayed_26; +reg [`DWIDTH-1:0] a27_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_1; +reg [`DWIDTH-1:0] a28_data_delayed_2; +reg [`DWIDTH-1:0] a28_data_delayed_3; +reg [`DWIDTH-1:0] a28_data_delayed_4; +reg [`DWIDTH-1:0] a28_data_delayed_5; +reg [`DWIDTH-1:0] a28_data_delayed_6; +reg [`DWIDTH-1:0] a28_data_delayed_7; +reg [`DWIDTH-1:0] a28_data_delayed_8; +reg [`DWIDTH-1:0] a28_data_delayed_9; +reg [`DWIDTH-1:0] a28_data_delayed_10; +reg [`DWIDTH-1:0] a28_data_delayed_11; +reg [`DWIDTH-1:0] a28_data_delayed_12; +reg [`DWIDTH-1:0] a28_data_delayed_13; +reg [`DWIDTH-1:0] a28_data_delayed_14; +reg [`DWIDTH-1:0] a28_data_delayed_15; +reg [`DWIDTH-1:0] a28_data_delayed_16; +reg [`DWIDTH-1:0] a28_data_delayed_17; +reg [`DWIDTH-1:0] a28_data_delayed_18; +reg [`DWIDTH-1:0] a28_data_delayed_19; +reg [`DWIDTH-1:0] a28_data_delayed_20; +reg [`DWIDTH-1:0] a28_data_delayed_21; +reg [`DWIDTH-1:0] a28_data_delayed_22; +reg [`DWIDTH-1:0] a28_data_delayed_23; +reg [`DWIDTH-1:0] a28_data_delayed_24; +reg [`DWIDTH-1:0] a28_data_delayed_25; +reg [`DWIDTH-1:0] a28_data_delayed_26; +reg [`DWIDTH-1:0] a28_data_delayed_27; +reg [`DWIDTH-1:0] a28_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_1; +reg [`DWIDTH-1:0] a29_data_delayed_2; +reg [`DWIDTH-1:0] a29_data_delayed_3; +reg [`DWIDTH-1:0] a29_data_delayed_4; +reg [`DWIDTH-1:0] a29_data_delayed_5; +reg [`DWIDTH-1:0] a29_data_delayed_6; +reg [`DWIDTH-1:0] a29_data_delayed_7; +reg [`DWIDTH-1:0] a29_data_delayed_8; +reg [`DWIDTH-1:0] a29_data_delayed_9; +reg [`DWIDTH-1:0] a29_data_delayed_10; +reg [`DWIDTH-1:0] a29_data_delayed_11; +reg [`DWIDTH-1:0] a29_data_delayed_12; +reg [`DWIDTH-1:0] a29_data_delayed_13; +reg [`DWIDTH-1:0] a29_data_delayed_14; +reg [`DWIDTH-1:0] a29_data_delayed_15; +reg [`DWIDTH-1:0] a29_data_delayed_16; +reg [`DWIDTH-1:0] a29_data_delayed_17; +reg [`DWIDTH-1:0] a29_data_delayed_18; +reg [`DWIDTH-1:0] a29_data_delayed_19; +reg [`DWIDTH-1:0] a29_data_delayed_20; +reg [`DWIDTH-1:0] a29_data_delayed_21; +reg [`DWIDTH-1:0] a29_data_delayed_22; +reg [`DWIDTH-1:0] a29_data_delayed_23; +reg [`DWIDTH-1:0] a29_data_delayed_24; +reg [`DWIDTH-1:0] a29_data_delayed_25; +reg [`DWIDTH-1:0] a29_data_delayed_26; +reg [`DWIDTH-1:0] a29_data_delayed_27; +reg [`DWIDTH-1:0] a29_data_delayed_28; +reg [`DWIDTH-1:0] a29_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_1; +reg [`DWIDTH-1:0] a30_data_delayed_2; +reg [`DWIDTH-1:0] a30_data_delayed_3; +reg [`DWIDTH-1:0] a30_data_delayed_4; +reg [`DWIDTH-1:0] a30_data_delayed_5; +reg [`DWIDTH-1:0] a30_data_delayed_6; +reg [`DWIDTH-1:0] a30_data_delayed_7; +reg [`DWIDTH-1:0] a30_data_delayed_8; +reg [`DWIDTH-1:0] a30_data_delayed_9; +reg [`DWIDTH-1:0] a30_data_delayed_10; +reg [`DWIDTH-1:0] a30_data_delayed_11; +reg [`DWIDTH-1:0] a30_data_delayed_12; +reg [`DWIDTH-1:0] a30_data_delayed_13; +reg [`DWIDTH-1:0] a30_data_delayed_14; +reg [`DWIDTH-1:0] a30_data_delayed_15; +reg [`DWIDTH-1:0] a30_data_delayed_16; +reg [`DWIDTH-1:0] a30_data_delayed_17; +reg [`DWIDTH-1:0] a30_data_delayed_18; +reg [`DWIDTH-1:0] a30_data_delayed_19; +reg [`DWIDTH-1:0] a30_data_delayed_20; +reg [`DWIDTH-1:0] a30_data_delayed_21; +reg [`DWIDTH-1:0] a30_data_delayed_22; +reg [`DWIDTH-1:0] a30_data_delayed_23; +reg [`DWIDTH-1:0] a30_data_delayed_24; +reg [`DWIDTH-1:0] a30_data_delayed_25; +reg [`DWIDTH-1:0] a30_data_delayed_26; +reg [`DWIDTH-1:0] a30_data_delayed_27; +reg [`DWIDTH-1:0] a30_data_delayed_28; +reg [`DWIDTH-1:0] a30_data_delayed_29; +reg [`DWIDTH-1:0] a30_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_1; +reg [`DWIDTH-1:0] a31_data_delayed_2; +reg [`DWIDTH-1:0] a31_data_delayed_3; +reg [`DWIDTH-1:0] a31_data_delayed_4; +reg [`DWIDTH-1:0] a31_data_delayed_5; +reg [`DWIDTH-1:0] a31_data_delayed_6; +reg [`DWIDTH-1:0] a31_data_delayed_7; +reg [`DWIDTH-1:0] a31_data_delayed_8; +reg [`DWIDTH-1:0] a31_data_delayed_9; +reg [`DWIDTH-1:0] a31_data_delayed_10; +reg [`DWIDTH-1:0] a31_data_delayed_11; +reg [`DWIDTH-1:0] a31_data_delayed_12; +reg [`DWIDTH-1:0] a31_data_delayed_13; +reg [`DWIDTH-1:0] a31_data_delayed_14; +reg [`DWIDTH-1:0] a31_data_delayed_15; +reg [`DWIDTH-1:0] a31_data_delayed_16; +reg [`DWIDTH-1:0] a31_data_delayed_17; +reg [`DWIDTH-1:0] a31_data_delayed_18; +reg [`DWIDTH-1:0] a31_data_delayed_19; +reg [`DWIDTH-1:0] a31_data_delayed_20; +reg [`DWIDTH-1:0] a31_data_delayed_21; +reg [`DWIDTH-1:0] a31_data_delayed_22; +reg [`DWIDTH-1:0] a31_data_delayed_23; +reg [`DWIDTH-1:0] a31_data_delayed_24; +reg [`DWIDTH-1:0] a31_data_delayed_25; +reg [`DWIDTH-1:0] a31_data_delayed_26; +reg [`DWIDTH-1:0] a31_data_delayed_27; +reg [`DWIDTH-1:0] a31_data_delayed_28; +reg [`DWIDTH-1:0] a31_data_delayed_29; +reg [`DWIDTH-1:0] a31_data_delayed_30; +reg [`DWIDTH-1:0] a31_data_delayed_31; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + a1_data_delayed_1 <= 0; + a2_data_delayed_1 <= 0; + a2_data_delayed_2 <= 0; + a3_data_delayed_1 <= 0; + a3_data_delayed_2 <= 0; + a3_data_delayed_3 <= 0; + a4_data_delayed_1 <= 0; + a4_data_delayed_2 <= 0; + a4_data_delayed_3 <= 0; + a4_data_delayed_4 <= 0; + a5_data_delayed_1 <= 0; + a5_data_delayed_2 <= 0; + a5_data_delayed_3 <= 0; + a5_data_delayed_4 <= 0; + a5_data_delayed_5 <= 0; + a6_data_delayed_1 <= 0; + a6_data_delayed_2 <= 0; + a6_data_delayed_3 <= 0; + a6_data_delayed_4 <= 0; + a6_data_delayed_5 <= 0; + a6_data_delayed_6 <= 0; + a7_data_delayed_1 <= 0; + a7_data_delayed_2 <= 0; + a7_data_delayed_3 <= 0; + a7_data_delayed_4 <= 0; + a7_data_delayed_5 <= 0; + a7_data_delayed_6 <= 0; + a7_data_delayed_7 <= 0; + a8_data_delayed_1 <= 0; + a8_data_delayed_2 <= 0; + a8_data_delayed_3 <= 0; + a8_data_delayed_4 <= 0; + a8_data_delayed_5 <= 0; + a8_data_delayed_6 <= 0; + a8_data_delayed_7 <= 0; + a8_data_delayed_8 <= 0; + a9_data_delayed_1 <= 0; + a9_data_delayed_2 <= 0; + a9_data_delayed_3 <= 0; + a9_data_delayed_4 <= 0; + a9_data_delayed_5 <= 0; + a9_data_delayed_6 <= 0; + a9_data_delayed_7 <= 0; + a9_data_delayed_8 <= 0; + a9_data_delayed_9 <= 0; + a10_data_delayed_1 <= 0; + a10_data_delayed_2 <= 0; + a10_data_delayed_3 <= 0; + a10_data_delayed_4 <= 0; + a10_data_delayed_5 <= 0; + a10_data_delayed_6 <= 0; + a10_data_delayed_7 <= 0; + a10_data_delayed_8 <= 0; + a10_data_delayed_9 <= 0; + a10_data_delayed_10 <= 0; + a11_data_delayed_1 <= 0; + a11_data_delayed_2 <= 0; + a11_data_delayed_3 <= 0; + a11_data_delayed_4 <= 0; + a11_data_delayed_5 <= 0; + a11_data_delayed_6 <= 0; + a11_data_delayed_7 <= 0; + a11_data_delayed_8 <= 0; + a11_data_delayed_9 <= 0; + a11_data_delayed_10 <= 0; + a11_data_delayed_11 <= 0; + a12_data_delayed_1 <= 0; + a12_data_delayed_2 <= 0; + a12_data_delayed_3 <= 0; + a12_data_delayed_4 <= 0; + a12_data_delayed_5 <= 0; + a12_data_delayed_6 <= 0; + a12_data_delayed_7 <= 0; + a12_data_delayed_8 <= 0; + a12_data_delayed_9 <= 0; + a12_data_delayed_10 <= 0; + a12_data_delayed_11 <= 0; + a12_data_delayed_12 <= 0; + a13_data_delayed_1 <= 0; + a13_data_delayed_2 <= 0; + a13_data_delayed_3 <= 0; + a13_data_delayed_4 <= 0; + a13_data_delayed_5 <= 0; + a13_data_delayed_6 <= 0; + a13_data_delayed_7 <= 0; + a13_data_delayed_8 <= 0; + a13_data_delayed_9 <= 0; + a13_data_delayed_10 <= 0; + a13_data_delayed_11 <= 0; + a13_data_delayed_12 <= 0; + a13_data_delayed_13 <= 0; + a14_data_delayed_1 <= 0; + a14_data_delayed_2 <= 0; + a14_data_delayed_3 <= 0; + a14_data_delayed_4 <= 0; + a14_data_delayed_5 <= 0; + a14_data_delayed_6 <= 0; + a14_data_delayed_7 <= 0; + a14_data_delayed_8 <= 0; + a14_data_delayed_9 <= 0; + a14_data_delayed_10 <= 0; + a14_data_delayed_11 <= 0; + a14_data_delayed_12 <= 0; + a14_data_delayed_13 <= 0; + a14_data_delayed_14 <= 0; + a15_data_delayed_1 <= 0; + a15_data_delayed_2 <= 0; + a15_data_delayed_3 <= 0; + a15_data_delayed_4 <= 0; + a15_data_delayed_5 <= 0; + a15_data_delayed_6 <= 0; + a15_data_delayed_7 <= 0; + a15_data_delayed_8 <= 0; + a15_data_delayed_9 <= 0; + a15_data_delayed_10 <= 0; + a15_data_delayed_11 <= 0; + a15_data_delayed_12 <= 0; + a15_data_delayed_13 <= 0; + a15_data_delayed_14 <= 0; + a15_data_delayed_15 <= 0; + a16_data_delayed_1 <= 0; + a16_data_delayed_2 <= 0; + a16_data_delayed_3 <= 0; + a16_data_delayed_4 <= 0; + a16_data_delayed_5 <= 0; + a16_data_delayed_6 <= 0; + a16_data_delayed_7 <= 0; + a16_data_delayed_8 <= 0; + a16_data_delayed_9 <= 0; + a16_data_delayed_10 <= 0; + a16_data_delayed_11 <= 0; + a16_data_delayed_12 <= 0; + a16_data_delayed_13 <= 0; + a16_data_delayed_14 <= 0; + a16_data_delayed_15 <= 0; + a16_data_delayed_16 <= 0; + a17_data_delayed_1 <= 0; + a17_data_delayed_2 <= 0; + a17_data_delayed_3 <= 0; + a17_data_delayed_4 <= 0; + a17_data_delayed_5 <= 0; + a17_data_delayed_6 <= 0; + a17_data_delayed_7 <= 0; + a17_data_delayed_8 <= 0; + a17_data_delayed_9 <= 0; + a17_data_delayed_10 <= 0; + a17_data_delayed_11 <= 0; + a17_data_delayed_12 <= 0; + a17_data_delayed_13 <= 0; + a17_data_delayed_14 <= 0; + a17_data_delayed_15 <= 0; + a17_data_delayed_16 <= 0; + a17_data_delayed_17 <= 0; + a18_data_delayed_1 <= 0; + a18_data_delayed_2 <= 0; + a18_data_delayed_3 <= 0; + a18_data_delayed_4 <= 0; + a18_data_delayed_5 <= 0; + a18_data_delayed_6 <= 0; + a18_data_delayed_7 <= 0; + a18_data_delayed_8 <= 0; + a18_data_delayed_9 <= 0; + a18_data_delayed_10 <= 0; + a18_data_delayed_11 <= 0; + a18_data_delayed_12 <= 0; + a18_data_delayed_13 <= 0; + a18_data_delayed_14 <= 0; + a18_data_delayed_15 <= 0; + a18_data_delayed_16 <= 0; + a18_data_delayed_17 <= 0; + a18_data_delayed_18 <= 0; + a19_data_delayed_1 <= 0; + a19_data_delayed_2 <= 0; + a19_data_delayed_3 <= 0; + a19_data_delayed_4 <= 0; + a19_data_delayed_5 <= 0; + a19_data_delayed_6 <= 0; + a19_data_delayed_7 <= 0; + a19_data_delayed_8 <= 0; + a19_data_delayed_9 <= 0; + a19_data_delayed_10 <= 0; + a19_data_delayed_11 <= 0; + a19_data_delayed_12 <= 0; + a19_data_delayed_13 <= 0; + a19_data_delayed_14 <= 0; + a19_data_delayed_15 <= 0; + a19_data_delayed_16 <= 0; + a19_data_delayed_17 <= 0; + a19_data_delayed_18 <= 0; + a19_data_delayed_19 <= 0; + a20_data_delayed_1 <= 0; + a20_data_delayed_2 <= 0; + a20_data_delayed_3 <= 0; + a20_data_delayed_4 <= 0; + a20_data_delayed_5 <= 0; + a20_data_delayed_6 <= 0; + a20_data_delayed_7 <= 0; + a20_data_delayed_8 <= 0; + a20_data_delayed_9 <= 0; + a20_data_delayed_10 <= 0; + a20_data_delayed_11 <= 0; + a20_data_delayed_12 <= 0; + a20_data_delayed_13 <= 0; + a20_data_delayed_14 <= 0; + a20_data_delayed_15 <= 0; + a20_data_delayed_16 <= 0; + a20_data_delayed_17 <= 0; + a20_data_delayed_18 <= 0; + a20_data_delayed_19 <= 0; + a20_data_delayed_20 <= 0; + a21_data_delayed_1 <= 0; + a21_data_delayed_2 <= 0; + a21_data_delayed_3 <= 0; + a21_data_delayed_4 <= 0; + a21_data_delayed_5 <= 0; + a21_data_delayed_6 <= 0; + a21_data_delayed_7 <= 0; + a21_data_delayed_8 <= 0; + a21_data_delayed_9 <= 0; + a21_data_delayed_10 <= 0; + a21_data_delayed_11 <= 0; + a21_data_delayed_12 <= 0; + a21_data_delayed_13 <= 0; + a21_data_delayed_14 <= 0; + a21_data_delayed_15 <= 0; + a21_data_delayed_16 <= 0; + a21_data_delayed_17 <= 0; + a21_data_delayed_18 <= 0; + a21_data_delayed_19 <= 0; + a21_data_delayed_20 <= 0; + a21_data_delayed_21 <= 0; + a22_data_delayed_1 <= 0; + a22_data_delayed_2 <= 0; + a22_data_delayed_3 <= 0; + a22_data_delayed_4 <= 0; + a22_data_delayed_5 <= 0; + a22_data_delayed_6 <= 0; + a22_data_delayed_7 <= 0; + a22_data_delayed_8 <= 0; + a22_data_delayed_9 <= 0; + a22_data_delayed_10 <= 0; + a22_data_delayed_11 <= 0; + a22_data_delayed_12 <= 0; + a22_data_delayed_13 <= 0; + a22_data_delayed_14 <= 0; + a22_data_delayed_15 <= 0; + a22_data_delayed_16 <= 0; + a22_data_delayed_17 <= 0; + a22_data_delayed_18 <= 0; + a22_data_delayed_19 <= 0; + a22_data_delayed_20 <= 0; + a22_data_delayed_21 <= 0; + a22_data_delayed_22 <= 0; + a23_data_delayed_1 <= 0; + a23_data_delayed_2 <= 0; + a23_data_delayed_3 <= 0; + a23_data_delayed_4 <= 0; + a23_data_delayed_5 <= 0; + a23_data_delayed_6 <= 0; + a23_data_delayed_7 <= 0; + a23_data_delayed_8 <= 0; + a23_data_delayed_9 <= 0; + a23_data_delayed_10 <= 0; + a23_data_delayed_11 <= 0; + a23_data_delayed_12 <= 0; + a23_data_delayed_13 <= 0; + a23_data_delayed_14 <= 0; + a23_data_delayed_15 <= 0; + a23_data_delayed_16 <= 0; + a23_data_delayed_17 <= 0; + a23_data_delayed_18 <= 0; + a23_data_delayed_19 <= 0; + a23_data_delayed_20 <= 0; + a23_data_delayed_21 <= 0; + a23_data_delayed_22 <= 0; + a23_data_delayed_23 <= 0; + a24_data_delayed_1 <= 0; + a24_data_delayed_2 <= 0; + a24_data_delayed_3 <= 0; + a24_data_delayed_4 <= 0; + a24_data_delayed_5 <= 0; + a24_data_delayed_6 <= 0; + a24_data_delayed_7 <= 0; + a24_data_delayed_8 <= 0; + a24_data_delayed_9 <= 0; + a24_data_delayed_10 <= 0; + a24_data_delayed_11 <= 0; + a24_data_delayed_12 <= 0; + a24_data_delayed_13 <= 0; + a24_data_delayed_14 <= 0; + a24_data_delayed_15 <= 0; + a24_data_delayed_16 <= 0; + a24_data_delayed_17 <= 0; + a24_data_delayed_18 <= 0; + a24_data_delayed_19 <= 0; + a24_data_delayed_20 <= 0; + a24_data_delayed_21 <= 0; + a24_data_delayed_22 <= 0; + a24_data_delayed_23 <= 0; + a24_data_delayed_24 <= 0; + a25_data_delayed_1 <= 0; + a25_data_delayed_2 <= 0; + a25_data_delayed_3 <= 0; + a25_data_delayed_4 <= 0; + a25_data_delayed_5 <= 0; + a25_data_delayed_6 <= 0; + a25_data_delayed_7 <= 0; + a25_data_delayed_8 <= 0; + a25_data_delayed_9 <= 0; + a25_data_delayed_10 <= 0; + a25_data_delayed_11 <= 0; + a25_data_delayed_12 <= 0; + a25_data_delayed_13 <= 0; + a25_data_delayed_14 <= 0; + a25_data_delayed_15 <= 0; + a25_data_delayed_16 <= 0; + a25_data_delayed_17 <= 0; + a25_data_delayed_18 <= 0; + a25_data_delayed_19 <= 0; + a25_data_delayed_20 <= 0; + a25_data_delayed_21 <= 0; + a25_data_delayed_22 <= 0; + a25_data_delayed_23 <= 0; + a25_data_delayed_24 <= 0; + a25_data_delayed_25 <= 0; + a26_data_delayed_1 <= 0; + a26_data_delayed_2 <= 0; + a26_data_delayed_3 <= 0; + a26_data_delayed_4 <= 0; + a26_data_delayed_5 <= 0; + a26_data_delayed_6 <= 0; + a26_data_delayed_7 <= 0; + a26_data_delayed_8 <= 0; + a26_data_delayed_9 <= 0; + a26_data_delayed_10 <= 0; + a26_data_delayed_11 <= 0; + a26_data_delayed_12 <= 0; + a26_data_delayed_13 <= 0; + a26_data_delayed_14 <= 0; + a26_data_delayed_15 <= 0; + a26_data_delayed_16 <= 0; + a26_data_delayed_17 <= 0; + a26_data_delayed_18 <= 0; + a26_data_delayed_19 <= 0; + a26_data_delayed_20 <= 0; + a26_data_delayed_21 <= 0; + a26_data_delayed_22 <= 0; + a26_data_delayed_23 <= 0; + a26_data_delayed_24 <= 0; + a26_data_delayed_25 <= 0; + a26_data_delayed_26 <= 0; + a27_data_delayed_1 <= 0; + a27_data_delayed_2 <= 0; + a27_data_delayed_3 <= 0; + a27_data_delayed_4 <= 0; + a27_data_delayed_5 <= 0; + a27_data_delayed_6 <= 0; + a27_data_delayed_7 <= 0; + a27_data_delayed_8 <= 0; + a27_data_delayed_9 <= 0; + a27_data_delayed_10 <= 0; + a27_data_delayed_11 <= 0; + a27_data_delayed_12 <= 0; + a27_data_delayed_13 <= 0; + a27_data_delayed_14 <= 0; + a27_data_delayed_15 <= 0; + a27_data_delayed_16 <= 0; + a27_data_delayed_17 <= 0; + a27_data_delayed_18 <= 0; + a27_data_delayed_19 <= 0; + a27_data_delayed_20 <= 0; + a27_data_delayed_21 <= 0; + a27_data_delayed_22 <= 0; + a27_data_delayed_23 <= 0; + a27_data_delayed_24 <= 0; + a27_data_delayed_25 <= 0; + a27_data_delayed_26 <= 0; + a27_data_delayed_27 <= 0; + a28_data_delayed_1 <= 0; + a28_data_delayed_2 <= 0; + a28_data_delayed_3 <= 0; + a28_data_delayed_4 <= 0; + a28_data_delayed_5 <= 0; + a28_data_delayed_6 <= 0; + a28_data_delayed_7 <= 0; + a28_data_delayed_8 <= 0; + a28_data_delayed_9 <= 0; + a28_data_delayed_10 <= 0; + a28_data_delayed_11 <= 0; + a28_data_delayed_12 <= 0; + a28_data_delayed_13 <= 0; + a28_data_delayed_14 <= 0; + a28_data_delayed_15 <= 0; + a28_data_delayed_16 <= 0; + a28_data_delayed_17 <= 0; + a28_data_delayed_18 <= 0; + a28_data_delayed_19 <= 0; + a28_data_delayed_20 <= 0; + a28_data_delayed_21 <= 0; + a28_data_delayed_22 <= 0; + a28_data_delayed_23 <= 0; + a28_data_delayed_24 <= 0; + a28_data_delayed_25 <= 0; + a28_data_delayed_26 <= 0; + a28_data_delayed_27 <= 0; + a28_data_delayed_28 <= 0; + a29_data_delayed_1 <= 0; + a29_data_delayed_2 <= 0; + a29_data_delayed_3 <= 0; + a29_data_delayed_4 <= 0; + a29_data_delayed_5 <= 0; + a29_data_delayed_6 <= 0; + a29_data_delayed_7 <= 0; + a29_data_delayed_8 <= 0; + a29_data_delayed_9 <= 0; + a29_data_delayed_10 <= 0; + a29_data_delayed_11 <= 0; + a29_data_delayed_12 <= 0; + a29_data_delayed_13 <= 0; + a29_data_delayed_14 <= 0; + a29_data_delayed_15 <= 0; + a29_data_delayed_16 <= 0; + a29_data_delayed_17 <= 0; + a29_data_delayed_18 <= 0; + a29_data_delayed_19 <= 0; + a29_data_delayed_20 <= 0; + a29_data_delayed_21 <= 0; + a29_data_delayed_22 <= 0; + a29_data_delayed_23 <= 0; + a29_data_delayed_24 <= 0; + a29_data_delayed_25 <= 0; + a29_data_delayed_26 <= 0; + a29_data_delayed_27 <= 0; + a29_data_delayed_28 <= 0; + a29_data_delayed_29 <= 0; + a30_data_delayed_1 <= 0; + a30_data_delayed_2 <= 0; + a30_data_delayed_3 <= 0; + a30_data_delayed_4 <= 0; + a30_data_delayed_5 <= 0; + a30_data_delayed_6 <= 0; + a30_data_delayed_7 <= 0; + a30_data_delayed_8 <= 0; + a30_data_delayed_9 <= 0; + a30_data_delayed_10 <= 0; + a30_data_delayed_11 <= 0; + a30_data_delayed_12 <= 0; + a30_data_delayed_13 <= 0; + a30_data_delayed_14 <= 0; + a30_data_delayed_15 <= 0; + a30_data_delayed_16 <= 0; + a30_data_delayed_17 <= 0; + a30_data_delayed_18 <= 0; + a30_data_delayed_19 <= 0; + a30_data_delayed_20 <= 0; + a30_data_delayed_21 <= 0; + a30_data_delayed_22 <= 0; + a30_data_delayed_23 <= 0; + a30_data_delayed_24 <= 0; + a30_data_delayed_25 <= 0; + a30_data_delayed_26 <= 0; + a30_data_delayed_27 <= 0; + a30_data_delayed_28 <= 0; + a30_data_delayed_29 <= 0; + a30_data_delayed_30 <= 0; + a31_data_delayed_1 <= 0; + a31_data_delayed_2 <= 0; + a31_data_delayed_3 <= 0; + a31_data_delayed_4 <= 0; + a31_data_delayed_5 <= 0; + a31_data_delayed_6 <= 0; + a31_data_delayed_7 <= 0; + a31_data_delayed_8 <= 0; + a31_data_delayed_9 <= 0; + a31_data_delayed_10 <= 0; + a31_data_delayed_11 <= 0; + a31_data_delayed_12 <= 0; + a31_data_delayed_13 <= 0; + a31_data_delayed_14 <= 0; + a31_data_delayed_15 <= 0; + a31_data_delayed_16 <= 0; + a31_data_delayed_17 <= 0; + a31_data_delayed_18 <= 0; + a31_data_delayed_19 <= 0; + a31_data_delayed_20 <= 0; + a31_data_delayed_21 <= 0; + a31_data_delayed_22 <= 0; + a31_data_delayed_23 <= 0; + a31_data_delayed_24 <= 0; + a31_data_delayed_25 <= 0; + a31_data_delayed_26 <= 0; + a31_data_delayed_27 <= 0; + a31_data_delayed_28 <= 0; + a31_data_delayed_29 <= 0; + a31_data_delayed_30 <= 0; + a31_data_delayed_31 <= 0; + + end + else begin + a1_data_delayed_1 <= a1_data; + a2_data_delayed_1 <= a2_data; + a3_data_delayed_1 <= a3_data; + a4_data_delayed_1 <= a4_data; + a5_data_delayed_1 <= a5_data; + a6_data_delayed_1 <= a6_data; + a7_data_delayed_1 <= a7_data; + a8_data_delayed_1 <= a8_data; + a9_data_delayed_1 <= a9_data; + a10_data_delayed_1 <= a10_data; + a11_data_delayed_1 <= a11_data; + a12_data_delayed_1 <= a12_data; + a13_data_delayed_1 <= a13_data; + a14_data_delayed_1 <= a14_data; + a15_data_delayed_1 <= a15_data; + a16_data_delayed_1 <= a16_data; + a17_data_delayed_1 <= a17_data; + a18_data_delayed_1 <= a18_data; + a19_data_delayed_1 <= a19_data; + a20_data_delayed_1 <= a20_data; + a21_data_delayed_1 <= a21_data; + a22_data_delayed_1 <= a22_data; + a23_data_delayed_1 <= a23_data; + a24_data_delayed_1 <= a24_data; + a25_data_delayed_1 <= a25_data; + a26_data_delayed_1 <= a26_data; + a27_data_delayed_1 <= a27_data; + a28_data_delayed_1 <= a28_data; + a29_data_delayed_1 <= a29_data; + a30_data_delayed_1 <= a30_data; + a31_data_delayed_1 <= a31_data; + a2_data_delayed_2 <= a2_data_delayed_1; + a3_data_delayed_2 <= a3_data_delayed_1; + a3_data_delayed_3 <= a3_data_delayed_2; + a4_data_delayed_2 <= a4_data_delayed_1; + a4_data_delayed_3 <= a4_data_delayed_2; + a4_data_delayed_4 <= a4_data_delayed_3; + a5_data_delayed_2 <= a5_data_delayed_1; + a5_data_delayed_3 <= a5_data_delayed_2; + a5_data_delayed_4 <= a5_data_delayed_3; + a5_data_delayed_5 <= a5_data_delayed_4; + a6_data_delayed_2 <= a6_data_delayed_1; + a6_data_delayed_3 <= a6_data_delayed_2; + a6_data_delayed_4 <= a6_data_delayed_3; + a6_data_delayed_5 <= a6_data_delayed_4; + a6_data_delayed_6 <= a6_data_delayed_5; + a7_data_delayed_2 <= a7_data_delayed_1; + a7_data_delayed_3 <= a7_data_delayed_2; + a7_data_delayed_4 <= a7_data_delayed_3; + a7_data_delayed_5 <= a7_data_delayed_4; + a7_data_delayed_6 <= a7_data_delayed_5; + a7_data_delayed_7 <= a7_data_delayed_6; + a8_data_delayed_2 <= a8_data_delayed_1; + a8_data_delayed_3 <= a8_data_delayed_2; + a8_data_delayed_4 <= a8_data_delayed_3; + a8_data_delayed_5 <= a8_data_delayed_4; + a8_data_delayed_6 <= a8_data_delayed_5; + a8_data_delayed_7 <= a8_data_delayed_6; + a8_data_delayed_8 <= a8_data_delayed_7; + a9_data_delayed_2 <= a9_data_delayed_1; + a9_data_delayed_3 <= a9_data_delayed_2; + a9_data_delayed_4 <= a9_data_delayed_3; + a9_data_delayed_5 <= a9_data_delayed_4; + a9_data_delayed_6 <= a9_data_delayed_5; + a9_data_delayed_7 <= a9_data_delayed_6; + a9_data_delayed_8 <= a9_data_delayed_7; + a9_data_delayed_9 <= a9_data_delayed_8; + a10_data_delayed_2 <= a10_data_delayed_1; + a10_data_delayed_3 <= a10_data_delayed_2; + a10_data_delayed_4 <= a10_data_delayed_3; + a10_data_delayed_5 <= a10_data_delayed_4; + a10_data_delayed_6 <= a10_data_delayed_5; + a10_data_delayed_7 <= a10_data_delayed_6; + a10_data_delayed_8 <= a10_data_delayed_7; + a10_data_delayed_9 <= a10_data_delayed_8; + a10_data_delayed_10 <= a10_data_delayed_9; + a11_data_delayed_2 <= a11_data_delayed_1; + a11_data_delayed_3 <= a11_data_delayed_2; + a11_data_delayed_4 <= a11_data_delayed_3; + a11_data_delayed_5 <= a11_data_delayed_4; + a11_data_delayed_6 <= a11_data_delayed_5; + a11_data_delayed_7 <= a11_data_delayed_6; + a11_data_delayed_8 <= a11_data_delayed_7; + a11_data_delayed_9 <= a11_data_delayed_8; + a11_data_delayed_10 <= a11_data_delayed_9; + a11_data_delayed_11 <= a11_data_delayed_10; + a12_data_delayed_2 <= a12_data_delayed_1; + a12_data_delayed_3 <= a12_data_delayed_2; + a12_data_delayed_4 <= a12_data_delayed_3; + a12_data_delayed_5 <= a12_data_delayed_4; + a12_data_delayed_6 <= a12_data_delayed_5; + a12_data_delayed_7 <= a12_data_delayed_6; + a12_data_delayed_8 <= a12_data_delayed_7; + a12_data_delayed_9 <= a12_data_delayed_8; + a12_data_delayed_10 <= a12_data_delayed_9; + a12_data_delayed_11 <= a12_data_delayed_10; + a12_data_delayed_12 <= a12_data_delayed_11; + a13_data_delayed_2 <= a13_data_delayed_1; + a13_data_delayed_3 <= a13_data_delayed_2; + a13_data_delayed_4 <= a13_data_delayed_3; + a13_data_delayed_5 <= a13_data_delayed_4; + a13_data_delayed_6 <= a13_data_delayed_5; + a13_data_delayed_7 <= a13_data_delayed_6; + a13_data_delayed_8 <= a13_data_delayed_7; + a13_data_delayed_9 <= a13_data_delayed_8; + a13_data_delayed_10 <= a13_data_delayed_9; + a13_data_delayed_11 <= a13_data_delayed_10; + a13_data_delayed_12 <= a13_data_delayed_11; + a13_data_delayed_13 <= a13_data_delayed_12; + a14_data_delayed_2 <= a14_data_delayed_1; + a14_data_delayed_3 <= a14_data_delayed_2; + a14_data_delayed_4 <= a14_data_delayed_3; + a14_data_delayed_5 <= a14_data_delayed_4; + a14_data_delayed_6 <= a14_data_delayed_5; + a14_data_delayed_7 <= a14_data_delayed_6; + a14_data_delayed_8 <= a14_data_delayed_7; + a14_data_delayed_9 <= a14_data_delayed_8; + a14_data_delayed_10 <= a14_data_delayed_9; + a14_data_delayed_11 <= a14_data_delayed_10; + a14_data_delayed_12 <= a14_data_delayed_11; + a14_data_delayed_13 <= a14_data_delayed_12; + a14_data_delayed_14 <= a14_data_delayed_13; + a15_data_delayed_2 <= a15_data_delayed_1; + a15_data_delayed_3 <= a15_data_delayed_2; + a15_data_delayed_4 <= a15_data_delayed_3; + a15_data_delayed_5 <= a15_data_delayed_4; + a15_data_delayed_6 <= a15_data_delayed_5; + a15_data_delayed_7 <= a15_data_delayed_6; + a15_data_delayed_8 <= a15_data_delayed_7; + a15_data_delayed_9 <= a15_data_delayed_8; + a15_data_delayed_10 <= a15_data_delayed_9; + a15_data_delayed_11 <= a15_data_delayed_10; + a15_data_delayed_12 <= a15_data_delayed_11; + a15_data_delayed_13 <= a15_data_delayed_12; + a15_data_delayed_14 <= a15_data_delayed_13; + a15_data_delayed_15 <= a15_data_delayed_14; + a16_data_delayed_2 <= a16_data_delayed_1; + a16_data_delayed_3 <= a16_data_delayed_2; + a16_data_delayed_4 <= a16_data_delayed_3; + a16_data_delayed_5 <= a16_data_delayed_4; + a16_data_delayed_6 <= a16_data_delayed_5; + a16_data_delayed_7 <= a16_data_delayed_6; + a16_data_delayed_8 <= a16_data_delayed_7; + a16_data_delayed_9 <= a16_data_delayed_8; + a16_data_delayed_10 <= a16_data_delayed_9; + a16_data_delayed_11 <= a16_data_delayed_10; + a16_data_delayed_12 <= a16_data_delayed_11; + a16_data_delayed_13 <= a16_data_delayed_12; + a16_data_delayed_14 <= a16_data_delayed_13; + a16_data_delayed_15 <= a16_data_delayed_14; + a16_data_delayed_16 <= a16_data_delayed_15; + a17_data_delayed_2 <= a17_data_delayed_1; + a17_data_delayed_3 <= a17_data_delayed_2; + a17_data_delayed_4 <= a17_data_delayed_3; + a17_data_delayed_5 <= a17_data_delayed_4; + a17_data_delayed_6 <= a17_data_delayed_5; + a17_data_delayed_7 <= a17_data_delayed_6; + a17_data_delayed_8 <= a17_data_delayed_7; + a17_data_delayed_9 <= a17_data_delayed_8; + a17_data_delayed_10 <= a17_data_delayed_9; + a17_data_delayed_11 <= a17_data_delayed_10; + a17_data_delayed_12 <= a17_data_delayed_11; + a17_data_delayed_13 <= a17_data_delayed_12; + a17_data_delayed_14 <= a17_data_delayed_13; + a17_data_delayed_15 <= a17_data_delayed_14; + a17_data_delayed_16 <= a17_data_delayed_15; + a17_data_delayed_17 <= a17_data_delayed_16; + a18_data_delayed_2 <= a18_data_delayed_1; + a18_data_delayed_3 <= a18_data_delayed_2; + a18_data_delayed_4 <= a18_data_delayed_3; + a18_data_delayed_5 <= a18_data_delayed_4; + a18_data_delayed_6 <= a18_data_delayed_5; + a18_data_delayed_7 <= a18_data_delayed_6; + a18_data_delayed_8 <= a18_data_delayed_7; + a18_data_delayed_9 <= a18_data_delayed_8; + a18_data_delayed_10 <= a18_data_delayed_9; + a18_data_delayed_11 <= a18_data_delayed_10; + a18_data_delayed_12 <= a18_data_delayed_11; + a18_data_delayed_13 <= a18_data_delayed_12; + a18_data_delayed_14 <= a18_data_delayed_13; + a18_data_delayed_15 <= a18_data_delayed_14; + a18_data_delayed_16 <= a18_data_delayed_15; + a18_data_delayed_17 <= a18_data_delayed_16; + a18_data_delayed_18 <= a18_data_delayed_17; + a19_data_delayed_2 <= a19_data_delayed_1; + a19_data_delayed_3 <= a19_data_delayed_2; + a19_data_delayed_4 <= a19_data_delayed_3; + a19_data_delayed_5 <= a19_data_delayed_4; + a19_data_delayed_6 <= a19_data_delayed_5; + a19_data_delayed_7 <= a19_data_delayed_6; + a19_data_delayed_8 <= a19_data_delayed_7; + a19_data_delayed_9 <= a19_data_delayed_8; + a19_data_delayed_10 <= a19_data_delayed_9; + a19_data_delayed_11 <= a19_data_delayed_10; + a19_data_delayed_12 <= a19_data_delayed_11; + a19_data_delayed_13 <= a19_data_delayed_12; + a19_data_delayed_14 <= a19_data_delayed_13; + a19_data_delayed_15 <= a19_data_delayed_14; + a19_data_delayed_16 <= a19_data_delayed_15; + a19_data_delayed_17 <= a19_data_delayed_16; + a19_data_delayed_18 <= a19_data_delayed_17; + a19_data_delayed_19 <= a19_data_delayed_18; + a20_data_delayed_2 <= a20_data_delayed_1; + a20_data_delayed_3 <= a20_data_delayed_2; + a20_data_delayed_4 <= a20_data_delayed_3; + a20_data_delayed_5 <= a20_data_delayed_4; + a20_data_delayed_6 <= a20_data_delayed_5; + a20_data_delayed_7 <= a20_data_delayed_6; + a20_data_delayed_8 <= a20_data_delayed_7; + a20_data_delayed_9 <= a20_data_delayed_8; + a20_data_delayed_10 <= a20_data_delayed_9; + a20_data_delayed_11 <= a20_data_delayed_10; + a20_data_delayed_12 <= a20_data_delayed_11; + a20_data_delayed_13 <= a20_data_delayed_12; + a20_data_delayed_14 <= a20_data_delayed_13; + a20_data_delayed_15 <= a20_data_delayed_14; + a20_data_delayed_16 <= a20_data_delayed_15; + a20_data_delayed_17 <= a20_data_delayed_16; + a20_data_delayed_18 <= a20_data_delayed_17; + a20_data_delayed_19 <= a20_data_delayed_18; + a20_data_delayed_20 <= a20_data_delayed_19; + a21_data_delayed_2 <= a21_data_delayed_1; + a21_data_delayed_3 <= a21_data_delayed_2; + a21_data_delayed_4 <= a21_data_delayed_3; + a21_data_delayed_5 <= a21_data_delayed_4; + a21_data_delayed_6 <= a21_data_delayed_5; + a21_data_delayed_7 <= a21_data_delayed_6; + a21_data_delayed_8 <= a21_data_delayed_7; + a21_data_delayed_9 <= a21_data_delayed_8; + a21_data_delayed_10 <= a21_data_delayed_9; + a21_data_delayed_11 <= a21_data_delayed_10; + a21_data_delayed_12 <= a21_data_delayed_11; + a21_data_delayed_13 <= a21_data_delayed_12; + a21_data_delayed_14 <= a21_data_delayed_13; + a21_data_delayed_15 <= a21_data_delayed_14; + a21_data_delayed_16 <= a21_data_delayed_15; + a21_data_delayed_17 <= a21_data_delayed_16; + a21_data_delayed_18 <= a21_data_delayed_17; + a21_data_delayed_19 <= a21_data_delayed_18; + a21_data_delayed_20 <= a21_data_delayed_19; + a21_data_delayed_21 <= a21_data_delayed_20; + a22_data_delayed_2 <= a22_data_delayed_1; + a22_data_delayed_3 <= a22_data_delayed_2; + a22_data_delayed_4 <= a22_data_delayed_3; + a22_data_delayed_5 <= a22_data_delayed_4; + a22_data_delayed_6 <= a22_data_delayed_5; + a22_data_delayed_7 <= a22_data_delayed_6; + a22_data_delayed_8 <= a22_data_delayed_7; + a22_data_delayed_9 <= a22_data_delayed_8; + a22_data_delayed_10 <= a22_data_delayed_9; + a22_data_delayed_11 <= a22_data_delayed_10; + a22_data_delayed_12 <= a22_data_delayed_11; + a22_data_delayed_13 <= a22_data_delayed_12; + a22_data_delayed_14 <= a22_data_delayed_13; + a22_data_delayed_15 <= a22_data_delayed_14; + a22_data_delayed_16 <= a22_data_delayed_15; + a22_data_delayed_17 <= a22_data_delayed_16; + a22_data_delayed_18 <= a22_data_delayed_17; + a22_data_delayed_19 <= a22_data_delayed_18; + a22_data_delayed_20 <= a22_data_delayed_19; + a22_data_delayed_21 <= a22_data_delayed_20; + a22_data_delayed_22 <= a22_data_delayed_21; + a23_data_delayed_2 <= a23_data_delayed_1; + a23_data_delayed_3 <= a23_data_delayed_2; + a23_data_delayed_4 <= a23_data_delayed_3; + a23_data_delayed_5 <= a23_data_delayed_4; + a23_data_delayed_6 <= a23_data_delayed_5; + a23_data_delayed_7 <= a23_data_delayed_6; + a23_data_delayed_8 <= a23_data_delayed_7; + a23_data_delayed_9 <= a23_data_delayed_8; + a23_data_delayed_10 <= a23_data_delayed_9; + a23_data_delayed_11 <= a23_data_delayed_10; + a23_data_delayed_12 <= a23_data_delayed_11; + a23_data_delayed_13 <= a23_data_delayed_12; + a23_data_delayed_14 <= a23_data_delayed_13; + a23_data_delayed_15 <= a23_data_delayed_14; + a23_data_delayed_16 <= a23_data_delayed_15; + a23_data_delayed_17 <= a23_data_delayed_16; + a23_data_delayed_18 <= a23_data_delayed_17; + a23_data_delayed_19 <= a23_data_delayed_18; + a23_data_delayed_20 <= a23_data_delayed_19; + a23_data_delayed_21 <= a23_data_delayed_20; + a23_data_delayed_22 <= a23_data_delayed_21; + a23_data_delayed_23 <= a23_data_delayed_22; + a24_data_delayed_2 <= a24_data_delayed_1; + a24_data_delayed_3 <= a24_data_delayed_2; + a24_data_delayed_4 <= a24_data_delayed_3; + a24_data_delayed_5 <= a24_data_delayed_4; + a24_data_delayed_6 <= a24_data_delayed_5; + a24_data_delayed_7 <= a24_data_delayed_6; + a24_data_delayed_8 <= a24_data_delayed_7; + a24_data_delayed_9 <= a24_data_delayed_8; + a24_data_delayed_10 <= a24_data_delayed_9; + a24_data_delayed_11 <= a24_data_delayed_10; + a24_data_delayed_12 <= a24_data_delayed_11; + a24_data_delayed_13 <= a24_data_delayed_12; + a24_data_delayed_14 <= a24_data_delayed_13; + a24_data_delayed_15 <= a24_data_delayed_14; + a24_data_delayed_16 <= a24_data_delayed_15; + a24_data_delayed_17 <= a24_data_delayed_16; + a24_data_delayed_18 <= a24_data_delayed_17; + a24_data_delayed_19 <= a24_data_delayed_18; + a24_data_delayed_20 <= a24_data_delayed_19; + a24_data_delayed_21 <= a24_data_delayed_20; + a24_data_delayed_22 <= a24_data_delayed_21; + a24_data_delayed_23 <= a24_data_delayed_22; + a24_data_delayed_24 <= a24_data_delayed_23; + a25_data_delayed_2 <= a25_data_delayed_1; + a25_data_delayed_3 <= a25_data_delayed_2; + a25_data_delayed_4 <= a25_data_delayed_3; + a25_data_delayed_5 <= a25_data_delayed_4; + a25_data_delayed_6 <= a25_data_delayed_5; + a25_data_delayed_7 <= a25_data_delayed_6; + a25_data_delayed_8 <= a25_data_delayed_7; + a25_data_delayed_9 <= a25_data_delayed_8; + a25_data_delayed_10 <= a25_data_delayed_9; + a25_data_delayed_11 <= a25_data_delayed_10; + a25_data_delayed_12 <= a25_data_delayed_11; + a25_data_delayed_13 <= a25_data_delayed_12; + a25_data_delayed_14 <= a25_data_delayed_13; + a25_data_delayed_15 <= a25_data_delayed_14; + a25_data_delayed_16 <= a25_data_delayed_15; + a25_data_delayed_17 <= a25_data_delayed_16; + a25_data_delayed_18 <= a25_data_delayed_17; + a25_data_delayed_19 <= a25_data_delayed_18; + a25_data_delayed_20 <= a25_data_delayed_19; + a25_data_delayed_21 <= a25_data_delayed_20; + a25_data_delayed_22 <= a25_data_delayed_21; + a25_data_delayed_23 <= a25_data_delayed_22; + a25_data_delayed_24 <= a25_data_delayed_23; + a25_data_delayed_25 <= a25_data_delayed_24; + a26_data_delayed_2 <= a26_data_delayed_1; + a26_data_delayed_3 <= a26_data_delayed_2; + a26_data_delayed_4 <= a26_data_delayed_3; + a26_data_delayed_5 <= a26_data_delayed_4; + a26_data_delayed_6 <= a26_data_delayed_5; + a26_data_delayed_7 <= a26_data_delayed_6; + a26_data_delayed_8 <= a26_data_delayed_7; + a26_data_delayed_9 <= a26_data_delayed_8; + a26_data_delayed_10 <= a26_data_delayed_9; + a26_data_delayed_11 <= a26_data_delayed_10; + a26_data_delayed_12 <= a26_data_delayed_11; + a26_data_delayed_13 <= a26_data_delayed_12; + a26_data_delayed_14 <= a26_data_delayed_13; + a26_data_delayed_15 <= a26_data_delayed_14; + a26_data_delayed_16 <= a26_data_delayed_15; + a26_data_delayed_17 <= a26_data_delayed_16; + a26_data_delayed_18 <= a26_data_delayed_17; + a26_data_delayed_19 <= a26_data_delayed_18; + a26_data_delayed_20 <= a26_data_delayed_19; + a26_data_delayed_21 <= a26_data_delayed_20; + a26_data_delayed_22 <= a26_data_delayed_21; + a26_data_delayed_23 <= a26_data_delayed_22; + a26_data_delayed_24 <= a26_data_delayed_23; + a26_data_delayed_25 <= a26_data_delayed_24; + a26_data_delayed_26 <= a26_data_delayed_25; + a27_data_delayed_2 <= a27_data_delayed_1; + a27_data_delayed_3 <= a27_data_delayed_2; + a27_data_delayed_4 <= a27_data_delayed_3; + a27_data_delayed_5 <= a27_data_delayed_4; + a27_data_delayed_6 <= a27_data_delayed_5; + a27_data_delayed_7 <= a27_data_delayed_6; + a27_data_delayed_8 <= a27_data_delayed_7; + a27_data_delayed_9 <= a27_data_delayed_8; + a27_data_delayed_10 <= a27_data_delayed_9; + a27_data_delayed_11 <= a27_data_delayed_10; + a27_data_delayed_12 <= a27_data_delayed_11; + a27_data_delayed_13 <= a27_data_delayed_12; + a27_data_delayed_14 <= a27_data_delayed_13; + a27_data_delayed_15 <= a27_data_delayed_14; + a27_data_delayed_16 <= a27_data_delayed_15; + a27_data_delayed_17 <= a27_data_delayed_16; + a27_data_delayed_18 <= a27_data_delayed_17; + a27_data_delayed_19 <= a27_data_delayed_18; + a27_data_delayed_20 <= a27_data_delayed_19; + a27_data_delayed_21 <= a27_data_delayed_20; + a27_data_delayed_22 <= a27_data_delayed_21; + a27_data_delayed_23 <= a27_data_delayed_22; + a27_data_delayed_24 <= a27_data_delayed_23; + a27_data_delayed_25 <= a27_data_delayed_24; + a27_data_delayed_26 <= a27_data_delayed_25; + a27_data_delayed_27 <= a27_data_delayed_26; + a28_data_delayed_2 <= a28_data_delayed_1; + a28_data_delayed_3 <= a28_data_delayed_2; + a28_data_delayed_4 <= a28_data_delayed_3; + a28_data_delayed_5 <= a28_data_delayed_4; + a28_data_delayed_6 <= a28_data_delayed_5; + a28_data_delayed_7 <= a28_data_delayed_6; + a28_data_delayed_8 <= a28_data_delayed_7; + a28_data_delayed_9 <= a28_data_delayed_8; + a28_data_delayed_10 <= a28_data_delayed_9; + a28_data_delayed_11 <= a28_data_delayed_10; + a28_data_delayed_12 <= a28_data_delayed_11; + a28_data_delayed_13 <= a28_data_delayed_12; + a28_data_delayed_14 <= a28_data_delayed_13; + a28_data_delayed_15 <= a28_data_delayed_14; + a28_data_delayed_16 <= a28_data_delayed_15; + a28_data_delayed_17 <= a28_data_delayed_16; + a28_data_delayed_18 <= a28_data_delayed_17; + a28_data_delayed_19 <= a28_data_delayed_18; + a28_data_delayed_20 <= a28_data_delayed_19; + a28_data_delayed_21 <= a28_data_delayed_20; + a28_data_delayed_22 <= a28_data_delayed_21; + a28_data_delayed_23 <= a28_data_delayed_22; + a28_data_delayed_24 <= a28_data_delayed_23; + a28_data_delayed_25 <= a28_data_delayed_24; + a28_data_delayed_26 <= a28_data_delayed_25; + a28_data_delayed_27 <= a28_data_delayed_26; + a28_data_delayed_28 <= a28_data_delayed_27; + a29_data_delayed_2 <= a29_data_delayed_1; + a29_data_delayed_3 <= a29_data_delayed_2; + a29_data_delayed_4 <= a29_data_delayed_3; + a29_data_delayed_5 <= a29_data_delayed_4; + a29_data_delayed_6 <= a29_data_delayed_5; + a29_data_delayed_7 <= a29_data_delayed_6; + a29_data_delayed_8 <= a29_data_delayed_7; + a29_data_delayed_9 <= a29_data_delayed_8; + a29_data_delayed_10 <= a29_data_delayed_9; + a29_data_delayed_11 <= a29_data_delayed_10; + a29_data_delayed_12 <= a29_data_delayed_11; + a29_data_delayed_13 <= a29_data_delayed_12; + a29_data_delayed_14 <= a29_data_delayed_13; + a29_data_delayed_15 <= a29_data_delayed_14; + a29_data_delayed_16 <= a29_data_delayed_15; + a29_data_delayed_17 <= a29_data_delayed_16; + a29_data_delayed_18 <= a29_data_delayed_17; + a29_data_delayed_19 <= a29_data_delayed_18; + a29_data_delayed_20 <= a29_data_delayed_19; + a29_data_delayed_21 <= a29_data_delayed_20; + a29_data_delayed_22 <= a29_data_delayed_21; + a29_data_delayed_23 <= a29_data_delayed_22; + a29_data_delayed_24 <= a29_data_delayed_23; + a29_data_delayed_25 <= a29_data_delayed_24; + a29_data_delayed_26 <= a29_data_delayed_25; + a29_data_delayed_27 <= a29_data_delayed_26; + a29_data_delayed_28 <= a29_data_delayed_27; + a29_data_delayed_29 <= a29_data_delayed_28; + a30_data_delayed_2 <= a30_data_delayed_1; + a30_data_delayed_3 <= a30_data_delayed_2; + a30_data_delayed_4 <= a30_data_delayed_3; + a30_data_delayed_5 <= a30_data_delayed_4; + a30_data_delayed_6 <= a30_data_delayed_5; + a30_data_delayed_7 <= a30_data_delayed_6; + a30_data_delayed_8 <= a30_data_delayed_7; + a30_data_delayed_9 <= a30_data_delayed_8; + a30_data_delayed_10 <= a30_data_delayed_9; + a30_data_delayed_11 <= a30_data_delayed_10; + a30_data_delayed_12 <= a30_data_delayed_11; + a30_data_delayed_13 <= a30_data_delayed_12; + a30_data_delayed_14 <= a30_data_delayed_13; + a30_data_delayed_15 <= a30_data_delayed_14; + a30_data_delayed_16 <= a30_data_delayed_15; + a30_data_delayed_17 <= a30_data_delayed_16; + a30_data_delayed_18 <= a30_data_delayed_17; + a30_data_delayed_19 <= a30_data_delayed_18; + a30_data_delayed_20 <= a30_data_delayed_19; + a30_data_delayed_21 <= a30_data_delayed_20; + a30_data_delayed_22 <= a30_data_delayed_21; + a30_data_delayed_23 <= a30_data_delayed_22; + a30_data_delayed_24 <= a30_data_delayed_23; + a30_data_delayed_25 <= a30_data_delayed_24; + a30_data_delayed_26 <= a30_data_delayed_25; + a30_data_delayed_27 <= a30_data_delayed_26; + a30_data_delayed_28 <= a30_data_delayed_27; + a30_data_delayed_29 <= a30_data_delayed_28; + a30_data_delayed_30 <= a30_data_delayed_29; + a31_data_delayed_2 <= a31_data_delayed_1; + a31_data_delayed_3 <= a31_data_delayed_2; + a31_data_delayed_4 <= a31_data_delayed_3; + a31_data_delayed_5 <= a31_data_delayed_4; + a31_data_delayed_6 <= a31_data_delayed_5; + a31_data_delayed_7 <= a31_data_delayed_6; + a31_data_delayed_8 <= a31_data_delayed_7; + a31_data_delayed_9 <= a31_data_delayed_8; + a31_data_delayed_10 <= a31_data_delayed_9; + a31_data_delayed_11 <= a31_data_delayed_10; + a31_data_delayed_12 <= a31_data_delayed_11; + a31_data_delayed_13 <= a31_data_delayed_12; + a31_data_delayed_14 <= a31_data_delayed_13; + a31_data_delayed_15 <= a31_data_delayed_14; + a31_data_delayed_16 <= a31_data_delayed_15; + a31_data_delayed_17 <= a31_data_delayed_16; + a31_data_delayed_18 <= a31_data_delayed_17; + a31_data_delayed_19 <= a31_data_delayed_18; + a31_data_delayed_20 <= a31_data_delayed_19; + a31_data_delayed_21 <= a31_data_delayed_20; + a31_data_delayed_22 <= a31_data_delayed_21; + a31_data_delayed_23 <= a31_data_delayed_22; + a31_data_delayed_24 <= a31_data_delayed_23; + a31_data_delayed_25 <= a31_data_delayed_24; + a31_data_delayed_26 <= a31_data_delayed_25; + a31_data_delayed_27 <= a31_data_delayed_26; + a31_data_delayed_28 <= a31_data_delayed_27; + a31_data_delayed_29 <= a31_data_delayed_28; + a31_data_delayed_30 <= a31_data_delayed_29; + a31_data_delayed_31 <= a31_data_delayed_30; + + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate addresses to BRAM B +////////////////////////////////////////////////////////////////////////// +reg [`AWIDTH-1:0] b_addr; +reg b_mem_access; //flag that tells whether the matmul is trying to access memory or not +always @(posedge clk) begin + //else if (clk_cnt >= b_loc*`MAT_MUL_SIZE+final_mat_mul_size) begin + //Writing the line above to avoid multiplication: + + if ((reset || ~start_mat_mul) || (clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= address_mat_b - address_stride_b; + + b_mem_access <= 0; + end + //else if ((clk_cnt >= b_loc*`MAT_MUL_SIZE) && (clk_cnt < b_loc*`MAT_MUL_SIZE+final_mat_mul_size)) begin + //Writing the line above to avoid multiplication: + + else if ((clk_cnt >= (b_loc<<`LOG2_MAT_MUL_SIZE)) && (clk_cnt < (b_loc<<`LOG2_MAT_MUL_SIZE)+`final_mat_mul_size)) begin + + b_addr <= b_addr + address_stride_b; + + b_mem_access <= 1; + end +end + +////////////////////////////////////////////////////////////////////////// +// Logic to generate valid signals for data coming from BRAM B +////////////////////////////////////////////////////////////////////////// +reg [7:0] b_mem_access_counter; +always @(posedge clk) begin + if (reset || ~start_mat_mul) begin + b_mem_access_counter <= 0; + end + else if (b_mem_access == 1) begin + b_mem_access_counter <= b_mem_access_counter + 1; + end + else begin + b_mem_access_counter <= 0; + end +end + +wire b_data_valid; //flag that tells whether the data from memory is valid +assign b_data_valid = + ((validity_mask_b_rows[0]==1'b0 && b_mem_access_counter==1) || + (validity_mask_b_rows[1]==1'b0 && b_mem_access_counter==2) || + (validity_mask_b_rows[2]==1'b0 && b_mem_access_counter==3) || + (validity_mask_b_rows[3]==1'b0 && b_mem_access_counter==4) || + (validity_mask_b_rows[4]==1'b0 && b_mem_access_counter==5) || + (validity_mask_b_rows[5]==1'b0 && b_mem_access_counter==6) || + (validity_mask_b_rows[6]==1'b0 && b_mem_access_counter==7) || + (validity_mask_b_rows[7]==1'b0 && b_mem_access_counter==8) || + (validity_mask_b_rows[8]==1'b0 && b_mem_access_counter==9) || + (validity_mask_b_rows[9]==1'b0 && b_mem_access_counter==10) || + (validity_mask_b_rows[10]==1'b0 && b_mem_access_counter==11) || + (validity_mask_b_rows[11]==1'b0 && b_mem_access_counter==12) || + (validity_mask_b_rows[12]==1'b0 && b_mem_access_counter==13) || + (validity_mask_b_rows[13]==1'b0 && b_mem_access_counter==14) || + (validity_mask_b_rows[14]==1'b0 && b_mem_access_counter==15) || + (validity_mask_b_rows[15]==1'b0 && b_mem_access_counter==16) || + (validity_mask_b_rows[16]==1'b0 && b_mem_access_counter==17) || + (validity_mask_b_rows[17]==1'b0 && b_mem_access_counter==18) || + (validity_mask_b_rows[18]==1'b0 && b_mem_access_counter==19) || + (validity_mask_b_rows[19]==1'b0 && b_mem_access_counter==20) || + (validity_mask_b_rows[20]==1'b0 && b_mem_access_counter==21) || + (validity_mask_b_rows[21]==1'b0 && b_mem_access_counter==22) || + (validity_mask_b_rows[22]==1'b0 && b_mem_access_counter==23) || + (validity_mask_b_rows[23]==1'b0 && b_mem_access_counter==24) || + (validity_mask_b_rows[24]==1'b0 && b_mem_access_counter==25) || + (validity_mask_b_rows[25]==1'b0 && b_mem_access_counter==26) || + (validity_mask_b_rows[26]==1'b0 && b_mem_access_counter==27) || + (validity_mask_b_rows[27]==1'b0 && b_mem_access_counter==28) || + (validity_mask_b_rows[28]==1'b0 && b_mem_access_counter==29) || + (validity_mask_b_rows[29]==1'b0 && b_mem_access_counter==30) || + (validity_mask_b_rows[30]==1'b0 && b_mem_access_counter==31) || + (validity_mask_b_rows[31]==1'b0 && b_mem_access_counter==32)) ? + + 1'b0 : (b_mem_access_counter >= `MEM_ACCESS_LATENCY); + +////////////////////////////////////////////////////////////////////////// +// Logic to delay certain parts of the data received from BRAM B (systolic data setup) +////////////////////////////////////////////////////////////////////////// +assign b0_data = b_data[1*`DWIDTH-1:0*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[0]}}; +assign b1_data = b_data[2*`DWIDTH-1:1*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[1]}}; +assign b2_data = b_data[3*`DWIDTH-1:2*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[2]}}; +assign b3_data = b_data[4*`DWIDTH-1:3*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[3]}}; +assign b4_data = b_data[5*`DWIDTH-1:4*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[4]}}; +assign b5_data = b_data[6*`DWIDTH-1:5*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[5]}}; +assign b6_data = b_data[7*`DWIDTH-1:6*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[6]}}; +assign b7_data = b_data[8*`DWIDTH-1:7*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[7]}}; +assign b8_data = b_data[9*`DWIDTH-1:8*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[8]}}; +assign b9_data = b_data[10*`DWIDTH-1:9*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[9]}}; +assign b10_data = b_data[11*`DWIDTH-1:10*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[10]}}; +assign b11_data = b_data[12*`DWIDTH-1:11*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[11]}}; +assign b12_data = b_data[13*`DWIDTH-1:12*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[12]}}; +assign b13_data = b_data[14*`DWIDTH-1:13*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[13]}}; +assign b14_data = b_data[15*`DWIDTH-1:14*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[14]}}; +assign b15_data = b_data[16*`DWIDTH-1:15*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[15]}}; +assign b16_data = b_data[17*`DWIDTH-1:16*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[16]}}; +assign b17_data = b_data[18*`DWIDTH-1:17*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[17]}}; +assign b18_data = b_data[19*`DWIDTH-1:18*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[18]}}; +assign b19_data = b_data[20*`DWIDTH-1:19*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[19]}}; +assign b20_data = b_data[21*`DWIDTH-1:20*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[20]}}; +assign b21_data = b_data[22*`DWIDTH-1:21*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[21]}}; +assign b22_data = b_data[23*`DWIDTH-1:22*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[22]}}; +assign b23_data = b_data[24*`DWIDTH-1:23*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[23]}}; +assign b24_data = b_data[25*`DWIDTH-1:24*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[24]}}; +assign b25_data = b_data[26*`DWIDTH-1:25*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[25]}}; +assign b26_data = b_data[27*`DWIDTH-1:26*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[26]}}; +assign b27_data = b_data[28*`DWIDTH-1:27*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[27]}}; +assign b28_data = b_data[29*`DWIDTH-1:28*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[28]}}; +assign b29_data = b_data[30*`DWIDTH-1:29*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[29]}}; +assign b30_data = b_data[31*`DWIDTH-1:30*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[30]}}; +assign b31_data = b_data[32*`DWIDTH-1:31*`DWIDTH] & {`DWIDTH{b_data_valid}} & {`DWIDTH{validity_mask_b_cols[31]}}; + +reg [`DWIDTH-1:0] b1_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_1; +reg [`DWIDTH-1:0] b2_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_1; +reg [`DWIDTH-1:0] b3_data_delayed_2; +reg [`DWIDTH-1:0] b3_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_1; +reg [`DWIDTH-1:0] b4_data_delayed_2; +reg [`DWIDTH-1:0] b4_data_delayed_3; +reg [`DWIDTH-1:0] b4_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_1; +reg [`DWIDTH-1:0] b5_data_delayed_2; +reg [`DWIDTH-1:0] b5_data_delayed_3; +reg [`DWIDTH-1:0] b5_data_delayed_4; +reg [`DWIDTH-1:0] b5_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_1; +reg [`DWIDTH-1:0] b6_data_delayed_2; +reg [`DWIDTH-1:0] b6_data_delayed_3; +reg [`DWIDTH-1:0] b6_data_delayed_4; +reg [`DWIDTH-1:0] b6_data_delayed_5; +reg [`DWIDTH-1:0] b6_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_1; +reg [`DWIDTH-1:0] b7_data_delayed_2; +reg [`DWIDTH-1:0] b7_data_delayed_3; +reg [`DWIDTH-1:0] b7_data_delayed_4; +reg [`DWIDTH-1:0] b7_data_delayed_5; +reg [`DWIDTH-1:0] b7_data_delayed_6; +reg [`DWIDTH-1:0] b7_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_1; +reg [`DWIDTH-1:0] b8_data_delayed_2; +reg [`DWIDTH-1:0] b8_data_delayed_3; +reg [`DWIDTH-1:0] b8_data_delayed_4; +reg [`DWIDTH-1:0] b8_data_delayed_5; +reg [`DWIDTH-1:0] b8_data_delayed_6; +reg [`DWIDTH-1:0] b8_data_delayed_7; +reg [`DWIDTH-1:0] b8_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_1; +reg [`DWIDTH-1:0] b9_data_delayed_2; +reg [`DWIDTH-1:0] b9_data_delayed_3; +reg [`DWIDTH-1:0] b9_data_delayed_4; +reg [`DWIDTH-1:0] b9_data_delayed_5; +reg [`DWIDTH-1:0] b9_data_delayed_6; +reg [`DWIDTH-1:0] b9_data_delayed_7; +reg [`DWIDTH-1:0] b9_data_delayed_8; +reg [`DWIDTH-1:0] b9_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_1; +reg [`DWIDTH-1:0] b10_data_delayed_2; +reg [`DWIDTH-1:0] b10_data_delayed_3; +reg [`DWIDTH-1:0] b10_data_delayed_4; +reg [`DWIDTH-1:0] b10_data_delayed_5; +reg [`DWIDTH-1:0] b10_data_delayed_6; +reg [`DWIDTH-1:0] b10_data_delayed_7; +reg [`DWIDTH-1:0] b10_data_delayed_8; +reg [`DWIDTH-1:0] b10_data_delayed_9; +reg [`DWIDTH-1:0] b10_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_1; +reg [`DWIDTH-1:0] b11_data_delayed_2; +reg [`DWIDTH-1:0] b11_data_delayed_3; +reg [`DWIDTH-1:0] b11_data_delayed_4; +reg [`DWIDTH-1:0] b11_data_delayed_5; +reg [`DWIDTH-1:0] b11_data_delayed_6; +reg [`DWIDTH-1:0] b11_data_delayed_7; +reg [`DWIDTH-1:0] b11_data_delayed_8; +reg [`DWIDTH-1:0] b11_data_delayed_9; +reg [`DWIDTH-1:0] b11_data_delayed_10; +reg [`DWIDTH-1:0] b11_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_1; +reg [`DWIDTH-1:0] b12_data_delayed_2; +reg [`DWIDTH-1:0] b12_data_delayed_3; +reg [`DWIDTH-1:0] b12_data_delayed_4; +reg [`DWIDTH-1:0] b12_data_delayed_5; +reg [`DWIDTH-1:0] b12_data_delayed_6; +reg [`DWIDTH-1:0] b12_data_delayed_7; +reg [`DWIDTH-1:0] b12_data_delayed_8; +reg [`DWIDTH-1:0] b12_data_delayed_9; +reg [`DWIDTH-1:0] b12_data_delayed_10; +reg [`DWIDTH-1:0] b12_data_delayed_11; +reg [`DWIDTH-1:0] b12_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_1; +reg [`DWIDTH-1:0] b13_data_delayed_2; +reg [`DWIDTH-1:0] b13_data_delayed_3; +reg [`DWIDTH-1:0] b13_data_delayed_4; +reg [`DWIDTH-1:0] b13_data_delayed_5; +reg [`DWIDTH-1:0] b13_data_delayed_6; +reg [`DWIDTH-1:0] b13_data_delayed_7; +reg [`DWIDTH-1:0] b13_data_delayed_8; +reg [`DWIDTH-1:0] b13_data_delayed_9; +reg [`DWIDTH-1:0] b13_data_delayed_10; +reg [`DWIDTH-1:0] b13_data_delayed_11; +reg [`DWIDTH-1:0] b13_data_delayed_12; +reg [`DWIDTH-1:0] b13_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_1; +reg [`DWIDTH-1:0] b14_data_delayed_2; +reg [`DWIDTH-1:0] b14_data_delayed_3; +reg [`DWIDTH-1:0] b14_data_delayed_4; +reg [`DWIDTH-1:0] b14_data_delayed_5; +reg [`DWIDTH-1:0] b14_data_delayed_6; +reg [`DWIDTH-1:0] b14_data_delayed_7; +reg [`DWIDTH-1:0] b14_data_delayed_8; +reg [`DWIDTH-1:0] b14_data_delayed_9; +reg [`DWIDTH-1:0] b14_data_delayed_10; +reg [`DWIDTH-1:0] b14_data_delayed_11; +reg [`DWIDTH-1:0] b14_data_delayed_12; +reg [`DWIDTH-1:0] b14_data_delayed_13; +reg [`DWIDTH-1:0] b14_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_1; +reg [`DWIDTH-1:0] b15_data_delayed_2; +reg [`DWIDTH-1:0] b15_data_delayed_3; +reg [`DWIDTH-1:0] b15_data_delayed_4; +reg [`DWIDTH-1:0] b15_data_delayed_5; +reg [`DWIDTH-1:0] b15_data_delayed_6; +reg [`DWIDTH-1:0] b15_data_delayed_7; +reg [`DWIDTH-1:0] b15_data_delayed_8; +reg [`DWIDTH-1:0] b15_data_delayed_9; +reg [`DWIDTH-1:0] b15_data_delayed_10; +reg [`DWIDTH-1:0] b15_data_delayed_11; +reg [`DWIDTH-1:0] b15_data_delayed_12; +reg [`DWIDTH-1:0] b15_data_delayed_13; +reg [`DWIDTH-1:0] b15_data_delayed_14; +reg [`DWIDTH-1:0] b15_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_1; +reg [`DWIDTH-1:0] b16_data_delayed_2; +reg [`DWIDTH-1:0] b16_data_delayed_3; +reg [`DWIDTH-1:0] b16_data_delayed_4; +reg [`DWIDTH-1:0] b16_data_delayed_5; +reg [`DWIDTH-1:0] b16_data_delayed_6; +reg [`DWIDTH-1:0] b16_data_delayed_7; +reg [`DWIDTH-1:0] b16_data_delayed_8; +reg [`DWIDTH-1:0] b16_data_delayed_9; +reg [`DWIDTH-1:0] b16_data_delayed_10; +reg [`DWIDTH-1:0] b16_data_delayed_11; +reg [`DWIDTH-1:0] b16_data_delayed_12; +reg [`DWIDTH-1:0] b16_data_delayed_13; +reg [`DWIDTH-1:0] b16_data_delayed_14; +reg [`DWIDTH-1:0] b16_data_delayed_15; +reg [`DWIDTH-1:0] b16_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_1; +reg [`DWIDTH-1:0] b17_data_delayed_2; +reg [`DWIDTH-1:0] b17_data_delayed_3; +reg [`DWIDTH-1:0] b17_data_delayed_4; +reg [`DWIDTH-1:0] b17_data_delayed_5; +reg [`DWIDTH-1:0] b17_data_delayed_6; +reg [`DWIDTH-1:0] b17_data_delayed_7; +reg [`DWIDTH-1:0] b17_data_delayed_8; +reg [`DWIDTH-1:0] b17_data_delayed_9; +reg [`DWIDTH-1:0] b17_data_delayed_10; +reg [`DWIDTH-1:0] b17_data_delayed_11; +reg [`DWIDTH-1:0] b17_data_delayed_12; +reg [`DWIDTH-1:0] b17_data_delayed_13; +reg [`DWIDTH-1:0] b17_data_delayed_14; +reg [`DWIDTH-1:0] b17_data_delayed_15; +reg [`DWIDTH-1:0] b17_data_delayed_16; +reg [`DWIDTH-1:0] b17_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_1; +reg [`DWIDTH-1:0] b18_data_delayed_2; +reg [`DWIDTH-1:0] b18_data_delayed_3; +reg [`DWIDTH-1:0] b18_data_delayed_4; +reg [`DWIDTH-1:0] b18_data_delayed_5; +reg [`DWIDTH-1:0] b18_data_delayed_6; +reg [`DWIDTH-1:0] b18_data_delayed_7; +reg [`DWIDTH-1:0] b18_data_delayed_8; +reg [`DWIDTH-1:0] b18_data_delayed_9; +reg [`DWIDTH-1:0] b18_data_delayed_10; +reg [`DWIDTH-1:0] b18_data_delayed_11; +reg [`DWIDTH-1:0] b18_data_delayed_12; +reg [`DWIDTH-1:0] b18_data_delayed_13; +reg [`DWIDTH-1:0] b18_data_delayed_14; +reg [`DWIDTH-1:0] b18_data_delayed_15; +reg [`DWIDTH-1:0] b18_data_delayed_16; +reg [`DWIDTH-1:0] b18_data_delayed_17; +reg [`DWIDTH-1:0] b18_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_1; +reg [`DWIDTH-1:0] b19_data_delayed_2; +reg [`DWIDTH-1:0] b19_data_delayed_3; +reg [`DWIDTH-1:0] b19_data_delayed_4; +reg [`DWIDTH-1:0] b19_data_delayed_5; +reg [`DWIDTH-1:0] b19_data_delayed_6; +reg [`DWIDTH-1:0] b19_data_delayed_7; +reg [`DWIDTH-1:0] b19_data_delayed_8; +reg [`DWIDTH-1:0] b19_data_delayed_9; +reg [`DWIDTH-1:0] b19_data_delayed_10; +reg [`DWIDTH-1:0] b19_data_delayed_11; +reg [`DWIDTH-1:0] b19_data_delayed_12; +reg [`DWIDTH-1:0] b19_data_delayed_13; +reg [`DWIDTH-1:0] b19_data_delayed_14; +reg [`DWIDTH-1:0] b19_data_delayed_15; +reg [`DWIDTH-1:0] b19_data_delayed_16; +reg [`DWIDTH-1:0] b19_data_delayed_17; +reg [`DWIDTH-1:0] b19_data_delayed_18; +reg [`DWIDTH-1:0] b19_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_1; +reg [`DWIDTH-1:0] b20_data_delayed_2; +reg [`DWIDTH-1:0] b20_data_delayed_3; +reg [`DWIDTH-1:0] b20_data_delayed_4; +reg [`DWIDTH-1:0] b20_data_delayed_5; +reg [`DWIDTH-1:0] b20_data_delayed_6; +reg [`DWIDTH-1:0] b20_data_delayed_7; +reg [`DWIDTH-1:0] b20_data_delayed_8; +reg [`DWIDTH-1:0] b20_data_delayed_9; +reg [`DWIDTH-1:0] b20_data_delayed_10; +reg [`DWIDTH-1:0] b20_data_delayed_11; +reg [`DWIDTH-1:0] b20_data_delayed_12; +reg [`DWIDTH-1:0] b20_data_delayed_13; +reg [`DWIDTH-1:0] b20_data_delayed_14; +reg [`DWIDTH-1:0] b20_data_delayed_15; +reg [`DWIDTH-1:0] b20_data_delayed_16; +reg [`DWIDTH-1:0] b20_data_delayed_17; +reg [`DWIDTH-1:0] b20_data_delayed_18; +reg [`DWIDTH-1:0] b20_data_delayed_19; +reg [`DWIDTH-1:0] b20_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_1; +reg [`DWIDTH-1:0] b21_data_delayed_2; +reg [`DWIDTH-1:0] b21_data_delayed_3; +reg [`DWIDTH-1:0] b21_data_delayed_4; +reg [`DWIDTH-1:0] b21_data_delayed_5; +reg [`DWIDTH-1:0] b21_data_delayed_6; +reg [`DWIDTH-1:0] b21_data_delayed_7; +reg [`DWIDTH-1:0] b21_data_delayed_8; +reg [`DWIDTH-1:0] b21_data_delayed_9; +reg [`DWIDTH-1:0] b21_data_delayed_10; +reg [`DWIDTH-1:0] b21_data_delayed_11; +reg [`DWIDTH-1:0] b21_data_delayed_12; +reg [`DWIDTH-1:0] b21_data_delayed_13; +reg [`DWIDTH-1:0] b21_data_delayed_14; +reg [`DWIDTH-1:0] b21_data_delayed_15; +reg [`DWIDTH-1:0] b21_data_delayed_16; +reg [`DWIDTH-1:0] b21_data_delayed_17; +reg [`DWIDTH-1:0] b21_data_delayed_18; +reg [`DWIDTH-1:0] b21_data_delayed_19; +reg [`DWIDTH-1:0] b21_data_delayed_20; +reg [`DWIDTH-1:0] b21_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_1; +reg [`DWIDTH-1:0] b22_data_delayed_2; +reg [`DWIDTH-1:0] b22_data_delayed_3; +reg [`DWIDTH-1:0] b22_data_delayed_4; +reg [`DWIDTH-1:0] b22_data_delayed_5; +reg [`DWIDTH-1:0] b22_data_delayed_6; +reg [`DWIDTH-1:0] b22_data_delayed_7; +reg [`DWIDTH-1:0] b22_data_delayed_8; +reg [`DWIDTH-1:0] b22_data_delayed_9; +reg [`DWIDTH-1:0] b22_data_delayed_10; +reg [`DWIDTH-1:0] b22_data_delayed_11; +reg [`DWIDTH-1:0] b22_data_delayed_12; +reg [`DWIDTH-1:0] b22_data_delayed_13; +reg [`DWIDTH-1:0] b22_data_delayed_14; +reg [`DWIDTH-1:0] b22_data_delayed_15; +reg [`DWIDTH-1:0] b22_data_delayed_16; +reg [`DWIDTH-1:0] b22_data_delayed_17; +reg [`DWIDTH-1:0] b22_data_delayed_18; +reg [`DWIDTH-1:0] b22_data_delayed_19; +reg [`DWIDTH-1:0] b22_data_delayed_20; +reg [`DWIDTH-1:0] b22_data_delayed_21; +reg [`DWIDTH-1:0] b22_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_1; +reg [`DWIDTH-1:0] b23_data_delayed_2; +reg [`DWIDTH-1:0] b23_data_delayed_3; +reg [`DWIDTH-1:0] b23_data_delayed_4; +reg [`DWIDTH-1:0] b23_data_delayed_5; +reg [`DWIDTH-1:0] b23_data_delayed_6; +reg [`DWIDTH-1:0] b23_data_delayed_7; +reg [`DWIDTH-1:0] b23_data_delayed_8; +reg [`DWIDTH-1:0] b23_data_delayed_9; +reg [`DWIDTH-1:0] b23_data_delayed_10; +reg [`DWIDTH-1:0] b23_data_delayed_11; +reg [`DWIDTH-1:0] b23_data_delayed_12; +reg [`DWIDTH-1:0] b23_data_delayed_13; +reg [`DWIDTH-1:0] b23_data_delayed_14; +reg [`DWIDTH-1:0] b23_data_delayed_15; +reg [`DWIDTH-1:0] b23_data_delayed_16; +reg [`DWIDTH-1:0] b23_data_delayed_17; +reg [`DWIDTH-1:0] b23_data_delayed_18; +reg [`DWIDTH-1:0] b23_data_delayed_19; +reg [`DWIDTH-1:0] b23_data_delayed_20; +reg [`DWIDTH-1:0] b23_data_delayed_21; +reg [`DWIDTH-1:0] b23_data_delayed_22; +reg [`DWIDTH-1:0] b23_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_1; +reg [`DWIDTH-1:0] b24_data_delayed_2; +reg [`DWIDTH-1:0] b24_data_delayed_3; +reg [`DWIDTH-1:0] b24_data_delayed_4; +reg [`DWIDTH-1:0] b24_data_delayed_5; +reg [`DWIDTH-1:0] b24_data_delayed_6; +reg [`DWIDTH-1:0] b24_data_delayed_7; +reg [`DWIDTH-1:0] b24_data_delayed_8; +reg [`DWIDTH-1:0] b24_data_delayed_9; +reg [`DWIDTH-1:0] b24_data_delayed_10; +reg [`DWIDTH-1:0] b24_data_delayed_11; +reg [`DWIDTH-1:0] b24_data_delayed_12; +reg [`DWIDTH-1:0] b24_data_delayed_13; +reg [`DWIDTH-1:0] b24_data_delayed_14; +reg [`DWIDTH-1:0] b24_data_delayed_15; +reg [`DWIDTH-1:0] b24_data_delayed_16; +reg [`DWIDTH-1:0] b24_data_delayed_17; +reg [`DWIDTH-1:0] b24_data_delayed_18; +reg [`DWIDTH-1:0] b24_data_delayed_19; +reg [`DWIDTH-1:0] b24_data_delayed_20; +reg [`DWIDTH-1:0] b24_data_delayed_21; +reg [`DWIDTH-1:0] b24_data_delayed_22; +reg [`DWIDTH-1:0] b24_data_delayed_23; +reg [`DWIDTH-1:0] b24_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_1; +reg [`DWIDTH-1:0] b25_data_delayed_2; +reg [`DWIDTH-1:0] b25_data_delayed_3; +reg [`DWIDTH-1:0] b25_data_delayed_4; +reg [`DWIDTH-1:0] b25_data_delayed_5; +reg [`DWIDTH-1:0] b25_data_delayed_6; +reg [`DWIDTH-1:0] b25_data_delayed_7; +reg [`DWIDTH-1:0] b25_data_delayed_8; +reg [`DWIDTH-1:0] b25_data_delayed_9; +reg [`DWIDTH-1:0] b25_data_delayed_10; +reg [`DWIDTH-1:0] b25_data_delayed_11; +reg [`DWIDTH-1:0] b25_data_delayed_12; +reg [`DWIDTH-1:0] b25_data_delayed_13; +reg [`DWIDTH-1:0] b25_data_delayed_14; +reg [`DWIDTH-1:0] b25_data_delayed_15; +reg [`DWIDTH-1:0] b25_data_delayed_16; +reg [`DWIDTH-1:0] b25_data_delayed_17; +reg [`DWIDTH-1:0] b25_data_delayed_18; +reg [`DWIDTH-1:0] b25_data_delayed_19; +reg [`DWIDTH-1:0] b25_data_delayed_20; +reg [`DWIDTH-1:0] b25_data_delayed_21; +reg [`DWIDTH-1:0] b25_data_delayed_22; +reg [`DWIDTH-1:0] b25_data_delayed_23; +reg [`DWIDTH-1:0] b25_data_delayed_24; +reg [`DWIDTH-1:0] b25_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_1; +reg [`DWIDTH-1:0] b26_data_delayed_2; +reg [`DWIDTH-1:0] b26_data_delayed_3; +reg [`DWIDTH-1:0] b26_data_delayed_4; +reg [`DWIDTH-1:0] b26_data_delayed_5; +reg [`DWIDTH-1:0] b26_data_delayed_6; +reg [`DWIDTH-1:0] b26_data_delayed_7; +reg [`DWIDTH-1:0] b26_data_delayed_8; +reg [`DWIDTH-1:0] b26_data_delayed_9; +reg [`DWIDTH-1:0] b26_data_delayed_10; +reg [`DWIDTH-1:0] b26_data_delayed_11; +reg [`DWIDTH-1:0] b26_data_delayed_12; +reg [`DWIDTH-1:0] b26_data_delayed_13; +reg [`DWIDTH-1:0] b26_data_delayed_14; +reg [`DWIDTH-1:0] b26_data_delayed_15; +reg [`DWIDTH-1:0] b26_data_delayed_16; +reg [`DWIDTH-1:0] b26_data_delayed_17; +reg [`DWIDTH-1:0] b26_data_delayed_18; +reg [`DWIDTH-1:0] b26_data_delayed_19; +reg [`DWIDTH-1:0] b26_data_delayed_20; +reg [`DWIDTH-1:0] b26_data_delayed_21; +reg [`DWIDTH-1:0] b26_data_delayed_22; +reg [`DWIDTH-1:0] b26_data_delayed_23; +reg [`DWIDTH-1:0] b26_data_delayed_24; +reg [`DWIDTH-1:0] b26_data_delayed_25; +reg [`DWIDTH-1:0] b26_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_1; +reg [`DWIDTH-1:0] b27_data_delayed_2; +reg [`DWIDTH-1:0] b27_data_delayed_3; +reg [`DWIDTH-1:0] b27_data_delayed_4; +reg [`DWIDTH-1:0] b27_data_delayed_5; +reg [`DWIDTH-1:0] b27_data_delayed_6; +reg [`DWIDTH-1:0] b27_data_delayed_7; +reg [`DWIDTH-1:0] b27_data_delayed_8; +reg [`DWIDTH-1:0] b27_data_delayed_9; +reg [`DWIDTH-1:0] b27_data_delayed_10; +reg [`DWIDTH-1:0] b27_data_delayed_11; +reg [`DWIDTH-1:0] b27_data_delayed_12; +reg [`DWIDTH-1:0] b27_data_delayed_13; +reg [`DWIDTH-1:0] b27_data_delayed_14; +reg [`DWIDTH-1:0] b27_data_delayed_15; +reg [`DWIDTH-1:0] b27_data_delayed_16; +reg [`DWIDTH-1:0] b27_data_delayed_17; +reg [`DWIDTH-1:0] b27_data_delayed_18; +reg [`DWIDTH-1:0] b27_data_delayed_19; +reg [`DWIDTH-1:0] b27_data_delayed_20; +reg [`DWIDTH-1:0] b27_data_delayed_21; +reg [`DWIDTH-1:0] b27_data_delayed_22; +reg [`DWIDTH-1:0] b27_data_delayed_23; +reg [`DWIDTH-1:0] b27_data_delayed_24; +reg [`DWIDTH-1:0] b27_data_delayed_25; +reg [`DWIDTH-1:0] b27_data_delayed_26; +reg [`DWIDTH-1:0] b27_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_1; +reg [`DWIDTH-1:0] b28_data_delayed_2; +reg [`DWIDTH-1:0] b28_data_delayed_3; +reg [`DWIDTH-1:0] b28_data_delayed_4; +reg [`DWIDTH-1:0] b28_data_delayed_5; +reg [`DWIDTH-1:0] b28_data_delayed_6; +reg [`DWIDTH-1:0] b28_data_delayed_7; +reg [`DWIDTH-1:0] b28_data_delayed_8; +reg [`DWIDTH-1:0] b28_data_delayed_9; +reg [`DWIDTH-1:0] b28_data_delayed_10; +reg [`DWIDTH-1:0] b28_data_delayed_11; +reg [`DWIDTH-1:0] b28_data_delayed_12; +reg [`DWIDTH-1:0] b28_data_delayed_13; +reg [`DWIDTH-1:0] b28_data_delayed_14; +reg [`DWIDTH-1:0] b28_data_delayed_15; +reg [`DWIDTH-1:0] b28_data_delayed_16; +reg [`DWIDTH-1:0] b28_data_delayed_17; +reg [`DWIDTH-1:0] b28_data_delayed_18; +reg [`DWIDTH-1:0] b28_data_delayed_19; +reg [`DWIDTH-1:0] b28_data_delayed_20; +reg [`DWIDTH-1:0] b28_data_delayed_21; +reg [`DWIDTH-1:0] b28_data_delayed_22; +reg [`DWIDTH-1:0] b28_data_delayed_23; +reg [`DWIDTH-1:0] b28_data_delayed_24; +reg [`DWIDTH-1:0] b28_data_delayed_25; +reg [`DWIDTH-1:0] b28_data_delayed_26; +reg [`DWIDTH-1:0] b28_data_delayed_27; +reg [`DWIDTH-1:0] b28_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_1; +reg [`DWIDTH-1:0] b29_data_delayed_2; +reg [`DWIDTH-1:0] b29_data_delayed_3; +reg [`DWIDTH-1:0] b29_data_delayed_4; +reg [`DWIDTH-1:0] b29_data_delayed_5; +reg [`DWIDTH-1:0] b29_data_delayed_6; +reg [`DWIDTH-1:0] b29_data_delayed_7; +reg [`DWIDTH-1:0] b29_data_delayed_8; +reg [`DWIDTH-1:0] b29_data_delayed_9; +reg [`DWIDTH-1:0] b29_data_delayed_10; +reg [`DWIDTH-1:0] b29_data_delayed_11; +reg [`DWIDTH-1:0] b29_data_delayed_12; +reg [`DWIDTH-1:0] b29_data_delayed_13; +reg [`DWIDTH-1:0] b29_data_delayed_14; +reg [`DWIDTH-1:0] b29_data_delayed_15; +reg [`DWIDTH-1:0] b29_data_delayed_16; +reg [`DWIDTH-1:0] b29_data_delayed_17; +reg [`DWIDTH-1:0] b29_data_delayed_18; +reg [`DWIDTH-1:0] b29_data_delayed_19; +reg [`DWIDTH-1:0] b29_data_delayed_20; +reg [`DWIDTH-1:0] b29_data_delayed_21; +reg [`DWIDTH-1:0] b29_data_delayed_22; +reg [`DWIDTH-1:0] b29_data_delayed_23; +reg [`DWIDTH-1:0] b29_data_delayed_24; +reg [`DWIDTH-1:0] b29_data_delayed_25; +reg [`DWIDTH-1:0] b29_data_delayed_26; +reg [`DWIDTH-1:0] b29_data_delayed_27; +reg [`DWIDTH-1:0] b29_data_delayed_28; +reg [`DWIDTH-1:0] b29_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_1; +reg [`DWIDTH-1:0] b30_data_delayed_2; +reg [`DWIDTH-1:0] b30_data_delayed_3; +reg [`DWIDTH-1:0] b30_data_delayed_4; +reg [`DWIDTH-1:0] b30_data_delayed_5; +reg [`DWIDTH-1:0] b30_data_delayed_6; +reg [`DWIDTH-1:0] b30_data_delayed_7; +reg [`DWIDTH-1:0] b30_data_delayed_8; +reg [`DWIDTH-1:0] b30_data_delayed_9; +reg [`DWIDTH-1:0] b30_data_delayed_10; +reg [`DWIDTH-1:0] b30_data_delayed_11; +reg [`DWIDTH-1:0] b30_data_delayed_12; +reg [`DWIDTH-1:0] b30_data_delayed_13; +reg [`DWIDTH-1:0] b30_data_delayed_14; +reg [`DWIDTH-1:0] b30_data_delayed_15; +reg [`DWIDTH-1:0] b30_data_delayed_16; +reg [`DWIDTH-1:0] b30_data_delayed_17; +reg [`DWIDTH-1:0] b30_data_delayed_18; +reg [`DWIDTH-1:0] b30_data_delayed_19; +reg [`DWIDTH-1:0] b30_data_delayed_20; +reg [`DWIDTH-1:0] b30_data_delayed_21; +reg [`DWIDTH-1:0] b30_data_delayed_22; +reg [`DWIDTH-1:0] b30_data_delayed_23; +reg [`DWIDTH-1:0] b30_data_delayed_24; +reg [`DWIDTH-1:0] b30_data_delayed_25; +reg [`DWIDTH-1:0] b30_data_delayed_26; +reg [`DWIDTH-1:0] b30_data_delayed_27; +reg [`DWIDTH-1:0] b30_data_delayed_28; +reg [`DWIDTH-1:0] b30_data_delayed_29; +reg [`DWIDTH-1:0] b30_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_1; +reg [`DWIDTH-1:0] b31_data_delayed_2; +reg [`DWIDTH-1:0] b31_data_delayed_3; +reg [`DWIDTH-1:0] b31_data_delayed_4; +reg [`DWIDTH-1:0] b31_data_delayed_5; +reg [`DWIDTH-1:0] b31_data_delayed_6; +reg [`DWIDTH-1:0] b31_data_delayed_7; +reg [`DWIDTH-1:0] b31_data_delayed_8; +reg [`DWIDTH-1:0] b31_data_delayed_9; +reg [`DWIDTH-1:0] b31_data_delayed_10; +reg [`DWIDTH-1:0] b31_data_delayed_11; +reg [`DWIDTH-1:0] b31_data_delayed_12; +reg [`DWIDTH-1:0] b31_data_delayed_13; +reg [`DWIDTH-1:0] b31_data_delayed_14; +reg [`DWIDTH-1:0] b31_data_delayed_15; +reg [`DWIDTH-1:0] b31_data_delayed_16; +reg [`DWIDTH-1:0] b31_data_delayed_17; +reg [`DWIDTH-1:0] b31_data_delayed_18; +reg [`DWIDTH-1:0] b31_data_delayed_19; +reg [`DWIDTH-1:0] b31_data_delayed_20; +reg [`DWIDTH-1:0] b31_data_delayed_21; +reg [`DWIDTH-1:0] b31_data_delayed_22; +reg [`DWIDTH-1:0] b31_data_delayed_23; +reg [`DWIDTH-1:0] b31_data_delayed_24; +reg [`DWIDTH-1:0] b31_data_delayed_25; +reg [`DWIDTH-1:0] b31_data_delayed_26; +reg [`DWIDTH-1:0] b31_data_delayed_27; +reg [`DWIDTH-1:0] b31_data_delayed_28; +reg [`DWIDTH-1:0] b31_data_delayed_29; +reg [`DWIDTH-1:0] b31_data_delayed_30; +reg [`DWIDTH-1:0] b31_data_delayed_31; + + +always @(posedge clk) begin + if (reset || ~start_mat_mul || clk_cnt==0) begin + b1_data_delayed_1 <= 0; + b2_data_delayed_1 <= 0; + b2_data_delayed_2 <= 0; + b3_data_delayed_1 <= 0; + b3_data_delayed_2 <= 0; + b3_data_delayed_3 <= 0; + b4_data_delayed_1 <= 0; + b4_data_delayed_2 <= 0; + b4_data_delayed_3 <= 0; + b4_data_delayed_4 <= 0; + b5_data_delayed_1 <= 0; + b5_data_delayed_2 <= 0; + b5_data_delayed_3 <= 0; + b5_data_delayed_4 <= 0; + b5_data_delayed_5 <= 0; + b6_data_delayed_1 <= 0; + b6_data_delayed_2 <= 0; + b6_data_delayed_3 <= 0; + b6_data_delayed_4 <= 0; + b6_data_delayed_5 <= 0; + b6_data_delayed_6 <= 0; + b7_data_delayed_1 <= 0; + b7_data_delayed_2 <= 0; + b7_data_delayed_3 <= 0; + b7_data_delayed_4 <= 0; + b7_data_delayed_5 <= 0; + b7_data_delayed_6 <= 0; + b7_data_delayed_7 <= 0; + b8_data_delayed_1 <= 0; + b8_data_delayed_2 <= 0; + b8_data_delayed_3 <= 0; + b8_data_delayed_4 <= 0; + b8_data_delayed_5 <= 0; + b8_data_delayed_6 <= 0; + b8_data_delayed_7 <= 0; + b8_data_delayed_8 <= 0; + b9_data_delayed_1 <= 0; + b9_data_delayed_2 <= 0; + b9_data_delayed_3 <= 0; + b9_data_delayed_4 <= 0; + b9_data_delayed_5 <= 0; + b9_data_delayed_6 <= 0; + b9_data_delayed_7 <= 0; + b9_data_delayed_8 <= 0; + b9_data_delayed_9 <= 0; + b10_data_delayed_1 <= 0; + b10_data_delayed_2 <= 0; + b10_data_delayed_3 <= 0; + b10_data_delayed_4 <= 0; + b10_data_delayed_5 <= 0; + b10_data_delayed_6 <= 0; + b10_data_delayed_7 <= 0; + b10_data_delayed_8 <= 0; + b10_data_delayed_9 <= 0; + b10_data_delayed_10 <= 0; + b11_data_delayed_1 <= 0; + b11_data_delayed_2 <= 0; + b11_data_delayed_3 <= 0; + b11_data_delayed_4 <= 0; + b11_data_delayed_5 <= 0; + b11_data_delayed_6 <= 0; + b11_data_delayed_7 <= 0; + b11_data_delayed_8 <= 0; + b11_data_delayed_9 <= 0; + b11_data_delayed_10 <= 0; + b11_data_delayed_11 <= 0; + b12_data_delayed_1 <= 0; + b12_data_delayed_2 <= 0; + b12_data_delayed_3 <= 0; + b12_data_delayed_4 <= 0; + b12_data_delayed_5 <= 0; + b12_data_delayed_6 <= 0; + b12_data_delayed_7 <= 0; + b12_data_delayed_8 <= 0; + b12_data_delayed_9 <= 0; + b12_data_delayed_10 <= 0; + b12_data_delayed_11 <= 0; + b12_data_delayed_12 <= 0; + b13_data_delayed_1 <= 0; + b13_data_delayed_2 <= 0; + b13_data_delayed_3 <= 0; + b13_data_delayed_4 <= 0; + b13_data_delayed_5 <= 0; + b13_data_delayed_6 <= 0; + b13_data_delayed_7 <= 0; + b13_data_delayed_8 <= 0; + b13_data_delayed_9 <= 0; + b13_data_delayed_10 <= 0; + b13_data_delayed_11 <= 0; + b13_data_delayed_12 <= 0; + b13_data_delayed_13 <= 0; + b14_data_delayed_1 <= 0; + b14_data_delayed_2 <= 0; + b14_data_delayed_3 <= 0; + b14_data_delayed_4 <= 0; + b14_data_delayed_5 <= 0; + b14_data_delayed_6 <= 0; + b14_data_delayed_7 <= 0; + b14_data_delayed_8 <= 0; + b14_data_delayed_9 <= 0; + b14_data_delayed_10 <= 0; + b14_data_delayed_11 <= 0; + b14_data_delayed_12 <= 0; + b14_data_delayed_13 <= 0; + b14_data_delayed_14 <= 0; + b15_data_delayed_1 <= 0; + b15_data_delayed_2 <= 0; + b15_data_delayed_3 <= 0; + b15_data_delayed_4 <= 0; + b15_data_delayed_5 <= 0; + b15_data_delayed_6 <= 0; + b15_data_delayed_7 <= 0; + b15_data_delayed_8 <= 0; + b15_data_delayed_9 <= 0; + b15_data_delayed_10 <= 0; + b15_data_delayed_11 <= 0; + b15_data_delayed_12 <= 0; + b15_data_delayed_13 <= 0; + b15_data_delayed_14 <= 0; + b15_data_delayed_15 <= 0; + b16_data_delayed_1 <= 0; + b16_data_delayed_2 <= 0; + b16_data_delayed_3 <= 0; + b16_data_delayed_4 <= 0; + b16_data_delayed_5 <= 0; + b16_data_delayed_6 <= 0; + b16_data_delayed_7 <= 0; + b16_data_delayed_8 <= 0; + b16_data_delayed_9 <= 0; + b16_data_delayed_10 <= 0; + b16_data_delayed_11 <= 0; + b16_data_delayed_12 <= 0; + b16_data_delayed_13 <= 0; + b16_data_delayed_14 <= 0; + b16_data_delayed_15 <= 0; + b16_data_delayed_16 <= 0; + b17_data_delayed_1 <= 0; + b17_data_delayed_2 <= 0; + b17_data_delayed_3 <= 0; + b17_data_delayed_4 <= 0; + b17_data_delayed_5 <= 0; + b17_data_delayed_6 <= 0; + b17_data_delayed_7 <= 0; + b17_data_delayed_8 <= 0; + b17_data_delayed_9 <= 0; + b17_data_delayed_10 <= 0; + b17_data_delayed_11 <= 0; + b17_data_delayed_12 <= 0; + b17_data_delayed_13 <= 0; + b17_data_delayed_14 <= 0; + b17_data_delayed_15 <= 0; + b17_data_delayed_16 <= 0; + b17_data_delayed_17 <= 0; + b18_data_delayed_1 <= 0; + b18_data_delayed_2 <= 0; + b18_data_delayed_3 <= 0; + b18_data_delayed_4 <= 0; + b18_data_delayed_5 <= 0; + b18_data_delayed_6 <= 0; + b18_data_delayed_7 <= 0; + b18_data_delayed_8 <= 0; + b18_data_delayed_9 <= 0; + b18_data_delayed_10 <= 0; + b18_data_delayed_11 <= 0; + b18_data_delayed_12 <= 0; + b18_data_delayed_13 <= 0; + b18_data_delayed_14 <= 0; + b18_data_delayed_15 <= 0; + b18_data_delayed_16 <= 0; + b18_data_delayed_17 <= 0; + b18_data_delayed_18 <= 0; + b19_data_delayed_1 <= 0; + b19_data_delayed_2 <= 0; + b19_data_delayed_3 <= 0; + b19_data_delayed_4 <= 0; + b19_data_delayed_5 <= 0; + b19_data_delayed_6 <= 0; + b19_data_delayed_7 <= 0; + b19_data_delayed_8 <= 0; + b19_data_delayed_9 <= 0; + b19_data_delayed_10 <= 0; + b19_data_delayed_11 <= 0; + b19_data_delayed_12 <= 0; + b19_data_delayed_13 <= 0; + b19_data_delayed_14 <= 0; + b19_data_delayed_15 <= 0; + b19_data_delayed_16 <= 0; + b19_data_delayed_17 <= 0; + b19_data_delayed_18 <= 0; + b19_data_delayed_19 <= 0; + b20_data_delayed_1 <= 0; + b20_data_delayed_2 <= 0; + b20_data_delayed_3 <= 0; + b20_data_delayed_4 <= 0; + b20_data_delayed_5 <= 0; + b20_data_delayed_6 <= 0; + b20_data_delayed_7 <= 0; + b20_data_delayed_8 <= 0; + b20_data_delayed_9 <= 0; + b20_data_delayed_10 <= 0; + b20_data_delayed_11 <= 0; + b20_data_delayed_12 <= 0; + b20_data_delayed_13 <= 0; + b20_data_delayed_14 <= 0; + b20_data_delayed_15 <= 0; + b20_data_delayed_16 <= 0; + b20_data_delayed_17 <= 0; + b20_data_delayed_18 <= 0; + b20_data_delayed_19 <= 0; + b20_data_delayed_20 <= 0; + b21_data_delayed_1 <= 0; + b21_data_delayed_2 <= 0; + b21_data_delayed_3 <= 0; + b21_data_delayed_4 <= 0; + b21_data_delayed_5 <= 0; + b21_data_delayed_6 <= 0; + b21_data_delayed_7 <= 0; + b21_data_delayed_8 <= 0; + b21_data_delayed_9 <= 0; + b21_data_delayed_10 <= 0; + b21_data_delayed_11 <= 0; + b21_data_delayed_12 <= 0; + b21_data_delayed_13 <= 0; + b21_data_delayed_14 <= 0; + b21_data_delayed_15 <= 0; + b21_data_delayed_16 <= 0; + b21_data_delayed_17 <= 0; + b21_data_delayed_18 <= 0; + b21_data_delayed_19 <= 0; + b21_data_delayed_20 <= 0; + b21_data_delayed_21 <= 0; + b22_data_delayed_1 <= 0; + b22_data_delayed_2 <= 0; + b22_data_delayed_3 <= 0; + b22_data_delayed_4 <= 0; + b22_data_delayed_5 <= 0; + b22_data_delayed_6 <= 0; + b22_data_delayed_7 <= 0; + b22_data_delayed_8 <= 0; + b22_data_delayed_9 <= 0; + b22_data_delayed_10 <= 0; + b22_data_delayed_11 <= 0; + b22_data_delayed_12 <= 0; + b22_data_delayed_13 <= 0; + b22_data_delayed_14 <= 0; + b22_data_delayed_15 <= 0; + b22_data_delayed_16 <= 0; + b22_data_delayed_17 <= 0; + b22_data_delayed_18 <= 0; + b22_data_delayed_19 <= 0; + b22_data_delayed_20 <= 0; + b22_data_delayed_21 <= 0; + b22_data_delayed_22 <= 0; + b23_data_delayed_1 <= 0; + b23_data_delayed_2 <= 0; + b23_data_delayed_3 <= 0; + b23_data_delayed_4 <= 0; + b23_data_delayed_5 <= 0; + b23_data_delayed_6 <= 0; + b23_data_delayed_7 <= 0; + b23_data_delayed_8 <= 0; + b23_data_delayed_9 <= 0; + b23_data_delayed_10 <= 0; + b23_data_delayed_11 <= 0; + b23_data_delayed_12 <= 0; + b23_data_delayed_13 <= 0; + b23_data_delayed_14 <= 0; + b23_data_delayed_15 <= 0; + b23_data_delayed_16 <= 0; + b23_data_delayed_17 <= 0; + b23_data_delayed_18 <= 0; + b23_data_delayed_19 <= 0; + b23_data_delayed_20 <= 0; + b23_data_delayed_21 <= 0; + b23_data_delayed_22 <= 0; + b23_data_delayed_23 <= 0; + b24_data_delayed_1 <= 0; + b24_data_delayed_2 <= 0; + b24_data_delayed_3 <= 0; + b24_data_delayed_4 <= 0; + b24_data_delayed_5 <= 0; + b24_data_delayed_6 <= 0; + b24_data_delayed_7 <= 0; + b24_data_delayed_8 <= 0; + b24_data_delayed_9 <= 0; + b24_data_delayed_10 <= 0; + b24_data_delayed_11 <= 0; + b24_data_delayed_12 <= 0; + b24_data_delayed_13 <= 0; + b24_data_delayed_14 <= 0; + b24_data_delayed_15 <= 0; + b24_data_delayed_16 <= 0; + b24_data_delayed_17 <= 0; + b24_data_delayed_18 <= 0; + b24_data_delayed_19 <= 0; + b24_data_delayed_20 <= 0; + b24_data_delayed_21 <= 0; + b24_data_delayed_22 <= 0; + b24_data_delayed_23 <= 0; + b24_data_delayed_24 <= 0; + b25_data_delayed_1 <= 0; + b25_data_delayed_2 <= 0; + b25_data_delayed_3 <= 0; + b25_data_delayed_4 <= 0; + b25_data_delayed_5 <= 0; + b25_data_delayed_6 <= 0; + b25_data_delayed_7 <= 0; + b25_data_delayed_8 <= 0; + b25_data_delayed_9 <= 0; + b25_data_delayed_10 <= 0; + b25_data_delayed_11 <= 0; + b25_data_delayed_12 <= 0; + b25_data_delayed_13 <= 0; + b25_data_delayed_14 <= 0; + b25_data_delayed_15 <= 0; + b25_data_delayed_16 <= 0; + b25_data_delayed_17 <= 0; + b25_data_delayed_18 <= 0; + b25_data_delayed_19 <= 0; + b25_data_delayed_20 <= 0; + b25_data_delayed_21 <= 0; + b25_data_delayed_22 <= 0; + b25_data_delayed_23 <= 0; + b25_data_delayed_24 <= 0; + b25_data_delayed_25 <= 0; + b26_data_delayed_1 <= 0; + b26_data_delayed_2 <= 0; + b26_data_delayed_3 <= 0; + b26_data_delayed_4 <= 0; + b26_data_delayed_5 <= 0; + b26_data_delayed_6 <= 0; + b26_data_delayed_7 <= 0; + b26_data_delayed_8 <= 0; + b26_data_delayed_9 <= 0; + b26_data_delayed_10 <= 0; + b26_data_delayed_11 <= 0; + b26_data_delayed_12 <= 0; + b26_data_delayed_13 <= 0; + b26_data_delayed_14 <= 0; + b26_data_delayed_15 <= 0; + b26_data_delayed_16 <= 0; + b26_data_delayed_17 <= 0; + b26_data_delayed_18 <= 0; + b26_data_delayed_19 <= 0; + b26_data_delayed_20 <= 0; + b26_data_delayed_21 <= 0; + b26_data_delayed_22 <= 0; + b26_data_delayed_23 <= 0; + b26_data_delayed_24 <= 0; + b26_data_delayed_25 <= 0; + b26_data_delayed_26 <= 0; + b27_data_delayed_1 <= 0; + b27_data_delayed_2 <= 0; + b27_data_delayed_3 <= 0; + b27_data_delayed_4 <= 0; + b27_data_delayed_5 <= 0; + b27_data_delayed_6 <= 0; + b27_data_delayed_7 <= 0; + b27_data_delayed_8 <= 0; + b27_data_delayed_9 <= 0; + b27_data_delayed_10 <= 0; + b27_data_delayed_11 <= 0; + b27_data_delayed_12 <= 0; + b27_data_delayed_13 <= 0; + b27_data_delayed_14 <= 0; + b27_data_delayed_15 <= 0; + b27_data_delayed_16 <= 0; + b27_data_delayed_17 <= 0; + b27_data_delayed_18 <= 0; + b27_data_delayed_19 <= 0; + b27_data_delayed_20 <= 0; + b27_data_delayed_21 <= 0; + b27_data_delayed_22 <= 0; + b27_data_delayed_23 <= 0; + b27_data_delayed_24 <= 0; + b27_data_delayed_25 <= 0; + b27_data_delayed_26 <= 0; + b27_data_delayed_27 <= 0; + b28_data_delayed_1 <= 0; + b28_data_delayed_2 <= 0; + b28_data_delayed_3 <= 0; + b28_data_delayed_4 <= 0; + b28_data_delayed_5 <= 0; + b28_data_delayed_6 <= 0; + b28_data_delayed_7 <= 0; + b28_data_delayed_8 <= 0; + b28_data_delayed_9 <= 0; + b28_data_delayed_10 <= 0; + b28_data_delayed_11 <= 0; + b28_data_delayed_12 <= 0; + b28_data_delayed_13 <= 0; + b28_data_delayed_14 <= 0; + b28_data_delayed_15 <= 0; + b28_data_delayed_16 <= 0; + b28_data_delayed_17 <= 0; + b28_data_delayed_18 <= 0; + b28_data_delayed_19 <= 0; + b28_data_delayed_20 <= 0; + b28_data_delayed_21 <= 0; + b28_data_delayed_22 <= 0; + b28_data_delayed_23 <= 0; + b28_data_delayed_24 <= 0; + b28_data_delayed_25 <= 0; + b28_data_delayed_26 <= 0; + b28_data_delayed_27 <= 0; + b28_data_delayed_28 <= 0; + b29_data_delayed_1 <= 0; + b29_data_delayed_2 <= 0; + b29_data_delayed_3 <= 0; + b29_data_delayed_4 <= 0; + b29_data_delayed_5 <= 0; + b29_data_delayed_6 <= 0; + b29_data_delayed_7 <= 0; + b29_data_delayed_8 <= 0; + b29_data_delayed_9 <= 0; + b29_data_delayed_10 <= 0; + b29_data_delayed_11 <= 0; + b29_data_delayed_12 <= 0; + b29_data_delayed_13 <= 0; + b29_data_delayed_14 <= 0; + b29_data_delayed_15 <= 0; + b29_data_delayed_16 <= 0; + b29_data_delayed_17 <= 0; + b29_data_delayed_18 <= 0; + b29_data_delayed_19 <= 0; + b29_data_delayed_20 <= 0; + b29_data_delayed_21 <= 0; + b29_data_delayed_22 <= 0; + b29_data_delayed_23 <= 0; + b29_data_delayed_24 <= 0; + b29_data_delayed_25 <= 0; + b29_data_delayed_26 <= 0; + b29_data_delayed_27 <= 0; + b29_data_delayed_28 <= 0; + b29_data_delayed_29 <= 0; + b30_data_delayed_1 <= 0; + b30_data_delayed_2 <= 0; + b30_data_delayed_3 <= 0; + b30_data_delayed_4 <= 0; + b30_data_delayed_5 <= 0; + b30_data_delayed_6 <= 0; + b30_data_delayed_7 <= 0; + b30_data_delayed_8 <= 0; + b30_data_delayed_9 <= 0; + b30_data_delayed_10 <= 0; + b30_data_delayed_11 <= 0; + b30_data_delayed_12 <= 0; + b30_data_delayed_13 <= 0; + b30_data_delayed_14 <= 0; + b30_data_delayed_15 <= 0; + b30_data_delayed_16 <= 0; + b30_data_delayed_17 <= 0; + b30_data_delayed_18 <= 0; + b30_data_delayed_19 <= 0; + b30_data_delayed_20 <= 0; + b30_data_delayed_21 <= 0; + b30_data_delayed_22 <= 0; + b30_data_delayed_23 <= 0; + b30_data_delayed_24 <= 0; + b30_data_delayed_25 <= 0; + b30_data_delayed_26 <= 0; + b30_data_delayed_27 <= 0; + b30_data_delayed_28 <= 0; + b30_data_delayed_29 <= 0; + b30_data_delayed_30 <= 0; + b31_data_delayed_1 <= 0; + b31_data_delayed_2 <= 0; + b31_data_delayed_3 <= 0; + b31_data_delayed_4 <= 0; + b31_data_delayed_5 <= 0; + b31_data_delayed_6 <= 0; + b31_data_delayed_7 <= 0; + b31_data_delayed_8 <= 0; + b31_data_delayed_9 <= 0; + b31_data_delayed_10 <= 0; + b31_data_delayed_11 <= 0; + b31_data_delayed_12 <= 0; + b31_data_delayed_13 <= 0; + b31_data_delayed_14 <= 0; + b31_data_delayed_15 <= 0; + b31_data_delayed_16 <= 0; + b31_data_delayed_17 <= 0; + b31_data_delayed_18 <= 0; + b31_data_delayed_19 <= 0; + b31_data_delayed_20 <= 0; + b31_data_delayed_21 <= 0; + b31_data_delayed_22 <= 0; + b31_data_delayed_23 <= 0; + b31_data_delayed_24 <= 0; + b31_data_delayed_25 <= 0; + b31_data_delayed_26 <= 0; + b31_data_delayed_27 <= 0; + b31_data_delayed_28 <= 0; + b31_data_delayed_29 <= 0; + b31_data_delayed_30 <= 0; + b31_data_delayed_31 <= 0; + + end + else begin + b1_data_delayed_1 <= b1_data; + b2_data_delayed_1 <= b2_data; + b3_data_delayed_1 <= b3_data; + b4_data_delayed_1 <= b4_data; + b5_data_delayed_1 <= b5_data; + b6_data_delayed_1 <= b6_data; + b7_data_delayed_1 <= b7_data; + b8_data_delayed_1 <= b8_data; + b9_data_delayed_1 <= b9_data; + b10_data_delayed_1 <= b10_data; + b11_data_delayed_1 <= b11_data; + b12_data_delayed_1 <= b12_data; + b13_data_delayed_1 <= b13_data; + b14_data_delayed_1 <= b14_data; + b15_data_delayed_1 <= b15_data; + b16_data_delayed_1 <= b16_data; + b17_data_delayed_1 <= b17_data; + b18_data_delayed_1 <= b18_data; + b19_data_delayed_1 <= b19_data; + b20_data_delayed_1 <= b20_data; + b21_data_delayed_1 <= b21_data; + b22_data_delayed_1 <= b22_data; + b23_data_delayed_1 <= b23_data; + b24_data_delayed_1 <= b24_data; + b25_data_delayed_1 <= b25_data; + b26_data_delayed_1 <= b26_data; + b27_data_delayed_1 <= b27_data; + b28_data_delayed_1 <= b28_data; + b29_data_delayed_1 <= b29_data; + b30_data_delayed_1 <= b30_data; + b31_data_delayed_1 <= b31_data; + b2_data_delayed_2 <= b2_data_delayed_1; + b3_data_delayed_2 <= b3_data_delayed_1; + b3_data_delayed_3 <= b3_data_delayed_2; + b4_data_delayed_2 <= b4_data_delayed_1; + b4_data_delayed_3 <= b4_data_delayed_2; + b4_data_delayed_4 <= b4_data_delayed_3; + b5_data_delayed_2 <= b5_data_delayed_1; + b5_data_delayed_3 <= b5_data_delayed_2; + b5_data_delayed_4 <= b5_data_delayed_3; + b5_data_delayed_5 <= b5_data_delayed_4; + b6_data_delayed_2 <= b6_data_delayed_1; + b6_data_delayed_3 <= b6_data_delayed_2; + b6_data_delayed_4 <= b6_data_delayed_3; + b6_data_delayed_5 <= b6_data_delayed_4; + b6_data_delayed_6 <= b6_data_delayed_5; + b7_data_delayed_2 <= b7_data_delayed_1; + b7_data_delayed_3 <= b7_data_delayed_2; + b7_data_delayed_4 <= b7_data_delayed_3; + b7_data_delayed_5 <= b7_data_delayed_4; + b7_data_delayed_6 <= b7_data_delayed_5; + b7_data_delayed_7 <= b7_data_delayed_6; + b8_data_delayed_2 <= b8_data_delayed_1; + b8_data_delayed_3 <= b8_data_delayed_2; + b8_data_delayed_4 <= b8_data_delayed_3; + b8_data_delayed_5 <= b8_data_delayed_4; + b8_data_delayed_6 <= b8_data_delayed_5; + b8_data_delayed_7 <= b8_data_delayed_6; + b8_data_delayed_8 <= b8_data_delayed_7; + b9_data_delayed_2 <= b9_data_delayed_1; + b9_data_delayed_3 <= b9_data_delayed_2; + b9_data_delayed_4 <= b9_data_delayed_3; + b9_data_delayed_5 <= b9_data_delayed_4; + b9_data_delayed_6 <= b9_data_delayed_5; + b9_data_delayed_7 <= b9_data_delayed_6; + b9_data_delayed_8 <= b9_data_delayed_7; + b9_data_delayed_9 <= b9_data_delayed_8; + b10_data_delayed_2 <= b10_data_delayed_1; + b10_data_delayed_3 <= b10_data_delayed_2; + b10_data_delayed_4 <= b10_data_delayed_3; + b10_data_delayed_5 <= b10_data_delayed_4; + b10_data_delayed_6 <= b10_data_delayed_5; + b10_data_delayed_7 <= b10_data_delayed_6; + b10_data_delayed_8 <= b10_data_delayed_7; + b10_data_delayed_9 <= b10_data_delayed_8; + b10_data_delayed_10 <= b10_data_delayed_9; + b11_data_delayed_2 <= b11_data_delayed_1; + b11_data_delayed_3 <= b11_data_delayed_2; + b11_data_delayed_4 <= b11_data_delayed_3; + b11_data_delayed_5 <= b11_data_delayed_4; + b11_data_delayed_6 <= b11_data_delayed_5; + b11_data_delayed_7 <= b11_data_delayed_6; + b11_data_delayed_8 <= b11_data_delayed_7; + b11_data_delayed_9 <= b11_data_delayed_8; + b11_data_delayed_10 <= b11_data_delayed_9; + b11_data_delayed_11 <= b11_data_delayed_10; + b12_data_delayed_2 <= b12_data_delayed_1; + b12_data_delayed_3 <= b12_data_delayed_2; + b12_data_delayed_4 <= b12_data_delayed_3; + b12_data_delayed_5 <= b12_data_delayed_4; + b12_data_delayed_6 <= b12_data_delayed_5; + b12_data_delayed_7 <= b12_data_delayed_6; + b12_data_delayed_8 <= b12_data_delayed_7; + b12_data_delayed_9 <= b12_data_delayed_8; + b12_data_delayed_10 <= b12_data_delayed_9; + b12_data_delayed_11 <= b12_data_delayed_10; + b12_data_delayed_12 <= b12_data_delayed_11; + b13_data_delayed_2 <= b13_data_delayed_1; + b13_data_delayed_3 <= b13_data_delayed_2; + b13_data_delayed_4 <= b13_data_delayed_3; + b13_data_delayed_5 <= b13_data_delayed_4; + b13_data_delayed_6 <= b13_data_delayed_5; + b13_data_delayed_7 <= b13_data_delayed_6; + b13_data_delayed_8 <= b13_data_delayed_7; + b13_data_delayed_9 <= b13_data_delayed_8; + b13_data_delayed_10 <= b13_data_delayed_9; + b13_data_delayed_11 <= b13_data_delayed_10; + b13_data_delayed_12 <= b13_data_delayed_11; + b13_data_delayed_13 <= b13_data_delayed_12; + b14_data_delayed_2 <= b14_data_delayed_1; + b14_data_delayed_3 <= b14_data_delayed_2; + b14_data_delayed_4 <= b14_data_delayed_3; + b14_data_delayed_5 <= b14_data_delayed_4; + b14_data_delayed_6 <= b14_data_delayed_5; + b14_data_delayed_7 <= b14_data_delayed_6; + b14_data_delayed_8 <= b14_data_delayed_7; + b14_data_delayed_9 <= b14_data_delayed_8; + b14_data_delayed_10 <= b14_data_delayed_9; + b14_data_delayed_11 <= b14_data_delayed_10; + b14_data_delayed_12 <= b14_data_delayed_11; + b14_data_delayed_13 <= b14_data_delayed_12; + b14_data_delayed_14 <= b14_data_delayed_13; + b15_data_delayed_2 <= b15_data_delayed_1; + b15_data_delayed_3 <= b15_data_delayed_2; + b15_data_delayed_4 <= b15_data_delayed_3; + b15_data_delayed_5 <= b15_data_delayed_4; + b15_data_delayed_6 <= b15_data_delayed_5; + b15_data_delayed_7 <= b15_data_delayed_6; + b15_data_delayed_8 <= b15_data_delayed_7; + b15_data_delayed_9 <= b15_data_delayed_8; + b15_data_delayed_10 <= b15_data_delayed_9; + b15_data_delayed_11 <= b15_data_delayed_10; + b15_data_delayed_12 <= b15_data_delayed_11; + b15_data_delayed_13 <= b15_data_delayed_12; + b15_data_delayed_14 <= b15_data_delayed_13; + b15_data_delayed_15 <= b15_data_delayed_14; + b16_data_delayed_2 <= b16_data_delayed_1; + b16_data_delayed_3 <= b16_data_delayed_2; + b16_data_delayed_4 <= b16_data_delayed_3; + b16_data_delayed_5 <= b16_data_delayed_4; + b16_data_delayed_6 <= b16_data_delayed_5; + b16_data_delayed_7 <= b16_data_delayed_6; + b16_data_delayed_8 <= b16_data_delayed_7; + b16_data_delayed_9 <= b16_data_delayed_8; + b16_data_delayed_10 <= b16_data_delayed_9; + b16_data_delayed_11 <= b16_data_delayed_10; + b16_data_delayed_12 <= b16_data_delayed_11; + b16_data_delayed_13 <= b16_data_delayed_12; + b16_data_delayed_14 <= b16_data_delayed_13; + b16_data_delayed_15 <= b16_data_delayed_14; + b16_data_delayed_16 <= b16_data_delayed_15; + b17_data_delayed_2 <= b17_data_delayed_1; + b17_data_delayed_3 <= b17_data_delayed_2; + b17_data_delayed_4 <= b17_data_delayed_3; + b17_data_delayed_5 <= b17_data_delayed_4; + b17_data_delayed_6 <= b17_data_delayed_5; + b17_data_delayed_7 <= b17_data_delayed_6; + b17_data_delayed_8 <= b17_data_delayed_7; + b17_data_delayed_9 <= b17_data_delayed_8; + b17_data_delayed_10 <= b17_data_delayed_9; + b17_data_delayed_11 <= b17_data_delayed_10; + b17_data_delayed_12 <= b17_data_delayed_11; + b17_data_delayed_13 <= b17_data_delayed_12; + b17_data_delayed_14 <= b17_data_delayed_13; + b17_data_delayed_15 <= b17_data_delayed_14; + b17_data_delayed_16 <= b17_data_delayed_15; + b17_data_delayed_17 <= b17_data_delayed_16; + b18_data_delayed_2 <= b18_data_delayed_1; + b18_data_delayed_3 <= b18_data_delayed_2; + b18_data_delayed_4 <= b18_data_delayed_3; + b18_data_delayed_5 <= b18_data_delayed_4; + b18_data_delayed_6 <= b18_data_delayed_5; + b18_data_delayed_7 <= b18_data_delayed_6; + b18_data_delayed_8 <= b18_data_delayed_7; + b18_data_delayed_9 <= b18_data_delayed_8; + b18_data_delayed_10 <= b18_data_delayed_9; + b18_data_delayed_11 <= b18_data_delayed_10; + b18_data_delayed_12 <= b18_data_delayed_11; + b18_data_delayed_13 <= b18_data_delayed_12; + b18_data_delayed_14 <= b18_data_delayed_13; + b18_data_delayed_15 <= b18_data_delayed_14; + b18_data_delayed_16 <= b18_data_delayed_15; + b18_data_delayed_17 <= b18_data_delayed_16; + b18_data_delayed_18 <= b18_data_delayed_17; + b19_data_delayed_2 <= b19_data_delayed_1; + b19_data_delayed_3 <= b19_data_delayed_2; + b19_data_delayed_4 <= b19_data_delayed_3; + b19_data_delayed_5 <= b19_data_delayed_4; + b19_data_delayed_6 <= b19_data_delayed_5; + b19_data_delayed_7 <= b19_data_delayed_6; + b19_data_delayed_8 <= b19_data_delayed_7; + b19_data_delayed_9 <= b19_data_delayed_8; + b19_data_delayed_10 <= b19_data_delayed_9; + b19_data_delayed_11 <= b19_data_delayed_10; + b19_data_delayed_12 <= b19_data_delayed_11; + b19_data_delayed_13 <= b19_data_delayed_12; + b19_data_delayed_14 <= b19_data_delayed_13; + b19_data_delayed_15 <= b19_data_delayed_14; + b19_data_delayed_16 <= b19_data_delayed_15; + b19_data_delayed_17 <= b19_data_delayed_16; + b19_data_delayed_18 <= b19_data_delayed_17; + b19_data_delayed_19 <= b19_data_delayed_18; + b20_data_delayed_2 <= b20_data_delayed_1; + b20_data_delayed_3 <= b20_data_delayed_2; + b20_data_delayed_4 <= b20_data_delayed_3; + b20_data_delayed_5 <= b20_data_delayed_4; + b20_data_delayed_6 <= b20_data_delayed_5; + b20_data_delayed_7 <= b20_data_delayed_6; + b20_data_delayed_8 <= b20_data_delayed_7; + b20_data_delayed_9 <= b20_data_delayed_8; + b20_data_delayed_10 <= b20_data_delayed_9; + b20_data_delayed_11 <= b20_data_delayed_10; + b20_data_delayed_12 <= b20_data_delayed_11; + b20_data_delayed_13 <= b20_data_delayed_12; + b20_data_delayed_14 <= b20_data_delayed_13; + b20_data_delayed_15 <= b20_data_delayed_14; + b20_data_delayed_16 <= b20_data_delayed_15; + b20_data_delayed_17 <= b20_data_delayed_16; + b20_data_delayed_18 <= b20_data_delayed_17; + b20_data_delayed_19 <= b20_data_delayed_18; + b20_data_delayed_20 <= b20_data_delayed_19; + b21_data_delayed_2 <= b21_data_delayed_1; + b21_data_delayed_3 <= b21_data_delayed_2; + b21_data_delayed_4 <= b21_data_delayed_3; + b21_data_delayed_5 <= b21_data_delayed_4; + b21_data_delayed_6 <= b21_data_delayed_5; + b21_data_delayed_7 <= b21_data_delayed_6; + b21_data_delayed_8 <= b21_data_delayed_7; + b21_data_delayed_9 <= b21_data_delayed_8; + b21_data_delayed_10 <= b21_data_delayed_9; + b21_data_delayed_11 <= b21_data_delayed_10; + b21_data_delayed_12 <= b21_data_delayed_11; + b21_data_delayed_13 <= b21_data_delayed_12; + b21_data_delayed_14 <= b21_data_delayed_13; + b21_data_delayed_15 <= b21_data_delayed_14; + b21_data_delayed_16 <= b21_data_delayed_15; + b21_data_delayed_17 <= b21_data_delayed_16; + b21_data_delayed_18 <= b21_data_delayed_17; + b21_data_delayed_19 <= b21_data_delayed_18; + b21_data_delayed_20 <= b21_data_delayed_19; + b21_data_delayed_21 <= b21_data_delayed_20; + b22_data_delayed_2 <= b22_data_delayed_1; + b22_data_delayed_3 <= b22_data_delayed_2; + b22_data_delayed_4 <= b22_data_delayed_3; + b22_data_delayed_5 <= b22_data_delayed_4; + b22_data_delayed_6 <= b22_data_delayed_5; + b22_data_delayed_7 <= b22_data_delayed_6; + b22_data_delayed_8 <= b22_data_delayed_7; + b22_data_delayed_9 <= b22_data_delayed_8; + b22_data_delayed_10 <= b22_data_delayed_9; + b22_data_delayed_11 <= b22_data_delayed_10; + b22_data_delayed_12 <= b22_data_delayed_11; + b22_data_delayed_13 <= b22_data_delayed_12; + b22_data_delayed_14 <= b22_data_delayed_13; + b22_data_delayed_15 <= b22_data_delayed_14; + b22_data_delayed_16 <= b22_data_delayed_15; + b22_data_delayed_17 <= b22_data_delayed_16; + b22_data_delayed_18 <= b22_data_delayed_17; + b22_data_delayed_19 <= b22_data_delayed_18; + b22_data_delayed_20 <= b22_data_delayed_19; + b22_data_delayed_21 <= b22_data_delayed_20; + b22_data_delayed_22 <= b22_data_delayed_21; + b23_data_delayed_2 <= b23_data_delayed_1; + b23_data_delayed_3 <= b23_data_delayed_2; + b23_data_delayed_4 <= b23_data_delayed_3; + b23_data_delayed_5 <= b23_data_delayed_4; + b23_data_delayed_6 <= b23_data_delayed_5; + b23_data_delayed_7 <= b23_data_delayed_6; + b23_data_delayed_8 <= b23_data_delayed_7; + b23_data_delayed_9 <= b23_data_delayed_8; + b23_data_delayed_10 <= b23_data_delayed_9; + b23_data_delayed_11 <= b23_data_delayed_10; + b23_data_delayed_12 <= b23_data_delayed_11; + b23_data_delayed_13 <= b23_data_delayed_12; + b23_data_delayed_14 <= b23_data_delayed_13; + b23_data_delayed_15 <= b23_data_delayed_14; + b23_data_delayed_16 <= b23_data_delayed_15; + b23_data_delayed_17 <= b23_data_delayed_16; + b23_data_delayed_18 <= b23_data_delayed_17; + b23_data_delayed_19 <= b23_data_delayed_18; + b23_data_delayed_20 <= b23_data_delayed_19; + b23_data_delayed_21 <= b23_data_delayed_20; + b23_data_delayed_22 <= b23_data_delayed_21; + b23_data_delayed_23 <= b23_data_delayed_22; + b24_data_delayed_2 <= b24_data_delayed_1; + b24_data_delayed_3 <= b24_data_delayed_2; + b24_data_delayed_4 <= b24_data_delayed_3; + b24_data_delayed_5 <= b24_data_delayed_4; + b24_data_delayed_6 <= b24_data_delayed_5; + b24_data_delayed_7 <= b24_data_delayed_6; + b24_data_delayed_8 <= b24_data_delayed_7; + b24_data_delayed_9 <= b24_data_delayed_8; + b24_data_delayed_10 <= b24_data_delayed_9; + b24_data_delayed_11 <= b24_data_delayed_10; + b24_data_delayed_12 <= b24_data_delayed_11; + b24_data_delayed_13 <= b24_data_delayed_12; + b24_data_delayed_14 <= b24_data_delayed_13; + b24_data_delayed_15 <= b24_data_delayed_14; + b24_data_delayed_16 <= b24_data_delayed_15; + b24_data_delayed_17 <= b24_data_delayed_16; + b24_data_delayed_18 <= b24_data_delayed_17; + b24_data_delayed_19 <= b24_data_delayed_18; + b24_data_delayed_20 <= b24_data_delayed_19; + b24_data_delayed_21 <= b24_data_delayed_20; + b24_data_delayed_22 <= b24_data_delayed_21; + b24_data_delayed_23 <= b24_data_delayed_22; + b24_data_delayed_24 <= b24_data_delayed_23; + b25_data_delayed_2 <= b25_data_delayed_1; + b25_data_delayed_3 <= b25_data_delayed_2; + b25_data_delayed_4 <= b25_data_delayed_3; + b25_data_delayed_5 <= b25_data_delayed_4; + b25_data_delayed_6 <= b25_data_delayed_5; + b25_data_delayed_7 <= b25_data_delayed_6; + b25_data_delayed_8 <= b25_data_delayed_7; + b25_data_delayed_9 <= b25_data_delayed_8; + b25_data_delayed_10 <= b25_data_delayed_9; + b25_data_delayed_11 <= b25_data_delayed_10; + b25_data_delayed_12 <= b25_data_delayed_11; + b25_data_delayed_13 <= b25_data_delayed_12; + b25_data_delayed_14 <= b25_data_delayed_13; + b25_data_delayed_15 <= b25_data_delayed_14; + b25_data_delayed_16 <= b25_data_delayed_15; + b25_data_delayed_17 <= b25_data_delayed_16; + b25_data_delayed_18 <= b25_data_delayed_17; + b25_data_delayed_19 <= b25_data_delayed_18; + b25_data_delayed_20 <= b25_data_delayed_19; + b25_data_delayed_21 <= b25_data_delayed_20; + b25_data_delayed_22 <= b25_data_delayed_21; + b25_data_delayed_23 <= b25_data_delayed_22; + b25_data_delayed_24 <= b25_data_delayed_23; + b25_data_delayed_25 <= b25_data_delayed_24; + b26_data_delayed_2 <= b26_data_delayed_1; + b26_data_delayed_3 <= b26_data_delayed_2; + b26_data_delayed_4 <= b26_data_delayed_3; + b26_data_delayed_5 <= b26_data_delayed_4; + b26_data_delayed_6 <= b26_data_delayed_5; + b26_data_delayed_7 <= b26_data_delayed_6; + b26_data_delayed_8 <= b26_data_delayed_7; + b26_data_delayed_9 <= b26_data_delayed_8; + b26_data_delayed_10 <= b26_data_delayed_9; + b26_data_delayed_11 <= b26_data_delayed_10; + b26_data_delayed_12 <= b26_data_delayed_11; + b26_data_delayed_13 <= b26_data_delayed_12; + b26_data_delayed_14 <= b26_data_delayed_13; + b26_data_delayed_15 <= b26_data_delayed_14; + b26_data_delayed_16 <= b26_data_delayed_15; + b26_data_delayed_17 <= b26_data_delayed_16; + b26_data_delayed_18 <= b26_data_delayed_17; + b26_data_delayed_19 <= b26_data_delayed_18; + b26_data_delayed_20 <= b26_data_delayed_19; + b26_data_delayed_21 <= b26_data_delayed_20; + b26_data_delayed_22 <= b26_data_delayed_21; + b26_data_delayed_23 <= b26_data_delayed_22; + b26_data_delayed_24 <= b26_data_delayed_23; + b26_data_delayed_25 <= b26_data_delayed_24; + b26_data_delayed_26 <= b26_data_delayed_25; + b27_data_delayed_2 <= b27_data_delayed_1; + b27_data_delayed_3 <= b27_data_delayed_2; + b27_data_delayed_4 <= b27_data_delayed_3; + b27_data_delayed_5 <= b27_data_delayed_4; + b27_data_delayed_6 <= b27_data_delayed_5; + b27_data_delayed_7 <= b27_data_delayed_6; + b27_data_delayed_8 <= b27_data_delayed_7; + b27_data_delayed_9 <= b27_data_delayed_8; + b27_data_delayed_10 <= b27_data_delayed_9; + b27_data_delayed_11 <= b27_data_delayed_10; + b27_data_delayed_12 <= b27_data_delayed_11; + b27_data_delayed_13 <= b27_data_delayed_12; + b27_data_delayed_14 <= b27_data_delayed_13; + b27_data_delayed_15 <= b27_data_delayed_14; + b27_data_delayed_16 <= b27_data_delayed_15; + b27_data_delayed_17 <= b27_data_delayed_16; + b27_data_delayed_18 <= b27_data_delayed_17; + b27_data_delayed_19 <= b27_data_delayed_18; + b27_data_delayed_20 <= b27_data_delayed_19; + b27_data_delayed_21 <= b27_data_delayed_20; + b27_data_delayed_22 <= b27_data_delayed_21; + b27_data_delayed_23 <= b27_data_delayed_22; + b27_data_delayed_24 <= b27_data_delayed_23; + b27_data_delayed_25 <= b27_data_delayed_24; + b27_data_delayed_26 <= b27_data_delayed_25; + b27_data_delayed_27 <= b27_data_delayed_26; + b28_data_delayed_2 <= b28_data_delayed_1; + b28_data_delayed_3 <= b28_data_delayed_2; + b28_data_delayed_4 <= b28_data_delayed_3; + b28_data_delayed_5 <= b28_data_delayed_4; + b28_data_delayed_6 <= b28_data_delayed_5; + b28_data_delayed_7 <= b28_data_delayed_6; + b28_data_delayed_8 <= b28_data_delayed_7; + b28_data_delayed_9 <= b28_data_delayed_8; + b28_data_delayed_10 <= b28_data_delayed_9; + b28_data_delayed_11 <= b28_data_delayed_10; + b28_data_delayed_12 <= b28_data_delayed_11; + b28_data_delayed_13 <= b28_data_delayed_12; + b28_data_delayed_14 <= b28_data_delayed_13; + b28_data_delayed_15 <= b28_data_delayed_14; + b28_data_delayed_16 <= b28_data_delayed_15; + b28_data_delayed_17 <= b28_data_delayed_16; + b28_data_delayed_18 <= b28_data_delayed_17; + b28_data_delayed_19 <= b28_data_delayed_18; + b28_data_delayed_20 <= b28_data_delayed_19; + b28_data_delayed_21 <= b28_data_delayed_20; + b28_data_delayed_22 <= b28_data_delayed_21; + b28_data_delayed_23 <= b28_data_delayed_22; + b28_data_delayed_24 <= b28_data_delayed_23; + b28_data_delayed_25 <= b28_data_delayed_24; + b28_data_delayed_26 <= b28_data_delayed_25; + b28_data_delayed_27 <= b28_data_delayed_26; + b28_data_delayed_28 <= b28_data_delayed_27; + b29_data_delayed_2 <= b29_data_delayed_1; + b29_data_delayed_3 <= b29_data_delayed_2; + b29_data_delayed_4 <= b29_data_delayed_3; + b29_data_delayed_5 <= b29_data_delayed_4; + b29_data_delayed_6 <= b29_data_delayed_5; + b29_data_delayed_7 <= b29_data_delayed_6; + b29_data_delayed_8 <= b29_data_delayed_7; + b29_data_delayed_9 <= b29_data_delayed_8; + b29_data_delayed_10 <= b29_data_delayed_9; + b29_data_delayed_11 <= b29_data_delayed_10; + b29_data_delayed_12 <= b29_data_delayed_11; + b29_data_delayed_13 <= b29_data_delayed_12; + b29_data_delayed_14 <= b29_data_delayed_13; + b29_data_delayed_15 <= b29_data_delayed_14; + b29_data_delayed_16 <= b29_data_delayed_15; + b29_data_delayed_17 <= b29_data_delayed_16; + b29_data_delayed_18 <= b29_data_delayed_17; + b29_data_delayed_19 <= b29_data_delayed_18; + b29_data_delayed_20 <= b29_data_delayed_19; + b29_data_delayed_21 <= b29_data_delayed_20; + b29_data_delayed_22 <= b29_data_delayed_21; + b29_data_delayed_23 <= b29_data_delayed_22; + b29_data_delayed_24 <= b29_data_delayed_23; + b29_data_delayed_25 <= b29_data_delayed_24; + b29_data_delayed_26 <= b29_data_delayed_25; + b29_data_delayed_27 <= b29_data_delayed_26; + b29_data_delayed_28 <= b29_data_delayed_27; + b29_data_delayed_29 <= b29_data_delayed_28; + b30_data_delayed_2 <= b30_data_delayed_1; + b30_data_delayed_3 <= b30_data_delayed_2; + b30_data_delayed_4 <= b30_data_delayed_3; + b30_data_delayed_5 <= b30_data_delayed_4; + b30_data_delayed_6 <= b30_data_delayed_5; + b30_data_delayed_7 <= b30_data_delayed_6; + b30_data_delayed_8 <= b30_data_delayed_7; + b30_data_delayed_9 <= b30_data_delayed_8; + b30_data_delayed_10 <= b30_data_delayed_9; + b30_data_delayed_11 <= b30_data_delayed_10; + b30_data_delayed_12 <= b30_data_delayed_11; + b30_data_delayed_13 <= b30_data_delayed_12; + b30_data_delayed_14 <= b30_data_delayed_13; + b30_data_delayed_15 <= b30_data_delayed_14; + b30_data_delayed_16 <= b30_data_delayed_15; + b30_data_delayed_17 <= b30_data_delayed_16; + b30_data_delayed_18 <= b30_data_delayed_17; + b30_data_delayed_19 <= b30_data_delayed_18; + b30_data_delayed_20 <= b30_data_delayed_19; + b30_data_delayed_21 <= b30_data_delayed_20; + b30_data_delayed_22 <= b30_data_delayed_21; + b30_data_delayed_23 <= b30_data_delayed_22; + b30_data_delayed_24 <= b30_data_delayed_23; + b30_data_delayed_25 <= b30_data_delayed_24; + b30_data_delayed_26 <= b30_data_delayed_25; + b30_data_delayed_27 <= b30_data_delayed_26; + b30_data_delayed_28 <= b30_data_delayed_27; + b30_data_delayed_29 <= b30_data_delayed_28; + b30_data_delayed_30 <= b30_data_delayed_29; + b31_data_delayed_2 <= b31_data_delayed_1; + b31_data_delayed_3 <= b31_data_delayed_2; + b31_data_delayed_4 <= b31_data_delayed_3; + b31_data_delayed_5 <= b31_data_delayed_4; + b31_data_delayed_6 <= b31_data_delayed_5; + b31_data_delayed_7 <= b31_data_delayed_6; + b31_data_delayed_8 <= b31_data_delayed_7; + b31_data_delayed_9 <= b31_data_delayed_8; + b31_data_delayed_10 <= b31_data_delayed_9; + b31_data_delayed_11 <= b31_data_delayed_10; + b31_data_delayed_12 <= b31_data_delayed_11; + b31_data_delayed_13 <= b31_data_delayed_12; + b31_data_delayed_14 <= b31_data_delayed_13; + b31_data_delayed_15 <= b31_data_delayed_14; + b31_data_delayed_16 <= b31_data_delayed_15; + b31_data_delayed_17 <= b31_data_delayed_16; + b31_data_delayed_18 <= b31_data_delayed_17; + b31_data_delayed_19 <= b31_data_delayed_18; + b31_data_delayed_20 <= b31_data_delayed_19; + b31_data_delayed_21 <= b31_data_delayed_20; + b31_data_delayed_22 <= b31_data_delayed_21; + b31_data_delayed_23 <= b31_data_delayed_22; + b31_data_delayed_24 <= b31_data_delayed_23; + b31_data_delayed_25 <= b31_data_delayed_24; + b31_data_delayed_26 <= b31_data_delayed_25; + b31_data_delayed_27 <= b31_data_delayed_26; + b31_data_delayed_28 <= b31_data_delayed_27; + b31_data_delayed_29 <= b31_data_delayed_28; + b31_data_delayed_30 <= b31_data_delayed_29; + b31_data_delayed_31 <= b31_data_delayed_30; + + end +end +endmodule + + +////////////////////////////////////////////////////////////////////////// +// Systolically connected PEs +////////////////////////////////////////////////////////////////////////// +module systolic_pe_matrix( +clk, +reset, +pe_reset, +a0, +a1, +a2, +a3, +a4, +a5, +a6, +a7, +a8, +a9, +a10, +a11, +a12, +a13, +a14, +a15, +a16, +a17, +a18, +a19, +a20, +a21, +a22, +a23, +a24, +a25, +a26, +a27, +a28, +a29, +a30, +a31, +b0, +b1, +b2, +b3, +b4, +b5, +b6, +b7, +b8, +b9, +b10, +b11, +b12, +b13, +b14, +b15, +b16, +b17, +b18, +b19, +b20, +b21, +b22, +b23, +b24, +b25, +b26, +b27, +b28, +b29, +b30, +b31, +matrixC0_0, +matrixC0_1, +matrixC0_2, +matrixC0_3, +matrixC0_4, +matrixC0_5, +matrixC0_6, +matrixC0_7, +matrixC0_8, +matrixC0_9, +matrixC0_10, +matrixC0_11, +matrixC0_12, +matrixC0_13, +matrixC0_14, +matrixC0_15, +matrixC0_16, +matrixC0_17, +matrixC0_18, +matrixC0_19, +matrixC0_20, +matrixC0_21, +matrixC0_22, +matrixC0_23, +matrixC0_24, +matrixC0_25, +matrixC0_26, +matrixC0_27, +matrixC0_28, +matrixC0_29, +matrixC0_30, +matrixC0_31, +matrixC1_0, +matrixC1_1, +matrixC1_2, +matrixC1_3, +matrixC1_4, +matrixC1_5, +matrixC1_6, +matrixC1_7, +matrixC1_8, +matrixC1_9, +matrixC1_10, +matrixC1_11, +matrixC1_12, +matrixC1_13, +matrixC1_14, +matrixC1_15, +matrixC1_16, +matrixC1_17, +matrixC1_18, +matrixC1_19, +matrixC1_20, +matrixC1_21, +matrixC1_22, +matrixC1_23, +matrixC1_24, +matrixC1_25, +matrixC1_26, +matrixC1_27, +matrixC1_28, +matrixC1_29, +matrixC1_30, +matrixC1_31, +matrixC2_0, +matrixC2_1, +matrixC2_2, +matrixC2_3, +matrixC2_4, +matrixC2_5, +matrixC2_6, +matrixC2_7, +matrixC2_8, +matrixC2_9, +matrixC2_10, +matrixC2_11, +matrixC2_12, +matrixC2_13, +matrixC2_14, +matrixC2_15, +matrixC2_16, +matrixC2_17, +matrixC2_18, +matrixC2_19, +matrixC2_20, +matrixC2_21, +matrixC2_22, +matrixC2_23, +matrixC2_24, +matrixC2_25, +matrixC2_26, +matrixC2_27, +matrixC2_28, +matrixC2_29, +matrixC2_30, +matrixC2_31, +matrixC3_0, +matrixC3_1, +matrixC3_2, +matrixC3_3, +matrixC3_4, +matrixC3_5, +matrixC3_6, +matrixC3_7, +matrixC3_8, +matrixC3_9, +matrixC3_10, +matrixC3_11, +matrixC3_12, +matrixC3_13, +matrixC3_14, +matrixC3_15, +matrixC3_16, +matrixC3_17, +matrixC3_18, +matrixC3_19, +matrixC3_20, +matrixC3_21, +matrixC3_22, +matrixC3_23, +matrixC3_24, +matrixC3_25, +matrixC3_26, +matrixC3_27, +matrixC3_28, +matrixC3_29, +matrixC3_30, +matrixC3_31, +matrixC4_0, +matrixC4_1, +matrixC4_2, +matrixC4_3, +matrixC4_4, +matrixC4_5, +matrixC4_6, +matrixC4_7, +matrixC4_8, +matrixC4_9, +matrixC4_10, +matrixC4_11, +matrixC4_12, +matrixC4_13, +matrixC4_14, +matrixC4_15, +matrixC4_16, +matrixC4_17, +matrixC4_18, +matrixC4_19, +matrixC4_20, +matrixC4_21, +matrixC4_22, +matrixC4_23, +matrixC4_24, +matrixC4_25, +matrixC4_26, +matrixC4_27, +matrixC4_28, +matrixC4_29, +matrixC4_30, +matrixC4_31, +matrixC5_0, +matrixC5_1, +matrixC5_2, +matrixC5_3, +matrixC5_4, +matrixC5_5, +matrixC5_6, +matrixC5_7, +matrixC5_8, +matrixC5_9, +matrixC5_10, +matrixC5_11, +matrixC5_12, +matrixC5_13, +matrixC5_14, +matrixC5_15, +matrixC5_16, +matrixC5_17, +matrixC5_18, +matrixC5_19, +matrixC5_20, +matrixC5_21, +matrixC5_22, +matrixC5_23, +matrixC5_24, +matrixC5_25, +matrixC5_26, +matrixC5_27, +matrixC5_28, +matrixC5_29, +matrixC5_30, +matrixC5_31, +matrixC6_0, +matrixC6_1, +matrixC6_2, +matrixC6_3, +matrixC6_4, +matrixC6_5, +matrixC6_6, +matrixC6_7, +matrixC6_8, +matrixC6_9, +matrixC6_10, +matrixC6_11, +matrixC6_12, +matrixC6_13, +matrixC6_14, +matrixC6_15, +matrixC6_16, +matrixC6_17, +matrixC6_18, +matrixC6_19, +matrixC6_20, +matrixC6_21, +matrixC6_22, +matrixC6_23, +matrixC6_24, +matrixC6_25, +matrixC6_26, +matrixC6_27, +matrixC6_28, +matrixC6_29, +matrixC6_30, +matrixC6_31, +matrixC7_0, +matrixC7_1, +matrixC7_2, +matrixC7_3, +matrixC7_4, +matrixC7_5, +matrixC7_6, +matrixC7_7, +matrixC7_8, +matrixC7_9, +matrixC7_10, +matrixC7_11, +matrixC7_12, +matrixC7_13, +matrixC7_14, +matrixC7_15, +matrixC7_16, +matrixC7_17, +matrixC7_18, +matrixC7_19, +matrixC7_20, +matrixC7_21, +matrixC7_22, +matrixC7_23, +matrixC7_24, +matrixC7_25, +matrixC7_26, +matrixC7_27, +matrixC7_28, +matrixC7_29, +matrixC7_30, +matrixC7_31, +matrixC8_0, +matrixC8_1, +matrixC8_2, +matrixC8_3, +matrixC8_4, +matrixC8_5, +matrixC8_6, +matrixC8_7, +matrixC8_8, +matrixC8_9, +matrixC8_10, +matrixC8_11, +matrixC8_12, +matrixC8_13, +matrixC8_14, +matrixC8_15, +matrixC8_16, +matrixC8_17, +matrixC8_18, +matrixC8_19, +matrixC8_20, +matrixC8_21, +matrixC8_22, +matrixC8_23, +matrixC8_24, +matrixC8_25, +matrixC8_26, +matrixC8_27, +matrixC8_28, +matrixC8_29, +matrixC8_30, +matrixC8_31, +matrixC9_0, +matrixC9_1, +matrixC9_2, +matrixC9_3, +matrixC9_4, +matrixC9_5, +matrixC9_6, +matrixC9_7, +matrixC9_8, +matrixC9_9, +matrixC9_10, +matrixC9_11, +matrixC9_12, +matrixC9_13, +matrixC9_14, +matrixC9_15, +matrixC9_16, +matrixC9_17, +matrixC9_18, +matrixC9_19, +matrixC9_20, +matrixC9_21, +matrixC9_22, +matrixC9_23, +matrixC9_24, +matrixC9_25, +matrixC9_26, +matrixC9_27, +matrixC9_28, +matrixC9_29, +matrixC9_30, +matrixC9_31, +matrixC10_0, +matrixC10_1, +matrixC10_2, +matrixC10_3, +matrixC10_4, +matrixC10_5, +matrixC10_6, +matrixC10_7, +matrixC10_8, +matrixC10_9, +matrixC10_10, +matrixC10_11, +matrixC10_12, +matrixC10_13, +matrixC10_14, +matrixC10_15, +matrixC10_16, +matrixC10_17, +matrixC10_18, +matrixC10_19, +matrixC10_20, +matrixC10_21, +matrixC10_22, +matrixC10_23, +matrixC10_24, +matrixC10_25, +matrixC10_26, +matrixC10_27, +matrixC10_28, +matrixC10_29, +matrixC10_30, +matrixC10_31, +matrixC11_0, +matrixC11_1, +matrixC11_2, +matrixC11_3, +matrixC11_4, +matrixC11_5, +matrixC11_6, +matrixC11_7, +matrixC11_8, +matrixC11_9, +matrixC11_10, +matrixC11_11, +matrixC11_12, +matrixC11_13, +matrixC11_14, +matrixC11_15, +matrixC11_16, +matrixC11_17, +matrixC11_18, +matrixC11_19, +matrixC11_20, +matrixC11_21, +matrixC11_22, +matrixC11_23, +matrixC11_24, +matrixC11_25, +matrixC11_26, +matrixC11_27, +matrixC11_28, +matrixC11_29, +matrixC11_30, +matrixC11_31, +matrixC12_0, +matrixC12_1, +matrixC12_2, +matrixC12_3, +matrixC12_4, +matrixC12_5, +matrixC12_6, +matrixC12_7, +matrixC12_8, +matrixC12_9, +matrixC12_10, +matrixC12_11, +matrixC12_12, +matrixC12_13, +matrixC12_14, +matrixC12_15, +matrixC12_16, +matrixC12_17, +matrixC12_18, +matrixC12_19, +matrixC12_20, +matrixC12_21, +matrixC12_22, +matrixC12_23, +matrixC12_24, +matrixC12_25, +matrixC12_26, +matrixC12_27, +matrixC12_28, +matrixC12_29, +matrixC12_30, +matrixC12_31, +matrixC13_0, +matrixC13_1, +matrixC13_2, +matrixC13_3, +matrixC13_4, +matrixC13_5, +matrixC13_6, +matrixC13_7, +matrixC13_8, +matrixC13_9, +matrixC13_10, +matrixC13_11, +matrixC13_12, +matrixC13_13, +matrixC13_14, +matrixC13_15, +matrixC13_16, +matrixC13_17, +matrixC13_18, +matrixC13_19, +matrixC13_20, +matrixC13_21, +matrixC13_22, +matrixC13_23, +matrixC13_24, +matrixC13_25, +matrixC13_26, +matrixC13_27, +matrixC13_28, +matrixC13_29, +matrixC13_30, +matrixC13_31, +matrixC14_0, +matrixC14_1, +matrixC14_2, +matrixC14_3, +matrixC14_4, +matrixC14_5, +matrixC14_6, +matrixC14_7, +matrixC14_8, +matrixC14_9, +matrixC14_10, +matrixC14_11, +matrixC14_12, +matrixC14_13, +matrixC14_14, +matrixC14_15, +matrixC14_16, +matrixC14_17, +matrixC14_18, +matrixC14_19, +matrixC14_20, +matrixC14_21, +matrixC14_22, +matrixC14_23, +matrixC14_24, +matrixC14_25, +matrixC14_26, +matrixC14_27, +matrixC14_28, +matrixC14_29, +matrixC14_30, +matrixC14_31, +matrixC15_0, +matrixC15_1, +matrixC15_2, +matrixC15_3, +matrixC15_4, +matrixC15_5, +matrixC15_6, +matrixC15_7, +matrixC15_8, +matrixC15_9, +matrixC15_10, +matrixC15_11, +matrixC15_12, +matrixC15_13, +matrixC15_14, +matrixC15_15, +matrixC15_16, +matrixC15_17, +matrixC15_18, +matrixC15_19, +matrixC15_20, +matrixC15_21, +matrixC15_22, +matrixC15_23, +matrixC15_24, +matrixC15_25, +matrixC15_26, +matrixC15_27, +matrixC15_28, +matrixC15_29, +matrixC15_30, +matrixC15_31, +matrixC16_0, +matrixC16_1, +matrixC16_2, +matrixC16_3, +matrixC16_4, +matrixC16_5, +matrixC16_6, +matrixC16_7, +matrixC16_8, +matrixC16_9, +matrixC16_10, +matrixC16_11, +matrixC16_12, +matrixC16_13, +matrixC16_14, +matrixC16_15, +matrixC16_16, +matrixC16_17, +matrixC16_18, +matrixC16_19, +matrixC16_20, +matrixC16_21, +matrixC16_22, +matrixC16_23, +matrixC16_24, +matrixC16_25, +matrixC16_26, +matrixC16_27, +matrixC16_28, +matrixC16_29, +matrixC16_30, +matrixC16_31, +matrixC17_0, +matrixC17_1, +matrixC17_2, +matrixC17_3, +matrixC17_4, +matrixC17_5, +matrixC17_6, +matrixC17_7, +matrixC17_8, +matrixC17_9, +matrixC17_10, +matrixC17_11, +matrixC17_12, +matrixC17_13, +matrixC17_14, +matrixC17_15, +matrixC17_16, +matrixC17_17, +matrixC17_18, +matrixC17_19, +matrixC17_20, +matrixC17_21, +matrixC17_22, +matrixC17_23, +matrixC17_24, +matrixC17_25, +matrixC17_26, +matrixC17_27, +matrixC17_28, +matrixC17_29, +matrixC17_30, +matrixC17_31, +matrixC18_0, +matrixC18_1, +matrixC18_2, +matrixC18_3, +matrixC18_4, +matrixC18_5, +matrixC18_6, +matrixC18_7, +matrixC18_8, +matrixC18_9, +matrixC18_10, +matrixC18_11, +matrixC18_12, +matrixC18_13, +matrixC18_14, +matrixC18_15, +matrixC18_16, +matrixC18_17, +matrixC18_18, +matrixC18_19, +matrixC18_20, +matrixC18_21, +matrixC18_22, +matrixC18_23, +matrixC18_24, +matrixC18_25, +matrixC18_26, +matrixC18_27, +matrixC18_28, +matrixC18_29, +matrixC18_30, +matrixC18_31, +matrixC19_0, +matrixC19_1, +matrixC19_2, +matrixC19_3, +matrixC19_4, +matrixC19_5, +matrixC19_6, +matrixC19_7, +matrixC19_8, +matrixC19_9, +matrixC19_10, +matrixC19_11, +matrixC19_12, +matrixC19_13, +matrixC19_14, +matrixC19_15, +matrixC19_16, +matrixC19_17, +matrixC19_18, +matrixC19_19, +matrixC19_20, +matrixC19_21, +matrixC19_22, +matrixC19_23, +matrixC19_24, +matrixC19_25, +matrixC19_26, +matrixC19_27, +matrixC19_28, +matrixC19_29, +matrixC19_30, +matrixC19_31, +matrixC20_0, +matrixC20_1, +matrixC20_2, +matrixC20_3, +matrixC20_4, +matrixC20_5, +matrixC20_6, +matrixC20_7, +matrixC20_8, +matrixC20_9, +matrixC20_10, +matrixC20_11, +matrixC20_12, +matrixC20_13, +matrixC20_14, +matrixC20_15, +matrixC20_16, +matrixC20_17, +matrixC20_18, +matrixC20_19, +matrixC20_20, +matrixC20_21, +matrixC20_22, +matrixC20_23, +matrixC20_24, +matrixC20_25, +matrixC20_26, +matrixC20_27, +matrixC20_28, +matrixC20_29, +matrixC20_30, +matrixC20_31, +matrixC21_0, +matrixC21_1, +matrixC21_2, +matrixC21_3, +matrixC21_4, +matrixC21_5, +matrixC21_6, +matrixC21_7, +matrixC21_8, +matrixC21_9, +matrixC21_10, +matrixC21_11, +matrixC21_12, +matrixC21_13, +matrixC21_14, +matrixC21_15, +matrixC21_16, +matrixC21_17, +matrixC21_18, +matrixC21_19, +matrixC21_20, +matrixC21_21, +matrixC21_22, +matrixC21_23, +matrixC21_24, +matrixC21_25, +matrixC21_26, +matrixC21_27, +matrixC21_28, +matrixC21_29, +matrixC21_30, +matrixC21_31, +matrixC22_0, +matrixC22_1, +matrixC22_2, +matrixC22_3, +matrixC22_4, +matrixC22_5, +matrixC22_6, +matrixC22_7, +matrixC22_8, +matrixC22_9, +matrixC22_10, +matrixC22_11, +matrixC22_12, +matrixC22_13, +matrixC22_14, +matrixC22_15, +matrixC22_16, +matrixC22_17, +matrixC22_18, +matrixC22_19, +matrixC22_20, +matrixC22_21, +matrixC22_22, +matrixC22_23, +matrixC22_24, +matrixC22_25, +matrixC22_26, +matrixC22_27, +matrixC22_28, +matrixC22_29, +matrixC22_30, +matrixC22_31, +matrixC23_0, +matrixC23_1, +matrixC23_2, +matrixC23_3, +matrixC23_4, +matrixC23_5, +matrixC23_6, +matrixC23_7, +matrixC23_8, +matrixC23_9, +matrixC23_10, +matrixC23_11, +matrixC23_12, +matrixC23_13, +matrixC23_14, +matrixC23_15, +matrixC23_16, +matrixC23_17, +matrixC23_18, +matrixC23_19, +matrixC23_20, +matrixC23_21, +matrixC23_22, +matrixC23_23, +matrixC23_24, +matrixC23_25, +matrixC23_26, +matrixC23_27, +matrixC23_28, +matrixC23_29, +matrixC23_30, +matrixC23_31, +matrixC24_0, +matrixC24_1, +matrixC24_2, +matrixC24_3, +matrixC24_4, +matrixC24_5, +matrixC24_6, +matrixC24_7, +matrixC24_8, +matrixC24_9, +matrixC24_10, +matrixC24_11, +matrixC24_12, +matrixC24_13, +matrixC24_14, +matrixC24_15, +matrixC24_16, +matrixC24_17, +matrixC24_18, +matrixC24_19, +matrixC24_20, +matrixC24_21, +matrixC24_22, +matrixC24_23, +matrixC24_24, +matrixC24_25, +matrixC24_26, +matrixC24_27, +matrixC24_28, +matrixC24_29, +matrixC24_30, +matrixC24_31, +matrixC25_0, +matrixC25_1, +matrixC25_2, +matrixC25_3, +matrixC25_4, +matrixC25_5, +matrixC25_6, +matrixC25_7, +matrixC25_8, +matrixC25_9, +matrixC25_10, +matrixC25_11, +matrixC25_12, +matrixC25_13, +matrixC25_14, +matrixC25_15, +matrixC25_16, +matrixC25_17, +matrixC25_18, +matrixC25_19, +matrixC25_20, +matrixC25_21, +matrixC25_22, +matrixC25_23, +matrixC25_24, +matrixC25_25, +matrixC25_26, +matrixC25_27, +matrixC25_28, +matrixC25_29, +matrixC25_30, +matrixC25_31, +matrixC26_0, +matrixC26_1, +matrixC26_2, +matrixC26_3, +matrixC26_4, +matrixC26_5, +matrixC26_6, +matrixC26_7, +matrixC26_8, +matrixC26_9, +matrixC26_10, +matrixC26_11, +matrixC26_12, +matrixC26_13, +matrixC26_14, +matrixC26_15, +matrixC26_16, +matrixC26_17, +matrixC26_18, +matrixC26_19, +matrixC26_20, +matrixC26_21, +matrixC26_22, +matrixC26_23, +matrixC26_24, +matrixC26_25, +matrixC26_26, +matrixC26_27, +matrixC26_28, +matrixC26_29, +matrixC26_30, +matrixC26_31, +matrixC27_0, +matrixC27_1, +matrixC27_2, +matrixC27_3, +matrixC27_4, +matrixC27_5, +matrixC27_6, +matrixC27_7, +matrixC27_8, +matrixC27_9, +matrixC27_10, +matrixC27_11, +matrixC27_12, +matrixC27_13, +matrixC27_14, +matrixC27_15, +matrixC27_16, +matrixC27_17, +matrixC27_18, +matrixC27_19, +matrixC27_20, +matrixC27_21, +matrixC27_22, +matrixC27_23, +matrixC27_24, +matrixC27_25, +matrixC27_26, +matrixC27_27, +matrixC27_28, +matrixC27_29, +matrixC27_30, +matrixC27_31, +matrixC28_0, +matrixC28_1, +matrixC28_2, +matrixC28_3, +matrixC28_4, +matrixC28_5, +matrixC28_6, +matrixC28_7, +matrixC28_8, +matrixC28_9, +matrixC28_10, +matrixC28_11, +matrixC28_12, +matrixC28_13, +matrixC28_14, +matrixC28_15, +matrixC28_16, +matrixC28_17, +matrixC28_18, +matrixC28_19, +matrixC28_20, +matrixC28_21, +matrixC28_22, +matrixC28_23, +matrixC28_24, +matrixC28_25, +matrixC28_26, +matrixC28_27, +matrixC28_28, +matrixC28_29, +matrixC28_30, +matrixC28_31, +matrixC29_0, +matrixC29_1, +matrixC29_2, +matrixC29_3, +matrixC29_4, +matrixC29_5, +matrixC29_6, +matrixC29_7, +matrixC29_8, +matrixC29_9, +matrixC29_10, +matrixC29_11, +matrixC29_12, +matrixC29_13, +matrixC29_14, +matrixC29_15, +matrixC29_16, +matrixC29_17, +matrixC29_18, +matrixC29_19, +matrixC29_20, +matrixC29_21, +matrixC29_22, +matrixC29_23, +matrixC29_24, +matrixC29_25, +matrixC29_26, +matrixC29_27, +matrixC29_28, +matrixC29_29, +matrixC29_30, +matrixC29_31, +matrixC30_0, +matrixC30_1, +matrixC30_2, +matrixC30_3, +matrixC30_4, +matrixC30_5, +matrixC30_6, +matrixC30_7, +matrixC30_8, +matrixC30_9, +matrixC30_10, +matrixC30_11, +matrixC30_12, +matrixC30_13, +matrixC30_14, +matrixC30_15, +matrixC30_16, +matrixC30_17, +matrixC30_18, +matrixC30_19, +matrixC30_20, +matrixC30_21, +matrixC30_22, +matrixC30_23, +matrixC30_24, +matrixC30_25, +matrixC30_26, +matrixC30_27, +matrixC30_28, +matrixC30_29, +matrixC30_30, +matrixC30_31, +matrixC31_0, +matrixC31_1, +matrixC31_2, +matrixC31_3, +matrixC31_4, +matrixC31_5, +matrixC31_6, +matrixC31_7, +matrixC31_8, +matrixC31_9, +matrixC31_10, +matrixC31_11, +matrixC31_12, +matrixC31_13, +matrixC31_14, +matrixC31_15, +matrixC31_16, +matrixC31_17, +matrixC31_18, +matrixC31_19, +matrixC31_20, +matrixC31_21, +matrixC31_22, +matrixC31_23, +matrixC31_24, +matrixC31_25, +matrixC31_26, +matrixC31_27, +matrixC31_28, +matrixC31_29, +matrixC31_30, +matrixC31_31, + +a_data_out, +b_data_out +); + +input clk; +input reset; +input pe_reset; +input [`DWIDTH-1:0] a0; +input [`DWIDTH-1:0] a1; +input [`DWIDTH-1:0] a2; +input [`DWIDTH-1:0] a3; +input [`DWIDTH-1:0] a4; +input [`DWIDTH-1:0] a5; +input [`DWIDTH-1:0] a6; +input [`DWIDTH-1:0] a7; +input [`DWIDTH-1:0] a8; +input [`DWIDTH-1:0] a9; +input [`DWIDTH-1:0] a10; +input [`DWIDTH-1:0] a11; +input [`DWIDTH-1:0] a12; +input [`DWIDTH-1:0] a13; +input [`DWIDTH-1:0] a14; +input [`DWIDTH-1:0] a15; +input [`DWIDTH-1:0] a16; +input [`DWIDTH-1:0] a17; +input [`DWIDTH-1:0] a18; +input [`DWIDTH-1:0] a19; +input [`DWIDTH-1:0] a20; +input [`DWIDTH-1:0] a21; +input [`DWIDTH-1:0] a22; +input [`DWIDTH-1:0] a23; +input [`DWIDTH-1:0] a24; +input [`DWIDTH-1:0] a25; +input [`DWIDTH-1:0] a26; +input [`DWIDTH-1:0] a27; +input [`DWIDTH-1:0] a28; +input [`DWIDTH-1:0] a29; +input [`DWIDTH-1:0] a30; +input [`DWIDTH-1:0] a31; +input [`DWIDTH-1:0] b0; +input [`DWIDTH-1:0] b1; +input [`DWIDTH-1:0] b2; +input [`DWIDTH-1:0] b3; +input [`DWIDTH-1:0] b4; +input [`DWIDTH-1:0] b5; +input [`DWIDTH-1:0] b6; +input [`DWIDTH-1:0] b7; +input [`DWIDTH-1:0] b8; +input [`DWIDTH-1:0] b9; +input [`DWIDTH-1:0] b10; +input [`DWIDTH-1:0] b11; +input [`DWIDTH-1:0] b12; +input [`DWIDTH-1:0] b13; +input [`DWIDTH-1:0] b14; +input [`DWIDTH-1:0] b15; +input [`DWIDTH-1:0] b16; +input [`DWIDTH-1:0] b17; +input [`DWIDTH-1:0] b18; +input [`DWIDTH-1:0] b19; +input [`DWIDTH-1:0] b20; +input [`DWIDTH-1:0] b21; +input [`DWIDTH-1:0] b22; +input [`DWIDTH-1:0] b23; +input [`DWIDTH-1:0] b24; +input [`DWIDTH-1:0] b25; +input [`DWIDTH-1:0] b26; +input [`DWIDTH-1:0] b27; +input [`DWIDTH-1:0] b28; +input [`DWIDTH-1:0] b29; +input [`DWIDTH-1:0] b30; +input [`DWIDTH-1:0] b31; +output [`DWIDTH-1:0] matrixC0_0; +output [`DWIDTH-1:0] matrixC0_1; +output [`DWIDTH-1:0] matrixC0_2; +output [`DWIDTH-1:0] matrixC0_3; +output [`DWIDTH-1:0] matrixC0_4; +output [`DWIDTH-1:0] matrixC0_5; +output [`DWIDTH-1:0] matrixC0_6; +output [`DWIDTH-1:0] matrixC0_7; +output [`DWIDTH-1:0] matrixC0_8; +output [`DWIDTH-1:0] matrixC0_9; +output [`DWIDTH-1:0] matrixC0_10; +output [`DWIDTH-1:0] matrixC0_11; +output [`DWIDTH-1:0] matrixC0_12; +output [`DWIDTH-1:0] matrixC0_13; +output [`DWIDTH-1:0] matrixC0_14; +output [`DWIDTH-1:0] matrixC0_15; +output [`DWIDTH-1:0] matrixC0_16; +output [`DWIDTH-1:0] matrixC0_17; +output [`DWIDTH-1:0] matrixC0_18; +output [`DWIDTH-1:0] matrixC0_19; +output [`DWIDTH-1:0] matrixC0_20; +output [`DWIDTH-1:0] matrixC0_21; +output [`DWIDTH-1:0] matrixC0_22; +output [`DWIDTH-1:0] matrixC0_23; +output [`DWIDTH-1:0] matrixC0_24; +output [`DWIDTH-1:0] matrixC0_25; +output [`DWIDTH-1:0] matrixC0_26; +output [`DWIDTH-1:0] matrixC0_27; +output [`DWIDTH-1:0] matrixC0_28; +output [`DWIDTH-1:0] matrixC0_29; +output [`DWIDTH-1:0] matrixC0_30; +output [`DWIDTH-1:0] matrixC0_31; +output [`DWIDTH-1:0] matrixC1_0; +output [`DWIDTH-1:0] matrixC1_1; +output [`DWIDTH-1:0] matrixC1_2; +output [`DWIDTH-1:0] matrixC1_3; +output [`DWIDTH-1:0] matrixC1_4; +output [`DWIDTH-1:0] matrixC1_5; +output [`DWIDTH-1:0] matrixC1_6; +output [`DWIDTH-1:0] matrixC1_7; +output [`DWIDTH-1:0] matrixC1_8; +output [`DWIDTH-1:0] matrixC1_9; +output [`DWIDTH-1:0] matrixC1_10; +output [`DWIDTH-1:0] matrixC1_11; +output [`DWIDTH-1:0] matrixC1_12; +output [`DWIDTH-1:0] matrixC1_13; +output [`DWIDTH-1:0] matrixC1_14; +output [`DWIDTH-1:0] matrixC1_15; +output [`DWIDTH-1:0] matrixC1_16; +output [`DWIDTH-1:0] matrixC1_17; +output [`DWIDTH-1:0] matrixC1_18; +output [`DWIDTH-1:0] matrixC1_19; +output [`DWIDTH-1:0] matrixC1_20; +output [`DWIDTH-1:0] matrixC1_21; +output [`DWIDTH-1:0] matrixC1_22; +output [`DWIDTH-1:0] matrixC1_23; +output [`DWIDTH-1:0] matrixC1_24; +output [`DWIDTH-1:0] matrixC1_25; +output [`DWIDTH-1:0] matrixC1_26; +output [`DWIDTH-1:0] matrixC1_27; +output [`DWIDTH-1:0] matrixC1_28; +output [`DWIDTH-1:0] matrixC1_29; +output [`DWIDTH-1:0] matrixC1_30; +output [`DWIDTH-1:0] matrixC1_31; +output [`DWIDTH-1:0] matrixC2_0; +output [`DWIDTH-1:0] matrixC2_1; +output [`DWIDTH-1:0] matrixC2_2; +output [`DWIDTH-1:0] matrixC2_3; +output [`DWIDTH-1:0] matrixC2_4; +output [`DWIDTH-1:0] matrixC2_5; +output [`DWIDTH-1:0] matrixC2_6; +output [`DWIDTH-1:0] matrixC2_7; +output [`DWIDTH-1:0] matrixC2_8; +output [`DWIDTH-1:0] matrixC2_9; +output [`DWIDTH-1:0] matrixC2_10; +output [`DWIDTH-1:0] matrixC2_11; +output [`DWIDTH-1:0] matrixC2_12; +output [`DWIDTH-1:0] matrixC2_13; +output [`DWIDTH-1:0] matrixC2_14; +output [`DWIDTH-1:0] matrixC2_15; +output [`DWIDTH-1:0] matrixC2_16; +output [`DWIDTH-1:0] matrixC2_17; +output [`DWIDTH-1:0] matrixC2_18; +output [`DWIDTH-1:0] matrixC2_19; +output [`DWIDTH-1:0] matrixC2_20; +output [`DWIDTH-1:0] matrixC2_21; +output [`DWIDTH-1:0] matrixC2_22; +output [`DWIDTH-1:0] matrixC2_23; +output [`DWIDTH-1:0] matrixC2_24; +output [`DWIDTH-1:0] matrixC2_25; +output [`DWIDTH-1:0] matrixC2_26; +output [`DWIDTH-1:0] matrixC2_27; +output [`DWIDTH-1:0] matrixC2_28; +output [`DWIDTH-1:0] matrixC2_29; +output [`DWIDTH-1:0] matrixC2_30; +output [`DWIDTH-1:0] matrixC2_31; +output [`DWIDTH-1:0] matrixC3_0; +output [`DWIDTH-1:0] matrixC3_1; +output [`DWIDTH-1:0] matrixC3_2; +output [`DWIDTH-1:0] matrixC3_3; +output [`DWIDTH-1:0] matrixC3_4; +output [`DWIDTH-1:0] matrixC3_5; +output [`DWIDTH-1:0] matrixC3_6; +output [`DWIDTH-1:0] matrixC3_7; +output [`DWIDTH-1:0] matrixC3_8; +output [`DWIDTH-1:0] matrixC3_9; +output [`DWIDTH-1:0] matrixC3_10; +output [`DWIDTH-1:0] matrixC3_11; +output [`DWIDTH-1:0] matrixC3_12; +output [`DWIDTH-1:0] matrixC3_13; +output [`DWIDTH-1:0] matrixC3_14; +output [`DWIDTH-1:0] matrixC3_15; +output [`DWIDTH-1:0] matrixC3_16; +output [`DWIDTH-1:0] matrixC3_17; +output [`DWIDTH-1:0] matrixC3_18; +output [`DWIDTH-1:0] matrixC3_19; +output [`DWIDTH-1:0] matrixC3_20; +output [`DWIDTH-1:0] matrixC3_21; +output [`DWIDTH-1:0] matrixC3_22; +output [`DWIDTH-1:0] matrixC3_23; +output [`DWIDTH-1:0] matrixC3_24; +output [`DWIDTH-1:0] matrixC3_25; +output [`DWIDTH-1:0] matrixC3_26; +output [`DWIDTH-1:0] matrixC3_27; +output [`DWIDTH-1:0] matrixC3_28; +output [`DWIDTH-1:0] matrixC3_29; +output [`DWIDTH-1:0] matrixC3_30; +output [`DWIDTH-1:0] matrixC3_31; +output [`DWIDTH-1:0] matrixC4_0; +output [`DWIDTH-1:0] matrixC4_1; +output [`DWIDTH-1:0] matrixC4_2; +output [`DWIDTH-1:0] matrixC4_3; +output [`DWIDTH-1:0] matrixC4_4; +output [`DWIDTH-1:0] matrixC4_5; +output [`DWIDTH-1:0] matrixC4_6; +output [`DWIDTH-1:0] matrixC4_7; +output [`DWIDTH-1:0] matrixC4_8; +output [`DWIDTH-1:0] matrixC4_9; +output [`DWIDTH-1:0] matrixC4_10; +output [`DWIDTH-1:0] matrixC4_11; +output [`DWIDTH-1:0] matrixC4_12; +output [`DWIDTH-1:0] matrixC4_13; +output [`DWIDTH-1:0] matrixC4_14; +output [`DWIDTH-1:0] matrixC4_15; +output [`DWIDTH-1:0] matrixC4_16; +output [`DWIDTH-1:0] matrixC4_17; +output [`DWIDTH-1:0] matrixC4_18; +output [`DWIDTH-1:0] matrixC4_19; +output [`DWIDTH-1:0] matrixC4_20; +output [`DWIDTH-1:0] matrixC4_21; +output [`DWIDTH-1:0] matrixC4_22; +output [`DWIDTH-1:0] matrixC4_23; +output [`DWIDTH-1:0] matrixC4_24; +output [`DWIDTH-1:0] matrixC4_25; +output [`DWIDTH-1:0] matrixC4_26; +output [`DWIDTH-1:0] matrixC4_27; +output [`DWIDTH-1:0] matrixC4_28; +output [`DWIDTH-1:0] matrixC4_29; +output [`DWIDTH-1:0] matrixC4_30; +output [`DWIDTH-1:0] matrixC4_31; +output [`DWIDTH-1:0] matrixC5_0; +output [`DWIDTH-1:0] matrixC5_1; +output [`DWIDTH-1:0] matrixC5_2; +output [`DWIDTH-1:0] matrixC5_3; +output [`DWIDTH-1:0] matrixC5_4; +output [`DWIDTH-1:0] matrixC5_5; +output [`DWIDTH-1:0] matrixC5_6; +output [`DWIDTH-1:0] matrixC5_7; +output [`DWIDTH-1:0] matrixC5_8; +output [`DWIDTH-1:0] matrixC5_9; +output [`DWIDTH-1:0] matrixC5_10; +output [`DWIDTH-1:0] matrixC5_11; +output [`DWIDTH-1:0] matrixC5_12; +output [`DWIDTH-1:0] matrixC5_13; +output [`DWIDTH-1:0] matrixC5_14; +output [`DWIDTH-1:0] matrixC5_15; +output [`DWIDTH-1:0] matrixC5_16; +output [`DWIDTH-1:0] matrixC5_17; +output [`DWIDTH-1:0] matrixC5_18; +output [`DWIDTH-1:0] matrixC5_19; +output [`DWIDTH-1:0] matrixC5_20; +output [`DWIDTH-1:0] matrixC5_21; +output [`DWIDTH-1:0] matrixC5_22; +output [`DWIDTH-1:0] matrixC5_23; +output [`DWIDTH-1:0] matrixC5_24; +output [`DWIDTH-1:0] matrixC5_25; +output [`DWIDTH-1:0] matrixC5_26; +output [`DWIDTH-1:0] matrixC5_27; +output [`DWIDTH-1:0] matrixC5_28; +output [`DWIDTH-1:0] matrixC5_29; +output [`DWIDTH-1:0] matrixC5_30; +output [`DWIDTH-1:0] matrixC5_31; +output [`DWIDTH-1:0] matrixC6_0; +output [`DWIDTH-1:0] matrixC6_1; +output [`DWIDTH-1:0] matrixC6_2; +output [`DWIDTH-1:0] matrixC6_3; +output [`DWIDTH-1:0] matrixC6_4; +output [`DWIDTH-1:0] matrixC6_5; +output [`DWIDTH-1:0] matrixC6_6; +output [`DWIDTH-1:0] matrixC6_7; +output [`DWIDTH-1:0] matrixC6_8; +output [`DWIDTH-1:0] matrixC6_9; +output [`DWIDTH-1:0] matrixC6_10; +output [`DWIDTH-1:0] matrixC6_11; +output [`DWIDTH-1:0] matrixC6_12; +output [`DWIDTH-1:0] matrixC6_13; +output [`DWIDTH-1:0] matrixC6_14; +output [`DWIDTH-1:0] matrixC6_15; +output [`DWIDTH-1:0] matrixC6_16; +output [`DWIDTH-1:0] matrixC6_17; +output [`DWIDTH-1:0] matrixC6_18; +output [`DWIDTH-1:0] matrixC6_19; +output [`DWIDTH-1:0] matrixC6_20; +output [`DWIDTH-1:0] matrixC6_21; +output [`DWIDTH-1:0] matrixC6_22; +output [`DWIDTH-1:0] matrixC6_23; +output [`DWIDTH-1:0] matrixC6_24; +output [`DWIDTH-1:0] matrixC6_25; +output [`DWIDTH-1:0] matrixC6_26; +output [`DWIDTH-1:0] matrixC6_27; +output [`DWIDTH-1:0] matrixC6_28; +output [`DWIDTH-1:0] matrixC6_29; +output [`DWIDTH-1:0] matrixC6_30; +output [`DWIDTH-1:0] matrixC6_31; +output [`DWIDTH-1:0] matrixC7_0; +output [`DWIDTH-1:0] matrixC7_1; +output [`DWIDTH-1:0] matrixC7_2; +output [`DWIDTH-1:0] matrixC7_3; +output [`DWIDTH-1:0] matrixC7_4; +output [`DWIDTH-1:0] matrixC7_5; +output [`DWIDTH-1:0] matrixC7_6; +output [`DWIDTH-1:0] matrixC7_7; +output [`DWIDTH-1:0] matrixC7_8; +output [`DWIDTH-1:0] matrixC7_9; +output [`DWIDTH-1:0] matrixC7_10; +output [`DWIDTH-1:0] matrixC7_11; +output [`DWIDTH-1:0] matrixC7_12; +output [`DWIDTH-1:0] matrixC7_13; +output [`DWIDTH-1:0] matrixC7_14; +output [`DWIDTH-1:0] matrixC7_15; +output [`DWIDTH-1:0] matrixC7_16; +output [`DWIDTH-1:0] matrixC7_17; +output [`DWIDTH-1:0] matrixC7_18; +output [`DWIDTH-1:0] matrixC7_19; +output [`DWIDTH-1:0] matrixC7_20; +output [`DWIDTH-1:0] matrixC7_21; +output [`DWIDTH-1:0] matrixC7_22; +output [`DWIDTH-1:0] matrixC7_23; +output [`DWIDTH-1:0] matrixC7_24; +output [`DWIDTH-1:0] matrixC7_25; +output [`DWIDTH-1:0] matrixC7_26; +output [`DWIDTH-1:0] matrixC7_27; +output [`DWIDTH-1:0] matrixC7_28; +output [`DWIDTH-1:0] matrixC7_29; +output [`DWIDTH-1:0] matrixC7_30; +output [`DWIDTH-1:0] matrixC7_31; +output [`DWIDTH-1:0] matrixC8_0; +output [`DWIDTH-1:0] matrixC8_1; +output [`DWIDTH-1:0] matrixC8_2; +output [`DWIDTH-1:0] matrixC8_3; +output [`DWIDTH-1:0] matrixC8_4; +output [`DWIDTH-1:0] matrixC8_5; +output [`DWIDTH-1:0] matrixC8_6; +output [`DWIDTH-1:0] matrixC8_7; +output [`DWIDTH-1:0] matrixC8_8; +output [`DWIDTH-1:0] matrixC8_9; +output [`DWIDTH-1:0] matrixC8_10; +output [`DWIDTH-1:0] matrixC8_11; +output [`DWIDTH-1:0] matrixC8_12; +output [`DWIDTH-1:0] matrixC8_13; +output [`DWIDTH-1:0] matrixC8_14; +output [`DWIDTH-1:0] matrixC8_15; +output [`DWIDTH-1:0] matrixC8_16; +output [`DWIDTH-1:0] matrixC8_17; +output [`DWIDTH-1:0] matrixC8_18; +output [`DWIDTH-1:0] matrixC8_19; +output [`DWIDTH-1:0] matrixC8_20; +output [`DWIDTH-1:0] matrixC8_21; +output [`DWIDTH-1:0] matrixC8_22; +output [`DWIDTH-1:0] matrixC8_23; +output [`DWIDTH-1:0] matrixC8_24; +output [`DWIDTH-1:0] matrixC8_25; +output [`DWIDTH-1:0] matrixC8_26; +output [`DWIDTH-1:0] matrixC8_27; +output [`DWIDTH-1:0] matrixC8_28; +output [`DWIDTH-1:0] matrixC8_29; +output [`DWIDTH-1:0] matrixC8_30; +output [`DWIDTH-1:0] matrixC8_31; +output [`DWIDTH-1:0] matrixC9_0; +output [`DWIDTH-1:0] matrixC9_1; +output [`DWIDTH-1:0] matrixC9_2; +output [`DWIDTH-1:0] matrixC9_3; +output [`DWIDTH-1:0] matrixC9_4; +output [`DWIDTH-1:0] matrixC9_5; +output [`DWIDTH-1:0] matrixC9_6; +output [`DWIDTH-1:0] matrixC9_7; +output [`DWIDTH-1:0] matrixC9_8; +output [`DWIDTH-1:0] matrixC9_9; +output [`DWIDTH-1:0] matrixC9_10; +output [`DWIDTH-1:0] matrixC9_11; +output [`DWIDTH-1:0] matrixC9_12; +output [`DWIDTH-1:0] matrixC9_13; +output [`DWIDTH-1:0] matrixC9_14; +output [`DWIDTH-1:0] matrixC9_15; +output [`DWIDTH-1:0] matrixC9_16; +output [`DWIDTH-1:0] matrixC9_17; +output [`DWIDTH-1:0] matrixC9_18; +output [`DWIDTH-1:0] matrixC9_19; +output [`DWIDTH-1:0] matrixC9_20; +output [`DWIDTH-1:0] matrixC9_21; +output [`DWIDTH-1:0] matrixC9_22; +output [`DWIDTH-1:0] matrixC9_23; +output [`DWIDTH-1:0] matrixC9_24; +output [`DWIDTH-1:0] matrixC9_25; +output [`DWIDTH-1:0] matrixC9_26; +output [`DWIDTH-1:0] matrixC9_27; +output [`DWIDTH-1:0] matrixC9_28; +output [`DWIDTH-1:0] matrixC9_29; +output [`DWIDTH-1:0] matrixC9_30; +output [`DWIDTH-1:0] matrixC9_31; +output [`DWIDTH-1:0] matrixC10_0; +output [`DWIDTH-1:0] matrixC10_1; +output [`DWIDTH-1:0] matrixC10_2; +output [`DWIDTH-1:0] matrixC10_3; +output [`DWIDTH-1:0] matrixC10_4; +output [`DWIDTH-1:0] matrixC10_5; +output [`DWIDTH-1:0] matrixC10_6; +output [`DWIDTH-1:0] matrixC10_7; +output [`DWIDTH-1:0] matrixC10_8; +output [`DWIDTH-1:0] matrixC10_9; +output [`DWIDTH-1:0] matrixC10_10; +output [`DWIDTH-1:0] matrixC10_11; +output [`DWIDTH-1:0] matrixC10_12; +output [`DWIDTH-1:0] matrixC10_13; +output [`DWIDTH-1:0] matrixC10_14; +output [`DWIDTH-1:0] matrixC10_15; +output [`DWIDTH-1:0] matrixC10_16; +output [`DWIDTH-1:0] matrixC10_17; +output [`DWIDTH-1:0] matrixC10_18; +output [`DWIDTH-1:0] matrixC10_19; +output [`DWIDTH-1:0] matrixC10_20; +output [`DWIDTH-1:0] matrixC10_21; +output [`DWIDTH-1:0] matrixC10_22; +output [`DWIDTH-1:0] matrixC10_23; +output [`DWIDTH-1:0] matrixC10_24; +output [`DWIDTH-1:0] matrixC10_25; +output [`DWIDTH-1:0] matrixC10_26; +output [`DWIDTH-1:0] matrixC10_27; +output [`DWIDTH-1:0] matrixC10_28; +output [`DWIDTH-1:0] matrixC10_29; +output [`DWIDTH-1:0] matrixC10_30; +output [`DWIDTH-1:0] matrixC10_31; +output [`DWIDTH-1:0] matrixC11_0; +output [`DWIDTH-1:0] matrixC11_1; +output [`DWIDTH-1:0] matrixC11_2; +output [`DWIDTH-1:0] matrixC11_3; +output [`DWIDTH-1:0] matrixC11_4; +output [`DWIDTH-1:0] matrixC11_5; +output [`DWIDTH-1:0] matrixC11_6; +output [`DWIDTH-1:0] matrixC11_7; +output [`DWIDTH-1:0] matrixC11_8; +output [`DWIDTH-1:0] matrixC11_9; +output [`DWIDTH-1:0] matrixC11_10; +output [`DWIDTH-1:0] matrixC11_11; +output [`DWIDTH-1:0] matrixC11_12; +output [`DWIDTH-1:0] matrixC11_13; +output [`DWIDTH-1:0] matrixC11_14; +output [`DWIDTH-1:0] matrixC11_15; +output [`DWIDTH-1:0] matrixC11_16; +output [`DWIDTH-1:0] matrixC11_17; +output [`DWIDTH-1:0] matrixC11_18; +output [`DWIDTH-1:0] matrixC11_19; +output [`DWIDTH-1:0] matrixC11_20; +output [`DWIDTH-1:0] matrixC11_21; +output [`DWIDTH-1:0] matrixC11_22; +output [`DWIDTH-1:0] matrixC11_23; +output [`DWIDTH-1:0] matrixC11_24; +output [`DWIDTH-1:0] matrixC11_25; +output [`DWIDTH-1:0] matrixC11_26; +output [`DWIDTH-1:0] matrixC11_27; +output [`DWIDTH-1:0] matrixC11_28; +output [`DWIDTH-1:0] matrixC11_29; +output [`DWIDTH-1:0] matrixC11_30; +output [`DWIDTH-1:0] matrixC11_31; +output [`DWIDTH-1:0] matrixC12_0; +output [`DWIDTH-1:0] matrixC12_1; +output [`DWIDTH-1:0] matrixC12_2; +output [`DWIDTH-1:0] matrixC12_3; +output [`DWIDTH-1:0] matrixC12_4; +output [`DWIDTH-1:0] matrixC12_5; +output [`DWIDTH-1:0] matrixC12_6; +output [`DWIDTH-1:0] matrixC12_7; +output [`DWIDTH-1:0] matrixC12_8; +output [`DWIDTH-1:0] matrixC12_9; +output [`DWIDTH-1:0] matrixC12_10; +output [`DWIDTH-1:0] matrixC12_11; +output [`DWIDTH-1:0] matrixC12_12; +output [`DWIDTH-1:0] matrixC12_13; +output [`DWIDTH-1:0] matrixC12_14; +output [`DWIDTH-1:0] matrixC12_15; +output [`DWIDTH-1:0] matrixC12_16; +output [`DWIDTH-1:0] matrixC12_17; +output [`DWIDTH-1:0] matrixC12_18; +output [`DWIDTH-1:0] matrixC12_19; +output [`DWIDTH-1:0] matrixC12_20; +output [`DWIDTH-1:0] matrixC12_21; +output [`DWIDTH-1:0] matrixC12_22; +output [`DWIDTH-1:0] matrixC12_23; +output [`DWIDTH-1:0] matrixC12_24; +output [`DWIDTH-1:0] matrixC12_25; +output [`DWIDTH-1:0] matrixC12_26; +output [`DWIDTH-1:0] matrixC12_27; +output [`DWIDTH-1:0] matrixC12_28; +output [`DWIDTH-1:0] matrixC12_29; +output [`DWIDTH-1:0] matrixC12_30; +output [`DWIDTH-1:0] matrixC12_31; +output [`DWIDTH-1:0] matrixC13_0; +output [`DWIDTH-1:0] matrixC13_1; +output [`DWIDTH-1:0] matrixC13_2; +output [`DWIDTH-1:0] matrixC13_3; +output [`DWIDTH-1:0] matrixC13_4; +output [`DWIDTH-1:0] matrixC13_5; +output [`DWIDTH-1:0] matrixC13_6; +output [`DWIDTH-1:0] matrixC13_7; +output [`DWIDTH-1:0] matrixC13_8; +output [`DWIDTH-1:0] matrixC13_9; +output [`DWIDTH-1:0] matrixC13_10; +output [`DWIDTH-1:0] matrixC13_11; +output [`DWIDTH-1:0] matrixC13_12; +output [`DWIDTH-1:0] matrixC13_13; +output [`DWIDTH-1:0] matrixC13_14; +output [`DWIDTH-1:0] matrixC13_15; +output [`DWIDTH-1:0] matrixC13_16; +output [`DWIDTH-1:0] matrixC13_17; +output [`DWIDTH-1:0] matrixC13_18; +output [`DWIDTH-1:0] matrixC13_19; +output [`DWIDTH-1:0] matrixC13_20; +output [`DWIDTH-1:0] matrixC13_21; +output [`DWIDTH-1:0] matrixC13_22; +output [`DWIDTH-1:0] matrixC13_23; +output [`DWIDTH-1:0] matrixC13_24; +output [`DWIDTH-1:0] matrixC13_25; +output [`DWIDTH-1:0] matrixC13_26; +output [`DWIDTH-1:0] matrixC13_27; +output [`DWIDTH-1:0] matrixC13_28; +output [`DWIDTH-1:0] matrixC13_29; +output [`DWIDTH-1:0] matrixC13_30; +output [`DWIDTH-1:0] matrixC13_31; +output [`DWIDTH-1:0] matrixC14_0; +output [`DWIDTH-1:0] matrixC14_1; +output [`DWIDTH-1:0] matrixC14_2; +output [`DWIDTH-1:0] matrixC14_3; +output [`DWIDTH-1:0] matrixC14_4; +output [`DWIDTH-1:0] matrixC14_5; +output [`DWIDTH-1:0] matrixC14_6; +output [`DWIDTH-1:0] matrixC14_7; +output [`DWIDTH-1:0] matrixC14_8; +output [`DWIDTH-1:0] matrixC14_9; +output [`DWIDTH-1:0] matrixC14_10; +output [`DWIDTH-1:0] matrixC14_11; +output [`DWIDTH-1:0] matrixC14_12; +output [`DWIDTH-1:0] matrixC14_13; +output [`DWIDTH-1:0] matrixC14_14; +output [`DWIDTH-1:0] matrixC14_15; +output [`DWIDTH-1:0] matrixC14_16; +output [`DWIDTH-1:0] matrixC14_17; +output [`DWIDTH-1:0] matrixC14_18; +output [`DWIDTH-1:0] matrixC14_19; +output [`DWIDTH-1:0] matrixC14_20; +output [`DWIDTH-1:0] matrixC14_21; +output [`DWIDTH-1:0] matrixC14_22; +output [`DWIDTH-1:0] matrixC14_23; +output [`DWIDTH-1:0] matrixC14_24; +output [`DWIDTH-1:0] matrixC14_25; +output [`DWIDTH-1:0] matrixC14_26; +output [`DWIDTH-1:0] matrixC14_27; +output [`DWIDTH-1:0] matrixC14_28; +output [`DWIDTH-1:0] matrixC14_29; +output [`DWIDTH-1:0] matrixC14_30; +output [`DWIDTH-1:0] matrixC14_31; +output [`DWIDTH-1:0] matrixC15_0; +output [`DWIDTH-1:0] matrixC15_1; +output [`DWIDTH-1:0] matrixC15_2; +output [`DWIDTH-1:0] matrixC15_3; +output [`DWIDTH-1:0] matrixC15_4; +output [`DWIDTH-1:0] matrixC15_5; +output [`DWIDTH-1:0] matrixC15_6; +output [`DWIDTH-1:0] matrixC15_7; +output [`DWIDTH-1:0] matrixC15_8; +output [`DWIDTH-1:0] matrixC15_9; +output [`DWIDTH-1:0] matrixC15_10; +output [`DWIDTH-1:0] matrixC15_11; +output [`DWIDTH-1:0] matrixC15_12; +output [`DWIDTH-1:0] matrixC15_13; +output [`DWIDTH-1:0] matrixC15_14; +output [`DWIDTH-1:0] matrixC15_15; +output [`DWIDTH-1:0] matrixC15_16; +output [`DWIDTH-1:0] matrixC15_17; +output [`DWIDTH-1:0] matrixC15_18; +output [`DWIDTH-1:0] matrixC15_19; +output [`DWIDTH-1:0] matrixC15_20; +output [`DWIDTH-1:0] matrixC15_21; +output [`DWIDTH-1:0] matrixC15_22; +output [`DWIDTH-1:0] matrixC15_23; +output [`DWIDTH-1:0] matrixC15_24; +output [`DWIDTH-1:0] matrixC15_25; +output [`DWIDTH-1:0] matrixC15_26; +output [`DWIDTH-1:0] matrixC15_27; +output [`DWIDTH-1:0] matrixC15_28; +output [`DWIDTH-1:0] matrixC15_29; +output [`DWIDTH-1:0] matrixC15_30; +output [`DWIDTH-1:0] matrixC15_31; +output [`DWIDTH-1:0] matrixC16_0; +output [`DWIDTH-1:0] matrixC16_1; +output [`DWIDTH-1:0] matrixC16_2; +output [`DWIDTH-1:0] matrixC16_3; +output [`DWIDTH-1:0] matrixC16_4; +output [`DWIDTH-1:0] matrixC16_5; +output [`DWIDTH-1:0] matrixC16_6; +output [`DWIDTH-1:0] matrixC16_7; +output [`DWIDTH-1:0] matrixC16_8; +output [`DWIDTH-1:0] matrixC16_9; +output [`DWIDTH-1:0] matrixC16_10; +output [`DWIDTH-1:0] matrixC16_11; +output [`DWIDTH-1:0] matrixC16_12; +output [`DWIDTH-1:0] matrixC16_13; +output [`DWIDTH-1:0] matrixC16_14; +output [`DWIDTH-1:0] matrixC16_15; +output [`DWIDTH-1:0] matrixC16_16; +output [`DWIDTH-1:0] matrixC16_17; +output [`DWIDTH-1:0] matrixC16_18; +output [`DWIDTH-1:0] matrixC16_19; +output [`DWIDTH-1:0] matrixC16_20; +output [`DWIDTH-1:0] matrixC16_21; +output [`DWIDTH-1:0] matrixC16_22; +output [`DWIDTH-1:0] matrixC16_23; +output [`DWIDTH-1:0] matrixC16_24; +output [`DWIDTH-1:0] matrixC16_25; +output [`DWIDTH-1:0] matrixC16_26; +output [`DWIDTH-1:0] matrixC16_27; +output [`DWIDTH-1:0] matrixC16_28; +output [`DWIDTH-1:0] matrixC16_29; +output [`DWIDTH-1:0] matrixC16_30; +output [`DWIDTH-1:0] matrixC16_31; +output [`DWIDTH-1:0] matrixC17_0; +output [`DWIDTH-1:0] matrixC17_1; +output [`DWIDTH-1:0] matrixC17_2; +output [`DWIDTH-1:0] matrixC17_3; +output [`DWIDTH-1:0] matrixC17_4; +output [`DWIDTH-1:0] matrixC17_5; +output [`DWIDTH-1:0] matrixC17_6; +output [`DWIDTH-1:0] matrixC17_7; +output [`DWIDTH-1:0] matrixC17_8; +output [`DWIDTH-1:0] matrixC17_9; +output [`DWIDTH-1:0] matrixC17_10; +output [`DWIDTH-1:0] matrixC17_11; +output [`DWIDTH-1:0] matrixC17_12; +output [`DWIDTH-1:0] matrixC17_13; +output [`DWIDTH-1:0] matrixC17_14; +output [`DWIDTH-1:0] matrixC17_15; +output [`DWIDTH-1:0] matrixC17_16; +output [`DWIDTH-1:0] matrixC17_17; +output [`DWIDTH-1:0] matrixC17_18; +output [`DWIDTH-1:0] matrixC17_19; +output [`DWIDTH-1:0] matrixC17_20; +output [`DWIDTH-1:0] matrixC17_21; +output [`DWIDTH-1:0] matrixC17_22; +output [`DWIDTH-1:0] matrixC17_23; +output [`DWIDTH-1:0] matrixC17_24; +output [`DWIDTH-1:0] matrixC17_25; +output [`DWIDTH-1:0] matrixC17_26; +output [`DWIDTH-1:0] matrixC17_27; +output [`DWIDTH-1:0] matrixC17_28; +output [`DWIDTH-1:0] matrixC17_29; +output [`DWIDTH-1:0] matrixC17_30; +output [`DWIDTH-1:0] matrixC17_31; +output [`DWIDTH-1:0] matrixC18_0; +output [`DWIDTH-1:0] matrixC18_1; +output [`DWIDTH-1:0] matrixC18_2; +output [`DWIDTH-1:0] matrixC18_3; +output [`DWIDTH-1:0] matrixC18_4; +output [`DWIDTH-1:0] matrixC18_5; +output [`DWIDTH-1:0] matrixC18_6; +output [`DWIDTH-1:0] matrixC18_7; +output [`DWIDTH-1:0] matrixC18_8; +output [`DWIDTH-1:0] matrixC18_9; +output [`DWIDTH-1:0] matrixC18_10; +output [`DWIDTH-1:0] matrixC18_11; +output [`DWIDTH-1:0] matrixC18_12; +output [`DWIDTH-1:0] matrixC18_13; +output [`DWIDTH-1:0] matrixC18_14; +output [`DWIDTH-1:0] matrixC18_15; +output [`DWIDTH-1:0] matrixC18_16; +output [`DWIDTH-1:0] matrixC18_17; +output [`DWIDTH-1:0] matrixC18_18; +output [`DWIDTH-1:0] matrixC18_19; +output [`DWIDTH-1:0] matrixC18_20; +output [`DWIDTH-1:0] matrixC18_21; +output [`DWIDTH-1:0] matrixC18_22; +output [`DWIDTH-1:0] matrixC18_23; +output [`DWIDTH-1:0] matrixC18_24; +output [`DWIDTH-1:0] matrixC18_25; +output [`DWIDTH-1:0] matrixC18_26; +output [`DWIDTH-1:0] matrixC18_27; +output [`DWIDTH-1:0] matrixC18_28; +output [`DWIDTH-1:0] matrixC18_29; +output [`DWIDTH-1:0] matrixC18_30; +output [`DWIDTH-1:0] matrixC18_31; +output [`DWIDTH-1:0] matrixC19_0; +output [`DWIDTH-1:0] matrixC19_1; +output [`DWIDTH-1:0] matrixC19_2; +output [`DWIDTH-1:0] matrixC19_3; +output [`DWIDTH-1:0] matrixC19_4; +output [`DWIDTH-1:0] matrixC19_5; +output [`DWIDTH-1:0] matrixC19_6; +output [`DWIDTH-1:0] matrixC19_7; +output [`DWIDTH-1:0] matrixC19_8; +output [`DWIDTH-1:0] matrixC19_9; +output [`DWIDTH-1:0] matrixC19_10; +output [`DWIDTH-1:0] matrixC19_11; +output [`DWIDTH-1:0] matrixC19_12; +output [`DWIDTH-1:0] matrixC19_13; +output [`DWIDTH-1:0] matrixC19_14; +output [`DWIDTH-1:0] matrixC19_15; +output [`DWIDTH-1:0] matrixC19_16; +output [`DWIDTH-1:0] matrixC19_17; +output [`DWIDTH-1:0] matrixC19_18; +output [`DWIDTH-1:0] matrixC19_19; +output [`DWIDTH-1:0] matrixC19_20; +output [`DWIDTH-1:0] matrixC19_21; +output [`DWIDTH-1:0] matrixC19_22; +output [`DWIDTH-1:0] matrixC19_23; +output [`DWIDTH-1:0] matrixC19_24; +output [`DWIDTH-1:0] matrixC19_25; +output [`DWIDTH-1:0] matrixC19_26; +output [`DWIDTH-1:0] matrixC19_27; +output [`DWIDTH-1:0] matrixC19_28; +output [`DWIDTH-1:0] matrixC19_29; +output [`DWIDTH-1:0] matrixC19_30; +output [`DWIDTH-1:0] matrixC19_31; +output [`DWIDTH-1:0] matrixC20_0; +output [`DWIDTH-1:0] matrixC20_1; +output [`DWIDTH-1:0] matrixC20_2; +output [`DWIDTH-1:0] matrixC20_3; +output [`DWIDTH-1:0] matrixC20_4; +output [`DWIDTH-1:0] matrixC20_5; +output [`DWIDTH-1:0] matrixC20_6; +output [`DWIDTH-1:0] matrixC20_7; +output [`DWIDTH-1:0] matrixC20_8; +output [`DWIDTH-1:0] matrixC20_9; +output [`DWIDTH-1:0] matrixC20_10; +output [`DWIDTH-1:0] matrixC20_11; +output [`DWIDTH-1:0] matrixC20_12; +output [`DWIDTH-1:0] matrixC20_13; +output [`DWIDTH-1:0] matrixC20_14; +output [`DWIDTH-1:0] matrixC20_15; +output [`DWIDTH-1:0] matrixC20_16; +output [`DWIDTH-1:0] matrixC20_17; +output [`DWIDTH-1:0] matrixC20_18; +output [`DWIDTH-1:0] matrixC20_19; +output [`DWIDTH-1:0] matrixC20_20; +output [`DWIDTH-1:0] matrixC20_21; +output [`DWIDTH-1:0] matrixC20_22; +output [`DWIDTH-1:0] matrixC20_23; +output [`DWIDTH-1:0] matrixC20_24; +output [`DWIDTH-1:0] matrixC20_25; +output [`DWIDTH-1:0] matrixC20_26; +output [`DWIDTH-1:0] matrixC20_27; +output [`DWIDTH-1:0] matrixC20_28; +output [`DWIDTH-1:0] matrixC20_29; +output [`DWIDTH-1:0] matrixC20_30; +output [`DWIDTH-1:0] matrixC20_31; +output [`DWIDTH-1:0] matrixC21_0; +output [`DWIDTH-1:0] matrixC21_1; +output [`DWIDTH-1:0] matrixC21_2; +output [`DWIDTH-1:0] matrixC21_3; +output [`DWIDTH-1:0] matrixC21_4; +output [`DWIDTH-1:0] matrixC21_5; +output [`DWIDTH-1:0] matrixC21_6; +output [`DWIDTH-1:0] matrixC21_7; +output [`DWIDTH-1:0] matrixC21_8; +output [`DWIDTH-1:0] matrixC21_9; +output [`DWIDTH-1:0] matrixC21_10; +output [`DWIDTH-1:0] matrixC21_11; +output [`DWIDTH-1:0] matrixC21_12; +output [`DWIDTH-1:0] matrixC21_13; +output [`DWIDTH-1:0] matrixC21_14; +output [`DWIDTH-1:0] matrixC21_15; +output [`DWIDTH-1:0] matrixC21_16; +output [`DWIDTH-1:0] matrixC21_17; +output [`DWIDTH-1:0] matrixC21_18; +output [`DWIDTH-1:0] matrixC21_19; +output [`DWIDTH-1:0] matrixC21_20; +output [`DWIDTH-1:0] matrixC21_21; +output [`DWIDTH-1:0] matrixC21_22; +output [`DWIDTH-1:0] matrixC21_23; +output [`DWIDTH-1:0] matrixC21_24; +output [`DWIDTH-1:0] matrixC21_25; +output [`DWIDTH-1:0] matrixC21_26; +output [`DWIDTH-1:0] matrixC21_27; +output [`DWIDTH-1:0] matrixC21_28; +output [`DWIDTH-1:0] matrixC21_29; +output [`DWIDTH-1:0] matrixC21_30; +output [`DWIDTH-1:0] matrixC21_31; +output [`DWIDTH-1:0] matrixC22_0; +output [`DWIDTH-1:0] matrixC22_1; +output [`DWIDTH-1:0] matrixC22_2; +output [`DWIDTH-1:0] matrixC22_3; +output [`DWIDTH-1:0] matrixC22_4; +output [`DWIDTH-1:0] matrixC22_5; +output [`DWIDTH-1:0] matrixC22_6; +output [`DWIDTH-1:0] matrixC22_7; +output [`DWIDTH-1:0] matrixC22_8; +output [`DWIDTH-1:0] matrixC22_9; +output [`DWIDTH-1:0] matrixC22_10; +output [`DWIDTH-1:0] matrixC22_11; +output [`DWIDTH-1:0] matrixC22_12; +output [`DWIDTH-1:0] matrixC22_13; +output [`DWIDTH-1:0] matrixC22_14; +output [`DWIDTH-1:0] matrixC22_15; +output [`DWIDTH-1:0] matrixC22_16; +output [`DWIDTH-1:0] matrixC22_17; +output [`DWIDTH-1:0] matrixC22_18; +output [`DWIDTH-1:0] matrixC22_19; +output [`DWIDTH-1:0] matrixC22_20; +output [`DWIDTH-1:0] matrixC22_21; +output [`DWIDTH-1:0] matrixC22_22; +output [`DWIDTH-1:0] matrixC22_23; +output [`DWIDTH-1:0] matrixC22_24; +output [`DWIDTH-1:0] matrixC22_25; +output [`DWIDTH-1:0] matrixC22_26; +output [`DWIDTH-1:0] matrixC22_27; +output [`DWIDTH-1:0] matrixC22_28; +output [`DWIDTH-1:0] matrixC22_29; +output [`DWIDTH-1:0] matrixC22_30; +output [`DWIDTH-1:0] matrixC22_31; +output [`DWIDTH-1:0] matrixC23_0; +output [`DWIDTH-1:0] matrixC23_1; +output [`DWIDTH-1:0] matrixC23_2; +output [`DWIDTH-1:0] matrixC23_3; +output [`DWIDTH-1:0] matrixC23_4; +output [`DWIDTH-1:0] matrixC23_5; +output [`DWIDTH-1:0] matrixC23_6; +output [`DWIDTH-1:0] matrixC23_7; +output [`DWIDTH-1:0] matrixC23_8; +output [`DWIDTH-1:0] matrixC23_9; +output [`DWIDTH-1:0] matrixC23_10; +output [`DWIDTH-1:0] matrixC23_11; +output [`DWIDTH-1:0] matrixC23_12; +output [`DWIDTH-1:0] matrixC23_13; +output [`DWIDTH-1:0] matrixC23_14; +output [`DWIDTH-1:0] matrixC23_15; +output [`DWIDTH-1:0] matrixC23_16; +output [`DWIDTH-1:0] matrixC23_17; +output [`DWIDTH-1:0] matrixC23_18; +output [`DWIDTH-1:0] matrixC23_19; +output [`DWIDTH-1:0] matrixC23_20; +output [`DWIDTH-1:0] matrixC23_21; +output [`DWIDTH-1:0] matrixC23_22; +output [`DWIDTH-1:0] matrixC23_23; +output [`DWIDTH-1:0] matrixC23_24; +output [`DWIDTH-1:0] matrixC23_25; +output [`DWIDTH-1:0] matrixC23_26; +output [`DWIDTH-1:0] matrixC23_27; +output [`DWIDTH-1:0] matrixC23_28; +output [`DWIDTH-1:0] matrixC23_29; +output [`DWIDTH-1:0] matrixC23_30; +output [`DWIDTH-1:0] matrixC23_31; +output [`DWIDTH-1:0] matrixC24_0; +output [`DWIDTH-1:0] matrixC24_1; +output [`DWIDTH-1:0] matrixC24_2; +output [`DWIDTH-1:0] matrixC24_3; +output [`DWIDTH-1:0] matrixC24_4; +output [`DWIDTH-1:0] matrixC24_5; +output [`DWIDTH-1:0] matrixC24_6; +output [`DWIDTH-1:0] matrixC24_7; +output [`DWIDTH-1:0] matrixC24_8; +output [`DWIDTH-1:0] matrixC24_9; +output [`DWIDTH-1:0] matrixC24_10; +output [`DWIDTH-1:0] matrixC24_11; +output [`DWIDTH-1:0] matrixC24_12; +output [`DWIDTH-1:0] matrixC24_13; +output [`DWIDTH-1:0] matrixC24_14; +output [`DWIDTH-1:0] matrixC24_15; +output [`DWIDTH-1:0] matrixC24_16; +output [`DWIDTH-1:0] matrixC24_17; +output [`DWIDTH-1:0] matrixC24_18; +output [`DWIDTH-1:0] matrixC24_19; +output [`DWIDTH-1:0] matrixC24_20; +output [`DWIDTH-1:0] matrixC24_21; +output [`DWIDTH-1:0] matrixC24_22; +output [`DWIDTH-1:0] matrixC24_23; +output [`DWIDTH-1:0] matrixC24_24; +output [`DWIDTH-1:0] matrixC24_25; +output [`DWIDTH-1:0] matrixC24_26; +output [`DWIDTH-1:0] matrixC24_27; +output [`DWIDTH-1:0] matrixC24_28; +output [`DWIDTH-1:0] matrixC24_29; +output [`DWIDTH-1:0] matrixC24_30; +output [`DWIDTH-1:0] matrixC24_31; +output [`DWIDTH-1:0] matrixC25_0; +output [`DWIDTH-1:0] matrixC25_1; +output [`DWIDTH-1:0] matrixC25_2; +output [`DWIDTH-1:0] matrixC25_3; +output [`DWIDTH-1:0] matrixC25_4; +output [`DWIDTH-1:0] matrixC25_5; +output [`DWIDTH-1:0] matrixC25_6; +output [`DWIDTH-1:0] matrixC25_7; +output [`DWIDTH-1:0] matrixC25_8; +output [`DWIDTH-1:0] matrixC25_9; +output [`DWIDTH-1:0] matrixC25_10; +output [`DWIDTH-1:0] matrixC25_11; +output [`DWIDTH-1:0] matrixC25_12; +output [`DWIDTH-1:0] matrixC25_13; +output [`DWIDTH-1:0] matrixC25_14; +output [`DWIDTH-1:0] matrixC25_15; +output [`DWIDTH-1:0] matrixC25_16; +output [`DWIDTH-1:0] matrixC25_17; +output [`DWIDTH-1:0] matrixC25_18; +output [`DWIDTH-1:0] matrixC25_19; +output [`DWIDTH-1:0] matrixC25_20; +output [`DWIDTH-1:0] matrixC25_21; +output [`DWIDTH-1:0] matrixC25_22; +output [`DWIDTH-1:0] matrixC25_23; +output [`DWIDTH-1:0] matrixC25_24; +output [`DWIDTH-1:0] matrixC25_25; +output [`DWIDTH-1:0] matrixC25_26; +output [`DWIDTH-1:0] matrixC25_27; +output [`DWIDTH-1:0] matrixC25_28; +output [`DWIDTH-1:0] matrixC25_29; +output [`DWIDTH-1:0] matrixC25_30; +output [`DWIDTH-1:0] matrixC25_31; +output [`DWIDTH-1:0] matrixC26_0; +output [`DWIDTH-1:0] matrixC26_1; +output [`DWIDTH-1:0] matrixC26_2; +output [`DWIDTH-1:0] matrixC26_3; +output [`DWIDTH-1:0] matrixC26_4; +output [`DWIDTH-1:0] matrixC26_5; +output [`DWIDTH-1:0] matrixC26_6; +output [`DWIDTH-1:0] matrixC26_7; +output [`DWIDTH-1:0] matrixC26_8; +output [`DWIDTH-1:0] matrixC26_9; +output [`DWIDTH-1:0] matrixC26_10; +output [`DWIDTH-1:0] matrixC26_11; +output [`DWIDTH-1:0] matrixC26_12; +output [`DWIDTH-1:0] matrixC26_13; +output [`DWIDTH-1:0] matrixC26_14; +output [`DWIDTH-1:0] matrixC26_15; +output [`DWIDTH-1:0] matrixC26_16; +output [`DWIDTH-1:0] matrixC26_17; +output [`DWIDTH-1:0] matrixC26_18; +output [`DWIDTH-1:0] matrixC26_19; +output [`DWIDTH-1:0] matrixC26_20; +output [`DWIDTH-1:0] matrixC26_21; +output [`DWIDTH-1:0] matrixC26_22; +output [`DWIDTH-1:0] matrixC26_23; +output [`DWIDTH-1:0] matrixC26_24; +output [`DWIDTH-1:0] matrixC26_25; +output [`DWIDTH-1:0] matrixC26_26; +output [`DWIDTH-1:0] matrixC26_27; +output [`DWIDTH-1:0] matrixC26_28; +output [`DWIDTH-1:0] matrixC26_29; +output [`DWIDTH-1:0] matrixC26_30; +output [`DWIDTH-1:0] matrixC26_31; +output [`DWIDTH-1:0] matrixC27_0; +output [`DWIDTH-1:0] matrixC27_1; +output [`DWIDTH-1:0] matrixC27_2; +output [`DWIDTH-1:0] matrixC27_3; +output [`DWIDTH-1:0] matrixC27_4; +output [`DWIDTH-1:0] matrixC27_5; +output [`DWIDTH-1:0] matrixC27_6; +output [`DWIDTH-1:0] matrixC27_7; +output [`DWIDTH-1:0] matrixC27_8; +output [`DWIDTH-1:0] matrixC27_9; +output [`DWIDTH-1:0] matrixC27_10; +output [`DWIDTH-1:0] matrixC27_11; +output [`DWIDTH-1:0] matrixC27_12; +output [`DWIDTH-1:0] matrixC27_13; +output [`DWIDTH-1:0] matrixC27_14; +output [`DWIDTH-1:0] matrixC27_15; +output [`DWIDTH-1:0] matrixC27_16; +output [`DWIDTH-1:0] matrixC27_17; +output [`DWIDTH-1:0] matrixC27_18; +output [`DWIDTH-1:0] matrixC27_19; +output [`DWIDTH-1:0] matrixC27_20; +output [`DWIDTH-1:0] matrixC27_21; +output [`DWIDTH-1:0] matrixC27_22; +output [`DWIDTH-1:0] matrixC27_23; +output [`DWIDTH-1:0] matrixC27_24; +output [`DWIDTH-1:0] matrixC27_25; +output [`DWIDTH-1:0] matrixC27_26; +output [`DWIDTH-1:0] matrixC27_27; +output [`DWIDTH-1:0] matrixC27_28; +output [`DWIDTH-1:0] matrixC27_29; +output [`DWIDTH-1:0] matrixC27_30; +output [`DWIDTH-1:0] matrixC27_31; +output [`DWIDTH-1:0] matrixC28_0; +output [`DWIDTH-1:0] matrixC28_1; +output [`DWIDTH-1:0] matrixC28_2; +output [`DWIDTH-1:0] matrixC28_3; +output [`DWIDTH-1:0] matrixC28_4; +output [`DWIDTH-1:0] matrixC28_5; +output [`DWIDTH-1:0] matrixC28_6; +output [`DWIDTH-1:0] matrixC28_7; +output [`DWIDTH-1:0] matrixC28_8; +output [`DWIDTH-1:0] matrixC28_9; +output [`DWIDTH-1:0] matrixC28_10; +output [`DWIDTH-1:0] matrixC28_11; +output [`DWIDTH-1:0] matrixC28_12; +output [`DWIDTH-1:0] matrixC28_13; +output [`DWIDTH-1:0] matrixC28_14; +output [`DWIDTH-1:0] matrixC28_15; +output [`DWIDTH-1:0] matrixC28_16; +output [`DWIDTH-1:0] matrixC28_17; +output [`DWIDTH-1:0] matrixC28_18; +output [`DWIDTH-1:0] matrixC28_19; +output [`DWIDTH-1:0] matrixC28_20; +output [`DWIDTH-1:0] matrixC28_21; +output [`DWIDTH-1:0] matrixC28_22; +output [`DWIDTH-1:0] matrixC28_23; +output [`DWIDTH-1:0] matrixC28_24; +output [`DWIDTH-1:0] matrixC28_25; +output [`DWIDTH-1:0] matrixC28_26; +output [`DWIDTH-1:0] matrixC28_27; +output [`DWIDTH-1:0] matrixC28_28; +output [`DWIDTH-1:0] matrixC28_29; +output [`DWIDTH-1:0] matrixC28_30; +output [`DWIDTH-1:0] matrixC28_31; +output [`DWIDTH-1:0] matrixC29_0; +output [`DWIDTH-1:0] matrixC29_1; +output [`DWIDTH-1:0] matrixC29_2; +output [`DWIDTH-1:0] matrixC29_3; +output [`DWIDTH-1:0] matrixC29_4; +output [`DWIDTH-1:0] matrixC29_5; +output [`DWIDTH-1:0] matrixC29_6; +output [`DWIDTH-1:0] matrixC29_7; +output [`DWIDTH-1:0] matrixC29_8; +output [`DWIDTH-1:0] matrixC29_9; +output [`DWIDTH-1:0] matrixC29_10; +output [`DWIDTH-1:0] matrixC29_11; +output [`DWIDTH-1:0] matrixC29_12; +output [`DWIDTH-1:0] matrixC29_13; +output [`DWIDTH-1:0] matrixC29_14; +output [`DWIDTH-1:0] matrixC29_15; +output [`DWIDTH-1:0] matrixC29_16; +output [`DWIDTH-1:0] matrixC29_17; +output [`DWIDTH-1:0] matrixC29_18; +output [`DWIDTH-1:0] matrixC29_19; +output [`DWIDTH-1:0] matrixC29_20; +output [`DWIDTH-1:0] matrixC29_21; +output [`DWIDTH-1:0] matrixC29_22; +output [`DWIDTH-1:0] matrixC29_23; +output [`DWIDTH-1:0] matrixC29_24; +output [`DWIDTH-1:0] matrixC29_25; +output [`DWIDTH-1:0] matrixC29_26; +output [`DWIDTH-1:0] matrixC29_27; +output [`DWIDTH-1:0] matrixC29_28; +output [`DWIDTH-1:0] matrixC29_29; +output [`DWIDTH-1:0] matrixC29_30; +output [`DWIDTH-1:0] matrixC29_31; +output [`DWIDTH-1:0] matrixC30_0; +output [`DWIDTH-1:0] matrixC30_1; +output [`DWIDTH-1:0] matrixC30_2; +output [`DWIDTH-1:0] matrixC30_3; +output [`DWIDTH-1:0] matrixC30_4; +output [`DWIDTH-1:0] matrixC30_5; +output [`DWIDTH-1:0] matrixC30_6; +output [`DWIDTH-1:0] matrixC30_7; +output [`DWIDTH-1:0] matrixC30_8; +output [`DWIDTH-1:0] matrixC30_9; +output [`DWIDTH-1:0] matrixC30_10; +output [`DWIDTH-1:0] matrixC30_11; +output [`DWIDTH-1:0] matrixC30_12; +output [`DWIDTH-1:0] matrixC30_13; +output [`DWIDTH-1:0] matrixC30_14; +output [`DWIDTH-1:0] matrixC30_15; +output [`DWIDTH-1:0] matrixC30_16; +output [`DWIDTH-1:0] matrixC30_17; +output [`DWIDTH-1:0] matrixC30_18; +output [`DWIDTH-1:0] matrixC30_19; +output [`DWIDTH-1:0] matrixC30_20; +output [`DWIDTH-1:0] matrixC30_21; +output [`DWIDTH-1:0] matrixC30_22; +output [`DWIDTH-1:0] matrixC30_23; +output [`DWIDTH-1:0] matrixC30_24; +output [`DWIDTH-1:0] matrixC30_25; +output [`DWIDTH-1:0] matrixC30_26; +output [`DWIDTH-1:0] matrixC30_27; +output [`DWIDTH-1:0] matrixC30_28; +output [`DWIDTH-1:0] matrixC30_29; +output [`DWIDTH-1:0] matrixC30_30; +output [`DWIDTH-1:0] matrixC30_31; +output [`DWIDTH-1:0] matrixC31_0; +output [`DWIDTH-1:0] matrixC31_1; +output [`DWIDTH-1:0] matrixC31_2; +output [`DWIDTH-1:0] matrixC31_3; +output [`DWIDTH-1:0] matrixC31_4; +output [`DWIDTH-1:0] matrixC31_5; +output [`DWIDTH-1:0] matrixC31_6; +output [`DWIDTH-1:0] matrixC31_7; +output [`DWIDTH-1:0] matrixC31_8; +output [`DWIDTH-1:0] matrixC31_9; +output [`DWIDTH-1:0] matrixC31_10; +output [`DWIDTH-1:0] matrixC31_11; +output [`DWIDTH-1:0] matrixC31_12; +output [`DWIDTH-1:0] matrixC31_13; +output [`DWIDTH-1:0] matrixC31_14; +output [`DWIDTH-1:0] matrixC31_15; +output [`DWIDTH-1:0] matrixC31_16; +output [`DWIDTH-1:0] matrixC31_17; +output [`DWIDTH-1:0] matrixC31_18; +output [`DWIDTH-1:0] matrixC31_19; +output [`DWIDTH-1:0] matrixC31_20; +output [`DWIDTH-1:0] matrixC31_21; +output [`DWIDTH-1:0] matrixC31_22; +output [`DWIDTH-1:0] matrixC31_23; +output [`DWIDTH-1:0] matrixC31_24; +output [`DWIDTH-1:0] matrixC31_25; +output [`DWIDTH-1:0] matrixC31_26; +output [`DWIDTH-1:0] matrixC31_27; +output [`DWIDTH-1:0] matrixC31_28; +output [`DWIDTH-1:0] matrixC31_29; +output [`DWIDTH-1:0] matrixC31_30; +output [`DWIDTH-1:0] matrixC31_31; + +output [`MAT_MUL_SIZE*`DWIDTH-1:0] a_data_out; +output [`MAT_MUL_SIZE*`DWIDTH-1:0] b_data_out; + +wire [`DWIDTH-1:0] a0_0to0_1, a0_1to0_2, a0_2to0_3, a0_3to0_4, a0_4to0_5, a0_5to0_6, a0_6to0_7, a0_7to0_8, a0_8to0_9, a0_9to0_10, a0_10to0_11, a0_11to0_12, a0_12to0_13, a0_13to0_14, a0_14to0_15, a0_15to0_16, a0_16to0_17, a0_17to0_18, a0_18to0_19, a0_19to0_20, a0_20to0_21, a0_21to0_22, a0_22to0_23, a0_23to0_24, a0_24to0_25, a0_25to0_26, a0_26to0_27, a0_27to0_28, a0_28to0_29, a0_29to0_30, a0_30to0_31, a0_31to0_32; +wire [`DWIDTH-1:0] a1_0to1_1, a1_1to1_2, a1_2to1_3, a1_3to1_4, a1_4to1_5, a1_5to1_6, a1_6to1_7, a1_7to1_8, a1_8to1_9, a1_9to1_10, a1_10to1_11, a1_11to1_12, a1_12to1_13, a1_13to1_14, a1_14to1_15, a1_15to1_16, a1_16to1_17, a1_17to1_18, a1_18to1_19, a1_19to1_20, a1_20to1_21, a1_21to1_22, a1_22to1_23, a1_23to1_24, a1_24to1_25, a1_25to1_26, a1_26to1_27, a1_27to1_28, a1_28to1_29, a1_29to1_30, a1_30to1_31, a1_31to1_32; +wire [`DWIDTH-1:0] a2_0to2_1, a2_1to2_2, a2_2to2_3, a2_3to2_4, a2_4to2_5, a2_5to2_6, a2_6to2_7, a2_7to2_8, a2_8to2_9, a2_9to2_10, a2_10to2_11, a2_11to2_12, a2_12to2_13, a2_13to2_14, a2_14to2_15, a2_15to2_16, a2_16to2_17, a2_17to2_18, a2_18to2_19, a2_19to2_20, a2_20to2_21, a2_21to2_22, a2_22to2_23, a2_23to2_24, a2_24to2_25, a2_25to2_26, a2_26to2_27, a2_27to2_28, a2_28to2_29, a2_29to2_30, a2_30to2_31, a2_31to2_32; +wire [`DWIDTH-1:0] a3_0to3_1, a3_1to3_2, a3_2to3_3, a3_3to3_4, a3_4to3_5, a3_5to3_6, a3_6to3_7, a3_7to3_8, a3_8to3_9, a3_9to3_10, a3_10to3_11, a3_11to3_12, a3_12to3_13, a3_13to3_14, a3_14to3_15, a3_15to3_16, a3_16to3_17, a3_17to3_18, a3_18to3_19, a3_19to3_20, a3_20to3_21, a3_21to3_22, a3_22to3_23, a3_23to3_24, a3_24to3_25, a3_25to3_26, a3_26to3_27, a3_27to3_28, a3_28to3_29, a3_29to3_30, a3_30to3_31, a3_31to3_32; +wire [`DWIDTH-1:0] a4_0to4_1, a4_1to4_2, a4_2to4_3, a4_3to4_4, a4_4to4_5, a4_5to4_6, a4_6to4_7, a4_7to4_8, a4_8to4_9, a4_9to4_10, a4_10to4_11, a4_11to4_12, a4_12to4_13, a4_13to4_14, a4_14to4_15, a4_15to4_16, a4_16to4_17, a4_17to4_18, a4_18to4_19, a4_19to4_20, a4_20to4_21, a4_21to4_22, a4_22to4_23, a4_23to4_24, a4_24to4_25, a4_25to4_26, a4_26to4_27, a4_27to4_28, a4_28to4_29, a4_29to4_30, a4_30to4_31, a4_31to4_32; +wire [`DWIDTH-1:0] a5_0to5_1, a5_1to5_2, a5_2to5_3, a5_3to5_4, a5_4to5_5, a5_5to5_6, a5_6to5_7, a5_7to5_8, a5_8to5_9, a5_9to5_10, a5_10to5_11, a5_11to5_12, a5_12to5_13, a5_13to5_14, a5_14to5_15, a5_15to5_16, a5_16to5_17, a5_17to5_18, a5_18to5_19, a5_19to5_20, a5_20to5_21, a5_21to5_22, a5_22to5_23, a5_23to5_24, a5_24to5_25, a5_25to5_26, a5_26to5_27, a5_27to5_28, a5_28to5_29, a5_29to5_30, a5_30to5_31, a5_31to5_32; +wire [`DWIDTH-1:0] a6_0to6_1, a6_1to6_2, a6_2to6_3, a6_3to6_4, a6_4to6_5, a6_5to6_6, a6_6to6_7, a6_7to6_8, a6_8to6_9, a6_9to6_10, a6_10to6_11, a6_11to6_12, a6_12to6_13, a6_13to6_14, a6_14to6_15, a6_15to6_16, a6_16to6_17, a6_17to6_18, a6_18to6_19, a6_19to6_20, a6_20to6_21, a6_21to6_22, a6_22to6_23, a6_23to6_24, a6_24to6_25, a6_25to6_26, a6_26to6_27, a6_27to6_28, a6_28to6_29, a6_29to6_30, a6_30to6_31, a6_31to6_32; +wire [`DWIDTH-1:0] a7_0to7_1, a7_1to7_2, a7_2to7_3, a7_3to7_4, a7_4to7_5, a7_5to7_6, a7_6to7_7, a7_7to7_8, a7_8to7_9, a7_9to7_10, a7_10to7_11, a7_11to7_12, a7_12to7_13, a7_13to7_14, a7_14to7_15, a7_15to7_16, a7_16to7_17, a7_17to7_18, a7_18to7_19, a7_19to7_20, a7_20to7_21, a7_21to7_22, a7_22to7_23, a7_23to7_24, a7_24to7_25, a7_25to7_26, a7_26to7_27, a7_27to7_28, a7_28to7_29, a7_29to7_30, a7_30to7_31, a7_31to7_32; +wire [`DWIDTH-1:0] a8_0to8_1, a8_1to8_2, a8_2to8_3, a8_3to8_4, a8_4to8_5, a8_5to8_6, a8_6to8_7, a8_7to8_8, a8_8to8_9, a8_9to8_10, a8_10to8_11, a8_11to8_12, a8_12to8_13, a8_13to8_14, a8_14to8_15, a8_15to8_16, a8_16to8_17, a8_17to8_18, a8_18to8_19, a8_19to8_20, a8_20to8_21, a8_21to8_22, a8_22to8_23, a8_23to8_24, a8_24to8_25, a8_25to8_26, a8_26to8_27, a8_27to8_28, a8_28to8_29, a8_29to8_30, a8_30to8_31, a8_31to8_32; +wire [`DWIDTH-1:0] a9_0to9_1, a9_1to9_2, a9_2to9_3, a9_3to9_4, a9_4to9_5, a9_5to9_6, a9_6to9_7, a9_7to9_8, a9_8to9_9, a9_9to9_10, a9_10to9_11, a9_11to9_12, a9_12to9_13, a9_13to9_14, a9_14to9_15, a9_15to9_16, a9_16to9_17, a9_17to9_18, a9_18to9_19, a9_19to9_20, a9_20to9_21, a9_21to9_22, a9_22to9_23, a9_23to9_24, a9_24to9_25, a9_25to9_26, a9_26to9_27, a9_27to9_28, a9_28to9_29, a9_29to9_30, a9_30to9_31, a9_31to9_32; +wire [`DWIDTH-1:0] a10_0to10_1, a10_1to10_2, a10_2to10_3, a10_3to10_4, a10_4to10_5, a10_5to10_6, a10_6to10_7, a10_7to10_8, a10_8to10_9, a10_9to10_10, a10_10to10_11, a10_11to10_12, a10_12to10_13, a10_13to10_14, a10_14to10_15, a10_15to10_16, a10_16to10_17, a10_17to10_18, a10_18to10_19, a10_19to10_20, a10_20to10_21, a10_21to10_22, a10_22to10_23, a10_23to10_24, a10_24to10_25, a10_25to10_26, a10_26to10_27, a10_27to10_28, a10_28to10_29, a10_29to10_30, a10_30to10_31, a10_31to10_32; +wire [`DWIDTH-1:0] a11_0to11_1, a11_1to11_2, a11_2to11_3, a11_3to11_4, a11_4to11_5, a11_5to11_6, a11_6to11_7, a11_7to11_8, a11_8to11_9, a11_9to11_10, a11_10to11_11, a11_11to11_12, a11_12to11_13, a11_13to11_14, a11_14to11_15, a11_15to11_16, a11_16to11_17, a11_17to11_18, a11_18to11_19, a11_19to11_20, a11_20to11_21, a11_21to11_22, a11_22to11_23, a11_23to11_24, a11_24to11_25, a11_25to11_26, a11_26to11_27, a11_27to11_28, a11_28to11_29, a11_29to11_30, a11_30to11_31, a11_31to11_32; +wire [`DWIDTH-1:0] a12_0to12_1, a12_1to12_2, a12_2to12_3, a12_3to12_4, a12_4to12_5, a12_5to12_6, a12_6to12_7, a12_7to12_8, a12_8to12_9, a12_9to12_10, a12_10to12_11, a12_11to12_12, a12_12to12_13, a12_13to12_14, a12_14to12_15, a12_15to12_16, a12_16to12_17, a12_17to12_18, a12_18to12_19, a12_19to12_20, a12_20to12_21, a12_21to12_22, a12_22to12_23, a12_23to12_24, a12_24to12_25, a12_25to12_26, a12_26to12_27, a12_27to12_28, a12_28to12_29, a12_29to12_30, a12_30to12_31, a12_31to12_32; +wire [`DWIDTH-1:0] a13_0to13_1, a13_1to13_2, a13_2to13_3, a13_3to13_4, a13_4to13_5, a13_5to13_6, a13_6to13_7, a13_7to13_8, a13_8to13_9, a13_9to13_10, a13_10to13_11, a13_11to13_12, a13_12to13_13, a13_13to13_14, a13_14to13_15, a13_15to13_16, a13_16to13_17, a13_17to13_18, a13_18to13_19, a13_19to13_20, a13_20to13_21, a13_21to13_22, a13_22to13_23, a13_23to13_24, a13_24to13_25, a13_25to13_26, a13_26to13_27, a13_27to13_28, a13_28to13_29, a13_29to13_30, a13_30to13_31, a13_31to13_32; +wire [`DWIDTH-1:0] a14_0to14_1, a14_1to14_2, a14_2to14_3, a14_3to14_4, a14_4to14_5, a14_5to14_6, a14_6to14_7, a14_7to14_8, a14_8to14_9, a14_9to14_10, a14_10to14_11, a14_11to14_12, a14_12to14_13, a14_13to14_14, a14_14to14_15, a14_15to14_16, a14_16to14_17, a14_17to14_18, a14_18to14_19, a14_19to14_20, a14_20to14_21, a14_21to14_22, a14_22to14_23, a14_23to14_24, a14_24to14_25, a14_25to14_26, a14_26to14_27, a14_27to14_28, a14_28to14_29, a14_29to14_30, a14_30to14_31, a14_31to14_32; +wire [`DWIDTH-1:0] a15_0to15_1, a15_1to15_2, a15_2to15_3, a15_3to15_4, a15_4to15_5, a15_5to15_6, a15_6to15_7, a15_7to15_8, a15_8to15_9, a15_9to15_10, a15_10to15_11, a15_11to15_12, a15_12to15_13, a15_13to15_14, a15_14to15_15, a15_15to15_16, a15_16to15_17, a15_17to15_18, a15_18to15_19, a15_19to15_20, a15_20to15_21, a15_21to15_22, a15_22to15_23, a15_23to15_24, a15_24to15_25, a15_25to15_26, a15_26to15_27, a15_27to15_28, a15_28to15_29, a15_29to15_30, a15_30to15_31, a15_31to15_32; +wire [`DWIDTH-1:0] a16_0to16_1, a16_1to16_2, a16_2to16_3, a16_3to16_4, a16_4to16_5, a16_5to16_6, a16_6to16_7, a16_7to16_8, a16_8to16_9, a16_9to16_10, a16_10to16_11, a16_11to16_12, a16_12to16_13, a16_13to16_14, a16_14to16_15, a16_15to16_16, a16_16to16_17, a16_17to16_18, a16_18to16_19, a16_19to16_20, a16_20to16_21, a16_21to16_22, a16_22to16_23, a16_23to16_24, a16_24to16_25, a16_25to16_26, a16_26to16_27, a16_27to16_28, a16_28to16_29, a16_29to16_30, a16_30to16_31, a16_31to16_32; +wire [`DWIDTH-1:0] a17_0to17_1, a17_1to17_2, a17_2to17_3, a17_3to17_4, a17_4to17_5, a17_5to17_6, a17_6to17_7, a17_7to17_8, a17_8to17_9, a17_9to17_10, a17_10to17_11, a17_11to17_12, a17_12to17_13, a17_13to17_14, a17_14to17_15, a17_15to17_16, a17_16to17_17, a17_17to17_18, a17_18to17_19, a17_19to17_20, a17_20to17_21, a17_21to17_22, a17_22to17_23, a17_23to17_24, a17_24to17_25, a17_25to17_26, a17_26to17_27, a17_27to17_28, a17_28to17_29, a17_29to17_30, a17_30to17_31, a17_31to17_32; +wire [`DWIDTH-1:0] a18_0to18_1, a18_1to18_2, a18_2to18_3, a18_3to18_4, a18_4to18_5, a18_5to18_6, a18_6to18_7, a18_7to18_8, a18_8to18_9, a18_9to18_10, a18_10to18_11, a18_11to18_12, a18_12to18_13, a18_13to18_14, a18_14to18_15, a18_15to18_16, a18_16to18_17, a18_17to18_18, a18_18to18_19, a18_19to18_20, a18_20to18_21, a18_21to18_22, a18_22to18_23, a18_23to18_24, a18_24to18_25, a18_25to18_26, a18_26to18_27, a18_27to18_28, a18_28to18_29, a18_29to18_30, a18_30to18_31, a18_31to18_32; +wire [`DWIDTH-1:0] a19_0to19_1, a19_1to19_2, a19_2to19_3, a19_3to19_4, a19_4to19_5, a19_5to19_6, a19_6to19_7, a19_7to19_8, a19_8to19_9, a19_9to19_10, a19_10to19_11, a19_11to19_12, a19_12to19_13, a19_13to19_14, a19_14to19_15, a19_15to19_16, a19_16to19_17, a19_17to19_18, a19_18to19_19, a19_19to19_20, a19_20to19_21, a19_21to19_22, a19_22to19_23, a19_23to19_24, a19_24to19_25, a19_25to19_26, a19_26to19_27, a19_27to19_28, a19_28to19_29, a19_29to19_30, a19_30to19_31, a19_31to19_32; +wire [`DWIDTH-1:0] a20_0to20_1, a20_1to20_2, a20_2to20_3, a20_3to20_4, a20_4to20_5, a20_5to20_6, a20_6to20_7, a20_7to20_8, a20_8to20_9, a20_9to20_10, a20_10to20_11, a20_11to20_12, a20_12to20_13, a20_13to20_14, a20_14to20_15, a20_15to20_16, a20_16to20_17, a20_17to20_18, a20_18to20_19, a20_19to20_20, a20_20to20_21, a20_21to20_22, a20_22to20_23, a20_23to20_24, a20_24to20_25, a20_25to20_26, a20_26to20_27, a20_27to20_28, a20_28to20_29, a20_29to20_30, a20_30to20_31, a20_31to20_32; +wire [`DWIDTH-1:0] a21_0to21_1, a21_1to21_2, a21_2to21_3, a21_3to21_4, a21_4to21_5, a21_5to21_6, a21_6to21_7, a21_7to21_8, a21_8to21_9, a21_9to21_10, a21_10to21_11, a21_11to21_12, a21_12to21_13, a21_13to21_14, a21_14to21_15, a21_15to21_16, a21_16to21_17, a21_17to21_18, a21_18to21_19, a21_19to21_20, a21_20to21_21, a21_21to21_22, a21_22to21_23, a21_23to21_24, a21_24to21_25, a21_25to21_26, a21_26to21_27, a21_27to21_28, a21_28to21_29, a21_29to21_30, a21_30to21_31, a21_31to21_32; +wire [`DWIDTH-1:0] a22_0to22_1, a22_1to22_2, a22_2to22_3, a22_3to22_4, a22_4to22_5, a22_5to22_6, a22_6to22_7, a22_7to22_8, a22_8to22_9, a22_9to22_10, a22_10to22_11, a22_11to22_12, a22_12to22_13, a22_13to22_14, a22_14to22_15, a22_15to22_16, a22_16to22_17, a22_17to22_18, a22_18to22_19, a22_19to22_20, a22_20to22_21, a22_21to22_22, a22_22to22_23, a22_23to22_24, a22_24to22_25, a22_25to22_26, a22_26to22_27, a22_27to22_28, a22_28to22_29, a22_29to22_30, a22_30to22_31, a22_31to22_32; +wire [`DWIDTH-1:0] a23_0to23_1, a23_1to23_2, a23_2to23_3, a23_3to23_4, a23_4to23_5, a23_5to23_6, a23_6to23_7, a23_7to23_8, a23_8to23_9, a23_9to23_10, a23_10to23_11, a23_11to23_12, a23_12to23_13, a23_13to23_14, a23_14to23_15, a23_15to23_16, a23_16to23_17, a23_17to23_18, a23_18to23_19, a23_19to23_20, a23_20to23_21, a23_21to23_22, a23_22to23_23, a23_23to23_24, a23_24to23_25, a23_25to23_26, a23_26to23_27, a23_27to23_28, a23_28to23_29, a23_29to23_30, a23_30to23_31, a23_31to23_32; +wire [`DWIDTH-1:0] a24_0to24_1, a24_1to24_2, a24_2to24_3, a24_3to24_4, a24_4to24_5, a24_5to24_6, a24_6to24_7, a24_7to24_8, a24_8to24_9, a24_9to24_10, a24_10to24_11, a24_11to24_12, a24_12to24_13, a24_13to24_14, a24_14to24_15, a24_15to24_16, a24_16to24_17, a24_17to24_18, a24_18to24_19, a24_19to24_20, a24_20to24_21, a24_21to24_22, a24_22to24_23, a24_23to24_24, a24_24to24_25, a24_25to24_26, a24_26to24_27, a24_27to24_28, a24_28to24_29, a24_29to24_30, a24_30to24_31, a24_31to24_32; +wire [`DWIDTH-1:0] a25_0to25_1, a25_1to25_2, a25_2to25_3, a25_3to25_4, a25_4to25_5, a25_5to25_6, a25_6to25_7, a25_7to25_8, a25_8to25_9, a25_9to25_10, a25_10to25_11, a25_11to25_12, a25_12to25_13, a25_13to25_14, a25_14to25_15, a25_15to25_16, a25_16to25_17, a25_17to25_18, a25_18to25_19, a25_19to25_20, a25_20to25_21, a25_21to25_22, a25_22to25_23, a25_23to25_24, a25_24to25_25, a25_25to25_26, a25_26to25_27, a25_27to25_28, a25_28to25_29, a25_29to25_30, a25_30to25_31, a25_31to25_32; +wire [`DWIDTH-1:0] a26_0to26_1, a26_1to26_2, a26_2to26_3, a26_3to26_4, a26_4to26_5, a26_5to26_6, a26_6to26_7, a26_7to26_8, a26_8to26_9, a26_9to26_10, a26_10to26_11, a26_11to26_12, a26_12to26_13, a26_13to26_14, a26_14to26_15, a26_15to26_16, a26_16to26_17, a26_17to26_18, a26_18to26_19, a26_19to26_20, a26_20to26_21, a26_21to26_22, a26_22to26_23, a26_23to26_24, a26_24to26_25, a26_25to26_26, a26_26to26_27, a26_27to26_28, a26_28to26_29, a26_29to26_30, a26_30to26_31, a26_31to26_32; +wire [`DWIDTH-1:0] a27_0to27_1, a27_1to27_2, a27_2to27_3, a27_3to27_4, a27_4to27_5, a27_5to27_6, a27_6to27_7, a27_7to27_8, a27_8to27_9, a27_9to27_10, a27_10to27_11, a27_11to27_12, a27_12to27_13, a27_13to27_14, a27_14to27_15, a27_15to27_16, a27_16to27_17, a27_17to27_18, a27_18to27_19, a27_19to27_20, a27_20to27_21, a27_21to27_22, a27_22to27_23, a27_23to27_24, a27_24to27_25, a27_25to27_26, a27_26to27_27, a27_27to27_28, a27_28to27_29, a27_29to27_30, a27_30to27_31, a27_31to27_32; +wire [`DWIDTH-1:0] a28_0to28_1, a28_1to28_2, a28_2to28_3, a28_3to28_4, a28_4to28_5, a28_5to28_6, a28_6to28_7, a28_7to28_8, a28_8to28_9, a28_9to28_10, a28_10to28_11, a28_11to28_12, a28_12to28_13, a28_13to28_14, a28_14to28_15, a28_15to28_16, a28_16to28_17, a28_17to28_18, a28_18to28_19, a28_19to28_20, a28_20to28_21, a28_21to28_22, a28_22to28_23, a28_23to28_24, a28_24to28_25, a28_25to28_26, a28_26to28_27, a28_27to28_28, a28_28to28_29, a28_29to28_30, a28_30to28_31, a28_31to28_32; +wire [`DWIDTH-1:0] a29_0to29_1, a29_1to29_2, a29_2to29_3, a29_3to29_4, a29_4to29_5, a29_5to29_6, a29_6to29_7, a29_7to29_8, a29_8to29_9, a29_9to29_10, a29_10to29_11, a29_11to29_12, a29_12to29_13, a29_13to29_14, a29_14to29_15, a29_15to29_16, a29_16to29_17, a29_17to29_18, a29_18to29_19, a29_19to29_20, a29_20to29_21, a29_21to29_22, a29_22to29_23, a29_23to29_24, a29_24to29_25, a29_25to29_26, a29_26to29_27, a29_27to29_28, a29_28to29_29, a29_29to29_30, a29_30to29_31, a29_31to29_32; +wire [`DWIDTH-1:0] a30_0to30_1, a30_1to30_2, a30_2to30_3, a30_3to30_4, a30_4to30_5, a30_5to30_6, a30_6to30_7, a30_7to30_8, a30_8to30_9, a30_9to30_10, a30_10to30_11, a30_11to30_12, a30_12to30_13, a30_13to30_14, a30_14to30_15, a30_15to30_16, a30_16to30_17, a30_17to30_18, a30_18to30_19, a30_19to30_20, a30_20to30_21, a30_21to30_22, a30_22to30_23, a30_23to30_24, a30_24to30_25, a30_25to30_26, a30_26to30_27, a30_27to30_28, a30_28to30_29, a30_29to30_30, a30_30to30_31, a30_31to30_32; +wire [`DWIDTH-1:0] a31_0to31_1, a31_1to31_2, a31_2to31_3, a31_3to31_4, a31_4to31_5, a31_5to31_6, a31_6to31_7, a31_7to31_8, a31_8to31_9, a31_9to31_10, a31_10to31_11, a31_11to31_12, a31_12to31_13, a31_13to31_14, a31_14to31_15, a31_15to31_16, a31_16to31_17, a31_17to31_18, a31_18to31_19, a31_19to31_20, a31_20to31_21, a31_21to31_22, a31_22to31_23, a31_23to31_24, a31_24to31_25, a31_25to31_26, a31_26to31_27, a31_27to31_28, a31_28to31_29, a31_29to31_30, a31_30to31_31, a31_31to31_32; + +wire [`DWIDTH-1:0] b0_0to1_0, b1_0to2_0, b2_0to3_0, b3_0to4_0, b4_0to5_0, b5_0to6_0, b6_0to7_0, b7_0to8_0, b8_0to9_0, b9_0to10_0, b10_0to11_0, b11_0to12_0, b12_0to13_0, b13_0to14_0, b14_0to15_0, b15_0to16_0, b16_0to17_0, b17_0to18_0, b18_0to19_0, b19_0to20_0, b20_0to21_0, b21_0to22_0, b22_0to23_0, b23_0to24_0, b24_0to25_0, b25_0to26_0, b26_0to27_0, b27_0to28_0, b28_0to29_0, b29_0to30_0, b30_0to31_0, b31_0to32_0; +wire [`DWIDTH-1:0] b0_1to1_1, b1_1to2_1, b2_1to3_1, b3_1to4_1, b4_1to5_1, b5_1to6_1, b6_1to7_1, b7_1to8_1, b8_1to9_1, b9_1to10_1, b10_1to11_1, b11_1to12_1, b12_1to13_1, b13_1to14_1, b14_1to15_1, b15_1to16_1, b16_1to17_1, b17_1to18_1, b18_1to19_1, b19_1to20_1, b20_1to21_1, b21_1to22_1, b22_1to23_1, b23_1to24_1, b24_1to25_1, b25_1to26_1, b26_1to27_1, b27_1to28_1, b28_1to29_1, b29_1to30_1, b30_1to31_1, b31_1to32_1; +wire [`DWIDTH-1:0] b0_2to1_2, b1_2to2_2, b2_2to3_2, b3_2to4_2, b4_2to5_2, b5_2to6_2, b6_2to7_2, b7_2to8_2, b8_2to9_2, b9_2to10_2, b10_2to11_2, b11_2to12_2, b12_2to13_2, b13_2to14_2, b14_2to15_2, b15_2to16_2, b16_2to17_2, b17_2to18_2, b18_2to19_2, b19_2to20_2, b20_2to21_2, b21_2to22_2, b22_2to23_2, b23_2to24_2, b24_2to25_2, b25_2to26_2, b26_2to27_2, b27_2to28_2, b28_2to29_2, b29_2to30_2, b30_2to31_2, b31_2to32_2; +wire [`DWIDTH-1:0] b0_3to1_3, b1_3to2_3, b2_3to3_3, b3_3to4_3, b4_3to5_3, b5_3to6_3, b6_3to7_3, b7_3to8_3, b8_3to9_3, b9_3to10_3, b10_3to11_3, b11_3to12_3, b12_3to13_3, b13_3to14_3, b14_3to15_3, b15_3to16_3, b16_3to17_3, b17_3to18_3, b18_3to19_3, b19_3to20_3, b20_3to21_3, b21_3to22_3, b22_3to23_3, b23_3to24_3, b24_3to25_3, b25_3to26_3, b26_3to27_3, b27_3to28_3, b28_3to29_3, b29_3to30_3, b30_3to31_3, b31_3to32_3; +wire [`DWIDTH-1:0] b0_4to1_4, b1_4to2_4, b2_4to3_4, b3_4to4_4, b4_4to5_4, b5_4to6_4, b6_4to7_4, b7_4to8_4, b8_4to9_4, b9_4to10_4, b10_4to11_4, b11_4to12_4, b12_4to13_4, b13_4to14_4, b14_4to15_4, b15_4to16_4, b16_4to17_4, b17_4to18_4, b18_4to19_4, b19_4to20_4, b20_4to21_4, b21_4to22_4, b22_4to23_4, b23_4to24_4, b24_4to25_4, b25_4to26_4, b26_4to27_4, b27_4to28_4, b28_4to29_4, b29_4to30_4, b30_4to31_4, b31_4to32_4; +wire [`DWIDTH-1:0] b0_5to1_5, b1_5to2_5, b2_5to3_5, b3_5to4_5, b4_5to5_5, b5_5to6_5, b6_5to7_5, b7_5to8_5, b8_5to9_5, b9_5to10_5, b10_5to11_5, b11_5to12_5, b12_5to13_5, b13_5to14_5, b14_5to15_5, b15_5to16_5, b16_5to17_5, b17_5to18_5, b18_5to19_5, b19_5to20_5, b20_5to21_5, b21_5to22_5, b22_5to23_5, b23_5to24_5, b24_5to25_5, b25_5to26_5, b26_5to27_5, b27_5to28_5, b28_5to29_5, b29_5to30_5, b30_5to31_5, b31_5to32_5; +wire [`DWIDTH-1:0] b0_6to1_6, b1_6to2_6, b2_6to3_6, b3_6to4_6, b4_6to5_6, b5_6to6_6, b6_6to7_6, b7_6to8_6, b8_6to9_6, b9_6to10_6, b10_6to11_6, b11_6to12_6, b12_6to13_6, b13_6to14_6, b14_6to15_6, b15_6to16_6, b16_6to17_6, b17_6to18_6, b18_6to19_6, b19_6to20_6, b20_6to21_6, b21_6to22_6, b22_6to23_6, b23_6to24_6, b24_6to25_6, b25_6to26_6, b26_6to27_6, b27_6to28_6, b28_6to29_6, b29_6to30_6, b30_6to31_6, b31_6to32_6; +wire [`DWIDTH-1:0] b0_7to1_7, b1_7to2_7, b2_7to3_7, b3_7to4_7, b4_7to5_7, b5_7to6_7, b6_7to7_7, b7_7to8_7, b8_7to9_7, b9_7to10_7, b10_7to11_7, b11_7to12_7, b12_7to13_7, b13_7to14_7, b14_7to15_7, b15_7to16_7, b16_7to17_7, b17_7to18_7, b18_7to19_7, b19_7to20_7, b20_7to21_7, b21_7to22_7, b22_7to23_7, b23_7to24_7, b24_7to25_7, b25_7to26_7, b26_7to27_7, b27_7to28_7, b28_7to29_7, b29_7to30_7, b30_7to31_7, b31_7to32_7; +wire [`DWIDTH-1:0] b0_8to1_8, b1_8to2_8, b2_8to3_8, b3_8to4_8, b4_8to5_8, b5_8to6_8, b6_8to7_8, b7_8to8_8, b8_8to9_8, b9_8to10_8, b10_8to11_8, b11_8to12_8, b12_8to13_8, b13_8to14_8, b14_8to15_8, b15_8to16_8, b16_8to17_8, b17_8to18_8, b18_8to19_8, b19_8to20_8, b20_8to21_8, b21_8to22_8, b22_8to23_8, b23_8to24_8, b24_8to25_8, b25_8to26_8, b26_8to27_8, b27_8to28_8, b28_8to29_8, b29_8to30_8, b30_8to31_8, b31_8to32_8; +wire [`DWIDTH-1:0] b0_9to1_9, b1_9to2_9, b2_9to3_9, b3_9to4_9, b4_9to5_9, b5_9to6_9, b6_9to7_9, b7_9to8_9, b8_9to9_9, b9_9to10_9, b10_9to11_9, b11_9to12_9, b12_9to13_9, b13_9to14_9, b14_9to15_9, b15_9to16_9, b16_9to17_9, b17_9to18_9, b18_9to19_9, b19_9to20_9, b20_9to21_9, b21_9to22_9, b22_9to23_9, b23_9to24_9, b24_9to25_9, b25_9to26_9, b26_9to27_9, b27_9to28_9, b28_9to29_9, b29_9to30_9, b30_9to31_9, b31_9to32_9; +wire [`DWIDTH-1:0] b0_10to1_10, b1_10to2_10, b2_10to3_10, b3_10to4_10, b4_10to5_10, b5_10to6_10, b6_10to7_10, b7_10to8_10, b8_10to9_10, b9_10to10_10, b10_10to11_10, b11_10to12_10, b12_10to13_10, b13_10to14_10, b14_10to15_10, b15_10to16_10, b16_10to17_10, b17_10to18_10, b18_10to19_10, b19_10to20_10, b20_10to21_10, b21_10to22_10, b22_10to23_10, b23_10to24_10, b24_10to25_10, b25_10to26_10, b26_10to27_10, b27_10to28_10, b28_10to29_10, b29_10to30_10, b30_10to31_10, b31_10to32_10; +wire [`DWIDTH-1:0] b0_11to1_11, b1_11to2_11, b2_11to3_11, b3_11to4_11, b4_11to5_11, b5_11to6_11, b6_11to7_11, b7_11to8_11, b8_11to9_11, b9_11to10_11, b10_11to11_11, b11_11to12_11, b12_11to13_11, b13_11to14_11, b14_11to15_11, b15_11to16_11, b16_11to17_11, b17_11to18_11, b18_11to19_11, b19_11to20_11, b20_11to21_11, b21_11to22_11, b22_11to23_11, b23_11to24_11, b24_11to25_11, b25_11to26_11, b26_11to27_11, b27_11to28_11, b28_11to29_11, b29_11to30_11, b30_11to31_11, b31_11to32_11; +wire [`DWIDTH-1:0] b0_12to1_12, b1_12to2_12, b2_12to3_12, b3_12to4_12, b4_12to5_12, b5_12to6_12, b6_12to7_12, b7_12to8_12, b8_12to9_12, b9_12to10_12, b10_12to11_12, b11_12to12_12, b12_12to13_12, b13_12to14_12, b14_12to15_12, b15_12to16_12, b16_12to17_12, b17_12to18_12, b18_12to19_12, b19_12to20_12, b20_12to21_12, b21_12to22_12, b22_12to23_12, b23_12to24_12, b24_12to25_12, b25_12to26_12, b26_12to27_12, b27_12to28_12, b28_12to29_12, b29_12to30_12, b30_12to31_12, b31_12to32_12; +wire [`DWIDTH-1:0] b0_13to1_13, b1_13to2_13, b2_13to3_13, b3_13to4_13, b4_13to5_13, b5_13to6_13, b6_13to7_13, b7_13to8_13, b8_13to9_13, b9_13to10_13, b10_13to11_13, b11_13to12_13, b12_13to13_13, b13_13to14_13, b14_13to15_13, b15_13to16_13, b16_13to17_13, b17_13to18_13, b18_13to19_13, b19_13to20_13, b20_13to21_13, b21_13to22_13, b22_13to23_13, b23_13to24_13, b24_13to25_13, b25_13to26_13, b26_13to27_13, b27_13to28_13, b28_13to29_13, b29_13to30_13, b30_13to31_13, b31_13to32_13; +wire [`DWIDTH-1:0] b0_14to1_14, b1_14to2_14, b2_14to3_14, b3_14to4_14, b4_14to5_14, b5_14to6_14, b6_14to7_14, b7_14to8_14, b8_14to9_14, b9_14to10_14, b10_14to11_14, b11_14to12_14, b12_14to13_14, b13_14to14_14, b14_14to15_14, b15_14to16_14, b16_14to17_14, b17_14to18_14, b18_14to19_14, b19_14to20_14, b20_14to21_14, b21_14to22_14, b22_14to23_14, b23_14to24_14, b24_14to25_14, b25_14to26_14, b26_14to27_14, b27_14to28_14, b28_14to29_14, b29_14to30_14, b30_14to31_14, b31_14to32_14; +wire [`DWIDTH-1:0] b0_15to1_15, b1_15to2_15, b2_15to3_15, b3_15to4_15, b4_15to5_15, b5_15to6_15, b6_15to7_15, b7_15to8_15, b8_15to9_15, b9_15to10_15, b10_15to11_15, b11_15to12_15, b12_15to13_15, b13_15to14_15, b14_15to15_15, b15_15to16_15, b16_15to17_15, b17_15to18_15, b18_15to19_15, b19_15to20_15, b20_15to21_15, b21_15to22_15, b22_15to23_15, b23_15to24_15, b24_15to25_15, b25_15to26_15, b26_15to27_15, b27_15to28_15, b28_15to29_15, b29_15to30_15, b30_15to31_15, b31_15to32_15; +wire [`DWIDTH-1:0] b0_16to1_16, b1_16to2_16, b2_16to3_16, b3_16to4_16, b4_16to5_16, b5_16to6_16, b6_16to7_16, b7_16to8_16, b8_16to9_16, b9_16to10_16, b10_16to11_16, b11_16to12_16, b12_16to13_16, b13_16to14_16, b14_16to15_16, b15_16to16_16, b16_16to17_16, b17_16to18_16, b18_16to19_16, b19_16to20_16, b20_16to21_16, b21_16to22_16, b22_16to23_16, b23_16to24_16, b24_16to25_16, b25_16to26_16, b26_16to27_16, b27_16to28_16, b28_16to29_16, b29_16to30_16, b30_16to31_16, b31_16to32_16; +wire [`DWIDTH-1:0] b0_17to1_17, b1_17to2_17, b2_17to3_17, b3_17to4_17, b4_17to5_17, b5_17to6_17, b6_17to7_17, b7_17to8_17, b8_17to9_17, b9_17to10_17, b10_17to11_17, b11_17to12_17, b12_17to13_17, b13_17to14_17, b14_17to15_17, b15_17to16_17, b16_17to17_17, b17_17to18_17, b18_17to19_17, b19_17to20_17, b20_17to21_17, b21_17to22_17, b22_17to23_17, b23_17to24_17, b24_17to25_17, b25_17to26_17, b26_17to27_17, b27_17to28_17, b28_17to29_17, b29_17to30_17, b30_17to31_17, b31_17to32_17; +wire [`DWIDTH-1:0] b0_18to1_18, b1_18to2_18, b2_18to3_18, b3_18to4_18, b4_18to5_18, b5_18to6_18, b6_18to7_18, b7_18to8_18, b8_18to9_18, b9_18to10_18, b10_18to11_18, b11_18to12_18, b12_18to13_18, b13_18to14_18, b14_18to15_18, b15_18to16_18, b16_18to17_18, b17_18to18_18, b18_18to19_18, b19_18to20_18, b20_18to21_18, b21_18to22_18, b22_18to23_18, b23_18to24_18, b24_18to25_18, b25_18to26_18, b26_18to27_18, b27_18to28_18, b28_18to29_18, b29_18to30_18, b30_18to31_18, b31_18to32_18; +wire [`DWIDTH-1:0] b0_19to1_19, b1_19to2_19, b2_19to3_19, b3_19to4_19, b4_19to5_19, b5_19to6_19, b6_19to7_19, b7_19to8_19, b8_19to9_19, b9_19to10_19, b10_19to11_19, b11_19to12_19, b12_19to13_19, b13_19to14_19, b14_19to15_19, b15_19to16_19, b16_19to17_19, b17_19to18_19, b18_19to19_19, b19_19to20_19, b20_19to21_19, b21_19to22_19, b22_19to23_19, b23_19to24_19, b24_19to25_19, b25_19to26_19, b26_19to27_19, b27_19to28_19, b28_19to29_19, b29_19to30_19, b30_19to31_19, b31_19to32_19; +wire [`DWIDTH-1:0] b0_20to1_20, b1_20to2_20, b2_20to3_20, b3_20to4_20, b4_20to5_20, b5_20to6_20, b6_20to7_20, b7_20to8_20, b8_20to9_20, b9_20to10_20, b10_20to11_20, b11_20to12_20, b12_20to13_20, b13_20to14_20, b14_20to15_20, b15_20to16_20, b16_20to17_20, b17_20to18_20, b18_20to19_20, b19_20to20_20, b20_20to21_20, b21_20to22_20, b22_20to23_20, b23_20to24_20, b24_20to25_20, b25_20to26_20, b26_20to27_20, b27_20to28_20, b28_20to29_20, b29_20to30_20, b30_20to31_20, b31_20to32_20; +wire [`DWIDTH-1:0] b0_21to1_21, b1_21to2_21, b2_21to3_21, b3_21to4_21, b4_21to5_21, b5_21to6_21, b6_21to7_21, b7_21to8_21, b8_21to9_21, b9_21to10_21, b10_21to11_21, b11_21to12_21, b12_21to13_21, b13_21to14_21, b14_21to15_21, b15_21to16_21, b16_21to17_21, b17_21to18_21, b18_21to19_21, b19_21to20_21, b20_21to21_21, b21_21to22_21, b22_21to23_21, b23_21to24_21, b24_21to25_21, b25_21to26_21, b26_21to27_21, b27_21to28_21, b28_21to29_21, b29_21to30_21, b30_21to31_21, b31_21to32_21; +wire [`DWIDTH-1:0] b0_22to1_22, b1_22to2_22, b2_22to3_22, b3_22to4_22, b4_22to5_22, b5_22to6_22, b6_22to7_22, b7_22to8_22, b8_22to9_22, b9_22to10_22, b10_22to11_22, b11_22to12_22, b12_22to13_22, b13_22to14_22, b14_22to15_22, b15_22to16_22, b16_22to17_22, b17_22to18_22, b18_22to19_22, b19_22to20_22, b20_22to21_22, b21_22to22_22, b22_22to23_22, b23_22to24_22, b24_22to25_22, b25_22to26_22, b26_22to27_22, b27_22to28_22, b28_22to29_22, b29_22to30_22, b30_22to31_22, b31_22to32_22; +wire [`DWIDTH-1:0] b0_23to1_23, b1_23to2_23, b2_23to3_23, b3_23to4_23, b4_23to5_23, b5_23to6_23, b6_23to7_23, b7_23to8_23, b8_23to9_23, b9_23to10_23, b10_23to11_23, b11_23to12_23, b12_23to13_23, b13_23to14_23, b14_23to15_23, b15_23to16_23, b16_23to17_23, b17_23to18_23, b18_23to19_23, b19_23to20_23, b20_23to21_23, b21_23to22_23, b22_23to23_23, b23_23to24_23, b24_23to25_23, b25_23to26_23, b26_23to27_23, b27_23to28_23, b28_23to29_23, b29_23to30_23, b30_23to31_23, b31_23to32_23; +wire [`DWIDTH-1:0] b0_24to1_24, b1_24to2_24, b2_24to3_24, b3_24to4_24, b4_24to5_24, b5_24to6_24, b6_24to7_24, b7_24to8_24, b8_24to9_24, b9_24to10_24, b10_24to11_24, b11_24to12_24, b12_24to13_24, b13_24to14_24, b14_24to15_24, b15_24to16_24, b16_24to17_24, b17_24to18_24, b18_24to19_24, b19_24to20_24, b20_24to21_24, b21_24to22_24, b22_24to23_24, b23_24to24_24, b24_24to25_24, b25_24to26_24, b26_24to27_24, b27_24to28_24, b28_24to29_24, b29_24to30_24, b30_24to31_24, b31_24to32_24; +wire [`DWIDTH-1:0] b0_25to1_25, b1_25to2_25, b2_25to3_25, b3_25to4_25, b4_25to5_25, b5_25to6_25, b6_25to7_25, b7_25to8_25, b8_25to9_25, b9_25to10_25, b10_25to11_25, b11_25to12_25, b12_25to13_25, b13_25to14_25, b14_25to15_25, b15_25to16_25, b16_25to17_25, b17_25to18_25, b18_25to19_25, b19_25to20_25, b20_25to21_25, b21_25to22_25, b22_25to23_25, b23_25to24_25, b24_25to25_25, b25_25to26_25, b26_25to27_25, b27_25to28_25, b28_25to29_25, b29_25to30_25, b30_25to31_25, b31_25to32_25; +wire [`DWIDTH-1:0] b0_26to1_26, b1_26to2_26, b2_26to3_26, b3_26to4_26, b4_26to5_26, b5_26to6_26, b6_26to7_26, b7_26to8_26, b8_26to9_26, b9_26to10_26, b10_26to11_26, b11_26to12_26, b12_26to13_26, b13_26to14_26, b14_26to15_26, b15_26to16_26, b16_26to17_26, b17_26to18_26, b18_26to19_26, b19_26to20_26, b20_26to21_26, b21_26to22_26, b22_26to23_26, b23_26to24_26, b24_26to25_26, b25_26to26_26, b26_26to27_26, b27_26to28_26, b28_26to29_26, b29_26to30_26, b30_26to31_26, b31_26to32_26; +wire [`DWIDTH-1:0] b0_27to1_27, b1_27to2_27, b2_27to3_27, b3_27to4_27, b4_27to5_27, b5_27to6_27, b6_27to7_27, b7_27to8_27, b8_27to9_27, b9_27to10_27, b10_27to11_27, b11_27to12_27, b12_27to13_27, b13_27to14_27, b14_27to15_27, b15_27to16_27, b16_27to17_27, b17_27to18_27, b18_27to19_27, b19_27to20_27, b20_27to21_27, b21_27to22_27, b22_27to23_27, b23_27to24_27, b24_27to25_27, b25_27to26_27, b26_27to27_27, b27_27to28_27, b28_27to29_27, b29_27to30_27, b30_27to31_27, b31_27to32_27; +wire [`DWIDTH-1:0] b0_28to1_28, b1_28to2_28, b2_28to3_28, b3_28to4_28, b4_28to5_28, b5_28to6_28, b6_28to7_28, b7_28to8_28, b8_28to9_28, b9_28to10_28, b10_28to11_28, b11_28to12_28, b12_28to13_28, b13_28to14_28, b14_28to15_28, b15_28to16_28, b16_28to17_28, b17_28to18_28, b18_28to19_28, b19_28to20_28, b20_28to21_28, b21_28to22_28, b22_28to23_28, b23_28to24_28, b24_28to25_28, b25_28to26_28, b26_28to27_28, b27_28to28_28, b28_28to29_28, b29_28to30_28, b30_28to31_28, b31_28to32_28; +wire [`DWIDTH-1:0] b0_29to1_29, b1_29to2_29, b2_29to3_29, b3_29to4_29, b4_29to5_29, b5_29to6_29, b6_29to7_29, b7_29to8_29, b8_29to9_29, b9_29to10_29, b10_29to11_29, b11_29to12_29, b12_29to13_29, b13_29to14_29, b14_29to15_29, b15_29to16_29, b16_29to17_29, b17_29to18_29, b18_29to19_29, b19_29to20_29, b20_29to21_29, b21_29to22_29, b22_29to23_29, b23_29to24_29, b24_29to25_29, b25_29to26_29, b26_29to27_29, b27_29to28_29, b28_29to29_29, b29_29to30_29, b30_29to31_29, b31_29to32_29; +wire [`DWIDTH-1:0] b0_30to1_30, b1_30to2_30, b2_30to3_30, b3_30to4_30, b4_30to5_30, b5_30to6_30, b6_30to7_30, b7_30to8_30, b8_30to9_30, b9_30to10_30, b10_30to11_30, b11_30to12_30, b12_30to13_30, b13_30to14_30, b14_30to15_30, b15_30to16_30, b16_30to17_30, b17_30to18_30, b18_30to19_30, b19_30to20_30, b20_30to21_30, b21_30to22_30, b22_30to23_30, b23_30to24_30, b24_30to25_30, b25_30to26_30, b26_30to27_30, b27_30to28_30, b28_30to29_30, b29_30to30_30, b30_30to31_30, b31_30to32_30; +wire [`DWIDTH-1:0] b0_31to1_31, b1_31to2_31, b2_31to3_31, b3_31to4_31, b4_31to5_31, b5_31to6_31, b6_31to7_31, b7_31to8_31, b8_31to9_31, b9_31to10_31, b10_31to11_31, b11_31to12_31, b12_31to13_31, b13_31to14_31, b14_31to15_31, b15_31to16_31, b16_31to17_31, b17_31to18_31, b18_31to19_31, b19_31to20_31, b20_31to21_31, b21_31to22_31, b22_31to23_31, b23_31to24_31, b24_31to25_31, b25_31to26_31, b26_31to27_31, b27_31to28_31, b28_31to29_31, b29_31to30_31, b30_31to31_31, b31_31to32_31; + +////////////////////////////////////////////////////////////////////////// +// Instantiations of the actual PEs +////////////////////////////////////////////////////////////////////////// +//For larger matmul, more PEs will be needed +wire effective_rst; +assign effective_rst = reset | pe_reset; + +processing_element pe0_0(.reset(effective_rst), .clk(clk), .in_a(a0), .in_b(b0), .out_a(a0_0to0_1), .out_b(b0_0to1_0), .out_c(matrixC0_0)); +processing_element pe0_1(.reset(effective_rst), .clk(clk), .in_a(a0_0to0_1), .in_b(b1), .out_a(a0_1to0_2), .out_b(b0_1to1_1), .out_c(matrixC0_1)); +processing_element pe0_2(.reset(effective_rst), .clk(clk), .in_a(a0_1to0_2), .in_b(b2), .out_a(a0_2to0_3), .out_b(b0_2to1_2), .out_c(matrixC0_2)); +processing_element pe0_3(.reset(effective_rst), .clk(clk), .in_a(a0_2to0_3), .in_b(b3), .out_a(a0_3to0_4), .out_b(b0_3to1_3), .out_c(matrixC0_3)); +processing_element pe0_4(.reset(effective_rst), .clk(clk), .in_a(a0_3to0_4), .in_b(b4), .out_a(a0_4to0_5), .out_b(b0_4to1_4), .out_c(matrixC0_4)); +processing_element pe0_5(.reset(effective_rst), .clk(clk), .in_a(a0_4to0_5), .in_b(b5), .out_a(a0_5to0_6), .out_b(b0_5to1_5), .out_c(matrixC0_5)); +processing_element pe0_6(.reset(effective_rst), .clk(clk), .in_a(a0_5to0_6), .in_b(b6), .out_a(a0_6to0_7), .out_b(b0_6to1_6), .out_c(matrixC0_6)); +processing_element pe0_7(.reset(effective_rst), .clk(clk), .in_a(a0_6to0_7), .in_b(b7), .out_a(a0_7to0_8), .out_b(b0_7to1_7), .out_c(matrixC0_7)); +processing_element pe0_8(.reset(effective_rst), .clk(clk), .in_a(a0_7to0_8), .in_b(b8), .out_a(a0_8to0_9), .out_b(b0_8to1_8), .out_c(matrixC0_8)); +processing_element pe0_9(.reset(effective_rst), .clk(clk), .in_a(a0_8to0_9), .in_b(b9), .out_a(a0_9to0_10), .out_b(b0_9to1_9), .out_c(matrixC0_9)); +processing_element pe0_10(.reset(effective_rst), .clk(clk), .in_a(a0_9to0_10), .in_b(b10), .out_a(a0_10to0_11), .out_b(b0_10to1_10), .out_c(matrixC0_10)); +processing_element pe0_11(.reset(effective_rst), .clk(clk), .in_a(a0_10to0_11), .in_b(b11), .out_a(a0_11to0_12), .out_b(b0_11to1_11), .out_c(matrixC0_11)); +processing_element pe0_12(.reset(effective_rst), .clk(clk), .in_a(a0_11to0_12), .in_b(b12), .out_a(a0_12to0_13), .out_b(b0_12to1_12), .out_c(matrixC0_12)); +processing_element pe0_13(.reset(effective_rst), .clk(clk), .in_a(a0_12to0_13), .in_b(b13), .out_a(a0_13to0_14), .out_b(b0_13to1_13), .out_c(matrixC0_13)); +processing_element pe0_14(.reset(effective_rst), .clk(clk), .in_a(a0_13to0_14), .in_b(b14), .out_a(a0_14to0_15), .out_b(b0_14to1_14), .out_c(matrixC0_14)); +processing_element pe0_15(.reset(effective_rst), .clk(clk), .in_a(a0_14to0_15), .in_b(b15), .out_a(a0_15to0_16), .out_b(b0_15to1_15), .out_c(matrixC0_15)); +processing_element pe0_16(.reset(effective_rst), .clk(clk), .in_a(a0_15to0_16), .in_b(b16), .out_a(a0_16to0_17), .out_b(b0_16to1_16), .out_c(matrixC0_16)); +processing_element pe0_17(.reset(effective_rst), .clk(clk), .in_a(a0_16to0_17), .in_b(b17), .out_a(a0_17to0_18), .out_b(b0_17to1_17), .out_c(matrixC0_17)); +processing_element pe0_18(.reset(effective_rst), .clk(clk), .in_a(a0_17to0_18), .in_b(b18), .out_a(a0_18to0_19), .out_b(b0_18to1_18), .out_c(matrixC0_18)); +processing_element pe0_19(.reset(effective_rst), .clk(clk), .in_a(a0_18to0_19), .in_b(b19), .out_a(a0_19to0_20), .out_b(b0_19to1_19), .out_c(matrixC0_19)); +processing_element pe0_20(.reset(effective_rst), .clk(clk), .in_a(a0_19to0_20), .in_b(b20), .out_a(a0_20to0_21), .out_b(b0_20to1_20), .out_c(matrixC0_20)); +processing_element pe0_21(.reset(effective_rst), .clk(clk), .in_a(a0_20to0_21), .in_b(b21), .out_a(a0_21to0_22), .out_b(b0_21to1_21), .out_c(matrixC0_21)); +processing_element pe0_22(.reset(effective_rst), .clk(clk), .in_a(a0_21to0_22), .in_b(b22), .out_a(a0_22to0_23), .out_b(b0_22to1_22), .out_c(matrixC0_22)); +processing_element pe0_23(.reset(effective_rst), .clk(clk), .in_a(a0_22to0_23), .in_b(b23), .out_a(a0_23to0_24), .out_b(b0_23to1_23), .out_c(matrixC0_23)); +processing_element pe0_24(.reset(effective_rst), .clk(clk), .in_a(a0_23to0_24), .in_b(b24), .out_a(a0_24to0_25), .out_b(b0_24to1_24), .out_c(matrixC0_24)); +processing_element pe0_25(.reset(effective_rst), .clk(clk), .in_a(a0_24to0_25), .in_b(b25), .out_a(a0_25to0_26), .out_b(b0_25to1_25), .out_c(matrixC0_25)); +processing_element pe0_26(.reset(effective_rst), .clk(clk), .in_a(a0_25to0_26), .in_b(b26), .out_a(a0_26to0_27), .out_b(b0_26to1_26), .out_c(matrixC0_26)); +processing_element pe0_27(.reset(effective_rst), .clk(clk), .in_a(a0_26to0_27), .in_b(b27), .out_a(a0_27to0_28), .out_b(b0_27to1_27), .out_c(matrixC0_27)); +processing_element pe0_28(.reset(effective_rst), .clk(clk), .in_a(a0_27to0_28), .in_b(b28), .out_a(a0_28to0_29), .out_b(b0_28to1_28), .out_c(matrixC0_28)); +processing_element pe0_29(.reset(effective_rst), .clk(clk), .in_a(a0_28to0_29), .in_b(b29), .out_a(a0_29to0_30), .out_b(b0_29to1_29), .out_c(matrixC0_29)); +processing_element pe0_30(.reset(effective_rst), .clk(clk), .in_a(a0_29to0_30), .in_b(b30), .out_a(a0_30to0_31), .out_b(b0_30to1_30), .out_c(matrixC0_30)); +processing_element pe0_31(.reset(effective_rst), .clk(clk), .in_a(a0_30to0_31), .in_b(b31), .out_a(a0_31to0_32), .out_b(b0_31to1_31), .out_c(matrixC0_31)); + +processing_element pe1_0(.reset(effective_rst), .clk(clk), .in_a(a1), .in_b(b0_0to1_0), .out_a(a1_0to1_1), .out_b(b1_0to2_0), .out_c(matrixC1_0)); +processing_element pe2_0(.reset(effective_rst), .clk(clk), .in_a(a2), .in_b(b1_0to2_0), .out_a(a2_0to2_1), .out_b(b2_0to3_0), .out_c(matrixC2_0)); +processing_element pe3_0(.reset(effective_rst), .clk(clk), .in_a(a3), .in_b(b2_0to3_0), .out_a(a3_0to3_1), .out_b(b3_0to4_0), .out_c(matrixC3_0)); +processing_element pe4_0(.reset(effective_rst), .clk(clk), .in_a(a4), .in_b(b3_0to4_0), .out_a(a4_0to4_1), .out_b(b4_0to5_0), .out_c(matrixC4_0)); +processing_element pe5_0(.reset(effective_rst), .clk(clk), .in_a(a5), .in_b(b4_0to5_0), .out_a(a5_0to5_1), .out_b(b5_0to6_0), .out_c(matrixC5_0)); +processing_element pe6_0(.reset(effective_rst), .clk(clk), .in_a(a6), .in_b(b5_0to6_0), .out_a(a6_0to6_1), .out_b(b6_0to7_0), .out_c(matrixC6_0)); +processing_element pe7_0(.reset(effective_rst), .clk(clk), .in_a(a7), .in_b(b6_0to7_0), .out_a(a7_0to7_1), .out_b(b7_0to8_0), .out_c(matrixC7_0)); +processing_element pe8_0(.reset(effective_rst), .clk(clk), .in_a(a8), .in_b(b7_0to8_0), .out_a(a8_0to8_1), .out_b(b8_0to9_0), .out_c(matrixC8_0)); +processing_element pe9_0(.reset(effective_rst), .clk(clk), .in_a(a9), .in_b(b8_0to9_0), .out_a(a9_0to9_1), .out_b(b9_0to10_0), .out_c(matrixC9_0)); +processing_element pe10_0(.reset(effective_rst), .clk(clk), .in_a(a10), .in_b(b9_0to10_0), .out_a(a10_0to10_1), .out_b(b10_0to11_0), .out_c(matrixC10_0)); +processing_element pe11_0(.reset(effective_rst), .clk(clk), .in_a(a11), .in_b(b10_0to11_0), .out_a(a11_0to11_1), .out_b(b11_0to12_0), .out_c(matrixC11_0)); +processing_element pe12_0(.reset(effective_rst), .clk(clk), .in_a(a12), .in_b(b11_0to12_0), .out_a(a12_0to12_1), .out_b(b12_0to13_0), .out_c(matrixC12_0)); +processing_element pe13_0(.reset(effective_rst), .clk(clk), .in_a(a13), .in_b(b12_0to13_0), .out_a(a13_0to13_1), .out_b(b13_0to14_0), .out_c(matrixC13_0)); +processing_element pe14_0(.reset(effective_rst), .clk(clk), .in_a(a14), .in_b(b13_0to14_0), .out_a(a14_0to14_1), .out_b(b14_0to15_0), .out_c(matrixC14_0)); +processing_element pe15_0(.reset(effective_rst), .clk(clk), .in_a(a15), .in_b(b14_0to15_0), .out_a(a15_0to15_1), .out_b(b15_0to16_0), .out_c(matrixC15_0)); +processing_element pe16_0(.reset(effective_rst), .clk(clk), .in_a(a16), .in_b(b15_0to16_0), .out_a(a16_0to16_1), .out_b(b16_0to17_0), .out_c(matrixC16_0)); +processing_element pe17_0(.reset(effective_rst), .clk(clk), .in_a(a17), .in_b(b16_0to17_0), .out_a(a17_0to17_1), .out_b(b17_0to18_0), .out_c(matrixC17_0)); +processing_element pe18_0(.reset(effective_rst), .clk(clk), .in_a(a18), .in_b(b17_0to18_0), .out_a(a18_0to18_1), .out_b(b18_0to19_0), .out_c(matrixC18_0)); +processing_element pe19_0(.reset(effective_rst), .clk(clk), .in_a(a19), .in_b(b18_0to19_0), .out_a(a19_0to19_1), .out_b(b19_0to20_0), .out_c(matrixC19_0)); +processing_element pe20_0(.reset(effective_rst), .clk(clk), .in_a(a20), .in_b(b19_0to20_0), .out_a(a20_0to20_1), .out_b(b20_0to21_0), .out_c(matrixC20_0)); +processing_element pe21_0(.reset(effective_rst), .clk(clk), .in_a(a21), .in_b(b20_0to21_0), .out_a(a21_0to21_1), .out_b(b21_0to22_0), .out_c(matrixC21_0)); +processing_element pe22_0(.reset(effective_rst), .clk(clk), .in_a(a22), .in_b(b21_0to22_0), .out_a(a22_0to22_1), .out_b(b22_0to23_0), .out_c(matrixC22_0)); +processing_element pe23_0(.reset(effective_rst), .clk(clk), .in_a(a23), .in_b(b22_0to23_0), .out_a(a23_0to23_1), .out_b(b23_0to24_0), .out_c(matrixC23_0)); +processing_element pe24_0(.reset(effective_rst), .clk(clk), .in_a(a24), .in_b(b23_0to24_0), .out_a(a24_0to24_1), .out_b(b24_0to25_0), .out_c(matrixC24_0)); +processing_element pe25_0(.reset(effective_rst), .clk(clk), .in_a(a25), .in_b(b24_0to25_0), .out_a(a25_0to25_1), .out_b(b25_0to26_0), .out_c(matrixC25_0)); +processing_element pe26_0(.reset(effective_rst), .clk(clk), .in_a(a26), .in_b(b25_0to26_0), .out_a(a26_0to26_1), .out_b(b26_0to27_0), .out_c(matrixC26_0)); +processing_element pe27_0(.reset(effective_rst), .clk(clk), .in_a(a27), .in_b(b26_0to27_0), .out_a(a27_0to27_1), .out_b(b27_0to28_0), .out_c(matrixC27_0)); +processing_element pe28_0(.reset(effective_rst), .clk(clk), .in_a(a28), .in_b(b27_0to28_0), .out_a(a28_0to28_1), .out_b(b28_0to29_0), .out_c(matrixC28_0)); +processing_element pe29_0(.reset(effective_rst), .clk(clk), .in_a(a29), .in_b(b28_0to29_0), .out_a(a29_0to29_1), .out_b(b29_0to30_0), .out_c(matrixC29_0)); +processing_element pe30_0(.reset(effective_rst), .clk(clk), .in_a(a30), .in_b(b29_0to30_0), .out_a(a30_0to30_1), .out_b(b30_0to31_0), .out_c(matrixC30_0)); +processing_element pe31_0(.reset(effective_rst), .clk(clk), .in_a(a31), .in_b(b30_0to31_0), .out_a(a31_0to31_1), .out_b(b31_0to32_0), .out_c(matrixC31_0)); + +processing_element pe1_1(.reset(effective_rst), .clk(clk), .in_a(a1_0to1_1), .in_b(b0_1to1_1), .out_a(a1_1to1_2), .out_b(b1_1to2_1), .out_c(matrixC1_1)); +processing_element pe1_2(.reset(effective_rst), .clk(clk), .in_a(a1_1to1_2), .in_b(b0_2to1_2), .out_a(a1_2to1_3), .out_b(b1_2to2_2), .out_c(matrixC1_2)); +processing_element pe1_3(.reset(effective_rst), .clk(clk), .in_a(a1_2to1_3), .in_b(b0_3to1_3), .out_a(a1_3to1_4), .out_b(b1_3to2_3), .out_c(matrixC1_3)); +processing_element pe1_4(.reset(effective_rst), .clk(clk), .in_a(a1_3to1_4), .in_b(b0_4to1_4), .out_a(a1_4to1_5), .out_b(b1_4to2_4), .out_c(matrixC1_4)); +processing_element pe1_5(.reset(effective_rst), .clk(clk), .in_a(a1_4to1_5), .in_b(b0_5to1_5), .out_a(a1_5to1_6), .out_b(b1_5to2_5), .out_c(matrixC1_5)); +processing_element pe1_6(.reset(effective_rst), .clk(clk), .in_a(a1_5to1_6), .in_b(b0_6to1_6), .out_a(a1_6to1_7), .out_b(b1_6to2_6), .out_c(matrixC1_6)); +processing_element pe1_7(.reset(effective_rst), .clk(clk), .in_a(a1_6to1_7), .in_b(b0_7to1_7), .out_a(a1_7to1_8), .out_b(b1_7to2_7), .out_c(matrixC1_7)); +processing_element pe1_8(.reset(effective_rst), .clk(clk), .in_a(a1_7to1_8), .in_b(b0_8to1_8), .out_a(a1_8to1_9), .out_b(b1_8to2_8), .out_c(matrixC1_8)); +processing_element pe1_9(.reset(effective_rst), .clk(clk), .in_a(a1_8to1_9), .in_b(b0_9to1_9), .out_a(a1_9to1_10), .out_b(b1_9to2_9), .out_c(matrixC1_9)); +processing_element pe1_10(.reset(effective_rst), .clk(clk), .in_a(a1_9to1_10), .in_b(b0_10to1_10), .out_a(a1_10to1_11), .out_b(b1_10to2_10), .out_c(matrixC1_10)); +processing_element pe1_11(.reset(effective_rst), .clk(clk), .in_a(a1_10to1_11), .in_b(b0_11to1_11), .out_a(a1_11to1_12), .out_b(b1_11to2_11), .out_c(matrixC1_11)); +processing_element pe1_12(.reset(effective_rst), .clk(clk), .in_a(a1_11to1_12), .in_b(b0_12to1_12), .out_a(a1_12to1_13), .out_b(b1_12to2_12), .out_c(matrixC1_12)); +processing_element pe1_13(.reset(effective_rst), .clk(clk), .in_a(a1_12to1_13), .in_b(b0_13to1_13), .out_a(a1_13to1_14), .out_b(b1_13to2_13), .out_c(matrixC1_13)); +processing_element pe1_14(.reset(effective_rst), .clk(clk), .in_a(a1_13to1_14), .in_b(b0_14to1_14), .out_a(a1_14to1_15), .out_b(b1_14to2_14), .out_c(matrixC1_14)); +processing_element pe1_15(.reset(effective_rst), .clk(clk), .in_a(a1_14to1_15), .in_b(b0_15to1_15), .out_a(a1_15to1_16), .out_b(b1_15to2_15), .out_c(matrixC1_15)); +processing_element pe1_16(.reset(effective_rst), .clk(clk), .in_a(a1_15to1_16), .in_b(b0_16to1_16), .out_a(a1_16to1_17), .out_b(b1_16to2_16), .out_c(matrixC1_16)); +processing_element pe1_17(.reset(effective_rst), .clk(clk), .in_a(a1_16to1_17), .in_b(b0_17to1_17), .out_a(a1_17to1_18), .out_b(b1_17to2_17), .out_c(matrixC1_17)); +processing_element pe1_18(.reset(effective_rst), .clk(clk), .in_a(a1_17to1_18), .in_b(b0_18to1_18), .out_a(a1_18to1_19), .out_b(b1_18to2_18), .out_c(matrixC1_18)); +processing_element pe1_19(.reset(effective_rst), .clk(clk), .in_a(a1_18to1_19), .in_b(b0_19to1_19), .out_a(a1_19to1_20), .out_b(b1_19to2_19), .out_c(matrixC1_19)); +processing_element pe1_20(.reset(effective_rst), .clk(clk), .in_a(a1_19to1_20), .in_b(b0_20to1_20), .out_a(a1_20to1_21), .out_b(b1_20to2_20), .out_c(matrixC1_20)); +processing_element pe1_21(.reset(effective_rst), .clk(clk), .in_a(a1_20to1_21), .in_b(b0_21to1_21), .out_a(a1_21to1_22), .out_b(b1_21to2_21), .out_c(matrixC1_21)); +processing_element pe1_22(.reset(effective_rst), .clk(clk), .in_a(a1_21to1_22), .in_b(b0_22to1_22), .out_a(a1_22to1_23), .out_b(b1_22to2_22), .out_c(matrixC1_22)); +processing_element pe1_23(.reset(effective_rst), .clk(clk), .in_a(a1_22to1_23), .in_b(b0_23to1_23), .out_a(a1_23to1_24), .out_b(b1_23to2_23), .out_c(matrixC1_23)); +processing_element pe1_24(.reset(effective_rst), .clk(clk), .in_a(a1_23to1_24), .in_b(b0_24to1_24), .out_a(a1_24to1_25), .out_b(b1_24to2_24), .out_c(matrixC1_24)); +processing_element pe1_25(.reset(effective_rst), .clk(clk), .in_a(a1_24to1_25), .in_b(b0_25to1_25), .out_a(a1_25to1_26), .out_b(b1_25to2_25), .out_c(matrixC1_25)); +processing_element pe1_26(.reset(effective_rst), .clk(clk), .in_a(a1_25to1_26), .in_b(b0_26to1_26), .out_a(a1_26to1_27), .out_b(b1_26to2_26), .out_c(matrixC1_26)); +processing_element pe1_27(.reset(effective_rst), .clk(clk), .in_a(a1_26to1_27), .in_b(b0_27to1_27), .out_a(a1_27to1_28), .out_b(b1_27to2_27), .out_c(matrixC1_27)); +processing_element pe1_28(.reset(effective_rst), .clk(clk), .in_a(a1_27to1_28), .in_b(b0_28to1_28), .out_a(a1_28to1_29), .out_b(b1_28to2_28), .out_c(matrixC1_28)); +processing_element pe1_29(.reset(effective_rst), .clk(clk), .in_a(a1_28to1_29), .in_b(b0_29to1_29), .out_a(a1_29to1_30), .out_b(b1_29to2_29), .out_c(matrixC1_29)); +processing_element pe1_30(.reset(effective_rst), .clk(clk), .in_a(a1_29to1_30), .in_b(b0_30to1_30), .out_a(a1_30to1_31), .out_b(b1_30to2_30), .out_c(matrixC1_30)); +processing_element pe1_31(.reset(effective_rst), .clk(clk), .in_a(a1_30to1_31), .in_b(b0_31to1_31), .out_a(a1_31to1_32), .out_b(b1_31to2_31), .out_c(matrixC1_31)); +processing_element pe2_1(.reset(effective_rst), .clk(clk), .in_a(a2_0to2_1), .in_b(b1_1to2_1), .out_a(a2_1to2_2), .out_b(b2_1to3_1), .out_c(matrixC2_1)); +processing_element pe2_2(.reset(effective_rst), .clk(clk), .in_a(a2_1to2_2), .in_b(b1_2to2_2), .out_a(a2_2to2_3), .out_b(b2_2to3_2), .out_c(matrixC2_2)); +processing_element pe2_3(.reset(effective_rst), .clk(clk), .in_a(a2_2to2_3), .in_b(b1_3to2_3), .out_a(a2_3to2_4), .out_b(b2_3to3_3), .out_c(matrixC2_3)); +processing_element pe2_4(.reset(effective_rst), .clk(clk), .in_a(a2_3to2_4), .in_b(b1_4to2_4), .out_a(a2_4to2_5), .out_b(b2_4to3_4), .out_c(matrixC2_4)); +processing_element pe2_5(.reset(effective_rst), .clk(clk), .in_a(a2_4to2_5), .in_b(b1_5to2_5), .out_a(a2_5to2_6), .out_b(b2_5to3_5), .out_c(matrixC2_5)); +processing_element pe2_6(.reset(effective_rst), .clk(clk), .in_a(a2_5to2_6), .in_b(b1_6to2_6), .out_a(a2_6to2_7), .out_b(b2_6to3_6), .out_c(matrixC2_6)); +processing_element pe2_7(.reset(effective_rst), .clk(clk), .in_a(a2_6to2_7), .in_b(b1_7to2_7), .out_a(a2_7to2_8), .out_b(b2_7to3_7), .out_c(matrixC2_7)); +processing_element pe2_8(.reset(effective_rst), .clk(clk), .in_a(a2_7to2_8), .in_b(b1_8to2_8), .out_a(a2_8to2_9), .out_b(b2_8to3_8), .out_c(matrixC2_8)); +processing_element pe2_9(.reset(effective_rst), .clk(clk), .in_a(a2_8to2_9), .in_b(b1_9to2_9), .out_a(a2_9to2_10), .out_b(b2_9to3_9), .out_c(matrixC2_9)); +processing_element pe2_10(.reset(effective_rst), .clk(clk), .in_a(a2_9to2_10), .in_b(b1_10to2_10), .out_a(a2_10to2_11), .out_b(b2_10to3_10), .out_c(matrixC2_10)); +processing_element pe2_11(.reset(effective_rst), .clk(clk), .in_a(a2_10to2_11), .in_b(b1_11to2_11), .out_a(a2_11to2_12), .out_b(b2_11to3_11), .out_c(matrixC2_11)); +processing_element pe2_12(.reset(effective_rst), .clk(clk), .in_a(a2_11to2_12), .in_b(b1_12to2_12), .out_a(a2_12to2_13), .out_b(b2_12to3_12), .out_c(matrixC2_12)); +processing_element pe2_13(.reset(effective_rst), .clk(clk), .in_a(a2_12to2_13), .in_b(b1_13to2_13), .out_a(a2_13to2_14), .out_b(b2_13to3_13), .out_c(matrixC2_13)); +processing_element pe2_14(.reset(effective_rst), .clk(clk), .in_a(a2_13to2_14), .in_b(b1_14to2_14), .out_a(a2_14to2_15), .out_b(b2_14to3_14), .out_c(matrixC2_14)); +processing_element pe2_15(.reset(effective_rst), .clk(clk), .in_a(a2_14to2_15), .in_b(b1_15to2_15), .out_a(a2_15to2_16), .out_b(b2_15to3_15), .out_c(matrixC2_15)); +processing_element pe2_16(.reset(effective_rst), .clk(clk), .in_a(a2_15to2_16), .in_b(b1_16to2_16), .out_a(a2_16to2_17), .out_b(b2_16to3_16), .out_c(matrixC2_16)); +processing_element pe2_17(.reset(effective_rst), .clk(clk), .in_a(a2_16to2_17), .in_b(b1_17to2_17), .out_a(a2_17to2_18), .out_b(b2_17to3_17), .out_c(matrixC2_17)); +processing_element pe2_18(.reset(effective_rst), .clk(clk), .in_a(a2_17to2_18), .in_b(b1_18to2_18), .out_a(a2_18to2_19), .out_b(b2_18to3_18), .out_c(matrixC2_18)); +processing_element pe2_19(.reset(effective_rst), .clk(clk), .in_a(a2_18to2_19), .in_b(b1_19to2_19), .out_a(a2_19to2_20), .out_b(b2_19to3_19), .out_c(matrixC2_19)); +processing_element pe2_20(.reset(effective_rst), .clk(clk), .in_a(a2_19to2_20), .in_b(b1_20to2_20), .out_a(a2_20to2_21), .out_b(b2_20to3_20), .out_c(matrixC2_20)); +processing_element pe2_21(.reset(effective_rst), .clk(clk), .in_a(a2_20to2_21), .in_b(b1_21to2_21), .out_a(a2_21to2_22), .out_b(b2_21to3_21), .out_c(matrixC2_21)); +processing_element pe2_22(.reset(effective_rst), .clk(clk), .in_a(a2_21to2_22), .in_b(b1_22to2_22), .out_a(a2_22to2_23), .out_b(b2_22to3_22), .out_c(matrixC2_22)); +processing_element pe2_23(.reset(effective_rst), .clk(clk), .in_a(a2_22to2_23), .in_b(b1_23to2_23), .out_a(a2_23to2_24), .out_b(b2_23to3_23), .out_c(matrixC2_23)); +processing_element pe2_24(.reset(effective_rst), .clk(clk), .in_a(a2_23to2_24), .in_b(b1_24to2_24), .out_a(a2_24to2_25), .out_b(b2_24to3_24), .out_c(matrixC2_24)); +processing_element pe2_25(.reset(effective_rst), .clk(clk), .in_a(a2_24to2_25), .in_b(b1_25to2_25), .out_a(a2_25to2_26), .out_b(b2_25to3_25), .out_c(matrixC2_25)); +processing_element pe2_26(.reset(effective_rst), .clk(clk), .in_a(a2_25to2_26), .in_b(b1_26to2_26), .out_a(a2_26to2_27), .out_b(b2_26to3_26), .out_c(matrixC2_26)); +processing_element pe2_27(.reset(effective_rst), .clk(clk), .in_a(a2_26to2_27), .in_b(b1_27to2_27), .out_a(a2_27to2_28), .out_b(b2_27to3_27), .out_c(matrixC2_27)); +processing_element pe2_28(.reset(effective_rst), .clk(clk), .in_a(a2_27to2_28), .in_b(b1_28to2_28), .out_a(a2_28to2_29), .out_b(b2_28to3_28), .out_c(matrixC2_28)); +processing_element pe2_29(.reset(effective_rst), .clk(clk), .in_a(a2_28to2_29), .in_b(b1_29to2_29), .out_a(a2_29to2_30), .out_b(b2_29to3_29), .out_c(matrixC2_29)); +processing_element pe2_30(.reset(effective_rst), .clk(clk), .in_a(a2_29to2_30), .in_b(b1_30to2_30), .out_a(a2_30to2_31), .out_b(b2_30to3_30), .out_c(matrixC2_30)); +processing_element pe2_31(.reset(effective_rst), .clk(clk), .in_a(a2_30to2_31), .in_b(b1_31to2_31), .out_a(a2_31to2_32), .out_b(b2_31to3_31), .out_c(matrixC2_31)); +processing_element pe3_1(.reset(effective_rst), .clk(clk), .in_a(a3_0to3_1), .in_b(b2_1to3_1), .out_a(a3_1to3_2), .out_b(b3_1to4_1), .out_c(matrixC3_1)); +processing_element pe3_2(.reset(effective_rst), .clk(clk), .in_a(a3_1to3_2), .in_b(b2_2to3_2), .out_a(a3_2to3_3), .out_b(b3_2to4_2), .out_c(matrixC3_2)); +processing_element pe3_3(.reset(effective_rst), .clk(clk), .in_a(a3_2to3_3), .in_b(b2_3to3_3), .out_a(a3_3to3_4), .out_b(b3_3to4_3), .out_c(matrixC3_3)); +processing_element pe3_4(.reset(effective_rst), .clk(clk), .in_a(a3_3to3_4), .in_b(b2_4to3_4), .out_a(a3_4to3_5), .out_b(b3_4to4_4), .out_c(matrixC3_4)); +processing_element pe3_5(.reset(effective_rst), .clk(clk), .in_a(a3_4to3_5), .in_b(b2_5to3_5), .out_a(a3_5to3_6), .out_b(b3_5to4_5), .out_c(matrixC3_5)); +processing_element pe3_6(.reset(effective_rst), .clk(clk), .in_a(a3_5to3_6), .in_b(b2_6to3_6), .out_a(a3_6to3_7), .out_b(b3_6to4_6), .out_c(matrixC3_6)); +processing_element pe3_7(.reset(effective_rst), .clk(clk), .in_a(a3_6to3_7), .in_b(b2_7to3_7), .out_a(a3_7to3_8), .out_b(b3_7to4_7), .out_c(matrixC3_7)); +processing_element pe3_8(.reset(effective_rst), .clk(clk), .in_a(a3_7to3_8), .in_b(b2_8to3_8), .out_a(a3_8to3_9), .out_b(b3_8to4_8), .out_c(matrixC3_8)); +processing_element pe3_9(.reset(effective_rst), .clk(clk), .in_a(a3_8to3_9), .in_b(b2_9to3_9), .out_a(a3_9to3_10), .out_b(b3_9to4_9), .out_c(matrixC3_9)); +processing_element pe3_10(.reset(effective_rst), .clk(clk), .in_a(a3_9to3_10), .in_b(b2_10to3_10), .out_a(a3_10to3_11), .out_b(b3_10to4_10), .out_c(matrixC3_10)); +processing_element pe3_11(.reset(effective_rst), .clk(clk), .in_a(a3_10to3_11), .in_b(b2_11to3_11), .out_a(a3_11to3_12), .out_b(b3_11to4_11), .out_c(matrixC3_11)); +processing_element pe3_12(.reset(effective_rst), .clk(clk), .in_a(a3_11to3_12), .in_b(b2_12to3_12), .out_a(a3_12to3_13), .out_b(b3_12to4_12), .out_c(matrixC3_12)); +processing_element pe3_13(.reset(effective_rst), .clk(clk), .in_a(a3_12to3_13), .in_b(b2_13to3_13), .out_a(a3_13to3_14), .out_b(b3_13to4_13), .out_c(matrixC3_13)); +processing_element pe3_14(.reset(effective_rst), .clk(clk), .in_a(a3_13to3_14), .in_b(b2_14to3_14), .out_a(a3_14to3_15), .out_b(b3_14to4_14), .out_c(matrixC3_14)); +processing_element pe3_15(.reset(effective_rst), .clk(clk), .in_a(a3_14to3_15), .in_b(b2_15to3_15), .out_a(a3_15to3_16), .out_b(b3_15to4_15), .out_c(matrixC3_15)); +processing_element pe3_16(.reset(effective_rst), .clk(clk), .in_a(a3_15to3_16), .in_b(b2_16to3_16), .out_a(a3_16to3_17), .out_b(b3_16to4_16), .out_c(matrixC3_16)); +processing_element pe3_17(.reset(effective_rst), .clk(clk), .in_a(a3_16to3_17), .in_b(b2_17to3_17), .out_a(a3_17to3_18), .out_b(b3_17to4_17), .out_c(matrixC3_17)); +processing_element pe3_18(.reset(effective_rst), .clk(clk), .in_a(a3_17to3_18), .in_b(b2_18to3_18), .out_a(a3_18to3_19), .out_b(b3_18to4_18), .out_c(matrixC3_18)); +processing_element pe3_19(.reset(effective_rst), .clk(clk), .in_a(a3_18to3_19), .in_b(b2_19to3_19), .out_a(a3_19to3_20), .out_b(b3_19to4_19), .out_c(matrixC3_19)); +processing_element pe3_20(.reset(effective_rst), .clk(clk), .in_a(a3_19to3_20), .in_b(b2_20to3_20), .out_a(a3_20to3_21), .out_b(b3_20to4_20), .out_c(matrixC3_20)); +processing_element pe3_21(.reset(effective_rst), .clk(clk), .in_a(a3_20to3_21), .in_b(b2_21to3_21), .out_a(a3_21to3_22), .out_b(b3_21to4_21), .out_c(matrixC3_21)); +processing_element pe3_22(.reset(effective_rst), .clk(clk), .in_a(a3_21to3_22), .in_b(b2_22to3_22), .out_a(a3_22to3_23), .out_b(b3_22to4_22), .out_c(matrixC3_22)); +processing_element pe3_23(.reset(effective_rst), .clk(clk), .in_a(a3_22to3_23), .in_b(b2_23to3_23), .out_a(a3_23to3_24), .out_b(b3_23to4_23), .out_c(matrixC3_23)); +processing_element pe3_24(.reset(effective_rst), .clk(clk), .in_a(a3_23to3_24), .in_b(b2_24to3_24), .out_a(a3_24to3_25), .out_b(b3_24to4_24), .out_c(matrixC3_24)); +processing_element pe3_25(.reset(effective_rst), .clk(clk), .in_a(a3_24to3_25), .in_b(b2_25to3_25), .out_a(a3_25to3_26), .out_b(b3_25to4_25), .out_c(matrixC3_25)); +processing_element pe3_26(.reset(effective_rst), .clk(clk), .in_a(a3_25to3_26), .in_b(b2_26to3_26), .out_a(a3_26to3_27), .out_b(b3_26to4_26), .out_c(matrixC3_26)); +processing_element pe3_27(.reset(effective_rst), .clk(clk), .in_a(a3_26to3_27), .in_b(b2_27to3_27), .out_a(a3_27to3_28), .out_b(b3_27to4_27), .out_c(matrixC3_27)); +processing_element pe3_28(.reset(effective_rst), .clk(clk), .in_a(a3_27to3_28), .in_b(b2_28to3_28), .out_a(a3_28to3_29), .out_b(b3_28to4_28), .out_c(matrixC3_28)); +processing_element pe3_29(.reset(effective_rst), .clk(clk), .in_a(a3_28to3_29), .in_b(b2_29to3_29), .out_a(a3_29to3_30), .out_b(b3_29to4_29), .out_c(matrixC3_29)); +processing_element pe3_30(.reset(effective_rst), .clk(clk), .in_a(a3_29to3_30), .in_b(b2_30to3_30), .out_a(a3_30to3_31), .out_b(b3_30to4_30), .out_c(matrixC3_30)); +processing_element pe3_31(.reset(effective_rst), .clk(clk), .in_a(a3_30to3_31), .in_b(b2_31to3_31), .out_a(a3_31to3_32), .out_b(b3_31to4_31), .out_c(matrixC3_31)); +processing_element pe4_1(.reset(effective_rst), .clk(clk), .in_a(a4_0to4_1), .in_b(b3_1to4_1), .out_a(a4_1to4_2), .out_b(b4_1to5_1), .out_c(matrixC4_1)); +processing_element pe4_2(.reset(effective_rst), .clk(clk), .in_a(a4_1to4_2), .in_b(b3_2to4_2), .out_a(a4_2to4_3), .out_b(b4_2to5_2), .out_c(matrixC4_2)); +processing_element pe4_3(.reset(effective_rst), .clk(clk), .in_a(a4_2to4_3), .in_b(b3_3to4_3), .out_a(a4_3to4_4), .out_b(b4_3to5_3), .out_c(matrixC4_3)); +processing_element pe4_4(.reset(effective_rst), .clk(clk), .in_a(a4_3to4_4), .in_b(b3_4to4_4), .out_a(a4_4to4_5), .out_b(b4_4to5_4), .out_c(matrixC4_4)); +processing_element pe4_5(.reset(effective_rst), .clk(clk), .in_a(a4_4to4_5), .in_b(b3_5to4_5), .out_a(a4_5to4_6), .out_b(b4_5to5_5), .out_c(matrixC4_5)); +processing_element pe4_6(.reset(effective_rst), .clk(clk), .in_a(a4_5to4_6), .in_b(b3_6to4_6), .out_a(a4_6to4_7), .out_b(b4_6to5_6), .out_c(matrixC4_6)); +processing_element pe4_7(.reset(effective_rst), .clk(clk), .in_a(a4_6to4_7), .in_b(b3_7to4_7), .out_a(a4_7to4_8), .out_b(b4_7to5_7), .out_c(matrixC4_7)); +processing_element pe4_8(.reset(effective_rst), .clk(clk), .in_a(a4_7to4_8), .in_b(b3_8to4_8), .out_a(a4_8to4_9), .out_b(b4_8to5_8), .out_c(matrixC4_8)); +processing_element pe4_9(.reset(effective_rst), .clk(clk), .in_a(a4_8to4_9), .in_b(b3_9to4_9), .out_a(a4_9to4_10), .out_b(b4_9to5_9), .out_c(matrixC4_9)); +processing_element pe4_10(.reset(effective_rst), .clk(clk), .in_a(a4_9to4_10), .in_b(b3_10to4_10), .out_a(a4_10to4_11), .out_b(b4_10to5_10), .out_c(matrixC4_10)); +processing_element pe4_11(.reset(effective_rst), .clk(clk), .in_a(a4_10to4_11), .in_b(b3_11to4_11), .out_a(a4_11to4_12), .out_b(b4_11to5_11), .out_c(matrixC4_11)); +processing_element pe4_12(.reset(effective_rst), .clk(clk), .in_a(a4_11to4_12), .in_b(b3_12to4_12), .out_a(a4_12to4_13), .out_b(b4_12to5_12), .out_c(matrixC4_12)); +processing_element pe4_13(.reset(effective_rst), .clk(clk), .in_a(a4_12to4_13), .in_b(b3_13to4_13), .out_a(a4_13to4_14), .out_b(b4_13to5_13), .out_c(matrixC4_13)); +processing_element pe4_14(.reset(effective_rst), .clk(clk), .in_a(a4_13to4_14), .in_b(b3_14to4_14), .out_a(a4_14to4_15), .out_b(b4_14to5_14), .out_c(matrixC4_14)); +processing_element pe4_15(.reset(effective_rst), .clk(clk), .in_a(a4_14to4_15), .in_b(b3_15to4_15), .out_a(a4_15to4_16), .out_b(b4_15to5_15), .out_c(matrixC4_15)); +processing_element pe4_16(.reset(effective_rst), .clk(clk), .in_a(a4_15to4_16), .in_b(b3_16to4_16), .out_a(a4_16to4_17), .out_b(b4_16to5_16), .out_c(matrixC4_16)); +processing_element pe4_17(.reset(effective_rst), .clk(clk), .in_a(a4_16to4_17), .in_b(b3_17to4_17), .out_a(a4_17to4_18), .out_b(b4_17to5_17), .out_c(matrixC4_17)); +processing_element pe4_18(.reset(effective_rst), .clk(clk), .in_a(a4_17to4_18), .in_b(b3_18to4_18), .out_a(a4_18to4_19), .out_b(b4_18to5_18), .out_c(matrixC4_18)); +processing_element pe4_19(.reset(effective_rst), .clk(clk), .in_a(a4_18to4_19), .in_b(b3_19to4_19), .out_a(a4_19to4_20), .out_b(b4_19to5_19), .out_c(matrixC4_19)); +processing_element pe4_20(.reset(effective_rst), .clk(clk), .in_a(a4_19to4_20), .in_b(b3_20to4_20), .out_a(a4_20to4_21), .out_b(b4_20to5_20), .out_c(matrixC4_20)); +processing_element pe4_21(.reset(effective_rst), .clk(clk), .in_a(a4_20to4_21), .in_b(b3_21to4_21), .out_a(a4_21to4_22), .out_b(b4_21to5_21), .out_c(matrixC4_21)); +processing_element pe4_22(.reset(effective_rst), .clk(clk), .in_a(a4_21to4_22), .in_b(b3_22to4_22), .out_a(a4_22to4_23), .out_b(b4_22to5_22), .out_c(matrixC4_22)); +processing_element pe4_23(.reset(effective_rst), .clk(clk), .in_a(a4_22to4_23), .in_b(b3_23to4_23), .out_a(a4_23to4_24), .out_b(b4_23to5_23), .out_c(matrixC4_23)); +processing_element pe4_24(.reset(effective_rst), .clk(clk), .in_a(a4_23to4_24), .in_b(b3_24to4_24), .out_a(a4_24to4_25), .out_b(b4_24to5_24), .out_c(matrixC4_24)); +processing_element pe4_25(.reset(effective_rst), .clk(clk), .in_a(a4_24to4_25), .in_b(b3_25to4_25), .out_a(a4_25to4_26), .out_b(b4_25to5_25), .out_c(matrixC4_25)); +processing_element pe4_26(.reset(effective_rst), .clk(clk), .in_a(a4_25to4_26), .in_b(b3_26to4_26), .out_a(a4_26to4_27), .out_b(b4_26to5_26), .out_c(matrixC4_26)); +processing_element pe4_27(.reset(effective_rst), .clk(clk), .in_a(a4_26to4_27), .in_b(b3_27to4_27), .out_a(a4_27to4_28), .out_b(b4_27to5_27), .out_c(matrixC4_27)); +processing_element pe4_28(.reset(effective_rst), .clk(clk), .in_a(a4_27to4_28), .in_b(b3_28to4_28), .out_a(a4_28to4_29), .out_b(b4_28to5_28), .out_c(matrixC4_28)); +processing_element pe4_29(.reset(effective_rst), .clk(clk), .in_a(a4_28to4_29), .in_b(b3_29to4_29), .out_a(a4_29to4_30), .out_b(b4_29to5_29), .out_c(matrixC4_29)); +processing_element pe4_30(.reset(effective_rst), .clk(clk), .in_a(a4_29to4_30), .in_b(b3_30to4_30), .out_a(a4_30to4_31), .out_b(b4_30to5_30), .out_c(matrixC4_30)); +processing_element pe4_31(.reset(effective_rst), .clk(clk), .in_a(a4_30to4_31), .in_b(b3_31to4_31), .out_a(a4_31to4_32), .out_b(b4_31to5_31), .out_c(matrixC4_31)); +processing_element pe5_1(.reset(effective_rst), .clk(clk), .in_a(a5_0to5_1), .in_b(b4_1to5_1), .out_a(a5_1to5_2), .out_b(b5_1to6_1), .out_c(matrixC5_1)); +processing_element pe5_2(.reset(effective_rst), .clk(clk), .in_a(a5_1to5_2), .in_b(b4_2to5_2), .out_a(a5_2to5_3), .out_b(b5_2to6_2), .out_c(matrixC5_2)); +processing_element pe5_3(.reset(effective_rst), .clk(clk), .in_a(a5_2to5_3), .in_b(b4_3to5_3), .out_a(a5_3to5_4), .out_b(b5_3to6_3), .out_c(matrixC5_3)); +processing_element pe5_4(.reset(effective_rst), .clk(clk), .in_a(a5_3to5_4), .in_b(b4_4to5_4), .out_a(a5_4to5_5), .out_b(b5_4to6_4), .out_c(matrixC5_4)); +processing_element pe5_5(.reset(effective_rst), .clk(clk), .in_a(a5_4to5_5), .in_b(b4_5to5_5), .out_a(a5_5to5_6), .out_b(b5_5to6_5), .out_c(matrixC5_5)); +processing_element pe5_6(.reset(effective_rst), .clk(clk), .in_a(a5_5to5_6), .in_b(b4_6to5_6), .out_a(a5_6to5_7), .out_b(b5_6to6_6), .out_c(matrixC5_6)); +processing_element pe5_7(.reset(effective_rst), .clk(clk), .in_a(a5_6to5_7), .in_b(b4_7to5_7), .out_a(a5_7to5_8), .out_b(b5_7to6_7), .out_c(matrixC5_7)); +processing_element pe5_8(.reset(effective_rst), .clk(clk), .in_a(a5_7to5_8), .in_b(b4_8to5_8), .out_a(a5_8to5_9), .out_b(b5_8to6_8), .out_c(matrixC5_8)); +processing_element pe5_9(.reset(effective_rst), .clk(clk), .in_a(a5_8to5_9), .in_b(b4_9to5_9), .out_a(a5_9to5_10), .out_b(b5_9to6_9), .out_c(matrixC5_9)); +processing_element pe5_10(.reset(effective_rst), .clk(clk), .in_a(a5_9to5_10), .in_b(b4_10to5_10), .out_a(a5_10to5_11), .out_b(b5_10to6_10), .out_c(matrixC5_10)); +processing_element pe5_11(.reset(effective_rst), .clk(clk), .in_a(a5_10to5_11), .in_b(b4_11to5_11), .out_a(a5_11to5_12), .out_b(b5_11to6_11), .out_c(matrixC5_11)); +processing_element pe5_12(.reset(effective_rst), .clk(clk), .in_a(a5_11to5_12), .in_b(b4_12to5_12), .out_a(a5_12to5_13), .out_b(b5_12to6_12), .out_c(matrixC5_12)); +processing_element pe5_13(.reset(effective_rst), .clk(clk), .in_a(a5_12to5_13), .in_b(b4_13to5_13), .out_a(a5_13to5_14), .out_b(b5_13to6_13), .out_c(matrixC5_13)); +processing_element pe5_14(.reset(effective_rst), .clk(clk), .in_a(a5_13to5_14), .in_b(b4_14to5_14), .out_a(a5_14to5_15), .out_b(b5_14to6_14), .out_c(matrixC5_14)); +processing_element pe5_15(.reset(effective_rst), .clk(clk), .in_a(a5_14to5_15), .in_b(b4_15to5_15), .out_a(a5_15to5_16), .out_b(b5_15to6_15), .out_c(matrixC5_15)); +processing_element pe5_16(.reset(effective_rst), .clk(clk), .in_a(a5_15to5_16), .in_b(b4_16to5_16), .out_a(a5_16to5_17), .out_b(b5_16to6_16), .out_c(matrixC5_16)); +processing_element pe5_17(.reset(effective_rst), .clk(clk), .in_a(a5_16to5_17), .in_b(b4_17to5_17), .out_a(a5_17to5_18), .out_b(b5_17to6_17), .out_c(matrixC5_17)); +processing_element pe5_18(.reset(effective_rst), .clk(clk), .in_a(a5_17to5_18), .in_b(b4_18to5_18), .out_a(a5_18to5_19), .out_b(b5_18to6_18), .out_c(matrixC5_18)); +processing_element pe5_19(.reset(effective_rst), .clk(clk), .in_a(a5_18to5_19), .in_b(b4_19to5_19), .out_a(a5_19to5_20), .out_b(b5_19to6_19), .out_c(matrixC5_19)); +processing_element pe5_20(.reset(effective_rst), .clk(clk), .in_a(a5_19to5_20), .in_b(b4_20to5_20), .out_a(a5_20to5_21), .out_b(b5_20to6_20), .out_c(matrixC5_20)); +processing_element pe5_21(.reset(effective_rst), .clk(clk), .in_a(a5_20to5_21), .in_b(b4_21to5_21), .out_a(a5_21to5_22), .out_b(b5_21to6_21), .out_c(matrixC5_21)); +processing_element pe5_22(.reset(effective_rst), .clk(clk), .in_a(a5_21to5_22), .in_b(b4_22to5_22), .out_a(a5_22to5_23), .out_b(b5_22to6_22), .out_c(matrixC5_22)); +processing_element pe5_23(.reset(effective_rst), .clk(clk), .in_a(a5_22to5_23), .in_b(b4_23to5_23), .out_a(a5_23to5_24), .out_b(b5_23to6_23), .out_c(matrixC5_23)); +processing_element pe5_24(.reset(effective_rst), .clk(clk), .in_a(a5_23to5_24), .in_b(b4_24to5_24), .out_a(a5_24to5_25), .out_b(b5_24to6_24), .out_c(matrixC5_24)); +processing_element pe5_25(.reset(effective_rst), .clk(clk), .in_a(a5_24to5_25), .in_b(b4_25to5_25), .out_a(a5_25to5_26), .out_b(b5_25to6_25), .out_c(matrixC5_25)); +processing_element pe5_26(.reset(effective_rst), .clk(clk), .in_a(a5_25to5_26), .in_b(b4_26to5_26), .out_a(a5_26to5_27), .out_b(b5_26to6_26), .out_c(matrixC5_26)); +processing_element pe5_27(.reset(effective_rst), .clk(clk), .in_a(a5_26to5_27), .in_b(b4_27to5_27), .out_a(a5_27to5_28), .out_b(b5_27to6_27), .out_c(matrixC5_27)); +processing_element pe5_28(.reset(effective_rst), .clk(clk), .in_a(a5_27to5_28), .in_b(b4_28to5_28), .out_a(a5_28to5_29), .out_b(b5_28to6_28), .out_c(matrixC5_28)); +processing_element pe5_29(.reset(effective_rst), .clk(clk), .in_a(a5_28to5_29), .in_b(b4_29to5_29), .out_a(a5_29to5_30), .out_b(b5_29to6_29), .out_c(matrixC5_29)); +processing_element pe5_30(.reset(effective_rst), .clk(clk), .in_a(a5_29to5_30), .in_b(b4_30to5_30), .out_a(a5_30to5_31), .out_b(b5_30to6_30), .out_c(matrixC5_30)); +processing_element pe5_31(.reset(effective_rst), .clk(clk), .in_a(a5_30to5_31), .in_b(b4_31to5_31), .out_a(a5_31to5_32), .out_b(b5_31to6_31), .out_c(matrixC5_31)); +processing_element pe6_1(.reset(effective_rst), .clk(clk), .in_a(a6_0to6_1), .in_b(b5_1to6_1), .out_a(a6_1to6_2), .out_b(b6_1to7_1), .out_c(matrixC6_1)); +processing_element pe6_2(.reset(effective_rst), .clk(clk), .in_a(a6_1to6_2), .in_b(b5_2to6_2), .out_a(a6_2to6_3), .out_b(b6_2to7_2), .out_c(matrixC6_2)); +processing_element pe6_3(.reset(effective_rst), .clk(clk), .in_a(a6_2to6_3), .in_b(b5_3to6_3), .out_a(a6_3to6_4), .out_b(b6_3to7_3), .out_c(matrixC6_3)); +processing_element pe6_4(.reset(effective_rst), .clk(clk), .in_a(a6_3to6_4), .in_b(b5_4to6_4), .out_a(a6_4to6_5), .out_b(b6_4to7_4), .out_c(matrixC6_4)); +processing_element pe6_5(.reset(effective_rst), .clk(clk), .in_a(a6_4to6_5), .in_b(b5_5to6_5), .out_a(a6_5to6_6), .out_b(b6_5to7_5), .out_c(matrixC6_5)); +processing_element pe6_6(.reset(effective_rst), .clk(clk), .in_a(a6_5to6_6), .in_b(b5_6to6_6), .out_a(a6_6to6_7), .out_b(b6_6to7_6), .out_c(matrixC6_6)); +processing_element pe6_7(.reset(effective_rst), .clk(clk), .in_a(a6_6to6_7), .in_b(b5_7to6_7), .out_a(a6_7to6_8), .out_b(b6_7to7_7), .out_c(matrixC6_7)); +processing_element pe6_8(.reset(effective_rst), .clk(clk), .in_a(a6_7to6_8), .in_b(b5_8to6_8), .out_a(a6_8to6_9), .out_b(b6_8to7_8), .out_c(matrixC6_8)); +processing_element pe6_9(.reset(effective_rst), .clk(clk), .in_a(a6_8to6_9), .in_b(b5_9to6_9), .out_a(a6_9to6_10), .out_b(b6_9to7_9), .out_c(matrixC6_9)); +processing_element pe6_10(.reset(effective_rst), .clk(clk), .in_a(a6_9to6_10), .in_b(b5_10to6_10), .out_a(a6_10to6_11), .out_b(b6_10to7_10), .out_c(matrixC6_10)); +processing_element pe6_11(.reset(effective_rst), .clk(clk), .in_a(a6_10to6_11), .in_b(b5_11to6_11), .out_a(a6_11to6_12), .out_b(b6_11to7_11), .out_c(matrixC6_11)); +processing_element pe6_12(.reset(effective_rst), .clk(clk), .in_a(a6_11to6_12), .in_b(b5_12to6_12), .out_a(a6_12to6_13), .out_b(b6_12to7_12), .out_c(matrixC6_12)); +processing_element pe6_13(.reset(effective_rst), .clk(clk), .in_a(a6_12to6_13), .in_b(b5_13to6_13), .out_a(a6_13to6_14), .out_b(b6_13to7_13), .out_c(matrixC6_13)); +processing_element pe6_14(.reset(effective_rst), .clk(clk), .in_a(a6_13to6_14), .in_b(b5_14to6_14), .out_a(a6_14to6_15), .out_b(b6_14to7_14), .out_c(matrixC6_14)); +processing_element pe6_15(.reset(effective_rst), .clk(clk), .in_a(a6_14to6_15), .in_b(b5_15to6_15), .out_a(a6_15to6_16), .out_b(b6_15to7_15), .out_c(matrixC6_15)); +processing_element pe6_16(.reset(effective_rst), .clk(clk), .in_a(a6_15to6_16), .in_b(b5_16to6_16), .out_a(a6_16to6_17), .out_b(b6_16to7_16), .out_c(matrixC6_16)); +processing_element pe6_17(.reset(effective_rst), .clk(clk), .in_a(a6_16to6_17), .in_b(b5_17to6_17), .out_a(a6_17to6_18), .out_b(b6_17to7_17), .out_c(matrixC6_17)); +processing_element pe6_18(.reset(effective_rst), .clk(clk), .in_a(a6_17to6_18), .in_b(b5_18to6_18), .out_a(a6_18to6_19), .out_b(b6_18to7_18), .out_c(matrixC6_18)); +processing_element pe6_19(.reset(effective_rst), .clk(clk), .in_a(a6_18to6_19), .in_b(b5_19to6_19), .out_a(a6_19to6_20), .out_b(b6_19to7_19), .out_c(matrixC6_19)); +processing_element pe6_20(.reset(effective_rst), .clk(clk), .in_a(a6_19to6_20), .in_b(b5_20to6_20), .out_a(a6_20to6_21), .out_b(b6_20to7_20), .out_c(matrixC6_20)); +processing_element pe6_21(.reset(effective_rst), .clk(clk), .in_a(a6_20to6_21), .in_b(b5_21to6_21), .out_a(a6_21to6_22), .out_b(b6_21to7_21), .out_c(matrixC6_21)); +processing_element pe6_22(.reset(effective_rst), .clk(clk), .in_a(a6_21to6_22), .in_b(b5_22to6_22), .out_a(a6_22to6_23), .out_b(b6_22to7_22), .out_c(matrixC6_22)); +processing_element pe6_23(.reset(effective_rst), .clk(clk), .in_a(a6_22to6_23), .in_b(b5_23to6_23), .out_a(a6_23to6_24), .out_b(b6_23to7_23), .out_c(matrixC6_23)); +processing_element pe6_24(.reset(effective_rst), .clk(clk), .in_a(a6_23to6_24), .in_b(b5_24to6_24), .out_a(a6_24to6_25), .out_b(b6_24to7_24), .out_c(matrixC6_24)); +processing_element pe6_25(.reset(effective_rst), .clk(clk), .in_a(a6_24to6_25), .in_b(b5_25to6_25), .out_a(a6_25to6_26), .out_b(b6_25to7_25), .out_c(matrixC6_25)); +processing_element pe6_26(.reset(effective_rst), .clk(clk), .in_a(a6_25to6_26), .in_b(b5_26to6_26), .out_a(a6_26to6_27), .out_b(b6_26to7_26), .out_c(matrixC6_26)); +processing_element pe6_27(.reset(effective_rst), .clk(clk), .in_a(a6_26to6_27), .in_b(b5_27to6_27), .out_a(a6_27to6_28), .out_b(b6_27to7_27), .out_c(matrixC6_27)); +processing_element pe6_28(.reset(effective_rst), .clk(clk), .in_a(a6_27to6_28), .in_b(b5_28to6_28), .out_a(a6_28to6_29), .out_b(b6_28to7_28), .out_c(matrixC6_28)); +processing_element pe6_29(.reset(effective_rst), .clk(clk), .in_a(a6_28to6_29), .in_b(b5_29to6_29), .out_a(a6_29to6_30), .out_b(b6_29to7_29), .out_c(matrixC6_29)); +processing_element pe6_30(.reset(effective_rst), .clk(clk), .in_a(a6_29to6_30), .in_b(b5_30to6_30), .out_a(a6_30to6_31), .out_b(b6_30to7_30), .out_c(matrixC6_30)); +processing_element pe6_31(.reset(effective_rst), .clk(clk), .in_a(a6_30to6_31), .in_b(b5_31to6_31), .out_a(a6_31to6_32), .out_b(b6_31to7_31), .out_c(matrixC6_31)); +processing_element pe7_1(.reset(effective_rst), .clk(clk), .in_a(a7_0to7_1), .in_b(b6_1to7_1), .out_a(a7_1to7_2), .out_b(b7_1to8_1), .out_c(matrixC7_1)); +processing_element pe7_2(.reset(effective_rst), .clk(clk), .in_a(a7_1to7_2), .in_b(b6_2to7_2), .out_a(a7_2to7_3), .out_b(b7_2to8_2), .out_c(matrixC7_2)); +processing_element pe7_3(.reset(effective_rst), .clk(clk), .in_a(a7_2to7_3), .in_b(b6_3to7_3), .out_a(a7_3to7_4), .out_b(b7_3to8_3), .out_c(matrixC7_3)); +processing_element pe7_4(.reset(effective_rst), .clk(clk), .in_a(a7_3to7_4), .in_b(b6_4to7_4), .out_a(a7_4to7_5), .out_b(b7_4to8_4), .out_c(matrixC7_4)); +processing_element pe7_5(.reset(effective_rst), .clk(clk), .in_a(a7_4to7_5), .in_b(b6_5to7_5), .out_a(a7_5to7_6), .out_b(b7_5to8_5), .out_c(matrixC7_5)); +processing_element pe7_6(.reset(effective_rst), .clk(clk), .in_a(a7_5to7_6), .in_b(b6_6to7_6), .out_a(a7_6to7_7), .out_b(b7_6to8_6), .out_c(matrixC7_6)); +processing_element pe7_7(.reset(effective_rst), .clk(clk), .in_a(a7_6to7_7), .in_b(b6_7to7_7), .out_a(a7_7to7_8), .out_b(b7_7to8_7), .out_c(matrixC7_7)); +processing_element pe7_8(.reset(effective_rst), .clk(clk), .in_a(a7_7to7_8), .in_b(b6_8to7_8), .out_a(a7_8to7_9), .out_b(b7_8to8_8), .out_c(matrixC7_8)); +processing_element pe7_9(.reset(effective_rst), .clk(clk), .in_a(a7_8to7_9), .in_b(b6_9to7_9), .out_a(a7_9to7_10), .out_b(b7_9to8_9), .out_c(matrixC7_9)); +processing_element pe7_10(.reset(effective_rst), .clk(clk), .in_a(a7_9to7_10), .in_b(b6_10to7_10), .out_a(a7_10to7_11), .out_b(b7_10to8_10), .out_c(matrixC7_10)); +processing_element pe7_11(.reset(effective_rst), .clk(clk), .in_a(a7_10to7_11), .in_b(b6_11to7_11), .out_a(a7_11to7_12), .out_b(b7_11to8_11), .out_c(matrixC7_11)); +processing_element pe7_12(.reset(effective_rst), .clk(clk), .in_a(a7_11to7_12), .in_b(b6_12to7_12), .out_a(a7_12to7_13), .out_b(b7_12to8_12), .out_c(matrixC7_12)); +processing_element pe7_13(.reset(effective_rst), .clk(clk), .in_a(a7_12to7_13), .in_b(b6_13to7_13), .out_a(a7_13to7_14), .out_b(b7_13to8_13), .out_c(matrixC7_13)); +processing_element pe7_14(.reset(effective_rst), .clk(clk), .in_a(a7_13to7_14), .in_b(b6_14to7_14), .out_a(a7_14to7_15), .out_b(b7_14to8_14), .out_c(matrixC7_14)); +processing_element pe7_15(.reset(effective_rst), .clk(clk), .in_a(a7_14to7_15), .in_b(b6_15to7_15), .out_a(a7_15to7_16), .out_b(b7_15to8_15), .out_c(matrixC7_15)); +processing_element pe7_16(.reset(effective_rst), .clk(clk), .in_a(a7_15to7_16), .in_b(b6_16to7_16), .out_a(a7_16to7_17), .out_b(b7_16to8_16), .out_c(matrixC7_16)); +processing_element pe7_17(.reset(effective_rst), .clk(clk), .in_a(a7_16to7_17), .in_b(b6_17to7_17), .out_a(a7_17to7_18), .out_b(b7_17to8_17), .out_c(matrixC7_17)); +processing_element pe7_18(.reset(effective_rst), .clk(clk), .in_a(a7_17to7_18), .in_b(b6_18to7_18), .out_a(a7_18to7_19), .out_b(b7_18to8_18), .out_c(matrixC7_18)); +processing_element pe7_19(.reset(effective_rst), .clk(clk), .in_a(a7_18to7_19), .in_b(b6_19to7_19), .out_a(a7_19to7_20), .out_b(b7_19to8_19), .out_c(matrixC7_19)); +processing_element pe7_20(.reset(effective_rst), .clk(clk), .in_a(a7_19to7_20), .in_b(b6_20to7_20), .out_a(a7_20to7_21), .out_b(b7_20to8_20), .out_c(matrixC7_20)); +processing_element pe7_21(.reset(effective_rst), .clk(clk), .in_a(a7_20to7_21), .in_b(b6_21to7_21), .out_a(a7_21to7_22), .out_b(b7_21to8_21), .out_c(matrixC7_21)); +processing_element pe7_22(.reset(effective_rst), .clk(clk), .in_a(a7_21to7_22), .in_b(b6_22to7_22), .out_a(a7_22to7_23), .out_b(b7_22to8_22), .out_c(matrixC7_22)); +processing_element pe7_23(.reset(effective_rst), .clk(clk), .in_a(a7_22to7_23), .in_b(b6_23to7_23), .out_a(a7_23to7_24), .out_b(b7_23to8_23), .out_c(matrixC7_23)); +processing_element pe7_24(.reset(effective_rst), .clk(clk), .in_a(a7_23to7_24), .in_b(b6_24to7_24), .out_a(a7_24to7_25), .out_b(b7_24to8_24), .out_c(matrixC7_24)); +processing_element pe7_25(.reset(effective_rst), .clk(clk), .in_a(a7_24to7_25), .in_b(b6_25to7_25), .out_a(a7_25to7_26), .out_b(b7_25to8_25), .out_c(matrixC7_25)); +processing_element pe7_26(.reset(effective_rst), .clk(clk), .in_a(a7_25to7_26), .in_b(b6_26to7_26), .out_a(a7_26to7_27), .out_b(b7_26to8_26), .out_c(matrixC7_26)); +processing_element pe7_27(.reset(effective_rst), .clk(clk), .in_a(a7_26to7_27), .in_b(b6_27to7_27), .out_a(a7_27to7_28), .out_b(b7_27to8_27), .out_c(matrixC7_27)); +processing_element pe7_28(.reset(effective_rst), .clk(clk), .in_a(a7_27to7_28), .in_b(b6_28to7_28), .out_a(a7_28to7_29), .out_b(b7_28to8_28), .out_c(matrixC7_28)); +processing_element pe7_29(.reset(effective_rst), .clk(clk), .in_a(a7_28to7_29), .in_b(b6_29to7_29), .out_a(a7_29to7_30), .out_b(b7_29to8_29), .out_c(matrixC7_29)); +processing_element pe7_30(.reset(effective_rst), .clk(clk), .in_a(a7_29to7_30), .in_b(b6_30to7_30), .out_a(a7_30to7_31), .out_b(b7_30to8_30), .out_c(matrixC7_30)); +processing_element pe7_31(.reset(effective_rst), .clk(clk), .in_a(a7_30to7_31), .in_b(b6_31to7_31), .out_a(a7_31to7_32), .out_b(b7_31to8_31), .out_c(matrixC7_31)); +processing_element pe8_1(.reset(effective_rst), .clk(clk), .in_a(a8_0to8_1), .in_b(b7_1to8_1), .out_a(a8_1to8_2), .out_b(b8_1to9_1), .out_c(matrixC8_1)); +processing_element pe8_2(.reset(effective_rst), .clk(clk), .in_a(a8_1to8_2), .in_b(b7_2to8_2), .out_a(a8_2to8_3), .out_b(b8_2to9_2), .out_c(matrixC8_2)); +processing_element pe8_3(.reset(effective_rst), .clk(clk), .in_a(a8_2to8_3), .in_b(b7_3to8_3), .out_a(a8_3to8_4), .out_b(b8_3to9_3), .out_c(matrixC8_3)); +processing_element pe8_4(.reset(effective_rst), .clk(clk), .in_a(a8_3to8_4), .in_b(b7_4to8_4), .out_a(a8_4to8_5), .out_b(b8_4to9_4), .out_c(matrixC8_4)); +processing_element pe8_5(.reset(effective_rst), .clk(clk), .in_a(a8_4to8_5), .in_b(b7_5to8_5), .out_a(a8_5to8_6), .out_b(b8_5to9_5), .out_c(matrixC8_5)); +processing_element pe8_6(.reset(effective_rst), .clk(clk), .in_a(a8_5to8_6), .in_b(b7_6to8_6), .out_a(a8_6to8_7), .out_b(b8_6to9_6), .out_c(matrixC8_6)); +processing_element pe8_7(.reset(effective_rst), .clk(clk), .in_a(a8_6to8_7), .in_b(b7_7to8_7), .out_a(a8_7to8_8), .out_b(b8_7to9_7), .out_c(matrixC8_7)); +processing_element pe8_8(.reset(effective_rst), .clk(clk), .in_a(a8_7to8_8), .in_b(b7_8to8_8), .out_a(a8_8to8_9), .out_b(b8_8to9_8), .out_c(matrixC8_8)); +processing_element pe8_9(.reset(effective_rst), .clk(clk), .in_a(a8_8to8_9), .in_b(b7_9to8_9), .out_a(a8_9to8_10), .out_b(b8_9to9_9), .out_c(matrixC8_9)); +processing_element pe8_10(.reset(effective_rst), .clk(clk), .in_a(a8_9to8_10), .in_b(b7_10to8_10), .out_a(a8_10to8_11), .out_b(b8_10to9_10), .out_c(matrixC8_10)); +processing_element pe8_11(.reset(effective_rst), .clk(clk), .in_a(a8_10to8_11), .in_b(b7_11to8_11), .out_a(a8_11to8_12), .out_b(b8_11to9_11), .out_c(matrixC8_11)); +processing_element pe8_12(.reset(effective_rst), .clk(clk), .in_a(a8_11to8_12), .in_b(b7_12to8_12), .out_a(a8_12to8_13), .out_b(b8_12to9_12), .out_c(matrixC8_12)); +processing_element pe8_13(.reset(effective_rst), .clk(clk), .in_a(a8_12to8_13), .in_b(b7_13to8_13), .out_a(a8_13to8_14), .out_b(b8_13to9_13), .out_c(matrixC8_13)); +processing_element pe8_14(.reset(effective_rst), .clk(clk), .in_a(a8_13to8_14), .in_b(b7_14to8_14), .out_a(a8_14to8_15), .out_b(b8_14to9_14), .out_c(matrixC8_14)); +processing_element pe8_15(.reset(effective_rst), .clk(clk), .in_a(a8_14to8_15), .in_b(b7_15to8_15), .out_a(a8_15to8_16), .out_b(b8_15to9_15), .out_c(matrixC8_15)); +processing_element pe8_16(.reset(effective_rst), .clk(clk), .in_a(a8_15to8_16), .in_b(b7_16to8_16), .out_a(a8_16to8_17), .out_b(b8_16to9_16), .out_c(matrixC8_16)); +processing_element pe8_17(.reset(effective_rst), .clk(clk), .in_a(a8_16to8_17), .in_b(b7_17to8_17), .out_a(a8_17to8_18), .out_b(b8_17to9_17), .out_c(matrixC8_17)); +processing_element pe8_18(.reset(effective_rst), .clk(clk), .in_a(a8_17to8_18), .in_b(b7_18to8_18), .out_a(a8_18to8_19), .out_b(b8_18to9_18), .out_c(matrixC8_18)); +processing_element pe8_19(.reset(effective_rst), .clk(clk), .in_a(a8_18to8_19), .in_b(b7_19to8_19), .out_a(a8_19to8_20), .out_b(b8_19to9_19), .out_c(matrixC8_19)); +processing_element pe8_20(.reset(effective_rst), .clk(clk), .in_a(a8_19to8_20), .in_b(b7_20to8_20), .out_a(a8_20to8_21), .out_b(b8_20to9_20), .out_c(matrixC8_20)); +processing_element pe8_21(.reset(effective_rst), .clk(clk), .in_a(a8_20to8_21), .in_b(b7_21to8_21), .out_a(a8_21to8_22), .out_b(b8_21to9_21), .out_c(matrixC8_21)); +processing_element pe8_22(.reset(effective_rst), .clk(clk), .in_a(a8_21to8_22), .in_b(b7_22to8_22), .out_a(a8_22to8_23), .out_b(b8_22to9_22), .out_c(matrixC8_22)); +processing_element pe8_23(.reset(effective_rst), .clk(clk), .in_a(a8_22to8_23), .in_b(b7_23to8_23), .out_a(a8_23to8_24), .out_b(b8_23to9_23), .out_c(matrixC8_23)); +processing_element pe8_24(.reset(effective_rst), .clk(clk), .in_a(a8_23to8_24), .in_b(b7_24to8_24), .out_a(a8_24to8_25), .out_b(b8_24to9_24), .out_c(matrixC8_24)); +processing_element pe8_25(.reset(effective_rst), .clk(clk), .in_a(a8_24to8_25), .in_b(b7_25to8_25), .out_a(a8_25to8_26), .out_b(b8_25to9_25), .out_c(matrixC8_25)); +processing_element pe8_26(.reset(effective_rst), .clk(clk), .in_a(a8_25to8_26), .in_b(b7_26to8_26), .out_a(a8_26to8_27), .out_b(b8_26to9_26), .out_c(matrixC8_26)); +processing_element pe8_27(.reset(effective_rst), .clk(clk), .in_a(a8_26to8_27), .in_b(b7_27to8_27), .out_a(a8_27to8_28), .out_b(b8_27to9_27), .out_c(matrixC8_27)); +processing_element pe8_28(.reset(effective_rst), .clk(clk), .in_a(a8_27to8_28), .in_b(b7_28to8_28), .out_a(a8_28to8_29), .out_b(b8_28to9_28), .out_c(matrixC8_28)); +processing_element pe8_29(.reset(effective_rst), .clk(clk), .in_a(a8_28to8_29), .in_b(b7_29to8_29), .out_a(a8_29to8_30), .out_b(b8_29to9_29), .out_c(matrixC8_29)); +processing_element pe8_30(.reset(effective_rst), .clk(clk), .in_a(a8_29to8_30), .in_b(b7_30to8_30), .out_a(a8_30to8_31), .out_b(b8_30to9_30), .out_c(matrixC8_30)); +processing_element pe8_31(.reset(effective_rst), .clk(clk), .in_a(a8_30to8_31), .in_b(b7_31to8_31), .out_a(a8_31to8_32), .out_b(b8_31to9_31), .out_c(matrixC8_31)); +processing_element pe9_1(.reset(effective_rst), .clk(clk), .in_a(a9_0to9_1), .in_b(b8_1to9_1), .out_a(a9_1to9_2), .out_b(b9_1to10_1), .out_c(matrixC9_1)); +processing_element pe9_2(.reset(effective_rst), .clk(clk), .in_a(a9_1to9_2), .in_b(b8_2to9_2), .out_a(a9_2to9_3), .out_b(b9_2to10_2), .out_c(matrixC9_2)); +processing_element pe9_3(.reset(effective_rst), .clk(clk), .in_a(a9_2to9_3), .in_b(b8_3to9_3), .out_a(a9_3to9_4), .out_b(b9_3to10_3), .out_c(matrixC9_3)); +processing_element pe9_4(.reset(effective_rst), .clk(clk), .in_a(a9_3to9_4), .in_b(b8_4to9_4), .out_a(a9_4to9_5), .out_b(b9_4to10_4), .out_c(matrixC9_4)); +processing_element pe9_5(.reset(effective_rst), .clk(clk), .in_a(a9_4to9_5), .in_b(b8_5to9_5), .out_a(a9_5to9_6), .out_b(b9_5to10_5), .out_c(matrixC9_5)); +processing_element pe9_6(.reset(effective_rst), .clk(clk), .in_a(a9_5to9_6), .in_b(b8_6to9_6), .out_a(a9_6to9_7), .out_b(b9_6to10_6), .out_c(matrixC9_6)); +processing_element pe9_7(.reset(effective_rst), .clk(clk), .in_a(a9_6to9_7), .in_b(b8_7to9_7), .out_a(a9_7to9_8), .out_b(b9_7to10_7), .out_c(matrixC9_7)); +processing_element pe9_8(.reset(effective_rst), .clk(clk), .in_a(a9_7to9_8), .in_b(b8_8to9_8), .out_a(a9_8to9_9), .out_b(b9_8to10_8), .out_c(matrixC9_8)); +processing_element pe9_9(.reset(effective_rst), .clk(clk), .in_a(a9_8to9_9), .in_b(b8_9to9_9), .out_a(a9_9to9_10), .out_b(b9_9to10_9), .out_c(matrixC9_9)); +processing_element pe9_10(.reset(effective_rst), .clk(clk), .in_a(a9_9to9_10), .in_b(b8_10to9_10), .out_a(a9_10to9_11), .out_b(b9_10to10_10), .out_c(matrixC9_10)); +processing_element pe9_11(.reset(effective_rst), .clk(clk), .in_a(a9_10to9_11), .in_b(b8_11to9_11), .out_a(a9_11to9_12), .out_b(b9_11to10_11), .out_c(matrixC9_11)); +processing_element pe9_12(.reset(effective_rst), .clk(clk), .in_a(a9_11to9_12), .in_b(b8_12to9_12), .out_a(a9_12to9_13), .out_b(b9_12to10_12), .out_c(matrixC9_12)); +processing_element pe9_13(.reset(effective_rst), .clk(clk), .in_a(a9_12to9_13), .in_b(b8_13to9_13), .out_a(a9_13to9_14), .out_b(b9_13to10_13), .out_c(matrixC9_13)); +processing_element pe9_14(.reset(effective_rst), .clk(clk), .in_a(a9_13to9_14), .in_b(b8_14to9_14), .out_a(a9_14to9_15), .out_b(b9_14to10_14), .out_c(matrixC9_14)); +processing_element pe9_15(.reset(effective_rst), .clk(clk), .in_a(a9_14to9_15), .in_b(b8_15to9_15), .out_a(a9_15to9_16), .out_b(b9_15to10_15), .out_c(matrixC9_15)); +processing_element pe9_16(.reset(effective_rst), .clk(clk), .in_a(a9_15to9_16), .in_b(b8_16to9_16), .out_a(a9_16to9_17), .out_b(b9_16to10_16), .out_c(matrixC9_16)); +processing_element pe9_17(.reset(effective_rst), .clk(clk), .in_a(a9_16to9_17), .in_b(b8_17to9_17), .out_a(a9_17to9_18), .out_b(b9_17to10_17), .out_c(matrixC9_17)); +processing_element pe9_18(.reset(effective_rst), .clk(clk), .in_a(a9_17to9_18), .in_b(b8_18to9_18), .out_a(a9_18to9_19), .out_b(b9_18to10_18), .out_c(matrixC9_18)); +processing_element pe9_19(.reset(effective_rst), .clk(clk), .in_a(a9_18to9_19), .in_b(b8_19to9_19), .out_a(a9_19to9_20), .out_b(b9_19to10_19), .out_c(matrixC9_19)); +processing_element pe9_20(.reset(effective_rst), .clk(clk), .in_a(a9_19to9_20), .in_b(b8_20to9_20), .out_a(a9_20to9_21), .out_b(b9_20to10_20), .out_c(matrixC9_20)); +processing_element pe9_21(.reset(effective_rst), .clk(clk), .in_a(a9_20to9_21), .in_b(b8_21to9_21), .out_a(a9_21to9_22), .out_b(b9_21to10_21), .out_c(matrixC9_21)); +processing_element pe9_22(.reset(effective_rst), .clk(clk), .in_a(a9_21to9_22), .in_b(b8_22to9_22), .out_a(a9_22to9_23), .out_b(b9_22to10_22), .out_c(matrixC9_22)); +processing_element pe9_23(.reset(effective_rst), .clk(clk), .in_a(a9_22to9_23), .in_b(b8_23to9_23), .out_a(a9_23to9_24), .out_b(b9_23to10_23), .out_c(matrixC9_23)); +processing_element pe9_24(.reset(effective_rst), .clk(clk), .in_a(a9_23to9_24), .in_b(b8_24to9_24), .out_a(a9_24to9_25), .out_b(b9_24to10_24), .out_c(matrixC9_24)); +processing_element pe9_25(.reset(effective_rst), .clk(clk), .in_a(a9_24to9_25), .in_b(b8_25to9_25), .out_a(a9_25to9_26), .out_b(b9_25to10_25), .out_c(matrixC9_25)); +processing_element pe9_26(.reset(effective_rst), .clk(clk), .in_a(a9_25to9_26), .in_b(b8_26to9_26), .out_a(a9_26to9_27), .out_b(b9_26to10_26), .out_c(matrixC9_26)); +processing_element pe9_27(.reset(effective_rst), .clk(clk), .in_a(a9_26to9_27), .in_b(b8_27to9_27), .out_a(a9_27to9_28), .out_b(b9_27to10_27), .out_c(matrixC9_27)); +processing_element pe9_28(.reset(effective_rst), .clk(clk), .in_a(a9_27to9_28), .in_b(b8_28to9_28), .out_a(a9_28to9_29), .out_b(b9_28to10_28), .out_c(matrixC9_28)); +processing_element pe9_29(.reset(effective_rst), .clk(clk), .in_a(a9_28to9_29), .in_b(b8_29to9_29), .out_a(a9_29to9_30), .out_b(b9_29to10_29), .out_c(matrixC9_29)); +processing_element pe9_30(.reset(effective_rst), .clk(clk), .in_a(a9_29to9_30), .in_b(b8_30to9_30), .out_a(a9_30to9_31), .out_b(b9_30to10_30), .out_c(matrixC9_30)); +processing_element pe9_31(.reset(effective_rst), .clk(clk), .in_a(a9_30to9_31), .in_b(b8_31to9_31), .out_a(a9_31to9_32), .out_b(b9_31to10_31), .out_c(matrixC9_31)); +processing_element pe10_1(.reset(effective_rst), .clk(clk), .in_a(a10_0to10_1), .in_b(b9_1to10_1), .out_a(a10_1to10_2), .out_b(b10_1to11_1), .out_c(matrixC10_1)); +processing_element pe10_2(.reset(effective_rst), .clk(clk), .in_a(a10_1to10_2), .in_b(b9_2to10_2), .out_a(a10_2to10_3), .out_b(b10_2to11_2), .out_c(matrixC10_2)); +processing_element pe10_3(.reset(effective_rst), .clk(clk), .in_a(a10_2to10_3), .in_b(b9_3to10_3), .out_a(a10_3to10_4), .out_b(b10_3to11_3), .out_c(matrixC10_3)); +processing_element pe10_4(.reset(effective_rst), .clk(clk), .in_a(a10_3to10_4), .in_b(b9_4to10_4), .out_a(a10_4to10_5), .out_b(b10_4to11_4), .out_c(matrixC10_4)); +processing_element pe10_5(.reset(effective_rst), .clk(clk), .in_a(a10_4to10_5), .in_b(b9_5to10_5), .out_a(a10_5to10_6), .out_b(b10_5to11_5), .out_c(matrixC10_5)); +processing_element pe10_6(.reset(effective_rst), .clk(clk), .in_a(a10_5to10_6), .in_b(b9_6to10_6), .out_a(a10_6to10_7), .out_b(b10_6to11_6), .out_c(matrixC10_6)); +processing_element pe10_7(.reset(effective_rst), .clk(clk), .in_a(a10_6to10_7), .in_b(b9_7to10_7), .out_a(a10_7to10_8), .out_b(b10_7to11_7), .out_c(matrixC10_7)); +processing_element pe10_8(.reset(effective_rst), .clk(clk), .in_a(a10_7to10_8), .in_b(b9_8to10_8), .out_a(a10_8to10_9), .out_b(b10_8to11_8), .out_c(matrixC10_8)); +processing_element pe10_9(.reset(effective_rst), .clk(clk), .in_a(a10_8to10_9), .in_b(b9_9to10_9), .out_a(a10_9to10_10), .out_b(b10_9to11_9), .out_c(matrixC10_9)); +processing_element pe10_10(.reset(effective_rst), .clk(clk), .in_a(a10_9to10_10), .in_b(b9_10to10_10), .out_a(a10_10to10_11), .out_b(b10_10to11_10), .out_c(matrixC10_10)); +processing_element pe10_11(.reset(effective_rst), .clk(clk), .in_a(a10_10to10_11), .in_b(b9_11to10_11), .out_a(a10_11to10_12), .out_b(b10_11to11_11), .out_c(matrixC10_11)); +processing_element pe10_12(.reset(effective_rst), .clk(clk), .in_a(a10_11to10_12), .in_b(b9_12to10_12), .out_a(a10_12to10_13), .out_b(b10_12to11_12), .out_c(matrixC10_12)); +processing_element pe10_13(.reset(effective_rst), .clk(clk), .in_a(a10_12to10_13), .in_b(b9_13to10_13), .out_a(a10_13to10_14), .out_b(b10_13to11_13), .out_c(matrixC10_13)); +processing_element pe10_14(.reset(effective_rst), .clk(clk), .in_a(a10_13to10_14), .in_b(b9_14to10_14), .out_a(a10_14to10_15), .out_b(b10_14to11_14), .out_c(matrixC10_14)); +processing_element pe10_15(.reset(effective_rst), .clk(clk), .in_a(a10_14to10_15), .in_b(b9_15to10_15), .out_a(a10_15to10_16), .out_b(b10_15to11_15), .out_c(matrixC10_15)); +processing_element pe10_16(.reset(effective_rst), .clk(clk), .in_a(a10_15to10_16), .in_b(b9_16to10_16), .out_a(a10_16to10_17), .out_b(b10_16to11_16), .out_c(matrixC10_16)); +processing_element pe10_17(.reset(effective_rst), .clk(clk), .in_a(a10_16to10_17), .in_b(b9_17to10_17), .out_a(a10_17to10_18), .out_b(b10_17to11_17), .out_c(matrixC10_17)); +processing_element pe10_18(.reset(effective_rst), .clk(clk), .in_a(a10_17to10_18), .in_b(b9_18to10_18), .out_a(a10_18to10_19), .out_b(b10_18to11_18), .out_c(matrixC10_18)); +processing_element pe10_19(.reset(effective_rst), .clk(clk), .in_a(a10_18to10_19), .in_b(b9_19to10_19), .out_a(a10_19to10_20), .out_b(b10_19to11_19), .out_c(matrixC10_19)); +processing_element pe10_20(.reset(effective_rst), .clk(clk), .in_a(a10_19to10_20), .in_b(b9_20to10_20), .out_a(a10_20to10_21), .out_b(b10_20to11_20), .out_c(matrixC10_20)); +processing_element pe10_21(.reset(effective_rst), .clk(clk), .in_a(a10_20to10_21), .in_b(b9_21to10_21), .out_a(a10_21to10_22), .out_b(b10_21to11_21), .out_c(matrixC10_21)); +processing_element pe10_22(.reset(effective_rst), .clk(clk), .in_a(a10_21to10_22), .in_b(b9_22to10_22), .out_a(a10_22to10_23), .out_b(b10_22to11_22), .out_c(matrixC10_22)); +processing_element pe10_23(.reset(effective_rst), .clk(clk), .in_a(a10_22to10_23), .in_b(b9_23to10_23), .out_a(a10_23to10_24), .out_b(b10_23to11_23), .out_c(matrixC10_23)); +processing_element pe10_24(.reset(effective_rst), .clk(clk), .in_a(a10_23to10_24), .in_b(b9_24to10_24), .out_a(a10_24to10_25), .out_b(b10_24to11_24), .out_c(matrixC10_24)); +processing_element pe10_25(.reset(effective_rst), .clk(clk), .in_a(a10_24to10_25), .in_b(b9_25to10_25), .out_a(a10_25to10_26), .out_b(b10_25to11_25), .out_c(matrixC10_25)); +processing_element pe10_26(.reset(effective_rst), .clk(clk), .in_a(a10_25to10_26), .in_b(b9_26to10_26), .out_a(a10_26to10_27), .out_b(b10_26to11_26), .out_c(matrixC10_26)); +processing_element pe10_27(.reset(effective_rst), .clk(clk), .in_a(a10_26to10_27), .in_b(b9_27to10_27), .out_a(a10_27to10_28), .out_b(b10_27to11_27), .out_c(matrixC10_27)); +processing_element pe10_28(.reset(effective_rst), .clk(clk), .in_a(a10_27to10_28), .in_b(b9_28to10_28), .out_a(a10_28to10_29), .out_b(b10_28to11_28), .out_c(matrixC10_28)); +processing_element pe10_29(.reset(effective_rst), .clk(clk), .in_a(a10_28to10_29), .in_b(b9_29to10_29), .out_a(a10_29to10_30), .out_b(b10_29to11_29), .out_c(matrixC10_29)); +processing_element pe10_30(.reset(effective_rst), .clk(clk), .in_a(a10_29to10_30), .in_b(b9_30to10_30), .out_a(a10_30to10_31), .out_b(b10_30to11_30), .out_c(matrixC10_30)); +processing_element pe10_31(.reset(effective_rst), .clk(clk), .in_a(a10_30to10_31), .in_b(b9_31to10_31), .out_a(a10_31to10_32), .out_b(b10_31to11_31), .out_c(matrixC10_31)); +processing_element pe11_1(.reset(effective_rst), .clk(clk), .in_a(a11_0to11_1), .in_b(b10_1to11_1), .out_a(a11_1to11_2), .out_b(b11_1to12_1), .out_c(matrixC11_1)); +processing_element pe11_2(.reset(effective_rst), .clk(clk), .in_a(a11_1to11_2), .in_b(b10_2to11_2), .out_a(a11_2to11_3), .out_b(b11_2to12_2), .out_c(matrixC11_2)); +processing_element pe11_3(.reset(effective_rst), .clk(clk), .in_a(a11_2to11_3), .in_b(b10_3to11_3), .out_a(a11_3to11_4), .out_b(b11_3to12_3), .out_c(matrixC11_3)); +processing_element pe11_4(.reset(effective_rst), .clk(clk), .in_a(a11_3to11_4), .in_b(b10_4to11_4), .out_a(a11_4to11_5), .out_b(b11_4to12_4), .out_c(matrixC11_4)); +processing_element pe11_5(.reset(effective_rst), .clk(clk), .in_a(a11_4to11_5), .in_b(b10_5to11_5), .out_a(a11_5to11_6), .out_b(b11_5to12_5), .out_c(matrixC11_5)); +processing_element pe11_6(.reset(effective_rst), .clk(clk), .in_a(a11_5to11_6), .in_b(b10_6to11_6), .out_a(a11_6to11_7), .out_b(b11_6to12_6), .out_c(matrixC11_6)); +processing_element pe11_7(.reset(effective_rst), .clk(clk), .in_a(a11_6to11_7), .in_b(b10_7to11_7), .out_a(a11_7to11_8), .out_b(b11_7to12_7), .out_c(matrixC11_7)); +processing_element pe11_8(.reset(effective_rst), .clk(clk), .in_a(a11_7to11_8), .in_b(b10_8to11_8), .out_a(a11_8to11_9), .out_b(b11_8to12_8), .out_c(matrixC11_8)); +processing_element pe11_9(.reset(effective_rst), .clk(clk), .in_a(a11_8to11_9), .in_b(b10_9to11_9), .out_a(a11_9to11_10), .out_b(b11_9to12_9), .out_c(matrixC11_9)); +processing_element pe11_10(.reset(effective_rst), .clk(clk), .in_a(a11_9to11_10), .in_b(b10_10to11_10), .out_a(a11_10to11_11), .out_b(b11_10to12_10), .out_c(matrixC11_10)); +processing_element pe11_11(.reset(effective_rst), .clk(clk), .in_a(a11_10to11_11), .in_b(b10_11to11_11), .out_a(a11_11to11_12), .out_b(b11_11to12_11), .out_c(matrixC11_11)); +processing_element pe11_12(.reset(effective_rst), .clk(clk), .in_a(a11_11to11_12), .in_b(b10_12to11_12), .out_a(a11_12to11_13), .out_b(b11_12to12_12), .out_c(matrixC11_12)); +processing_element pe11_13(.reset(effective_rst), .clk(clk), .in_a(a11_12to11_13), .in_b(b10_13to11_13), .out_a(a11_13to11_14), .out_b(b11_13to12_13), .out_c(matrixC11_13)); +processing_element pe11_14(.reset(effective_rst), .clk(clk), .in_a(a11_13to11_14), .in_b(b10_14to11_14), .out_a(a11_14to11_15), .out_b(b11_14to12_14), .out_c(matrixC11_14)); +processing_element pe11_15(.reset(effective_rst), .clk(clk), .in_a(a11_14to11_15), .in_b(b10_15to11_15), .out_a(a11_15to11_16), .out_b(b11_15to12_15), .out_c(matrixC11_15)); +processing_element pe11_16(.reset(effective_rst), .clk(clk), .in_a(a11_15to11_16), .in_b(b10_16to11_16), .out_a(a11_16to11_17), .out_b(b11_16to12_16), .out_c(matrixC11_16)); +processing_element pe11_17(.reset(effective_rst), .clk(clk), .in_a(a11_16to11_17), .in_b(b10_17to11_17), .out_a(a11_17to11_18), .out_b(b11_17to12_17), .out_c(matrixC11_17)); +processing_element pe11_18(.reset(effective_rst), .clk(clk), .in_a(a11_17to11_18), .in_b(b10_18to11_18), .out_a(a11_18to11_19), .out_b(b11_18to12_18), .out_c(matrixC11_18)); +processing_element pe11_19(.reset(effective_rst), .clk(clk), .in_a(a11_18to11_19), .in_b(b10_19to11_19), .out_a(a11_19to11_20), .out_b(b11_19to12_19), .out_c(matrixC11_19)); +processing_element pe11_20(.reset(effective_rst), .clk(clk), .in_a(a11_19to11_20), .in_b(b10_20to11_20), .out_a(a11_20to11_21), .out_b(b11_20to12_20), .out_c(matrixC11_20)); +processing_element pe11_21(.reset(effective_rst), .clk(clk), .in_a(a11_20to11_21), .in_b(b10_21to11_21), .out_a(a11_21to11_22), .out_b(b11_21to12_21), .out_c(matrixC11_21)); +processing_element pe11_22(.reset(effective_rst), .clk(clk), .in_a(a11_21to11_22), .in_b(b10_22to11_22), .out_a(a11_22to11_23), .out_b(b11_22to12_22), .out_c(matrixC11_22)); +processing_element pe11_23(.reset(effective_rst), .clk(clk), .in_a(a11_22to11_23), .in_b(b10_23to11_23), .out_a(a11_23to11_24), .out_b(b11_23to12_23), .out_c(matrixC11_23)); +processing_element pe11_24(.reset(effective_rst), .clk(clk), .in_a(a11_23to11_24), .in_b(b10_24to11_24), .out_a(a11_24to11_25), .out_b(b11_24to12_24), .out_c(matrixC11_24)); +processing_element pe11_25(.reset(effective_rst), .clk(clk), .in_a(a11_24to11_25), .in_b(b10_25to11_25), .out_a(a11_25to11_26), .out_b(b11_25to12_25), .out_c(matrixC11_25)); +processing_element pe11_26(.reset(effective_rst), .clk(clk), .in_a(a11_25to11_26), .in_b(b10_26to11_26), .out_a(a11_26to11_27), .out_b(b11_26to12_26), .out_c(matrixC11_26)); +processing_element pe11_27(.reset(effective_rst), .clk(clk), .in_a(a11_26to11_27), .in_b(b10_27to11_27), .out_a(a11_27to11_28), .out_b(b11_27to12_27), .out_c(matrixC11_27)); +processing_element pe11_28(.reset(effective_rst), .clk(clk), .in_a(a11_27to11_28), .in_b(b10_28to11_28), .out_a(a11_28to11_29), .out_b(b11_28to12_28), .out_c(matrixC11_28)); +processing_element pe11_29(.reset(effective_rst), .clk(clk), .in_a(a11_28to11_29), .in_b(b10_29to11_29), .out_a(a11_29to11_30), .out_b(b11_29to12_29), .out_c(matrixC11_29)); +processing_element pe11_30(.reset(effective_rst), .clk(clk), .in_a(a11_29to11_30), .in_b(b10_30to11_30), .out_a(a11_30to11_31), .out_b(b11_30to12_30), .out_c(matrixC11_30)); +processing_element pe11_31(.reset(effective_rst), .clk(clk), .in_a(a11_30to11_31), .in_b(b10_31to11_31), .out_a(a11_31to11_32), .out_b(b11_31to12_31), .out_c(matrixC11_31)); +processing_element pe12_1(.reset(effective_rst), .clk(clk), .in_a(a12_0to12_1), .in_b(b11_1to12_1), .out_a(a12_1to12_2), .out_b(b12_1to13_1), .out_c(matrixC12_1)); +processing_element pe12_2(.reset(effective_rst), .clk(clk), .in_a(a12_1to12_2), .in_b(b11_2to12_2), .out_a(a12_2to12_3), .out_b(b12_2to13_2), .out_c(matrixC12_2)); +processing_element pe12_3(.reset(effective_rst), .clk(clk), .in_a(a12_2to12_3), .in_b(b11_3to12_3), .out_a(a12_3to12_4), .out_b(b12_3to13_3), .out_c(matrixC12_3)); +processing_element pe12_4(.reset(effective_rst), .clk(clk), .in_a(a12_3to12_4), .in_b(b11_4to12_4), .out_a(a12_4to12_5), .out_b(b12_4to13_4), .out_c(matrixC12_4)); +processing_element pe12_5(.reset(effective_rst), .clk(clk), .in_a(a12_4to12_5), .in_b(b11_5to12_5), .out_a(a12_5to12_6), .out_b(b12_5to13_5), .out_c(matrixC12_5)); +processing_element pe12_6(.reset(effective_rst), .clk(clk), .in_a(a12_5to12_6), .in_b(b11_6to12_6), .out_a(a12_6to12_7), .out_b(b12_6to13_6), .out_c(matrixC12_6)); +processing_element pe12_7(.reset(effective_rst), .clk(clk), .in_a(a12_6to12_7), .in_b(b11_7to12_7), .out_a(a12_7to12_8), .out_b(b12_7to13_7), .out_c(matrixC12_7)); +processing_element pe12_8(.reset(effective_rst), .clk(clk), .in_a(a12_7to12_8), .in_b(b11_8to12_8), .out_a(a12_8to12_9), .out_b(b12_8to13_8), .out_c(matrixC12_8)); +processing_element pe12_9(.reset(effective_rst), .clk(clk), .in_a(a12_8to12_9), .in_b(b11_9to12_9), .out_a(a12_9to12_10), .out_b(b12_9to13_9), .out_c(matrixC12_9)); +processing_element pe12_10(.reset(effective_rst), .clk(clk), .in_a(a12_9to12_10), .in_b(b11_10to12_10), .out_a(a12_10to12_11), .out_b(b12_10to13_10), .out_c(matrixC12_10)); +processing_element pe12_11(.reset(effective_rst), .clk(clk), .in_a(a12_10to12_11), .in_b(b11_11to12_11), .out_a(a12_11to12_12), .out_b(b12_11to13_11), .out_c(matrixC12_11)); +processing_element pe12_12(.reset(effective_rst), .clk(clk), .in_a(a12_11to12_12), .in_b(b11_12to12_12), .out_a(a12_12to12_13), .out_b(b12_12to13_12), .out_c(matrixC12_12)); +processing_element pe12_13(.reset(effective_rst), .clk(clk), .in_a(a12_12to12_13), .in_b(b11_13to12_13), .out_a(a12_13to12_14), .out_b(b12_13to13_13), .out_c(matrixC12_13)); +processing_element pe12_14(.reset(effective_rst), .clk(clk), .in_a(a12_13to12_14), .in_b(b11_14to12_14), .out_a(a12_14to12_15), .out_b(b12_14to13_14), .out_c(matrixC12_14)); +processing_element pe12_15(.reset(effective_rst), .clk(clk), .in_a(a12_14to12_15), .in_b(b11_15to12_15), .out_a(a12_15to12_16), .out_b(b12_15to13_15), .out_c(matrixC12_15)); +processing_element pe12_16(.reset(effective_rst), .clk(clk), .in_a(a12_15to12_16), .in_b(b11_16to12_16), .out_a(a12_16to12_17), .out_b(b12_16to13_16), .out_c(matrixC12_16)); +processing_element pe12_17(.reset(effective_rst), .clk(clk), .in_a(a12_16to12_17), .in_b(b11_17to12_17), .out_a(a12_17to12_18), .out_b(b12_17to13_17), .out_c(matrixC12_17)); +processing_element pe12_18(.reset(effective_rst), .clk(clk), .in_a(a12_17to12_18), .in_b(b11_18to12_18), .out_a(a12_18to12_19), .out_b(b12_18to13_18), .out_c(matrixC12_18)); +processing_element pe12_19(.reset(effective_rst), .clk(clk), .in_a(a12_18to12_19), .in_b(b11_19to12_19), .out_a(a12_19to12_20), .out_b(b12_19to13_19), .out_c(matrixC12_19)); +processing_element pe12_20(.reset(effective_rst), .clk(clk), .in_a(a12_19to12_20), .in_b(b11_20to12_20), .out_a(a12_20to12_21), .out_b(b12_20to13_20), .out_c(matrixC12_20)); +processing_element pe12_21(.reset(effective_rst), .clk(clk), .in_a(a12_20to12_21), .in_b(b11_21to12_21), .out_a(a12_21to12_22), .out_b(b12_21to13_21), .out_c(matrixC12_21)); +processing_element pe12_22(.reset(effective_rst), .clk(clk), .in_a(a12_21to12_22), .in_b(b11_22to12_22), .out_a(a12_22to12_23), .out_b(b12_22to13_22), .out_c(matrixC12_22)); +processing_element pe12_23(.reset(effective_rst), .clk(clk), .in_a(a12_22to12_23), .in_b(b11_23to12_23), .out_a(a12_23to12_24), .out_b(b12_23to13_23), .out_c(matrixC12_23)); +processing_element pe12_24(.reset(effective_rst), .clk(clk), .in_a(a12_23to12_24), .in_b(b11_24to12_24), .out_a(a12_24to12_25), .out_b(b12_24to13_24), .out_c(matrixC12_24)); +processing_element pe12_25(.reset(effective_rst), .clk(clk), .in_a(a12_24to12_25), .in_b(b11_25to12_25), .out_a(a12_25to12_26), .out_b(b12_25to13_25), .out_c(matrixC12_25)); +processing_element pe12_26(.reset(effective_rst), .clk(clk), .in_a(a12_25to12_26), .in_b(b11_26to12_26), .out_a(a12_26to12_27), .out_b(b12_26to13_26), .out_c(matrixC12_26)); +processing_element pe12_27(.reset(effective_rst), .clk(clk), .in_a(a12_26to12_27), .in_b(b11_27to12_27), .out_a(a12_27to12_28), .out_b(b12_27to13_27), .out_c(matrixC12_27)); +processing_element pe12_28(.reset(effective_rst), .clk(clk), .in_a(a12_27to12_28), .in_b(b11_28to12_28), .out_a(a12_28to12_29), .out_b(b12_28to13_28), .out_c(matrixC12_28)); +processing_element pe12_29(.reset(effective_rst), .clk(clk), .in_a(a12_28to12_29), .in_b(b11_29to12_29), .out_a(a12_29to12_30), .out_b(b12_29to13_29), .out_c(matrixC12_29)); +processing_element pe12_30(.reset(effective_rst), .clk(clk), .in_a(a12_29to12_30), .in_b(b11_30to12_30), .out_a(a12_30to12_31), .out_b(b12_30to13_30), .out_c(matrixC12_30)); +processing_element pe12_31(.reset(effective_rst), .clk(clk), .in_a(a12_30to12_31), .in_b(b11_31to12_31), .out_a(a12_31to12_32), .out_b(b12_31to13_31), .out_c(matrixC12_31)); +processing_element pe13_1(.reset(effective_rst), .clk(clk), .in_a(a13_0to13_1), .in_b(b12_1to13_1), .out_a(a13_1to13_2), .out_b(b13_1to14_1), .out_c(matrixC13_1)); +processing_element pe13_2(.reset(effective_rst), .clk(clk), .in_a(a13_1to13_2), .in_b(b12_2to13_2), .out_a(a13_2to13_3), .out_b(b13_2to14_2), .out_c(matrixC13_2)); +processing_element pe13_3(.reset(effective_rst), .clk(clk), .in_a(a13_2to13_3), .in_b(b12_3to13_3), .out_a(a13_3to13_4), .out_b(b13_3to14_3), .out_c(matrixC13_3)); +processing_element pe13_4(.reset(effective_rst), .clk(clk), .in_a(a13_3to13_4), .in_b(b12_4to13_4), .out_a(a13_4to13_5), .out_b(b13_4to14_4), .out_c(matrixC13_4)); +processing_element pe13_5(.reset(effective_rst), .clk(clk), .in_a(a13_4to13_5), .in_b(b12_5to13_5), .out_a(a13_5to13_6), .out_b(b13_5to14_5), .out_c(matrixC13_5)); +processing_element pe13_6(.reset(effective_rst), .clk(clk), .in_a(a13_5to13_6), .in_b(b12_6to13_6), .out_a(a13_6to13_7), .out_b(b13_6to14_6), .out_c(matrixC13_6)); +processing_element pe13_7(.reset(effective_rst), .clk(clk), .in_a(a13_6to13_7), .in_b(b12_7to13_7), .out_a(a13_7to13_8), .out_b(b13_7to14_7), .out_c(matrixC13_7)); +processing_element pe13_8(.reset(effective_rst), .clk(clk), .in_a(a13_7to13_8), .in_b(b12_8to13_8), .out_a(a13_8to13_9), .out_b(b13_8to14_8), .out_c(matrixC13_8)); +processing_element pe13_9(.reset(effective_rst), .clk(clk), .in_a(a13_8to13_9), .in_b(b12_9to13_9), .out_a(a13_9to13_10), .out_b(b13_9to14_9), .out_c(matrixC13_9)); +processing_element pe13_10(.reset(effective_rst), .clk(clk), .in_a(a13_9to13_10), .in_b(b12_10to13_10), .out_a(a13_10to13_11), .out_b(b13_10to14_10), .out_c(matrixC13_10)); +processing_element pe13_11(.reset(effective_rst), .clk(clk), .in_a(a13_10to13_11), .in_b(b12_11to13_11), .out_a(a13_11to13_12), .out_b(b13_11to14_11), .out_c(matrixC13_11)); +processing_element pe13_12(.reset(effective_rst), .clk(clk), .in_a(a13_11to13_12), .in_b(b12_12to13_12), .out_a(a13_12to13_13), .out_b(b13_12to14_12), .out_c(matrixC13_12)); +processing_element pe13_13(.reset(effective_rst), .clk(clk), .in_a(a13_12to13_13), .in_b(b12_13to13_13), .out_a(a13_13to13_14), .out_b(b13_13to14_13), .out_c(matrixC13_13)); +processing_element pe13_14(.reset(effective_rst), .clk(clk), .in_a(a13_13to13_14), .in_b(b12_14to13_14), .out_a(a13_14to13_15), .out_b(b13_14to14_14), .out_c(matrixC13_14)); +processing_element pe13_15(.reset(effective_rst), .clk(clk), .in_a(a13_14to13_15), .in_b(b12_15to13_15), .out_a(a13_15to13_16), .out_b(b13_15to14_15), .out_c(matrixC13_15)); +processing_element pe13_16(.reset(effective_rst), .clk(clk), .in_a(a13_15to13_16), .in_b(b12_16to13_16), .out_a(a13_16to13_17), .out_b(b13_16to14_16), .out_c(matrixC13_16)); +processing_element pe13_17(.reset(effective_rst), .clk(clk), .in_a(a13_16to13_17), .in_b(b12_17to13_17), .out_a(a13_17to13_18), .out_b(b13_17to14_17), .out_c(matrixC13_17)); +processing_element pe13_18(.reset(effective_rst), .clk(clk), .in_a(a13_17to13_18), .in_b(b12_18to13_18), .out_a(a13_18to13_19), .out_b(b13_18to14_18), .out_c(matrixC13_18)); +processing_element pe13_19(.reset(effective_rst), .clk(clk), .in_a(a13_18to13_19), .in_b(b12_19to13_19), .out_a(a13_19to13_20), .out_b(b13_19to14_19), .out_c(matrixC13_19)); +processing_element pe13_20(.reset(effective_rst), .clk(clk), .in_a(a13_19to13_20), .in_b(b12_20to13_20), .out_a(a13_20to13_21), .out_b(b13_20to14_20), .out_c(matrixC13_20)); +processing_element pe13_21(.reset(effective_rst), .clk(clk), .in_a(a13_20to13_21), .in_b(b12_21to13_21), .out_a(a13_21to13_22), .out_b(b13_21to14_21), .out_c(matrixC13_21)); +processing_element pe13_22(.reset(effective_rst), .clk(clk), .in_a(a13_21to13_22), .in_b(b12_22to13_22), .out_a(a13_22to13_23), .out_b(b13_22to14_22), .out_c(matrixC13_22)); +processing_element pe13_23(.reset(effective_rst), .clk(clk), .in_a(a13_22to13_23), .in_b(b12_23to13_23), .out_a(a13_23to13_24), .out_b(b13_23to14_23), .out_c(matrixC13_23)); +processing_element pe13_24(.reset(effective_rst), .clk(clk), .in_a(a13_23to13_24), .in_b(b12_24to13_24), .out_a(a13_24to13_25), .out_b(b13_24to14_24), .out_c(matrixC13_24)); +processing_element pe13_25(.reset(effective_rst), .clk(clk), .in_a(a13_24to13_25), .in_b(b12_25to13_25), .out_a(a13_25to13_26), .out_b(b13_25to14_25), .out_c(matrixC13_25)); +processing_element pe13_26(.reset(effective_rst), .clk(clk), .in_a(a13_25to13_26), .in_b(b12_26to13_26), .out_a(a13_26to13_27), .out_b(b13_26to14_26), .out_c(matrixC13_26)); +processing_element pe13_27(.reset(effective_rst), .clk(clk), .in_a(a13_26to13_27), .in_b(b12_27to13_27), .out_a(a13_27to13_28), .out_b(b13_27to14_27), .out_c(matrixC13_27)); +processing_element pe13_28(.reset(effective_rst), .clk(clk), .in_a(a13_27to13_28), .in_b(b12_28to13_28), .out_a(a13_28to13_29), .out_b(b13_28to14_28), .out_c(matrixC13_28)); +processing_element pe13_29(.reset(effective_rst), .clk(clk), .in_a(a13_28to13_29), .in_b(b12_29to13_29), .out_a(a13_29to13_30), .out_b(b13_29to14_29), .out_c(matrixC13_29)); +processing_element pe13_30(.reset(effective_rst), .clk(clk), .in_a(a13_29to13_30), .in_b(b12_30to13_30), .out_a(a13_30to13_31), .out_b(b13_30to14_30), .out_c(matrixC13_30)); +processing_element pe13_31(.reset(effective_rst), .clk(clk), .in_a(a13_30to13_31), .in_b(b12_31to13_31), .out_a(a13_31to13_32), .out_b(b13_31to14_31), .out_c(matrixC13_31)); +processing_element pe14_1(.reset(effective_rst), .clk(clk), .in_a(a14_0to14_1), .in_b(b13_1to14_1), .out_a(a14_1to14_2), .out_b(b14_1to15_1), .out_c(matrixC14_1)); +processing_element pe14_2(.reset(effective_rst), .clk(clk), .in_a(a14_1to14_2), .in_b(b13_2to14_2), .out_a(a14_2to14_3), .out_b(b14_2to15_2), .out_c(matrixC14_2)); +processing_element pe14_3(.reset(effective_rst), .clk(clk), .in_a(a14_2to14_3), .in_b(b13_3to14_3), .out_a(a14_3to14_4), .out_b(b14_3to15_3), .out_c(matrixC14_3)); +processing_element pe14_4(.reset(effective_rst), .clk(clk), .in_a(a14_3to14_4), .in_b(b13_4to14_4), .out_a(a14_4to14_5), .out_b(b14_4to15_4), .out_c(matrixC14_4)); +processing_element pe14_5(.reset(effective_rst), .clk(clk), .in_a(a14_4to14_5), .in_b(b13_5to14_5), .out_a(a14_5to14_6), .out_b(b14_5to15_5), .out_c(matrixC14_5)); +processing_element pe14_6(.reset(effective_rst), .clk(clk), .in_a(a14_5to14_6), .in_b(b13_6to14_6), .out_a(a14_6to14_7), .out_b(b14_6to15_6), .out_c(matrixC14_6)); +processing_element pe14_7(.reset(effective_rst), .clk(clk), .in_a(a14_6to14_7), .in_b(b13_7to14_7), .out_a(a14_7to14_8), .out_b(b14_7to15_7), .out_c(matrixC14_7)); +processing_element pe14_8(.reset(effective_rst), .clk(clk), .in_a(a14_7to14_8), .in_b(b13_8to14_8), .out_a(a14_8to14_9), .out_b(b14_8to15_8), .out_c(matrixC14_8)); +processing_element pe14_9(.reset(effective_rst), .clk(clk), .in_a(a14_8to14_9), .in_b(b13_9to14_9), .out_a(a14_9to14_10), .out_b(b14_9to15_9), .out_c(matrixC14_9)); +processing_element pe14_10(.reset(effective_rst), .clk(clk), .in_a(a14_9to14_10), .in_b(b13_10to14_10), .out_a(a14_10to14_11), .out_b(b14_10to15_10), .out_c(matrixC14_10)); +processing_element pe14_11(.reset(effective_rst), .clk(clk), .in_a(a14_10to14_11), .in_b(b13_11to14_11), .out_a(a14_11to14_12), .out_b(b14_11to15_11), .out_c(matrixC14_11)); +processing_element pe14_12(.reset(effective_rst), .clk(clk), .in_a(a14_11to14_12), .in_b(b13_12to14_12), .out_a(a14_12to14_13), .out_b(b14_12to15_12), .out_c(matrixC14_12)); +processing_element pe14_13(.reset(effective_rst), .clk(clk), .in_a(a14_12to14_13), .in_b(b13_13to14_13), .out_a(a14_13to14_14), .out_b(b14_13to15_13), .out_c(matrixC14_13)); +processing_element pe14_14(.reset(effective_rst), .clk(clk), .in_a(a14_13to14_14), .in_b(b13_14to14_14), .out_a(a14_14to14_15), .out_b(b14_14to15_14), .out_c(matrixC14_14)); +processing_element pe14_15(.reset(effective_rst), .clk(clk), .in_a(a14_14to14_15), .in_b(b13_15to14_15), .out_a(a14_15to14_16), .out_b(b14_15to15_15), .out_c(matrixC14_15)); +processing_element pe14_16(.reset(effective_rst), .clk(clk), .in_a(a14_15to14_16), .in_b(b13_16to14_16), .out_a(a14_16to14_17), .out_b(b14_16to15_16), .out_c(matrixC14_16)); +processing_element pe14_17(.reset(effective_rst), .clk(clk), .in_a(a14_16to14_17), .in_b(b13_17to14_17), .out_a(a14_17to14_18), .out_b(b14_17to15_17), .out_c(matrixC14_17)); +processing_element pe14_18(.reset(effective_rst), .clk(clk), .in_a(a14_17to14_18), .in_b(b13_18to14_18), .out_a(a14_18to14_19), .out_b(b14_18to15_18), .out_c(matrixC14_18)); +processing_element pe14_19(.reset(effective_rst), .clk(clk), .in_a(a14_18to14_19), .in_b(b13_19to14_19), .out_a(a14_19to14_20), .out_b(b14_19to15_19), .out_c(matrixC14_19)); +processing_element pe14_20(.reset(effective_rst), .clk(clk), .in_a(a14_19to14_20), .in_b(b13_20to14_20), .out_a(a14_20to14_21), .out_b(b14_20to15_20), .out_c(matrixC14_20)); +processing_element pe14_21(.reset(effective_rst), .clk(clk), .in_a(a14_20to14_21), .in_b(b13_21to14_21), .out_a(a14_21to14_22), .out_b(b14_21to15_21), .out_c(matrixC14_21)); +processing_element pe14_22(.reset(effective_rst), .clk(clk), .in_a(a14_21to14_22), .in_b(b13_22to14_22), .out_a(a14_22to14_23), .out_b(b14_22to15_22), .out_c(matrixC14_22)); +processing_element pe14_23(.reset(effective_rst), .clk(clk), .in_a(a14_22to14_23), .in_b(b13_23to14_23), .out_a(a14_23to14_24), .out_b(b14_23to15_23), .out_c(matrixC14_23)); +processing_element pe14_24(.reset(effective_rst), .clk(clk), .in_a(a14_23to14_24), .in_b(b13_24to14_24), .out_a(a14_24to14_25), .out_b(b14_24to15_24), .out_c(matrixC14_24)); +processing_element pe14_25(.reset(effective_rst), .clk(clk), .in_a(a14_24to14_25), .in_b(b13_25to14_25), .out_a(a14_25to14_26), .out_b(b14_25to15_25), .out_c(matrixC14_25)); +processing_element pe14_26(.reset(effective_rst), .clk(clk), .in_a(a14_25to14_26), .in_b(b13_26to14_26), .out_a(a14_26to14_27), .out_b(b14_26to15_26), .out_c(matrixC14_26)); +processing_element pe14_27(.reset(effective_rst), .clk(clk), .in_a(a14_26to14_27), .in_b(b13_27to14_27), .out_a(a14_27to14_28), .out_b(b14_27to15_27), .out_c(matrixC14_27)); +processing_element pe14_28(.reset(effective_rst), .clk(clk), .in_a(a14_27to14_28), .in_b(b13_28to14_28), .out_a(a14_28to14_29), .out_b(b14_28to15_28), .out_c(matrixC14_28)); +processing_element pe14_29(.reset(effective_rst), .clk(clk), .in_a(a14_28to14_29), .in_b(b13_29to14_29), .out_a(a14_29to14_30), .out_b(b14_29to15_29), .out_c(matrixC14_29)); +processing_element pe14_30(.reset(effective_rst), .clk(clk), .in_a(a14_29to14_30), .in_b(b13_30to14_30), .out_a(a14_30to14_31), .out_b(b14_30to15_30), .out_c(matrixC14_30)); +processing_element pe14_31(.reset(effective_rst), .clk(clk), .in_a(a14_30to14_31), .in_b(b13_31to14_31), .out_a(a14_31to14_32), .out_b(b14_31to15_31), .out_c(matrixC14_31)); +processing_element pe15_1(.reset(effective_rst), .clk(clk), .in_a(a15_0to15_1), .in_b(b14_1to15_1), .out_a(a15_1to15_2), .out_b(b15_1to16_1), .out_c(matrixC15_1)); +processing_element pe15_2(.reset(effective_rst), .clk(clk), .in_a(a15_1to15_2), .in_b(b14_2to15_2), .out_a(a15_2to15_3), .out_b(b15_2to16_2), .out_c(matrixC15_2)); +processing_element pe15_3(.reset(effective_rst), .clk(clk), .in_a(a15_2to15_3), .in_b(b14_3to15_3), .out_a(a15_3to15_4), .out_b(b15_3to16_3), .out_c(matrixC15_3)); +processing_element pe15_4(.reset(effective_rst), .clk(clk), .in_a(a15_3to15_4), .in_b(b14_4to15_4), .out_a(a15_4to15_5), .out_b(b15_4to16_4), .out_c(matrixC15_4)); +processing_element pe15_5(.reset(effective_rst), .clk(clk), .in_a(a15_4to15_5), .in_b(b14_5to15_5), .out_a(a15_5to15_6), .out_b(b15_5to16_5), .out_c(matrixC15_5)); +processing_element pe15_6(.reset(effective_rst), .clk(clk), .in_a(a15_5to15_6), .in_b(b14_6to15_6), .out_a(a15_6to15_7), .out_b(b15_6to16_6), .out_c(matrixC15_6)); +processing_element pe15_7(.reset(effective_rst), .clk(clk), .in_a(a15_6to15_7), .in_b(b14_7to15_7), .out_a(a15_7to15_8), .out_b(b15_7to16_7), .out_c(matrixC15_7)); +processing_element pe15_8(.reset(effective_rst), .clk(clk), .in_a(a15_7to15_8), .in_b(b14_8to15_8), .out_a(a15_8to15_9), .out_b(b15_8to16_8), .out_c(matrixC15_8)); +processing_element pe15_9(.reset(effective_rst), .clk(clk), .in_a(a15_8to15_9), .in_b(b14_9to15_9), .out_a(a15_9to15_10), .out_b(b15_9to16_9), .out_c(matrixC15_9)); +processing_element pe15_10(.reset(effective_rst), .clk(clk), .in_a(a15_9to15_10), .in_b(b14_10to15_10), .out_a(a15_10to15_11), .out_b(b15_10to16_10), .out_c(matrixC15_10)); +processing_element pe15_11(.reset(effective_rst), .clk(clk), .in_a(a15_10to15_11), .in_b(b14_11to15_11), .out_a(a15_11to15_12), .out_b(b15_11to16_11), .out_c(matrixC15_11)); +processing_element pe15_12(.reset(effective_rst), .clk(clk), .in_a(a15_11to15_12), .in_b(b14_12to15_12), .out_a(a15_12to15_13), .out_b(b15_12to16_12), .out_c(matrixC15_12)); +processing_element pe15_13(.reset(effective_rst), .clk(clk), .in_a(a15_12to15_13), .in_b(b14_13to15_13), .out_a(a15_13to15_14), .out_b(b15_13to16_13), .out_c(matrixC15_13)); +processing_element pe15_14(.reset(effective_rst), .clk(clk), .in_a(a15_13to15_14), .in_b(b14_14to15_14), .out_a(a15_14to15_15), .out_b(b15_14to16_14), .out_c(matrixC15_14)); +processing_element pe15_15(.reset(effective_rst), .clk(clk), .in_a(a15_14to15_15), .in_b(b14_15to15_15), .out_a(a15_15to15_16), .out_b(b15_15to16_15), .out_c(matrixC15_15)); +processing_element pe15_16(.reset(effective_rst), .clk(clk), .in_a(a15_15to15_16), .in_b(b14_16to15_16), .out_a(a15_16to15_17), .out_b(b15_16to16_16), .out_c(matrixC15_16)); +processing_element pe15_17(.reset(effective_rst), .clk(clk), .in_a(a15_16to15_17), .in_b(b14_17to15_17), .out_a(a15_17to15_18), .out_b(b15_17to16_17), .out_c(matrixC15_17)); +processing_element pe15_18(.reset(effective_rst), .clk(clk), .in_a(a15_17to15_18), .in_b(b14_18to15_18), .out_a(a15_18to15_19), .out_b(b15_18to16_18), .out_c(matrixC15_18)); +processing_element pe15_19(.reset(effective_rst), .clk(clk), .in_a(a15_18to15_19), .in_b(b14_19to15_19), .out_a(a15_19to15_20), .out_b(b15_19to16_19), .out_c(matrixC15_19)); +processing_element pe15_20(.reset(effective_rst), .clk(clk), .in_a(a15_19to15_20), .in_b(b14_20to15_20), .out_a(a15_20to15_21), .out_b(b15_20to16_20), .out_c(matrixC15_20)); +processing_element pe15_21(.reset(effective_rst), .clk(clk), .in_a(a15_20to15_21), .in_b(b14_21to15_21), .out_a(a15_21to15_22), .out_b(b15_21to16_21), .out_c(matrixC15_21)); +processing_element pe15_22(.reset(effective_rst), .clk(clk), .in_a(a15_21to15_22), .in_b(b14_22to15_22), .out_a(a15_22to15_23), .out_b(b15_22to16_22), .out_c(matrixC15_22)); +processing_element pe15_23(.reset(effective_rst), .clk(clk), .in_a(a15_22to15_23), .in_b(b14_23to15_23), .out_a(a15_23to15_24), .out_b(b15_23to16_23), .out_c(matrixC15_23)); +processing_element pe15_24(.reset(effective_rst), .clk(clk), .in_a(a15_23to15_24), .in_b(b14_24to15_24), .out_a(a15_24to15_25), .out_b(b15_24to16_24), .out_c(matrixC15_24)); +processing_element pe15_25(.reset(effective_rst), .clk(clk), .in_a(a15_24to15_25), .in_b(b14_25to15_25), .out_a(a15_25to15_26), .out_b(b15_25to16_25), .out_c(matrixC15_25)); +processing_element pe15_26(.reset(effective_rst), .clk(clk), .in_a(a15_25to15_26), .in_b(b14_26to15_26), .out_a(a15_26to15_27), .out_b(b15_26to16_26), .out_c(matrixC15_26)); +processing_element pe15_27(.reset(effective_rst), .clk(clk), .in_a(a15_26to15_27), .in_b(b14_27to15_27), .out_a(a15_27to15_28), .out_b(b15_27to16_27), .out_c(matrixC15_27)); +processing_element pe15_28(.reset(effective_rst), .clk(clk), .in_a(a15_27to15_28), .in_b(b14_28to15_28), .out_a(a15_28to15_29), .out_b(b15_28to16_28), .out_c(matrixC15_28)); +processing_element pe15_29(.reset(effective_rst), .clk(clk), .in_a(a15_28to15_29), .in_b(b14_29to15_29), .out_a(a15_29to15_30), .out_b(b15_29to16_29), .out_c(matrixC15_29)); +processing_element pe15_30(.reset(effective_rst), .clk(clk), .in_a(a15_29to15_30), .in_b(b14_30to15_30), .out_a(a15_30to15_31), .out_b(b15_30to16_30), .out_c(matrixC15_30)); +processing_element pe15_31(.reset(effective_rst), .clk(clk), .in_a(a15_30to15_31), .in_b(b14_31to15_31), .out_a(a15_31to15_32), .out_b(b15_31to16_31), .out_c(matrixC15_31)); +processing_element pe16_1(.reset(effective_rst), .clk(clk), .in_a(a16_0to16_1), .in_b(b15_1to16_1), .out_a(a16_1to16_2), .out_b(b16_1to17_1), .out_c(matrixC16_1)); +processing_element pe16_2(.reset(effective_rst), .clk(clk), .in_a(a16_1to16_2), .in_b(b15_2to16_2), .out_a(a16_2to16_3), .out_b(b16_2to17_2), .out_c(matrixC16_2)); +processing_element pe16_3(.reset(effective_rst), .clk(clk), .in_a(a16_2to16_3), .in_b(b15_3to16_3), .out_a(a16_3to16_4), .out_b(b16_3to17_3), .out_c(matrixC16_3)); +processing_element pe16_4(.reset(effective_rst), .clk(clk), .in_a(a16_3to16_4), .in_b(b15_4to16_4), .out_a(a16_4to16_5), .out_b(b16_4to17_4), .out_c(matrixC16_4)); +processing_element pe16_5(.reset(effective_rst), .clk(clk), .in_a(a16_4to16_5), .in_b(b15_5to16_5), .out_a(a16_5to16_6), .out_b(b16_5to17_5), .out_c(matrixC16_5)); +processing_element pe16_6(.reset(effective_rst), .clk(clk), .in_a(a16_5to16_6), .in_b(b15_6to16_6), .out_a(a16_6to16_7), .out_b(b16_6to17_6), .out_c(matrixC16_6)); +processing_element pe16_7(.reset(effective_rst), .clk(clk), .in_a(a16_6to16_7), .in_b(b15_7to16_7), .out_a(a16_7to16_8), .out_b(b16_7to17_7), .out_c(matrixC16_7)); +processing_element pe16_8(.reset(effective_rst), .clk(clk), .in_a(a16_7to16_8), .in_b(b15_8to16_8), .out_a(a16_8to16_9), .out_b(b16_8to17_8), .out_c(matrixC16_8)); +processing_element pe16_9(.reset(effective_rst), .clk(clk), .in_a(a16_8to16_9), .in_b(b15_9to16_9), .out_a(a16_9to16_10), .out_b(b16_9to17_9), .out_c(matrixC16_9)); +processing_element pe16_10(.reset(effective_rst), .clk(clk), .in_a(a16_9to16_10), .in_b(b15_10to16_10), .out_a(a16_10to16_11), .out_b(b16_10to17_10), .out_c(matrixC16_10)); +processing_element pe16_11(.reset(effective_rst), .clk(clk), .in_a(a16_10to16_11), .in_b(b15_11to16_11), .out_a(a16_11to16_12), .out_b(b16_11to17_11), .out_c(matrixC16_11)); +processing_element pe16_12(.reset(effective_rst), .clk(clk), .in_a(a16_11to16_12), .in_b(b15_12to16_12), .out_a(a16_12to16_13), .out_b(b16_12to17_12), .out_c(matrixC16_12)); +processing_element pe16_13(.reset(effective_rst), .clk(clk), .in_a(a16_12to16_13), .in_b(b15_13to16_13), .out_a(a16_13to16_14), .out_b(b16_13to17_13), .out_c(matrixC16_13)); +processing_element pe16_14(.reset(effective_rst), .clk(clk), .in_a(a16_13to16_14), .in_b(b15_14to16_14), .out_a(a16_14to16_15), .out_b(b16_14to17_14), .out_c(matrixC16_14)); +processing_element pe16_15(.reset(effective_rst), .clk(clk), .in_a(a16_14to16_15), .in_b(b15_15to16_15), .out_a(a16_15to16_16), .out_b(b16_15to17_15), .out_c(matrixC16_15)); +processing_element pe16_16(.reset(effective_rst), .clk(clk), .in_a(a16_15to16_16), .in_b(b15_16to16_16), .out_a(a16_16to16_17), .out_b(b16_16to17_16), .out_c(matrixC16_16)); +processing_element pe16_17(.reset(effective_rst), .clk(clk), .in_a(a16_16to16_17), .in_b(b15_17to16_17), .out_a(a16_17to16_18), .out_b(b16_17to17_17), .out_c(matrixC16_17)); +processing_element pe16_18(.reset(effective_rst), .clk(clk), .in_a(a16_17to16_18), .in_b(b15_18to16_18), .out_a(a16_18to16_19), .out_b(b16_18to17_18), .out_c(matrixC16_18)); +processing_element pe16_19(.reset(effective_rst), .clk(clk), .in_a(a16_18to16_19), .in_b(b15_19to16_19), .out_a(a16_19to16_20), .out_b(b16_19to17_19), .out_c(matrixC16_19)); +processing_element pe16_20(.reset(effective_rst), .clk(clk), .in_a(a16_19to16_20), .in_b(b15_20to16_20), .out_a(a16_20to16_21), .out_b(b16_20to17_20), .out_c(matrixC16_20)); +processing_element pe16_21(.reset(effective_rst), .clk(clk), .in_a(a16_20to16_21), .in_b(b15_21to16_21), .out_a(a16_21to16_22), .out_b(b16_21to17_21), .out_c(matrixC16_21)); +processing_element pe16_22(.reset(effective_rst), .clk(clk), .in_a(a16_21to16_22), .in_b(b15_22to16_22), .out_a(a16_22to16_23), .out_b(b16_22to17_22), .out_c(matrixC16_22)); +processing_element pe16_23(.reset(effective_rst), .clk(clk), .in_a(a16_22to16_23), .in_b(b15_23to16_23), .out_a(a16_23to16_24), .out_b(b16_23to17_23), .out_c(matrixC16_23)); +processing_element pe16_24(.reset(effective_rst), .clk(clk), .in_a(a16_23to16_24), .in_b(b15_24to16_24), .out_a(a16_24to16_25), .out_b(b16_24to17_24), .out_c(matrixC16_24)); +processing_element pe16_25(.reset(effective_rst), .clk(clk), .in_a(a16_24to16_25), .in_b(b15_25to16_25), .out_a(a16_25to16_26), .out_b(b16_25to17_25), .out_c(matrixC16_25)); +processing_element pe16_26(.reset(effective_rst), .clk(clk), .in_a(a16_25to16_26), .in_b(b15_26to16_26), .out_a(a16_26to16_27), .out_b(b16_26to17_26), .out_c(matrixC16_26)); +processing_element pe16_27(.reset(effective_rst), .clk(clk), .in_a(a16_26to16_27), .in_b(b15_27to16_27), .out_a(a16_27to16_28), .out_b(b16_27to17_27), .out_c(matrixC16_27)); +processing_element pe16_28(.reset(effective_rst), .clk(clk), .in_a(a16_27to16_28), .in_b(b15_28to16_28), .out_a(a16_28to16_29), .out_b(b16_28to17_28), .out_c(matrixC16_28)); +processing_element pe16_29(.reset(effective_rst), .clk(clk), .in_a(a16_28to16_29), .in_b(b15_29to16_29), .out_a(a16_29to16_30), .out_b(b16_29to17_29), .out_c(matrixC16_29)); +processing_element pe16_30(.reset(effective_rst), .clk(clk), .in_a(a16_29to16_30), .in_b(b15_30to16_30), .out_a(a16_30to16_31), .out_b(b16_30to17_30), .out_c(matrixC16_30)); +processing_element pe16_31(.reset(effective_rst), .clk(clk), .in_a(a16_30to16_31), .in_b(b15_31to16_31), .out_a(a16_31to16_32), .out_b(b16_31to17_31), .out_c(matrixC16_31)); +processing_element pe17_1(.reset(effective_rst), .clk(clk), .in_a(a17_0to17_1), .in_b(b16_1to17_1), .out_a(a17_1to17_2), .out_b(b17_1to18_1), .out_c(matrixC17_1)); +processing_element pe17_2(.reset(effective_rst), .clk(clk), .in_a(a17_1to17_2), .in_b(b16_2to17_2), .out_a(a17_2to17_3), .out_b(b17_2to18_2), .out_c(matrixC17_2)); +processing_element pe17_3(.reset(effective_rst), .clk(clk), .in_a(a17_2to17_3), .in_b(b16_3to17_3), .out_a(a17_3to17_4), .out_b(b17_3to18_3), .out_c(matrixC17_3)); +processing_element pe17_4(.reset(effective_rst), .clk(clk), .in_a(a17_3to17_4), .in_b(b16_4to17_4), .out_a(a17_4to17_5), .out_b(b17_4to18_4), .out_c(matrixC17_4)); +processing_element pe17_5(.reset(effective_rst), .clk(clk), .in_a(a17_4to17_5), .in_b(b16_5to17_5), .out_a(a17_5to17_6), .out_b(b17_5to18_5), .out_c(matrixC17_5)); +processing_element pe17_6(.reset(effective_rst), .clk(clk), .in_a(a17_5to17_6), .in_b(b16_6to17_6), .out_a(a17_6to17_7), .out_b(b17_6to18_6), .out_c(matrixC17_6)); +processing_element pe17_7(.reset(effective_rst), .clk(clk), .in_a(a17_6to17_7), .in_b(b16_7to17_7), .out_a(a17_7to17_8), .out_b(b17_7to18_7), .out_c(matrixC17_7)); +processing_element pe17_8(.reset(effective_rst), .clk(clk), .in_a(a17_7to17_8), .in_b(b16_8to17_8), .out_a(a17_8to17_9), .out_b(b17_8to18_8), .out_c(matrixC17_8)); +processing_element pe17_9(.reset(effective_rst), .clk(clk), .in_a(a17_8to17_9), .in_b(b16_9to17_9), .out_a(a17_9to17_10), .out_b(b17_9to18_9), .out_c(matrixC17_9)); +processing_element pe17_10(.reset(effective_rst), .clk(clk), .in_a(a17_9to17_10), .in_b(b16_10to17_10), .out_a(a17_10to17_11), .out_b(b17_10to18_10), .out_c(matrixC17_10)); +processing_element pe17_11(.reset(effective_rst), .clk(clk), .in_a(a17_10to17_11), .in_b(b16_11to17_11), .out_a(a17_11to17_12), .out_b(b17_11to18_11), .out_c(matrixC17_11)); +processing_element pe17_12(.reset(effective_rst), .clk(clk), .in_a(a17_11to17_12), .in_b(b16_12to17_12), .out_a(a17_12to17_13), .out_b(b17_12to18_12), .out_c(matrixC17_12)); +processing_element pe17_13(.reset(effective_rst), .clk(clk), .in_a(a17_12to17_13), .in_b(b16_13to17_13), .out_a(a17_13to17_14), .out_b(b17_13to18_13), .out_c(matrixC17_13)); +processing_element pe17_14(.reset(effective_rst), .clk(clk), .in_a(a17_13to17_14), .in_b(b16_14to17_14), .out_a(a17_14to17_15), .out_b(b17_14to18_14), .out_c(matrixC17_14)); +processing_element pe17_15(.reset(effective_rst), .clk(clk), .in_a(a17_14to17_15), .in_b(b16_15to17_15), .out_a(a17_15to17_16), .out_b(b17_15to18_15), .out_c(matrixC17_15)); +processing_element pe17_16(.reset(effective_rst), .clk(clk), .in_a(a17_15to17_16), .in_b(b16_16to17_16), .out_a(a17_16to17_17), .out_b(b17_16to18_16), .out_c(matrixC17_16)); +processing_element pe17_17(.reset(effective_rst), .clk(clk), .in_a(a17_16to17_17), .in_b(b16_17to17_17), .out_a(a17_17to17_18), .out_b(b17_17to18_17), .out_c(matrixC17_17)); +processing_element pe17_18(.reset(effective_rst), .clk(clk), .in_a(a17_17to17_18), .in_b(b16_18to17_18), .out_a(a17_18to17_19), .out_b(b17_18to18_18), .out_c(matrixC17_18)); +processing_element pe17_19(.reset(effective_rst), .clk(clk), .in_a(a17_18to17_19), .in_b(b16_19to17_19), .out_a(a17_19to17_20), .out_b(b17_19to18_19), .out_c(matrixC17_19)); +processing_element pe17_20(.reset(effective_rst), .clk(clk), .in_a(a17_19to17_20), .in_b(b16_20to17_20), .out_a(a17_20to17_21), .out_b(b17_20to18_20), .out_c(matrixC17_20)); +processing_element pe17_21(.reset(effective_rst), .clk(clk), .in_a(a17_20to17_21), .in_b(b16_21to17_21), .out_a(a17_21to17_22), .out_b(b17_21to18_21), .out_c(matrixC17_21)); +processing_element pe17_22(.reset(effective_rst), .clk(clk), .in_a(a17_21to17_22), .in_b(b16_22to17_22), .out_a(a17_22to17_23), .out_b(b17_22to18_22), .out_c(matrixC17_22)); +processing_element pe17_23(.reset(effective_rst), .clk(clk), .in_a(a17_22to17_23), .in_b(b16_23to17_23), .out_a(a17_23to17_24), .out_b(b17_23to18_23), .out_c(matrixC17_23)); +processing_element pe17_24(.reset(effective_rst), .clk(clk), .in_a(a17_23to17_24), .in_b(b16_24to17_24), .out_a(a17_24to17_25), .out_b(b17_24to18_24), .out_c(matrixC17_24)); +processing_element pe17_25(.reset(effective_rst), .clk(clk), .in_a(a17_24to17_25), .in_b(b16_25to17_25), .out_a(a17_25to17_26), .out_b(b17_25to18_25), .out_c(matrixC17_25)); +processing_element pe17_26(.reset(effective_rst), .clk(clk), .in_a(a17_25to17_26), .in_b(b16_26to17_26), .out_a(a17_26to17_27), .out_b(b17_26to18_26), .out_c(matrixC17_26)); +processing_element pe17_27(.reset(effective_rst), .clk(clk), .in_a(a17_26to17_27), .in_b(b16_27to17_27), .out_a(a17_27to17_28), .out_b(b17_27to18_27), .out_c(matrixC17_27)); +processing_element pe17_28(.reset(effective_rst), .clk(clk), .in_a(a17_27to17_28), .in_b(b16_28to17_28), .out_a(a17_28to17_29), .out_b(b17_28to18_28), .out_c(matrixC17_28)); +processing_element pe17_29(.reset(effective_rst), .clk(clk), .in_a(a17_28to17_29), .in_b(b16_29to17_29), .out_a(a17_29to17_30), .out_b(b17_29to18_29), .out_c(matrixC17_29)); +processing_element pe17_30(.reset(effective_rst), .clk(clk), .in_a(a17_29to17_30), .in_b(b16_30to17_30), .out_a(a17_30to17_31), .out_b(b17_30to18_30), .out_c(matrixC17_30)); +processing_element pe17_31(.reset(effective_rst), .clk(clk), .in_a(a17_30to17_31), .in_b(b16_31to17_31), .out_a(a17_31to17_32), .out_b(b17_31to18_31), .out_c(matrixC17_31)); +processing_element pe18_1(.reset(effective_rst), .clk(clk), .in_a(a18_0to18_1), .in_b(b17_1to18_1), .out_a(a18_1to18_2), .out_b(b18_1to19_1), .out_c(matrixC18_1)); +processing_element pe18_2(.reset(effective_rst), .clk(clk), .in_a(a18_1to18_2), .in_b(b17_2to18_2), .out_a(a18_2to18_3), .out_b(b18_2to19_2), .out_c(matrixC18_2)); +processing_element pe18_3(.reset(effective_rst), .clk(clk), .in_a(a18_2to18_3), .in_b(b17_3to18_3), .out_a(a18_3to18_4), .out_b(b18_3to19_3), .out_c(matrixC18_3)); +processing_element pe18_4(.reset(effective_rst), .clk(clk), .in_a(a18_3to18_4), .in_b(b17_4to18_4), .out_a(a18_4to18_5), .out_b(b18_4to19_4), .out_c(matrixC18_4)); +processing_element pe18_5(.reset(effective_rst), .clk(clk), .in_a(a18_4to18_5), .in_b(b17_5to18_5), .out_a(a18_5to18_6), .out_b(b18_5to19_5), .out_c(matrixC18_5)); +processing_element pe18_6(.reset(effective_rst), .clk(clk), .in_a(a18_5to18_6), .in_b(b17_6to18_6), .out_a(a18_6to18_7), .out_b(b18_6to19_6), .out_c(matrixC18_6)); +processing_element pe18_7(.reset(effective_rst), .clk(clk), .in_a(a18_6to18_7), .in_b(b17_7to18_7), .out_a(a18_7to18_8), .out_b(b18_7to19_7), .out_c(matrixC18_7)); +processing_element pe18_8(.reset(effective_rst), .clk(clk), .in_a(a18_7to18_8), .in_b(b17_8to18_8), .out_a(a18_8to18_9), .out_b(b18_8to19_8), .out_c(matrixC18_8)); +processing_element pe18_9(.reset(effective_rst), .clk(clk), .in_a(a18_8to18_9), .in_b(b17_9to18_9), .out_a(a18_9to18_10), .out_b(b18_9to19_9), .out_c(matrixC18_9)); +processing_element pe18_10(.reset(effective_rst), .clk(clk), .in_a(a18_9to18_10), .in_b(b17_10to18_10), .out_a(a18_10to18_11), .out_b(b18_10to19_10), .out_c(matrixC18_10)); +processing_element pe18_11(.reset(effective_rst), .clk(clk), .in_a(a18_10to18_11), .in_b(b17_11to18_11), .out_a(a18_11to18_12), .out_b(b18_11to19_11), .out_c(matrixC18_11)); +processing_element pe18_12(.reset(effective_rst), .clk(clk), .in_a(a18_11to18_12), .in_b(b17_12to18_12), .out_a(a18_12to18_13), .out_b(b18_12to19_12), .out_c(matrixC18_12)); +processing_element pe18_13(.reset(effective_rst), .clk(clk), .in_a(a18_12to18_13), .in_b(b17_13to18_13), .out_a(a18_13to18_14), .out_b(b18_13to19_13), .out_c(matrixC18_13)); +processing_element pe18_14(.reset(effective_rst), .clk(clk), .in_a(a18_13to18_14), .in_b(b17_14to18_14), .out_a(a18_14to18_15), .out_b(b18_14to19_14), .out_c(matrixC18_14)); +processing_element pe18_15(.reset(effective_rst), .clk(clk), .in_a(a18_14to18_15), .in_b(b17_15to18_15), .out_a(a18_15to18_16), .out_b(b18_15to19_15), .out_c(matrixC18_15)); +processing_element pe18_16(.reset(effective_rst), .clk(clk), .in_a(a18_15to18_16), .in_b(b17_16to18_16), .out_a(a18_16to18_17), .out_b(b18_16to19_16), .out_c(matrixC18_16)); +processing_element pe18_17(.reset(effective_rst), .clk(clk), .in_a(a18_16to18_17), .in_b(b17_17to18_17), .out_a(a18_17to18_18), .out_b(b18_17to19_17), .out_c(matrixC18_17)); +processing_element pe18_18(.reset(effective_rst), .clk(clk), .in_a(a18_17to18_18), .in_b(b17_18to18_18), .out_a(a18_18to18_19), .out_b(b18_18to19_18), .out_c(matrixC18_18)); +processing_element pe18_19(.reset(effective_rst), .clk(clk), .in_a(a18_18to18_19), .in_b(b17_19to18_19), .out_a(a18_19to18_20), .out_b(b18_19to19_19), .out_c(matrixC18_19)); +processing_element pe18_20(.reset(effective_rst), .clk(clk), .in_a(a18_19to18_20), .in_b(b17_20to18_20), .out_a(a18_20to18_21), .out_b(b18_20to19_20), .out_c(matrixC18_20)); +processing_element pe18_21(.reset(effective_rst), .clk(clk), .in_a(a18_20to18_21), .in_b(b17_21to18_21), .out_a(a18_21to18_22), .out_b(b18_21to19_21), .out_c(matrixC18_21)); +processing_element pe18_22(.reset(effective_rst), .clk(clk), .in_a(a18_21to18_22), .in_b(b17_22to18_22), .out_a(a18_22to18_23), .out_b(b18_22to19_22), .out_c(matrixC18_22)); +processing_element pe18_23(.reset(effective_rst), .clk(clk), .in_a(a18_22to18_23), .in_b(b17_23to18_23), .out_a(a18_23to18_24), .out_b(b18_23to19_23), .out_c(matrixC18_23)); +processing_element pe18_24(.reset(effective_rst), .clk(clk), .in_a(a18_23to18_24), .in_b(b17_24to18_24), .out_a(a18_24to18_25), .out_b(b18_24to19_24), .out_c(matrixC18_24)); +processing_element pe18_25(.reset(effective_rst), .clk(clk), .in_a(a18_24to18_25), .in_b(b17_25to18_25), .out_a(a18_25to18_26), .out_b(b18_25to19_25), .out_c(matrixC18_25)); +processing_element pe18_26(.reset(effective_rst), .clk(clk), .in_a(a18_25to18_26), .in_b(b17_26to18_26), .out_a(a18_26to18_27), .out_b(b18_26to19_26), .out_c(matrixC18_26)); +processing_element pe18_27(.reset(effective_rst), .clk(clk), .in_a(a18_26to18_27), .in_b(b17_27to18_27), .out_a(a18_27to18_28), .out_b(b18_27to19_27), .out_c(matrixC18_27)); +processing_element pe18_28(.reset(effective_rst), .clk(clk), .in_a(a18_27to18_28), .in_b(b17_28to18_28), .out_a(a18_28to18_29), .out_b(b18_28to19_28), .out_c(matrixC18_28)); +processing_element pe18_29(.reset(effective_rst), .clk(clk), .in_a(a18_28to18_29), .in_b(b17_29to18_29), .out_a(a18_29to18_30), .out_b(b18_29to19_29), .out_c(matrixC18_29)); +processing_element pe18_30(.reset(effective_rst), .clk(clk), .in_a(a18_29to18_30), .in_b(b17_30to18_30), .out_a(a18_30to18_31), .out_b(b18_30to19_30), .out_c(matrixC18_30)); +processing_element pe18_31(.reset(effective_rst), .clk(clk), .in_a(a18_30to18_31), .in_b(b17_31to18_31), .out_a(a18_31to18_32), .out_b(b18_31to19_31), .out_c(matrixC18_31)); +processing_element pe19_1(.reset(effective_rst), .clk(clk), .in_a(a19_0to19_1), .in_b(b18_1to19_1), .out_a(a19_1to19_2), .out_b(b19_1to20_1), .out_c(matrixC19_1)); +processing_element pe19_2(.reset(effective_rst), .clk(clk), .in_a(a19_1to19_2), .in_b(b18_2to19_2), .out_a(a19_2to19_3), .out_b(b19_2to20_2), .out_c(matrixC19_2)); +processing_element pe19_3(.reset(effective_rst), .clk(clk), .in_a(a19_2to19_3), .in_b(b18_3to19_3), .out_a(a19_3to19_4), .out_b(b19_3to20_3), .out_c(matrixC19_3)); +processing_element pe19_4(.reset(effective_rst), .clk(clk), .in_a(a19_3to19_4), .in_b(b18_4to19_4), .out_a(a19_4to19_5), .out_b(b19_4to20_4), .out_c(matrixC19_4)); +processing_element pe19_5(.reset(effective_rst), .clk(clk), .in_a(a19_4to19_5), .in_b(b18_5to19_5), .out_a(a19_5to19_6), .out_b(b19_5to20_5), .out_c(matrixC19_5)); +processing_element pe19_6(.reset(effective_rst), .clk(clk), .in_a(a19_5to19_6), .in_b(b18_6to19_6), .out_a(a19_6to19_7), .out_b(b19_6to20_6), .out_c(matrixC19_6)); +processing_element pe19_7(.reset(effective_rst), .clk(clk), .in_a(a19_6to19_7), .in_b(b18_7to19_7), .out_a(a19_7to19_8), .out_b(b19_7to20_7), .out_c(matrixC19_7)); +processing_element pe19_8(.reset(effective_rst), .clk(clk), .in_a(a19_7to19_8), .in_b(b18_8to19_8), .out_a(a19_8to19_9), .out_b(b19_8to20_8), .out_c(matrixC19_8)); +processing_element pe19_9(.reset(effective_rst), .clk(clk), .in_a(a19_8to19_9), .in_b(b18_9to19_9), .out_a(a19_9to19_10), .out_b(b19_9to20_9), .out_c(matrixC19_9)); +processing_element pe19_10(.reset(effective_rst), .clk(clk), .in_a(a19_9to19_10), .in_b(b18_10to19_10), .out_a(a19_10to19_11), .out_b(b19_10to20_10), .out_c(matrixC19_10)); +processing_element pe19_11(.reset(effective_rst), .clk(clk), .in_a(a19_10to19_11), .in_b(b18_11to19_11), .out_a(a19_11to19_12), .out_b(b19_11to20_11), .out_c(matrixC19_11)); +processing_element pe19_12(.reset(effective_rst), .clk(clk), .in_a(a19_11to19_12), .in_b(b18_12to19_12), .out_a(a19_12to19_13), .out_b(b19_12to20_12), .out_c(matrixC19_12)); +processing_element pe19_13(.reset(effective_rst), .clk(clk), .in_a(a19_12to19_13), .in_b(b18_13to19_13), .out_a(a19_13to19_14), .out_b(b19_13to20_13), .out_c(matrixC19_13)); +processing_element pe19_14(.reset(effective_rst), .clk(clk), .in_a(a19_13to19_14), .in_b(b18_14to19_14), .out_a(a19_14to19_15), .out_b(b19_14to20_14), .out_c(matrixC19_14)); +processing_element pe19_15(.reset(effective_rst), .clk(clk), .in_a(a19_14to19_15), .in_b(b18_15to19_15), .out_a(a19_15to19_16), .out_b(b19_15to20_15), .out_c(matrixC19_15)); +processing_element pe19_16(.reset(effective_rst), .clk(clk), .in_a(a19_15to19_16), .in_b(b18_16to19_16), .out_a(a19_16to19_17), .out_b(b19_16to20_16), .out_c(matrixC19_16)); +processing_element pe19_17(.reset(effective_rst), .clk(clk), .in_a(a19_16to19_17), .in_b(b18_17to19_17), .out_a(a19_17to19_18), .out_b(b19_17to20_17), .out_c(matrixC19_17)); +processing_element pe19_18(.reset(effective_rst), .clk(clk), .in_a(a19_17to19_18), .in_b(b18_18to19_18), .out_a(a19_18to19_19), .out_b(b19_18to20_18), .out_c(matrixC19_18)); +processing_element pe19_19(.reset(effective_rst), .clk(clk), .in_a(a19_18to19_19), .in_b(b18_19to19_19), .out_a(a19_19to19_20), .out_b(b19_19to20_19), .out_c(matrixC19_19)); +processing_element pe19_20(.reset(effective_rst), .clk(clk), .in_a(a19_19to19_20), .in_b(b18_20to19_20), .out_a(a19_20to19_21), .out_b(b19_20to20_20), .out_c(matrixC19_20)); +processing_element pe19_21(.reset(effective_rst), .clk(clk), .in_a(a19_20to19_21), .in_b(b18_21to19_21), .out_a(a19_21to19_22), .out_b(b19_21to20_21), .out_c(matrixC19_21)); +processing_element pe19_22(.reset(effective_rst), .clk(clk), .in_a(a19_21to19_22), .in_b(b18_22to19_22), .out_a(a19_22to19_23), .out_b(b19_22to20_22), .out_c(matrixC19_22)); +processing_element pe19_23(.reset(effective_rst), .clk(clk), .in_a(a19_22to19_23), .in_b(b18_23to19_23), .out_a(a19_23to19_24), .out_b(b19_23to20_23), .out_c(matrixC19_23)); +processing_element pe19_24(.reset(effective_rst), .clk(clk), .in_a(a19_23to19_24), .in_b(b18_24to19_24), .out_a(a19_24to19_25), .out_b(b19_24to20_24), .out_c(matrixC19_24)); +processing_element pe19_25(.reset(effective_rst), .clk(clk), .in_a(a19_24to19_25), .in_b(b18_25to19_25), .out_a(a19_25to19_26), .out_b(b19_25to20_25), .out_c(matrixC19_25)); +processing_element pe19_26(.reset(effective_rst), .clk(clk), .in_a(a19_25to19_26), .in_b(b18_26to19_26), .out_a(a19_26to19_27), .out_b(b19_26to20_26), .out_c(matrixC19_26)); +processing_element pe19_27(.reset(effective_rst), .clk(clk), .in_a(a19_26to19_27), .in_b(b18_27to19_27), .out_a(a19_27to19_28), .out_b(b19_27to20_27), .out_c(matrixC19_27)); +processing_element pe19_28(.reset(effective_rst), .clk(clk), .in_a(a19_27to19_28), .in_b(b18_28to19_28), .out_a(a19_28to19_29), .out_b(b19_28to20_28), .out_c(matrixC19_28)); +processing_element pe19_29(.reset(effective_rst), .clk(clk), .in_a(a19_28to19_29), .in_b(b18_29to19_29), .out_a(a19_29to19_30), .out_b(b19_29to20_29), .out_c(matrixC19_29)); +processing_element pe19_30(.reset(effective_rst), .clk(clk), .in_a(a19_29to19_30), .in_b(b18_30to19_30), .out_a(a19_30to19_31), .out_b(b19_30to20_30), .out_c(matrixC19_30)); +processing_element pe19_31(.reset(effective_rst), .clk(clk), .in_a(a19_30to19_31), .in_b(b18_31to19_31), .out_a(a19_31to19_32), .out_b(b19_31to20_31), .out_c(matrixC19_31)); +processing_element pe20_1(.reset(effective_rst), .clk(clk), .in_a(a20_0to20_1), .in_b(b19_1to20_1), .out_a(a20_1to20_2), .out_b(b20_1to21_1), .out_c(matrixC20_1)); +processing_element pe20_2(.reset(effective_rst), .clk(clk), .in_a(a20_1to20_2), .in_b(b19_2to20_2), .out_a(a20_2to20_3), .out_b(b20_2to21_2), .out_c(matrixC20_2)); +processing_element pe20_3(.reset(effective_rst), .clk(clk), .in_a(a20_2to20_3), .in_b(b19_3to20_3), .out_a(a20_3to20_4), .out_b(b20_3to21_3), .out_c(matrixC20_3)); +processing_element pe20_4(.reset(effective_rst), .clk(clk), .in_a(a20_3to20_4), .in_b(b19_4to20_4), .out_a(a20_4to20_5), .out_b(b20_4to21_4), .out_c(matrixC20_4)); +processing_element pe20_5(.reset(effective_rst), .clk(clk), .in_a(a20_4to20_5), .in_b(b19_5to20_5), .out_a(a20_5to20_6), .out_b(b20_5to21_5), .out_c(matrixC20_5)); +processing_element pe20_6(.reset(effective_rst), .clk(clk), .in_a(a20_5to20_6), .in_b(b19_6to20_6), .out_a(a20_6to20_7), .out_b(b20_6to21_6), .out_c(matrixC20_6)); +processing_element pe20_7(.reset(effective_rst), .clk(clk), .in_a(a20_6to20_7), .in_b(b19_7to20_7), .out_a(a20_7to20_8), .out_b(b20_7to21_7), .out_c(matrixC20_7)); +processing_element pe20_8(.reset(effective_rst), .clk(clk), .in_a(a20_7to20_8), .in_b(b19_8to20_8), .out_a(a20_8to20_9), .out_b(b20_8to21_8), .out_c(matrixC20_8)); +processing_element pe20_9(.reset(effective_rst), .clk(clk), .in_a(a20_8to20_9), .in_b(b19_9to20_9), .out_a(a20_9to20_10), .out_b(b20_9to21_9), .out_c(matrixC20_9)); +processing_element pe20_10(.reset(effective_rst), .clk(clk), .in_a(a20_9to20_10), .in_b(b19_10to20_10), .out_a(a20_10to20_11), .out_b(b20_10to21_10), .out_c(matrixC20_10)); +processing_element pe20_11(.reset(effective_rst), .clk(clk), .in_a(a20_10to20_11), .in_b(b19_11to20_11), .out_a(a20_11to20_12), .out_b(b20_11to21_11), .out_c(matrixC20_11)); +processing_element pe20_12(.reset(effective_rst), .clk(clk), .in_a(a20_11to20_12), .in_b(b19_12to20_12), .out_a(a20_12to20_13), .out_b(b20_12to21_12), .out_c(matrixC20_12)); +processing_element pe20_13(.reset(effective_rst), .clk(clk), .in_a(a20_12to20_13), .in_b(b19_13to20_13), .out_a(a20_13to20_14), .out_b(b20_13to21_13), .out_c(matrixC20_13)); +processing_element pe20_14(.reset(effective_rst), .clk(clk), .in_a(a20_13to20_14), .in_b(b19_14to20_14), .out_a(a20_14to20_15), .out_b(b20_14to21_14), .out_c(matrixC20_14)); +processing_element pe20_15(.reset(effective_rst), .clk(clk), .in_a(a20_14to20_15), .in_b(b19_15to20_15), .out_a(a20_15to20_16), .out_b(b20_15to21_15), .out_c(matrixC20_15)); +processing_element pe20_16(.reset(effective_rst), .clk(clk), .in_a(a20_15to20_16), .in_b(b19_16to20_16), .out_a(a20_16to20_17), .out_b(b20_16to21_16), .out_c(matrixC20_16)); +processing_element pe20_17(.reset(effective_rst), .clk(clk), .in_a(a20_16to20_17), .in_b(b19_17to20_17), .out_a(a20_17to20_18), .out_b(b20_17to21_17), .out_c(matrixC20_17)); +processing_element pe20_18(.reset(effective_rst), .clk(clk), .in_a(a20_17to20_18), .in_b(b19_18to20_18), .out_a(a20_18to20_19), .out_b(b20_18to21_18), .out_c(matrixC20_18)); +processing_element pe20_19(.reset(effective_rst), .clk(clk), .in_a(a20_18to20_19), .in_b(b19_19to20_19), .out_a(a20_19to20_20), .out_b(b20_19to21_19), .out_c(matrixC20_19)); +processing_element pe20_20(.reset(effective_rst), .clk(clk), .in_a(a20_19to20_20), .in_b(b19_20to20_20), .out_a(a20_20to20_21), .out_b(b20_20to21_20), .out_c(matrixC20_20)); +processing_element pe20_21(.reset(effective_rst), .clk(clk), .in_a(a20_20to20_21), .in_b(b19_21to20_21), .out_a(a20_21to20_22), .out_b(b20_21to21_21), .out_c(matrixC20_21)); +processing_element pe20_22(.reset(effective_rst), .clk(clk), .in_a(a20_21to20_22), .in_b(b19_22to20_22), .out_a(a20_22to20_23), .out_b(b20_22to21_22), .out_c(matrixC20_22)); +processing_element pe20_23(.reset(effective_rst), .clk(clk), .in_a(a20_22to20_23), .in_b(b19_23to20_23), .out_a(a20_23to20_24), .out_b(b20_23to21_23), .out_c(matrixC20_23)); +processing_element pe20_24(.reset(effective_rst), .clk(clk), .in_a(a20_23to20_24), .in_b(b19_24to20_24), .out_a(a20_24to20_25), .out_b(b20_24to21_24), .out_c(matrixC20_24)); +processing_element pe20_25(.reset(effective_rst), .clk(clk), .in_a(a20_24to20_25), .in_b(b19_25to20_25), .out_a(a20_25to20_26), .out_b(b20_25to21_25), .out_c(matrixC20_25)); +processing_element pe20_26(.reset(effective_rst), .clk(clk), .in_a(a20_25to20_26), .in_b(b19_26to20_26), .out_a(a20_26to20_27), .out_b(b20_26to21_26), .out_c(matrixC20_26)); +processing_element pe20_27(.reset(effective_rst), .clk(clk), .in_a(a20_26to20_27), .in_b(b19_27to20_27), .out_a(a20_27to20_28), .out_b(b20_27to21_27), .out_c(matrixC20_27)); +processing_element pe20_28(.reset(effective_rst), .clk(clk), .in_a(a20_27to20_28), .in_b(b19_28to20_28), .out_a(a20_28to20_29), .out_b(b20_28to21_28), .out_c(matrixC20_28)); +processing_element pe20_29(.reset(effective_rst), .clk(clk), .in_a(a20_28to20_29), .in_b(b19_29to20_29), .out_a(a20_29to20_30), .out_b(b20_29to21_29), .out_c(matrixC20_29)); +processing_element pe20_30(.reset(effective_rst), .clk(clk), .in_a(a20_29to20_30), .in_b(b19_30to20_30), .out_a(a20_30to20_31), .out_b(b20_30to21_30), .out_c(matrixC20_30)); +processing_element pe20_31(.reset(effective_rst), .clk(clk), .in_a(a20_30to20_31), .in_b(b19_31to20_31), .out_a(a20_31to20_32), .out_b(b20_31to21_31), .out_c(matrixC20_31)); +processing_element pe21_1(.reset(effective_rst), .clk(clk), .in_a(a21_0to21_1), .in_b(b20_1to21_1), .out_a(a21_1to21_2), .out_b(b21_1to22_1), .out_c(matrixC21_1)); +processing_element pe21_2(.reset(effective_rst), .clk(clk), .in_a(a21_1to21_2), .in_b(b20_2to21_2), .out_a(a21_2to21_3), .out_b(b21_2to22_2), .out_c(matrixC21_2)); +processing_element pe21_3(.reset(effective_rst), .clk(clk), .in_a(a21_2to21_3), .in_b(b20_3to21_3), .out_a(a21_3to21_4), .out_b(b21_3to22_3), .out_c(matrixC21_3)); +processing_element pe21_4(.reset(effective_rst), .clk(clk), .in_a(a21_3to21_4), .in_b(b20_4to21_4), .out_a(a21_4to21_5), .out_b(b21_4to22_4), .out_c(matrixC21_4)); +processing_element pe21_5(.reset(effective_rst), .clk(clk), .in_a(a21_4to21_5), .in_b(b20_5to21_5), .out_a(a21_5to21_6), .out_b(b21_5to22_5), .out_c(matrixC21_5)); +processing_element pe21_6(.reset(effective_rst), .clk(clk), .in_a(a21_5to21_6), .in_b(b20_6to21_6), .out_a(a21_6to21_7), .out_b(b21_6to22_6), .out_c(matrixC21_6)); +processing_element pe21_7(.reset(effective_rst), .clk(clk), .in_a(a21_6to21_7), .in_b(b20_7to21_7), .out_a(a21_7to21_8), .out_b(b21_7to22_7), .out_c(matrixC21_7)); +processing_element pe21_8(.reset(effective_rst), .clk(clk), .in_a(a21_7to21_8), .in_b(b20_8to21_8), .out_a(a21_8to21_9), .out_b(b21_8to22_8), .out_c(matrixC21_8)); +processing_element pe21_9(.reset(effective_rst), .clk(clk), .in_a(a21_8to21_9), .in_b(b20_9to21_9), .out_a(a21_9to21_10), .out_b(b21_9to22_9), .out_c(matrixC21_9)); +processing_element pe21_10(.reset(effective_rst), .clk(clk), .in_a(a21_9to21_10), .in_b(b20_10to21_10), .out_a(a21_10to21_11), .out_b(b21_10to22_10), .out_c(matrixC21_10)); +processing_element pe21_11(.reset(effective_rst), .clk(clk), .in_a(a21_10to21_11), .in_b(b20_11to21_11), .out_a(a21_11to21_12), .out_b(b21_11to22_11), .out_c(matrixC21_11)); +processing_element pe21_12(.reset(effective_rst), .clk(clk), .in_a(a21_11to21_12), .in_b(b20_12to21_12), .out_a(a21_12to21_13), .out_b(b21_12to22_12), .out_c(matrixC21_12)); +processing_element pe21_13(.reset(effective_rst), .clk(clk), .in_a(a21_12to21_13), .in_b(b20_13to21_13), .out_a(a21_13to21_14), .out_b(b21_13to22_13), .out_c(matrixC21_13)); +processing_element pe21_14(.reset(effective_rst), .clk(clk), .in_a(a21_13to21_14), .in_b(b20_14to21_14), .out_a(a21_14to21_15), .out_b(b21_14to22_14), .out_c(matrixC21_14)); +processing_element pe21_15(.reset(effective_rst), .clk(clk), .in_a(a21_14to21_15), .in_b(b20_15to21_15), .out_a(a21_15to21_16), .out_b(b21_15to22_15), .out_c(matrixC21_15)); +processing_element pe21_16(.reset(effective_rst), .clk(clk), .in_a(a21_15to21_16), .in_b(b20_16to21_16), .out_a(a21_16to21_17), .out_b(b21_16to22_16), .out_c(matrixC21_16)); +processing_element pe21_17(.reset(effective_rst), .clk(clk), .in_a(a21_16to21_17), .in_b(b20_17to21_17), .out_a(a21_17to21_18), .out_b(b21_17to22_17), .out_c(matrixC21_17)); +processing_element pe21_18(.reset(effective_rst), .clk(clk), .in_a(a21_17to21_18), .in_b(b20_18to21_18), .out_a(a21_18to21_19), .out_b(b21_18to22_18), .out_c(matrixC21_18)); +processing_element pe21_19(.reset(effective_rst), .clk(clk), .in_a(a21_18to21_19), .in_b(b20_19to21_19), .out_a(a21_19to21_20), .out_b(b21_19to22_19), .out_c(matrixC21_19)); +processing_element pe21_20(.reset(effective_rst), .clk(clk), .in_a(a21_19to21_20), .in_b(b20_20to21_20), .out_a(a21_20to21_21), .out_b(b21_20to22_20), .out_c(matrixC21_20)); +processing_element pe21_21(.reset(effective_rst), .clk(clk), .in_a(a21_20to21_21), .in_b(b20_21to21_21), .out_a(a21_21to21_22), .out_b(b21_21to22_21), .out_c(matrixC21_21)); +processing_element pe21_22(.reset(effective_rst), .clk(clk), .in_a(a21_21to21_22), .in_b(b20_22to21_22), .out_a(a21_22to21_23), .out_b(b21_22to22_22), .out_c(matrixC21_22)); +processing_element pe21_23(.reset(effective_rst), .clk(clk), .in_a(a21_22to21_23), .in_b(b20_23to21_23), .out_a(a21_23to21_24), .out_b(b21_23to22_23), .out_c(matrixC21_23)); +processing_element pe21_24(.reset(effective_rst), .clk(clk), .in_a(a21_23to21_24), .in_b(b20_24to21_24), .out_a(a21_24to21_25), .out_b(b21_24to22_24), .out_c(matrixC21_24)); +processing_element pe21_25(.reset(effective_rst), .clk(clk), .in_a(a21_24to21_25), .in_b(b20_25to21_25), .out_a(a21_25to21_26), .out_b(b21_25to22_25), .out_c(matrixC21_25)); +processing_element pe21_26(.reset(effective_rst), .clk(clk), .in_a(a21_25to21_26), .in_b(b20_26to21_26), .out_a(a21_26to21_27), .out_b(b21_26to22_26), .out_c(matrixC21_26)); +processing_element pe21_27(.reset(effective_rst), .clk(clk), .in_a(a21_26to21_27), .in_b(b20_27to21_27), .out_a(a21_27to21_28), .out_b(b21_27to22_27), .out_c(matrixC21_27)); +processing_element pe21_28(.reset(effective_rst), .clk(clk), .in_a(a21_27to21_28), .in_b(b20_28to21_28), .out_a(a21_28to21_29), .out_b(b21_28to22_28), .out_c(matrixC21_28)); +processing_element pe21_29(.reset(effective_rst), .clk(clk), .in_a(a21_28to21_29), .in_b(b20_29to21_29), .out_a(a21_29to21_30), .out_b(b21_29to22_29), .out_c(matrixC21_29)); +processing_element pe21_30(.reset(effective_rst), .clk(clk), .in_a(a21_29to21_30), .in_b(b20_30to21_30), .out_a(a21_30to21_31), .out_b(b21_30to22_30), .out_c(matrixC21_30)); +processing_element pe21_31(.reset(effective_rst), .clk(clk), .in_a(a21_30to21_31), .in_b(b20_31to21_31), .out_a(a21_31to21_32), .out_b(b21_31to22_31), .out_c(matrixC21_31)); +processing_element pe22_1(.reset(effective_rst), .clk(clk), .in_a(a22_0to22_1), .in_b(b21_1to22_1), .out_a(a22_1to22_2), .out_b(b22_1to23_1), .out_c(matrixC22_1)); +processing_element pe22_2(.reset(effective_rst), .clk(clk), .in_a(a22_1to22_2), .in_b(b21_2to22_2), .out_a(a22_2to22_3), .out_b(b22_2to23_2), .out_c(matrixC22_2)); +processing_element pe22_3(.reset(effective_rst), .clk(clk), .in_a(a22_2to22_3), .in_b(b21_3to22_3), .out_a(a22_3to22_4), .out_b(b22_3to23_3), .out_c(matrixC22_3)); +processing_element pe22_4(.reset(effective_rst), .clk(clk), .in_a(a22_3to22_4), .in_b(b21_4to22_4), .out_a(a22_4to22_5), .out_b(b22_4to23_4), .out_c(matrixC22_4)); +processing_element pe22_5(.reset(effective_rst), .clk(clk), .in_a(a22_4to22_5), .in_b(b21_5to22_5), .out_a(a22_5to22_6), .out_b(b22_5to23_5), .out_c(matrixC22_5)); +processing_element pe22_6(.reset(effective_rst), .clk(clk), .in_a(a22_5to22_6), .in_b(b21_6to22_6), .out_a(a22_6to22_7), .out_b(b22_6to23_6), .out_c(matrixC22_6)); +processing_element pe22_7(.reset(effective_rst), .clk(clk), .in_a(a22_6to22_7), .in_b(b21_7to22_7), .out_a(a22_7to22_8), .out_b(b22_7to23_7), .out_c(matrixC22_7)); +processing_element pe22_8(.reset(effective_rst), .clk(clk), .in_a(a22_7to22_8), .in_b(b21_8to22_8), .out_a(a22_8to22_9), .out_b(b22_8to23_8), .out_c(matrixC22_8)); +processing_element pe22_9(.reset(effective_rst), .clk(clk), .in_a(a22_8to22_9), .in_b(b21_9to22_9), .out_a(a22_9to22_10), .out_b(b22_9to23_9), .out_c(matrixC22_9)); +processing_element pe22_10(.reset(effective_rst), .clk(clk), .in_a(a22_9to22_10), .in_b(b21_10to22_10), .out_a(a22_10to22_11), .out_b(b22_10to23_10), .out_c(matrixC22_10)); +processing_element pe22_11(.reset(effective_rst), .clk(clk), .in_a(a22_10to22_11), .in_b(b21_11to22_11), .out_a(a22_11to22_12), .out_b(b22_11to23_11), .out_c(matrixC22_11)); +processing_element pe22_12(.reset(effective_rst), .clk(clk), .in_a(a22_11to22_12), .in_b(b21_12to22_12), .out_a(a22_12to22_13), .out_b(b22_12to23_12), .out_c(matrixC22_12)); +processing_element pe22_13(.reset(effective_rst), .clk(clk), .in_a(a22_12to22_13), .in_b(b21_13to22_13), .out_a(a22_13to22_14), .out_b(b22_13to23_13), .out_c(matrixC22_13)); +processing_element pe22_14(.reset(effective_rst), .clk(clk), .in_a(a22_13to22_14), .in_b(b21_14to22_14), .out_a(a22_14to22_15), .out_b(b22_14to23_14), .out_c(matrixC22_14)); +processing_element pe22_15(.reset(effective_rst), .clk(clk), .in_a(a22_14to22_15), .in_b(b21_15to22_15), .out_a(a22_15to22_16), .out_b(b22_15to23_15), .out_c(matrixC22_15)); +processing_element pe22_16(.reset(effective_rst), .clk(clk), .in_a(a22_15to22_16), .in_b(b21_16to22_16), .out_a(a22_16to22_17), .out_b(b22_16to23_16), .out_c(matrixC22_16)); +processing_element pe22_17(.reset(effective_rst), .clk(clk), .in_a(a22_16to22_17), .in_b(b21_17to22_17), .out_a(a22_17to22_18), .out_b(b22_17to23_17), .out_c(matrixC22_17)); +processing_element pe22_18(.reset(effective_rst), .clk(clk), .in_a(a22_17to22_18), .in_b(b21_18to22_18), .out_a(a22_18to22_19), .out_b(b22_18to23_18), .out_c(matrixC22_18)); +processing_element pe22_19(.reset(effective_rst), .clk(clk), .in_a(a22_18to22_19), .in_b(b21_19to22_19), .out_a(a22_19to22_20), .out_b(b22_19to23_19), .out_c(matrixC22_19)); +processing_element pe22_20(.reset(effective_rst), .clk(clk), .in_a(a22_19to22_20), .in_b(b21_20to22_20), .out_a(a22_20to22_21), .out_b(b22_20to23_20), .out_c(matrixC22_20)); +processing_element pe22_21(.reset(effective_rst), .clk(clk), .in_a(a22_20to22_21), .in_b(b21_21to22_21), .out_a(a22_21to22_22), .out_b(b22_21to23_21), .out_c(matrixC22_21)); +processing_element pe22_22(.reset(effective_rst), .clk(clk), .in_a(a22_21to22_22), .in_b(b21_22to22_22), .out_a(a22_22to22_23), .out_b(b22_22to23_22), .out_c(matrixC22_22)); +processing_element pe22_23(.reset(effective_rst), .clk(clk), .in_a(a22_22to22_23), .in_b(b21_23to22_23), .out_a(a22_23to22_24), .out_b(b22_23to23_23), .out_c(matrixC22_23)); +processing_element pe22_24(.reset(effective_rst), .clk(clk), .in_a(a22_23to22_24), .in_b(b21_24to22_24), .out_a(a22_24to22_25), .out_b(b22_24to23_24), .out_c(matrixC22_24)); +processing_element pe22_25(.reset(effective_rst), .clk(clk), .in_a(a22_24to22_25), .in_b(b21_25to22_25), .out_a(a22_25to22_26), .out_b(b22_25to23_25), .out_c(matrixC22_25)); +processing_element pe22_26(.reset(effective_rst), .clk(clk), .in_a(a22_25to22_26), .in_b(b21_26to22_26), .out_a(a22_26to22_27), .out_b(b22_26to23_26), .out_c(matrixC22_26)); +processing_element pe22_27(.reset(effective_rst), .clk(clk), .in_a(a22_26to22_27), .in_b(b21_27to22_27), .out_a(a22_27to22_28), .out_b(b22_27to23_27), .out_c(matrixC22_27)); +processing_element pe22_28(.reset(effective_rst), .clk(clk), .in_a(a22_27to22_28), .in_b(b21_28to22_28), .out_a(a22_28to22_29), .out_b(b22_28to23_28), .out_c(matrixC22_28)); +processing_element pe22_29(.reset(effective_rst), .clk(clk), .in_a(a22_28to22_29), .in_b(b21_29to22_29), .out_a(a22_29to22_30), .out_b(b22_29to23_29), .out_c(matrixC22_29)); +processing_element pe22_30(.reset(effective_rst), .clk(clk), .in_a(a22_29to22_30), .in_b(b21_30to22_30), .out_a(a22_30to22_31), .out_b(b22_30to23_30), .out_c(matrixC22_30)); +processing_element pe22_31(.reset(effective_rst), .clk(clk), .in_a(a22_30to22_31), .in_b(b21_31to22_31), .out_a(a22_31to22_32), .out_b(b22_31to23_31), .out_c(matrixC22_31)); +processing_element pe23_1(.reset(effective_rst), .clk(clk), .in_a(a23_0to23_1), .in_b(b22_1to23_1), .out_a(a23_1to23_2), .out_b(b23_1to24_1), .out_c(matrixC23_1)); +processing_element pe23_2(.reset(effective_rst), .clk(clk), .in_a(a23_1to23_2), .in_b(b22_2to23_2), .out_a(a23_2to23_3), .out_b(b23_2to24_2), .out_c(matrixC23_2)); +processing_element pe23_3(.reset(effective_rst), .clk(clk), .in_a(a23_2to23_3), .in_b(b22_3to23_3), .out_a(a23_3to23_4), .out_b(b23_3to24_3), .out_c(matrixC23_3)); +processing_element pe23_4(.reset(effective_rst), .clk(clk), .in_a(a23_3to23_4), .in_b(b22_4to23_4), .out_a(a23_4to23_5), .out_b(b23_4to24_4), .out_c(matrixC23_4)); +processing_element pe23_5(.reset(effective_rst), .clk(clk), .in_a(a23_4to23_5), .in_b(b22_5to23_5), .out_a(a23_5to23_6), .out_b(b23_5to24_5), .out_c(matrixC23_5)); +processing_element pe23_6(.reset(effective_rst), .clk(clk), .in_a(a23_5to23_6), .in_b(b22_6to23_6), .out_a(a23_6to23_7), .out_b(b23_6to24_6), .out_c(matrixC23_6)); +processing_element pe23_7(.reset(effective_rst), .clk(clk), .in_a(a23_6to23_7), .in_b(b22_7to23_7), .out_a(a23_7to23_8), .out_b(b23_7to24_7), .out_c(matrixC23_7)); +processing_element pe23_8(.reset(effective_rst), .clk(clk), .in_a(a23_7to23_8), .in_b(b22_8to23_8), .out_a(a23_8to23_9), .out_b(b23_8to24_8), .out_c(matrixC23_8)); +processing_element pe23_9(.reset(effective_rst), .clk(clk), .in_a(a23_8to23_9), .in_b(b22_9to23_9), .out_a(a23_9to23_10), .out_b(b23_9to24_9), .out_c(matrixC23_9)); +processing_element pe23_10(.reset(effective_rst), .clk(clk), .in_a(a23_9to23_10), .in_b(b22_10to23_10), .out_a(a23_10to23_11), .out_b(b23_10to24_10), .out_c(matrixC23_10)); +processing_element pe23_11(.reset(effective_rst), .clk(clk), .in_a(a23_10to23_11), .in_b(b22_11to23_11), .out_a(a23_11to23_12), .out_b(b23_11to24_11), .out_c(matrixC23_11)); +processing_element pe23_12(.reset(effective_rst), .clk(clk), .in_a(a23_11to23_12), .in_b(b22_12to23_12), .out_a(a23_12to23_13), .out_b(b23_12to24_12), .out_c(matrixC23_12)); +processing_element pe23_13(.reset(effective_rst), .clk(clk), .in_a(a23_12to23_13), .in_b(b22_13to23_13), .out_a(a23_13to23_14), .out_b(b23_13to24_13), .out_c(matrixC23_13)); +processing_element pe23_14(.reset(effective_rst), .clk(clk), .in_a(a23_13to23_14), .in_b(b22_14to23_14), .out_a(a23_14to23_15), .out_b(b23_14to24_14), .out_c(matrixC23_14)); +processing_element pe23_15(.reset(effective_rst), .clk(clk), .in_a(a23_14to23_15), .in_b(b22_15to23_15), .out_a(a23_15to23_16), .out_b(b23_15to24_15), .out_c(matrixC23_15)); +processing_element pe23_16(.reset(effective_rst), .clk(clk), .in_a(a23_15to23_16), .in_b(b22_16to23_16), .out_a(a23_16to23_17), .out_b(b23_16to24_16), .out_c(matrixC23_16)); +processing_element pe23_17(.reset(effective_rst), .clk(clk), .in_a(a23_16to23_17), .in_b(b22_17to23_17), .out_a(a23_17to23_18), .out_b(b23_17to24_17), .out_c(matrixC23_17)); +processing_element pe23_18(.reset(effective_rst), .clk(clk), .in_a(a23_17to23_18), .in_b(b22_18to23_18), .out_a(a23_18to23_19), .out_b(b23_18to24_18), .out_c(matrixC23_18)); +processing_element pe23_19(.reset(effective_rst), .clk(clk), .in_a(a23_18to23_19), .in_b(b22_19to23_19), .out_a(a23_19to23_20), .out_b(b23_19to24_19), .out_c(matrixC23_19)); +processing_element pe23_20(.reset(effective_rst), .clk(clk), .in_a(a23_19to23_20), .in_b(b22_20to23_20), .out_a(a23_20to23_21), .out_b(b23_20to24_20), .out_c(matrixC23_20)); +processing_element pe23_21(.reset(effective_rst), .clk(clk), .in_a(a23_20to23_21), .in_b(b22_21to23_21), .out_a(a23_21to23_22), .out_b(b23_21to24_21), .out_c(matrixC23_21)); +processing_element pe23_22(.reset(effective_rst), .clk(clk), .in_a(a23_21to23_22), .in_b(b22_22to23_22), .out_a(a23_22to23_23), .out_b(b23_22to24_22), .out_c(matrixC23_22)); +processing_element pe23_23(.reset(effective_rst), .clk(clk), .in_a(a23_22to23_23), .in_b(b22_23to23_23), .out_a(a23_23to23_24), .out_b(b23_23to24_23), .out_c(matrixC23_23)); +processing_element pe23_24(.reset(effective_rst), .clk(clk), .in_a(a23_23to23_24), .in_b(b22_24to23_24), .out_a(a23_24to23_25), .out_b(b23_24to24_24), .out_c(matrixC23_24)); +processing_element pe23_25(.reset(effective_rst), .clk(clk), .in_a(a23_24to23_25), .in_b(b22_25to23_25), .out_a(a23_25to23_26), .out_b(b23_25to24_25), .out_c(matrixC23_25)); +processing_element pe23_26(.reset(effective_rst), .clk(clk), .in_a(a23_25to23_26), .in_b(b22_26to23_26), .out_a(a23_26to23_27), .out_b(b23_26to24_26), .out_c(matrixC23_26)); +processing_element pe23_27(.reset(effective_rst), .clk(clk), .in_a(a23_26to23_27), .in_b(b22_27to23_27), .out_a(a23_27to23_28), .out_b(b23_27to24_27), .out_c(matrixC23_27)); +processing_element pe23_28(.reset(effective_rst), .clk(clk), .in_a(a23_27to23_28), .in_b(b22_28to23_28), .out_a(a23_28to23_29), .out_b(b23_28to24_28), .out_c(matrixC23_28)); +processing_element pe23_29(.reset(effective_rst), .clk(clk), .in_a(a23_28to23_29), .in_b(b22_29to23_29), .out_a(a23_29to23_30), .out_b(b23_29to24_29), .out_c(matrixC23_29)); +processing_element pe23_30(.reset(effective_rst), .clk(clk), .in_a(a23_29to23_30), .in_b(b22_30to23_30), .out_a(a23_30to23_31), .out_b(b23_30to24_30), .out_c(matrixC23_30)); +processing_element pe23_31(.reset(effective_rst), .clk(clk), .in_a(a23_30to23_31), .in_b(b22_31to23_31), .out_a(a23_31to23_32), .out_b(b23_31to24_31), .out_c(matrixC23_31)); +processing_element pe24_1(.reset(effective_rst), .clk(clk), .in_a(a24_0to24_1), .in_b(b23_1to24_1), .out_a(a24_1to24_2), .out_b(b24_1to25_1), .out_c(matrixC24_1)); +processing_element pe24_2(.reset(effective_rst), .clk(clk), .in_a(a24_1to24_2), .in_b(b23_2to24_2), .out_a(a24_2to24_3), .out_b(b24_2to25_2), .out_c(matrixC24_2)); +processing_element pe24_3(.reset(effective_rst), .clk(clk), .in_a(a24_2to24_3), .in_b(b23_3to24_3), .out_a(a24_3to24_4), .out_b(b24_3to25_3), .out_c(matrixC24_3)); +processing_element pe24_4(.reset(effective_rst), .clk(clk), .in_a(a24_3to24_4), .in_b(b23_4to24_4), .out_a(a24_4to24_5), .out_b(b24_4to25_4), .out_c(matrixC24_4)); +processing_element pe24_5(.reset(effective_rst), .clk(clk), .in_a(a24_4to24_5), .in_b(b23_5to24_5), .out_a(a24_5to24_6), .out_b(b24_5to25_5), .out_c(matrixC24_5)); +processing_element pe24_6(.reset(effective_rst), .clk(clk), .in_a(a24_5to24_6), .in_b(b23_6to24_6), .out_a(a24_6to24_7), .out_b(b24_6to25_6), .out_c(matrixC24_6)); +processing_element pe24_7(.reset(effective_rst), .clk(clk), .in_a(a24_6to24_7), .in_b(b23_7to24_7), .out_a(a24_7to24_8), .out_b(b24_7to25_7), .out_c(matrixC24_7)); +processing_element pe24_8(.reset(effective_rst), .clk(clk), .in_a(a24_7to24_8), .in_b(b23_8to24_8), .out_a(a24_8to24_9), .out_b(b24_8to25_8), .out_c(matrixC24_8)); +processing_element pe24_9(.reset(effective_rst), .clk(clk), .in_a(a24_8to24_9), .in_b(b23_9to24_9), .out_a(a24_9to24_10), .out_b(b24_9to25_9), .out_c(matrixC24_9)); +processing_element pe24_10(.reset(effective_rst), .clk(clk), .in_a(a24_9to24_10), .in_b(b23_10to24_10), .out_a(a24_10to24_11), .out_b(b24_10to25_10), .out_c(matrixC24_10)); +processing_element pe24_11(.reset(effective_rst), .clk(clk), .in_a(a24_10to24_11), .in_b(b23_11to24_11), .out_a(a24_11to24_12), .out_b(b24_11to25_11), .out_c(matrixC24_11)); +processing_element pe24_12(.reset(effective_rst), .clk(clk), .in_a(a24_11to24_12), .in_b(b23_12to24_12), .out_a(a24_12to24_13), .out_b(b24_12to25_12), .out_c(matrixC24_12)); +processing_element pe24_13(.reset(effective_rst), .clk(clk), .in_a(a24_12to24_13), .in_b(b23_13to24_13), .out_a(a24_13to24_14), .out_b(b24_13to25_13), .out_c(matrixC24_13)); +processing_element pe24_14(.reset(effective_rst), .clk(clk), .in_a(a24_13to24_14), .in_b(b23_14to24_14), .out_a(a24_14to24_15), .out_b(b24_14to25_14), .out_c(matrixC24_14)); +processing_element pe24_15(.reset(effective_rst), .clk(clk), .in_a(a24_14to24_15), .in_b(b23_15to24_15), .out_a(a24_15to24_16), .out_b(b24_15to25_15), .out_c(matrixC24_15)); +processing_element pe24_16(.reset(effective_rst), .clk(clk), .in_a(a24_15to24_16), .in_b(b23_16to24_16), .out_a(a24_16to24_17), .out_b(b24_16to25_16), .out_c(matrixC24_16)); +processing_element pe24_17(.reset(effective_rst), .clk(clk), .in_a(a24_16to24_17), .in_b(b23_17to24_17), .out_a(a24_17to24_18), .out_b(b24_17to25_17), .out_c(matrixC24_17)); +processing_element pe24_18(.reset(effective_rst), .clk(clk), .in_a(a24_17to24_18), .in_b(b23_18to24_18), .out_a(a24_18to24_19), .out_b(b24_18to25_18), .out_c(matrixC24_18)); +processing_element pe24_19(.reset(effective_rst), .clk(clk), .in_a(a24_18to24_19), .in_b(b23_19to24_19), .out_a(a24_19to24_20), .out_b(b24_19to25_19), .out_c(matrixC24_19)); +processing_element pe24_20(.reset(effective_rst), .clk(clk), .in_a(a24_19to24_20), .in_b(b23_20to24_20), .out_a(a24_20to24_21), .out_b(b24_20to25_20), .out_c(matrixC24_20)); +processing_element pe24_21(.reset(effective_rst), .clk(clk), .in_a(a24_20to24_21), .in_b(b23_21to24_21), .out_a(a24_21to24_22), .out_b(b24_21to25_21), .out_c(matrixC24_21)); +processing_element pe24_22(.reset(effective_rst), .clk(clk), .in_a(a24_21to24_22), .in_b(b23_22to24_22), .out_a(a24_22to24_23), .out_b(b24_22to25_22), .out_c(matrixC24_22)); +processing_element pe24_23(.reset(effective_rst), .clk(clk), .in_a(a24_22to24_23), .in_b(b23_23to24_23), .out_a(a24_23to24_24), .out_b(b24_23to25_23), .out_c(matrixC24_23)); +processing_element pe24_24(.reset(effective_rst), .clk(clk), .in_a(a24_23to24_24), .in_b(b23_24to24_24), .out_a(a24_24to24_25), .out_b(b24_24to25_24), .out_c(matrixC24_24)); +processing_element pe24_25(.reset(effective_rst), .clk(clk), .in_a(a24_24to24_25), .in_b(b23_25to24_25), .out_a(a24_25to24_26), .out_b(b24_25to25_25), .out_c(matrixC24_25)); +processing_element pe24_26(.reset(effective_rst), .clk(clk), .in_a(a24_25to24_26), .in_b(b23_26to24_26), .out_a(a24_26to24_27), .out_b(b24_26to25_26), .out_c(matrixC24_26)); +processing_element pe24_27(.reset(effective_rst), .clk(clk), .in_a(a24_26to24_27), .in_b(b23_27to24_27), .out_a(a24_27to24_28), .out_b(b24_27to25_27), .out_c(matrixC24_27)); +processing_element pe24_28(.reset(effective_rst), .clk(clk), .in_a(a24_27to24_28), .in_b(b23_28to24_28), .out_a(a24_28to24_29), .out_b(b24_28to25_28), .out_c(matrixC24_28)); +processing_element pe24_29(.reset(effective_rst), .clk(clk), .in_a(a24_28to24_29), .in_b(b23_29to24_29), .out_a(a24_29to24_30), .out_b(b24_29to25_29), .out_c(matrixC24_29)); +processing_element pe24_30(.reset(effective_rst), .clk(clk), .in_a(a24_29to24_30), .in_b(b23_30to24_30), .out_a(a24_30to24_31), .out_b(b24_30to25_30), .out_c(matrixC24_30)); +processing_element pe24_31(.reset(effective_rst), .clk(clk), .in_a(a24_30to24_31), .in_b(b23_31to24_31), .out_a(a24_31to24_32), .out_b(b24_31to25_31), .out_c(matrixC24_31)); +processing_element pe25_1(.reset(effective_rst), .clk(clk), .in_a(a25_0to25_1), .in_b(b24_1to25_1), .out_a(a25_1to25_2), .out_b(b25_1to26_1), .out_c(matrixC25_1)); +processing_element pe25_2(.reset(effective_rst), .clk(clk), .in_a(a25_1to25_2), .in_b(b24_2to25_2), .out_a(a25_2to25_3), .out_b(b25_2to26_2), .out_c(matrixC25_2)); +processing_element pe25_3(.reset(effective_rst), .clk(clk), .in_a(a25_2to25_3), .in_b(b24_3to25_3), .out_a(a25_3to25_4), .out_b(b25_3to26_3), .out_c(matrixC25_3)); +processing_element pe25_4(.reset(effective_rst), .clk(clk), .in_a(a25_3to25_4), .in_b(b24_4to25_4), .out_a(a25_4to25_5), .out_b(b25_4to26_4), .out_c(matrixC25_4)); +processing_element pe25_5(.reset(effective_rst), .clk(clk), .in_a(a25_4to25_5), .in_b(b24_5to25_5), .out_a(a25_5to25_6), .out_b(b25_5to26_5), .out_c(matrixC25_5)); +processing_element pe25_6(.reset(effective_rst), .clk(clk), .in_a(a25_5to25_6), .in_b(b24_6to25_6), .out_a(a25_6to25_7), .out_b(b25_6to26_6), .out_c(matrixC25_6)); +processing_element pe25_7(.reset(effective_rst), .clk(clk), .in_a(a25_6to25_7), .in_b(b24_7to25_7), .out_a(a25_7to25_8), .out_b(b25_7to26_7), .out_c(matrixC25_7)); +processing_element pe25_8(.reset(effective_rst), .clk(clk), .in_a(a25_7to25_8), .in_b(b24_8to25_8), .out_a(a25_8to25_9), .out_b(b25_8to26_8), .out_c(matrixC25_8)); +processing_element pe25_9(.reset(effective_rst), .clk(clk), .in_a(a25_8to25_9), .in_b(b24_9to25_9), .out_a(a25_9to25_10), .out_b(b25_9to26_9), .out_c(matrixC25_9)); +processing_element pe25_10(.reset(effective_rst), .clk(clk), .in_a(a25_9to25_10), .in_b(b24_10to25_10), .out_a(a25_10to25_11), .out_b(b25_10to26_10), .out_c(matrixC25_10)); +processing_element pe25_11(.reset(effective_rst), .clk(clk), .in_a(a25_10to25_11), .in_b(b24_11to25_11), .out_a(a25_11to25_12), .out_b(b25_11to26_11), .out_c(matrixC25_11)); +processing_element pe25_12(.reset(effective_rst), .clk(clk), .in_a(a25_11to25_12), .in_b(b24_12to25_12), .out_a(a25_12to25_13), .out_b(b25_12to26_12), .out_c(matrixC25_12)); +processing_element pe25_13(.reset(effective_rst), .clk(clk), .in_a(a25_12to25_13), .in_b(b24_13to25_13), .out_a(a25_13to25_14), .out_b(b25_13to26_13), .out_c(matrixC25_13)); +processing_element pe25_14(.reset(effective_rst), .clk(clk), .in_a(a25_13to25_14), .in_b(b24_14to25_14), .out_a(a25_14to25_15), .out_b(b25_14to26_14), .out_c(matrixC25_14)); +processing_element pe25_15(.reset(effective_rst), .clk(clk), .in_a(a25_14to25_15), .in_b(b24_15to25_15), .out_a(a25_15to25_16), .out_b(b25_15to26_15), .out_c(matrixC25_15)); +processing_element pe25_16(.reset(effective_rst), .clk(clk), .in_a(a25_15to25_16), .in_b(b24_16to25_16), .out_a(a25_16to25_17), .out_b(b25_16to26_16), .out_c(matrixC25_16)); +processing_element pe25_17(.reset(effective_rst), .clk(clk), .in_a(a25_16to25_17), .in_b(b24_17to25_17), .out_a(a25_17to25_18), .out_b(b25_17to26_17), .out_c(matrixC25_17)); +processing_element pe25_18(.reset(effective_rst), .clk(clk), .in_a(a25_17to25_18), .in_b(b24_18to25_18), .out_a(a25_18to25_19), .out_b(b25_18to26_18), .out_c(matrixC25_18)); +processing_element pe25_19(.reset(effective_rst), .clk(clk), .in_a(a25_18to25_19), .in_b(b24_19to25_19), .out_a(a25_19to25_20), .out_b(b25_19to26_19), .out_c(matrixC25_19)); +processing_element pe25_20(.reset(effective_rst), .clk(clk), .in_a(a25_19to25_20), .in_b(b24_20to25_20), .out_a(a25_20to25_21), .out_b(b25_20to26_20), .out_c(matrixC25_20)); +processing_element pe25_21(.reset(effective_rst), .clk(clk), .in_a(a25_20to25_21), .in_b(b24_21to25_21), .out_a(a25_21to25_22), .out_b(b25_21to26_21), .out_c(matrixC25_21)); +processing_element pe25_22(.reset(effective_rst), .clk(clk), .in_a(a25_21to25_22), .in_b(b24_22to25_22), .out_a(a25_22to25_23), .out_b(b25_22to26_22), .out_c(matrixC25_22)); +processing_element pe25_23(.reset(effective_rst), .clk(clk), .in_a(a25_22to25_23), .in_b(b24_23to25_23), .out_a(a25_23to25_24), .out_b(b25_23to26_23), .out_c(matrixC25_23)); +processing_element pe25_24(.reset(effective_rst), .clk(clk), .in_a(a25_23to25_24), .in_b(b24_24to25_24), .out_a(a25_24to25_25), .out_b(b25_24to26_24), .out_c(matrixC25_24)); +processing_element pe25_25(.reset(effective_rst), .clk(clk), .in_a(a25_24to25_25), .in_b(b24_25to25_25), .out_a(a25_25to25_26), .out_b(b25_25to26_25), .out_c(matrixC25_25)); +processing_element pe25_26(.reset(effective_rst), .clk(clk), .in_a(a25_25to25_26), .in_b(b24_26to25_26), .out_a(a25_26to25_27), .out_b(b25_26to26_26), .out_c(matrixC25_26)); +processing_element pe25_27(.reset(effective_rst), .clk(clk), .in_a(a25_26to25_27), .in_b(b24_27to25_27), .out_a(a25_27to25_28), .out_b(b25_27to26_27), .out_c(matrixC25_27)); +processing_element pe25_28(.reset(effective_rst), .clk(clk), .in_a(a25_27to25_28), .in_b(b24_28to25_28), .out_a(a25_28to25_29), .out_b(b25_28to26_28), .out_c(matrixC25_28)); +processing_element pe25_29(.reset(effective_rst), .clk(clk), .in_a(a25_28to25_29), .in_b(b24_29to25_29), .out_a(a25_29to25_30), .out_b(b25_29to26_29), .out_c(matrixC25_29)); +processing_element pe25_30(.reset(effective_rst), .clk(clk), .in_a(a25_29to25_30), .in_b(b24_30to25_30), .out_a(a25_30to25_31), .out_b(b25_30to26_30), .out_c(matrixC25_30)); +processing_element pe25_31(.reset(effective_rst), .clk(clk), .in_a(a25_30to25_31), .in_b(b24_31to25_31), .out_a(a25_31to25_32), .out_b(b25_31to26_31), .out_c(matrixC25_31)); +processing_element pe26_1(.reset(effective_rst), .clk(clk), .in_a(a26_0to26_1), .in_b(b25_1to26_1), .out_a(a26_1to26_2), .out_b(b26_1to27_1), .out_c(matrixC26_1)); +processing_element pe26_2(.reset(effective_rst), .clk(clk), .in_a(a26_1to26_2), .in_b(b25_2to26_2), .out_a(a26_2to26_3), .out_b(b26_2to27_2), .out_c(matrixC26_2)); +processing_element pe26_3(.reset(effective_rst), .clk(clk), .in_a(a26_2to26_3), .in_b(b25_3to26_3), .out_a(a26_3to26_4), .out_b(b26_3to27_3), .out_c(matrixC26_3)); +processing_element pe26_4(.reset(effective_rst), .clk(clk), .in_a(a26_3to26_4), .in_b(b25_4to26_4), .out_a(a26_4to26_5), .out_b(b26_4to27_4), .out_c(matrixC26_4)); +processing_element pe26_5(.reset(effective_rst), .clk(clk), .in_a(a26_4to26_5), .in_b(b25_5to26_5), .out_a(a26_5to26_6), .out_b(b26_5to27_5), .out_c(matrixC26_5)); +processing_element pe26_6(.reset(effective_rst), .clk(clk), .in_a(a26_5to26_6), .in_b(b25_6to26_6), .out_a(a26_6to26_7), .out_b(b26_6to27_6), .out_c(matrixC26_6)); +processing_element pe26_7(.reset(effective_rst), .clk(clk), .in_a(a26_6to26_7), .in_b(b25_7to26_7), .out_a(a26_7to26_8), .out_b(b26_7to27_7), .out_c(matrixC26_7)); +processing_element pe26_8(.reset(effective_rst), .clk(clk), .in_a(a26_7to26_8), .in_b(b25_8to26_8), .out_a(a26_8to26_9), .out_b(b26_8to27_8), .out_c(matrixC26_8)); +processing_element pe26_9(.reset(effective_rst), .clk(clk), .in_a(a26_8to26_9), .in_b(b25_9to26_9), .out_a(a26_9to26_10), .out_b(b26_9to27_9), .out_c(matrixC26_9)); +processing_element pe26_10(.reset(effective_rst), .clk(clk), .in_a(a26_9to26_10), .in_b(b25_10to26_10), .out_a(a26_10to26_11), .out_b(b26_10to27_10), .out_c(matrixC26_10)); +processing_element pe26_11(.reset(effective_rst), .clk(clk), .in_a(a26_10to26_11), .in_b(b25_11to26_11), .out_a(a26_11to26_12), .out_b(b26_11to27_11), .out_c(matrixC26_11)); +processing_element pe26_12(.reset(effective_rst), .clk(clk), .in_a(a26_11to26_12), .in_b(b25_12to26_12), .out_a(a26_12to26_13), .out_b(b26_12to27_12), .out_c(matrixC26_12)); +processing_element pe26_13(.reset(effective_rst), .clk(clk), .in_a(a26_12to26_13), .in_b(b25_13to26_13), .out_a(a26_13to26_14), .out_b(b26_13to27_13), .out_c(matrixC26_13)); +processing_element pe26_14(.reset(effective_rst), .clk(clk), .in_a(a26_13to26_14), .in_b(b25_14to26_14), .out_a(a26_14to26_15), .out_b(b26_14to27_14), .out_c(matrixC26_14)); +processing_element pe26_15(.reset(effective_rst), .clk(clk), .in_a(a26_14to26_15), .in_b(b25_15to26_15), .out_a(a26_15to26_16), .out_b(b26_15to27_15), .out_c(matrixC26_15)); +processing_element pe26_16(.reset(effective_rst), .clk(clk), .in_a(a26_15to26_16), .in_b(b25_16to26_16), .out_a(a26_16to26_17), .out_b(b26_16to27_16), .out_c(matrixC26_16)); +processing_element pe26_17(.reset(effective_rst), .clk(clk), .in_a(a26_16to26_17), .in_b(b25_17to26_17), .out_a(a26_17to26_18), .out_b(b26_17to27_17), .out_c(matrixC26_17)); +processing_element pe26_18(.reset(effective_rst), .clk(clk), .in_a(a26_17to26_18), .in_b(b25_18to26_18), .out_a(a26_18to26_19), .out_b(b26_18to27_18), .out_c(matrixC26_18)); +processing_element pe26_19(.reset(effective_rst), .clk(clk), .in_a(a26_18to26_19), .in_b(b25_19to26_19), .out_a(a26_19to26_20), .out_b(b26_19to27_19), .out_c(matrixC26_19)); +processing_element pe26_20(.reset(effective_rst), .clk(clk), .in_a(a26_19to26_20), .in_b(b25_20to26_20), .out_a(a26_20to26_21), .out_b(b26_20to27_20), .out_c(matrixC26_20)); +processing_element pe26_21(.reset(effective_rst), .clk(clk), .in_a(a26_20to26_21), .in_b(b25_21to26_21), .out_a(a26_21to26_22), .out_b(b26_21to27_21), .out_c(matrixC26_21)); +processing_element pe26_22(.reset(effective_rst), .clk(clk), .in_a(a26_21to26_22), .in_b(b25_22to26_22), .out_a(a26_22to26_23), .out_b(b26_22to27_22), .out_c(matrixC26_22)); +processing_element pe26_23(.reset(effective_rst), .clk(clk), .in_a(a26_22to26_23), .in_b(b25_23to26_23), .out_a(a26_23to26_24), .out_b(b26_23to27_23), .out_c(matrixC26_23)); +processing_element pe26_24(.reset(effective_rst), .clk(clk), .in_a(a26_23to26_24), .in_b(b25_24to26_24), .out_a(a26_24to26_25), .out_b(b26_24to27_24), .out_c(matrixC26_24)); +processing_element pe26_25(.reset(effective_rst), .clk(clk), .in_a(a26_24to26_25), .in_b(b25_25to26_25), .out_a(a26_25to26_26), .out_b(b26_25to27_25), .out_c(matrixC26_25)); +processing_element pe26_26(.reset(effective_rst), .clk(clk), .in_a(a26_25to26_26), .in_b(b25_26to26_26), .out_a(a26_26to26_27), .out_b(b26_26to27_26), .out_c(matrixC26_26)); +processing_element pe26_27(.reset(effective_rst), .clk(clk), .in_a(a26_26to26_27), .in_b(b25_27to26_27), .out_a(a26_27to26_28), .out_b(b26_27to27_27), .out_c(matrixC26_27)); +processing_element pe26_28(.reset(effective_rst), .clk(clk), .in_a(a26_27to26_28), .in_b(b25_28to26_28), .out_a(a26_28to26_29), .out_b(b26_28to27_28), .out_c(matrixC26_28)); +processing_element pe26_29(.reset(effective_rst), .clk(clk), .in_a(a26_28to26_29), .in_b(b25_29to26_29), .out_a(a26_29to26_30), .out_b(b26_29to27_29), .out_c(matrixC26_29)); +processing_element pe26_30(.reset(effective_rst), .clk(clk), .in_a(a26_29to26_30), .in_b(b25_30to26_30), .out_a(a26_30to26_31), .out_b(b26_30to27_30), .out_c(matrixC26_30)); +processing_element pe26_31(.reset(effective_rst), .clk(clk), .in_a(a26_30to26_31), .in_b(b25_31to26_31), .out_a(a26_31to26_32), .out_b(b26_31to27_31), .out_c(matrixC26_31)); +processing_element pe27_1(.reset(effective_rst), .clk(clk), .in_a(a27_0to27_1), .in_b(b26_1to27_1), .out_a(a27_1to27_2), .out_b(b27_1to28_1), .out_c(matrixC27_1)); +processing_element pe27_2(.reset(effective_rst), .clk(clk), .in_a(a27_1to27_2), .in_b(b26_2to27_2), .out_a(a27_2to27_3), .out_b(b27_2to28_2), .out_c(matrixC27_2)); +processing_element pe27_3(.reset(effective_rst), .clk(clk), .in_a(a27_2to27_3), .in_b(b26_3to27_3), .out_a(a27_3to27_4), .out_b(b27_3to28_3), .out_c(matrixC27_3)); +processing_element pe27_4(.reset(effective_rst), .clk(clk), .in_a(a27_3to27_4), .in_b(b26_4to27_4), .out_a(a27_4to27_5), .out_b(b27_4to28_4), .out_c(matrixC27_4)); +processing_element pe27_5(.reset(effective_rst), .clk(clk), .in_a(a27_4to27_5), .in_b(b26_5to27_5), .out_a(a27_5to27_6), .out_b(b27_5to28_5), .out_c(matrixC27_5)); +processing_element pe27_6(.reset(effective_rst), .clk(clk), .in_a(a27_5to27_6), .in_b(b26_6to27_6), .out_a(a27_6to27_7), .out_b(b27_6to28_6), .out_c(matrixC27_6)); +processing_element pe27_7(.reset(effective_rst), .clk(clk), .in_a(a27_6to27_7), .in_b(b26_7to27_7), .out_a(a27_7to27_8), .out_b(b27_7to28_7), .out_c(matrixC27_7)); +processing_element pe27_8(.reset(effective_rst), .clk(clk), .in_a(a27_7to27_8), .in_b(b26_8to27_8), .out_a(a27_8to27_9), .out_b(b27_8to28_8), .out_c(matrixC27_8)); +processing_element pe27_9(.reset(effective_rst), .clk(clk), .in_a(a27_8to27_9), .in_b(b26_9to27_9), .out_a(a27_9to27_10), .out_b(b27_9to28_9), .out_c(matrixC27_9)); +processing_element pe27_10(.reset(effective_rst), .clk(clk), .in_a(a27_9to27_10), .in_b(b26_10to27_10), .out_a(a27_10to27_11), .out_b(b27_10to28_10), .out_c(matrixC27_10)); +processing_element pe27_11(.reset(effective_rst), .clk(clk), .in_a(a27_10to27_11), .in_b(b26_11to27_11), .out_a(a27_11to27_12), .out_b(b27_11to28_11), .out_c(matrixC27_11)); +processing_element pe27_12(.reset(effective_rst), .clk(clk), .in_a(a27_11to27_12), .in_b(b26_12to27_12), .out_a(a27_12to27_13), .out_b(b27_12to28_12), .out_c(matrixC27_12)); +processing_element pe27_13(.reset(effective_rst), .clk(clk), .in_a(a27_12to27_13), .in_b(b26_13to27_13), .out_a(a27_13to27_14), .out_b(b27_13to28_13), .out_c(matrixC27_13)); +processing_element pe27_14(.reset(effective_rst), .clk(clk), .in_a(a27_13to27_14), .in_b(b26_14to27_14), .out_a(a27_14to27_15), .out_b(b27_14to28_14), .out_c(matrixC27_14)); +processing_element pe27_15(.reset(effective_rst), .clk(clk), .in_a(a27_14to27_15), .in_b(b26_15to27_15), .out_a(a27_15to27_16), .out_b(b27_15to28_15), .out_c(matrixC27_15)); +processing_element pe27_16(.reset(effective_rst), .clk(clk), .in_a(a27_15to27_16), .in_b(b26_16to27_16), .out_a(a27_16to27_17), .out_b(b27_16to28_16), .out_c(matrixC27_16)); +processing_element pe27_17(.reset(effective_rst), .clk(clk), .in_a(a27_16to27_17), .in_b(b26_17to27_17), .out_a(a27_17to27_18), .out_b(b27_17to28_17), .out_c(matrixC27_17)); +processing_element pe27_18(.reset(effective_rst), .clk(clk), .in_a(a27_17to27_18), .in_b(b26_18to27_18), .out_a(a27_18to27_19), .out_b(b27_18to28_18), .out_c(matrixC27_18)); +processing_element pe27_19(.reset(effective_rst), .clk(clk), .in_a(a27_18to27_19), .in_b(b26_19to27_19), .out_a(a27_19to27_20), .out_b(b27_19to28_19), .out_c(matrixC27_19)); +processing_element pe27_20(.reset(effective_rst), .clk(clk), .in_a(a27_19to27_20), .in_b(b26_20to27_20), .out_a(a27_20to27_21), .out_b(b27_20to28_20), .out_c(matrixC27_20)); +processing_element pe27_21(.reset(effective_rst), .clk(clk), .in_a(a27_20to27_21), .in_b(b26_21to27_21), .out_a(a27_21to27_22), .out_b(b27_21to28_21), .out_c(matrixC27_21)); +processing_element pe27_22(.reset(effective_rst), .clk(clk), .in_a(a27_21to27_22), .in_b(b26_22to27_22), .out_a(a27_22to27_23), .out_b(b27_22to28_22), .out_c(matrixC27_22)); +processing_element pe27_23(.reset(effective_rst), .clk(clk), .in_a(a27_22to27_23), .in_b(b26_23to27_23), .out_a(a27_23to27_24), .out_b(b27_23to28_23), .out_c(matrixC27_23)); +processing_element pe27_24(.reset(effective_rst), .clk(clk), .in_a(a27_23to27_24), .in_b(b26_24to27_24), .out_a(a27_24to27_25), .out_b(b27_24to28_24), .out_c(matrixC27_24)); +processing_element pe27_25(.reset(effective_rst), .clk(clk), .in_a(a27_24to27_25), .in_b(b26_25to27_25), .out_a(a27_25to27_26), .out_b(b27_25to28_25), .out_c(matrixC27_25)); +processing_element pe27_26(.reset(effective_rst), .clk(clk), .in_a(a27_25to27_26), .in_b(b26_26to27_26), .out_a(a27_26to27_27), .out_b(b27_26to28_26), .out_c(matrixC27_26)); +processing_element pe27_27(.reset(effective_rst), .clk(clk), .in_a(a27_26to27_27), .in_b(b26_27to27_27), .out_a(a27_27to27_28), .out_b(b27_27to28_27), .out_c(matrixC27_27)); +processing_element pe27_28(.reset(effective_rst), .clk(clk), .in_a(a27_27to27_28), .in_b(b26_28to27_28), .out_a(a27_28to27_29), .out_b(b27_28to28_28), .out_c(matrixC27_28)); +processing_element pe27_29(.reset(effective_rst), .clk(clk), .in_a(a27_28to27_29), .in_b(b26_29to27_29), .out_a(a27_29to27_30), .out_b(b27_29to28_29), .out_c(matrixC27_29)); +processing_element pe27_30(.reset(effective_rst), .clk(clk), .in_a(a27_29to27_30), .in_b(b26_30to27_30), .out_a(a27_30to27_31), .out_b(b27_30to28_30), .out_c(matrixC27_30)); +processing_element pe27_31(.reset(effective_rst), .clk(clk), .in_a(a27_30to27_31), .in_b(b26_31to27_31), .out_a(a27_31to27_32), .out_b(b27_31to28_31), .out_c(matrixC27_31)); +processing_element pe28_1(.reset(effective_rst), .clk(clk), .in_a(a28_0to28_1), .in_b(b27_1to28_1), .out_a(a28_1to28_2), .out_b(b28_1to29_1), .out_c(matrixC28_1)); +processing_element pe28_2(.reset(effective_rst), .clk(clk), .in_a(a28_1to28_2), .in_b(b27_2to28_2), .out_a(a28_2to28_3), .out_b(b28_2to29_2), .out_c(matrixC28_2)); +processing_element pe28_3(.reset(effective_rst), .clk(clk), .in_a(a28_2to28_3), .in_b(b27_3to28_3), .out_a(a28_3to28_4), .out_b(b28_3to29_3), .out_c(matrixC28_3)); +processing_element pe28_4(.reset(effective_rst), .clk(clk), .in_a(a28_3to28_4), .in_b(b27_4to28_4), .out_a(a28_4to28_5), .out_b(b28_4to29_4), .out_c(matrixC28_4)); +processing_element pe28_5(.reset(effective_rst), .clk(clk), .in_a(a28_4to28_5), .in_b(b27_5to28_5), .out_a(a28_5to28_6), .out_b(b28_5to29_5), .out_c(matrixC28_5)); +processing_element pe28_6(.reset(effective_rst), .clk(clk), .in_a(a28_5to28_6), .in_b(b27_6to28_6), .out_a(a28_6to28_7), .out_b(b28_6to29_6), .out_c(matrixC28_6)); +processing_element pe28_7(.reset(effective_rst), .clk(clk), .in_a(a28_6to28_7), .in_b(b27_7to28_7), .out_a(a28_7to28_8), .out_b(b28_7to29_7), .out_c(matrixC28_7)); +processing_element pe28_8(.reset(effective_rst), .clk(clk), .in_a(a28_7to28_8), .in_b(b27_8to28_8), .out_a(a28_8to28_9), .out_b(b28_8to29_8), .out_c(matrixC28_8)); +processing_element pe28_9(.reset(effective_rst), .clk(clk), .in_a(a28_8to28_9), .in_b(b27_9to28_9), .out_a(a28_9to28_10), .out_b(b28_9to29_9), .out_c(matrixC28_9)); +processing_element pe28_10(.reset(effective_rst), .clk(clk), .in_a(a28_9to28_10), .in_b(b27_10to28_10), .out_a(a28_10to28_11), .out_b(b28_10to29_10), .out_c(matrixC28_10)); +processing_element pe28_11(.reset(effective_rst), .clk(clk), .in_a(a28_10to28_11), .in_b(b27_11to28_11), .out_a(a28_11to28_12), .out_b(b28_11to29_11), .out_c(matrixC28_11)); +processing_element pe28_12(.reset(effective_rst), .clk(clk), .in_a(a28_11to28_12), .in_b(b27_12to28_12), .out_a(a28_12to28_13), .out_b(b28_12to29_12), .out_c(matrixC28_12)); +processing_element pe28_13(.reset(effective_rst), .clk(clk), .in_a(a28_12to28_13), .in_b(b27_13to28_13), .out_a(a28_13to28_14), .out_b(b28_13to29_13), .out_c(matrixC28_13)); +processing_element pe28_14(.reset(effective_rst), .clk(clk), .in_a(a28_13to28_14), .in_b(b27_14to28_14), .out_a(a28_14to28_15), .out_b(b28_14to29_14), .out_c(matrixC28_14)); +processing_element pe28_15(.reset(effective_rst), .clk(clk), .in_a(a28_14to28_15), .in_b(b27_15to28_15), .out_a(a28_15to28_16), .out_b(b28_15to29_15), .out_c(matrixC28_15)); +processing_element pe28_16(.reset(effective_rst), .clk(clk), .in_a(a28_15to28_16), .in_b(b27_16to28_16), .out_a(a28_16to28_17), .out_b(b28_16to29_16), .out_c(matrixC28_16)); +processing_element pe28_17(.reset(effective_rst), .clk(clk), .in_a(a28_16to28_17), .in_b(b27_17to28_17), .out_a(a28_17to28_18), .out_b(b28_17to29_17), .out_c(matrixC28_17)); +processing_element pe28_18(.reset(effective_rst), .clk(clk), .in_a(a28_17to28_18), .in_b(b27_18to28_18), .out_a(a28_18to28_19), .out_b(b28_18to29_18), .out_c(matrixC28_18)); +processing_element pe28_19(.reset(effective_rst), .clk(clk), .in_a(a28_18to28_19), .in_b(b27_19to28_19), .out_a(a28_19to28_20), .out_b(b28_19to29_19), .out_c(matrixC28_19)); +processing_element pe28_20(.reset(effective_rst), .clk(clk), .in_a(a28_19to28_20), .in_b(b27_20to28_20), .out_a(a28_20to28_21), .out_b(b28_20to29_20), .out_c(matrixC28_20)); +processing_element pe28_21(.reset(effective_rst), .clk(clk), .in_a(a28_20to28_21), .in_b(b27_21to28_21), .out_a(a28_21to28_22), .out_b(b28_21to29_21), .out_c(matrixC28_21)); +processing_element pe28_22(.reset(effective_rst), .clk(clk), .in_a(a28_21to28_22), .in_b(b27_22to28_22), .out_a(a28_22to28_23), .out_b(b28_22to29_22), .out_c(matrixC28_22)); +processing_element pe28_23(.reset(effective_rst), .clk(clk), .in_a(a28_22to28_23), .in_b(b27_23to28_23), .out_a(a28_23to28_24), .out_b(b28_23to29_23), .out_c(matrixC28_23)); +processing_element pe28_24(.reset(effective_rst), .clk(clk), .in_a(a28_23to28_24), .in_b(b27_24to28_24), .out_a(a28_24to28_25), .out_b(b28_24to29_24), .out_c(matrixC28_24)); +processing_element pe28_25(.reset(effective_rst), .clk(clk), .in_a(a28_24to28_25), .in_b(b27_25to28_25), .out_a(a28_25to28_26), .out_b(b28_25to29_25), .out_c(matrixC28_25)); +processing_element pe28_26(.reset(effective_rst), .clk(clk), .in_a(a28_25to28_26), .in_b(b27_26to28_26), .out_a(a28_26to28_27), .out_b(b28_26to29_26), .out_c(matrixC28_26)); +processing_element pe28_27(.reset(effective_rst), .clk(clk), .in_a(a28_26to28_27), .in_b(b27_27to28_27), .out_a(a28_27to28_28), .out_b(b28_27to29_27), .out_c(matrixC28_27)); +processing_element pe28_28(.reset(effective_rst), .clk(clk), .in_a(a28_27to28_28), .in_b(b27_28to28_28), .out_a(a28_28to28_29), .out_b(b28_28to29_28), .out_c(matrixC28_28)); +processing_element pe28_29(.reset(effective_rst), .clk(clk), .in_a(a28_28to28_29), .in_b(b27_29to28_29), .out_a(a28_29to28_30), .out_b(b28_29to29_29), .out_c(matrixC28_29)); +processing_element pe28_30(.reset(effective_rst), .clk(clk), .in_a(a28_29to28_30), .in_b(b27_30to28_30), .out_a(a28_30to28_31), .out_b(b28_30to29_30), .out_c(matrixC28_30)); +processing_element pe28_31(.reset(effective_rst), .clk(clk), .in_a(a28_30to28_31), .in_b(b27_31to28_31), .out_a(a28_31to28_32), .out_b(b28_31to29_31), .out_c(matrixC28_31)); +processing_element pe29_1(.reset(effective_rst), .clk(clk), .in_a(a29_0to29_1), .in_b(b28_1to29_1), .out_a(a29_1to29_2), .out_b(b29_1to30_1), .out_c(matrixC29_1)); +processing_element pe29_2(.reset(effective_rst), .clk(clk), .in_a(a29_1to29_2), .in_b(b28_2to29_2), .out_a(a29_2to29_3), .out_b(b29_2to30_2), .out_c(matrixC29_2)); +processing_element pe29_3(.reset(effective_rst), .clk(clk), .in_a(a29_2to29_3), .in_b(b28_3to29_3), .out_a(a29_3to29_4), .out_b(b29_3to30_3), .out_c(matrixC29_3)); +processing_element pe29_4(.reset(effective_rst), .clk(clk), .in_a(a29_3to29_4), .in_b(b28_4to29_4), .out_a(a29_4to29_5), .out_b(b29_4to30_4), .out_c(matrixC29_4)); +processing_element pe29_5(.reset(effective_rst), .clk(clk), .in_a(a29_4to29_5), .in_b(b28_5to29_5), .out_a(a29_5to29_6), .out_b(b29_5to30_5), .out_c(matrixC29_5)); +processing_element pe29_6(.reset(effective_rst), .clk(clk), .in_a(a29_5to29_6), .in_b(b28_6to29_6), .out_a(a29_6to29_7), .out_b(b29_6to30_6), .out_c(matrixC29_6)); +processing_element pe29_7(.reset(effective_rst), .clk(clk), .in_a(a29_6to29_7), .in_b(b28_7to29_7), .out_a(a29_7to29_8), .out_b(b29_7to30_7), .out_c(matrixC29_7)); +processing_element pe29_8(.reset(effective_rst), .clk(clk), .in_a(a29_7to29_8), .in_b(b28_8to29_8), .out_a(a29_8to29_9), .out_b(b29_8to30_8), .out_c(matrixC29_8)); +processing_element pe29_9(.reset(effective_rst), .clk(clk), .in_a(a29_8to29_9), .in_b(b28_9to29_9), .out_a(a29_9to29_10), .out_b(b29_9to30_9), .out_c(matrixC29_9)); +processing_element pe29_10(.reset(effective_rst), .clk(clk), .in_a(a29_9to29_10), .in_b(b28_10to29_10), .out_a(a29_10to29_11), .out_b(b29_10to30_10), .out_c(matrixC29_10)); +processing_element pe29_11(.reset(effective_rst), .clk(clk), .in_a(a29_10to29_11), .in_b(b28_11to29_11), .out_a(a29_11to29_12), .out_b(b29_11to30_11), .out_c(matrixC29_11)); +processing_element pe29_12(.reset(effective_rst), .clk(clk), .in_a(a29_11to29_12), .in_b(b28_12to29_12), .out_a(a29_12to29_13), .out_b(b29_12to30_12), .out_c(matrixC29_12)); +processing_element pe29_13(.reset(effective_rst), .clk(clk), .in_a(a29_12to29_13), .in_b(b28_13to29_13), .out_a(a29_13to29_14), .out_b(b29_13to30_13), .out_c(matrixC29_13)); +processing_element pe29_14(.reset(effective_rst), .clk(clk), .in_a(a29_13to29_14), .in_b(b28_14to29_14), .out_a(a29_14to29_15), .out_b(b29_14to30_14), .out_c(matrixC29_14)); +processing_element pe29_15(.reset(effective_rst), .clk(clk), .in_a(a29_14to29_15), .in_b(b28_15to29_15), .out_a(a29_15to29_16), .out_b(b29_15to30_15), .out_c(matrixC29_15)); +processing_element pe29_16(.reset(effective_rst), .clk(clk), .in_a(a29_15to29_16), .in_b(b28_16to29_16), .out_a(a29_16to29_17), .out_b(b29_16to30_16), .out_c(matrixC29_16)); +processing_element pe29_17(.reset(effective_rst), .clk(clk), .in_a(a29_16to29_17), .in_b(b28_17to29_17), .out_a(a29_17to29_18), .out_b(b29_17to30_17), .out_c(matrixC29_17)); +processing_element pe29_18(.reset(effective_rst), .clk(clk), .in_a(a29_17to29_18), .in_b(b28_18to29_18), .out_a(a29_18to29_19), .out_b(b29_18to30_18), .out_c(matrixC29_18)); +processing_element pe29_19(.reset(effective_rst), .clk(clk), .in_a(a29_18to29_19), .in_b(b28_19to29_19), .out_a(a29_19to29_20), .out_b(b29_19to30_19), .out_c(matrixC29_19)); +processing_element pe29_20(.reset(effective_rst), .clk(clk), .in_a(a29_19to29_20), .in_b(b28_20to29_20), .out_a(a29_20to29_21), .out_b(b29_20to30_20), .out_c(matrixC29_20)); +processing_element pe29_21(.reset(effective_rst), .clk(clk), .in_a(a29_20to29_21), .in_b(b28_21to29_21), .out_a(a29_21to29_22), .out_b(b29_21to30_21), .out_c(matrixC29_21)); +processing_element pe29_22(.reset(effective_rst), .clk(clk), .in_a(a29_21to29_22), .in_b(b28_22to29_22), .out_a(a29_22to29_23), .out_b(b29_22to30_22), .out_c(matrixC29_22)); +processing_element pe29_23(.reset(effective_rst), .clk(clk), .in_a(a29_22to29_23), .in_b(b28_23to29_23), .out_a(a29_23to29_24), .out_b(b29_23to30_23), .out_c(matrixC29_23)); +processing_element pe29_24(.reset(effective_rst), .clk(clk), .in_a(a29_23to29_24), .in_b(b28_24to29_24), .out_a(a29_24to29_25), .out_b(b29_24to30_24), .out_c(matrixC29_24)); +processing_element pe29_25(.reset(effective_rst), .clk(clk), .in_a(a29_24to29_25), .in_b(b28_25to29_25), .out_a(a29_25to29_26), .out_b(b29_25to30_25), .out_c(matrixC29_25)); +processing_element pe29_26(.reset(effective_rst), .clk(clk), .in_a(a29_25to29_26), .in_b(b28_26to29_26), .out_a(a29_26to29_27), .out_b(b29_26to30_26), .out_c(matrixC29_26)); +processing_element pe29_27(.reset(effective_rst), .clk(clk), .in_a(a29_26to29_27), .in_b(b28_27to29_27), .out_a(a29_27to29_28), .out_b(b29_27to30_27), .out_c(matrixC29_27)); +processing_element pe29_28(.reset(effective_rst), .clk(clk), .in_a(a29_27to29_28), .in_b(b28_28to29_28), .out_a(a29_28to29_29), .out_b(b29_28to30_28), .out_c(matrixC29_28)); +processing_element pe29_29(.reset(effective_rst), .clk(clk), .in_a(a29_28to29_29), .in_b(b28_29to29_29), .out_a(a29_29to29_30), .out_b(b29_29to30_29), .out_c(matrixC29_29)); +processing_element pe29_30(.reset(effective_rst), .clk(clk), .in_a(a29_29to29_30), .in_b(b28_30to29_30), .out_a(a29_30to29_31), .out_b(b29_30to30_30), .out_c(matrixC29_30)); +processing_element pe29_31(.reset(effective_rst), .clk(clk), .in_a(a29_30to29_31), .in_b(b28_31to29_31), .out_a(a29_31to29_32), .out_b(b29_31to30_31), .out_c(matrixC29_31)); +processing_element pe30_1(.reset(effective_rst), .clk(clk), .in_a(a30_0to30_1), .in_b(b29_1to30_1), .out_a(a30_1to30_2), .out_b(b30_1to31_1), .out_c(matrixC30_1)); +processing_element pe30_2(.reset(effective_rst), .clk(clk), .in_a(a30_1to30_2), .in_b(b29_2to30_2), .out_a(a30_2to30_3), .out_b(b30_2to31_2), .out_c(matrixC30_2)); +processing_element pe30_3(.reset(effective_rst), .clk(clk), .in_a(a30_2to30_3), .in_b(b29_3to30_3), .out_a(a30_3to30_4), .out_b(b30_3to31_3), .out_c(matrixC30_3)); +processing_element pe30_4(.reset(effective_rst), .clk(clk), .in_a(a30_3to30_4), .in_b(b29_4to30_4), .out_a(a30_4to30_5), .out_b(b30_4to31_4), .out_c(matrixC30_4)); +processing_element pe30_5(.reset(effective_rst), .clk(clk), .in_a(a30_4to30_5), .in_b(b29_5to30_5), .out_a(a30_5to30_6), .out_b(b30_5to31_5), .out_c(matrixC30_5)); +processing_element pe30_6(.reset(effective_rst), .clk(clk), .in_a(a30_5to30_6), .in_b(b29_6to30_6), .out_a(a30_6to30_7), .out_b(b30_6to31_6), .out_c(matrixC30_6)); +processing_element pe30_7(.reset(effective_rst), .clk(clk), .in_a(a30_6to30_7), .in_b(b29_7to30_7), .out_a(a30_7to30_8), .out_b(b30_7to31_7), .out_c(matrixC30_7)); +processing_element pe30_8(.reset(effective_rst), .clk(clk), .in_a(a30_7to30_8), .in_b(b29_8to30_8), .out_a(a30_8to30_9), .out_b(b30_8to31_8), .out_c(matrixC30_8)); +processing_element pe30_9(.reset(effective_rst), .clk(clk), .in_a(a30_8to30_9), .in_b(b29_9to30_9), .out_a(a30_9to30_10), .out_b(b30_9to31_9), .out_c(matrixC30_9)); +processing_element pe30_10(.reset(effective_rst), .clk(clk), .in_a(a30_9to30_10), .in_b(b29_10to30_10), .out_a(a30_10to30_11), .out_b(b30_10to31_10), .out_c(matrixC30_10)); +processing_element pe30_11(.reset(effective_rst), .clk(clk), .in_a(a30_10to30_11), .in_b(b29_11to30_11), .out_a(a30_11to30_12), .out_b(b30_11to31_11), .out_c(matrixC30_11)); +processing_element pe30_12(.reset(effective_rst), .clk(clk), .in_a(a30_11to30_12), .in_b(b29_12to30_12), .out_a(a30_12to30_13), .out_b(b30_12to31_12), .out_c(matrixC30_12)); +processing_element pe30_13(.reset(effective_rst), .clk(clk), .in_a(a30_12to30_13), .in_b(b29_13to30_13), .out_a(a30_13to30_14), .out_b(b30_13to31_13), .out_c(matrixC30_13)); +processing_element pe30_14(.reset(effective_rst), .clk(clk), .in_a(a30_13to30_14), .in_b(b29_14to30_14), .out_a(a30_14to30_15), .out_b(b30_14to31_14), .out_c(matrixC30_14)); +processing_element pe30_15(.reset(effective_rst), .clk(clk), .in_a(a30_14to30_15), .in_b(b29_15to30_15), .out_a(a30_15to30_16), .out_b(b30_15to31_15), .out_c(matrixC30_15)); +processing_element pe30_16(.reset(effective_rst), .clk(clk), .in_a(a30_15to30_16), .in_b(b29_16to30_16), .out_a(a30_16to30_17), .out_b(b30_16to31_16), .out_c(matrixC30_16)); +processing_element pe30_17(.reset(effective_rst), .clk(clk), .in_a(a30_16to30_17), .in_b(b29_17to30_17), .out_a(a30_17to30_18), .out_b(b30_17to31_17), .out_c(matrixC30_17)); +processing_element pe30_18(.reset(effective_rst), .clk(clk), .in_a(a30_17to30_18), .in_b(b29_18to30_18), .out_a(a30_18to30_19), .out_b(b30_18to31_18), .out_c(matrixC30_18)); +processing_element pe30_19(.reset(effective_rst), .clk(clk), .in_a(a30_18to30_19), .in_b(b29_19to30_19), .out_a(a30_19to30_20), .out_b(b30_19to31_19), .out_c(matrixC30_19)); +processing_element pe30_20(.reset(effective_rst), .clk(clk), .in_a(a30_19to30_20), .in_b(b29_20to30_20), .out_a(a30_20to30_21), .out_b(b30_20to31_20), .out_c(matrixC30_20)); +processing_element pe30_21(.reset(effective_rst), .clk(clk), .in_a(a30_20to30_21), .in_b(b29_21to30_21), .out_a(a30_21to30_22), .out_b(b30_21to31_21), .out_c(matrixC30_21)); +processing_element pe30_22(.reset(effective_rst), .clk(clk), .in_a(a30_21to30_22), .in_b(b29_22to30_22), .out_a(a30_22to30_23), .out_b(b30_22to31_22), .out_c(matrixC30_22)); +processing_element pe30_23(.reset(effective_rst), .clk(clk), .in_a(a30_22to30_23), .in_b(b29_23to30_23), .out_a(a30_23to30_24), .out_b(b30_23to31_23), .out_c(matrixC30_23)); +processing_element pe30_24(.reset(effective_rst), .clk(clk), .in_a(a30_23to30_24), .in_b(b29_24to30_24), .out_a(a30_24to30_25), .out_b(b30_24to31_24), .out_c(matrixC30_24)); +processing_element pe30_25(.reset(effective_rst), .clk(clk), .in_a(a30_24to30_25), .in_b(b29_25to30_25), .out_a(a30_25to30_26), .out_b(b30_25to31_25), .out_c(matrixC30_25)); +processing_element pe30_26(.reset(effective_rst), .clk(clk), .in_a(a30_25to30_26), .in_b(b29_26to30_26), .out_a(a30_26to30_27), .out_b(b30_26to31_26), .out_c(matrixC30_26)); +processing_element pe30_27(.reset(effective_rst), .clk(clk), .in_a(a30_26to30_27), .in_b(b29_27to30_27), .out_a(a30_27to30_28), .out_b(b30_27to31_27), .out_c(matrixC30_27)); +processing_element pe30_28(.reset(effective_rst), .clk(clk), .in_a(a30_27to30_28), .in_b(b29_28to30_28), .out_a(a30_28to30_29), .out_b(b30_28to31_28), .out_c(matrixC30_28)); +processing_element pe30_29(.reset(effective_rst), .clk(clk), .in_a(a30_28to30_29), .in_b(b29_29to30_29), .out_a(a30_29to30_30), .out_b(b30_29to31_29), .out_c(matrixC30_29)); +processing_element pe30_30(.reset(effective_rst), .clk(clk), .in_a(a30_29to30_30), .in_b(b29_30to30_30), .out_a(a30_30to30_31), .out_b(b30_30to31_30), .out_c(matrixC30_30)); +processing_element pe30_31(.reset(effective_rst), .clk(clk), .in_a(a30_30to30_31), .in_b(b29_31to30_31), .out_a(a30_31to30_32), .out_b(b30_31to31_31), .out_c(matrixC30_31)); +processing_element pe31_1(.reset(effective_rst), .clk(clk), .in_a(a31_0to31_1), .in_b(b30_1to31_1), .out_a(a31_1to31_2), .out_b(b31_1to32_1), .out_c(matrixC31_1)); +processing_element pe31_2(.reset(effective_rst), .clk(clk), .in_a(a31_1to31_2), .in_b(b30_2to31_2), .out_a(a31_2to31_3), .out_b(b31_2to32_2), .out_c(matrixC31_2)); +processing_element pe31_3(.reset(effective_rst), .clk(clk), .in_a(a31_2to31_3), .in_b(b30_3to31_3), .out_a(a31_3to31_4), .out_b(b31_3to32_3), .out_c(matrixC31_3)); +processing_element pe31_4(.reset(effective_rst), .clk(clk), .in_a(a31_3to31_4), .in_b(b30_4to31_4), .out_a(a31_4to31_5), .out_b(b31_4to32_4), .out_c(matrixC31_4)); +processing_element pe31_5(.reset(effective_rst), .clk(clk), .in_a(a31_4to31_5), .in_b(b30_5to31_5), .out_a(a31_5to31_6), .out_b(b31_5to32_5), .out_c(matrixC31_5)); +processing_element pe31_6(.reset(effective_rst), .clk(clk), .in_a(a31_5to31_6), .in_b(b30_6to31_6), .out_a(a31_6to31_7), .out_b(b31_6to32_6), .out_c(matrixC31_6)); +processing_element pe31_7(.reset(effective_rst), .clk(clk), .in_a(a31_6to31_7), .in_b(b30_7to31_7), .out_a(a31_7to31_8), .out_b(b31_7to32_7), .out_c(matrixC31_7)); +processing_element pe31_8(.reset(effective_rst), .clk(clk), .in_a(a31_7to31_8), .in_b(b30_8to31_8), .out_a(a31_8to31_9), .out_b(b31_8to32_8), .out_c(matrixC31_8)); +processing_element pe31_9(.reset(effective_rst), .clk(clk), .in_a(a31_8to31_9), .in_b(b30_9to31_9), .out_a(a31_9to31_10), .out_b(b31_9to32_9), .out_c(matrixC31_9)); +processing_element pe31_10(.reset(effective_rst), .clk(clk), .in_a(a31_9to31_10), .in_b(b30_10to31_10), .out_a(a31_10to31_11), .out_b(b31_10to32_10), .out_c(matrixC31_10)); +processing_element pe31_11(.reset(effective_rst), .clk(clk), .in_a(a31_10to31_11), .in_b(b30_11to31_11), .out_a(a31_11to31_12), .out_b(b31_11to32_11), .out_c(matrixC31_11)); +processing_element pe31_12(.reset(effective_rst), .clk(clk), .in_a(a31_11to31_12), .in_b(b30_12to31_12), .out_a(a31_12to31_13), .out_b(b31_12to32_12), .out_c(matrixC31_12)); +processing_element pe31_13(.reset(effective_rst), .clk(clk), .in_a(a31_12to31_13), .in_b(b30_13to31_13), .out_a(a31_13to31_14), .out_b(b31_13to32_13), .out_c(matrixC31_13)); +processing_element pe31_14(.reset(effective_rst), .clk(clk), .in_a(a31_13to31_14), .in_b(b30_14to31_14), .out_a(a31_14to31_15), .out_b(b31_14to32_14), .out_c(matrixC31_14)); +processing_element pe31_15(.reset(effective_rst), .clk(clk), .in_a(a31_14to31_15), .in_b(b30_15to31_15), .out_a(a31_15to31_16), .out_b(b31_15to32_15), .out_c(matrixC31_15)); +processing_element pe31_16(.reset(effective_rst), .clk(clk), .in_a(a31_15to31_16), .in_b(b30_16to31_16), .out_a(a31_16to31_17), .out_b(b31_16to32_16), .out_c(matrixC31_16)); +processing_element pe31_17(.reset(effective_rst), .clk(clk), .in_a(a31_16to31_17), .in_b(b30_17to31_17), .out_a(a31_17to31_18), .out_b(b31_17to32_17), .out_c(matrixC31_17)); +processing_element pe31_18(.reset(effective_rst), .clk(clk), .in_a(a31_17to31_18), .in_b(b30_18to31_18), .out_a(a31_18to31_19), .out_b(b31_18to32_18), .out_c(matrixC31_18)); +processing_element pe31_19(.reset(effective_rst), .clk(clk), .in_a(a31_18to31_19), .in_b(b30_19to31_19), .out_a(a31_19to31_20), .out_b(b31_19to32_19), .out_c(matrixC31_19)); +processing_element pe31_20(.reset(effective_rst), .clk(clk), .in_a(a31_19to31_20), .in_b(b30_20to31_20), .out_a(a31_20to31_21), .out_b(b31_20to32_20), .out_c(matrixC31_20)); +processing_element pe31_21(.reset(effective_rst), .clk(clk), .in_a(a31_20to31_21), .in_b(b30_21to31_21), .out_a(a31_21to31_22), .out_b(b31_21to32_21), .out_c(matrixC31_21)); +processing_element pe31_22(.reset(effective_rst), .clk(clk), .in_a(a31_21to31_22), .in_b(b30_22to31_22), .out_a(a31_22to31_23), .out_b(b31_22to32_22), .out_c(matrixC31_22)); +processing_element pe31_23(.reset(effective_rst), .clk(clk), .in_a(a31_22to31_23), .in_b(b30_23to31_23), .out_a(a31_23to31_24), .out_b(b31_23to32_23), .out_c(matrixC31_23)); +processing_element pe31_24(.reset(effective_rst), .clk(clk), .in_a(a31_23to31_24), .in_b(b30_24to31_24), .out_a(a31_24to31_25), .out_b(b31_24to32_24), .out_c(matrixC31_24)); +processing_element pe31_25(.reset(effective_rst), .clk(clk), .in_a(a31_24to31_25), .in_b(b30_25to31_25), .out_a(a31_25to31_26), .out_b(b31_25to32_25), .out_c(matrixC31_25)); +processing_element pe31_26(.reset(effective_rst), .clk(clk), .in_a(a31_25to31_26), .in_b(b30_26to31_26), .out_a(a31_26to31_27), .out_b(b31_26to32_26), .out_c(matrixC31_26)); +processing_element pe31_27(.reset(effective_rst), .clk(clk), .in_a(a31_26to31_27), .in_b(b30_27to31_27), .out_a(a31_27to31_28), .out_b(b31_27to32_27), .out_c(matrixC31_27)); +processing_element pe31_28(.reset(effective_rst), .clk(clk), .in_a(a31_27to31_28), .in_b(b30_28to31_28), .out_a(a31_28to31_29), .out_b(b31_28to32_28), .out_c(matrixC31_28)); +processing_element pe31_29(.reset(effective_rst), .clk(clk), .in_a(a31_28to31_29), .in_b(b30_29to31_29), .out_a(a31_29to31_30), .out_b(b31_29to32_29), .out_c(matrixC31_29)); +processing_element pe31_30(.reset(effective_rst), .clk(clk), .in_a(a31_29to31_30), .in_b(b30_30to31_30), .out_a(a31_30to31_31), .out_b(b31_30to32_30), .out_c(matrixC31_30)); +processing_element pe31_31(.reset(effective_rst), .clk(clk), .in_a(a31_30to31_31), .in_b(b30_31to31_31), .out_a(a31_31to31_32), .out_b(b31_31to32_31), .out_c(matrixC31_31)); +assign a_data_out = {a31_31to31_32,a30_31to30_32,a29_31to29_32,a28_31to28_32,a27_31to27_32,a26_31to26_32,a25_31to25_32,a24_31to24_32,a23_31to23_32,a22_31to22_32,a21_31to21_32,a20_31to20_32,a19_31to19_32,a18_31to18_32,a17_31to17_32,a16_31to16_32,a15_31to15_32,a14_31to14_32,a13_31to13_32,a12_31to12_32,a11_31to11_32,a10_31to10_32,a9_31to9_32,a8_31to8_32,a7_31to7_32,a6_31to6_32,a5_31to5_32,a4_31to4_32,a3_31to3_32,a2_31to2_32,a1_31to1_32,a0_31to0_32}; +assign b_data_out = {b31_31to32_31,b31_30to32_30,b31_29to32_29,b31_28to32_28,b31_27to32_27,b31_26to32_26,b31_25to32_25,b31_24to32_24,b31_23to32_23,b31_22to32_22,b31_21to32_21,b31_20to32_20,b31_19to32_19,b31_18to32_18,b31_17to32_17,b31_16to32_16,b31_15to32_15,b31_14to32_14,b31_13to32_13,b31_12to32_12,b31_11to32_11,b31_10to32_10,b31_9to32_9,b31_8to32_8,b31_7to32_7,b31_6to32_6,b31_5to32_5,b31_4to32_4,b31_3to32_3,b31_2to32_2,b31_1to32_1,b31_0to32_0}; + +endmodule + +module processing_element( + reset, + clk, + in_a, + in_b, + out_a, + out_b, + out_c + ); + + input reset; + input clk; + input [`DWIDTH-1:0] in_a; + input [`DWIDTH-1:0] in_b; + output [`DWIDTH-1:0] out_a; + output [`DWIDTH-1:0] out_b; + output [`DWIDTH-1:0] out_c; //reduced precision + + reg [`DWIDTH-1:0] out_a; + reg [`DWIDTH-1:0] out_b; + wire [`DWIDTH-1:0] out_c; + + wire [`DWIDTH-1:0] out_mac; + + assign out_c = out_mac; + + seq_mac u_mac(.a(in_a), .b(in_b), .out(out_mac), .reset(reset), .clk(clk)); + + always @(posedge clk)begin + if(reset) begin + out_a<=0; + out_b<=0; + end + else begin + out_a<=in_a; + out_b<=in_b; + end + end + +endmodule + +module seq_mac(a, b, out, reset, clk); +input [`DWIDTH-1:0] a; +input [`DWIDTH-1:0] b; +input reset; +input clk; +output [`DWIDTH-1:0] out; + +reg [2*`DWIDTH-1:0] out_temp; +wire [`DWIDTH-1:0] mul_out; +wire [2*`DWIDTH-1:0] add_out; + +reg [`DWIDTH-1:0] a_flopped; +reg [`DWIDTH-1:0] b_flopped; + +wire [2*`DWIDTH-1:0] mul_out_temp; +reg [2*`DWIDTH-1:0] mul_out_temp_reg; + +always @(posedge clk) begin + if (reset) begin + a_flopped <= 0; + b_flopped <= 0; + end else begin + a_flopped <= a; + b_flopped <= b; + end +end + +//assign mul_out = a * b; +qmult mult_u1(.i_multiplicand(a_flopped), .i_multiplier(b_flopped), .o_result(mul_out_temp)); + +always @(posedge clk) begin + if (reset) begin + mul_out_temp_reg <= 0; + end else begin + mul_out_temp_reg <= mul_out_temp; + end +end + +//we just truncate the higher bits of the product +//assign add_out = mul_out + out; +qadd add_u1(.a(out_temp), .b(mul_out_temp_reg), .c(add_out)); + +always @(posedge clk) begin + if (reset) begin + out_temp <= 0; + end else begin + out_temp <= add_out; + end +end + +//down cast the result +assign out = + (out_temp[2*`DWIDTH-1] == 0) ? //positive number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 1, that means overlfow + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b1}}} : //sign bit and then all 1s + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} + ) + : //negative number + ( + (|(out_temp[2*`DWIDTH-2 : `DWIDTH-1])) ? //is any bit from 14:7 is 0, that means overlfow + {out_temp[2*`DWIDTH-1] , out_temp[`DWIDTH-2:0]} : + {out_temp[2*`DWIDTH-1] , {(`DWIDTH-1){1'b0}}} //sign bit and then all 0s + ); + +endmodule + +module qmult(i_multiplicand,i_multiplier,o_result); +input [`DWIDTH-1:0] i_multiplicand; +input [`DWIDTH-1:0] i_multiplier; +output [2*`DWIDTH-1:0] o_result; + +assign o_result = i_multiplicand * i_multiplier; +//DW02_mult #(`DWIDTH,`DWIDTH) u_mult(.A(i_multiplicand), .B(i_multiplier), .TC(1'b1), .PRODUCT(o_result)); + +endmodule + +module qadd(a,b,c); +input [2*`DWIDTH-1:0] a; +input [2*`DWIDTH-1:0] b; +output [2*`DWIDTH-1:0] c; + +assign c = a + b; +//DW01_add #(`DWIDTH) u_add(.A(a), .B(b), .CI(1'b0), .SUM(c), .CO()); +endmodule + + +////////////////////////////////////////////// +// Configuration block +////////////////////////////////////////////// + +module cfg( + input PCLK, + input PRESETn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output reg [`REG_DATAWIDTH-1:0] PRDATA, + output reg PREADY, + output reg start_tpu, + output reg enable_matmul, + output reg enable_norm, + output reg enable_pool, + output reg enable_activation, + output reg enable_conv_mode, + output reg [`DWIDTH-1:0] mean, + output reg [`DWIDTH-1:0] inv_var, + output reg [`MAX_BITS_POOL-1:0] pool_window_size, + output reg [`AWIDTH-1:0] address_mat_a, + output reg [`AWIDTH-1:0] address_mat_b, + output reg [`AWIDTH-1:0] address_mat_c, + output reg [`MASK_WIDTH-1:0] validity_mask_a_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_a_cols, + output reg [`MASK_WIDTH-1:0] validity_mask_b_rows, + output reg [`MASK_WIDTH-1:0] validity_mask_b_cols, + output reg save_output_to_accum, + output reg add_accum_to_output, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_a, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_b, + output reg [`ADDR_STRIDE_WIDTH-1:0] address_stride_c, + output reg activation_type, + output reg [3:0] conv_filter_height, + output reg [3:0] conv_filter_width, + output reg [3:0] conv_stride_horiz, + output reg [3:0] conv_stride_verti, + output reg [3:0] conv_padding_left, + output reg [3:0] conv_padding_right, + output reg [3:0] conv_padding_top, + output reg [3:0] conv_padding_bottom, + output reg [15:0] num_channels_inp, + output reg [15:0] num_channels_out, + output reg [15:0] inp_img_height, + output reg [15:0] inp_img_width, + output reg [15:0] out_img_height, + output reg [15:0] out_img_width, + output reg [31:0] batch_size, + output reg pe_reset, + input done_tpu +); + +//Dummy register to sync all other invalid/unimplemented addresses +reg [`REG_DATAWIDTH-1:0] reg_dummy; + + +////////////////////////////////////////////////////// +//Using a simple APB interface. Taken from: +// https://github.com/maomran/APB-Slave +// https://research.ijcaonline.org/volume95/number21/pxc3897047.pdf + +reg [1:0] State; +`define IDLE 2'b00 +`define W_ENABLE 2'b01 +`define R_ENABLE 2'b10 + +always @(posedge PCLK) begin + if (PRESETn == 0) begin + State <= `IDLE; + PRDATA <= 0; + PREADY <= 0; + start_tpu <= 0; + enable_matmul <= 0; + enable_norm <= 0; + enable_pool <= 0; + enable_activation <= 0; + mean <= 0; + inv_var <= 0; + pool_window_size <= 1; + reg_dummy <= 0; + address_mat_a <= 0; + address_mat_b <= 0; + address_mat_c <= 0; + validity_mask_a_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_a_cols <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_rows <= {`MASK_WIDTH{1'b1}}; + validity_mask_b_cols <= {`MASK_WIDTH{1'b1}}; + save_output_to_accum <= 0; + add_accum_to_output <= 0; + address_stride_a <= `DESIGN_SIZE; + address_stride_b <= `DESIGN_SIZE; + address_stride_c <= `DESIGN_SIZE; + activation_type <= 1; + conv_filter_height <= 2; + conv_filter_width <= 2; + conv_stride_horiz <= 1; + conv_stride_verti <= 1; + conv_padding_left <= 0; + conv_padding_right <= 0; + conv_padding_top <= 0; + conv_padding_bottom<= 0; + num_channels_inp <= 4; + num_channels_out <= 4; + inp_img_height <= 8; + inp_img_width <= 8; + out_img_height <= 7; + out_img_width <= 7; + batch_size <= 2; + enable_conv_mode <= 0; + pe_reset <= 0; + end + + else begin + case (State) + `IDLE : begin + PRDATA <= 0; + if (PSEL) begin + if (PWRITE) begin + State <= `W_ENABLE; + end + else begin + State <= `R_ENABLE; + end + end + PREADY <= 0; + pe_reset <= 0; //this register bit auto resets itself + end + + `W_ENABLE : begin + if (PSEL && PWRITE && PENABLE) begin + case (PADDR) + `REG_ENABLES_ADDR : begin + enable_conv_mode <= PWDATA[31]; + enable_activation <= PWDATA[3]; + enable_pool <= PWDATA[2]; + enable_norm <= PWDATA[1]; + enable_matmul <= PWDATA[0]; + end + `REG_STDN_TPU_ADDR : begin + start_tpu <= PWDATA[0]; + pe_reset <= PWDATA[15]; + end + `REG_MEAN_ADDR : mean <= PWDATA[`DWIDTH-1:0]; + `REG_INV_VAR_ADDR : inv_var <= PWDATA[`DWIDTH-1:0]; + `REG_MATRIX_A_ADDR : address_mat_a <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_B_ADDR : address_mat_b <= PWDATA[`AWIDTH-1:0]; + `REG_MATRIX_C_ADDR : address_mat_c <= PWDATA[`AWIDTH-1:0]; + `REG_VALID_MASK_A_ROWS_ADDR: begin + validity_mask_a_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_A_COLS_ADDR: begin + validity_mask_a_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_ROWS_ADDR: begin + validity_mask_b_rows <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_VALID_MASK_B_COLS_ADDR: begin + validity_mask_b_cols <= PWDATA[`MASK_WIDTH-1:0]; + end + `REG_POOL_WINDOW_ADDR: pool_window_size <= PWDATA[`MAX_BITS_POOL-1:0]; + `REG_ACCUM_ACTIONS_ADDR: begin + add_accum_to_output <= PWDATA[1]; + save_output_to_accum <= PWDATA[0]; + end + `REG_MATRIX_A_STRIDE_ADDR : address_stride_a <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_B_STRIDE_ADDR : address_stride_b <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_MATRIX_C_STRIDE_ADDR : address_stride_c <= PWDATA[`ADDR_STRIDE_WIDTH-1:0]; + `REG_ACTIVATION_CSR_ADDR : activation_type <= PWDATA[0]; + `REG_CONV_PARAMS_1_ADDR : begin + conv_filter_height <= PWDATA[3:0]; + conv_filter_width <= PWDATA[7:4]; + conv_stride_horiz <= PWDATA[11:8]; + conv_stride_verti <= PWDATA[15:12]; + conv_padding_left <= PWDATA[19:16]; + conv_padding_right <= PWDATA[23:20]; + conv_padding_top <= PWDATA[27:24]; + conv_padding_bottom<= PWDATA[31:28]; + end + `REG_CONV_PARAMS_2_ADDR : begin + num_channels_inp <= PWDATA[15:0]; + num_channels_out <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_3_ADDR : begin + inp_img_height <= PWDATA[15:0]; + inp_img_width <= PWDATA[31:16]; + end + `REG_CONV_PARAMS_4_ADDR : begin + out_img_height <= PWDATA[15:0]; + out_img_width <= PWDATA[31:16]; + end + `REG_BATCH_SIZE_ADDR : batch_size <= PWDATA[31:0]; + default: reg_dummy <= PWDATA; //sink writes to a dummy register + endcase + PREADY <=1; + end + State <= `IDLE; + end + + `R_ENABLE : begin + if (PSEL && !PWRITE && PENABLE) begin + PREADY <= 1; + case (PADDR) + `REG_ENABLES_ADDR : PRDATA <= {28'b0, enable_activation, enable_pool, enable_norm, enable_matmul}; + `REG_STDN_TPU_ADDR : PRDATA <= {done_tpu, 30'b0, start_tpu}; + `REG_MEAN_ADDR : PRDATA <= mean; + `REG_INV_VAR_ADDR : PRDATA <= inv_var; + `REG_MATRIX_A_ADDR : PRDATA <= address_mat_a; + `REG_MATRIX_B_ADDR : PRDATA <= address_mat_b; + `REG_MATRIX_C_ADDR : PRDATA <= address_mat_c; + `REG_VALID_MASK_A_ROWS_ADDR: PRDATA <= validity_mask_a_rows; + `REG_VALID_MASK_A_COLS_ADDR: PRDATA <= validity_mask_a_cols; + `REG_VALID_MASK_B_ROWS_ADDR: PRDATA <= validity_mask_b_rows; + `REG_VALID_MASK_B_COLS_ADDR: PRDATA <= validity_mask_b_cols; + `REG_POOL_WINDOW_ADDR : PRDATA <= pool_window_size; + `REG_ACCUM_ACTIONS_ADDR: PRDATA <= {30'b0, add_accum_to_output, save_output_to_accum}; + `REG_MATRIX_A_STRIDE_ADDR : PRDATA <= address_stride_a; + `REG_MATRIX_B_STRIDE_ADDR : PRDATA <= address_stride_b; + `REG_MATRIX_C_STRIDE_ADDR : PRDATA <= address_stride_c; + `REG_ACTIVATION_CSR_ADDR : PRDATA <= {31'b0, activation_type}; + `REG_CONV_PARAMS_1_ADDR : PRDATA <= { + conv_filter_height, + conv_filter_width, + conv_stride_horiz, + conv_stride_verti, + conv_padding_left, + conv_padding_right, + conv_padding_top, + conv_padding_bottom + }; + `REG_CONV_PARAMS_2_ADDR : PRDATA <= { + num_channels_inp, + num_channels_out + }; + `REG_CONV_PARAMS_3_ADDR : PRDATA <= { + inp_img_height, + inp_img_width + }; + `REG_CONV_PARAMS_4_ADDR : PRDATA <= { + out_img_height, + out_img_width + }; + `REG_BATCH_SIZE_ADDR : PRDATA <= batch_size; + default : PRDATA <= reg_dummy; //read the dummy register for undefined addresses + endcase + end + State <= `IDLE; + end + default: begin + State <= `IDLE; + end + endcase + end +end + +endmodule + + +//////////////////////////////////////////////// +// Normalization block +//////////////////////////////////////////////// + +module norm( + input enable_norm, + input [`DWIDTH-1:0] mean, + input [`DWIDTH-1:0] inv_var, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_norm, + input clk, + input reset +); + +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data; +reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data; +reg done_norm_internal; +reg norm_in_progress; +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +//Muxing logic to handle the case when this block is disabled +assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available_flopped; +assign out_data = (enable_norm) ? out_data_internal : inp_data_flopped; +assign done_norm = (enable_norm) ? done_norm_internal : 1'b1; + +//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul. +//on each clock edge, if in_data_available is 1, then we will normalize the inputs. + +//the code uses the funky part-select syntax. example: +//wire [7:0] byteN = word[byte_num*8 +: 8]; +//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available +//+: indicates the part-select increases from the starting point +//-: indicates the part-select decreases from the starting point +//another example: +//loc = 3; +//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4]; + +reg [31:0] cycle_count; +reg [31:0] i; +always @(posedge clk) begin + if ((reset || ~enable_norm)) begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end else if (in_data_available || norm_in_progress) begin + cycle_count = cycle_count + 1; + //Let's apply mean and variance as the input data comes in. + //We have a pipeline here. First stage does the add (to apply the mean) + //and second stage does the multiplication (to apply the variance). + //Note: the following loop is not a loop across multiple columns of data. + //This loop will run in 2 cycle on the same column of data that comes into + //this module in 1 clock. + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (validity_mask[i] == 1'b1) begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH] - mean); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var); + end + else begin + mean_applied_data[i*`DWIDTH +: `DWIDTH] <= (inp_data[i*`DWIDTH +: `DWIDTH]); + variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH]); + end + end + + //Out data is available starting with the second clock cycle because + //in the first cycle, we only apply the mean. + if(cycle_count==2) begin + out_data_available_internal <= 1; + end + + //When we've normalized values N times, where N is the matmul + //size, that means we're done. But there is one additional cycle + //that is taken in the beginning (when we are applying the mean to the first + //column of data). We can call this the Initiation Interval of the pipeline. + //So, for a 4x4 matmul, this block takes 5 cycles. + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_norm_internal <= 1'b1; + norm_in_progress <= 0; + end + else begin + norm_in_progress <= 1; + end + end + else begin + mean_applied_data <= 0; + variance_applied_data <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + done_norm_internal <= 0; + norm_in_progress <= 0; + end +end + +assign out_data_internal = variance_applied_data; + +endmodule + +////////////////////////////////// +// Dual port RAM +////////////////////////////////// + +module ram ( + addr0, + d0, + we0, + q0, + addr1, + d1, + we1, + q1, + clk); + +input [`AWIDTH-1:0] addr0; +input [`AWIDTH-1:0] addr1; +input [`DESIGN_SIZE*`DWIDTH-1:0] d0; +input [`DESIGN_SIZE*`DWIDTH-1:0] d1; +input [`DESIGN_SIZE-1:0] we0; +input [`DESIGN_SIZE-1:0] we1; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0; +output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1; +input clk; + +`ifdef SIMULATION + +reg [7:0] ram[((1<<`AWIDTH)-1):0]; +reg [31:0] i; + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q0[i*`DWIDTH +: `DWIDTH] <= ram[addr0+i]; + end +end + +always @(posedge clk) +begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH +: `DWIDTH]; + end + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + q1[i*`DWIDTH +: `DWIDTH] <= ram[addr1+i]; + end +end + +`else +//BRAMs available in VTR FPGA architectures have one bit write-enables. +//So let's combine multiple bits into 1. We don't have a usecase of +//writing/not-writing only parts of the word anyway. +wire we0_coalesced; +assign we0_coalesced = |we0; +wire we1_coalesced; +assign we1_coalesced = |we1; + +dual_port_ram u_dual_port_ram( +.addr1(addr0), +.we1(we0_coalesced), +.data1(d0), +.out1(q0), +.addr2(addr1), +.we2(we1_coalesced), +.data2(d1), +.out2(q1), +.clk(clk) +); + +`endif + + +endmodule + +//////////////////////////////////////////////// +// Control unit +//////////////////////////////////////////////// + +module control( + input clk, + input reset, + input start_tpu, + input enable_matmul, + input enable_norm, + input enable_activation, + input enable_pool, + output reg start_mat_mul, + input done_mat_mul, + input done_norm, + input done_pool, + input done_activation, + input save_output_to_accum, + output reg done_tpu +); + +reg [3:0] state; + +`define STATE_INIT 4'b0000 +`define STATE_MATMUL 4'b0001 +`define STATE_NORM 4'b0010 +`define STATE_POOL 4'b0011 +`define STATE_ACTIVATION 4'b0100 +`define STATE_DONE 4'b0101 + +////////////////////////////////////////////////////// +// Assumption: We will always run matmul first. That is, matmul is not optional. +// The other blocks - norm, act, pool - are optional. +// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation +////////////////////////////////////////////////////// + +always @( posedge clk) begin + if (reset) begin + state <= `STATE_INIT; + start_mat_mul <= 1'b0; + done_tpu <= 1'b0; + end else begin + case (state) + `STATE_INIT: begin + if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin + if (enable_matmul == 1'b1) begin + start_mat_mul <= 1'b1; + state <= `STATE_MATMUL; + end + end + end + + //start_mat_mul is kinda used as a reset in some logic + //inside the matmul unit. So, we can't make it 0 right away after + //asserting it. + `STATE_MATMUL: begin + if (done_mat_mul == 1'b1) begin + start_mat_mul <= 1'b0; + if(save_output_to_accum) begin + state <= `STATE_DONE; + end + else if (enable_norm) begin + state <= `STATE_NORM; + end + else if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + else begin + start_mat_mul <= 1'b1; + end + end + + `STATE_NORM: begin + if (done_norm == 1'b1) begin + if (enable_pool) begin + state <= `STATE_POOL; + end + else if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_POOL: begin + if (done_pool == 1'b1) begin + if (enable_activation) begin + state <= `STATE_ACTIVATION; + end + else begin + state <= `STATE_DONE; + end + end + end + + `STATE_ACTIVATION: begin + if (done_activation == 1'b1) begin + state <= `STATE_DONE; + end + end + + `STATE_DONE: begin + //We need to write start_tpu to 0 in the CFG block to get out of this state + if (start_tpu == 1'b0) begin + state <= `STATE_INIT; + done_tpu <= 0; + end + else begin + done_tpu <= 1; + end + end + endcase + end +end +endmodule + +//////////////////////////////////////////////// +// Pooling block +//////////////////////////////////////////////// + +module pool( + input enable_pool, + input in_data_available, + input [`MAX_BITS_POOL-1:0] pool_window_size, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_pool, + input clk, + input reset +); + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp; +reg done_pool_temp; +reg out_data_available_temp; +reg [31:0] i,j; +reg [31:0] cycle_count; + +always @(posedge clk) begin + if (reset || ~enable_pool || ~in_data_available) begin + out_data_temp <= 0; + done_pool_temp <= 0; + out_data_available_temp <= 0; + cycle_count <= 0; + in_data_available_flopped <= in_data_available; + inp_data_flopped <= inp_data; + end + + else if (in_data_available) begin + cycle_count = cycle_count + 1; + out_data_available_temp <= 1; + + case (pool_window_size) + 1: begin + out_data_temp <= inp_data; + end + 2: begin + for (i = 0; i < `DESIGN_SIZE/2; i = i + 8) begin + out_data_temp[ i +: 8] <= (inp_data[i*2 +: 8] + inp_data[i*2 + 8 +: 8]) >> 1; + end + end + 4: begin + for (i = 0; i < `DESIGN_SIZE/4; i = i + 8) begin + //TODO: If 3 adders are the critical path, break into 2 cycles + out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2; + end + end + endcase + + if(cycle_count==`DESIGN_SIZE) begin + done_pool_temp <= 1'b1; + end + end +end + +assign out_data = enable_pool ? out_data_temp : inp_data_flopped; +assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped; +assign done_pool = enable_pool ? done_pool_temp : 1'b1; + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + +//////////////////////////////////////////////// +// Activation block +//////////////////////////////////////////////// + +module activation( + input activation_type, + input enable_activation, + input in_data_available, + input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data, + output [`DESIGN_SIZE*`DWIDTH-1:0] out_data, + output out_data_available, + input [`MASK_WIDTH-1:0] validity_mask, + output done_activation, + input clk, + input reset +); + +reg done_activation_internal; +reg out_data_available_internal; +wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] slope_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] intercept_applied_data_internal; +reg [`DESIGN_SIZE*`DWIDTH-1:0] relu_applied_data_internal; +reg [31:0] i; +reg [31:0] cycle_count; +reg activation_in_progress; + +reg [(`DESIGN_SIZE*4)-1:0] address; +reg [(`DESIGN_SIZE*8)-1:0] data_slope; +reg [(`DESIGN_SIZE*8)-1:0] data_slope_flopped; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_delayed; +reg [(`DESIGN_SIZE*8)-1:0] data_intercept_flopped; + +reg in_data_available_flopped; +reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped; + +always @(posedge clk) begin + if (reset) begin + inp_data_flopped <= 0; + data_slope_flopped <= 0; + end else begin + inp_data_flopped <= inp_data; + data_slope_flopped <= data_slope; + end +end + +// If the activation block is not enabled, just forward the input data +assign out_data = enable_activation ? out_data_internal : inp_data_flopped; +assign done_activation = enable_activation ? done_activation_internal : 1'b1; +assign out_data_available = enable_activation ? out_data_available_internal : in_data_available_flopped; + +always @(posedge clk) begin + if (reset || ~enable_activation) begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + in_data_available_flopped <= in_data_available; + end else if(in_data_available || activation_in_progress) begin + cycle_count = cycle_count + 1; + + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if(activation_type==1'b1) begin // tanH + slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= data_slope_flopped[i*8 +: 8] * inp_data_flopped[i*`DWIDTH +:`DWIDTH]; + data_intercept_flopped[i*8 +: 8] <= data_intercept[i*8 +: 8]; + data_intercept_delayed[i*8 +: 8] <= data_intercept_flopped[i*8 +: 8]; + intercept_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= slope_applied_data_internal[i*`DWIDTH +:`DWIDTH] + data_intercept_delayed[i*8 +: 8]; + end else begin // ReLU + relu_applied_data_internal[i*`DWIDTH +:`DWIDTH] <= inp_data[i*`DWIDTH] ? {`DWIDTH{1'b0}} : inp_data[i*`DWIDTH +:`DWIDTH]; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if (cycle_count==3) begin + out_data_available_internal <= 1; + end + end else begin + if (cycle_count==2) begin + out_data_available_internal <= 1; + end + end + + //TANH needs 1 extra cycle + if (activation_type==1'b1) begin + if(cycle_count==(`DESIGN_SIZE+2)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end else begin + if(cycle_count==(`DESIGN_SIZE+1)) begin + done_activation_internal <= 1'b1; + activation_in_progress <= 0; + end + else begin + activation_in_progress <= 1; + end + end + end + else begin + slope_applied_data_internal <= 0; + intercept_applied_data_internal <= 0; + relu_applied_data_internal <= 0; + data_intercept_delayed <= 0; + data_intercept_flopped <= 0; + done_activation_internal <= 0; + out_data_available_internal <= 0; + cycle_count <= 0; + activation_in_progress <= 0; + end +end + +assign out_data_internal = (activation_type) ? intercept_applied_data_internal : relu_applied_data_internal; + +//Our equation of tanh is Y=AX+B +//A is the slope and B is the intercept. +//We store A in one LUT and B in another. +//LUT for the slope +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_slope[i*8+:8] = 8'd0; + 4'b0001: data_slope[i*8+:8] = 8'd0; + 4'b0010: data_slope[i*8+:8] = 8'd2; + 4'b0011: data_slope[i*8+:8] = 8'd3; + 4'b0100: data_slope[i*8+:8] = 8'd4; + 4'b0101: data_slope[i*8+:8] = 8'd0; + 4'b0110: data_slope[i*8+:8] = 8'd4; + 4'b0111: data_slope[i*8+:8] = 8'd3; + 4'b1000: data_slope[i*8+:8] = 8'd2; + 4'b1001: data_slope[i*8+:8] = 8'd0; + 4'b1010: data_slope[i*8+:8] = 8'd0; + default: data_slope[i*8+:8] = 8'd0; + endcase + end +end + +//LUT for the intercept +always @(address) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + case (address[i*4+:4]) + 4'b0000: data_intercept[i*8+:8] = 8'd127; + 4'b0001: data_intercept[i*8+:8] = 8'd99; + 4'b0010: data_intercept[i*8+:8] = 8'd46; + 4'b0011: data_intercept[i*8+:8] = 8'd18; + 4'b0100: data_intercept[i*8+:8] = 8'd0; + 4'b0101: data_intercept[i*8+:8] = 8'd0; + 4'b0110: data_intercept[i*8+:8] = 8'd0; + 4'b0111: data_intercept[i*8+:8] = -8'd18; + 4'b1000: data_intercept[i*8+:8] = -8'd46; + 4'b1001: data_intercept[i*8+:8] = -8'd99; + 4'b1010: data_intercept[i*8+:8] = -8'd127; + default: data_intercept[i*8+:8] = 8'd0; + endcase + end +end + +//Logic to find address +always @(inp_data) begin + for (i = 0; i < `DESIGN_SIZE; i=i+1) begin + if((inp_data[i*`DWIDTH +:`DWIDTH])>=90) begin + address[i*4+:4] = 4'b0000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=39 && (inp_data[i*`DWIDTH +:`DWIDTH])<90) begin + address[i*4+:4] = 4'b0001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=28 && (inp_data[i*`DWIDTH +:`DWIDTH])<39) begin + address[i*4+:4] = 4'b0010; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=16 && (inp_data[i*`DWIDTH +:`DWIDTH])<28) begin + address[i*4+:4] = 4'b0011; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>=1 && (inp_data[i*`DWIDTH +:`DWIDTH])<16) begin + address[i*4+:4] = 4'b0100; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])==0) begin + address[i*4+:4] = 4'b0101; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-16 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-1) begin + address[i*4+:4] = 4'b0110; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-28 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-16) begin + address[i*4+:4] = 4'b0111; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-39 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-28) begin + address[i*4+:4] = 4'b1000; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])>-90 && (inp_data[i*`DWIDTH +:`DWIDTH])<=-39) begin + address[i*4+:4] = 4'b1001; + end + else if ((inp_data[i*`DWIDTH +:`DWIDTH])<=-90) begin + address[i*4+:4] = 4'b1010; + end + else begin + address[i*4+:4] = 4'b0101; + end + end +end + +//Adding a dummy signal to use validity_mask input, to make ODIN happy +//TODO: Need to correctly use validity_mask +wire [`MASK_WIDTH-1:0] dummy; +assign dummy = validity_mask; + +endmodule + + +////////////////////////////////////////////////////// +// Top module +////////////////////////////////////////////////////// + +module top( + input clk, + input clk_mem, + input reset, + input resetn, + input [`REG_ADDRWIDTH-1:0] PADDR, + input PWRITE, + input PSEL, + input PENABLE, + input [`REG_DATAWIDTH-1:0] PWDATA, + output [`REG_DATAWIDTH-1:0] PRDATA, + output PREADY, + input [`AWIDTH-1:0] bram_addr_a_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a_ext, + input [`DESIGN_SIZE-1:0] bram_we_a_ext, + input [`AWIDTH-1:0] bram_addr_b_ext, + output [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b_ext, + input [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b_ext, + input [`DESIGN_SIZE-1:0] bram_we_b_ext +); + +wire [`AWIDTH-1:0] bram_addr_a; +wire [`AWIDTH-1:0] bram_addr_a_for_reading; +reg [`AWIDTH-1:0] bram_addr_a_for_writing; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_a; +reg [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_a; +wire [`DESIGN_SIZE-1:0] bram_we_a; +wire bram_en_a; +wire [`AWIDTH-1:0] bram_addr_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_rdata_b; +wire [`DESIGN_SIZE*`DWIDTH-1:0] bram_wdata_b; +wire [`DESIGN_SIZE-1:0] bram_we_b; +wire bram_en_b; +reg bram_a_wdata_available; +wire [`AWIDTH-1:0] bram_addr_c_NC; +wire start_tpu; +wire done_tpu; +wire start_mat_mul; +wire done_mat_mul; +wire norm_out_data_available; +wire done_norm; +wire pool_out_data_available; +wire done_pool; +wire activation_out_data_available; +wire done_activation; +wire enable_matmul; +wire enable_norm; +wire enable_activation; +wire enable_pool; +wire [`DESIGN_SIZE*`DWIDTH-1:0] matmul_c_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] norm_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] pool_data_out; +wire [`DESIGN_SIZE*`DWIDTH-1:0] activation_data_out; +wire matmul_c_data_available; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_out_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] a_data_in_NC; +wire [`DESIGN_SIZE*`DWIDTH-1:0] b_data_in_NC; +wire [`DWIDTH-1:0] mean; +wire [`DWIDTH-1:0] inv_var; +wire [`AWIDTH-1:0] address_mat_a; +wire [`AWIDTH-1:0] address_mat_b; +wire [`AWIDTH-1:0] address_mat_c; +wire [`MASK_WIDTH-1:0] validity_mask_a_rows; +wire [`MASK_WIDTH-1:0] validity_mask_a_cols; +wire [`MASK_WIDTH-1:0] validity_mask_b_rows; +wire [`MASK_WIDTH-1:0] validity_mask_b_cols; +wire save_output_to_accum; +wire add_accum_to_output; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_a; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_b; +wire [`ADDR_STRIDE_WIDTH-1:0] address_stride_c; +wire [`MAX_BITS_POOL-1:0] pool_window_size; +wire activation_type; +wire [3:0] conv_filter_height; +wire [3:0] conv_filter_width; +wire [3:0] conv_stride_horiz; +wire [3:0] conv_stride_verti; +wire [3:0] conv_padding_left; +wire [3:0] conv_padding_right; +wire [3:0] conv_padding_top; +wire [3:0] conv_padding_bottom; +wire [15:0] num_channels_inp; +wire [15:0] num_channels_out; +wire [15:0] inp_img_height; +wire [15:0] inp_img_width; +wire [15:0] out_img_height; +wire [15:0] out_img_width; +wire [31:0] batch_size; +wire enable_conv_mode; +wire pe_reset; + +//Connections for bram a (activation/input matrix) +//bram_addr_a -> connected to u_matmul_4x4 +//bram_rdata_a -> connected to u_matmul_4x4 +//bram_wdata_a -> will come from the last block that is enabled +//bram_we_a -> will be 1 when the last block's data is available +//bram_en_a -> hardcoded to 1 +assign bram_addr_a = (bram_a_wdata_available) ? bram_addr_a_for_writing : bram_addr_a_for_reading; +assign bram_en_a = 1'b1; +assign bram_we_a = (bram_a_wdata_available) ? {`DESIGN_SIZE{1'b1}} : {`DESIGN_SIZE{1'b0}}; + +//Connections for bram b (weights matrix) +//bram_addr_b -> connected to u_matmul_4x4 +//bram_rdata_b -> connected to u_matmul_4x4 +//bram_wdata_b -> hardcoded to 0 (this block only reads from bram b) +//bram_we_b -> hardcoded to 0 (this block only reads from bram b) +//bram_en_b -> hardcoded to 1 +assign bram_wdata_b = {`DESIGN_SIZE*`DWIDTH{1'b0}}; +assign bram_en_b = 1'b1; +assign bram_we_b = {`DESIGN_SIZE{1'b0}}; + +//////////////////////////////////////////////////////////////// +// BRAM matrix A (inputs/activations) +//////////////////////////////////////////////////////////////// +ram matrix_A ( + .addr0(bram_addr_a), + .d0(bram_wdata_a), + .we0(bram_we_a), + .q0(bram_rdata_a), + .addr1(bram_addr_a_ext), + .d1(bram_wdata_a_ext), + .we1(bram_we_a_ext), + .q1(bram_rdata_a_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// BRAM matrix B (weights) +//////////////////////////////////////////////////////////////// +ram matrix_B ( + .addr0(bram_addr_b), + .d0(bram_wdata_b), + .we0(bram_we_b), + .q0(bram_rdata_b), + .addr1(bram_addr_b_ext), + .d1(bram_wdata_b_ext), + .we1(bram_we_b_ext), + .q1(bram_rdata_b_ext), + .clk(clk_mem)); + +//////////////////////////////////////////////////////////////// +// Control logic that directs all the operation +//////////////////////////////////////////////////////////////// +control u_control( + .clk(clk), + .reset(reset), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_activation(enable_activation), + .enable_pool(enable_pool), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .done_norm(done_norm), + .done_pool(done_pool), + .done_activation(done_activation), + .save_output_to_accum(save_output_to_accum), + .done_tpu(done_tpu) +); + +//////////////////////////////////////////////////////////////// +// Configuration (register) block +//////////////////////////////////////////////////////////////// +cfg u_cfg( + .PCLK(clk), + .PRESETn(resetn), + .PADDR(PADDR), + .PWRITE(PWRITE), + .PSEL(PSEL), + .PENABLE(PENABLE), + .PWDATA(PWDATA), + .PRDATA(PRDATA), + .PREADY(PREADY), + .start_tpu(start_tpu), + .enable_matmul(enable_matmul), + .enable_norm(enable_norm), + .enable_pool(enable_pool), + .enable_activation(enable_activation), + .enable_conv_mode(enable_conv_mode), + .mean(mean), + .inv_var(inv_var), + .pool_window_size(pool_window_size), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .save_output_to_accum(save_output_to_accum), + .add_accum_to_output(add_accum_to_output), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .activation_type(activation_type), + .conv_filter_height(conv_filter_height), + .conv_filter_width(conv_filter_width), + .conv_stride_horiz(conv_stride_horiz), + .conv_stride_verti(conv_stride_verti), + .conv_padding_left(conv_padding_left), + .conv_padding_right(conv_padding_right), + .conv_padding_top(conv_padding_top), + .conv_padding_bottom(conv_padding_bottom), + .num_channels_inp(num_channels_inp), + .num_channels_out(num_channels_out), + .inp_img_height(inp_img_height), + .inp_img_width(inp_img_width), + .out_img_height(out_img_height), + .out_img_width(out_img_width), + .batch_size(batch_size), + .pe_reset(pe_reset), + .done_tpu(done_tpu) +); + +//TODO: We want to move the data setup part +//and the interface to BRAM_A and BRAM_B outside +//into its own modules. For now, it is all inside +//the matmul block + +//////////////////////////////////////////////////////////////// +//Matrix multiplier +//Note: the ports on this module to write data to bram c +//are not used in this top module. +//////////////////////////////////////////////////////////////// +matmul_32x32_systolic u_matmul( + .clk(clk), + .reset(reset), + .pe_reset(pe_reset), + .start_mat_mul(start_mat_mul), + .done_mat_mul(done_mat_mul), + .address_mat_a(address_mat_a), + .address_mat_b(address_mat_b), + .address_mat_c(address_mat_c), + .address_stride_a(address_stride_a), + .address_stride_b(address_stride_b), + .address_stride_c(address_stride_c), + .a_data(bram_rdata_a), + .b_data(bram_rdata_b), + .a_data_in(a_data_in_NC), + .b_data_in(b_data_in_NC), + .c_data_in({`DESIGN_SIZE*`DWIDTH{1'b0}}), + .c_data_out(matmul_c_data_out), + .a_data_out(a_data_out_NC), + .b_data_out(b_data_out_NC), + .a_addr(bram_addr_a_for_reading), + .b_addr(bram_addr_b), + .c_addr(bram_addr_c_NC), + .c_data_available(matmul_c_data_available), + .validity_mask_a_rows(validity_mask_a_rows), + .validity_mask_a_cols(validity_mask_a_cols), + .validity_mask_b_rows(validity_mask_b_rows), + .validity_mask_b_cols(validity_mask_b_cols), + .final_mat_mul_size(8'd32), + .a_loc(8'd0), + .b_loc(8'd0) +); + +//////////////////////////////////////////////////////////////// +// Normalization module +//////////////////////////////////////////////////////////////// +norm u_norm( + .enable_norm(enable_norm), + .mean(mean), + .inv_var(inv_var), + .in_data_available(matmul_c_data_available), + .inp_data(matmul_c_data_out), + .out_data(norm_data_out), + .out_data_available(norm_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_norm(done_norm), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Pooling module +//////////////////////////////////////////////////////////////// +pool u_pool( + .enable_pool(enable_pool), + .in_data_available(norm_out_data_available), + .pool_window_size(pool_window_size), + .inp_data(norm_data_out), + .out_data(pool_data_out), + .out_data_available(pool_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_pool(done_pool), + .clk(clk), + .reset(reset) +); + +//////////////////////////////////////////////////////////////// +// Activation module +//////////////////////////////////////////////////////////////// +activation u_activation( + .activation_type(activation_type), + .enable_activation(enable_activation), + .in_data_available(pool_out_data_available), + .inp_data(pool_data_out), + .out_data(activation_data_out), + .out_data_available(activation_out_data_available), + .validity_mask(validity_mask_a_rows), + .done_activation(done_activation), + .clk(clk), + .reset(reset) +); + +//Interface to BRAM to write the output. +//Ideally, we could remove this flop stage. But then we'd +//have to generate the address for the output BRAM in each +//block that could potentially write the output. +always @(posedge clk) begin + if (reset) begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end + else if (activation_out_data_available) begin + bram_wdata_a <= activation_data_out; + bram_addr_a_for_writing <= bram_addr_a_for_writing - address_stride_c; + bram_a_wdata_available <= activation_out_data_available; + end + else begin + bram_wdata_a <= 0; + bram_addr_a_for_writing <= address_mat_c + address_stride_c; + bram_a_wdata_available <= 0; + end +end + +endmodule From d22d935322a330e201c33d54494e2d7e29f45e5f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Mar 2021 16:08:33 -0600 Subject: [PATCH 17/17] [CI] Update regressiont tests run in CI script --- .github/workflows/build.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c94e91abd..90ee24e72 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -211,6 +211,7 @@ jobs: - name: fpga_sdc_reg_test - name: fpga_spice_reg_test - name: quicklogic_reg_test + - name: vtr_benchmark_reg_test steps: - name: Checkout OpenFPGA repo uses: actions/checkout@v2