Lalit Sharma
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0cbad747a1
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Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
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Lalit Sharma
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817729ac86
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Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
tangxifan
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e34380a654
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Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
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Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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Lalit Sharma
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0038496d9c
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Replacing -openfpga with -family qlf_k4n8
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2021-02-28 21:08:47 -08:00 |
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tangxifan
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b4b6ada06f
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[Script] Correct bugs in example scripts using default_net_type
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2021-02-28 16:31:44 -07:00 |
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tangxifan
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86930d63d3
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[Test] Deploy new test to CI
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2021-02-28 16:18:46 -07:00 |
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tangxifan
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b90a17543d
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[Test] Add new test case to test default nettype in different verilog syntax
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2021-02-28 16:16:45 -07:00 |
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tangxifan
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9f4d05da67
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[Test] Bug fix for new test case
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2021-02-28 16:11:30 -07:00 |
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tangxifan
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8cc2c7d924
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[Script] Bug fix for default net type example script
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2021-02-28 12:35:44 -07:00 |
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tangxifan
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6d419fed41
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[Test] Deploy verilog default net wire type test case to CI
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2021-02-28 12:33:48 -07:00 |
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tangxifan
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18a7041424
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[Test] Add default net type test for explicit port mapping
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2021-02-28 12:31:32 -07:00 |
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tangxifan
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0723b79bce
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[Script] Add example script for verilog default net type
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2021-02-28 12:29:56 -07:00 |
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tangxifan
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27200e3daa
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[Test] Update regression test cases for fpga verilog
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2021-02-28 12:24:36 -07:00 |
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tangxifan
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ff29cc3dff
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[Test] Move tests to a test group
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2021-02-28 12:23:35 -07:00 |
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tangxifan
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9cb1ca42fe
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[Test] Deploy default net type option to test case
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2021-02-28 12:20:43 -07:00 |
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tangxifan
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ae05871b1f
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[Script] Remove default net type from an example script; Limit it to some test cases
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2021-02-28 12:19:14 -07:00 |
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tangxifan
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d7eb159726
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[Script] Add default net type option to example openfpga shell scripts
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2021-02-28 12:08:30 -07:00 |
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tangxifan
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0d82e4939c
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[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
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2021-02-26 09:35:40 -07:00 |
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tangxifan
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744d87cb4e
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[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
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2021-02-26 09:34:52 -07:00 |
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tangxifan
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870d3a0e27
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Merge branch 'master' into dev
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2021-02-26 09:28:42 -07:00 |
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Lalit Sharma
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1082d3c677
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Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |
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Lalit Sharma
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1e48d4f6dc
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Modifying custom yosys script file name
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2021-02-25 22:21:39 -08:00 |
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tangxifan
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4c2a88e27f
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[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
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2021-02-24 11:51:10 -07:00 |
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tangxifan
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0ce9b66c75
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[Arch] Add a dummy adder lut circuit model to support HDL simulation
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2021-02-24 10:09:44 -07:00 |
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tangxifan
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86a602d381
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[Test] Deploy new test to CI
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2021-02-23 19:55:07 -07:00 |
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tangxifan
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a62786986b
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[Test] Turn off verification in adder lut test temporarily
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2021-02-23 19:03:25 -07:00 |
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tangxifan
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ad25944e59
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[Arch] Patched superLUT architecture example when trying adder8 synthesis script
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2021-02-23 19:00:27 -07:00 |
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tangxifan
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53df7f69e7
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[Test] Bug fix in the test case using lut adder
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2021-02-23 16:59:46 -07:00 |
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tangxifan
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db71cc8a16
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[Test] Add LUT adder test using quicklogic synthesis script
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2021-02-23 16:50:58 -07:00 |
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tangxifan
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19f6b221b1
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[Test] Rework comments on runtime
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2021-02-22 15:25:57 -07:00 |
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tangxifan
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4803b0ce42
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[Test] Add test case for sdc controller
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2021-02-22 15:02:14 -07:00 |
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tangxifan
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c7a9a4e896
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[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
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2021-02-22 15:01:50 -07:00 |
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tangxifan
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ca135f3325
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[Arch] Add flagship architecture with 8-clock
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2021-02-22 15:01:18 -07:00 |
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tangxifan
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2e2b1cb6e7
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[Test] Use hetergenenous FPGA architecture in quicklogic tests
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2021-02-22 13:41:04 -07:00 |
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tangxifan
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1c09c55e9f
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[Arch] Add hetergenenous 8-clock FPGA architecture
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2021-02-22 13:38:50 -07:00 |
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tangxifan
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b3fed683f9
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[Test] Deploy test to CI
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2021-02-22 12:43:30 -07:00 |
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tangxifan
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bc30f62c5a
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[Test] Add test for sdc controller
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2021-02-22 12:41:53 -07:00 |
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tangxifan
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60dc194d8f
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[Test] Bug fix in the 5clock test case
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2021-02-22 11:46:23 -07:00 |
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tangxifan
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71e0026a50
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[Test] Add new test for 5-clock counter to quicklogic tests
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2021-02-22 11:32:17 -07:00 |
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tangxifan
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2bb588dacf
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[Flow] Add a new script for generating bitstream for multi-clock architectures
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2021-02-22 11:31:24 -07:00 |
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tangxifan
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77896379e2
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[Arch] Add simulation setting for 8-clock architectures
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2021-02-22 11:10:03 -07:00 |
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tangxifan
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16debe49f6
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[Arch] Add more comments on the 4 clock simulation setting file
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2021-02-22 11:04:34 -07:00 |
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tangxifan
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0ac75723af
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[Arch] Add new architecture with 8 clocks
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2021-02-22 11:00:45 -07:00 |
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tangxifan
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b9c2564a7e
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[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
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2021-02-22 10:49:21 -07:00 |
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tangxifan
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bc8aa0ebc6
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[Test] Remove routing test from quicklogic's flow test
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2021-02-22 10:22:47 -07:00 |
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tangxifan
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2dbdc2644f
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[Benchmark] Remove replicate micro benchmarks
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2021-02-22 10:22:19 -07:00 |
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tangxifan
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9b6b2068ee
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[Test] Move MCNC test to benchmark sweep test group
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2021-02-22 10:18:34 -07:00 |
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tangxifan
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c1f4a434e4
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[Doc] Update README for the regression test tasks
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2021-02-22 10:17:02 -07:00 |
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tangxifan
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d6a02a985e
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Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
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2021-02-22 09:02:29 -07:00 |