Ganesh Gore
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27005d6640
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Added Modelsim Python Script
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2019-11-01 18:20:40 -06:00 |
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Ganesh Gore
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a0512e40b1
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Created intermidiate file for modelsim simulation
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2019-11-01 18:20:00 -06:00 |
tangxifan
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4d4ef1113d
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give up iverilog on travis
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2019-11-01 17:53:50 -06:00 |
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tangxifan
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1d78725d4d
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add installation
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2019-11-01 17:48:17 -06:00 |
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tangxifan
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9a37b66d53
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move installation to a script
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2019-11-01 17:39:30 -06:00 |
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tangxifan
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161664f253
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try to comfort iverilog package extraction
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2019-11-01 17:24:06 -06:00 |
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tangxifan
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2dc3a4eb1f
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fixing bugs in iVerilog installation
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2019-11-01 17:03:21 -06:00 |
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tangxifan
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5332588e82
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retrying travis installation of iVerilog 10.3
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2019-11-01 16:36:29 -06:00 |
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tangxifan
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3ae841b80f
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start refactoring auto-check top testbench generation
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2019-11-01 16:33:12 -06:00 |
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tangxifan
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b61b81b8d8
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tuning iverilog version display
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2019-11-01 15:29:08 -06:00 |
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tangxifan
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d4fedb76d7
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revert to default iverilog of Ubuntu 18.04
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2019-11-01 15:24:58 -06:00 |
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tangxifan
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b54bec1609
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streamline regression tes
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2019-11-01 15:23:38 -06:00 |
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tangxifan
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000f93ffd7
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try to fix travis bugs
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2019-11-01 15:19:34 -06:00 |
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tangxifan
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480478e545
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reorganizing travis
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2019-11-01 15:12:08 -06:00 |
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tangxifan
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8c0d60abd6
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debugging travis
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2019-11-01 15:00:33 -06:00 |
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tangxifan
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c2cef205a4
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update travis: try to compile iverilog through source
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2019-11-01 14:52:42 -06:00 |
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tangxifan
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b53a9b13bf
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update travis with installation
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2019-11-01 14:03:55 -06:00 |
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tangxifan
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32953b0292
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rework on Travis Scripts
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2019-11-01 13:41:30 -06:00 |
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tangxifan
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de0be72634
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try to make travis install latest iVerilog
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2019-11-01 13:25:29 -06:00 |
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tangxifan
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a49010d2d3
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reorganize the Travis regression test, temporarily shadow s298
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2019-11-01 11:09:35 -06:00 |
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tangxifan
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49bfb3223c
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add compact routing to regression test
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2019-11-01 10:53:47 -06:00 |
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tangxifan
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139ea8b3e3
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add s298 single mode arch to Travis
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2019-11-01 10:49:37 -06:00 |
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tangxifan
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531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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Ganesh Gore
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da0778e813
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Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
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2019-11-01 00:46:34 -06:00 |
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tangxifan
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d709868463
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adding more regression tests which is quick run but very helpful for debugging
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2019-10-31 20:17:40 -06:00 |
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tangxifan
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2dff779005
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critical bug fixed for bitstream generation for offset truth tables
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2019-10-31 20:16:08 -06:00 |
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tangxifan
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a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
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Ganesh Gore
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81180939ca
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Bug fix: Missing exit_if_fail flag in fpga_flow script
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2019-10-31 09:56:57 -06:00 |
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tangxifan
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de78718724
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remove unused gcc setting in travis
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2019-10-30 20:07:32 -06:00 |
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tangxifan
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7eac8be475
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try to upgrade travis OS linux for the latest iverilog
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2019-10-30 20:04:20 -06:00 |
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tangxifan
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858c1aefce
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try use force for Icarus
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2019-10-30 19:50:34 -06:00 |
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tangxifan
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5531422186
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update regression test with no-explicit port mapping cases
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2019-10-30 19:37:06 -06:00 |
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tangxifan
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7460dc8cab
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pass current regression tests
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2019-10-30 19:10:36 -06:00 |
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tangxifan
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55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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1faacfa3cf
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keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
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2019-10-29 14:23:09 -06:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
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10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
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5cb3717433
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add single mode test case to regression test. debugging now
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2019-10-28 15:57:17 -06:00 |
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tangxifan
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fe005f1f56
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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tangxifan
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c047fd3cb2
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plugged in the refactored formal verification Verilog testbench using random vectors
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2019-10-28 15:10:29 -06:00 |
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tangxifan
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ccabe4ce2a
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refactoring Verilog formal verification top testbench using random vectors
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2019-10-28 14:45:51 -06:00 |
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tangxifan
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55eea6c4d5
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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tangxifan
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35073f48cf
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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tangxifan
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2b06cfc3cf
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added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
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tangxifan
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f116351831
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add instance name for each pb graph node
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2019-10-26 17:25:45 -06:00 |
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tangxifan
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7649d9228e
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fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
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tangxifan
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0a9c89be0b
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add bitstream writers and start debugging
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2019-10-26 12:41:23 -06:00 |
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tangxifan
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ca2b836128
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temporary remove MacOS from travis. Will bring back when debugged
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2019-10-25 22:13:48 -06:00 |
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tangxifan
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db9beec77c
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try to fix Travis MacOS issue
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2019-10-25 21:52:30 -06:00 |