AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
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0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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tangxifan
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5a40c6713d
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managed to plug in refactored essential gates, dead codes to be removed
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2019-08-21 21:50:26 -06:00 |
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tangxifan
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b08ff465c9
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refactored pass-gate verilog generation
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2019-08-21 17:33:16 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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a40e5c91ca
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refactored power-gate inverter
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2019-08-20 21:56:55 -06:00 |
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tangxifan
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5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
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29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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a7ac1e4980
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remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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dcca9f4f0f
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finish mux graph builders
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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638969c3c9
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adding mux graph data structures
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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c7526cb43c
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memory sanitized
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2019-08-13 14:19:40 -06:00 |
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tangxifan
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ef4d15df4e
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reorganize the libarchfpga repository
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2019-08-13 13:37:35 -06:00 |
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tangxifan
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392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
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2019-08-13 13:25:23 -06:00 |
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tangxifan
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c56f289d3e
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add checkers for circuit library
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2019-08-12 16:45:33 -06:00 |
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tangxifan
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d4ae160d3a
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start adding circuit library checkers
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2019-08-12 14:20:11 -06:00 |
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tangxifan
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fbdab32a2d
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timing graph for circuit models are working
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2019-08-10 13:03:24 -06:00 |
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tangxifan
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c004699a14
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complete parsers for ports
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2019-08-09 21:00:41 -06:00 |
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tangxifan
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2c7d6e3de4
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adding port parsers
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2019-08-09 17:48:55 -06:00 |
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tangxifan
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f80e58c753
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developing a in-house tokenizer
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2019-08-09 16:36:22 -06:00 |
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tangxifan
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3d7adb3dd9
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start developing parsers for delay values
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2019-08-09 15:52:28 -06:00 |
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tangxifan
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6b5ac2e1ef
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add timing graph builder for circuit models
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2019-08-09 12:45:03 -06:00 |
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tangxifan
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c8d04c4f00
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plug in fast look-up builder
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2019-08-08 21:20:28 -06:00 |
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tangxifan
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158c67075e
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built a conversion from spice_models to circuit_library and plug in
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2019-08-08 17:25:27 -06:00 |
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tangxifan
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e19485bbb7
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add more accessors and more to be added when plug into framework
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2019-08-08 14:16:29 -06:00 |
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tangxifan
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ad8c33e1ba
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complete the mutators
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2019-08-08 11:33:11 -06:00 |
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tangxifan
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5b0c9572c3
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add mutators for delay_info
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2019-08-07 21:19:16 -06:00 |
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tangxifan
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03a64e2ad8
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complete the mutators for ports
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2019-08-07 20:54:27 -06:00 |
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tangxifan
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9f8c7a3fc7
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adding port mutators
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2019-08-07 17:47:39 -06:00 |
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tangxifan
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ed4642a23f
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adding basic mutators
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2019-08-07 17:12:05 -06:00 |
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tangxifan
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38962c4607
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adding member functions for circuit library
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2019-08-07 15:45:27 -06:00 |
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tangxifan
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74da4ed51a
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start creating the class for circuit models
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2019-08-07 11:38:45 -06:00 |
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tangxifan
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fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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33f3a991b5
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init effort to start developing mux local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
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AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
Baudouin Chauviere
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4ca0967453
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-09 14:35:51 -06:00 |
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Baudouin Chauviere
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25f5bc7792
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Latest version, not stable yet but close
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2019-07-09 08:34:01 -06:00 |
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tangxifan
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3077efa74f
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add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |