chungshien
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ae5b9a3f72
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Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
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2024-07-28 02:52:18 -07:00 |
chungshien-chai
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22d7df5ffb
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Update doc
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2024-07-28 02:40:24 -07:00 |
|
chungshien-chai
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2a3d69aded
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Update code based on feedback
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2024-07-28 02:37:15 -07:00 |
tangxifan
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4a07a32902
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Merge pull request #1759 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-07-28 17:04:48 +08:00 |
github-actions[bot]
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ec4be3595b
|
Updated Patch Count
|
2024-07-28 09:04:21 +00:00 |
|
tangxifan
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f5051398b5
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Merge pull request #1758 from lnis-uofu/dependabot/submodules/yosys-610d27d
Bump yosys from `118b282` to `610d27d`
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2024-07-28 17:04:04 +08:00 |
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chungshien-chai
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cbe9a46f95
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Format and update doc
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2024-07-28 00:02:20 -07:00 |
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chungshien-chai
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933155b08f
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Update test flow
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2024-07-27 23:52:54 -07:00 |
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chungshien-chai
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0ff0c3445e
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Update doc
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2024-07-26 13:43:31 -07:00 |
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chungshien-chai
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fbe5ae6bd3
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Update test
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2024-07-26 02:18:08 -07:00 |
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chungshien-chai
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9641aaf6c4
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Update test
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2024-07-26 02:17:25 -07:00 |
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chungshien
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6974e1b7e7
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Merge branch 'master' into openfpga-overwrite-bits
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2024-07-26 01:37:57 -07:00 |
|
chungshien-chai
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e60777d23e
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Use Bitstream Setting XML
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2024-07-26 01:36:49 -07:00 |
dependabot[bot]
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67bc1b569b
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Bump yosys from `118b282` to `610d27d`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `118b282` to `610d27d`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](118b2829db...610d27dc1c)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-26 06:52:25 +00:00 |
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tangxifan
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aed082817e
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Merge pull request #1757 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-07-26 10:28:21 +08:00 |
|
github-actions[bot]
|
b635d17358
|
Updated Patch Count
|
2024-07-26 02:07:52 +00:00 |
|
tangxifan
|
4bf4a77861
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Merge pull request #1754 from lnis-uofu/dependabot/submodules/yosys-118b282
Bump yosys from `28ebefd` to `118b282`
|
2024-07-26 10:07:28 +08:00 |
|
chungshien-chai
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2ef362d53d
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Init support overwriting bitstream
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2024-07-25 17:40:46 -07:00 |
|
chungshien
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f142c73a11
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Merge branch 'lnis-uofu:master' into master
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2024-07-25 12:53:25 -07:00 |
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tangxifan
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542d422911
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2
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2024-07-22 21:56:00 +08:00 |
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dependabot[bot]
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cd9f533292
|
Bump yosys from `28ebefd` to `118b282`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `28ebefd` to `118b282`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](28ebefda4a...118b2829db)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-22 06:13:18 +00:00 |
|
tangxifan
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0d82682a73
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Merge pull request #1753 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-21 11:35:44 +08:00 |
|
github-actions[bot]
|
9570726ab9
|
Updated Patch Count
|
2024-07-21 03:13:52 +00:00 |
|
tangxifan
|
ce17197614
|
Merge pull request #1751 from lnis-uofu/dependabot/submodules/yosys-28ebefd
Bump yosys from `b08688f` to `28ebefd`
|
2024-07-21 11:13:31 +08:00 |
|
dependabot[bot]
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df0d64ddb4
|
Bump yosys from `b08688f` to `28ebefd`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `b08688f` to `28ebefd`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](b08688f711...28ebefda4a)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-19 06:34:08 +00:00 |
|
tangxifan
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1513ea749b
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[core] supporting clk spine on the same direction
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2024-07-16 22:12:51 -07:00 |
|
tangxifan
|
18d12109fb
|
[core] fixed a critical bug where cb port name using index is not considered on clock network entry
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2024-07-16 17:42:21 -07:00 |
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tangxifan
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c1f46c448a
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[core] fixed a critical bug where clock network entry is on a CHANY
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2024-07-16 17:04:44 -07:00 |
|
tangxifan
|
cbd10e1222
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[core] fixed a bug where tile module's global port is not derived from dedicated clock network
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2024-07-16 16:58:21 -07:00 |
|
tangxifan
|
f607987386
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[core] patch the out-of-range in clock rr nodes
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2024-07-16 16:45:55 -07:00 |
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tangxifan
|
fc58daa239
|
Merge pull request #1748 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-10 16:58:40 -07:00 |
|
github-actions[bot]
|
ab126d8cfc
|
Updated Patch Count
|
2024-07-10 23:57:28 +00:00 |
|
tangxifan
|
1b9356e05c
|
Merge pull request #1747 from lnis-uofu/dependabot/submodules/yosys-b08688f
Bump yosys from `dac5bd1` to `b08688f`
|
2024-07-10 16:57:05 -07:00 |
|
tangxifan
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37b302b335
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Merge pull request #1746 from lnis-uofu/xt_clkntwk2
Support global net routing on regular inputs of programmable blocks
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2024-07-10 16:56:47 -07:00 |
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tangxifan
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0c99fcf6f4
|
[doc] format
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2024-07-10 15:07:57 -07:00 |
|
tangxifan
|
c96f899c53
|
[core] code format
|
2024-07-10 15:07:26 -07:00 |
|
tangxifan
|
a390aad0b8
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[doc] add new syntax
|
2024-07-10 15:07:16 -07:00 |
|
tangxifan
|
e614ca7380
|
[test] use new syntax
|
2024-07-10 15:03:27 -07:00 |
|
tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
|
2024-07-10 15:01:18 -07:00 |
|
tangxifan
|
b2fc47a12a
|
[core] reworked i/o for clock network files
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2024-07-10 14:34:54 -07:00 |
|
tangxifan
|
079e6f2fca
|
[core] add new syntax to support from_pin and to_pin for internal driver in clock network
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2024-07-10 14:28:28 -07:00 |
|
tangxifan
|
215de8eb93
|
[core] code format
|
2024-07-10 14:17:22 -07:00 |
|
tangxifan
|
f5ba43e392
|
[core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench
|
2024-07-10 14:16:24 -07:00 |
|
tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
213914e4ac
|
[core] code format
|
2024-07-10 12:23:57 -07:00 |
|
tangxifan
|
48e159dd8d
|
[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
|
2024-07-10 12:23:15 -07:00 |
|
tangxifan
|
c6dd33a965
|
[core] fixed a bug when annotating global nets on OPIN
|
2024-07-10 11:59:25 -07:00 |
|
tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |
|
tangxifan
|
dbe8e63f53
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[test] remove unused files
|
2024-07-10 10:15:47 -07:00 |