tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
|
tangxifan
|
0d8d8446ee
|
[test] fixed a bug where OPIN for direct connection is included in GSB
|
2022-09-30 15:24:51 -07:00 |
|
tangxifan
|
36b3e64b35
|
[engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results
|
2022-09-28 12:17:16 -07:00 |
|
tangxifan
|
3285af4107
|
[engine] syntax
|
2022-09-28 11:39:37 -07:00 |
|
tangxifan
|
51f54bbf20
|
[engine] developing the steps to annotate clustering results
|
2022-09-27 16:54:48 -07:00 |
|
tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
|
tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
|
2022-09-19 11:00:08 -07:00 |
|
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
|
tangxifan
|
eab3580f79
|
[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity
|
2022-09-06 13:40:29 -07:00 |
|
tangxifan
|
2f84ce5955
|
[engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used
|
2022-09-06 11:48:21 -07:00 |
|
tangxifan
|
b26b2d0ed0
|
Merge branch 'master' into vtr_upgrade
|
2022-09-02 10:05:23 -07:00 |
coolbreeze413
|
04abd1a36f
|
add <array> declaration to fix gcc error
|
2022-09-02 19:26:28 +05:30 |
|
tangxifan
|
e4aa6e0ee5
|
[engine] syntax
|
2022-09-01 15:17:39 -07:00 |
|
tangxifan
|
ee87b5c348
|
[engine] fixed all the remaining syntax errors due to API mismatches
|
2022-09-01 09:57:12 -07:00 |
|
tangxifan
|
7c5046cf4e
|
[engine] include the correct header file
|
2022-09-01 09:23:05 -07:00 |
|
tangxifan
|
71ad0721a1
|
Merge branch 'master' into vtr_upgrade
|
2022-08-31 13:56:17 -07:00 |
|
tangxifan
|
26388dfb2f
|
[engine] fixed a bug which causes errors when writing unique GSB to files
|
2022-08-30 15:45:00 -07:00 |
|
tangxifan
|
3656154913
|
[engine] fixed syntax errors
|
2022-08-29 21:17:48 -07:00 |
|
tangxifan
|
2321ea6274
|
[engine] complete the code required to output rr_gsb with options
|
2022-08-29 20:44:16 -07:00 |
|
tangxifan
|
12a30196e0
|
[engine] updating gsb writer; Unfinished!!!
|
2022-08-29 16:58:48 -07:00 |
|
tangxifan
|
e9d6e7e38a
|
[engine] update vtr and enable more debugging info
|
2022-08-27 19:12:43 -07:00 |
|
tangxifan
|
d1edc51165
|
[engine] clean up header files that include rr_graph_obj
|
2022-08-23 18:38:21 -07:00 |
|
tangxifan
|
892770a8fb
|
[engine] debugging subtile index failures
|
2022-08-23 14:13:10 -07:00 |
|
tangxifan
|
019e663e12
|
[engine] fixing the bugs on building global nets to sub tile pins
|
2022-08-23 11:58:44 -07:00 |
|
tangxifan
|
ba0ddd01d3
|
[engine] fixing the bugs on subtiles
|
2022-08-23 10:52:05 -07:00 |
|
tangxifan
|
c17e5d46ab
|
[engine] fixed a bug due to the API of subtile data structure
|
2022-08-22 21:44:05 -07:00 |
|
tangxifan
|
800ce6a290
|
[engine] avoid function naming conflicts
|
2022-08-18 19:33:56 -07:00 |
|
tangxifan
|
e9c4d102c1
|
[engine] rename files to avoid conflicts with VPR files
|
2022-08-17 20:01:50 -07:00 |
|
tangxifan
|
8f1aac885e
|
[engine] fixing mismatches in APIs
|
2022-08-17 14:19:02 -07:00 |
|
tangxifan
|
4e871be357
|
[engine] adapt the use of API in RRGraph for annotation functions
|
2022-08-17 10:50:16 -07:00 |
|
tangxifan
|
01d53db484
|
[script] Adapt timing analysis APIs
|
2022-08-17 10:28:58 -07:00 |
|
tangxifan
|
ade8f43a36
|
[engine] Updating RRGraph Annotation and VTr
|
2022-08-17 10:16:55 -07:00 |
|
tangxifan
|
716929536d
|
[engine] adapting source files for new APIs in VTR
|
2022-08-17 09:54:31 -07:00 |
|
tangxifan
|
d3d81f0b18
|
[engine] keep adapting to latest VTR
|
2022-08-16 21:05:50 -07:00 |
|
tangxifan
|
0c329866da
|
[engine] Use RRGraphView in openfpga source codes
|
2022-08-16 16:48:32 -07:00 |
|
tangxifan
|
ce7204daec
|
[engine] debugging
|
2022-08-16 16:35:08 -07:00 |
|
tangxifan
|
a20f6eaf06
|
[Engine] Fixed a few bugs
|
2022-04-10 21:29:38 +08:00 |
|
tangxifan
|
755be78b39
|
[Engine] Now GSB output file contains segments name and pin name in SB module
|
2022-04-10 21:22:30 +08:00 |
|
tangxifan
|
a9a56686e2
|
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
|
2022-01-26 11:10:29 -08:00 |
|
tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
|
tangxifan
|
0aec30bac6
|
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
|
2021-04-19 15:53:33 -06:00 |
|
tangxifan
|
87006e1374
|
Merge branch 'master' into netlist_name_patch
|
2021-03-15 10:06:24 -06:00 |
|
tangxifan
|
d2fbda4070
|
Merge branch 'master' into netlist_name_patch
|
2021-03-15 09:13:04 -06:00 |
|
tangxifan
|
b080bcf018
|
Merge branch 'master' into ganesh_dev
|
2021-03-15 09:12:50 -06:00 |
Maciej Kurc
|
02967f2870
|
Added writing rr graph node indices to GSB dump.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
|
2021-03-15 09:28:38 +01:00 |
|
tangxifan
|
2c5634ee76
|
[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
|
tangxifan
|
d877a02534
|
[Tool] Patch the extended bitstream setting support on mode-select bits
|
2021-03-10 21:28:09 -07:00 |
|
tangxifan
|
85640a7403
|
[Tool] Extend bitstream setting to support mode bits overload from eblif file
|
2021-03-10 20:45:48 -07:00 |
|
tangxifan
|
0c409b5bcc
|
[Tool] Add bitstream annotation support
|
2021-02-01 20:49:36 -07:00 |
|
tangxifan
|
4b77a3a574
|
[Tool] Now activity file is not a manadatory input of openfpga tools
|
2021-01-29 11:33:40 -07:00 |