87b2c1f3b8
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
2021-01-15 12:01:53 -07:00
852f5bb72e
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
2021-01-14 15:38:24 -07:00
b661c39b04
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
2020-12-02 19:36:36 -07:00
04070fd4ca
[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
2020-09-02 22:16:10 -06:00
3eea12ceae
added a new XML syntax: initial offset for physical mode pin mapping
2020-08-19 14:43:44 -06:00
f631245b2b
bug fix and enriched debugging info print out
2020-08-19 13:41:04 -06:00
79b6ff3cb0
relax checking for device annotation as we support multi-port during physical mode pin mapping
2020-08-19 12:44:51 -06:00
2712c354a9
now physical pb_port binding support multiple ports
2020-08-18 12:38:56 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
2e3a811f4f
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
2020-04-18 21:04:46 -06:00
72e8824a87
bug fixed on removing undriven pins (direct connection between clbs) from cb
2020-04-15 20:41:15 -06:00
b9dab2baaf
add exit codes to command execution in shell context
2020-04-08 16:18:05 -06:00
1fb37f4c71
improve directory creator to support same functionality as 'mkdir -p'
2020-04-08 12:55:09 -06:00
0b1c8ac139
bug fixed in identifying the physical interconnect for pb_graph nodes
2020-04-07 19:46:42 -06:00
62276f9e28
minor code format
2020-04-07 18:43:11 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
fdf6a6bd3e
use chan_node_in_edges from rr_gsb in XML writer
2020-03-22 15:48:11 -06:00
7b9384f3b2
add write_gsb command to shell interface
2020-03-21 19:40:26 -06:00
637be076dc
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
2020-03-21 18:49:20 -06:00
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
aff73bdd74
deployed edge sorting and make it as an option to link_arch command
2020-03-08 15:59:53 -06:00
0c7aa2581d
update vpr8 version with hotfix on undriven pins in GSB
2020-03-08 14:58:56 -06:00
6e83154703
move rr_gsb and rr_chan to tileable rr_graph builder
2020-03-04 14:14:28 -07:00
aa66042dfb
move simulation setting annotation to a separated source file
2020-02-29 15:19:02 -07:00
2dd80e4830
add more methods to acquire physical truth table from physical pb
2020-02-25 21:21:44 -07:00
8e9660b816
add mapped block fast look-up as placement annotation
2020-02-24 16:09:29 -07:00
921bf7dd7b
use constant in device annotation
2020-02-21 20:45:22 -07:00
12f2888c7c
add physical pb data structure and basic allocator
2020-02-21 17:47:27 -07:00
b035b4c87f
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
2020-02-21 12:16:50 -07:00
62e4f14e30
add lb_rr_graph to device annotation
2020-02-17 17:26:27 -07:00
59c13550e0
add direct annotation with inter-column/row syntax
2020-02-14 17:40:59 -07:00
ce63b1cc62
add circuit model binding for direct connections and enhance model type checking
2020-02-12 11:40:20 -07:00
4a05cec037
add rr_segment binding to circuit model
2020-02-12 11:21:40 -07:00
a736e09c29
add rr_switch binding in link openfpga arch command
2020-02-12 10:52:20 -07:00
feccbc5780
add more methods to link routing to circuit models in device annotation
2020-02-12 10:08:54 -07:00
a31d6c6d1e
rename pb_type annotation to device annotation
2020-02-12 09:52:18 -07:00
175bef014a
add compact_routing hierarchy command
2020-02-11 17:40:37 -07:00
1372f748f1
put GSB builder online
2020-02-11 16:37:14 -07:00
85f3826939
put device rr_gsb online. Ready to plug-in
2020-02-09 14:58:23 -07:00
230c7b709a
put rr_gsb data structure online
2020-02-09 00:20:44 -07:00
0b6b3bc029
start adapting rr_gsb related data structure
2020-02-07 11:32:33 -07:00
ed9e038845
add functionality of LUT truth table fix-up
2020-02-06 17:14:29 -07:00
99f5a86b49
bug fixed for routing annotation and routing net fix-up
2020-02-06 12:54:55 -07:00
cccbb9fd49
add missing files
2020-02-05 22:12:44 -07:00
dad204674b
done an initial version of clustering net fix-up based on routing results. Debugging on the way
2020-02-05 21:50:52 -07:00
75c3507acf
add verbose output option for openfpga linking architecture
2020-01-31 11:36:58 -07:00
392ab0f027
move duplicated codes on message printing to functions
2020-01-31 10:53:41 -07:00
afde9808da
add check codes for physical pb_graph_node and pb_graph_pin annotation
2020-01-31 10:47:05 -07:00
fdc304a0fb
fixed a bug in mapping pb_graph pins using rotation offset
2020-01-30 22:00:53 -07:00
02d6256e95
pass simple test on pb_type annotation for frac_lut5 architecture
2020-01-30 21:39:44 -07:00
007e1997e6
add pb_graph pin annotation
2020-01-30 19:40:40 -07:00
d62c9fe86f
adding pb_graph_node annotation
2020-01-30 16:40:13 -07:00
e48ab8cb44
move annotation source files to a separated folder
2020-01-30 13:37:41 -07:00
tangxifan