b9e4977e7e
don't leave bus ports unconnected
2022-03-09 08:25:20 -08:00
9a49782158
fix output connected to X
2022-02-25 10:08:33 -08:00
1ff3267ade
bring changes related to post layout netlist and sdf generation for black box
2022-02-23 05:33:02 -08:00
025ee67bc7
[Engine] Clear up compiler warning in tileable rr_graph builder
2021-09-24 15:20:43 -07:00
cbd7105083
[Tool] Add illustrative comments to tileable rr_graph generator
2021-04-26 11:57:17 -06:00
880624e699
[Tool] Update comments in tileable rr_graph generator to be easier to be understood
2021-04-26 11:48:02 -06:00
3513966078
[Tool] Borrow a quick fix from the VPR pull request https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1656/files
2021-02-04 17:30:49 -07:00
95c9e19901
[Tool] Tileable rr_graph now accept I/Os in center grid
2020-12-04 17:43:35 -07:00
7206cafc0e
[Tool] Minor bug fix
2020-12-04 17:18:02 -07:00
29fd13a42a
[Tool] Relax restrictions on I/O location in tileable rr_graph builder
2020-12-04 17:07:01 -07:00
3d38e76c8f
Disabled printing segment ids for non-channel nodes.
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-11-23 17:07:28 +01:00
b6728cf2d9
Added loading rr node segment indices
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-11-23 14:53:50 +01:00
801055b007
[OpenFPGA Tool] Bug Fix on the tileable RRG for multi segment
2020-09-22 12:47:02 -06:00
8041c90f12
bug fix in through channel support in tileable routing
2020-08-19 20:01:50 -06:00
f3ca1c0973
fix rr_graph on thru routing channel support
2020-08-19 17:28:25 -06:00
af1c7c6f29
start fixing the bug in thru channels
2020-08-19 12:18:35 -06:00
83e26adf90
add module usage types for future FPGA-SPICE development
2020-07-04 22:33:54 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
b8bc74cc26
trying to fix the dependency problem of VPR GUI in openfpga shell
2020-06-11 19:31:15 -06:00
6f133bd009
bug fix in packable mode support
2020-06-11 19:31:07 -06:00
0c4904065f
reduce activity error to warning.
2020-04-22 17:36:02 -06:00
2342d7cdc6
minor tweak on the scan-chain support in VPR8 as well as architecture file
...
Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
2020-04-07 17:03:44 -06:00
13cd48c119
add support on packable/unpackable modes in VPR architecture
2020-04-06 16:07:49 -06:00
07e1979498
add architecture examples on wide memory blocks (width=2). tileable routing is working
2020-03-28 15:41:26 -06:00
5ce078fe60
minor fix on rr_graph.clear()
2020-03-27 11:26:14 -06:00
91a618466d
bug fixing for rr_graph.clear() function
2020-03-27 10:52:48 -06:00
3b3c39454b
update print_route() in VPR to show correct track_id when tileable routing is used
2020-03-25 17:55:28 -06:00
610c71671f
experimentally developing through channels inside multi-width and multi-height grids.
...
Still debugging.
2020-03-24 16:47:45 -06:00
8a996ceae5
bug fixed in tileable routing when heterogeneous blocks are considered;
...
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
63c4669dbb
fixed bug in the fast look-up for tileable rr_graph
2020-03-21 17:36:08 -06:00
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
2ff2d65e58
start debugging tileable routing using larger array size. Bug spotted in finding chan nodes
2020-03-20 22:12:23 -06:00
3c37b33f17
critical bug fixed in edge sorting for rr_gsb
2020-03-20 17:45:50 -06:00
060c1a41d9
critical bug fixed for tileable routing: delayless and wire2ipin switch was reverted
2020-03-20 17:23:19 -06:00
708fda9606
fixed a bug in using tileable routing when directlist is enabled
2020-03-20 16:38:58 -06:00
7a7f8374b3
start deploying edge sorting in uniquifying SB modules
2020-03-08 15:24:34 -06:00
0fbf3fca41
start developing edge sorting inside RRGSB
2020-03-07 23:30:55 -07:00
c36c302052
looks like tileable routing is working
2020-03-06 17:16:53 -07:00
f54f46483b
start debugging tileable rr_graph generator
2020-03-06 17:02:22 -07:00
5be118d695
tileable rr_graph builder ready to debug
2020-03-06 16:18:45 -07:00
245a379c4f
start plug in tileable rr_graph builder
2020-03-06 16:03:00 -07:00
3eb59d201f
adapt top function of tileable rr_graph builder
2020-03-06 15:24:26 -07:00
441a307100
add routing chan width corrector to rr_graph builder utils
2020-03-06 14:54:40 -07:00
441de12936
adapt Fc in gsb connection builder to use VPR8 Fc builder
2020-03-06 14:43:12 -07:00
8d350ee22f
adapt tileable rr_graph edge builder to rr_graph object
2020-03-05 20:50:21 -07:00
328488f357
adapt chan rr node builder to use rr_graph obj
2020-03-05 20:15:16 -07:00
Tarachand Pagarani
tangxifan
Maciej Kurc