Commit Graph

484 Commits

Author SHA1 Message Date
Tim Newsome 0ad060d97a Review feedback.
Change-Id: If58c011fc8d89d329d65a6c624ffb631f111cef2
2018-05-17 18:08:08 -07:00
Tim Newsome 41c42bf2df Comment riscv_set_register, register_write_direct
Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17 18:01:00 -07:00
Megan Wachs efd7260972 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2018-05-14 07:31:25 -07:00
Tim Newsome dabaf170ba blank_check_memory prototype has changed.
Just remove our nop implementation. The default behavior when this is
left NULL does the same thing.

Change-Id: I865976c694d24661941584cb0efc92fc26612316
2018-05-08 15:21:49 -07:00
Tim Newsome 2a103bae44 Don't error if hart select isn't implemented.
It's not implemented for 0.11 because we don't need it. Returning error
caused 0.11 targets to not be debuggable since change
848062d0d1.

Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07 15:16:57 -07:00
Tim Newsome 67b4e2c522 counter*h registers only exist on RV32
Fixes #245.

Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-03 12:26:30 -07:00
Tim Newsome b62c014bdc Merge branch 'riscv' into notice_reset 2018-04-30 13:36:06 -07:00
Megan Wachs 3fedb7d97f Merge remote-tracking branch 'origin/riscv' into HEAD 2018-04-18 15:22:38 -07:00
Tim Newsome 69a426038d
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.

Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8

* Fail if `git diff` fails

Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9

* Maybe every line gets its own shell?

Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6

* Maybe this will error properly.

Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9

* Take different approach than merge-base

Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1

* Fix style issues.

Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
2018-04-18 13:11:08 -07:00
Megan Wachs 6217f56186 Merge remote-tracking branch 'origin/notice_reset' into riscv-compliance 2018-04-17 15:47:41 -07:00
Megan Wachs bc32aaafa4 riscv-compliance: whitespace cleanup 2018-04-16 17:49:16 -07:00
Ryan Macdonald bf0ffff1db Fix issue with COMMAND_PARSE_NUMBER 2018-04-13 16:09:57 -07:00
Megan Wachs adf7dd7b5e Merge branch 'riscv' into riscv-compliance 2018-04-12 16:03:54 -07:00
Ryan Macdonald cc98a14839 Added address alignment test, code fixups from review 2018-04-11 14:26:16 -07:00
Ryan Macdonald c2c52c89b1 Fix some build issues 2018-04-09 11:38:41 -07:00
Ryan Macdonald 99f2f5a272 Change #ifdef SIM_ON to be a run-time arg 2018-04-09 11:26:31 -07:00
Ryan Macdonald a9b2277574 Add #ifdef to only enable sbbusyerror test in simulation. 2018-04-09 10:51:53 -07:00
Ryan Macdonald d471fff3db Fixed build issues 2018-04-05 17:57:53 -07:00
Ryan Macdonald 3bdb8b29a8 Checkpoint: finish debug of tests, working on hitting sbbusyerror case 2018-04-05 16:31:09 -07:00
Ryan Macdonald c5a8e1cf4c Initial commit of tests for SBA feature 2018-04-04 13:50:17 -07:00
Tim Newsome 6030644a9d Track misa per-hart even in -rtos mode
This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.

This fixes #194.

Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
Tim Newsome eeae8c4261 Add gdb_report_register_access_error command
This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.

Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
2018-04-02 13:37:53 -07:00
Tim Newsome 3c7c7e26a4
Merge pull request #230 from riscv/deleg
Make m*deleg regs conditional on U/S/N
2018-03-30 14:02:13 -07:00
Tim Newsome 224e7b4f16 Once more... Less sloppy this time.
Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00
Tim Newsome 55e427b72b Don't rely on havereset when deasserting reset.
This removes the need for the supports_havereset config option as well.

Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
Tim Newsome 0c05aafbf8 Fix m*deleg logic.
Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00
Tim Newsome b6dca68b2e Make m*deleg regs conditional on U/S/N
Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
2018-03-23 13:43:12 -07:00
Tim Newsome d7282d0bfe Add set_supports_havereset
This lets reset work on targets that don't implement havereset.

Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
Tim Newsome 52eabbd2a5 Add `riscv set_prefer_sba`
This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.

Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
Tim Newsome 4d2d1f7324 Notice when a hart has reset.
Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.

Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
Tim Newsome 848062d0d1 Propagate errors in more places
Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00
Tim Newsome c10c570dca Fix cut and paste error message.
Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
2018-03-06 13:22:57 -08:00
Tim Newsome ddb894edf6 Add riscv dmi_read/dmi_write commands.
Mostly addresses #207.

Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.

Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
Tim Newsome 1d9418fbb0 Only propagate register errors on some targets
Without this change, connecting to ARM targets is impossible.

Fixes #115.

Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
2018-03-01 15:11:11 -08:00
Tim Newsome 10108b623d Add `authdata_read` and `authdata_write` commands.
They can be used to authenticate to a Debug Module.

There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.

Example usage (very simple challenge-response protocol):
```
init

set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]

reset halt
```

Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
Tim Newsome 3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
Megan Wachs 313885cb3b riscv-compliance: whitespace fixes 2018-02-13 13:08:15 -08:00
Tim Newsome ace6b7e49a Handle resuming from a trigger...
... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.

Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
2018-02-07 13:30:23 -08:00
Megan Wachs 5cf705d360 Merge remote-tracking branch 'origin/riscv' into HEAD 2018-02-06 10:26:22 -08:00
Tim Newsome bb2c25c5ce Make OpenOCD work when there is no program buffer.
Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.

Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
2018-01-31 15:33:45 -08:00
Tim Newsome fd506fa839 Propagate register read errors.
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
Tim Newsome 0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection
Select current hart before reading memory.
2018-01-05 14:07:38 -08:00
Tim Newsome 6f3913cedc Select current hart before reading memory.
This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).

Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04 17:12:01 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-04 13:27:18 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls.
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27 13:45:50 -08:00
Tim Newsome 4fa3d819d2 Remove unused code.
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
2017-12-26 14:27:44 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide.
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26 11:38:11 -08:00
Tim Newsome 1f66c7827b Fix flash/run algorithm with new register names
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21 16:41:50 -08:00
Megan Wachs a81ad34af3
Merge pull request #148 from riscv/macbuild
Use %ll instead of %L in scanf.
2017-12-21 15:16:57 -08:00
Tim Newsome fa385bdcd5 Use parens after if.
I'm surprised this built with gcc before.

Fixes Issue #150.

Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-21 12:43:22 -08:00
Tim Newsome 11c261cd50 Add `riscv expose_csrs` command.
This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.

Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19 10:41:48 -08:00
Tim Newsome 5f86f7208d Hide supervisor registers if there is no S mode.
Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19 10:41:48 -08:00
Tim Newsome f55d1a2030 Give FPRs ABI names.
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19 10:41:48 -08:00
Tim Newsome c7cddd2b5c Remove some debug printfs.
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
2017-12-19 10:41:48 -08:00
Tim Newsome 46715c7d8a Remove no-longer-true comment.
Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19 10:41:48 -08:00
Tim Newsome 37278cf2ec Make priv register 8 bits.
(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)

Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11.
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names.
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D.
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
Tim Newsome e648856a41 `make all` debug tests now pass.
Also properly support (I think) D extension on RV32.

Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
Tim Newsome 1e43d32e01 Use %ll instead of %L instead of scanf.
Mac build barfs on L, and the manpage says they're equivalent.

Hopefully fixes #147

Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
2017-12-15 15:31:36 -08:00
Tim Newsome db754536e8 Support 64-bit FPRs on RV32.
Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.

I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.

Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.

This change improves Issue #110 but there's more work to be done.

Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
Megan Wachs 1672f9a60d Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-10-25 15:41:41 -07:00
Tim Newsome d94b38279a Memtest{16,32} pass.
Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-16 21:08:59 -07:00
Tim Newsome 94e8250713 WIP; doesn't work.
Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-12 11:45:52 -07:00
Tim Newsome 51f73a6769 Fix triggers for multi-gdb mode. 2017-09-26 15:40:49 -07:00
Tim Newsome 848fe0ffcf Cleaning up single-hart reset. 2017-09-19 17:41:52 -07:00
Tim Newsome ce20be3d78 Add support for F extension. 2017-09-14 16:23:47 -07:00
Tim Newsome 8bcec87cc1 Remove unnecessary \n 2017-08-26 16:53:00 -07:00
Megan Wachs 6200d9a180 Merge branch 'riscv_timeout_commands' into riscv-compliance 2017-08-15 17:22:08 -07:00
Megan Wachs 94de39c221 riscv: Put commandd_handlers before they are needed. Tabs vs spaces. 2017-08-15 17:04:59 -07:00
Megan Wachs 879c274cb9 riscv: Add commands for setting timeouts 2017-08-15 15:59:40 -07:00
Megan Wachs 3ec1772c96 riscv: Add commands for setting timeouts 2017-08-15 15:55:09 -07:00
Megan Wachs 25eedb94a5 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-08-14 12:08:58 -07:00
Tim Newsome 46b5f913c7 Display register numbers in a more usable format. 2017-07-27 13:45:26 -07:00
Tim Newsome d60dbd60e8 Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.

In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
Megan Wachs 20d46b8bf0 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-12 18:46:26 -07:00
Tim Newsome 4072fa493b Disable debugger-set triggers on connect
When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.

To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.

Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
Tim Newsome 31e5b53a46 Merge pull request #74 from riscv/build32
Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
mwachs5 87abbe4a51 Merge remote-tracking branch 'origin/riscv' into riscv-compliance 2017-07-05 11:02:30 -07:00
Tim Newsome 450307b66f Fix 32-bit build errors.
I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71.
2017-07-03 12:17:07 -07:00
mwachs5 95ee7975ea riscv: Add skeleton of RISC-V v013 compliance 2017-06-28 19:32:38 -07:00
Megan Wachs 7a4948c126 riscv: initial checkin of a 'compliance test' command. 2017-06-28 19:32:38 -07:00
Palmer Dabbelt 689d0fcaf6 No longer hard-code the non-RTOS hart to 0
I was just being lazy here.
2017-06-21 12:25:19 -07:00
Palmer Dabbelt 788908fcf0 Factor out checking if harts should be used
Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled".  This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
Palmer Dabbelt 9f4cac5a38 Set current_hartid from coreid
This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
Tim Newsome 10518351bb Don't immediately segfault with -rtos on v0.11. 2017-06-20 11:32:42 -07:00
Tim Newsome ac2da40f74 Fix indentation to match OpenOCD style.
This change is just in the whitespace. There are no code changes.

See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
Palmer Dabbelt afc9eb6c47 Jump to the RTOS hartid after halting
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting.  This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
2017-06-15 12:16:33 -07:00
Tim Newsome 64af052911 Fix the build.
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.

Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
Palmer Dabbelt ab77c5d792 Invalidate the register cache when rtos_hartid==-1
This means I don't know what hart to look at, so I might as well
invalidate the register cache.  Without this, you might get stale
registers the first time you ask for them.
2017-05-25 13:14:31 -07:00
Palmer Dabbelt faa6123e36 Invalidate the register cache on step, resume, reset
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode.  With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
2017-05-25 13:14:31 -07:00
Palmer Dabbelt bcf2a16b0d Shim back in some old interfaces for now 2017-05-11 10:41:13 -07:00
Palmer Dabbelt 563f6acc3c Allow all harts to be reset 2017-05-09 13:33:20 -07:00
Megan Wachs fa8d7adf33 Avoid accessing null target->reg_cache
GDB might request registers even if target was not successfully initialized.
2017-05-05 11:05:28 -07:00
Palmer Dabbelt ba3a56937b Correct previous hart caching logic 2017-05-01 08:32:43 -07:00
Palmer Dabbelt 17d04aded3 Keep calling the old poll on v0.11 targets
This is another thing that should be fixed correctly.  Essentially this
just uses the old codepath, which works for v0.11.
2017-04-26 15:16:39 -07:00
Megan Wachs da66be0161 riscv: Fix some blocking compile warnings 2017-04-26 10:23:53 -07:00
Palmer Dabbelt 8dea2908b7 Add 64-bit and multihart support
This is a major rewrite of the RISC-V v0.13 OpenOCD port.  This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports.  This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around.  The changes are:

 * You can pass "-rtos riscv" to the target in OpenOCD's configuration
   file, which enables multi-hart mode.  This uses OpenOCD's RTOS
   support to control all the harts from the debug module using commands
   like "info threads" in GDB.  This support is still expermental.

 * There is support for RV64I, but due to OpenOCD limitations we only
   support 32-bit physical addresses.  I hope to remedy this by rebasing
   onto the latest OpenOCD release, which I've heard should fix this.

 * This matches the latest draft version of the RISC-V debug spec, as of
   April 26th.  This version fixes a number of spec bugs and should be
   close to the final debug spec.
2017-04-26 09:10:49 -07:00
Megan Wachs b04c6cb3ed riscv: Implement the assert/deassert reset functions for v13 2017-04-10 12:03:15 -07:00
Tim Newsome e6221e75c9 Attempt to discover XLEN with abstract reg reads
Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
2017-02-10 19:08:44 -08:00
Tim Newsome 8d195afd2d Use the csrNNN name instead of "mstatus".
Fixes flashing code.

Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
2017-02-05 18:19:00 -08:00
Tim Newsome d055f86552 Most gdbserver tests pass now.
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
2017-02-05 18:09:19 -08:00
Megan Wachs 5d82a395f1 riscv: disable interrupts for all priviledge levels 2017-01-25 21:51:02 -08:00
Megan Wachs d5892f0ee5 riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms. 2017-01-25 15:23:10 -08:00
Megan Wachs 5766efe0c3 riscv: Globally disable interrupts when running algorithms. 2017-01-25 11:35:57 -08:00
Megan Wachs 4a0d3fb035 riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just get a segfault when attempting to perform these actions. 2016-12-07 15:09:35 -08:00
Tim Newsome c1da323144 Fix issue #6: build failure on gcc 6
Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078
2016-12-01 19:15:55 -08:00
Tim Newsome 7dd48acdc0 Cope better if the target unexpectedly resets.
Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9
2016-11-25 09:46:55 -08:00
Tim Newsome 8ee0647365 Flash at 8KB/s, using 10,000 byte working area.
If the working area is large enough, every fespi_write() results in just
a single algorithm execution.

Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
2016-11-18 10:58:26 -08:00
Tim Newsome 18eedf996c Use algorithm to speed up fespi flash programming.
It's still really slow, at 854b/s, but it seems to work and it's a lot
of new code.

Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
2016-11-16 17:54:55 -08:00
Tim Newsome e51b0360f5 Make fpu regs work even if mstatus.fs is 0.
Change-Id: I2c283f2de226518ab9a4e0476edada51825b2993
2016-11-01 12:58:37 -07:00
Tim Newsome e7a745ed3b Fix bug with slow targets.
Halting didn't work right in slow targets, because some code assumed the
register cache is valid before it was guaranteed to be.

Also made dbus_busy_delay and interrupt_high_delay grow faster, so that
on slow targets it takes less time to learn the correct values.

Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42
2016-10-27 13:00:26 -07:00
Tim Newsome e6e2070692 Add some comments.
Change-Id: Icd7d5eb370c6c893ec4717c92249f35fb100370a
2016-10-24 14:21:34 -07:00
Tim Newsome 3eb6cf0fc0 Make CLI step and resume work.
Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
2016-10-20 14:49:23 -07:00
Tim Newsome 9b0be80d1e Use reg_cache structure, to make reg command work.
Change-Id: I9f1d1f2eab66822c3c47284aa91b52cc34998381
2016-10-20 10:42:28 -07:00
Tim Newsome 4eba841bfe Print when we're ready for gdb to connect.
This should help gdbserver.py to connect reliably to really slow targets
(ie. simulators).

Change-Id: I8e9adbaf2ebde11b44e15582f036622a2d00c1f9
2016-10-14 12:40:52 -07:00
Tim Newsome 3f6c2a9f78 Be quiet when the target is just running normally.
Change-Id: I7861f16ba6b1b5c1851787ce5d78c02aff0568f6
2016-10-13 10:51:53 -07:00
Tim Newsome cb93bb9035 Use an easily changed constant for timeout.
Change-Id: I7aace463b0bd9916580e950d60b2940879b27b2a
2016-10-11 16:26:19 -07:00
Tim Newsome 4882de94cc Display pc to the user in 'monitor reset init'.
Change-Id: Ifb8df31954dfc5a3badef4f0a29eb510a97310a2
2016-10-10 08:22:51 -07:00
Tim Newsome a08cef7633 Change invalid access from error to user message.
It's not a failure in the debugger or even a real problem if a user asks
to access memory that's not accessible.

Change-Id: I30b8424d5265d1996fe4826012ed160a83f0bc6c
2016-10-03 08:15:04 -07:00
Tim Newsome e273e23f41 Fix off-by-one error in assert.
Also only do work for debug RAM that actually exists on the target
(exposing the off-by-one error on 32-bit targets).

Change-Id: I37e0005b6a70e949286f1d6494716f3abea03c12
2016-09-29 10:40:50 -07:00
Tim Newsome 4dbc9962d3 Clear dmode triggers when we first halt the target
This helps repeated runs of the testsuite pass, and is probably a good
idea in general.

Change-Id: I89ed167968f8b8817c66f1718f374d0c502780c7
2016-09-29 10:23:46 -07:00
Tim Newsome 78fe0b56db Deal with dbus being busy in all cases.
Change-Id: Ifede6e05c3c4538f22a52cd0e9833cf3a9983d04
2016-09-29 08:28:31 -07:00
Tim Newsome b04d5e8821 Read idle, and test all debug RAM.
Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.

In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.

Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
2016-09-27 13:06:32 -07:00
Tim Newsome c67850b63d Only write to existing dram. Clear dbus error.
Old code would write 64 bytes of DRAM if the dbus was busy in
cache_write().

New code clears the dbus error condition when the bus is busy. (This
part is untested.)

Change-Id: Ia396fe819fa1828bb75726d85513b113cc9e13f0
2016-09-27 08:45:51 -07:00
Tim Newsome 54c65a9a4b Improve low-level logging.
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters up the
log/screen and is not generally helpful.
2016-09-23 14:16:24 -07:00
Tim Newsome 08228e6f53 Make more code use the scans "class".
Helps with consistency, and this is a rare commit that net deletes
lines.
2016-09-23 14:16:24 -07:00
Tim Newsome cf1dc0b6cb Implement hardware triggers that match spec.
It's basically working, but the following corner cases are failing:
    TriggerDmode
    TriggerLoadAddressInstant
    TriggerStoreAddressInstant
2016-09-23 14:16:24 -07:00
Tim Newsome 526bbc5284 Optimize read a bit.
Remove some unnecessary scans.
2016-09-23 14:16:24 -07:00
Tim Newsome c68b13ed67 Properly mark the cache as clean after its written
This reduces the number of scans, but I doubt it noticeably improves
performance.
2016-09-23 14:16:24 -07:00
Tim Newsome 243233c8b8 Convert some more code for 64-bit. 2016-09-23 14:16:24 -07:00
Tim Newsome b04f89076a Properly write 64-bit PCs. 2016-09-23 14:16:24 -07:00
Tim Newsome e3e745abb9 WIP for 64-bit support.
GPR register writes/reads seem to work.
2016-09-23 14:16:24 -07:00
Tim Newsome 2f1b6b5803 Stop using conditional writes.
It doesn't help, and makes the spec more complex. Now that I've proven
OpenOCD doesn't need it, I'll remove it from the spec.
2016-09-23 14:16:24 -07:00
Tim Newsome 5dbad6b0c9 Check for business in block reads. 2016-09-23 14:16:24 -07:00
Tim Newsome f8b0f4bf29 Check for exceptions in reads and writes. 2016-09-23 14:16:23 -07:00
Tim Newsome f5ae4d864c Add support for virtual priv register.
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
2016-09-23 14:16:23 -07:00
Tim Newsome 5de81da8f4 Remove commented out code.
Also added back the initial check that confirms debug RAM is written
correctly.
2016-09-23 14:16:23 -07:00
Tim Newsome a916d204b9 Optimize memory read.
Saves 8s on the full test suite.
2016-09-23 14:16:23 -07:00
Tim Newsome 32e7a962c3 Write fence.i before dret.
Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
2016-09-23 14:16:23 -07:00
Tim Newsome 4ced71b1f1 Log more. 2016-09-23 14:16:23 -07:00
Tim Newsome 20e2bfe3db Quickly read all GPRs on halt.
gdb will ask for them anyway, and one by one is slow.
StepTest went from 9.7s to 5.3s.
2016-09-23 14:16:23 -07:00
Tim Newsome 6fac5a41f8 Remove some hwbp debug code. 2016-09-23 14:16:23 -07:00
Tim Newsome 7dcc0681d4 Speed up some other operations. 2016-09-23 14:16:23 -07:00
Tim Newsome 1fdcfa7082 Speed up register read.
Don't scan an extra sequence just to read the return value.
2016-09-23 14:16:23 -07:00
Tim Newsome 27b94d36d0 Fix 32-bit build. 2016-09-23 14:16:23 -07:00
Tim Newsome 668070cc45 Faster download.
16K testcase:
Transfer rate: 53 KB/sec, 2222 bytes/write.
2016-09-23 14:16:23 -07:00
Tim Newsome 9aab0aa068 Minor cleanup. 2016-09-23 14:16:23 -07:00
Tim Newsome 06f6b5020c Use optimized cache/program write scheme for most
operations.
2016-09-23 14:16:23 -07:00
Tim Newsome a1875fbecf Working on optimized program running.
Makes a big difference on the XLEN code (29ms to 8ms). Now to use it in
more places.
2016-09-23 14:16:23 -07:00
Tim Newsome 9b9653ab7d Use hardware single step. 2016-09-23 14:16:23 -07:00
Tim Newsome eac8933b89 WIP on performance improvement.
Also implement empty arch_state to prevent occasional startup crash.
2016-09-23 14:16:23 -07:00
Tim Newsome 2d02e77bed Make this compile for 32-bit targets. 2016-09-23 14:16:23 -07:00
Tim Newsome aaa8ce10b8 Correctly figure out the number of extant hwbps. 2016-09-23 14:16:23 -07:00
Tim Newsome c471cfb63b Simple execute hardware breakpoint works. 2016-09-23 14:16:23 -07:00
Tim Newsome cb57aa55fa Deal with exceptions on register read.
Cache dpc, so we can restore it when it's clobbered by an exception.
2016-09-23 14:16:23 -07:00
Tim Newsome b81a846be5 Cache dcsr, since we're reading it anyway. 2016-09-23 14:16:23 -07:00
Tim Newsome c8430bb8f4 DebugTest.test_interrupt passes now. 2016-09-23 14:16:23 -07:00
Tim Newsome e10d407623 Speed up memory read a little. 2016-09-23 14:16:23 -07:00
Tim Newsome 4b19b7305f Save/restore T0 around block writes. 2016-09-23 14:16:23 -07:00
Tim Newsome 90f458e63f Reading/writing s1 now works. 2016-09-23 14:16:23 -07:00
Tim Newsome 0881092d9b Can successfully run to a swbp. 2016-09-23 14:16:23 -07:00
Tim Newsome c364bd0ab5 We can run to a software breakpoint, but
gdb doesn't notice we're halted once we hit it, even though riscv_poll()
is setting the target state to halted.
2016-09-23 14:16:23 -07:00
Tim Newsome 04cfc35147 Use the dram cache to save some scans. 2016-09-23 14:16:23 -07:00
Tim Newsome dce4a992a3 Single memory reads/writes work. 2016-09-23 14:16:23 -07:00
Tim Newsome 1b349df638 WIP hackery.
Main thing I added is code to output "verilog" for every JTAG op we do,
so we can run the same thing in simulation.
2016-09-23 14:16:23 -07:00
Tim Newsome f40862d87c Go through run-test/idle once per dbus access. 2016-09-23 14:16:23 -07:00
Tim Newsome 9f22176618 Reading registers appears to work. 2016-09-23 14:16:23 -07:00
Tim Newsome 84944ded87 Fix up some register stuff.
Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
2016-09-23 14:16:23 -07:00
Tim Newsome f634702aaf Successfully determine xlen.
There's a nop in there for no reason, though.
2016-09-23 14:16:23 -07:00
Tim Newsome db06dd45a0 Improve error checking. 2016-09-23 14:16:23 -07:00
Tim Newsome 041e0ccf9e Selecting dbus is sometimes necessary. 2016-09-23 14:16:22 -07:00
Tim Newsome 25e8b66b08 WIP registers. 2016-09-23 14:16:22 -07:00
Tim Newsome 3b60c3aa42 Fix bug when waiting for debugint to clear. 2016-09-23 14:16:22 -07:00
Tim Newsome 67009979ae Clearer debug logging. 2016-09-23 14:16:22 -07:00
Tim Newsome 3b3beb04ef WIP on registers. 2016-09-23 14:16:22 -07:00
Tim Newsome 482497c51a Blind implementation of write_memory. 2016-09-23 14:16:22 -07:00
Tim Newsome 50ca8ac373 Blind implementation of read_memory. 2016-09-23 14:16:22 -07:00
Tim Newsome 76fe7db0db In theory assert_reset/deassert_reset work. 2016-09-23 14:16:22 -07:00
Tim Newsome ea6836c5f6 WIP, blind coding. 2016-09-23 14:16:22 -07:00
Tim Newsome 413ab49dfd Blind coding new dbus behavior. 2016-09-23 14:16:22 -07:00
Tim Newsome feff2dd9e7 Always leave the TAP in Run-Test/Idle. 2016-09-23 14:16:22 -07:00
Tim Newsome 98f2fa897f Halt should work now. 2016-09-23 14:16:22 -07:00