Commit Graph

8985 Commits

Author SHA1 Message Date
Evgeniy Naydanov 08df077083 target/riscv: Handle error code in resume_prep
If hart can't change pc (e.g. it is running), resume command should
fail.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I14627366d574d806ea16262b7d305d8161f8bcc2
2023-04-10 17:19:20 +03:00
Mark Zhuang aa7344225b target/riscv: support log memory access128 for read
Change-Id: I9235150fa00c03a1d75d0b44a7500758daa56e2b
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-10 09:48:48 +08:00
Tim Newsome 0c76e263e3
Merge pull request #823 from panciyan/riscv
target/riscv: leaf PTE check PTE_W missing
2023-04-07 10:05:57 -07:00
Tim Newsome 15bb3e23b8
Merge pull request #821 from en-sc/en-sc/fix-reset-mharts
target/riscv: simplify reset for rtos harts
2023-04-06 09:54:15 -07:00
Tim Newsome 52b102318b
Merge pull request #830 from zqb-all/csr_32bit
target/riscv: set some csr size to 32
2023-04-06 09:40:59 -07:00
Tim Newsome 7e36bb6158
Merge branch 'riscv' into hypervisor
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-05 10:48:56 -07:00
Evgeniy Naydanov 1c168242e9 target/riscv: simplify reset
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
2023-04-05 19:14:45 +03:00
Tim Newsome c6ba4166e4
Merge pull request #816 from riscv/from_upstream
Merge up to commit '1293ddd65713d6551775b67169387622ada477c1' from upstream
2023-04-05 08:47:27 -07:00
Tim Newsome 2dc14117a7
Merge pull request #819 from zqb-all/fix_size_assert
target/riscv: support log memory access128
2023-04-04 11:05:52 -07:00
Tim Newsome d031d501cd flash/nor/spi: Move mt25ql02 to match upstream.
Change-Id: I7537c122d581ec1848a1e7902874506e0bbb6e31
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-04-04 10:51:29 -07:00
Mark Zhuang e284aa066e target/riscv: set some csr size to 32
Change-Id: I4703b7b8ad492b14dc8d188ebb8f645c568fd515
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-04-03 23:53:14 +08:00
Tim Newsome 38cf11abab
Merge pull request #824 from riscv/aia
target/riscv: AIA regs, check for H not V
2023-03-29 13:52:34 -07:00
Tim Newsome 4fdcc14e26 target/riscv: Set hypervisor bits.
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?

Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-29 13:40:39 -07:00
Mark Zhuang dfce1d2708 target/riscv: [NFC] rename variables named read/write
read/write is system function

Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 21:18:12 +08:00
Mark Zhuang 4cccda353c target/riscv: support log memory access128
Change-Id: I6b22c97f81fac26703b66d3dbd8b6d41aaea4875
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-03-25 20:31:42 +08:00
Tim Newsome 5bc9c207eb target/riscv: Don't ignore maskmax for icount.
Icount triggers don't have a maskmax field at all. This is a cut and
paste error.

Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24 13:41:06 -07:00
Tim Newsome 194a90186c target/riscv: AIA regs, check for H not V
Change-Id: Iac37b79dc737fd64a21dce83b3ef36f1a8aae118
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-24 09:21:48 -07:00
panciyan 1479eca38f target/riscv: leaf PTE check PTE_W missing
When permission bits R, W, and X in PTE all three are zero,
the PTE is a pointter to the next level of the page table;
otherwise, it is a leaf PTE. Here PTE_W is missed.

Change-Id: I82a4cc4e64280f0fcad75b20e51b617520aff29b
Signed-off-by: panciyan <panciyan@eswincomputing.com>
2023-03-23 02:45:42 +00:00
Tim Newsome d744207943
Merge pull request #815 from riscv/s_aia
target/riscv: Expose S?aia CSRs if they're on the target.
2023-03-20 08:45:13 -07:00
Tim Newsome 1c07a207e3 gdb_server: Keep working if gdb requests a non-existent reg
Change-Id: Ica55a227f7df4f0606fa1ac071bca172411e9230
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-17 09:48:41 -07:00
Tim Newsome 2cd3436002 Fix build.
Change-Id: I89de7dc21d7958531ec9619905d3d8c4f54a3acf
2023-03-16 18:08:25 -07:00
Tim Newsome 868ebdd89c Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.

Conflicts:
	.travis.yml
	contrib/loaders/flash/stm32/stm32f1x.S
	contrib/loaders/flash/stm32/stm32f2x.S
	doc/openocd.texi
	src/rtos/FreeRTOS.c
	src/server/gdb_server.c
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c
	src/target/riscv/riscv.h
	src/target/riscv/riscv_semihosting.c
	tcl/target/esp_common.cfg
	tcl/target/gd32vf103.cfg
	tools/scripts/checkpatch.pl

Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2023-03-16 18:02:35 -07:00
Tim Newsome 3387015af0
Merge pull request #800 from en-sc/en-sc/try-all-trigs-in-maybe-add-trig
Try all triggers in maybe_add_trigger_t*
2023-03-16 16:58:12 -07:00
Tim Newsome 2c760b6317 Expose S?aia CSRs if they're on the target.
Untested, because I don't have a target that implements this.

Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16 15:37:06 -07:00
Tim Newsome eb8cabf821 Update encoding.h.
Change-Id: I1b6d2cac86ec485310761b73370fb2667ebb3bbd
2023-03-16 11:27:06 -07:00
Tim Newsome 750f7b4bc3
Merge pull request #812 from XuHangHub/riscv
target/riscv: fix the bug of using S2 register in read_memory_progbuf
2023-03-15 09:29:03 -07:00
Evgeniy Naydanov 55a576037e Try all triggers in maybe_add_trigger_t2 and _t6
It is possible for triggers of the same type to support different match
field values, so it is needed to try all the triggers, not just the
first one.

Fixes issue #788.

Signed-off-by: Evgeniy Naydanov evgeniy.naydanov@syntacore.com
Change-Id: I4c9fbc98bae7259377456d9ad8e770232724a592
2023-03-15 13:05:33 +03:00
Hang Xu 2370d78249 target/riscv: fix the bug of using S2 register in read_memory_progbuf
We should avoid using x16~x31 register in program buffer because there
are no such general purpose registers in RVE(Embedded) extension.
For targets that support rvE, when the parameter increment=0
and count>1 of the read_memory_progbuf function, openocd will cause
an error due to the use of the s2 register.
For example:
{Command} {riscv repeat_read} count address [size=4]

Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435
Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
2023-03-12 04:01:05 +00:00
Tim Newsome dcb0b5b976 target/riscv: Remove unused address_in variable.
Change-Id: Iead46b543a3b866f36b4d61a8824b6335dab276a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-10 10:58:46 -08:00
Chao Du 59e368e308
Calculate the FreeRTOS type sizes and offsets more adaptively. (#806)
* Calculate the FreeRTOS type sizes and offsets more adaptively.

The definition of TickType_t varies between different targets. And it is also related to configUSE_16_BIT_TICKS option.
Thus introduce a new command to make sure we are using a correct ticktype size.

Change-Id: I9e38b331a9f07b96eb9a2c259e32377fca0106ad
Signed-off-by: Chao Du <duchao@eswincomputing.com>

* redundant semicolon.

Change-Id: Ia21f0537e476099d8fe519ef78b3328d14123a38

* Update after review.

Change-Id: I1825185ec9b0557d7e01f34a8f366661b3734aa7

* update doc

Change-Id: I24b21c88b02ca3d76f1362f2545e86c068fc0ec6

---------

Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-03-08 16:24:06 -08:00
Tim Newsome 81b37bb6b5 helper: Add missing entry to jep106.inc.
Change-Id: I08dc57f44f3e551a5ac4e3befcd8a7fe12d840e0
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-06 09:13:52 -08:00
Tim Newsome e2ec1894ae flash: Remove duplicate entry for micron mt25qu01.
This probably crept in when merging in upstream in the past.

Change-Id: Iccce4515b6b5d4a90773f6d432754b065fb240bb
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-06 09:04:39 -08:00
Tim Newsome 4f97898889 Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstream
Conflicts:
	doc/openocd.texi
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I8cd557a10c3d5beeaed05ecc05d4c325a9ee7e70
2023-02-28 10:54:48 -08:00
Chao Du 1655620c0c Set the current_thread when no FreeRTOS task was created.
The 'current thread' was not set when no FreeRTOS task created. Which could lead a wrongly invoking of freertos_get_thread_reg_list.

Change-Id: I0e0f8327080ef698d7ed4aae5ac2a630d532ddeb
Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-02-17 07:45:05 +00:00
Tim Newsome 87f9e590b9
Merge pull request #799 from riscv/icount
Add `riscv icount` command.
2023-02-16 10:16:30 -08:00
Anatoly Parshintsev da5d2748e6
target/riscv: hide_csrs configuration option (#787)
* target/riscv: hide_csrs configuration option

This option allows users to mark certain CSRs as hidden so they could be
expluded from *reg* output and target.xml

Change-Id: Iddf8456cd3901f572f8590329ebba5229974d24a

* Update doc/openocd.texi

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

---------

Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2023-02-15 09:53:37 -08:00
Jan Matyas 872ebb14ca
Add command "exec_progbuf" (#795)
* Add command "exec_progbuf"

Command "exec_progbuf" allows to execute a user-specified sequence
of instructions using the program buffer.

Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Updated the doc:

- Minor reword and reorder of the sentences.
- Added information about C-instructions in progbuf.
- Fixed a typo (per the review).
- Added examples.

Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Cosmetic changes

Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

---------

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-15 09:53:03 -08:00
Tim Newsome 9cafc75678
Merge pull request #796 from Du-Chao/freertos_log
Improve a debug log in freertos_update_threads()
2023-02-15 09:52:36 -08:00
Tim Newsome fb3376b7f0 Add `riscv icount` command.
Also refactor shared code for clearing itrigger/etrigger/icount.

Change-Id: Iac2e756332c89d2ed43435391e3c097abc825255
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-15 09:31:44 -08:00
Tim Newsome a57fc5e78c
Merge pull request #794 from riscv/fix-fence-instruction
Fix opcode for the "fence" instruction
2023-02-14 10:51:13 -08:00
Tim Newsome 2b4826cd32
Merge pull request #797 from riscv/Zve32
If XLEN=64 and vsew=64 fails, fall back to vsew=32.
2023-02-10 12:36:48 -08:00
Tim Newsome f4f3ce7db7 Don't reuse a single riscv_program.
Because riscv_program_exec() tries to add an instruction every time
through.

This would cause an error accessing vector registers where VL > 14(?).

Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10 11:51:21 -08:00
Tim Newsome abb918685f If XLEN=64 and vsew=64 fails, fall back to vsew=32.
This should make vector accesses work on 64-bit harts that implement
Zve32*. There doesn't appear to be any way to easily determine what vsew
values are allowed, so try and notice the failure.

Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10 11:51:17 -08:00
Parshintsev Anatoly 5845f3b71c CSR_MCOUNTEREN should not exist if U-mode is not supported
Change-Id: I1a2420fb88bd3ee37f6a539992e8dc119fdd6e0e
2023-02-10 02:08:40 +03:00
Tim Newsome 344e8bd263 Print out debug value after the assignment is made.
Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
2023-02-08 11:02:51 -08:00
Tim Newsome 91552c7999 Move yes_no_maybe_t into riscv.h.
Change-Id: I5bbdc1af3147e05e25612bf496f409111248c979
2023-02-08 11:02:20 -08:00
duchao 9cc6749370 Improve a debug log in freertos_update_threads()
To make the log more accurate and comprehensible. In case the offset is
non-zero.

Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-02-08 03:01:57 +00:00
Jan Matyas 2c96555c73 Fix opcode for the "fence" instruction
OpenOCD currently uses improper "fence" instruction:
"FENCE" opcode with empty predecessor and successor sets.

Such instruction has no effect and is reserved for future use
as a HINT instruction (RISC-V Unprivileged ISA spec V20191213,
section 2.9).

This patch fixes it by using the proper "fence rw,rw"
instruction.

Change-Id: Ia2a66059009153efef27279410850ddfd73dae38
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-01 14:59:33 +01:00
Erhan Kurubas dfbbfac4d7 rtos/nuttx: add riscv stacking info
Tested with Espressif ESP32-C3 MCU

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ia71ace4909f2dc93ddc07a2ec5524cf374f1937c
Reviewed-on: https://review.openocd.org/c/openocd/+/7251
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-28 15:50:33 +00:00
Erhan Kurubas 463df95215 rtos/nuttx: move stacking info to the new nuttx stackings file
Other OSes have separate files to keep stack register offsets.
Adding them for NuttX as well will provide a clearer way to expand.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1428fefefa199a95431f2073c0279dd7028ad8da
Reviewed-on: https://review.openocd.org/c/openocd/+/7250
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-28 15:43:02 +00:00
Marian Buschsieweke 6e67f1473a helper: Add generic little endian CRC32 function
This generalizes the little endian CRC32 function used in the OR1K
target and moves it to a common helper, so that other places do not need
to reinvent the wheel. It is directly used in the OR1K target.

Change-Id: I0e55340281a5bfd80669bb1994f3a96fecc1248a
Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7415
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-21 22:57:33 +00:00
Tomas Vanek 92dd917f5a flash/nor/psoc4: drop jtag_poll_mask() from flash write
Polling the target makes no harm during PSoC 4 flash write in the current
OpenOCD code. Don't mask it.

Change-Id: I6625ded0162ee3a96b92188844d0d2d6c30101c2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7162
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-21 22:56:32 +00:00
Antonio Borneo cda39f929e jtag: hla: use generic helper for commands 'jtag newtap' 'swd newdap'
The commands 'jtag newtap' and 'swd newdap' have to work either on
HLA transport and on standard JTAG/SWD. Having a dedicated
implementation for HLA is a non-sense.

Reuse the generic code jim_jtag_newtap() and drop the files
hla_tcl.[ch] as they are now empty.

Change-Id: I9dabbdc2a6f338f23b2fd3ed1a4dc3da0200c080
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7428
Tested-by: jenkins
2023-01-15 15:12:05 +00:00
Antonio Borneo 7a890a8f25 jtag: parse command options in 'swd newdap'
The same code is currently used for commands 'jtag newtap' and
'swd newdap' (plus dapdirect versions), but for SWD case the code
skips the parsing of the command line as not every flag is used.
This has the drawback that syntax errors get unchecked.

Move the check about the transport so the command line get always
parsed even when the corresponding flags are not useful.

Change-Id: I596c3beb04e9e8a9ebe6ee68a61395b679d43b3e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7427
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-01-15 15:11:50 +00:00
Marc Schink dbb42ca18d flash/nor/stm32l4x: Add revision 'X' and 'C' for STM32U575/585 devices
Change-Id: I4d950dc0a1421036418f2e5c1f0ed8eca86efc1a
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7390
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:10:59 +00:00
Tomas Vanek 5292c7eae9 jtag/drivers/cmsis_dap: prevent conn/discon workaround before line reset
The line reset SWD sequence is used quite often in SWD multidrop mode.
Prevent the ugly connect/disconnect adapter firmware bug workaround
to be called before each line reset.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Id85bff075dba9077e4e501e2cdcfd64d5d9d0531
Reviewed-on: https://review.openocd.org/c/openocd/+/7381
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:10:16 +00:00
Tomas Vanek 630cb5ea4d jtag/drivers/cmsis_dap: speed up long transfers using DAP_TransferBlock
DAP_TransferBlock command saves n - 3 bytes in comparison to DAP_Transfer,
where n is number of transfers.

Use DAP_TransferBlock optionaly to save some USB bandwidth.

The change increases the speed of the write transfer
from 40 KiB/s to 42 KiB/s @ USB FS, adapter speed 1000.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ifde0159cfd44481d2b81b90daa088e731c03e26d
Reviewed-on: https://review.openocd.org/c/openocd/+/7372
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:09:47 +00:00
Tomas Vanek 40bac8e8c4 jtag/drivers/cmsis_dap: improve USB packets filling
DAP write transaction occupies 5 bytes of a command packet.
DAP read transaction needs just one byte in a command packet
and expect 4 bytes in a response.

The fixed maximal number of transactions in a packet caused
packet filling less than optimal.

Compute both command and expected response sizes based on
read or write direction of each transaction.
Run the queue if one of sizes does not fit into a packet.

The change increases the speed of the mostly read transfer
from 36 KiB/s to almost 40 KiB/s @ USB FS, adapter speed 1000
due to reduction of adapter inserted RDBUFF reads.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ib70812600eaae0403b8ee8673b6f897348496569
Reviewed-on: https://review.openocd.org/c/openocd/+/7364
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:09:07 +00:00
Tomas Vanek 3d3d35c9b8 jtag/drivers/cmsis_dap: introduce packet_usable_size
USB bulk backend needs to avoid zero sized USB packets
sent after each full sized packed for performance reasons.

HID backend uses fixed size HID reports so the full size
of the report can be utilized.

Introduce packet_usable_size to reflect it.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I34094c9edac5730624480711cbd6aa65883c47c7
Reviewed-on: https://review.openocd.org/c/openocd/+/7363
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:08:49 +00:00
Tomas Vanek 600d0165cc jtag/drivers/cmsis_dap: use unsigned types
Not all variables converted, JTAG part is left as is.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ie9cc890769a2f53cb3a07fd457030e1b98910d44
Reviewed-on: https://review.openocd.org/c/openocd/+/7362
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:08:05 +00:00
Tomas Vanek a9b48a6f48 jtag/drivers/cmsis_dap: use dap parameter instead of cmsis_dap_handle
Replace the direct dereference of cmsis_dap_handle by dereference
of the dap function parameter wherever possible.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I32601dbe0270267642720a8524706aa76d187c3b
Reviewed-on: https://review.openocd.org/c/openocd/+/7361
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:07:51 +00:00
Tomas Vanek 128736d23f jtag/drivers/cmsis_dap: move pending request FIFO
Move all pending request FIFO related variables to
the struct cmsis_dap

Pure refactoring, no functional changes.

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I2cea9c1e265ac102ec0f314767b8b9afdcda9ee9
Reviewed-on: https://review.openocd.org/c/openocd/+/7360
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:07:38 +00:00
Jian-Hong Pan 9ffda10298 flash/nor, contrib/loaders: move numicro M0 write assembly to contrib/loaders
Simply move numicro M0 flash write assembly to contrib/loaders. Also,
modify corresponding Makefile and generated numicro_m0.inc.

To make the path more general, this patch rename the path
"contrib/loaders/flash/numicro_m4" to "contrib/loaders/flash/numicro" as
well.

Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Change-Id: I9adea24c2b3c97319a9b015cf50257f3d131dc26
Reviewed-on: https://review.openocd.org/c/openocd/+/7346
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:04:25 +00:00
Jian-Hong Pan 63336f4aaf flash/nor, contrib/loaders: move numicro M4 write assembly to contrib/loaders
Simply move numicro M4 flash write assembly to contrib/loaders. Also,
add corresponding Makefile and generated numicro_m4.inc.

Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Change-Id: I22b8be0a245857335b11bd0b538db415fc34748d
Reviewed-on: https://review.openocd.org/c/openocd/+/7343
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:04:06 +00:00
Zale Yu d1b0cb2b77 flash: support Nuvoton M541 & NUC442/472 series
This patch is picked from the flash part of OpenOCD-Nuvoton's commit
("flash: supported Nuvoton M4 series. jtag: Used HW reset instead of
auto reset. tcl: added a configuration file for Nuvoton M4 series.") [1]
to support flashing Nuvoton's Cortex-M4 chips: M541 & NUC442/472 series.

The code comes from the commit basically. Jian-Hong Pan tweaked for the
compatibility with current OpenOCD. So, leave the author as Zale Yu.

[1]: https://github.com/OpenNuvoton/OpenOCD-Nuvoton/commit/c2d5b8bfc705

Signed-off-by: Zale Yu <cyyu@nuvoton.com>
Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Change-Id: I9dc69eccb851df14c1b0ce2f619d7b3da0aa92aa
Reviewed-on: https://review.openocd.org/c/openocd/+/7329
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:03:09 +00:00
Zale Yu 776e045de0 flash/nor/numicro: reorder the parts list
This patch is picked from the flash part of OpenOCD-Nuvoton's commit
("flash: supported Nuvoton M4 series. jtag: Used HW reset instead of
auto reset. tcl: added a configuration file for Nuvoton M4 series.") [1]
It reorders Nuvoton MCU part list and spreads out the way to define the
banks' base address & size of the parts.

The code comes from the commit basically. Jian-Hong Pan tweaked for the
compatibility with current OpenOCD. So, leave the author as Zale Yu.

[1]: https://github.com/OpenNuvoton/OpenOCD-Nuvoton/commit/c2d5b8bfc705

Signed-off-by: Zale Yu <cyyu@nuvoton.com>
Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com>
Change-Id: I1f21f54dfdf53e5b8ea04d803347d1dbc8c321a0
Reviewed-on: https://review.openocd.org/c/openocd/+/7339
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:01:23 +00:00
Boris-Chengbiao Zhou 11ee500bff target/armv7m: Rename xPSR to xpsr
The org.gnu.gdb.arm.m-system GDB feature defines the name in lowercase
letters.[1] Not adhering to the definition can cause issues with tools
interacting with the GDB which expect the correct casing.

[1]: https://sourceware.org/gdb/onlinedocs/gdb/ARM-Features.html

Change-Id: I0b6584a78f86b053947d79686baad5dac3ec4a00
Signed-off-by: Boris-Chengbiao Zhou <bobo1239@web.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7292
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 15:01:03 +00:00
Tarek BOCHKATI 66da6f20e4 flash/stm32l4x: avoid multiple assignments
Change-Id: I6d8e0fbfa7e05f26295fc22733c65c11f7460b51
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7282
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
2023-01-15 15:00:38 +00:00
Jan Matyas 30631224da adapter: Improve three adapter-related prints
- Do not warn the user about adapter speed not being set
  if the selected adapter does not support configurable speed.
  This would be confusing to users.

- Minor reword in the "adapter speed is not selected" warning.

- Print the adapter name in the "adapter doesn't support
  configurable speed" log entry

- Another minor reword: autoselect --> autoselecting

Signed-off-by: Jan Matyas <matyas@codasip.com>
Change-Id: I4c198b547544fd8199921f092153562c5f159134
Reviewed-on: https://review.openocd.org/c/openocd/+/7269
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:57:25 +00:00
Antonio Borneo f2fc23e16b riscv: drop deprecated command 'riscv test_sba_config_reg'
Change-Id: I51c1b1cb3de8cb86ee38280fa3f035f6f7a63dbc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7272
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
2023-01-15 14:56:59 +00:00
Antonio Borneo 27edeb7757 riscv: drop deprecated command 'riscv set_prefer_sba'
Change-Id: I546efe4e1a6b673b26cfb4a74b5c3809fecda49c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7271
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
2023-01-15 14:56:50 +00:00
Tomas Vanek 0979cbc5bc flash/nor/rp2040: make SPI flash ID detection optional
Do not read ID from SPI flash and suppress autodetection
if non-zero flash bank size is configured.

Change-Id: Idcf9ee6ca17f9fa89964a60da7bf11e47b4af5e7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7241
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:55:25 +00:00
Tomas Vanek 59763653c6 target/cortex_m: add SMP support for Cortex-M
Cortex-M support for SMP multicore targets.

This SMP implementation unlike older ones does not act
on the first halted target found. It polls targets
until a SMP group is finished and stores eventual
'halted' events instead of emitting them. As soon as polling
of a group is done, poll proceeds with SMP related tasks.
This approach improves detection of a reason why debug
stopped - a correct reason is detected for all targets,
not only for the first found.
Drawback: SMP target group should be defined in the same
order as the targets were defined.

Obsolete gdb 'J' packet/smp_gdb command core switching is not implemented,
use with rtos hwthread.

Only one core is resumed if debug_execution is requested.

Some ideas taken from Graham Sanderson's [4936]
and src/target/aarch64.c

Added error checking of armv7m_restore_context().

Change-Id: I60f5b79e74b624dc2b5835ff10e38ac2ccb23792
Link: [4936]: target/cortex_m: Add smp support for Cortex M | https://review.openocd.org/c/openocd/+/4936
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:54:50 +00:00
Tomas Vanek 083100fca3 target/armv7m: check error in armv7m_restore_context()
Return error if arm.write_core_reg() fails.

Change-Id: Ide8f5aa5958532b202dc9f5e13d3250a706d832d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7238
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:54:27 +00:00
Koudai Iwahori d0436b0cda armv8: Add support of pointer authentication
When pointer authentication is enabled, some upper bits of the link
register (LR[63:VA_SIZE]) are used to store a signature. Therefore, GDB
need to remove the signature to get backtraces.
GDB has support of pointer authentication. When pointer authenticaion is
enabled, GDB requests 8-bytes mask to the target to remove the
signature. mask[63:VA_SIZE] should be all set and mask[VA_SIZE-1:0]
should be all cleared. GDB removes the signature by addr&~mask or
addr|mask.
I added a feature to provide the mask for pointer authentication.

Signed-off-by: Koudai Iwahori <koudai@google.com>
Change-Id: I56fbbf9cc23619b6536ecd326f350c8bf137f322
Reviewed-on: https://review.openocd.org/c/openocd/+/7248
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:51:44 +00:00
James G. Smith d96dc47ef6 src/rtos/eCos : Support per-build configuration specific structure layouts
Extended feature. This is a large patch, but is self-contained to the
eCos support and does not affect any other openocd functionality. It
does NOT affect existing eCos RTOS plugin users where their
applications do not provide the extended symbolic helper
information. If the helper symbols are not available the rtos support
code will behave as before. This "dynamic" functionality is *required*
because eCos does NOT have a fixed/hardwired, known, layout for the
thread descriptor structure. The per-application build eCos
configuration can affect the shape of the thread descriptor structure
(field presence, and hence offsets of subsequent fields) such that
constant values cannot be used to consistently interpret all possible
eCos application configurations. For historical reasons, there is not
yet a consistent namespace for the helper symbols across eCos HALs
hence the support is currently limited to specific architectures
(Cortex-M and ARM/Cortex-A). No new Clang analyser warnings are raised
by this changeset.

Change-Id: Ib3a36877326eeb56595cbca55e21b9e59a59c98a
Signed-off-by: James G. Smith <jsmith@rallysmith.co.uk>
Reviewed-on: https://review.openocd.org/c/openocd/+/6275
Reviewed-by: Alex Schuilenburg <alex.schuilenburg@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-01-15 14:51:21 +00:00
Fawaz Tirmizi 9a7781ff8c flash/nor/spi: Add issi is25lq040b to device list
The HiFive Inventor uses this flash chip, so adding it will allow for
openocd to be used to program it. These values were taken from the
chip's documentation.

Signed-off-by: Fawaz Tirmizi <fawaz@rivosinc.com>
Change-Id: I15c9d35f99d4500f73134cdc2d1b9ab6279b491c
Reviewed-on: https://review.openocd.org/c/openocd/+/7135
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:50:46 +00:00
Erhan Kurubas 0708ccead4 target/xtensa: remove needless target_was_examined check
In any case flag will be set as examined.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I5177ee656f726a807269e2f4725223f50e49e855
Reviewed-on: https://review.openocd.org/c/openocd/+/7231
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:47:59 +00:00
Kyle Schwarz 0c28006cf2 flash/nor/avrf: add ATmega32U4 support
Add new chip info and tcl target

Change-Id: Ib9d33d1b145a8659857b7a6cc9c5acba047f41d1
Signed-off-by: Kyle Schwarz <zeranoe@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7081
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15 14:47:30 +00:00
Antonio Borneo 95603fae18 openocd: revert workarounds for 'expr' syntax change
With OpenOCD v0.12.0 released, drop the workarounds for 'expr'
syntax change by reverting:
- commit 320043c054 ("openocd: fix for polling during "expr"
  computation");
- commit c7eaaf6204 ("openocd: prepare for jimtcl 0.81 'expr'
  syntax change").

Replace the call to target_call_timer_callbacks_now() with call
to target_call_timer_callbacks().

Change-Id: Iae5afc50e3f688e11176a52648efc9a6577a9a11
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7405
Tested-by: jenkins
2023-01-15 14:46:57 +00:00
Antonio Borneo da34e36cdb nds32: drop it, together with aice adapter driver
The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.

The arch nds32 has been dropped from Linux kernel v5.18-rc1.

For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.

Let it r.i.p. in OpenOCD git history.

While there, drop from checkpatch list the camelcase symbols that
where only used in this code.

Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
2023-01-15 14:46:36 +00:00
Antonio Borneo d92ebb5ab4 jtag: esp_usb_jtag: remove macro __packed
In FreeBSB 13.0 the build fails due to redefined macro __packed.

	src/jtag/drivers/esp_usb_jtag.c:19:9: error: '__packed' macro
	    redefined [-Werror,-Wmacro-redefined]
	#define __packed __attribute__((packed))
	        ^
	/usr/include/sys/cdefs.h:223:9: note: previous definition is here
	#define __packed        __attribute__((__packed__))
	        ^
	1 error generated.

Drop the macro and align the code with the other files in OpenOCD
project, where the attribute is directly applied without using a
macro.

Change-Id: I89ae943e77036206d40d4d54172cd4a73e76e5c5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Wojciech Puchar <wojtek@puchar.net>
Reviewed-on: https://review.openocd.org/c/openocd/+/7435
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-01-11 17:02:44 +00:00
Marcin Niestroj 7dd5b6a464 rtt: fix corner-cases of finding control block
This patch fixes two corner-cases of finding RTT control block.

The first one is when there was a partial match (even single byte) at
the end of loaded buffer (uint8_t buf[1024]), but this was not part of
full match. In that case `cb_offset` was not updated correctly and the
returned `*address` was lower by the legth of the partial match. In case
of searched 'SEGGER RTT' (the default control block ID) string, it was
enough to match `buf[1023] == 'S'`, which is quite likely to happen, and
the `*address` was offset by 1 (e.g. it was 0x20000fff instead of
0x20010000).

Updating (or even maintaining) `cb_offset` is not needed, as start
address of control block can be calculated based on memory address that
was loaded into `uint8_t buf[1024]`, the offset within this buffer and
the length of expected string.

The second issue is when control block is prepended with a byte that
matches first ID character, e.g. there is `SEGGER RTT` control block ID
is prepended by another `S`, making memory contents be `SSEGGER RTT`. In
that case there was no match found.

Fix that issue by making sure that tested byte is always compared with
first byte of expected control block ID.

While at it, change names of local variables to better describe their
meaning.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Change-Id: I12aa6e202bf12bedcbb888ab595751a2a2518a24
Reviewed-on: https://review.openocd.org/c/openocd/+/7429
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-11 17:02:25 +00:00
Parshintsev Anatoly 71e3d0aecb target/riscv: added support for missing VCSR register
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
2023-01-10 17:41:13 +03:00
Tim Newsome 43ea20dfbb
Merge pull request #777 from riscv/itrigger
target/riscv: Add `riscv` `itrigger` and `etrigger` commands.
2023-01-04 10:31:55 -08:00
Tim Newsome 5a72150604
target/riscv: Remove `riscv test_sba_config_reg` command. (#780)
This command is supposed to be a start at a compliance test for system
bus access. It doesn't pass against spike because it doesn't handle all
cases where the interface might be busy. It's not documented. As far as
I know nobody uses it.

So delete 400 lines of code instead of trying to fix it.

Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:54:33 -08:00
Tim Newsome d2ebfc8770 target/riscv: Use unsigned int for trigger indexes.
Change-Id: I1f7cf3a5c8b86f3d6825f45a67ff05822ea67d28
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:08:18 -08:00
Tim Newsome 9efa7775d4 target/riscv: Read back tdata2 in set_trigger()
Change-Id: I2a9271c66565a4c93de3322e14be8b75577ed1b6
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:06:12 -08:00
Tim Newsome 6c027e0df4 target/riscv: Add `riscv etrigger` command.
Change-Id: I7982231c5067b82e4ddb2999bca51dba06ccac7a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02 13:54:45 -08:00
Tim Newsome 0b022a349e target/riscv: Add `riscv itrigger` command.
This lets the user set an itrigger trigger, which doesn't fit in the
normal breakpoint abstraction.

This implementation only allows control of a single itrigger. Hardware
could support more than one, and that may be useful to catch different
interrupts in different execution modes. But it would make the code/UI
more complex and it feels like an unlikely use case.

Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02 13:54:35 -08:00
Tim Newsome 2258a59a0f target/riscv: Use macros for trigger types.
Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27 12:54:12 -08:00
Tim Newsome eb8bb957d4
flash: fix clang static analyzer build errors (#778)
Fixes "variable set but not used" errors.
Tested with Homebrew clang version 13.0.1

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ia90baf5b4857db2b5569ebe6adbbb832de772aad
Reviewed-on: https://review.openocd.org/c/openocd/+/6971
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Co-authored-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-12-27 10:54:26 -08:00
Antonio Borneo 77c281d2df cortex_m: handle armv8m cores without security extension
Cores armv8m, e.g. Cortex-M33, can be instantiated without the
optional Security Extension.
In this case, the secure registers are not present and when GDB
try accessing them it triggers a set of errors.

For armv8m cores without security extension, don't provide to GDB
the description of the secure registers.

Change-Id: I254478a4cf883e85b786df3f62c726b2f40d88d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7402
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-12-18 21:52:41 +00:00
Antonio Borneo c913e4d5a6 jtag: fix build with configure --enable-verbose
With flag --enable-verbose, configure enables compiling some
conditional code that with new gcc triggers an error:
	error: '%04x' directive output may be truncated writing
	between 4 and 8 bytes into a region of size 5
	[-Werror=format-truncation=]

Extend the buffer to contain the full 8 bytes of %04x on a 'int'
and change the limit in snprintf.
Skip the intermediate buffer 's[4]'.
Align the code to the coding style.

Change-Id: Ifc8a6e4686555578a7355a1f6049471fd5e31913
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Karl Hammar <karl@aspodata.se>
Reported-by: Tommy Murphy <tommy_murphy@hotmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/376/
Reviewed-on: https://review.openocd.org/c/openocd/+/7403
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-12-18 21:50:17 +00:00
Dan Stahlke 77c7abe4e7 at91samd: wait for nvm ready
Flashing a SAMD21J17D was failing during NVM erase.  The samd21
datasheet specifies that one cause of error conditions is executing an
NVM command while the previous command is still running.  The solution
is to wait for INTFLAG.READY after a command is issued.

SAMD21J17A was not exhibiting this problem.  Perhaps the later silicon
revision has slower NVM erase times.

Signed-off-by: Dan Stahlke <dan@stahlke.org>
Change-Id: I19745dae4d3fc6e3a7611dcac628e067cb41e0f0
Reviewed-on: https://review.openocd.org/c/openocd/+/7391
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-12-17 09:33:40 +00:00
Antonio Borneo 0a829efda5 driver: vdebug: fix mode of cmd 'vdebug mem_path'
The command 'vdebug mem_path' is reported in the documentation as
'{Config Command}', but the code sets mode = COMMAND_ANY.
The code of the commands sets some value that is only used during
the init phase, so the documentation is correct.

Change mode of command 'vdebug mem_path' to COMMAND_CONFIG.

Change-Id: Icb940fe382cbc75015273b35dcc8a88fc2a7d0ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7395
Tested-by: jenkins
Reviewed-by: Jacek Wuwer <jacekmw8@gmail.com>
2022-12-17 09:33:06 +00:00
Antonio Borneo 2b6fe8f1ab target: fix assert in 'monitor profile' on constant PC
When target is stopped in WFI/WFE or is in an infinite loop, the
sampled PC will always return the same value.
Command 'profile' requires that distance between min and max PC
should be at least 2, which is not the case for constant PC, and
incorrectly enforces the check through as assert().

Move the code that reads the optional parameters 'start' and 'end'
and check the gap 'end - start' before running the profile.
For self-computed min and max, increase max (or decrease min) to
match the required constraint.
Drop the assert().

Change-Id: I2be8df8568ce8c889923888c492e4f7ce354b16b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/370/
Reviewed-on: https://review.openocd.org/c/openocd/+/7400
Tested-by: jenkins
2022-12-17 09:32:34 +00:00
Antonio Borneo a51ac964c6 target: fix unsigned computation in 'monitor profile'
The implementation of command 'monitor profile' has few
issues:
- the address_space is a signed int, so cannot wrap-around on
  space over INT_MAX;
- max address is incremented without check for overflow;
- assert() used on errors instead of returning error codes;
- only handles 32 bits PC;
- output file created and left empty on error.

This patch fixes the first two issues, as a wider fix would be too
invasive and should be postponed in a following series.

Change-Id: Id8ead3f6db0fd5730682a0d1638f11836d06a632
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/370/
Reviewed-on: https://review.openocd.org/c/openocd/+/7394
Tested-by: jenkins
2022-12-17 09:32:09 +00:00
Antonio Borneo a6b0221952 target: cortex_a: fix clang error core.CallAndMessage
Clang complains about the variable 'orig_dfsr' that can be used
uninitialized both in cortex_a_read_cpu_memory() and in
cortex_a_write_cpu_memory().

The issue is caused by an incorrect error path that used to jump
through 'goto out'. The code after the label 'out' is specific to
handle the case of an error during memory R/W; it is incorrect to
jump there to handle an error during the initialization that
precedes the memory R/W.

Replace the 'goto out' with 'return retval'.
Remove the label 'out' that is now unused.

Change-Id: Ib4b140221d1c1b63419de109579bde8b63fc2e8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7393
Tested-by: jenkins
2022-12-17 09:31:29 +00:00
Antonio Borneo c6fe10de75 arm_adi_v5: fix SIGSEGV due to failing re-examine
Commit 35a503b08d ("arm_adi_v5: add ap refcount and add get/put
around ap use") modifies the examine functions of mem_ap, cortex_m,
cortex_a and aarch64 by calling dap_put_ap() and then looking again
for the mem-ap and calling dap_get_ap().
This causes an issue if the system is irresponsive and the examine
fails and left the AP pointer to NULL. If the system was already
examined the NULL pointer will cause a SIGSEGV.

Commit b6dad912b8 ("target/cortex_m: prevent segmentation fault
in cortex_m_poll()") proposes a fix for one specific case and only
on cortex_m.

Modify all the examine functions by skipping look-up for the AP if
it was already set in a previous examine; the target's AP is not
supposed to change during runtime.

Remove the partial fix for cortex_m as it is not needed anymore.

Change-Id: I806ec3b1b02fcc76e141c8dd3a65044febbf0a8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 35a503b08d ("arm_adi_v5: add ap refcount and add get/put around ap use")
Reviewed-on: https://review.openocd.org/c/openocd/+/7392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-12-17 09:30:45 +00:00
Nima Palizban 2278878a05 src/target/mips_m4k.c: set missing flag in set_watchpoint
Without the fix, will see "Can not find free FP Comparator" error log

Change-Id: Id0d91cc02b7055e44d27507f9c05ccd48ff49838
Signed-off-by: Nima Palizban <n.palizban@gmail.com>
Fixes: fb43f1ff4e (target: Rework 'set' variable of break-/watchpoints)
Reviewed-on: https://review.openocd.org/c/openocd/+/7389
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-17 09:29:32 +00:00
Evgeniy Naydanov 04887d3b68 Fix jim_target_smp for smp rtos target
If multiple targets are specified as -rtos <rtos_type>, the
rtos_update_threads was called only if the last target was specified as
rtos, which is inconsistent with other checks of whether or not smp target
is an rtos one.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: Ie52bc6b6c8f841d31b9590fcbc44e985d3cba0eb
Reviewed-on: https://review.openocd.org/c/openocd/+/7244
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-03 09:27:00 +00:00
Koudai Iwahori 4fe3997294 hwthread: Restore current_threadid in hwthread_update_threads
When OpenOCD receives a step-execution command from GDB and the target
is configured as rtos=hwthread, OpenOCD reconstructs the thread-info.
However, OpenOCD does not restore the thread id which is currently
selected by GDB. Due to this issue, OpenOCD sends the information of
wrong thread to GDB after the step execution.
This commit fixes the above issue by adding a code to save/restore the
thread id selected by GDB.

Signed-off-by: Koudai Iwahori <koudai@google.com>
Change-Id: I761a1141c04d48f1290e4f09baa7c7024f86f36a
Reviewed-on: https://review.openocd.org/c/openocd/+/7358
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-03 09:26:29 +00:00
Koudai Iwahori a9d7428535 hwthread: Add register validity check in get_thread_reg_list
When OpenOCD receives 'g' packet (read general registers) from GDB and
target is configured as rtos=hwthread, hwthread_get_thread_reg_list is
called. However, it does not check if the register valid or not. Due to
this issue, OpenOCD returns invalid register values to GDB.
This commit adds a validity check to hwthread_get_thread_reg_list. If
the register is not valid, it tries to read the register from the
target.

Signed-off-by: Koudai Iwahori <koudai@google.com>
Change-Id: Iad6424b62124271ec411b1dfc044b57dfc460280
Reviewed-on: https://review.openocd.org/c/openocd/+/7357
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-03 09:26:04 +00:00
Antonio Borneo 3ea1bfce4f jtag: xds110: fix clang error core.StackAddressEscape
Clang ignores that xds110_swd_write_reg() is always called with
bit SWD_CMD_RNW in 'cmd' set to zero.
It then complains that the local variable 'value' gets passed by
address to xds110_swd_queue_cmd() and in case of 'read request'
such stack address get stored for later use:
	src/jtag/drivers/xds110.c:1363:1: warning: Address of
	 stack memory associated with local variable 'value' is
	 still referred to by the global variable 'xds110' upon
	 returning to the caller. This will be a dangling
	 reference [core.StackAddressEscape]

To both xds110_swd_write_reg() and xds110_swd_read_reg(), add an
assert() to inform Clang about the state of bit SWD_CMD_RNW.

Change-Id: I7687c055ec71424b642e152f478723a930966e3a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7380
Tested-by: jenkins
2022-12-03 09:25:27 +00:00
Antonio Borneo 0f034868f2 flash: lpc2900: fix clang error 'dead assignment'
The variable retval is assigned a value that is never used.
Scan-build reports:
	Although the value stored to 'retval' is used in the
	enclosing expression, the value is never actually read
	from 'retval'.

Drop the dead assignment.

Change-Id: I11588dee748a55d52aa7f35bc1967b7df55af7fc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7379
Tested-by: jenkins
2022-12-03 09:24:59 +00:00
Dolu1990 b337b0cfb4
riscv/run_algorithm : Add support for memory parameters (#773)
* riscv/run_algorithm : Add support for memory parameters

Change-Id: I5045a3843dcd96edb0cf8cc54bbd41969e3260a6
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* riscv/run_algorithm : better parameter handeling

Change-Id: If3da8b83f784ef7b13ca83e98bc629e2219cc632
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* riscv/run_algorithm : Better mem param error reporting

Change-Id: I09f99ca117f7e5373b23cad0f69d9d5b2a77e61d
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
2022-12-02 09:38:40 -08:00
Tim Newsome 86e84d3f6d target/riscv: Set target->state in riscv013_halt_go()
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.

Hopefully fixes #749.

Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-29 09:24:24 -08:00
Marc Schink 6ea1ccf3e6 flash/nor/stm32lx: Add revision '1, X' for Cat.2 devices
Change-Id: I0ff1e2102175ee952b066b325c9acbcb598b3af7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7378
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-28 22:23:47 +00:00
Nick Kraus e345cefabd jtag/drivers/cmsis_dap.c: Fix Length of SWO Baudrate Command
The command should now send the full 5 byte command length, which
includes the command tag (0x19) and the 4-byte baudrate word, instead
of only the last 3 bytes of the baudrate.

Signed-off-by: Nick Kraus <nick@nckraus.com>
Change-Id: Idd6e084efd7492489aa900cdbf08f540944041cb
Reviewed-on: https://review.openocd.org/c/openocd/+/7370
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-28 22:23:03 +00:00
Tim Newsome 2d7dc3f5f5 target/riscv: Fix small riscv013_halt_go() bug
Exit the loop when no harts are running, instead of when at least one
hart has halted.

Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome 69222be761 target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK
Simple rename to make code slightly more clear.

Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome bf15b00315 target/riscv: Set correct target->state in riscv013_halt_go()
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.

Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 12:59:58 -08:00
Tim Newsome e69735db0b gdb_server: Operate on available targets.
When SMP is enabled, gdb will always use the first target in the SMP
group. That doesn't work when that first target is unavailable, but
others in the SMP group are still available.

For cases where gdb expects an operation to affect the entire group (run
control, memory access), find the first available target in an SMP group
and use that.

Change-Id: I4bed600da3ac0fdfe4287d8fdd090a58452db501
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome b1f3a75819 target/riscv: Don't resume unavailable harts.
Change-Id: I30a2e9ec6c1b99fb92ab1a160ddb63682167c6d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome d3bffe3d86 target/riscv: Share single-target and SMP resume code.
Change-Id: I416d8cc4c8c5ca0337c1f7e392b6b4fa3d75757f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome 5832b983f5 rtos/hwthread: Hide unavailable targets from thread list.
Change-Id: I53c6e2876d9bab70800a0f080e72a2abe0499120
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome ad93fda7e8 target/riscv: Make poll() use TARGET_UNAVAILABLE.
Change-Id: I7052dd08581f0ce6a05cd8319e9bec0086296fc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:47 -08:00
Tim Newsome e5f9024bb0 target/riscv: Refactor riscv_openocd_poll()
There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.

Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome 5a48975118 target/riscv: Error when hart becomes unavailable during resume
Change-Id: I731e6178b2b08b65206614b0dc2a0d993c149cc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome cc5e78172a
Merge pull request #769 from riscv/0.11
Revive 0.11 debug spec support
2022-11-21 09:26:38 -08:00
Tim Newsome f1e20767bc target/riscv: 0.11, call handle_halt() after step
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.

Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 11:41:27 -08:00
Tim Newsome e16d7a5611 target/riscv: Ignore maskmax when reading back tdata1
We don't correctly write it, so we shouldn't expect it to read back the
same value. Fixes hardware breakpoints on mcontrol triggers.

Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
2022-11-17 11:41:24 -08:00
Tim Newsome bec0fe2236
target/riscv: Don't always read on DMI batch write (#768)
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.

riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG  scan
operation.

When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.

This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.

Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling  to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.

This doubles download speeds to spike using remote bitbang.

Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
2022-11-17 11:34:27 -08:00
Tim Newsome fc210e8689 target/riscv: Ignore debug_execution in 0.11 resume
It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)

Fixes #757.

Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 09:49:28 -08:00
Evgeniy Naydanov 8ae41e86e1
Fix breackpoint_add for rtos swbp (#734)
breakpoint_add should use rtos only if request is done by gdb.

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-16 11:03:43 -08:00
Tomas Vanek 9d925776b4 target/armv7m: fix feature name of ARMv8M security extension regs
gdb requires this feature to enable stack unwinding of secure/nonsecure
interstate calls and exceptions on an ARMv8M target with
the security extension.

Tested on STM32L5 (Cortex-M33).

Change-Id: Ib09780c011afbc095b352074068597559ad14fcd
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ae7e2f45aa4798be449f282bbf75ad41e73f055e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7265
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:39:19 +00:00
Giulio Fieramosca 2e9f04c11a rtos/ThreadX: added check for NULL-named tasks
Thread name loading was not correctly handled if a ThreadX task has a NULL
name.

Signed-off-by: Giulio Fieramosca <giulio@glgprograms.it>
Change-Id: I03071930182bc2585b61ce5d8c67491710883dd6
Reviewed-on: https://review.openocd.org/c/openocd/+/7328
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:35:12 +00:00
Andreas Bolsch 2bad55bf83 Fix for segfault and some clang reported problems in stmqspi
Change-Id: Id003adb574085cdd603cc13aeb6f2efec73593f1
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7345
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:34:40 +00:00
Antonio Borneo 1762aa04ce jep106: update to revision JEP106BF.01 Oct 2022
Change-Id: Ia1f19dcce48da997c036ccffa65e76e179de2eb9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7341
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-11-15 21:34:22 +00:00
Simon Smiganovski 0d055602c3 flash/nor/stm32f1x: adjust size of the flash loader buffer
target_run_flash_async_algorithm expects the source_buffer to have
at least 2 words reserved for read and write pointers in addition to the
FIFO buffer. If the size of the data to be flashed is <= 8 bytes then
the flash function will fail with "corrupted fifo read pointer" error.

Ensure the allocated buffer is big enough to hold both FIFO buffer and
read/write pointers.

Change-Id: I09c22eaac517b8cfea8e0b463f5deb6b98afd267
Signed-off-by: Simon Smiganovski <simon.smiganovski@fruitcore.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7342
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:33:53 +00:00
Tomas Vanek 6939187853 target/armv7m: prevent saving and restoring non existent regs
armv7m_start_algorithm() saves register values to arch_info->context.
armv7m_wait_algorithm() restores register values from arch_info->context.
Exclude registers with flag exist = false from both loops.

While on it refactor the register restore: introduce 'struct reg' pointer
and dereference it instead of numerous accesses by a full path
from armv7m pointer.

Change-Id: I1600084db84809ee13bcf8e7828b79f8c9ff9077
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7276
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15 21:30:07 +00:00
Evgeniy Naydanov dc49ed8ae2
Workaround for fp register access in case fp unit is disabled (#766)
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus
set to 0), accessing any fp register results in a hang (any abstract
command timeouts, untill the board is rebooted).

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565

Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-15 08:52:13 -08:00
Antonio Borneo fb23c9c10b rtos: hwthread: fix clang error core.NullDereference
Clang spots a potential NULL pointer dereferencing that is instead
an incorrect use of an array of pointers:

	src/rtos/hwthread.c:254:32: warning: Dereference of null pointer
	  [core.NullDereference]
		(*rtos_reg_list)[j].number = (*reg_list)[i].number;
		                             ^~~~~~~~~~~~~~~~~~~~~
The error has not been spotted before because:
- this function is not called for the first core of the SMP node,
- for the other cores on Cortex-A it still returns valid register
  value for the first 12 ARM registers, then it diverges.

Also Valgrind does not spot any issue at runtime.

Address the array correctly.

While there, use DIV_ROUND_UP() macro for the computation.

Change-Id: Ib87e60e0edfd9671091f5dcfa9aedaf1aed800d1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7337
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-11-11 20:23:13 +00:00
Tomas Vanek 09731b69a6 Revert "Remove duplicate of a counter in hwthread_update_threads"
Commit 0cedf10f8f ("Remove duplicate of a counter in
hwthread_update_threads") introduced a code bug.

In the second foreach_smp_target() loop, variable "threads_found"
gets passed to routine hwthread_fill_thread(). By removing the
counting of threads_found from the second loop, the
incorrect thread counter value gets passed to hwthread_fill_thread().

Change-Id: Ie89e53ccd28bb72b6838ef2f12106a1fe8d00994
Suggested-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7307
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-11 20:22:53 +00:00
Tomas Vanek 3da0c2504c jtag/drivers/cmsis_dap: prevent CDC missdetect as CMSIS-DAP bulk
The autodetection of CMSIS-DAP v2 bulk interface is tricky
as not all adapters conform CMSIS-DAP specs.

If an interface has a string descriptor containing CMSIS-DAP,
then OpenOCD did not insisted on the correct interface class
LIBUSB_CLASS_VENDOR_SPEC.

However the relaxed test caused false autodetection of v2 bulk
interface on some CMSIS-DAP v1 adapters with an additional serial
interface with the string descriptor stupidly containing
CMSIS-DAP text.

Make the test less relaxed, refuse autodetection of the interfaces
with the class number of well known functions including CDC and MSC.

Link: https://sourceforge.net/p/openocd/tickets/368/
Change-Id: I917cb257eb42aab93560cc39c61ec35a60ce52e3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7279
Tested-by: jenkins
Reviewed-by: SilverFox <yyjdelete@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-11 20:22:25 +00:00
Antonio Borneo 1dea9ab41f flash: stmqspi: fix clang error 'dead assignment'
The variable retval is assigned a value that is never used, as it
is reassigned few lines below.

Drop the dead assignment.

Change-Id: Id4e9134408fab3e04936d36e95724bf8d3ab55aa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7304
Tested-by: jenkins
2022-11-11 20:12:48 +00:00
Antonio Borneo 5fc4882b80 dsp5680xx: fix clang error core.UndefinedBinaryOperatorResult
Clang get confused by initializing the array uint16_t lock_word[],
casting it to (uint8_t *), then accessing the second element of
the uint8_t pointer.

  src/target/dsp5680xx.c:2046:41: warning: The left operand of '<<'
    is a garbage value [core.UndefinedBinaryOperatorResult]
        uint16_t tmp = (buffer[0] | (buffer[1] << 8));
                                     ~~~~~~~~~ ^
Fix it by replacing the array with a single uint16_t.

The code is still depending on host endianness; no fix for this is
proposed.

Change-Id: I16dfd60cab117dd145aeecf10d9593574ff233a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7302
Tested-by: jenkins
2022-11-11 20:11:22 +00:00
Antonio Borneo 0946e80407 esirisc_jtag: fix clang error core.VLASize
The function esirisc_jtag_recv() can be called with argument
num_in_fields = 0, for example as consequence of calling
esirisc_jtag_continue().
In this case, num_in_bytes is zero and the allocation of the
variable-length array 'r' requires size zero.

  src/target/esirisc_jtag.c:133:2: warning: Declared variable-length
    array (VLA) has zero size [core.VLASize]
        uint8_t r[num_in_bytes * 2];
        ^~~~~~~~~ ~~~~~~~~~~~~~~~~

Fix it by forcing size one when num_in_bytes is zero.

Change-Id: Id764c7b5ec4f5b3c18c7da650bbff39fc98ed049
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7301
Tested-by: jenkins
2022-11-11 20:11:03 +00:00
Antonio Borneo 7a09635735 openrisc: fix clang error core.CallAndMessage
Clang assumes that size could assume a value that is not 1 nor 2
nor 4. In such condition the buffer in t is allocated (size != 1)
and not initialized. This triggers an error:
  src/target/openrisc/or1k_du_adv.c:655:14: warning: 2nd function
    call argument is an uninitialized value [core.CallAndMessage]
                crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Add the default case to cover other values of size.

After this fix, clang still complains on the same line, this time
misunderstanding the limits of the loop and considering that
buf_bswap16() only swaps the first 16 bits, thus passing not
initialized value data[2] to adbg_compute_crc()

Replace malloc() with calloc() to silent it.

Change-Id: I358d7fb2ebefd69255670641bd435b770762a301
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7300
Tested-by: jenkins
2022-11-11 20:10:41 +00:00
Antonio Borneo aca3707bd8 helper/types: use unsigned type for all h_u64_to_le() and similar
All the converters functions:
	h_u64_to_le()
	h_u64_to_be()
	h_u32_to_le()
	h_u32_to_be()
	h_u24_to_le()
	h_u24_to_be()
	h_u16_to_le()
	h_u16_to_be()
have signed type in their prototype, while the function name and
all the current use cases pass an unsigned value.

Change the prototypes to use unsigned types.

Change-Id: I76dcfdd7912b81f60902184712b2907eae9843f7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7299
Tested-by: jenkins
2022-11-11 20:10:05 +00:00
Tim Newsome 57dbcb1d02
Improve a couple of user/debug messages. (#763)
* gdb_server: Improve info message.

Add target name and state to "Not running when halt was requested"
message.

Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd
Signed-off-by: Tim Newsome <tim@sifive.com>

* rtos/hwthread: Nicer debug message in hwthread_update_threads()

Change-Id: Ia5931a772476a2ae186ed87cd70d7e4be2f196fb
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:32:23 -08:00
Tim Newsome f59bb72fde
target/riscv: Use vlenb to check whether vector registers exist (#762)
E.g. the Zve* vector extensions have all the same registers as the full
V extension, but leaves misa.V clear.

Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:46 -08:00
Tim Newsome 88a629c017
riscv/target: Replace is_halted() with get_hart_state() (#756)
Prep work for handling unavailable harts.

Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10 10:27:04 -08:00
Xiang W 61f183fb25
Use match field for trigger (#725)
* Use match field for trigger

The watchpoint cannot capture all data modifications only through the
trigger of ANY SIZE and EQUAL, and an error will occur. This patch
accommodates watchpoints by adding more types of matches

Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>

* Update src/target/riscv/riscv.c

Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a
Signed-off-by: Xiang W <wxjstz@126.com>

* Add variable type trigger support

Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1
Signed-off-by: Xiang W <wxjstz@126.com>

* remove trailing whitespace

Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84
Signed-off-by: Xiang W <wxjstz@126.com>

* update triggers enumerate

Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f
Signed-off-by: Xiang W <wxjstz@126.com>

Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:48:31 -08:00
Tim Newsome ae3ad22311
target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()

Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>

* Comment code more clearly.

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove extra tab

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09 14:39:19 -08:00
Ben McMorran 3ca7bc7354 ThreadX: set current_thread for kernel execution
If we just invented thread 1 to represent the current execution, we
need to make sure the RTOS object also claims it's the current thread
so that threadx_get_thread_reg_list() doesn't attempt to read a
thread control block at 0x00000001.

Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I7f71e730d047858898297e4cb31db8e47e0c371c
Reviewed-on: https://review.openocd.org/c/openocd/+/7280
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-04 21:49:03 +00:00
Dolu1990 70980e7f57
Fix dm->current_hartid corruption on hartsellen discovery (#754)
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery

Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

* target/riscv Ensure HART_INDEX_DIRTY does not have side effects

Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>

Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-11-01 09:51:33 -07:00
Tim Newsome fad123a16b
target: Add TARGET_UNAVAILABLE state. (#752)
This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).

Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-27 15:21:31 -07:00
Erhan Kurubas 535de48ca6 target/xtensa: remove redundant call for `TARGET_EVENT_HALTED`
`xtensa_do_step` is invoked from `xtensa_prepare_resume` to silently
step over BP/WP before resuming.
For example; in the case of WPs (DEBUGCAUSE_DB), in the current
implementation `xtensa_do_step` will generate one more
`TARGET_EVENT_HALTED` after the original one caused by WP itself.

This patch moves the halted event cb call after
the step is done successfully.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9048e14fb316dc124847a42cfaefb1f76b5ce53e
Reviewed-on: https://review.openocd.org/c/openocd/+/7274
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-21 18:16:23 +00:00