Commit Graph

8985 Commits

Author SHA1 Message Date
Tim Newsome 3acc277e49 target/riscv: Remove duplicate `read PC` message
Change-Id: Ie085758e3cf193f2671ea53fb82fd401d0c52d86
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-09-25 11:41:04 -07:00
Tim Newsome 67c2835997
Merge pull request #911 from riscv/from_upstream
From upstream
2023-09-11 12:53:42 -07:00
Tim Newsome 53f21336c4
Merge pull request #912 from MarekVCodasip/make-unknown-semihosting-error
target/riscv_semihosting: Make the unknown operation number an error
2023-09-08 09:22:10 -07:00
Tim Newsome 42dcc99026
Merge pull request #909 from en-sc/en-sc/cleanup-enumerate-triggers
target/riscv: cleanup riscv_enumerate_triggers()
2023-09-08 09:21:55 -07:00
Evgeniy Naydanov c286f938f4 target/riscv: cleanup riscv_enumerate_triggers()
1. Propagate error codes.
2. Disable leftover triggers in case `tinfo` is supported.

Change-Id: Ie20edb4d8b9245e13ac8757bf6afe549ac99c4f1
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-09-07 13:39:50 +03:00
Marek Vrbka 1936dbd6cf target/riscv_semihosting: Make the unknown operation number an error
Previously, an unknown semihosting operation number
was logged as debug. This patch changes it and few
other places to be logged as error instead.

Change-Id: I83cae5ca1e3daed440f92b08bd372bfffbbad63c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-07 08:08:06 +02:00
Marek Vrbka 8ad41767c0 target/riscv: Reject size 2 soft breakpoints when C extension not supported
This patch disables software breakpoints of size 2 for targets
which don't support compressed instructions.

Change-Id: I8200b22a51c97ba2aa89e6328beadde8dd35cdd5
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-09-04 07:47:03 +02:00
Tim Newsome 699eecaab4
Merge pull request #906 from MarekVCodasip/zero-no-cache
target/riscv: Don't write to zero.
2023-08-30 10:59:54 -07:00
Tim Newsome 0801c66ff4 Merge commit 'dfbbfac4d72e247e8094a49c8573b2f49689b6d5' into from_upstream
Change-Id: I6e7c0866291dd87946a4fd49d9bfe4cddefb3957
2023-08-29 13:10:44 -07:00
Tim Newsome 5efea16944
Merge pull request #900 from aap-sc/aap-sc/simplify_state_managment
riscv: simplify state management during examine
2023-08-29 10:11:52 -07:00
Marek Vrbka 0b914fe5ae target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.

Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-08-25 07:54:59 +02:00
Tim Newsome 928f2b374a
Merge pull request #904 from kr-sc/kr-sc/support-sv57
target/riscv: Add support for Sv57 (and Sv57x4) translation mode
2023-08-23 12:03:21 -07:00
Tim Newsome 7aedb15951
Merge pull request #905 from aap-sc/aap-sc/crash_when_on_vector_tgt_running
fix crash when we try to read vector register on a running target
2023-08-23 12:01:49 -07:00
Tim Newsome 5cb60e3f7d
Merge pull request #903 from wxjstz/riscv
target/riscv: fix execute_fence
2023-08-18 09:32:51 -07:00
Parshintsev Anatoly 198edca6d0 riscv: simplify state management during examine
This also fixes a bug when, after `examine` completion, the target still
has  `unknown` status. To reproduce this one spike, it is enough to do
the following:

---
// make sure spike harts are halted
openocd ... -c init -c 'echo "[targets]"'
---

this behavior is quite dangerous and leads to segfaults in some cases

Change-Id: I13915f7038ad6d0251d56d2d519fbad9a2f13c18
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 15:29:19 +03:00
Parshintsev Anatoly 0ae47ae472 fix crash when we try to read vector register on a running target
Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-18 00:18:10 +03:00
Xiang W 373b8f1a89 target/riscv: fix execute_fence
This patch improves the following issues:
1. Makes it compatible with targets with progbufsize == 1.
2. Although exceptions don’t update any registers, but  do end execution
of the progbuf. This will make fence rw, rw impossible to execute.

Change-Id: I2208fd31ec6a7dae6e61c5952f90901568caada6
Signed-off-by: Xiang W <wxjstz@126.com>
2023-08-17 09:05:36 +08:00
Parshintsev Anatoly a8fedebcb4 [riscv] refactor functions that register read/write via progbuf
The motivation for this refactor is to fixup error handling for some
corner cases. These functions attempt to cache S0 register and only then
perform a bunch of extra checks to figure out if the requested register
is valid one in this context. The problem is that there are few corner
cases when _*progbuf functions could receive a GPR as an input. For
example, an abstract read could fail (for whatever reason) leading to
infinite recursion:

````
save S0 -> read S0 -> save S0 -> read S0 -> ...
```

The case described above could be fixed by adding extra sanitity checks,
however I decided to make these functions more modular since I find
self-contained functions easier to read.

Change-Id: I01f57bf474ca45ebb67a30cd4d8fdef21f307c7d
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-15 17:54:00 +03:00
Tim Newsome 9260101307
Merge pull request #899 from en-sc/en-sc/trig-handle-res-not-avlbl
target/riscv: improve error handling in trigger setup
2023-08-14 09:48:03 -07:00
Kirill Radkin 1d2eea0399 target/riscv: Add support for Sv57 translation mode (including second-stage translations)
Also fix Sv48x4 translation mode
2023-08-14 14:33:44 +03:00
Evgeniy Naydanov 9b558838b1 target/riscv: improve error handling in trigger setup
Change-Id: I235973a3c44fb3d934925c74ffee47f8bd96de0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-08-03 17:58:16 +03:00
Parshintsev Anatoly bb7852646e add diagnostics for non-implemented data watchpoints
Change-Id: If5031c6d8cea1bfcc34bb65fd766f232498ed7ea
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-08-02 08:56:19 +03:00
Kirill Radkin 16e4096c00 target: OpenOCD fails with assert during running "reset" command
OpenOCD fails in the presence of inactive/unresponsive cores

I faced with case when inactive core returns 0 while reading dtmcontrol.
This leads to failure on assert: "addrbits != 0" in "dbus_scan".

Also change "read_bits","poll_target" funcs to avoid a lot lines in logs

Change-Id: If852126755317789602b7372c5c5732183fff6c5
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2023-07-31 19:27:51 +03:00
Tim Newsome c07d9251aa
Merge pull request #884 from riscv/from_upstream
Merge up to a3ed12401 from upstream.
2023-07-31 06:58:52 -07:00
Mark Zhuang a9f28dafd7 target/riscv: support check dbgbase exist
Change-Id: I0d65bf9b33fb6d10c33f4f038045832594579e58
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 14:31:11 +08:00
Mark Zhuang 80a8aa9e19 target/riscv: support multiple DMs
Support assign DMI address of the debug module by pass
-dbgbase to the target create command

Change-Id: I774c3746567f6e6d77c43a62dea5e9e67bb25770
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:44 +08:00
Mark Zhuang 895185caff target/riscv: add dm layer
prepare for support multiple DMs

Change-Id: Ia313006376e4fa762449343e5522b59d3bfd068a
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-26 01:06:38 +08:00
Marek Vrbka 9036f4003a target/riscv: Add target logging to most logging instances
This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-24 08:03:32 +02:00
Erhan Kurubas 617f62a476 target/riscv: fix semantic checker warnings
Besides checkpatch, now upstream codes are scanning with
Sparse semantic checker tool.
This commit addresses some Sparse and checkpatch warnings.

Change-Id: I0e3e9f15220d8829c5708897af27aa86a8f90c07
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2023-07-20 23:09:06 +02:00
Erhan Kurubas e6f30aef80 src: fix clang15 compiler warnings
Below warnings are fixed.

1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]

2- error: variable set but not used [-Werror,-Wunused-but-set-variable]

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
2023-07-20 23:09:06 +02:00
Tim Newsome fb284475a8
Merge pull request #878 from en-sc/en-sc/trigg-eq-check
target/riscv: cleanup trigger setup
2023-07-18 09:32:37 -07:00
Evgeniy Naydanov a8f28fdd48 target/riscv: cleanup trigger setup
* Add a warning when eq trigger is setup and it's behavior is different
from other triggers.

* Make eq trigger's behavior consistent with other triggers in case of
length == 1.

* Fix a bug in setting chained triggers (LT, GT case).

* Improve logging.

Change-Id: Id1ed0d11971b8ed875afbb979e6c8a8b51dd3818
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-17 20:41:01 +03:00
Tim Newsome b67b80c6ac
Merge pull request #879 from riscv/power_dance3
target/breakpoints: Clear software breakpoints from available targets
2023-07-17 09:30:41 -07:00
Tim Newsome 814a3b5e7b
Merge pull request #871 from en-sc/en-sc/fix-mdx-err
target/riscv: refactor read_memory_progbuf()
2023-07-17 09:30:11 -07:00
Evgeniy Naydanov 8d660ea98d target/riscv: refactor read_memory_progbuf()
There were a couple of problems with previous implementation:

* Misalligned read would return ERROR_OK and print all zeroes.

* CMDERR_BUSY for abstract access was improperly handled:

According to the spec, no assumptions can be made about DM_DATA*
contents in such a case, but these were considered valid values from
memory.

* A fallback to one element read was implemented when DMI_STATUS_BUSY
occurred during batch reads, even though this can be accounted for.

Change-Id: I09174c61c951b2bb97a529b7f0aa5afaa995179b
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-07-14 22:23:02 +03:00
Mark Zhuang d5425c253c target/riscv: dynamic allocate memory for hawindow
Change-Id: Id2f1a2568a39eec0a9dd4fe0f155619b11f9d6ba
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:47 +08:00
Mark Zhuang 04d8cfc48c target/riscv: update some macro
1. update RISCV_MAX_HARTS to 2^20 according to SPEC
2. remove RISCV_MAX_REGISTERS, it's not used anywhere anymore
3. add parentheses

Change-Id: Iadf0fa1ba3bbe5b9420b8430883e140db87f4f9e
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-07-14 00:07:44 +08:00
Tim Newsome 674911ef18 Merge commit 'a3ed12401b1f7d9578fb7da881d3504e07acfc27' into from_upstream
Conflicts:
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I65bdb4d28c91e9022ce811de976c9bf474a0b590
2023-07-12 16:32:38 -07:00
Tim Newsome 122c54b4c2 target/riscv: Message when harts become available.
Change-Id: I3824e215a845ba7df3c7887ce1693378fde94b4b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:43 -07:00
Tim Newsome 39a4f37f84 target/breakpoints: Clear software breakpoints from available targets
If a target where a software breakpoint was set is not currently
available, but there are other targets in the same SMP group that are
available, then we can use those to remove the software breakpoint.

Change-Id: I9faa427c7b3aee31504e6e6599539e6f29b58d8f
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-12 16:17:40 -07:00
Tim Newsome 162cc1e79d target/riscv: Fix typo in gdb_regno_cacheable() comment.
Change-Id: If8806853d47779b5b208202803ed5da437f7b624
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-07-06 10:40:59 -07:00
Tim Newsome 8fdce4534f rtos/hwthread: Call rtos_free_threadlist() again.
I think this was incorrectly removed in a merge.

Change-Id: I49fce230f35ae7bd368d2ed780c6c1ffe5939fda
2023-07-06 10:40:28 -07:00
Tim Newsome 21d21408aa
Merge pull request #872 from aap-sc/aap-sc/smp_manipulation
[target/riscv] support for smp group manipulation
2023-07-06 09:10:11 -07:00
Marek Vrbka ea115917b9 target/riscv: Fix the trigger writing sequence
According to section 5.6 in the RISC-V debug specification, the previous
way to set triggers was incorrect, as was discussed as part of
https://github.com/riscv/riscv-openocd/issues/870. This commit fixes the
sequence to be in line with the specification as well as adds some comments
to clarify for any future reader as to what is actually done.

Change-Id: Iffc5cc0f866a466a7aaa72a4c53ee95c9080ac9d
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
2023-07-04 12:04:02 +02:00
Parshintsev Anatoly 2903daa9f1 [target/riscv] support for smp group manipulation
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior

Change-Id: I469453d95e7c1640a91bc60d80c854404e508535
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-07-03 17:28:40 +03:00
Tim Newsome 92c0319261
Merge pull request #873 from eosea/bscan_tunnel_seg_fault_fix
Add null pointer check before right shift for bscan tunneling.
2023-06-29 10:09:12 -07:00
Mark Zhuang 34418ed1c8 target/riscv: fix haltgroup_supported to info->haltgroup_supported
Change-Id: Id1276aecd3097d90e035bf3808e0c472188ba474
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
2023-06-27 15:46:23 +08:00
eolson 9d23d3774a Add null pointer check before right shift for bscan tunneling.
Change-Id: I5d4764c777f33d48705b3e5273eb840c13cfbfb7
Signed-off-by: eolson <erin.olson@seagate.com>
2023-06-22 13:11:15 -05:00
Chao Du a45589d60a
rtos/FreeRTOS: solve some conflicting usage of thread id. (#865)
* rtos/FreeRTOS: solve some conflicting usage of thread id.

1.
There are some RISCV-specific usage of thread_id, which has conflict with upstream.
Some adaptions are made in this patch, to make sure OpenOCD is sending a clear thread list to gdb.

2.
Use freertos_read_struct_value for xSchedulerRunning.

Change-Id: I001a88a0c6d8eac98a389c0217b4897f28124840
Signed-off-by: Chao Du <duchao@eswincomputing.com>

* fix typo.

Change-Id: Id6546cc74de44bbee7e44b7cb29b769a2f35ec4a

* correct the data type.

Change-Id: I28c7e111e569d94ba5f6e1ae21745ddb34d4dd12

* changes as per the review comment.

Change-Id: Ica4c705a8f2657700dc27e24790287ca802480fd

* another macro replacement.

Change-Id: Ia9330fed32d917cf87804051ba1b8d6ac42cfb7b

---------

Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-06-22 09:05:29 -07:00
Tim Newsome 470c2a402c
Merge pull request #868 from en-sc/en-sc/upstream-resume-err-2
target/riscv: resume only halted harts
2023-06-21 09:37:40 -07:00