The riscv013_on_halt function was being called but its implementation was
empty, providing no additional functionality. Removed the function declaration,
calls to it, and its implementation since it is not required.
Change-Id: I425ea890deadeec945f0a47af247f3f99172e801
Signed-off-by: Tim Newsome <tim@sifive.com>
Otherwise we may end up modifying DCSR of a different hart than
intended.
Change-Id: I39bde21a1444623ed150f2b3d504b9318b9d6191
Signed-off-by: Tim Newsome <tim@sifive.com>
Register access on running target should fail if mstatus needs to be
modified.
Change-Id: Iec8e8d514ef2f5ca42606a5534cce55aaaa99180
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This way if you connect to a running target, before it's hit a breakpoint,
then when it does hit the breakpoint OpenOCD will catch it.
Change-Id: I6f1e5f169fa385f46759015786e664693c3872e4
Signed-off-by: Tim Newsome <tim@sifive.com>
Poll failure just means poll failed. It's safer to assume the target is
still running, because then if it is running and subsequently halts we can
relay this to gdb correctly. We can't do the other way around, because once
gdb thinks the target has halted, it can't deal with it spontaneously
running.
Change-Id: Idb56137f1d6baa9afc1b0e55e4a48f407b8ebe83
Signed-off-by: Tim Newsome <tim@sifive.com>
When a DM was powered down, we end up in examine() again, and clearly if
the DM was powered down we need to invalidate that cache.
Change-Id: I5eb6a289939f313e06c09cac22245db083026aa3
Signed-off-by: Tim Newsome <tim@sifive.com>
The error state is sticky, so this has to be done to recover.
Change-Id: I589f3cdab0f2351fd25f89951830cbc16c39bd93
Signed-off-by: Tim Newsome <tim@sifive.com>
In case in the future I have the same idea of optimizing progbuf writes
again.
Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?
Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
Untested, because I don't have a target that implements this.
Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
We should avoid using x16~x31 register in program buffer because there
are no such general purpose registers in RVE(Embedded) extension.
For targets that support rvE, when the parameter increment=0
and count>1 of the read_memory_progbuf function, openocd will cause
an error due to the use of the s2 register.
For example:
{Command} {riscv repeat_read} count address [size=4]
Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435
Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
* Add command "exec_progbuf"
Command "exec_progbuf" allows to execute a user-specified sequence
of instructions using the program buffer.
Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Updated the doc:
- Minor reword and reorder of the sentences.
- Added information about C-instructions in progbuf.
- Fixed a typo (per the review).
- Added examples.
Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Cosmetic changes
Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
---------
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
Because riscv_program_exec() tries to add an instruction every time
through.
This would cause an error accessing vector registers where VL > 14(?).
Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40
Signed-off-by: Tim Newsome <tim@sifive.com>
This should make vector accesses work on 64-bit harts that implement
Zve32*. There doesn't appear to be any way to easily determine what vsew
values are allowed, so try and notice the failure.
Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84
Signed-off-by: Tim Newsome <tim@sifive.com>
OpenOCD currently uses improper "fence" instruction:
"FENCE" opcode with empty predecessor and successor sets.
Such instruction has no effect and is reserved for future use
as a HINT instruction (RISC-V Unprivileged ISA spec V20191213,
section 2.9).
This patch fixes it by using the proper "fence rw,rw"
instruction.
Change-Id: Ia2a66059009153efef27279410850ddfd73dae38
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
This command is supposed to be a start at a compliance test for system
bus access. It doesn't pass against spike because it doesn't handle all
cases where the interface might be busy. It's not documented. As far as
I know nobody uses it.
So delete 400 lines of code instead of trying to fix it.
Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.
Hopefully fixes#749.
Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
Exit the loop when no harts are running, instead of when at least one
hart has halted.
Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.
Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.
riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG scan
operation.
When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.
This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.
Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.
This doubles download speeds to spike using remote bitbang.
Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus
set to 0), accessing any fp register results in a hang (any abstract
command timeouts, untill the board is rebooted).
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
E.g. the Zve* vector extensions have all the same registers as the full
V extension, but leaves misa.V clear.
Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Prep work for handling unavailable harts.
Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()
Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>
* Comment code more clearly.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove extra tab
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery
Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
* target/riscv Ensure HART_INDEX_DIRTY does not have side effects
Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
* target/riscv: Correctly set target->state in deassert_reset
This bug didn't lead to problems, but it would with some upcoming
changes.
Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb
Signed-off-by: Tim Newsome <tim@sifive.com>
* Keep debug_reason in sync with state
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* Properly track selecting multiple harts at once.
use_hasel is a bit of a hack.
Change-Id: Ia589ebc16bca32038d915df9988361b88e940917
Signed-off-by: Tim Newsome <tim@sifive.com>
* Clarifying comment.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Rename set_hartsel to set_dmcontrol_hartsel
Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850
* Make set_dmcontrol_hartsel() more idiomatic.
Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486
* Use constant for multiple harts instead of -1.
Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Tim Newsome
Evgeniy Naydanov
Parshintsev Anatoly
Mark Zhuang
Hang Xu
Jan Matyas
Jan Matyas
Evgeniy Naydanov
Dolu1990