Clifford Wolf
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a6c96b986b
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Added Yosys::{dict,nodict,vector} container types
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2014-12-26 10:53:21 +01:00 |
Clifford Wolf
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70b2efdb05
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Added support for $readmemh/$readmemb
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2014-10-26 20:33:10 +01:00 |
Clifford Wolf
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6b05a9e807
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Fixed handling of invalid array access in mem2reg code
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2014-10-16 00:44:23 +02:00 |
Clifford Wolf
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085c8e873d
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Added AstNode::asInt()
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2014-08-21 17:11:51 +02:00 |
Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
Clifford Wolf
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acb435b6cf
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Added const folding of AST_CASE to AST simplifier
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2014-08-18 00:02:30 +02:00 |
Clifford Wolf
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d491fd8c19
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Use stackmap<> in AST ProcessGenerator
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2014-08-17 00:57:24 +02:00 |
Clifford Wolf
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c83b990458
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Changed the AST genWidthRTLIL subst interface to use a std::map
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2014-08-14 23:02:07 +02:00 |
Clifford Wolf
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d259abbda2
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Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 15:52:54 +02:00 |
Clifford Wolf
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91dd87e60b
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
Clifford Wolf
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1cb25c05b3
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
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2014-07-31 13:19:47 +02:00 |
Clifford Wolf
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27a872d1e7
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
Clifford Wolf
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80e4594695
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Added AstNode::MEM2REG_FL_CMPLX_LHS
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2014-06-17 21:39:25 +02:00 |
Clifford Wolf
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5bfe865cec
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Added found_real feature to AstNode::detectSignWidth
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2014-06-16 15:00:57 +02:00 |
Clifford Wolf
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149fe83a8d
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improved (fixed) conversion of real values to bit vectors
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2014-06-14 21:00:51 +02:00 |
Clifford Wolf
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442a8e2875
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Implemented basic real arithmetic
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2014-06-14 08:51:22 +02:00 |
Clifford Wolf
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7ef0da32cd
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Added Verilog lexer and parser support for real values
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2014-06-13 11:29:23 +02:00 |
Clifford Wolf
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e275e8eef9
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Add support for cell arrays
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2014-06-07 11:48:50 +02:00 |
Clifford Wolf
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7c8a7b2131
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further improved const function support
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2014-06-07 00:02:05 +02:00 |
Clifford Wolf
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76da2fe172
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improved const function support
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2014-06-06 22:55:02 +02:00 |
Clifford Wolf
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b5cd7a0179
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added while and repeat support to verilog parser
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2014-06-06 17:40:04 +02:00 |
Clifford Wolf
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02e6f2c5be
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Added Verilog support for "`default_nettype none"
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2014-02-17 14:28:52 +01:00 |
Clifford Wolf
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e8af3def7f
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Added support for FOR loops in function calls in parameters
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2014-02-14 20:33:22 +01:00 |
Clifford Wolf
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534c1a5dd0
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Created basic support for function calls in parameter values
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2014-02-14 19:56:44 +01:00 |
Clifford Wolf
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cd9e8741a7
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Implemented read_verilog -defer
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2014-02-13 13:59:13 +01:00 |
Clifford Wolf
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d06258f74f
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Added constant size expression support of sized constants
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2014-02-01 13:50:23 +01:00 |
Clifford Wolf
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375c4dddc1
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Added read_verilog -icells option
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2014-01-29 00:59:28 +01:00 |
Clifford Wolf
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88fbdd4916
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Fixed algorithmic complexity of AST simplification of long expressions
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2014-01-20 20:25:20 +01:00 |
Clifford Wolf
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9a1eb45c75
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Added Verilog parser support for asserts
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2014-01-19 04:18:22 +01:00 |
Clifford Wolf
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ecc30255ba
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Added proper === and !== support in constant expressions
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2013-12-27 13:50:08 +01:00 |
Clifford Wolf
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891e4b5b0d
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Keep strings as strings in const ternary and concat
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2013-12-05 13:26:17 +01:00 |
Clifford Wolf
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5c39948ead
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Added AstNode::mkconst_str API
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2013-12-05 12:53:49 +01:00 |
Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
Clifford Wolf
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f4b46ed31e
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Replaced signed_parameters API with CONST_FLAG_SIGNED
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2013-12-04 14:24:44 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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7d9a90396d
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Added verilog frontend -ignore_redef option
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2013-11-24 19:57:42 +01:00 |
Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
Clifford Wolf
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609caa23b5
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Implemented correct handling of signed module parameters
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2013-11-24 17:17:21 +01:00 |
Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
Clifford Wolf
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943329c1dc
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Various ast changes for early expression width detection (prep for constfold fixes)
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2013-11-02 13:00:17 +01:00 |
Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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db98a18edb
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Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
Clifford Wolf
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f1a2fd966f
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Now only use value from "initial" when no matching "always" block is found
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2013-03-31 11:51:12 +02:00 |
Clifford Wolf
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161565be10
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
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2013-03-31 11:19:11 +02:00 |
Clifford Wolf
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7bfc7b61a8
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Implemented proper handling of stub placeholder modules
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2013-03-28 09:20:10 +01:00 |
Clifford Wolf
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227520f94d
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Added nosync attribute and some async reset related fixes
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2013-03-25 17:13:14 +01:00 |