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yosys
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2,772 Commits 75 Branches 48 Tags 60 MiB
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2772 Commits

Author SHA1 Message Date
Andrew Zonenberg 134e093e4e Added GP_PGA cell 2016-04-27 23:07:21 -07:00
Clifford Wolf 0d2923cccd Connections between inputs and inouts are driven by the input 2016-04-26 19:49:05 +02:00
Clifford Wolf 958fb29c76 Fixed test_autotb for modules with many cell ports 2016-04-25 16:37:11 +02:00
Clifford Wolf 93e107e455 Fixed proc_mux performance bug 2016-04-25 10:43:04 +02:00
Clifford Wolf d086224a39 Merge pull request #150 from azonenberg/master 
GreenPak analog comparator support
 2016-04-25 10:33:18 +02:00
Andrew Zonenberg d57c85111f Merge https://github.com/cliffordwolf/yosys 2016-04-24 22:11:56 -07:00
Andrew Zonenberg 349d717202 Removed VIN_BUF_EN 2016-04-24 17:01:21 -07:00
Clifford Wolf b1d6f05fa2 Fixed performance bug in proc_dlatch 2016-04-24 19:29:56 +02:00
Clifford Wolf 9aa4b3309c Added "yosys -D ALL" 2016-04-24 17:12:34 +02:00
Andrew Zonenberg 6e215f374d Renamed VOUT to OUT on GP_ACMP cell 2016-04-23 22:53:49 -07:00
Andrew Zonenberg 512486dcf3 Added GP_ACMP cell 2016-04-23 22:33:36 -07:00
Clifford Wolf 09ffebb995 Added "prep -flatten" and "synth -flatten" 2016-04-24 00:48:33 +02:00
Clifford Wolf 77aa2031e7 Converted "prep" to ScriptPass 2016-04-24 00:48:06 +02:00
Clifford Wolf 096c25d29d Improvements in greenpak4 shreg mapping 2016-04-23 23:10:13 +02:00
Clifford Wolf c9c5192cd6 Run clean after splitnets in synth_greenpak4 2016-04-23 23:09:45 +02:00
Andrew Zonenberg 7f16784f3c Merge https://github.com/cliffordwolf/yosys 2016-04-23 12:22:08 -07:00
Clifford Wolf e13c66122e Added "shregmap -zinit" for greenpak4 tech 2016-04-23 20:20:21 +02:00
Andrew Zonenberg 421b0d715c Merge https://github.com/cliffordwolf/yosys 2016-04-23 10:18:15 -07:00
Clifford Wolf 34195f281f Merge https://github.com/azonenberg/yosys 2016-04-23 10:33:32 +02:00
Clifford Wolf f85cfa5666 Added "shregmap" to synth_greenpak4 2016-04-23 10:31:19 +02:00
Clifford Wolf a24021ea20 Converted synth_greenpak4 to ScriptPass 2016-04-23 10:27:33 +02:00
Andrew Zonenberg 2849fd486e Fixed typo in help text 2016-04-22 23:01:39 -07:00
Andrew Zonenberg 0cbe70eaa4 Fixed typo 2016-04-22 19:08:19 -07:00
Andrew Zonenberg ab11f2aa70 Merge https://github.com/cliffordwolf/yosys 2016-04-22 19:07:55 -07:00
Clifford Wolf 7311be4028 Added "shregmap -tech greenpak4" 2016-04-22 19:42:08 +02:00
Clifford Wolf 779e2cc819 Added support for "active high" and "active low" latches in BLIF front-end 2016-04-22 18:02:55 +02:00
Clifford Wolf 60ac1bd178 Added support for "active high" and "active low" latches in BLIF back-end 2016-04-22 18:00:46 +02:00
Clifford Wolf 965b0d59b5 More flexible handling of initialization values 2016-04-22 12:13:06 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 1565d1af69 Fixed performance bug in "share" pass 2016-04-21 19:47:25 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf f38ca3e18f Improvements in opt_expr 2016-04-21 14:23:04 +02:00
Clifford Wolf 1761d08dd2 Bugfix and improvements in memory_share 2016-04-21 14:22:58 +02:00
Andrew Zonenberg d90c1e9522 Added GP_VREF cell 2016-04-20 20:48:19 -07:00
Clifford Wolf bf64974d43 Merge pull request #149 from azonenberg/master 
GP_RCOSC and GP_SHREG cells plus some cleanup
 2016-04-19 10:37:04 +02:00
Andrew Zonenberg 8c9ac5db7b Merge https://github.com/cliffordwolf/yosys 2016-04-18 19:22:52 -07:00
Clifford Wolf f1fa757d0e Added "shregmap -params" 2016-04-18 11:58:21 +02:00
Clifford Wolf 525651c8f6 Added "shregmap -zinit" and "shregmap -init" 2016-04-18 11:44:10 +02:00
Andrew Zonenberg b2c36f6136 Merge https://github.com/cliffordwolf/yosys 2016-04-17 08:15:34 -07:00
Clifford Wolf ce7c980ec7 Improvements in "shregmap" 2016-04-17 15:37:22 +02:00
Andrew Zonenberg be570712d8 Merge https://github.com/cliffordwolf/yosys 2016-04-16 15:14:32 -07:00
Clifford Wolf de647a390c Added "shregmap" pass 2016-04-16 23:20:49 +02:00
Clifford Wolf fbdb8e7b3e Fixed copy&paste error in log message in lut2mux 2016-04-16 23:20:34 +02:00
Clifford Wolf a07f893a5f Minor hashlib bugfix 2016-04-16 23:20:11 +02:00
Andrew Zonenberg d0aaf8d262 Added GP_SHREG cell 2016-04-13 23:13:51 -07:00
Andrew Zonenberg cdefa60367 Refactoring: alphabetized cells_sim 2016-04-13 23:13:39 -07:00
Andrew Zonenberg f1679936fe Fixed missing semicolon 2016-04-09 01:18:02 -07:00
Andrew Zonenberg c1b8d3b580 Merge https://github.com/cliffordwolf/yosys 2016-04-09 01:17:24 -07:00
Andrew Zonenberg 58d8715681 Added GP_RCOSC cell 2016-04-09 01:17:13 -07:00
Clifford Wolf 3d9ff912c2 Merge pull request #147 from azonenberg/master 
Added GP_BANDGAP, GP_POR, GP_RINGOSC primitives
 2016-04-08 11:58:40 +02:00