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1135 Commits

Author SHA1 Message Date
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Claire Wolf 5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Eddie Hung db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung 2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Eddie Hung 7f9ecddb7f Add testcase for #2010 2020-05-01 14:07:33 -07:00
Dan Ravensloft 3d149aff73 intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
Eddie Hung 988d47af85 tests: read +/xilinx/cell_sim.v before xilinx_dsp test 2020-04-22 17:50:30 -07:00
Eddie Hung db09e96dff test: ice40_dsp test to read +/ice40/cells_sim.v for default params 2020-04-22 16:35:35 -07:00
Eddie Hung f582eb14af xilinx: xilinx_dffopt to read cells_sim.v; fix test 2020-04-22 16:25:23 -07:00
Eddie Hung fa9df06c9d
Merge pull request #1949 from YosysHQ/eddie/select_blackbox 
select: do not select inside black-/white- boxes unless '=' prefix used
 2020-04-22 15:35:05 -07:00
Eddie Hung db27f2f378
Merge pull request #1973 from YosysHQ/eddie/fix1966 
tests: fix various/plugin.sh when PREFIX != /usr/local/share
 2020-04-22 10:19:30 -07:00
Eddie Hung 281cd10717 tests: update select black/white-box tests 2020-04-22 10:16:14 -07:00
Eddie Hung 28623f19ee
Merge pull request #1950 from YosysHQ/eddie/design_import 
design: -import to not count black/white-boxes as candidates for top
 2020-04-22 09:32:13 -07:00
Eddie Hung 634b5e2d9f tests: use `yosys-config --datdir` instead of hard-coded 2020-04-22 08:29:45 -07:00
Claire Wolf c32b4bded5
Merge pull request #1976 from YosysHQ/dave/fix-sim-const 
sim: Fix handling of constant-connected cell inputs at startup
 2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka 846c79b312 hierarchy: Convert positional parameters to named. 
Fixes #1821.
 2020-04-21 19:09:00 +02:00
Claire Wolf 9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite 
Improved rewrite code for writing to bit slice
 2020-04-21 18:46:52 +02:00
David Shah abf81c7639 sim: Fix handling of constant-connected cell inputs at startup 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-21 08:58:52 +01:00
Eddie Hung 38ee59184c tests: remove write_ilang 2020-04-20 15:42:29 -07:00
Eddie Hung caf4071c8b Remove '-ignore_unknown_cells' option from 'sat' 2020-04-20 11:58:23 -07:00
Eddie Hung a1573058e9 Simplify test case script 2020-04-20 11:54:10 -07:00
Eddie Hung 99a0958601 Remove ununsed files 2020-04-20 11:53:48 -07:00
diego 22f440506b Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
Eddie Hung 34d8ff8b56 abc9: add testcase reduced from #1970 2020-04-20 09:38:29 -07:00
diego 50581d5a94 Wrong fixed value 2020-04-17 10:15:22 -05:00
Eddie Hung 9eace8f360 design: add test 2020-04-16 12:48:40 -07:00
Eddie Hung 2ddfb61e65 select: add test for not selecting inside black/white boxes 2020-04-16 12:45:04 -07:00
diego 87910732f1 Adding tests for dynamic part select optimisation 2020-04-16 13:31:05 -05:00
Eddie Hung 2623e335cc tests: add select -unset tests 2020-04-16 10:51:58 -07:00
Eddie Hung e8a841467f tests: add design -delete tests 2020-04-16 08:05:18 -07:00
David Shah 2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919 
ast: Fix handling of identifiers in the global scope
 2020-04-16 13:48:20 +01:00
Marcelina Kościelnicka 2f8541a92e opt_expr: Fix X and CO outputs for $alu identity-mapping rules. 2020-04-16 11:48:29 +02:00
David Shah 4d02505820 ast: Fix handling of identifiers in the global scope 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-16 10:30:07 +01:00
Eddie Hung 33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more 
zinit: handle $__DFFS?E?_[NP][NP][01] too
 2020-04-15 08:36:25 -07:00
Claire Wolf 4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876 
Fix handling of ternary with constant condition
 2020-04-15 16:01:19 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00
Eddie Hung 383fe4a4bc tests: zinit for new types 2020-04-14 13:08:37 -07:00
Marcelina Kościelnicka 6c16fd760b opt_expr: Add more $alu optimizations. 
Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.

Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).

Fixes #1912.
 2020-04-14 21:48:13 +02:00
Eddie Hung e7121cc15c tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
Marcelina Kościelnicka 7a36728b2f dffinit: Avoid setting init parameter to zero-length value. 
Fixes #1704.
 2020-04-14 19:52:19 +02:00
whitequark f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl 
support using previously declared types/localparams/parameters in package
 2020-04-14 12:40:00 +00:00
Eddie Hung b75c5bf743 zinit: resolve one more comment by @mwkmwkmwk 2020-04-13 15:25:37 -07:00
Eddie Hung c6afce7638 zinit: fix review comments from @mwkmwkmwk 2020-04-13 15:16:51 -07:00
Eddie Hung 091297b9ee tests: zinit on $adff 2020-04-13 14:29:44 -07:00
Eddie Hung 3c5a9411b1 Add testcase for $_DFF_[NP][NP][01]_ 2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka 840bb17089 opt_expr: Optimize multiplications with low 0 bits in operands. 
Fixes #1500.
 2020-04-13 16:52:22 +02:00
Xiretza 7f1d83c5db Add .gitignore to tests/select/ 2020-04-12 22:45:45 +02:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00