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858 Commits

Author SHA1 Message Date
Eddie Hung d63f105708 SigSpec::remove_const() to return SigSpec& 2019-07-17 10:44:11 -07:00
Eddie Hung d086dfb5b0 SigSpec::extract to allow negative length 2019-07-16 14:06:07 -07:00
Eddie Hung b29f26f6c7 SigSpec::extend_u0() to return *this 2019-07-15 16:23:12 -07:00
Clifford Wolf ef07a313b4
Merge pull request #1162 from whitequark/rtlil-case-attrs 
Allow attributes on individual switch cases in RTLIL
 2019-07-09 16:56:29 +02:00
Eddie Hung 41d7d9d24b Clarify script -scriptwire doc 2019-07-08 19:21:21 -07:00
whitequark 93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Eddie Hung f1504696e5 Use Pass::call_on_module() as per @cliffordwolf comments 2019-07-02 08:20:37 -07:00
Eddie Hung 02ba85b133 script -select -> script -scriptwire 2019-07-02 08:17:26 -07:00
Eddie Hung 06971385fa Support ability for "script -select" to take commands from wires 2019-06-28 13:36:33 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Eddie Hung fb30fcb7c5 Undo iterator based Module::remove() for cells, as containers will not 
invalidate
 2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic 0f32cb4e0a Merge remote-tracking branch 'upstream/master' 2019-06-27 12:11:47 +02:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Ben Widawsky 8767ec3fbd Add a few more filename rewrites 
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-20 10:27:59 -07:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf b3441935b1
Merge pull request #1100 from bwidawsk/home 
Support ~ in filename parsing
 2019-06-19 10:52:59 +02:00
whitequark df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Ben Widawsky 468c41d997 Support ~ for home directory 
This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:38:40 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Bogdan Vukobratovic 8451cbea89 Move netlist helper module to passes/opt for the time being 2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic 53695e6729 Prepare for situation when port of the signal cannot be found 2019-06-14 11:39:24 +02:00
Eddie Hung d09d4e0706 Move ConstEvalAig to aigerparse.cc 2019-06-13 16:28:11 -07:00
Eddie Hung 63e2f83632 More slimming 2019-06-13 13:29:03 -07:00
Eddie Hung d39a5a77a9 Add ConstEvalAig specialised for AIGs 2019-06-13 13:13:48 -07:00
Bogdan Vukobratovic 8665f48879 Implement disconnection of constant register bits 2019-06-13 19:35:37 +02:00
Bogdan Vukobratovic 4912567cbf Pass SigBit by value to Netlist algorithms 2019-06-13 15:42:45 +02:00
Bogdan Vukobratovic d69989b8d2 Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
Eddie Hung f7a9769c14 Merge remote-tracking branch 'origin/master' into xaig 2019-06-12 08:50:39 -07:00
Bogdan Vukobratovic 9892df17ef Generate satgen instance instead of calling sat pass 2019-06-11 11:47:13 +02:00
Bogdan Vukobratovic d097f423d1 Refactor driver map generation 
- Implement iterators over the driver map that enumerate signals and cells
  within the cones of the signal
 2019-06-10 21:42:35 +02:00
Clifford Wolf 211d85cfcc Fixes and cleanups in AST_TECALL handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 12:41:09 +02:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Clifford Wolf 0971f772d7 Fix handling of warning and error messages within log_make_debug-blocks 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-22 13:46:38 +02:00
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 16:01:00 +02:00
Clifford Wolf 3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings 
Fix all warnings that occurred when compiling with gcc9
 2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch 30c762d3a1 Fix all warnings that occurred when compiling with gcc9 2019-05-08 10:27:14 +02:00
Clifford Wolf c582a25bdb
Merge pull request #998 from mdaiter/get_bool_attribute_opts 
Minor optimization to get_attribute_bool
 2019-05-08 08:34:35 +02:00
Matthew Daiter 6e629d2895 Minor optimization to get_attribute_bool 2019-05-07 22:04:28 -05:00
Matthew Daiter bafbb9ee90 Optimize ceil_log2 function 2019-05-07 12:17:56 -05:00
Clifford Wolf 87426f5a06 Improve write_verilog specify support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 08:46:24 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf 9268cd1613 Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:19:10 +02:00
Oleg Endo 4f15e7f00f fix codestyle formatting 2019-04-29 19:20:33 +09:00
Oleg Endo e531fb203a escape spaces with backslash when writing dep file 
filenames are sparated by spaces in the dep file.  if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
 2019-04-29 16:13:34 +09:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00