riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,384 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

51 Commits

Author SHA1 Message Date
Martin Povišer f0ae046c5a opt_share: Fix input confusion with ANDNOT, ORNOT gates 
Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.

Fixes #3848.
 2023-07-20 20:58:52 +01:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka 01626e6746 opt_share: Fix X and CO signal width for shifted $alu in opt_share. 
These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.
 2021-01-14 14:54:08 +01:00
Marcelina Kościelnicka 2b777bbda8 opt_share: Refactor, fix some bugs. 
Fixes #2334.
Fixes #2335.
Fixes #2336.
 2020-08-17 17:26:36 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Marcin Kościelnicki fdcbda195b opt_share: Fix handling of fine cells. 
Fixes #1525.
 2019-11-27 08:01:07 +01:00
Sean Cross 8d128ba6d0 passes: opt_share: don't statically initialize mergeable_type_map 
In 3d3779b037 this got turned from a
`std::map<std::string, std::string>` to `std::map<IdString, IdString>`.
Consequently, this exposed some initialization sequencing issues (#1361).

Only initialize the map when it's first used, to avoid these static issues.

This fixes #1361.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-09 12:40:01 +08:00
Eddie Hung f42ba811b6 ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc 2019-08-19 10:11:47 -07:00
Eddie Hung 3d3779b037 Use ID() macro 2019-08-16 14:01:55 -07:00
Bogdan Vukobratovic 067b44938c Fix wrong results when opt_share called before opt_clean 2019-08-07 09:30:58 +02:00
Bogdan Vukobratovic 6a796accc0 Support various binary operators in opt_share 2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic 280c4e7794 Fix spacing in opt_share tests, change wording in opt_share help 2019-08-03 12:28:46 +02:00
Bogdan Vukobratovic c075486c59 Reimplement opt_share to work on $alu and $pmux 2019-07-28 16:03:54 +02:00
Bogdan Vukobratovic 07c4a7d438 Implement opt_share 
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
 2019-07-26 11:36:48 +02:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Mingyu Gao 8c4c62f3e1 Bugfix for cell hash cache option in opt_share. 2015-08-11 11:40:23 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 08f9b38a9c Added opt_share -share_all 2015-05-31 14:24:34 +02:00
Clifford Wolf a8f4a099b5 Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
Clifford Wolf 951c72ba52 bugfix in opt_share 2014-12-28 21:26:36 +01:00
Clifford Wolf 3da46d3437 Renamed hashmap.h to hashlib.h, some related improvements 2014-12-28 17:51:16 +01:00
Clifford Wolf 66ab88d7b0 More hashtable finetuning 2014-12-27 03:04:50 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf ecdf1f5577 Improved handling of reg init in opt_share and opt_rmdff 2014-02-04 12:02:47 +01:00
Clifford Wolf 88af5b6a16 Improved opt_share for reduce cells 2013-03-29 11:19:21 +01:00
Clifford Wolf 0d48b846ac Improved opt_share for commutative standard cells 2013-03-29 11:01:26 +01:00
Clifford Wolf 36954471a6 Added help messages for opt_* passes 2013-03-01 09:01:49 +01:00
Clifford Wolf a321a5c412 Moved stand-alone libs to libs/ directory and added libs/subcircuit 2013-02-27 09:32:19 +01:00