6ffc315936
cxxrtl: export wire attributes through the C API.
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Co-authored-by: Charlotte <charlotte@lottia.net>
2023-10-25 16:01:48 +00:00
4a475fa7a2
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
2829cd9caa
cxxrtl_backend: move sync $print grouping out of dump into analyze
2023-08-11 04:46:52 +02:00
ce245b5105
cxxrtl_backend: respect sync `$print` priority
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We add a new flow graph node type, PRINT_SYNC, as they don't get handled
with regular CELL_EVALs. We could probably move this grouping out of
the dump method.
2023-08-11 04:46:52 +02:00
4ffdee65e0
cxxrtl: store comb $print cell last EN/ARGS in module
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statics were obviously wrong -- may be multiple instantiations of any
given module. Extend test to cover this.
2023-08-11 04:46:52 +02:00
843ad9331b
cxxrtl: WIP: adjust comb display cells to only fire on change
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Naming and use of statics to be possibly revised.
2023-08-11 04:46:52 +02:00
7f7c61c9f0
fmt: remove lzero by lowering during Verilog parse
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See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
2023-08-11 04:46:52 +02:00
fc0acd0ad1
cxxrtl: restrict -print-output to cout, cerr
2023-08-11 04:46:52 +02:00
f9b149fa7b
cxxrtl: add "-print-output" option, test in fmt
2023-08-11 04:46:52 +02:00
bfa8b631bf
cxxrtl: remove unused signedDivideWithRemainder
2023-08-11 04:46:52 +02:00
3571bf2c2d
fmt: fuzz, remove some unnecessary busywork
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Removing some signed checks and logic where we've already guaranteed the
values to be positive. Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
2023-08-11 04:46:52 +02:00
2ae551c0af
fmt: fuzz, fix (remove extraneous + incorrect fill)
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"blk + chunks" is often an overrun, plus the fill is unnecessary; we
throw blk away immediately.
2023-08-11 04:46:52 +02:00
c382d7d3ac
fmt: %t/$time support
2023-08-11 04:46:52 +02:00
52dc397a50
cxxrtl: don't use signed divide with unsigned/pos values
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Incorrect for unsigned, wasted effort for positive signed.
2023-08-11 04:46:52 +02:00
095b093f4a
cxxrtl: first pass of $print impl
2023-08-11 04:46:52 +02:00
eb397592f0
cxxrtl: add `$divfloor`.
2023-06-28 15:27:06 +01:00
24b895778a
Add support for GHDL modfloor operator
2022-07-05 15:15:54 -04:00
93508d58da
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
fc049e84a9
cxxrtl: don't reset elided wires with \init attribute.
2021-12-25 01:06:10 +00:00
7f2ea7d222
cxxrtl: demote wires not inlinable only in debug_eval to locals.
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Fixes #3112 .
Co-authored-by: Irides <irides@irides.network>
2021-12-15 09:14:33 +00:00
55c9fb3b18
cxxrtl: preserve interior memory pointers across reset.
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Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
2021-12-11 16:40:06 +00:00
7c9e498662
cxxrtl: use unique_ptr<value<>[]> to store memory contents.
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This makes the depth properly immutable.
2021-12-11 14:52:37 +00:00
e7d89e653c
Hook up $aldff support in various passes.
2021-10-02 21:01:21 +02:00
e6f3d1c225
kernel/mem: Introduce transparency masks.
2021-08-11 00:04:16 +02:00
a04844bdf8
Merge pull request #2885 from whitequark/cxxrtl-fix-2883
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cxxrtl: treat wires with multiple defs as not inlinable
2021-07-20 13:12:11 +00:00
1a6ddf7892
cxxrtl: treat wires with multiple defs as not inlinable.
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Fixes #2883 .
2021-07-20 10:30:39 +00:00
225af830c1
cxxrtl: treat assignable internal wires used only for debug as locals.
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This issue was introduced in commit 4aa65f40#2739 .
Fixes #2882 .
2021-07-20 10:10:42 +00:00
fc84f23001
cxxrtl: escape colon in variable names in VCD writer.
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The following VCD file crashes GTKWave's VCD loader:
$var wire 1 ! x:1 $end
$enddefinitions $end
In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:
update$func$.../hdl/hazard3_csr.v:350$2534.$result
2021-07-19 16:22:55 +00:00
948fc10d7b
cxxrtl: add debug_item::{get,set}.
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Fixes #2877 .
2021-07-18 06:20:45 +00:00
4aa65f406f
cxxrtl: treat internal wires used only for debug as constants.
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Fixes #2739 (again).
2021-07-17 14:23:57 +00:00
2db4137514
Merge pull request #2874 from whitequark/cxxrtl-fix-2589
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cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
2021-07-16 11:12:19 +00:00
efc43270fa
Merge pull request #2873 from whitequark/cxxrtl-fix-2500
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cxxrtl: emit debug items for unused public wires
2021-07-16 11:01:10 +00:00
5b003d6e5c
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.
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The hierarchy pass does a lot more than just finding the top module,
mainly resolving implicit (positional, wildcard) module connections.
Fixes #2589 .
2021-07-16 10:27:47 +00:00
09218896d6
cxxrtl: emit debug items for unused public wires.
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This greatly improves debug information coverage.
Fixes #2500 .
2021-07-16 10:14:40 +00:00
b28ca7f5ac
cxxrtl: don't expect user cell inputs to be wires.
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Ports can be connected to constants, too. (Usually resets.)
Fixes #2521 .
2021-07-16 09:51:52 +00:00
44a3d924ce
cxxrtl: don't mark buffered internal wires as UNUSED for debug.
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Public wires may alias buffered internal wires, so keep BUFFERED
wires in debug information even if they are private. Debug items are
only created for public wires, so this does not otherwise affect how
debug information is emitted.
Fixes #2540 .
Fixes #2841 .
2021-07-16 07:54:49 +00:00
54b6cb645f
cxxrtl: mark dead local wires as unused even with inlining disabled.
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Fixes #2739 .
2021-07-15 22:27:27 +00:00
8bf9cb407d
kernel/mem: Add a coalesce_inits helper.
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While this helper is already useful to squash sequential initializations
into one in cxxrtl, its main purpose is to squash overlapping masked memory
initializations (when they land) and avoid having to deal with them in
cxxrtl runtime.
2021-07-13 15:59:11 +02:00
37506d737c
cxxrtl: Support memory writes in processes.
2021-07-12 18:27:48 +02:00
af7fa62251
cxxrtl: Add support for memory read port reset.
2021-07-12 18:27:48 +02:00
be5cf29699
cxxrtl: Add support for mem read port initial data.
2021-07-12 18:27:48 +02:00
d5c9595668
cxxrtl: Convert to Mem helpers.
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This *only* does conversion, but doesn't add any new functionality —
support for memory read port init/reset is still upcoming.
2021-07-12 18:27:48 +02:00
ab76d9cec5
cxxrtl: don't assert on edge sync rules tied to a constant.
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These are commonly the result of tying an async reset to an inactive
level.
2021-03-07 14:29:30 +00:00
d1de08e38a
cxxrtl: allow `always` sync rules in debug_eval.
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These can be produced from `always @*` processes, if `-noproc`
is used.
2021-03-07 14:28:45 +00:00
9dd813374e
Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
2021-03-05 05:30:19 -08:00
06da2e0f18
Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types
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cxxrtl: add pass debug flag to show assigned wire types
2021-03-05 04:57:22 -08:00
14ce8bdaa6
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
2021-03-05 12:09:02 +00:00
8471808834
cxxrtl: add pass debug flag to show assigned wire types.
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Refs #2543 .
2021-03-05 11:58:59 +00:00
a9a873a1d2
cxxrtl: don't crash on empty designs.
2021-03-05 11:05:19 +00:00
a77fa6709b
Merge pull request #2563 from whitequark/cxxrtl-msvc
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cxxrtl: do not use `->template` for non-dependent names
2021-01-26 21:55:12 +00:00
Catherine
Asherah Connor
Charlotte
Michael Nolan
Marcelina Kościelnicka