riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cxxrtl: don't assert on edge sync rules tied to a constant. 

These are commonly the result of tying an async reset to an inactive
level.
This commit is contained in:
whitequark 2021-03-07 14:29:30 +00:00
parent d1de08e38a
commit ab76d9cec5
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
backends/cxxrtl/cxxrtl_backend.cc
View File

@ -1518,6 +1518,8 @@ struct CxxrtlWorker {
if (!sync->signal.empty()) {
sync_bit = sync->signal[0];
sync_bit = sigmaps[sync_bit.wire->module](sync_bit);
if (!sync_bit.is_wire())
continue; // a clock, or more commonly a reset, can be tied to a constant driver
}
pool<std::string> events;
@ -2285,6 +2287,8 @@ struct CxxrtlWorker {
void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type)
{
signal = sigmap(signal);
if (signal.is_fully_const())
return; // a clock, or more commonly a reset, can be tied to a constant driver
log_assert(is_valid_clock(signal));
log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe);