mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: Add support for mem read port initial data.
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d5c9595668
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@ -686,6 +686,7 @@ struct CxxrtlWorker {
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dict<const RTLIL::Module*, SigMap> sigmaps;
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dict<const RTLIL::Module*, std::vector<Mem>> mod_memories;
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pool<const RTLIL::Wire*> edge_wires;
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dict<const RTLIL::Wire*, RTLIL::Const> wire_init;
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dict<RTLIL::SigBit, RTLIL::SyncType> edge_types;
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dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule, debug_schedule;
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dict<const RTLIL::Wire*, WireType> wire_types, debug_wire_types;
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@ -1681,17 +1682,17 @@ struct CxxrtlWorker {
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f << "<" << wire->width << ">";
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}
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f << " " << mangle(wire);
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if (wire->has_attribute(ID::init)) {
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if (wire_init.count(wire)) {
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f << " ";
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dump_const_init(wire->attributes.at(ID::init));
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dump_const_init(wire_init.at(wire));
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}
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f << ";\n";
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if (edge_wires[wire]) {
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if (!wire_type.is_buffered()) {
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f << indent << "value<" << wire->width << "> prev_" << mangle(wire);
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if (wire->has_attribute(ID::init)) {
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if (wire_init.count(wire)) {
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f << " ";
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dump_const_init(wire->attributes.at(ID::init));
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dump_const_init(wire_init.at(wire));
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}
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f << ";\n";
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}
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@ -2447,6 +2448,10 @@ struct CxxrtlWorker {
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continue;
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}
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for (auto wire : module->wires())
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if (wire->has_attribute(ID::init))
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wire_init[wire] = wire->attributes.at(ID::init);
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// Construct a flow graph where each node is a basic computational operation generally corresponding
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// to a fragment of the RTLIL netlist.
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FlowGraph flow;
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@ -2491,6 +2496,19 @@ struct CxxrtlWorker {
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if (is_valid_clock(port.clk))
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register_edge_signal(sigmap, port.clk,
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port.clk_polarity ? RTLIL::STp : RTLIL::STn);
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// For read ports, also move initial value to wire_init (if any).
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for (int i = 0; i < GetSize(port.data); i++) {
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if (port.init_value[i] != State::Sx) {
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SigBit bit = port.data[i];
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if (bit.wire) {
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auto &init = wire_init[bit.wire];
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if (init == RTLIL::Const()) {
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init = RTLIL::Const(State::Sx, GetSize(bit.wire));
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}
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init[bit.offset] = port.init_value[i];
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}
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}
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}
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}
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for (auto &port : mem.wr_ports) {
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if (port.clk_enable)
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