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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.

This commit is contained in:
whitequark 2021-03-05 12:08:48 +00:00
parent 7d2097b005
commit 14ce8bdaa6
1 changed files with 3 additions and 1 deletions
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4
backends/cxxrtl/cxxrtl_backend.cc
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@ -1231,7 +1231,9 @@ struct CxxrtlWorker {
RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
std::string valid_index_temp = fresh_temporary();
f << indent << "auto " << valid_index_temp << " = memory_index(";
dump_sigspec_rhs(cell->getPort(ID::ADDR));
// Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous
// memory read ports can.
dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug);
f << ", " << memory->start_offset << ", " << memory->size << ");\n";
if (cell->type == ID($memrd)) {
bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();