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yosys
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369 Commits

Author SHA1 Message Date
Clifford Wolf 9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf 548519875b Fixed bug (typo) in passes/opt/opt_const.cc 2014-02-22 17:07:22 +01:00
Clifford Wolf 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf 483c99fe46 Added "design -push" and "design -pop" 2014-02-20 23:28:59 +01:00
Clifford Wolf 0dadfed46d Added connwrappers command 2014-02-20 20:44:11 +01:00
Clifford Wolf 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-18 20:05:53 +01:00
Clifford Wolf a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ 2014-02-18 19:51:00 +01:00
Clifford Wolf a78bba1f5c Added "sat -dump_cnf" 2014-02-18 09:29:08 +01:00
Clifford Wolf 32af10fa9b Coding style corrections in SatHelper::dump_model_to_vcd() 2014-02-18 09:28:05 +01:00
Clifford Wolf 13051e6acf Added "sat -initsteps" 2014-02-18 09:03:16 +01:00
Clifford Wolf 0851c2b6ea Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups 2014-02-17 13:59:39 +01:00
Andrew Zonenberg 4a948d780a Added "-dump_fail_to_vcd" argument to SAT solver 2014-02-17 13:52:36 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean 2014-02-16 21:58:27 +01:00
Clifford Wolf 42ce3db983 Fixed use of selection in splitnets command 2014-02-16 17:39:50 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf 9a816b65a8 Added != support for relational select pattern 2014-02-16 00:16:54 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 67effc9f5b Fixed opt_const handling of double invert with non-1 output width 2014-02-15 13:16:08 +01:00
Clifford Wolf 3121d19d95 Added abc -keepff option 2014-02-14 11:28:42 +01:00
Clifford Wolf de3ea9269a updated default ABC command strings 2014-02-13 19:14:15 +01:00
Clifford Wolf a123941618 Updated ABC 2014-02-13 18:56:36 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf b463907890 Removed double blanks in ABC default command sequences 2014-02-13 08:12:52 +01:00
Clifford Wolf 7664f5d92b Updated ABC and some related changes 2014-02-13 08:07:08 +01:00
Clifford Wolf ab71bd0746 Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
Clifford Wolf 38469e7686 Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00
Clifford Wolf b6f33576d5 Added delete {-input|-output|-port} 2014-02-09 10:03:26 +01:00
Clifford Wolf b3b5fac191 Bugfix in delete command 2014-02-09 09:34:58 +01:00
Clifford Wolf 85914c36e5 Fixed handling of async reset in expose -evert-dff 2014-02-08 21:26:40 +01:00
Clifford Wolf db86aaa07d Build fixes for log cmd 2014-02-08 21:21:51 +01:00
Clifford Wolf c06de50f05 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-08 21:08:46 +01:00
Clifford Wolf 0935e20003 Implemented expose -evert-dff 2014-02-08 21:08:38 +01:00
Johann Glaser af14bb5f65 added "log" command 2014-02-08 19:19:32 +01:00
Clifford Wolf 7f52c18a22 Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect 2014-02-08 19:13:19 +01:00
Clifford Wolf 926fa61119 Added various new options to splice command 2014-02-08 16:37:18 +01:00
Clifford Wolf 0c11d04144 Added %a select operator 2014-02-08 16:31:38 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf 03ee63ff80 Added support for "keep" attribute to abc pass 2014-02-08 14:25:29 +01:00
Clifford Wolf 82c98bbbe6 Added opt -purge (frontend to opt_clean -purge) 2014-02-08 14:21:34 +01:00
Clifford Wolf 922d1c9520 Only count non-trivial attributes when findinf master signal in opt_clean 2014-02-08 14:21:04 +01:00
Clifford Wolf 2c51619c2b Now also move net labes to the right position in splice cmd 2014-02-08 00:06:00 +01:00
Clifford Wolf 274bcef66c Improved detection of primary wire for a signal in opt_clean 2014-02-07 23:50:17 +01:00
Clifford Wolf 244e8ce1f4 Added splice command 2014-02-07 20:30:56 +01:00