Commit Graph

170 Commits

Author SHA1 Message Date
whitequark 8a4841d786
Merge pull request #2141 from whitequark/cxxrtl-cxx11
cxxrtl: various compiler compatibility fixes
2020-06-10 17:10:15 +00:00
whitequark 6021ff727d cxxrtl: restore C++11 compatibility.
This is necessary to be able to build CXXRTL models via yosys-config.
2020-06-10 15:57:07 +00:00
whitequark cde99e696a cxxrtl: fix a few gcc warnings. 2020-06-10 15:57:07 +00:00
whitequark 574f5cb5b2 Fix formatting. NFC. 2020-06-10 15:48:40 +00:00
whitequark 0955a603c8 cxxrtl: disambiguate values/wires and their aliases in debug info.
With this change, it is easier to see which signals carry state (only
wire<>s appear as `reg` in VCD files) and to construct a minimal
checkpoint (CXXRTL_WIRE debug items represent the canonical smallest
set of state required to fully reconstruct the simulation).
2020-06-10 14:39:45 +00:00
whitequark 5467fe563a cxxrtl: allow unbuffering without localizing.
Although logically two separate steps, these were treated as one for
historic reasons. Splitting the two makes it possible to have designs
that are only 2× slower than fastest possible (and are without extra
delta cycles) that allow probing all public wires.
2020-06-09 21:50:09 +00:00
whitequark 970ec34e70 cxxrtl: order -On levels as localize, elide instead of the reverse.
Historically, elision was implemented before localization, so levels
with elision are lower than corresponding levels with localization.
This is unfortunate for two reasons:
  1. Elision is a logical subset of localization, since it equals to
     not giving a name to a temporary.
  2. "Localize" currently actually means "unbuffer and localize",
     and it would be useful to split those steps (at least for
     public wires) for improved design visibility.
2020-06-09 20:55:40 +00:00
whitequark ba11060e59 cxxrtl: factor out -noproc/-noflatten from -O.
Although these options can be thought of as optimizations, they are
essentially orthogonal to the core of -O, which is managing signal
buffering and scope. Going from -O4 to -O2 means going from limited
to complete design visibility, yet in both cases proc and flatten
are desirable.
2020-06-09 20:18:07 +00:00
whitequark bbfe55a8d0 cxxrtl: fix two buggy split_by functions. 2020-06-09 11:05:35 +00:00
whitequark 74e3ac2449
Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops
cxxrtl: ignore cell input signedness when it is irrelevant
2020-06-09 09:54:09 +00:00
whitequark ef4e159447 cxxrtl: ignore cell input signedness when it is irrelevant.
Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.
2020-06-09 07:26:13 +00:00
whitequark 4e7d837747 cxxrtl: add missing namespace.
Fixes #2124.
2020-06-09 06:26:43 +00:00
whitequark 53688a24b5 cxxrtl: fix format of hdlnames.
The CXXRTL code that handled the `hdlname` attribute implemented
outdated semantics.
2020-06-08 20:19:41 +00:00
whitequark 467152d79f cxxrtl: don't check immutable values for changes in VCD writer.
This commit changes the VCD writer such that for all signals that
have `debug_item.type == VALUE && debug_item.next == nullptr`, it
would only sample the value once.

Commit f2d7a187 added more debug information by including constant
wires, and decreased the performance of VCD writer proportionally
because the constant wires were still repeatedly sampled; this commit
eliminates the performance hit.
2020-06-08 17:38:11 +00:00
whitequark f2d7a18756 cxxrtl: emit debug information for constant wires.
Constant wires can represent a significant chunk of the design in
generic designs or after optimization. Emitting them in VCD files
significantly improves usability because gtkwave removes all traces
that are not present in the VCD file after reload, and iterative
development suffers if switching a varying signal to a constant
disrupts the workflow.
2020-06-08 17:29:08 +00:00
whitequark d5c07e5b6f cxxrtl: track aliases in VCD writer.
This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.

Commit 9b39c6f7 added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.
2020-06-08 17:10:45 +00:00
whitequark 9b39c6f744 cxxrtl: emit debug information for alias wires.
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
2020-06-08 17:09:49 +00:00
whitequark 8262997c4e cxxrtl: fix typo in comment. NFC. 2020-06-08 12:50:35 +00:00
whitequark fb3704c896 cxxrtl: minor debug-related improvements. 2020-06-08 12:50:35 +00:00
whitequark ff5500f11a cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
2020-06-07 03:48:40 +00:00
whitequark 31f6c96b1f cxxrtl: add a C API for writing VCD dumps.
This C API is fully featured.
2020-06-07 03:48:00 +00:00
whitequark 68362a9053 cxxrtl: only write VCD values that were actually updated.
On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
2020-06-07 03:48:00 +00:00
whitequark 9c36102669 cxxrtl: add a VCD writer using debug information. 2020-06-07 03:48:00 +00:00
whitequark c399359ed6 cxxrtl: add a C API for driving and introspecting designs.
Compared to the C++ API, the C API currently has two limitations:
  1. Memories cannot be updated in a race-free way.
  2. Black boxes cannot be implemented in C.
2020-06-06 21:12:55 +00:00
whitequark f6e16e7f4c cxxrtl: generate debug information for non-localized public wires.
Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.

The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
2020-06-06 21:12:55 +00:00
whitequark 025663adff cxxrtl: fix implementation of $sshr cell.
Fixes #2111.
2020-06-05 02:04:46 +00:00
whitequark 0bf6b164be cxxrtl: make logging a little bit nicer. 2020-05-26 21:37:32 +00:00
whitequark e9c07e2bda cxxrtl: add missing parts of commit 281c9685. 2020-05-26 21:34:20 +00:00
whitequark 281c96856a cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.
This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.
2020-05-22 19:08:30 +00:00
Xiretza d86fc791f9
Reorder cases to avoid fall-through warning
log_assert(false) never returns and thus can't fall through, but gcc
doesn't seem to think that far. Making it the last case avoids the
problem entirely.
2020-05-07 13:39:34 +02:00
Xiretza 695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
David Shah 1b93dda037 cxxrtl: Round up constant width
Signed-off-by: David Shah <dave@ds0.me>
2020-04-25 10:42:21 +01:00
whitequark a0e658d412 cxxrtl: use `cxxrtl_` prefix rather than `cxxrtl.`
The former prefix does not need to be escaped in Verilog, unlike
the latter, and the Yosys convention is to use the former.
2020-04-24 18:35:53 +00:00
whitequark f88378ae61 cxxrtl: improve printing of narrow memories. 2020-04-24 05:50:36 +00:00
whitequark 3738391bdd cxxrtl: fix handling of parametric modules with large parameters.
These have a `$paramod$` prefix, not `$paramod\\`.
2020-04-24 05:44:39 +00:00
Asu dc77563a6a cxxrtl: keep the memory write queue sorted on insertion.
Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.

The Minerva SRAM SoC runs ~7% faster as a result.
2020-04-22 20:53:12 +02:00
whitequark 93288b8eae cxxrtl: run edge detectors only once in eval().
As a result, Minerva SRAM SoC runs ~15% faster.
2020-04-22 12:47:28 +00:00
whitequark 1d5b6ac253 cxxrtl: add an unsupported knob for manipulating clock trees.
This is quite possibly the worst way to implement this, but it does
work for a subset of well-behaved designs, and can be used to measure
how much performance is lost simulating the inactive edge of a clock.

It should be replaced with a clock tree analyzer generating safe
code once it is clear how should such a thing look like.
2020-04-22 01:15:27 +00:00
whitequark 5f17e0ced5 cxxrtl: use log_id() where appropriate. NFC. 2020-04-21 23:42:56 +00:00
whitequark d22a8d157d cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.
If the annotations are not used, this commit does not alter semantics
at all, other than removing elision of outputs of black box cells.
(Elision of such outputs is expected to be too rare to have any
noticeable benefit, and the implementation was somewhat of a hack.)

The (* cxxrtl.comb *) annotation alters the semantics of the output
of the black box it is applied to such that, if the black box
converges immediately, no additional delta cycle is necessary to
propagate the computed combinatorial value upwards in hierarchy.

The (* cxxrtl.sync *) annotation alters the semantics of the output
of the black box it is applied to such as to remove any uses of
the black box by the wires connected to this output, and break false
feedback arcs arising from conservative modeling of dependencies of
the black box.

Although currently these attributes are only recognized on black
boxes, if separate compilation is added in the future, it could also
emit and consume them.
2020-04-21 22:08:36 +00:00
whitequark 164b0746d2 cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.
The attribute for this is called (* cxxrtl.edge *), and there is
a planned attribute (* cxxrtl.sync *) that would cause blackbox
cell outputs to be added to sync defs rather than comb defs.
Rename the edge detector related stuff to avoid confusion.
2020-04-21 18:46:36 +00:00
whitequark 4aa0f450f5 cxxrtl: use one delta cycle for immediately converging netlists.
If it is statically known that eval() will converge in one delta
cycle (that is, the second commit() will always return `false`)
because the design contains no feedback or buffered wires, then
there is no need to run the second delta cycle at all.

After this commit, the case where eval() always converges immediately
is detected and the second delta cycle is omitted. As a result,
Minerva SRAM SoC runs ~25% faster.
2020-04-21 16:14:45 +00:00
whitequark 7f5313e6c3 cxxrtl: add -O6, a shortcut for running `proc; flatten`.
People judge a compiler backend by the first impression, and
the metric they judge it for is speed. -O6 does severely impact
debuggability, but it provides equally massive gains in performance,
so use it by default.
2020-04-21 15:33:12 +00:00
whitequark 06985c3afd cxxrtl: unbuffer module input wires.
Module input wires are never set by the module, so it is unnecessary
to buffer them. Although important for all inputs, this is especially
critical for clocks, since after this commit, hierarchy levels no
longer add delta cycles. As a result, Minerva SRAM SoC runs ~73%
faster when flattened, and ~264% (!!) faster when hierarchical.
2020-04-21 15:27:19 +00:00
whitequark 12c5e9275c cxxrtl: simplify generated edge detection logic.
This commit changes the way edge detectors are represented in
generated code from a variable that is set in commit() and reset in
eval() to a function that considers .curr and .next of the clock
wire. Behavior remains the same. Besides being simpler to generate
and providing more opportunities for optimization, this commit paves
way for unbuffering module inputs.
2020-04-21 13:59:42 +00:00
whitequark 757cbb3c80 cxxrtl: localize wires with multiple comb drivers, too.
Before this commit, any wire that was not driven by an output port of
exactly one comb cell would not be localized, even if there were no
feedback arcs through that wire. This would cause the wire to become
buffered and require (often quite a few) extraneous delta cycles
during evaluation. To alleviate this problem, -O5 was running
`splitnets -driver`.

However, this solution was mistaken. Because `splitnets -driver`
followed by `opt_clean -purge` would produce more nets with multiple
drivers, it would have to be iterated to fixpoint. Moreover, even if
this was done, it would not be sufficient because `opt_clean -purge`
does not currently remove wires with the `\init` attribute (and it
is not desirable to remove such wires, since they correspond to
registers and may be useful for debugging).

The proper solution is to consider the condition in which a wire
may be localized. Specifically, if there are no feedback arcs through
this wire, and no part of the wire is driven by an output of a sync
cell, then the wire holds no state and is localizable.

After this commit, the original condition for not localizing a wire
is replaced by a check for any sync cell driving it. This makes it
unnecessary to run `splitnets -driver` in the majority of cases
to get a design with no buffered wires, and -O5 no longer includes
that pass. As a result, Minerva SRAM SoC no longer has any buffered
wires, and runs ~27% faster.

In addition, this commit prepares the flow graph for introduction
of sync outputs of black boxes.

Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
2020-04-21 13:36:50 +00:00
whitequark f24fb4ae82 cxxrtl: detect buffered comb wires, not just feedback wires.
Any buffered combinatorial wires (including, as a subset, feedback
wires) will prevent the design from always converging in one delta
cycle. Before this commit, only feedback wires were detected. After
this commit, any buffered combinatorial wires, including feedback
wires, are detected.

Co-authored-by: Jean-François Nguyen <jf@lambdaconcept.com>
2020-04-21 13:36:50 +00:00
whitequark bf0f96b847 cxxrtl: provide attributes to black box factories, too.
Both parameters and attributes are necessary because the parameters
have to be the same between every instantiation of the cell, but
attributes may well vary. For example, for an UART PHY, the type
of the PHY (tty, pty, socket) would be a parameter, but configuration
of the implementation specified by the type (socket address) would
be an attribute.
2020-04-19 16:30:54 +00:00
whitequark 63d2a30857 cxxrtl: add templated black box support. 2020-04-18 08:04:57 +00:00
whitequark ab4297c326 cxxrtl: make eval() and commit() inline in blackboxes.
This change is a preparation for template blackboxes. It has no
effect on current generated code.
2020-04-18 04:38:50 +00:00
whitequark 2b88d9a3fe cxxrtl: add simple black box support.
This commit adds support for replacing RTLIL modules with CXXRTL
black boxes. Black box port widths may not depend on the parameters
with which it is instantiated (yet); the parameters may only be used
to change the behavior of the black box.
2020-04-18 04:35:10 +00:00
whitequark 8bc3cd30dc cxxrtl: use ID::X instead of ID(X). NFC. 2020-04-18 04:35:10 +00:00
whitequark e7ad209b15 cxxrtl: correctly handle `sync always` rules.
Fixes #1948.
2020-04-17 09:43:13 +00:00
whitequark 06c0338f2c cxxrtl: make ROMs writable, document memory::operator[].
There is no practical benefit from using `const memory` for ROMs;
it uses an std::vector internally, which prevents contemporary
compilers from constant-propagating ROM contents. (It is not clear
whether they are permitted to do so.)

However, there is a major benefit from using non-const `memory` for
ROMs, which is the ability to dynamically fill the ROM for each
individual simulation.
2020-04-16 16:45:54 +00:00
whitequark 9043632dcc cxxrtl: fix misleading example, caution about race conditions.
Fixes #1944.
2020-04-16 16:45:54 +00:00
whitequark 58e89cd368 cxxrtl: remove inaccurate comment. NFC. 2020-04-16 16:45:54 +00:00
David Shah 3b85b7c57a cxxrtl: Fix handling of unclocked memory read ports
Signed-off-by: David Shah <dave@ds0.me>
2020-04-14 20:39:13 +01:00
whitequark d8f2a1fda0
Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs
write_cxxrtl: ignore disconnected module ports
2020-04-14 14:37:48 +00:00
whitequark 0d0bf9c4a2 write_cxxrtl: ignore disconnected module ports.
E.g. port `q` in `submod x(.p(p), .q());`.

Fixes #1920.
2020-04-14 12:36:20 +00:00
whitequark 102fb5424f write_cxxrtl: enable separate compilation.
This commit makes it possible to use several cxxrtl-generated files
in one application, as well as compiling cxxrtl-generated code as
a separate compilation unit.
2020-04-14 12:07:58 +00:00
whitequark 4737f426ff write_cxxrtl: add basic documentation. 2020-04-09 04:08:36 +00:00
whitequark 753e34007d write_cxxrtl: add support for $dlatch and $dlatchsr cells.
Also, fix codegen for $dffe and $adff.
2020-04-09 04:08:36 +00:00
whitequark 711df56ad0 write_cxxrtl: add support for $sr cell.
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
2020-04-09 04:08:36 +00:00
whitequark 9534b51277 write_cxxrtl: add support for $slice and $concat cells. 2020-04-09 04:08:36 +00:00
whitequark 01e6850bd3 write_cxxrtl: improve writable memory handling.
This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
2020-04-09 04:08:36 +00:00
whitequark fb0270b752 write_cxxrtl: add support for hierarchical designs.
Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
 1. Since the `flatten` pass currently does not support flattening
    of designs with processes, this is the only way to simulate such
    designs with cxxrtl.
 2. Support for hierarchy paves way for simulation black boxes,
    which are necessary for e.g. replacing PHYs with C++ code that
    integrates with the host system.
2020-04-09 04:08:36 +00:00
whitequark 3376dcf37c write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.
After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.

This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
2020-04-09 04:08:36 +00:00
whitequark 5157691f0e write_cxxrtl: statically schedule comb logic and localize wires.
This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
2020-04-09 04:08:36 +00:00
whitequark d6d7273421 write_cxxrtl: elide wires for results of comb cells used once.
This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.
2020-04-09 04:08:36 +00:00
whitequark d20e971725 write_cxxrtl: new backend.
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00