mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: add a C API for driving and introspecting designs.
Compared to the C++ API, the C API currently has two limitations: 1. Memories cannot be updated in a race-free way. 2. Black boxes cannot be implemented in C.
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c399359ed6
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@ -1778,6 +1778,7 @@ struct CxxrtlWorker {
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void dump_design(RTLIL::Design *design)
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{
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RTLIL::Module *top_module = nullptr;
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std::vector<RTLIL::Module*> modules;
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TopoSort<RTLIL::Module*> topo_design;
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for (auto module : design->modules()) {
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@ -1787,6 +1788,8 @@ struct CxxrtlWorker {
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modules.push_back(module); // cxxrtl blackboxes first
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if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
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continue;
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if (module->get_bool_attribute(ID::top))
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top_module = module;
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topo_design.node(module);
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for (auto cell : module->cells()) {
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@ -1808,6 +1811,25 @@ struct CxxrtlWorker {
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f << "#ifndef " << include_guard << "\n";
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f << "#define " << include_guard << "\n";
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f << "\n";
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if (top_module != nullptr && debug_info) {
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f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
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f << "\n";
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f << "#ifdef __cplusplus\n";
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f << "extern \"C\" {\n";
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f << "#endif\n";
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f << "\n";
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f << "cxxrtl_toplevel " << design_ns << "_create();\n";
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f << "\n";
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f << "#ifdef __cplusplus\n";
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f << "}\n";
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f << "#endif\n";
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f << "\n";
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} else {
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f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
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f << "\n";
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}
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f << "#ifdef __cplusplus\n";
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f << "\n";
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f << "#include <backends/cxxrtl/cxxrtl.h>\n";
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f << "\n";
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f << "using namespace cxxrtl;\n";
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@ -1818,6 +1840,8 @@ struct CxxrtlWorker {
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dump_module_intf(module);
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f << "} // namespace " << design_ns << "\n";
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f << "\n";
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f << "#endif // __cplusplus\n";
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f << "\n";
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f << "#endif\n";
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*intf_f << f.str(); f.str("");
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}
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@ -1827,6 +1851,10 @@ struct CxxrtlWorker {
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else
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f << "#include <backends/cxxrtl/cxxrtl.h>\n";
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f << "\n";
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f << "#ifdef CXXRTL_INCLUDE_CAPI_IMPL\n";
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f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
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f << "#endif\n";
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f << "\n";
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f << "using namespace cxxrtl_yosys;\n";
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f << "\n";
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f << "namespace " << design_ns << " {\n";
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@ -1837,6 +1865,17 @@ struct CxxrtlWorker {
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dump_module_impl(module);
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}
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f << "} // namespace " << design_ns << "\n";
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f << "\n";
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if (top_module != nullptr && debug_info) {
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f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
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inc_indent();
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f << indent << "return new _cxxrtl_toplevel { ";
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f << "std::make_unique<" << design_ns << "::" << mangle(top_module) << ">()";
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f << " };\n";
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dec_indent();
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f << "}\n";
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}
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*impl_f << f.str(); f.str("");
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}
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@ -33,13 +33,15 @@
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#include <memory>
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#include <sstream>
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// The cxxrtl support library implements compile time specialized arbitrary width arithmetics, as well as provides
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#include <backends/cxxrtl/cxxrtl_capi.h>
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// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides
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// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass
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// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler
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// to unwrap the abstraction and generate efficient code.
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namespace cxxrtl {
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// All arbitrary-width values in cxxrtl are backed by arrays of unsigned integers called chunks. The chunk size
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// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size
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// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving
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// and introspecting the simulation in Python.
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//
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@ -716,39 +718,49 @@ typedef std::map<std::string, metadata> metadata_map;
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// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
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// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.
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struct debug_item {
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//
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// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used
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// in the C API, or it would not be possible to cast between the pointers to these.
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struct debug_item : ::cxxrtl_object {
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enum : uint32_t {
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VALUE = 0,
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WIRE = 1,
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MEMORY = 2,
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} type;
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size_t width; // in bits
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size_t depth; // 1 if `type != MEMORY`
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chunk_t *curr;
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chunk_t *next; // nullptr if `type == VALUE || type == MEMORY`
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VALUE = CXXRTL_VALUE,
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WIRE = CXXRTL_WIRE,
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MEMORY = CXXRTL_MEMORY,
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};
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template<size_t Bits>
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debug_item(value<Bits> &item) : type(VALUE), width(Bits), depth(1),
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curr(item.data), next(nullptr) {
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static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
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"value<Bits> is not compatible with C layout");
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}
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debug_item(value<Bits> &item) {
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static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
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"value<Bits> is not compatible with C layout");
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type = VALUE;
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width = Bits;
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depth = 1;
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curr = item.data;
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next = item.data;
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}
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template<size_t Bits>
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debug_item(wire<Bits> &item) : type(WIRE), width(Bits), depth(1),
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curr(item.curr.data), next(item.next.data) {
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static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
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sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
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"wire<Bits> is not compatible with C layout");
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}
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debug_item(wire<Bits> &item) {
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static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
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sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
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"wire<Bits> is not compatible with C layout");
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type = WIRE;
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width = Bits;
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depth = 1;
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curr = item.curr.data;
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next = item.next.data;
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}
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template<size_t Width>
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debug_item(memory<Width> &item) : type(MEMORY), width(Width), depth(item.data.size()),
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curr(item.data.empty() ? nullptr : item.data[0].data), next(nullptr) {
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static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
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"memory<Width> is not compatible with C layout");
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}
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debug_item(memory<Width> &item) {
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static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
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"memory<Width> is not compatible with C layout");
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type = MEMORY;
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width = Width;
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depth = item.data.size();
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curr = item.data.empty() ? nullptr : item.data[0].data;
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next = nullptr;
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}
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};
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static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
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@ -779,7 +791,12 @@ struct module {
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} // namespace cxxrtl
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// Definitions of internal Yosys cells. Other than the functions in this namespace, cxxrtl is fully generic
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// Internal structure used to communicate with the implementation of the C interface.
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typedef struct _cxxrtl_toplevel {
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std::unique_ptr<cxxrtl::module> module;
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} *cxxrtl_toplevel;
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// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic
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// and indepenent of Yosys implementation details.
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//
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// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these
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@ -0,0 +1,55 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.h`.
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#include <backends/cxxrtl/cxxrtl.h>
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#include <backends/cxxrtl/cxxrtl_capi.h>
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struct _cxxrtl_handle {
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std::unique_ptr<cxxrtl::module> module;
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cxxrtl::debug_items objects;
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};
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cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design) {
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cxxrtl_handle handle = new _cxxrtl_handle;
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handle->module = std::move(design->module);
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handle->module->debug_info(handle->objects);
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delete design;
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return handle;
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}
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void cxxrtl_destroy(cxxrtl_handle handle) {
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delete handle;
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}
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size_t cxxrtl_step(cxxrtl_handle handle) {
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return handle->module->step();
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}
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cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) {
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if (handle->objects.count(name) > 0)
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return static_cast<cxxrtl_object*>(&handle->objects.at(name));
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return nullptr;
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}
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void cxxrtl_enum(cxxrtl_handle handle, void *data,
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void (*callback)(void *data, const char *name, struct cxxrtl_object *object)) {
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for (auto &it : handle->objects)
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callback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second));
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}
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@ -0,0 +1,151 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 whitequark <whitequark@whitequark.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CXXRTL_CAPI_H
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#define CXXRTL_CAPI_H
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// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.cc`.
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//
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// The CXXRTL C API makes it possible to drive CXXRTL designs using C or any other language that
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// supports the C ABI, for example, Python. It does not provide a way to implement black boxes.
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#include <stddef.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Opaque reference to a design toplevel.
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//
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// A design toplevel can only be used to create a design handle.
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typedef struct _cxxrtl_toplevel *cxxrtl_toplevel;
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// The constructor for a design toplevel is provided as a part of generated code for that design.
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// Its prototype matches:
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//
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// cxxrtl_toplevel <design-name>_create();
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// Opaque reference to a design handle.
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//
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// A design handle is required by all operations in the C API.
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typedef struct _cxxrtl_handle *cxxrtl_handle;
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// Create a design handle from a design toplevel.
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//
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// The `design` is consumed by this operation and cannot be used afterwards.
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cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);
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// Release all resources used by a design and its handle.
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void cxxrtl_destroy(cxxrtl_handle handle);
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// Simulate the design to a fixed point.
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//
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// Returns the number of delta cycles.
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size_t cxxrtl_step(cxxrtl_handle handle);
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// Type of a simulated object.
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enum cxxrtl_type {
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// Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by
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// combinatorial cells, or toplevel input nodes.
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//
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// Values can be inspected via the `curr` pointer and modified via the `next` pointer (which are
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// equal for values); however, note that changes to the bits driven by combinatorial cells will
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// be ignored.
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//
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// Values always have depth 1.
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CXXRTL_VALUE = 0,
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// Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by
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// storage cells, or by combinatorial cells that are a part of a feedback path.
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//
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// Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are
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// distinct for wires); however, note that changes to the bits driven by combinatorial cells will
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// be ignored.
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//
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// Wires always have depth 1.
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CXXRTL_WIRE = 1,
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// Memories correspond to memory cells.
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//
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// Memories can be inspected and modified via the `curr` pointer. Due to a limitation of this
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// API, memories cannot yet be modified in a guaranteed race-free way, and the `next` pointer is
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// always NULL.
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CXXRTL_MEMORY = 2,
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// More object types will be added in the future, but the existing ones will never change.
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};
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// Description of a simulated object.
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//
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// The `data` array can be accessed directly to inspect and, if applicable, modify the bits
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// stored in the object.
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struct cxxrtl_object {
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// Type of the object.
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//
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// All objects have the same memory layout determined by `width` and `depth`, but the type
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// determines all other properties of the object.
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uint32_t type; // actually `enum cxxrtl_type`
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// Width of the object in bits.
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size_t width;
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// Depth of the object. Only meaningful for memories; for other objects, always 1.
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size_t depth;
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// Bits stored in the object, as 32-bit chunks, least significant bits first.
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//
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// The width is rounded up to a multiple of 32; the padding bits are always set to 0 by
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// the simulation code, and must be always written as 0 when modified by user code.
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// In memories, every element is stored contiguously. Therefore, the total number of chunks
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// in any object is `((width + 31) / 32) * depth`.
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//
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// To allow the simulation to be partitioned into multiple independent units communicating
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// through wires, the bits are double buffered. To avoid race conditions, user code should
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// always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects
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// that cannot be modified, or cannot be modified in a race-free way, `next` is NULL.
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uint32_t *curr;
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uint32_t *next;
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// More description fields will be added in the future, but the existing ones will never change.
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};
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// Retrieve description of a simulated object.
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//
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// The `name` is the full hierarchical name of the object in the Yosys notation, where public names
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// have a `\` prefix and hierarchy levels are separated by single spaces. For example, if
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// the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full
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// hierarchical name is `\foo \bar`.
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//
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// Returns the object if it was found, NULL otherwise. The returned value is valid until the design
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// is destroyed.
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struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name);
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// Enumerate simulated objects.
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//
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// For every object in the simulation, `callback` is called with the provided `data`, the full
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// hierarchical name of the object (see `cxxrtl_get` for details), and the object description.
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// The provided `name` and `object` values are valid until the design is destroyed.
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void cxxrtl_enum(cxxrtl_handle handle, void *data,
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void (*callback)(void *data, const char *name, struct cxxrtl_object *object));
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#ifdef __cplusplus
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}
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#endif
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#endif
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