mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: allow unbuffering without localizing.
Although logically two separate steps, these were treated as one for historic reasons. Splitting the two makes it possible to have designs that are only 2× slower than fastest possible (and are without extra delta cycles) that allow probing all public wires.
This commit is contained in:
whitequark
parent
970ec34e70
commit
5467fe563a
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@ -530,10 +530,12 @@ struct CxxrtlWorker {
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bool run_flatten = false;
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bool run_proc = false;
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bool elide_internal = false;
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bool elide_public = false;
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bool unbuffer_internal = false;
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bool unbuffer_public = false;
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bool localize_internal = false;
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bool localize_public = false;
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bool elide_internal = false;
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bool elide_public = false;
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bool debug_info = false;
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@ -548,6 +550,7 @@ struct CxxrtlWorker {
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dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
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dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
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dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
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pool<const RTLIL::Wire*> unbuffered_wires;
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pool<const RTLIL::Wire*> localized_wires;
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dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
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dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
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@ -787,7 +790,8 @@ struct CxxrtlWorker {
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dump_const(chunk.data, chunk.width, chunk.offset);
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return false;
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} else {
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if (!is_lhs && elided_wires.count(chunk.wire)) {
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if (elided_wires.count(chunk.wire)) {
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log_assert(!is_lhs);
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const FlowGraph::Node &node = elided_wires[chunk.wire];
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switch (node.type) {
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case FlowGraph::Node::Type::CONNECT:
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@ -800,7 +804,7 @@ struct CxxrtlWorker {
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default:
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log_assert(false);
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}
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} else if (localized_wires[chunk.wire] || is_input_wire(chunk.wire)) {
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} else if (unbuffered_wires[chunk.wire] || is_input_wire(chunk.wire)) {
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f << mangle(chunk.wire);
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} else {
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f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
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@ -1435,13 +1439,13 @@ struct CxxrtlWorker {
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{
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if (elided_wires.count(wire))
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return;
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if (localized_wires.count(wire) != is_local_context)
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return;
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if (is_local_context) {
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dump_attrs(wire);
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f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
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} else {
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if (unbuffered_wires[wire]) {
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if (localized_wires[wire] == is_local_context) {
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dump_attrs(wire);
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f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
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}
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} else if (!is_local_context) {
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std::string width;
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if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
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width = wire->get_string_attribute(ID(cxxrtl_width));
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@ -1591,7 +1595,7 @@ struct CxxrtlWorker {
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inc_indent();
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f << indent << "bool changed = false;\n";
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for (auto wire : module->wires()) {
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if (elided_wires.count(wire) || localized_wires.count(wire))
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if (elided_wires.count(wire) || unbuffered_wires.count(wire))
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continue;
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if (is_input_wire(wire)) {
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if (edge_wires[wire])
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@ -1620,6 +1624,7 @@ struct CxxrtlWorker {
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void dump_debug_info_method(RTLIL::Module *module)
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{
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size_t count_public_wires = 0;
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size_t count_const_wires = 0;
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size_t count_alias_wires = 0;
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size_t count_member_wires = 0;
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@ -1629,6 +1634,7 @@ struct CxxrtlWorker {
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for (auto wire : module->wires()) {
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if (wire->name[0] != '\\')
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continue;
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count_public_wires++;
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if (debug_const_wires.count(wire)) {
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// Wire tied to a constant
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f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
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@ -1666,11 +1672,12 @@ struct CxxrtlWorker {
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}
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dec_indent();
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log_debug("Debug information statistics for module %s:\n", log_id(module));
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log_debug(" Const wires: %zu\n", count_const_wires);
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log_debug(" Alias wires: %zu\n", count_alias_wires);
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log_debug(" Member wires: %zu\n", count_member_wires);
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log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
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log_debug("Debug information statistics for module `%s':\n", log_id(module));
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log_debug(" Public wires: %zu, of which:\n", count_public_wires);
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log_debug(" Const wires: %zu\n", count_const_wires);
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log_debug(" Alias wires: %zu\n", count_alias_wires);
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log_debug(" Member wires: %zu\n", count_member_wires);
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log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
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}
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void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
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@ -1950,7 +1957,7 @@ struct CxxrtlWorker {
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void analyze_design(RTLIL::Design *design)
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{
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bool has_feedback_arcs = false;
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bool has_buffered_wires = false;
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bool has_buffered_comb_wires = false;
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for (auto module : design->modules()) {
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if (!design->selected_module(module))
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@ -2152,10 +2159,13 @@ struct CxxrtlWorker {
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if (feedback_wires[wire]) continue;
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if (wire->port_id != 0) continue;
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if (wire->get_bool_attribute(ID::keep)) continue;
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if (wire->name.begins_with("$") && !localize_internal) continue;
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if (wire->name.begins_with("\\") && !localize_public) continue;
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if (wire->name.begins_with("$") && !unbuffer_internal) continue;
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if (wire->name.begins_with("\\") && !unbuffer_public) continue;
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if (edge_wires[wire]) continue;
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if (flow.wire_sync_defs.count(wire) > 0) continue;
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unbuffered_wires.insert(wire);
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if (wire->name.begins_with("$") && !localize_internal) continue;
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if (wire->name.begins_with("\\") && !localize_public) continue;
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localized_wires.insert(wire);
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}
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@ -2165,21 +2175,19 @@ struct CxxrtlWorker {
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// it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
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// as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
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// also require more than one delta cycle to converge.
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pool<const RTLIL::Wire*> buffered_wires;
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pool<const RTLIL::Wire*> buffered_comb_wires;
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for (auto wire : module->wires()) {
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if (flow.wire_comb_defs[wire].size() > 0 && !elided_wires.count(wire) && !localized_wires[wire]) {
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if (!feedback_wires[wire])
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buffered_wires.insert(wire);
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}
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if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
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buffered_comb_wires.insert(wire);
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}
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if (!buffered_wires.empty()) {
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has_buffered_wires = true;
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if (!buffered_comb_wires.empty()) {
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has_buffered_comb_wires = true;
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log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
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for (auto wire : buffered_wires)
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for (auto wire : buffered_comb_wires)
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log(" %s\n", log_id(wire));
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}
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eval_converges[module] = feedback_wires.empty() && buffered_wires.empty();
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eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
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if (debug_info) {
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// Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
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@ -2190,7 +2198,7 @@ struct CxxrtlWorker {
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for (auto wire : module->wires()) {
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if (wire->name[0] != '\\')
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continue;
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if (!localized_wires[wire])
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if (!unbuffered_wires[wire])
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continue;
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const RTLIL::Wire *wire_it = wire;
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while (1) {
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@ -2203,7 +2211,7 @@ struct CxxrtlWorker {
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RTLIL::SigSpec rhs_sig = node->connect.second;
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if (rhs_sig.is_wire()) {
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RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
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if (localized_wires[rhs_wire]) {
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if (unbuffered_wires[rhs_wire]) {
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wire_it = rhs_wire; // maybe an alias
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} else {
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debug_alias_wires[wire] = rhs_wire; // is an alias
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@ -2219,14 +2227,14 @@ struct CxxrtlWorker {
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}
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}
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}
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if (has_feedback_arcs || has_buffered_wires) {
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if (has_feedback_arcs || has_buffered_comb_wires) {
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// Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
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// by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
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// likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
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const char *why_pessimistic = nullptr;
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if (has_feedback_arcs)
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why_pessimistic = "feedback wires";
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else if (has_buffered_wires)
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else if (has_buffered_comb_wires)
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why_pessimistic = "buffered combinatorial wires";
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log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
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if (!run_flatten)
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@ -2298,7 +2306,8 @@ struct CxxrtlWorker {
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};
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struct CxxrtlBackend : public Backend {
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static const int DEFAULT_OPT_LEVEL = 4;
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static const int DEFAULT_OPT_LEVEL = 6;
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static const int OPT_LEVEL_DEBUG = 4;
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static const int DEFAULT_DEBUG_LEVEL = 1;
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CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
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@ -2493,13 +2502,23 @@ struct CxxrtlBackend : public Backend {
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log(" localize internal wires if possible.\n");
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log("\n");
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log(" -O2\n");
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log(" like -O1, and elide internal wires if possible.\n");
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log(" like -O1, and unbuffer internal wires if possible.\n");
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log("\n");
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log(" -O3\n");
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log(" like -O2, and localize public wires not marked (*keep*) if possible.\n");
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log(" like -O2, and elide internal wires if possible.\n");
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log("\n");
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log(" -O4\n");
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log(" like -O3, and elide public wires not marked (*keep*) if possible.\n");
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log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
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log("\n");
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log(" -O5\n");
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log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
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log("\n");
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log(" -O6\n");
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log(" like -O5, and elide public wires not marked (*keep*) if possible.\n");
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log("\n");
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log(" -Og\n");
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log(" highest optimization level that provides debug information for all\n");
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log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG);
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log("\n");
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log(" -g <level>\n");
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log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
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@ -2535,6 +2554,15 @@ struct CxxrtlBackend : public Backend {
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noproc = true;
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continue;
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}
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if (args[argidx] == "-Og") {
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opt_level = OPT_LEVEL_DEBUG;
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continue;
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}
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if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
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argidx++;
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opt_level = OPT_LEVEL_DEBUG;
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continue;
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}
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if (args[argidx] == "-O" && argidx+1 < args.size()) {
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opt_level = std::stoi(args[++argidx]);
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continue;
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@ -2567,18 +2595,24 @@ struct CxxrtlBackend : public Backend {
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worker.run_proc = !noproc;
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switch (opt_level) {
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// the highest level here must match DEFAULT_OPT_LEVEL
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case 4:
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case 6:
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worker.elide_public = true;
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YS_FALLTHROUGH
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case 3:
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case 5:
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worker.localize_public = true;
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YS_FALLTHROUGH
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case 2:
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case 4:
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worker.unbuffer_public = true;
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YS_FALLTHROUGH
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case 3:
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worker.elide_internal = true;
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YS_FALLTHROUGH
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case 1:
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case 2:
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worker.localize_internal = true;
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YS_FALLTHROUGH
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case 1:
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worker.unbuffer_internal = true;
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YS_FALLTHROUGH
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case 0:
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break;
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default:
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