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Author SHA1 Message Date
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung 88d5185596 Merge remote-tracking branch 'origin/master' into eddie/fix_1262 2019-08-11 21:13:40 -07:00
Eddie Hung 282cc77604 Wrong way around 2019-08-10 11:55:00 -07:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung 02b0d328ad cover_list -> cover as per @cliffordwolf 2019-08-10 08:26:41 -07:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf dad9514d86
Merge pull request #1276 from YosysHQ/clifford/fix1273 
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
 2019-08-10 09:38:22 +02:00
Eddie Hung 849e0eeab4 Grammar 2019-08-09 12:43:21 -07:00
Eddie Hung 31f6d74552 Separate $alu handling 2019-08-09 12:13:32 -07:00
Eddie Hung 9f1b82f594 opt_expr -fine to trim LSBs of $alu too 2019-08-09 10:32:12 -07:00
Clifford Wolf 6d0be8d206 Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-09 19:17:59 +02:00
whitequark 39f4c1096a
Merge pull request #1267 from whitequark/proc_prune-fix-1243 
proc_prune: fix handling of exactly identical assigns
 2019-08-09 17:10:46 +00:00
Eddie Hung ac2fc3a144
Merge pull request #1264 from YosysHQ/eddie/fix_1254 
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
 2019-08-08 07:58:33 -07:00
whitequark 0b09a347dc proc_prune: fix handling of exactly identical assigns. 
Before this commit, in a process like:
   process $proc$bug.v:8$3
     assign $foo \bar
     switch \sel
       case 1'1
         assign $foo 1'1
         assign $foo 1'1
       case
         assign $foo 1'0
     end
   end
both of the "assign $foo 1'1" would incorrectly be removed.

Fixes #1243.
 2019-08-08 05:32:35 +00:00
Eddie Hung 675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung f69410daaf opt_lut to ignore LUT cells, or those that drive bits, with (* keep *) 2019-08-07 13:15:02 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung 0c78c62d6c Remove std:: namespace 2019-08-07 11:11:14 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung 58e512ab70 Add comment 2019-08-07 09:54:27 -07:00
Eddie Hung f20acbc813 Revert "Add TODO" 
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
 2019-08-07 09:54:27 -07:00
Eddie Hung 789585a744 Add TODO 2019-08-07 09:54:27 -07:00
Eddie Hung 8a8c1d7857 Compute box_lookup just once 2019-08-07 09:54:27 -07:00
Clifford Wolf e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
Clifford Wolf 338f6765eb Tweak default gate costs, cleanup "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 10:25:51 +02:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung 234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung 046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf 100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Eddie Hung 43081337fa Cleanup opt_expr.cc 2019-08-06 16:04:21 -07:00
Eddie Hung bfc7164af7 Move LSB-trimming functionality from wreduce to opt_expr 2019-08-06 15:25:50 -07:00
Eddie Hung 26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
whitequark 44a9dcbbbf
Merge pull request #1242 from jfng/fix-proc_prune-partial 
proc_prune: Promote partially redundant assignments.
 2019-08-03 07:08:41 +00:00
Clifford Wolf 0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Jean-François Nguyen 320bf2fde5 proc_prune: Promote partially redundant assignments. 2019-08-01 13:09:55 +02:00
Miodrag Milanovic 35d28de478 Visual Studio build fix 2019-07-31 09:10:24 +02:00
Clifford Wolf c6d8692c97 Add "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-20 15:06:28 +02:00
Eddie Hung 09beeee38a Try and fix again 2019-07-19 14:40:57 -07:00
Eddie Hung cb0fd05215 Do not access beyond bounds 2019-07-19 13:58:50 -07:00
Eddie Hung 3a87dc3524 Wrap A and B in sigmap 2019-07-19 13:23:07 -07:00
Eddie Hung 31b0002e8c Remove "top" from message 2019-07-19 13:20:45 -07:00
Eddie Hung bcd8027182 Also optimise MSB of $sub 2019-07-19 13:11:48 -07:00