Alberto Gonzalez
b94f38295a
Revert to `stringf()` rather than stringstreams.
2020-04-16 18:56:50 +00:00
Alberto Gonzalez
6081c1bbd3
Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
2020-04-16 18:56:50 +00:00
Eddie Hung
8d3f6d0d79
Merge pull request #1928 from YosysHQ/eddie/design_delete
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kernel: add design -delete option
2020-04-16 10:51:09 -07:00
whitequark
c2804a68c2
Merge pull request #1896 from boqwxp/read_stdin_repl
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Frontend: allow reading file input from stdin, like a REPL heredoc mode
2020-04-16 17:18:29 +00:00
Claire Wolf
7a434cdd7b
Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo
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Keep file information when emitting firrtl
2020-04-16 18:50:43 +02:00
David Shah
1664bcda12
ecp5: Force SIGNED ports to be 1 bit
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 16:38:19 +01:00
Eddie Hung
aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
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kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-16 08:06:12 -07:00
Eddie Hung
e8a841467f
tests: add design -delete tests
2020-04-16 08:05:18 -07:00
Eddie Hung
a9ec0defb9
kernel: add design -delete option
2020-04-16 08:05:18 -07:00
whitequark
90a1c6b6a4
Merge pull request #1915 from boqwxp/dict_move_semantics
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kernel: Add `dict` support for rvalue references and C++11 move semantics.
2020-04-16 13:29:13 +00:00
whitequark
2ee028dcf1
Merge pull request #1900 from Xiretza/suppress-makefile-echo
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Suppress output of Makefile.conf when printing source versions
2020-04-16 13:28:34 +00:00
whitequark
e1f5145afa
Merge pull request #1937 from hzeller/consexpr-opportunity
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Use static constexpr instead of static const where possible.
2020-04-16 13:28:03 +00:00
David Shah
2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919
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ast: Fix handling of identifiers in the global scope
2020-04-16 13:48:20 +01:00
Marcelina Kościelnicka
2f8541a92e
opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
2020-04-16 11:48:29 +02:00
David Shah
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
Alberto Gonzalez
5eb1f83d2d
Rename overloaded `insert()` to `emplace()` and add overloaded versions for all possible lvalue/rvalue combinationsfor its arguments.
2020-04-16 03:54:33 +00:00
Alberto Gonzalez
76c9e1c265
Use script-style heredoc syntax for REPL heredocs.
2020-04-15 16:15:51 +00:00
Alberto Gonzalez
b5ecbbef94
Allow reading file input from stdin, improving REPL experience.
2020-04-15 16:15:50 +00:00
Miodrag Milanović
3c4758c60e
Merge pull request #1894 from YosysHQ/mingw_fix
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Fix compile for mingw
2020-04-15 17:43:31 +02:00
Eddie Hung
dc3d432aaa
Merge pull request #1916 from YosysHQ/eddie/kernel_makeblackbox
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kernel: Module::makeblackbox() to clear connections too
2020-04-15 08:42:39 -07:00
Eddie Hung
33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more
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zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-15 08:36:25 -07:00
N. Engelhardt
0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
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Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
Marcelina Kościelnicka
53ba3cf718
Fix the truth table for $_SR_* cells.
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This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.
Also get rid of sim-synth mismatch in the models while we're at it.
2020-04-15 17:17:48 +02:00
David Shah
7ad8b24280
Merge pull request #1897 from YosysHQ/dave/bram-rejection-fix
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memory_bram: Fix ignorance of valid, matched rules
2020-04-15 16:10:38 +01:00
Miodrag Milanovic
bc21e58bb5
Fix compile for mingw
2020-04-15 16:38:09 +02:00
Marcelina Kościelnicka
38a0c30d65
Get rid of dffsr2dff.
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This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Marcelina Kościelnicka
85166633bc
opt_clean: Add missing assignments to opt.did_something.
2020-04-15 16:20:56 +02:00
whitequark
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
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ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
Dan Ravensloft
43cc6bd8a1
synth_intel_alm: VQM support
2020-04-15 16:15:25 +02:00
whitequark
2106f78bb1
ast/simplify: improve enum handling.
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Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
Marcelina Kościelnicka
d7da491002
setundef: Improve error messages.
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Fixes #1092 .
2020-04-15 16:13:28 +02:00
Marcelina Kościelnicka
3611e7c864
json: Update format documentation.
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Fixes #1693 .
2020-04-15 16:12:14 +02:00
Claire Wolf
4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876
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Fix handling of ternary with constant condition
2020-04-15 16:01:19 +02:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
Marcelina Kościelnicka
4c52691a58
abc9_ops: Add a check ensuring that connected port actually exists.
2020-04-15 08:11:15 +02:00
whitequark
a143f04e7d
Merge pull request #1932 from YosysHQ/dave/cxxrtl-unclocked-read
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cxxrtl: Fix handling of unclocked memory read ports
2020-04-15 05:34:29 +00:00
Henner Zeller
5c6e681673
Use static constexpr instead of static const where possible.
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In particular inside class declarations, a static const
assignment is technically not a definition, while constexpr is.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2020-04-14 14:19:38 -07:00
Eddie Hung
383fe4a4bc
tests: zinit for new types
2020-04-14 13:08:37 -07:00
Eddie Hung
a8ab74285b
zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-14 13:08:23 -07:00
Marcelina Kościelnicka
6c16fd760b
opt_expr: Add more $alu optimizations.
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Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.
Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).
Fixes #1912 .
2020-04-14 21:48:13 +02:00
David Shah
3b85b7c57a
cxxrtl: Fix handling of unclocked memory read ports
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-14 20:39:13 +01:00
Eddie Hung
e7121cc15c
tests: add testcases from #1876
2020-04-14 12:39:10 -07:00
Claire Wolf
9b4dab397e
Fix 5bba9c3
, closes #1876
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
Marcelina Kościelnicka
7a36728b2f
dffinit: Avoid setting init parameter to zero-length value.
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Fixes #1704 .
2020-04-14 19:52:19 +02:00
Eddie Hung
75bb2c8c24
design: do not delete when iterating over Design::modules() directly
2020-04-14 10:43:05 -07:00
Eddie Hung
635b2b8939
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-14 09:31:06 -07:00
Eddie Hung
3a27906ac6
abc9_exe: verify -> &verify -s
2020-04-14 08:21:26 -07:00
Eddie Hung
843201ec96
techmap: fix error message
2020-04-14 08:17:02 -07:00
whitequark
d8f2a1fda0
Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs
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write_cxxrtl: ignore disconnected module ports
2020-04-14 14:37:48 +00:00
whitequark
7025881a5e
Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilation
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write_cxxrtl: enable separate compilation
2020-04-14 13:53:52 +00:00