riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,346 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

1891 Commits

Author SHA1 Message Date
George Rennie 8206951f77 proc_dff: add tests 2024-08-28 16:24:47 +01:00
Emily Schmidt 761eff594f functional backend: missing includes for stl containers 2024-08-22 11:13:58 +01:00
Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Emily Schmidt 831da51255 add picorv test to functional backend 2024-08-21 11:04:11 +01:00
Emily Schmidt 99effb6789 add support for initializing registers and memories to the functional backend 2024-08-21 11:03:29 +01:00
Emily Schmidt 145af6f10d fix memory handling in functional backend, add more error messages and comments for memory edgecases 2024-08-21 11:03:29 +01:00
Emily Schmidt 3cd5f4ed83 add support for RTLIL cells with multiple outputs to the functional backend, implement $fa,$lcu,$alu 2024-08-21 11:03:29 +01:00
Emily Schmidt c0c90c2c31 functional backend: require shift width == clog2(operand width) 2024-08-21 11:03:29 +01:00
Emily Schmidt 6922633b0b fix a few bugs in the functional backend and refactor the testing 2024-08-21 11:03:29 +01:00
Emily Schmidt 674e6d201d rewrite functional backend test code in python 2024-08-21 11:03:29 +01:00
Roland Coeurjoly 80582ed3af Check the existance of a different set of outputs. No need for (push 1) nor (pop 1) 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 7cff8fa3a3 Fix corner case of pos cell with input and output being same width 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 5780357cd9 Emit valid SMT for stateful designs, fix some cells 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 50f487e08c Added $ff test 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 762f8dd822 Add readme explaining how to create test files 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 73ed514623 Check that there are not other solutions other than the first given 2024-08-21 11:02:31 +01:00
Roland Coeurjoly cb5f08364c ´SMT success only if simulation is equivalent 2024-08-21 11:02:31 +01:00
Roland Coeurjoly e235fc704d Create std::mt19937 only once 2024-08-21 11:02:31 +01:00
Emily Schmidt 21bb1cf1bc rewrite functional c++ simulation library 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 39bf4f04f7 Create VCD file from SMT file 2024-08-21 11:02:31 +01:00
Roland Coeurjoly b98210d8ac Valid SMT is emitted, improved test script 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 71aaa1c80d Consolidate tests scripts into one 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 547c5466ec Ignore smt2 files, generated by the execution of the tests 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 54225b5c42 Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim 2024-08-21 11:02:31 +01:00
Roland Coeurjoly 720429b1fd Add test_cell tests for C++ functional backend 2024-08-21 11:01:09 +01:00
Emil J e0d3bbf3c3
Merge pull request #4452 from phsauter/shiftadd-underflow-fix 
peepopt: avoid shift-amount underflow
 2024-08-19 15:45:46 +02:00
Miodrag Milanovic 54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3848563600 Update tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 34f08bc639 Enable nanoxplore tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 65d2ebac9d fix test 2024-08-15 17:50:36 +02:00
Lofty b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Lofty b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b4a17cccc3 add few more tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 93543bd874 add lut tests 2024-08-15 17:50:36 +02:00
Martin Povišer c35f5e379c Extend liberty tests 2024-08-13 18:47:36 +02:00
George Rennie b6ceff2aab peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
N. Engelhardt 9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
Emil J. Tywoniak 01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
chunlin min 3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
Tony Min d41688f7d7
Revisions (#4) 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
 2024-07-08 10:57:16 -04:00
Tony Min 6fe0e00050
Add missing u sram init (#3) 
add missing INIT for uSRAM
 2024-07-04 16:39:10 -04:00
chunlin min 8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
phsauter 34b5c6d062 peepopt: avoid shift-amount underflow 2024-06-13 23:30:07 +02:00
Marian Buschsieweke 7f89a45ad7 cxxxrtl: fix use of format specifiers in test 
This fix a few instances of incorrect (and non-portable) use of format
specifiers.
 2024-06-11 07:22:39 +01:00
Asherah Connor dc69365258 cxxrtl: failing test: unconnected blackbox outputs don't compile. 2024-06-07 14:24:27 +03:00
Martin Povišer 4b67f3757f
Merge pull request #4404 from YosysHQ/povik/bbox_derive 
box_derive: New command to derive modules for boxes
 2024-05-31 19:09:18 +02:00
Martin Povišer 97fedff383 box_derive: Tune the test 2024-05-29 20:42:11 +02:00
Martin Povišer bff2443af8 box_derive: Finish the test 2024-05-21 16:34:49 +02:00
Martin Povišer c0a196173a Rename `bbox_derive` to `box_derive` 2024-05-21 16:18:03 +02:00
N. Engelhardt 24f9329c67
Merge pull request #4367 from YosysHQ/lofty/intel_alm-drop-quartus 
intel_alm: drop quartus support
 2024-05-21 16:01:23 +02:00
Martin Povišer 557db4ea46 bbox_drive: Add an incomplete test 2024-05-21 14:57:49 +02:00
Martin Povišer b143e5678f cellmatch: Rename the special design to `$cellmatch` 2024-05-03 16:42:41 +02:00
Martin Povišer 913bc87c44 cellmatch: Add test 2024-05-03 16:42:41 +02:00
Emil J. Tywoniak a833f05036 techmap: add dynamic cell type test 2024-05-03 13:53:49 +02:00
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
N. Engelhardt e8ec19c273 add command that should not have any effect to hierarchy -generate test (this documents the current behavior, not sure if it is desired functionality) 2024-04-12 13:51:06 +02:00
N. Engelhardt b87327d1b9 fix hierarchy -generate mode handling of cells 2024-04-12 13:38:33 +02:00
Miodrag Milanovic 0c7ac36dcf Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
Martin Povišer dc746080f5
Merge pull request #4298 from povik/kogge-stone 
techmap: Add a Kogge-Stone option for `$lcu` mapping
 2024-04-08 16:46:06 +02:00
N. Engelhardt 8e8885e1cc
Merge pull request #4323 from YosysHQ/tests_update 
Tests update for latest more strict iverilog
 2024-04-08 15:10:59 +02:00
Miodrag Milanovic 4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Miodrag Milanovic 91e41d8c80 Move parameters to module declaration 2024-04-08 12:44:37 +02:00
Catherine d9a4a42389 write_verilog: don't `assign` to a `reg`. 
Fixes #2035.
 2024-04-03 13:06:45 +02:00
Merry d07a55a852 cxxrtl: Fix sdivmod 
x = x.neg(); results in the subsequent x.is_neg() always being false.
Ditto for the dividend.is_neg() != divisor.is_neg() test.
 2024-03-30 07:56:11 +00:00
Martin Povišer c49d6e7874 techmap: Add Kogge-Stone test 2024-03-27 11:08:26 +01:00
Martin Povišer 5924d97381 tests: Remove part of test involving combinational loops 2024-03-11 10:45:36 +01:00
Martin Povišer 87e72ef86f celledges: Add read ports arst paths 2024-03-11 10:45:17 +01:00
Martin Povišer e4296072c4 check: Rephrase regex for portability 2024-03-11 10:45:17 +01:00
Martin Povišer e1e77a7fa9 check: Extend testing 2024-03-11 10:45:17 +01:00
Martin Povišer 3eef6450f1 check: Add coarse-grain false positive test 2024-03-11 10:43:49 +01:00
N. Engelhardt d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops 
celledges: support shift ops
 2024-03-08 09:35:47 +01:00
Jannis Harder 0db76c6ec4 tests/sva: Skip sva tests that use SBY until SBY is compatible again 
This commit is part of a PR that requires corresponding changes in SBY.
To prevent CI failures, detect whether those changes already landed and
skip the SBY using tests until then.
 2024-03-05 14:37:33 +01:00
Roland Coeurjoly 4a2fb18718 Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc 2024-02-25 17:23:56 +01:00
Miodrag Milanović bc8a3a5b18
Merge pull request #4219 from rovinski/master 
dfflibmap: Add a -dont_use flag to ignore cells
 2024-02-20 12:43:44 +01:00
Austin Rovinski 689feed012 dfflibmap: Add a -dont_use flag to ignore cells 
This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
 2024-02-19 13:00:18 -05:00
Martin Povišer db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch 
proc_rom: don't assert on big actionless switch.
 2024-02-19 16:21:40 +01:00
N. Engelhardt edd154e3cd
Merge pull request #4215 from povik/xprop-race 
Address race in `xprop` tests
 2024-02-19 16:16:16 +01:00
Amelia Cuss bf4a46ccb3 proc_rom: don't assert on big actionless switch. 
See the test case.  PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.
 2024-02-18 01:33:28 +11:00
Jannis Harder 811b7b54d4
Merge pull request #4204 from YosysHQ/micko/gen_test 
do not override existing shell variable
 2024-02-16 14:28:56 +01:00
Martin Povišer e51c77484a tests: Comment on `A[0]` 2024-02-16 11:43:28 +01:00
Martin Povišer 5a05344d9c tests: Fix initialization race in xprop tests 2024-02-16 11:43:28 +01:00
Jannis Harder bbdfcfdf30 clk2fflogic: Fix handling of $check cells 
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.

Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
 2024-02-14 11:42:27 +01:00
Miodrag Milanovic 353ccc9e58 do not override existing shell variable 2024-02-12 12:58:13 +01:00
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo 
$scopeinfo support
 2024-02-12 09:51:22 +01:00
Miodrag Milanovic 10297127be fix test for verific 2024-02-12 09:19:58 +01:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem a4ae773150 Added test for multidimensional packed arrays 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem a32d9b6c45 Fix test of memory vs. memory converted to registers 
The purpose of memtest02 in tests/simple/memory.v is to	test bit
select on both memory (mem1) and memory converted to registers (mem2).

After 7cfae2c52, mem1 was automatically converted to registers,
and the test no longer worked as intended. This is fixed by
adding (* nomem2reg *) to mem1.
 2024-02-11 11:26:52 -05:00