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Added $ff test

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Roland Coeurjoly 2024-07-04 16:04:21 +02:00 committed by Emily Schmidt
parent 762f8dd822
commit 50f487e08c
1 changed files with 83 additions and 0 deletions
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tests/functional/single_cells/rtlil/ff.il Normal file
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# Generated by Yosys 0.40+7 (git sha1 4fd5b29f9, g++ 13.2.0 -Og -fPIC)
autoidx 19
attribute \cells_not_processed 1
attribute \src "dff.v:1.1-16.10"
module \gold
attribute \src "dff.v:8.5-14.8"
wire $0\q[0:0]
attribute \init 1'0
wire $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
attribute \init 1'1
wire $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
attribute \init 1'0
wire $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
attribute \init 1'x
wire $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
wire $auto$rtlil.cc:2525:Eqx$10
wire $auto$rtlil.cc:2582:Mux$12
wire $auto$rtlil.cc:2582:Mux$16
wire $auto$rtlil.cc:2582:Mux$18
attribute \src "dff.v:2.16-2.19"
wire input 1 \clk
attribute \src "dff.v:4.16-4.17"
wire input 3 \d
attribute \keep 1
attribute \src "dff.v:5.16-5.17"
wire output 4 \q
attribute \src "dff.v:3.16-3.21"
wire input 2 \reset
cell $mux $auto$clk2fflogic.cc:113:mux$11
parameter \WIDTH 1
connect \A $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
connect \B $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
connect \S $auto$rtlil.cc:2525:Eqx$10
connect \Y $auto$rtlil.cc:2582:Mux$12
end
cell $mux $auto$clk2fflogic.cc:113:mux$15
parameter \WIDTH 1
connect \A $auto$rtlil.cc:2582:Mux$12
connect \B 1'0
connect \S $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
connect \Y $auto$rtlil.cc:2582:Mux$16
end
cell $mux $auto$clk2fflogic.cc:113:mux$17
parameter \WIDTH 1
connect \A $auto$rtlil.cc:2582:Mux$16
connect \B 1'0
connect \S \reset
connect \Y $auto$rtlil.cc:2582:Mux$18
end
cell $ff $auto$clk2fflogic.cc:70:sample_control$14
parameter \WIDTH 1
connect \D \reset
connect \Q $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13
end
cell $ff $auto$clk2fflogic.cc:82:sample_control_edge$8
parameter \WIDTH 1
connect \D \clk
connect \Q $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7
end
cell $eqx $auto$clk2fflogic.cc:83:sample_control_edge$9
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A { $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 \clk }
connect \B 2'01
connect \Y $auto$rtlil.cc:2525:Eqx$10
end
attribute \clk2fflogic 1
cell $ff $auto$clk2fflogic.cc:98:sample_data$4
parameter \WIDTH 1
connect \D \q
connect \Q $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3
end
cell $ff $auto$clk2fflogic.cc:98:sample_data$6
parameter \WIDTH 1
connect \D \d
connect \Q $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5
end
connect $0\q[0:0] \d
connect \q $auto$rtlil.cc:2582:Mux$18
end