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2841 Commits

Author SHA1 Message Date
David Shah 5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 1055b6b1dd
Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 
synth_xilinx: add -dsp-multonly
 2020-02-02 14:53:32 +00:00
David Shah 65716c9982 xilinx_dsp: Add multonly scratchpad var to bypass 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-01 15:30:43 +00:00
Gabriel Somlo 8106c3d31b abc9: restore ability to use ABCEXTERNAL 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-01-30 15:12:43 -05:00
Claire Wolf 1679682fa3 Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys 
Also some minor fixes to the original PR.
 2020-01-29 17:01:24 +01:00
Claire Wolf 4d0118d0c1
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check 
opt_reduce: Call check() per run rather than per optimised cell
 2020-01-29 15:27:11 +01:00
Eddie Hung 7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Claire Wolf 4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt 086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
David Shah 6fd9cae5ca opt_reduce: Call check() per run rather than per optimised cell 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-28 09:42:01 +00:00
Pepijn de Vos 409e532433 redirect fuser stderr to /dev/null 2020-01-28 10:02:41 +01:00
Eddie Hung e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung 48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung 9009b76a69 abc9_ops: add comments 2020-01-27 11:18:21 -08:00
Eddie Hung b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung dbf351390e abc9: -reintegrate recover type from existing cell, check against boxid 2020-01-23 22:45:34 -08:00
Eddie Hung 245873d42d abc9: warning message if no modules selected 2020-01-23 19:08:51 -08:00
Eddie Hung f180dba753 abc9_ops: -prep_xaiger to skip (* keep *) cells 2020-01-23 18:56:06 -08:00
Eddie Hung 1d4314d888 abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_* 2020-01-23 14:58:56 -08:00
Eddie Hung af0e7637a2 alumacc: undo accidental commit 2020-01-22 20:54:03 -08:00
Eddie Hung 8eb5bb258c Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor 2020-01-22 12:30:14 -08:00
Eddie Hung a94b41011d abc9: error out if flip-flop init is 1'b1 for '-dff' 
Due to ABC sequential synthesis restriction
 2020-01-22 10:08:48 -08:00
Eddie Hung 3b44b53e94 abc9: fix scratchpad entry abc9.verify 2020-01-22 09:36:54 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Claire Wolf 5791c52e1b
Merge pull request #1637 from YosysHQ/mwk/fix-1634 
fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.
 2020-01-21 18:37:06 +01:00
Claire Wolf f165a74824
Merge pull request #1621 from YosysHQ/clifford/fminit 
Add fminit pass
 2020-01-20 22:01:57 +01:00
Eddie Hung 6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung db68e4c2a7 ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
Eddie Hung e17f3f8c63 Consistency 2020-01-17 16:06:20 -08:00
Eddie Hung ee500b6d8e xilinx_dsp: add parameter defaults 2020-01-17 16:05:10 -08:00
Eddie Hung 4985318263 ice40_dsp: add default values for parameters 2020-01-17 15:37:52 -08:00
Eddie Hung 6692e5d558 ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputs 2020-01-17 15:28:02 -08:00
Eddie Hung d4e188299b abc9: add some log_{push,pop}() as per @nakengelhardt 2020-01-17 12:00:14 -08:00
Eddie Hung 4656f202c6 abc9_ops: -reintegrate to not trim box padding anymore 2020-01-14 14:27:29 -08:00
Marcin Kościelnicki a5d2358a60 fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks. 
Fixes #1634.
 2020-01-14 22:49:20 +01:00
Eddie Hung 654247abe9 abc9_ops/write_xaiger: update doc 2020-01-14 12:40:36 -08:00
Eddie Hung 468386d67d abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger 2020-01-14 12:25:45 -08:00
Eddie Hung 53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung 61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname 
autoname: do not rename ports
 2020-01-14 11:40:54 -08:00
Eddie Hung de969adcd8 autoname: do not autoname ports 2020-01-14 10:13:29 -08:00
Eddie Hung 531fddf797 abc9_ops: -break_scc -> -mark_scc using (* keep *), remove -unbreak_scc 2020-01-13 23:42:27 -08:00
Eddie Hung b678b15c6d abc9_ops: ignore inouts of all cell outputs for topo ordering 2020-01-13 23:33:37 -08:00
Eddie Hung 2c65e1abac abc9: break SCC by setting (* keep *) on output wires 2020-01-13 21:45:27 -08:00
Eddie Hung a2c4d98da7 abc9: add -run option 2020-01-13 19:22:23 -08:00
Eddie Hung a6d4ea7463 abc9: respect (* keep *) on cells 2020-01-13 19:21:11 -08:00
Eddie Hung 766e16b525 read_aiger: make $and/$not/$lut the prefix not suffix 2020-01-13 17:34:37 -08:00
Eddie Hung 808b388e34 abc9: log which module is being operated on 2020-01-13 09:43:57 -08:00
Eddie Hung 9f3cb981d7 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-13 09:22:42 -08:00
Eddie Hung 295e241c07 cleanup 2020-01-11 17:28:24 -08:00
Eddie Hung 79db12f238 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-11 17:26:25 -08:00