9ee3c57e46
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
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Fix #1496 .
2019-11-18 10:53:14 +01:00
cdb566b2d6
Merge pull request #1494 from whitequark/write_verilog-extmem
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write_verilog: add -extmem option, to write split memory init files
2019-11-18 09:37:14 +00:00
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
3c643c57df
write_verilog: add -extmem option, to write split memory init files.
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Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
2019-11-18 01:27:21 +00:00
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
2019-11-17 10:42:30 +01:00
51e4e29bb1
ecp5: Use new autoname pass for better cell/net names
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-15 21:03:11 +00:00
f5804a84fd
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-14 18:43:15 +00:00
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname
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Add "autoname" pass and use it in "synth_ice40"
2019-11-14 18:03:44 +01:00
4b18a4528b
Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams
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Python Wrappers: Expose global variables and allow logging to python streams
2019-11-14 12:10:12 +01:00
056ef76711
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
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ice40: Support for post-place-and-route timing simulations
2019-11-14 12:07:25 +01:00
f453f579bf
Merge branch 'makaimann-label-bads-btor'
2019-11-14 11:57:53 +01:00
cd44826d50
Use cell name for btor bad state props when it is a public name
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-14 11:57:38 +01:00
89834b98f7
Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor
2019-11-14 11:52:41 +01:00
07c854b7af
Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-13 13:41:16 +01:00
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes
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flowmap: fix a few crashes
2019-11-13 11:57:17 +00:00
6e332161db
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
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Bugfix in fsm_detect
2019-11-13 12:34:27 +01:00
4be5a0fd7c
Update fsm_detect bugfix
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 17:31:30 +01:00
16df8f5a32
Bugfix in fsm_detect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 14:26:02 +01:00
e0ba78bdf2
Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne
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Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
2019-11-12 10:24:12 +01:00
d88cc139a0
Add an info string symbol for bad states in btor backend
2019-11-11 16:40:51 -08:00
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
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Fixes #1475 .
2019-11-12 00:15:43 +00:00
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
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Fixes #1405 .
2019-11-11 23:13:00 +00:00
3e0ffe05a7
Fixed tests
2019-11-11 15:41:33 +01:00
362f4f996d
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-11 15:07:29 +01:00
1d148491c5
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
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Add CodingReadme section on script passes
2019-11-10 11:00:38 +01:00
65f197e28f
Add check for valid macro names in macro definitions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-07 13:30:03 +01:00
c4bd318e76
synth_xilinx: Merge blackbox primitive libraries.
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
5110a34dd7
Fix write_aiger bug added in 524af21
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-04 14:25:13 +01:00
c3ad375200
Add CodingReadme section on script passes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-31 10:46:20 +01:00
81876a3734
Merge pull request #1393 from whitequark/write_verilog-avoid-init
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write_verilog: do not print (*init*) attributes on regs
2019-10-27 10:25:01 +01:00
84982b3083
Improve naming scheme for (VHDL) modules imported from Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
34dadd9ab2
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
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Add BRAM and URAM mapping for UltraScale[+]
2019-10-24 08:14:20 +01:00
d49c6b2cba
Add "verific -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 09:14:03 +02:00
e135ed5d80
ice40: Add post-pnr ICESTORM_RAM model and fix FFs
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 18:44:34 +01:00
37dd3ad3fe
ice40: Support for post-pnr timing simulation
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 12:03:31 +01:00
3506eaf290
xilinx: Add URAM288 mapping for xcup
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:44 +01:00
6769d31ddb
xilinx: Add support for UltraScale[+] BRAM mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
f02623abb5
Bugfix in smtio vcd handling of $-identifiers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-23 00:04:34 +02:00
7b350cacd4
xilinx: Support multiplier mapping for all families.
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This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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Call memory_dff before DSP mapping to reserve registers (fixes #1447 )
2019-10-22 17:36:54 +02:00
5025aab8c9
Add "verilog_defines -list" and "verilog_defines -reset"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 13:35:56 +02:00
4033ff8c2e
Fix handling of "restrict" in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 12:39:28 +02:00
fa989e59e5
ecp5: Pass -nomfs to abc9
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Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
2019-10-20 10:30:41 +01:00
f2aa2d1bb4
Merge pull request #1457 from xobs/python-binary-name
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Makefile: don't assume python is called `python3`
2019-10-19 08:58:02 +02:00
82f60ba938
Makefile: don't assume python is called `python3`
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On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
e8ef3fcdfc
Merge pull request #1454 from YosysHQ/mmicko/common_tests
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Share common tests
2019-10-18 14:29:44 +02:00
190b40341a
fixed error
2019-10-18 13:15:36 +02:00
9bd9db56c8
Unify verilog style
2019-10-18 12:50:24 +02:00
12383f37b2
Common memory test now shared
2019-10-18 12:33:35 +02:00
477702b8c9
Remove not needed tests
2019-10-18 12:20:35 +02:00
Clifford Wolf
whitequark
Marcin Kościelnicki
David Shah
Makai Mann
Miodrag Milanovic
Marcin Kościelnicki
Sean Cross