riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
959 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

959 Commits

Author SHA1 Message Date
Clifford Wolf 672229eda5 Added yosys -H for command list 2014-01-30 12:32:59 +01:00
Clifford Wolf 34b39ec28a presentation progress 2014-01-29 15:56:58 +01:00
Clifford Wolf cbe77bf844 presentation progress 2014-01-29 12:15:38 +01:00
Clifford Wolf aceab5fc08 Tiny change in example script in README 2014-01-29 11:11:10 +01:00
Clifford Wolf 96084e9864 Added -h command line option 2014-01-29 11:10:39 +01:00
Clifford Wolf 6a7d7e847d Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
Clifford Wolf c46b23ab23 Updated ABC to hg rev e6b09e1 2014-01-29 10:50:15 +01:00
Clifford Wolf 375c4dddc1 Added read_verilog -icells option 2014-01-29 00:59:28 +01:00
Clifford Wolf a86f33653d Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal) 2014-01-29 00:36:03 +01:00
Clifford Wolf 961b791272 presentation progress 2014-01-28 20:28:22 +01:00
Clifford Wolf 2cb47355d4 Renamed manual/FILES_* directories 2014-01-28 06:55:47 +01:00
Clifford Wolf 842ca2f011 Progress on presentation 2014-01-28 06:51:50 +01:00
Clifford Wolf a3ac6b6f47 Progress on presentation 2014-01-27 20:42:35 +01:00
Clifford Wolf fb4c3dff33 Added first presentation slides 2014-01-27 17:08:19 +01:00
Clifford Wolf fa103e55ad Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys 2014-01-26 02:29:19 +01:00
Clifford Wolf fd6ca84f3c Merge pull request #21 from hansiglaser/master 
beautified write_intersynth, enabled multiple "-map" for the extract pass
 2014-01-25 17:28:17 -08:00
Johann Glaser e9a2094774 enabled multiple "-map" for the extract pass 2014-01-25 21:11:34 +01:00
Johann Glaser f13b3518aa beautified write_intersynth 2014-01-25 20:16:38 +01:00
Ahmed Irfan 0325efe172 root bug corrected 2014-01-25 19:33:24 +01:00
Clifford Wolf c1ed2607fb Added support for // comments in liberty parser 2014-01-25 06:32:16 +01:00
Clifford Wolf a139b49401 Merge branch 'btor' 2014-01-24 23:44:46 +01:00
Ahmed Irfan 137742786e removed regex include 2014-01-24 18:04:37 +01:00
Ahmed Irfan 2e44b1b73a merged clifford changes + removed regex 2014-01-24 17:35:42 +01:00
Clifford Wolf 210dda286f Use techmap -share_map in btor scripts 2014-01-24 15:52:16 +01:00
Clifford Wolf 6804edd5d4 Moved btor scripts to backends/btor/ 2014-01-24 15:48:07 +01:00
Clifford Wolf da26bb4378 Restored Makefile 2014-01-24 15:47:09 +01:00
Clifford Wolf ec167350b4 Restored IdString::check() 2014-01-24 15:46:41 +01:00
Clifford Wolf d8300d1fb8 Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-24 15:43:42 +01:00
Clifford Wolf 0b47d907d3 Fixed handling of unsized constants in verilog frontend 2014-01-24 15:05:24 +01:00
Ahmed Irfan 761b8f99d7 minor change in script 2014-01-24 15:00:43 +01:00
Ahmed Irfan 9d07d83c5a Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-22 10:45:21 +01:00
Clifford Wolf 88fbdd4916 Fixed algorithmic complexity of AST simplification of long expressions 2014-01-20 20:25:20 +01:00
Ahmed Irfan aa3cb20e1e slice bug corrected 2014-01-20 18:35:52 +01:00
Ahmed Irfan c347f2825f assert feature 2014-01-20 10:45:02 +01:00
Ahmed Irfan b7adf4c7a0 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-20 09:58:04 +01:00
Clifford Wolf 32a91458a7 Added hilomap command 2014-01-19 21:58:58 +01:00
Clifford Wolf 03a876c7e8 Added sat -tempinduc and sat -prove-asserts 2014-01-19 16:35:17 +01:00
Clifford Wolf c36bac0e10 Added $assert support to satgen 2014-01-19 15:37:56 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 9a1eb45c75 Added Verilog parser support for asserts 2014-01-19 04:18:22 +01:00
Ahmed Irfan 234d0d0e1c script added 2014-01-18 21:54:52 +01:00
Ahmed Irfan 90483f489b Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-18 19:45:16 +01:00
Clifford Wolf 3d7a1491aa Fixed $lut simlib model for a wider range of tools 2014-01-18 19:31:40 +01:00
Clifford Wolf 13359d65ba Fixed parsing of verilog macros at end of line 2014-01-18 19:22:20 +01:00
Clifford Wolf 2fbaaaca7a More changes to simlib to make it friendlier to a wider range of tools 2014-01-18 19:13:43 +01:00
Clifford Wolf 4a9e133fab Fixed a type in $mem model in simlib.v 2014-01-18 18:54:50 +01:00
Ahmed Irfan b281e13263 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys 2014-01-18 18:11:26 +01:00
Ahmed Irfan 1dd797ab09 Merge branch 'master' of https://github.com/cliffordwolf/yosys 2014-01-18 18:10:31 +01:00
Ahmed Irfan da8af91552 pmux2mux 2014-01-18 17:29:55 +01:00
Clifford Wolf bef17eeb10 Removed cases of trailing comma in stdcells.v 2014-01-18 15:36:17 +01:00