mirror of https://github.com/YosysHQ/yosys.git
script added
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11
btor.ys
11
btor.ys
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@ -1,10 +1,3 @@
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#design should be loaded before executing
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#set the: hierarchy -top <module_top>
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#set the: hierarchy -libdir <dir>
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#high level synthesis
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#################
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#converting processes to cells
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proc;
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opt; opt_const -mux_undef; opt;
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rename -hide;;;
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@ -17,6 +10,6 @@ flatten;;
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memory_unpack;
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#cell output to be a single wire
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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#writing btor
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write_btor design.btor;
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@ -0,0 +1,26 @@
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#!/bin/sh
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#
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# Script to writing btor from verilog design
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#
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if [ "$#" -ne 3 ]; then
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echo "Usage: $0 input.v output.btor top-module-name" >&2
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exit 1
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fi
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if ! [ -e "$1" ]; then
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echo "$1 not found" >&2
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exit 1
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fi
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FULL_PATH=$(readlink -f $1)
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DIR=$(dirname $FULL_PATH)
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./yosys -p "
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read_verilog $1;
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hierarchy -top $3;
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hierarchy -libdir $DIR;
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hierarchy -check;
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script btor.ys;
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write_btor $2;"
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