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pmux2mux

This commit is contained in:
Ahmed Irfan 2014-01-18 17:29:55 +01:00
parent 9a689f33a5 bef17eeb10
commit da8af91552
7 changed files with 197 additions and 9 deletions
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7
kernel/log.h
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@ -95,11 +95,16 @@ struct PerformanceTimer
// simple API for quickly dumping values when debugging
static inline void log_dump_val_worker(short v) { log("%d", v); }
static inline void log_dump_val_worker(unsigned short v) { log("%u", v); }
static inline void log_dump_val_worker(int v) { log("%d", v); }
static inline void log_dump_val_worker(size_t v) { log("%zd", v); }
static inline void log_dump_val_worker(unsigned int v) { log("%u", v); }
static inline void log_dump_val_worker(long int v) { log("%ld", v); }
static inline void log_dump_val_worker(unsigned long int v) { log("%lu", v); }
static inline void log_dump_val_worker(long long int v) { log("%lld", v); }
static inline void log_dump_val_worker(unsigned long long int v) { log("%lld", v); }
static inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); }
static inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); }
static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false"); }
static inline void log_dump_val_worker(double v) { log("%f", v); }
static inline void log_dump_val_worker(const char *v) { log("%s", v); }

1
passes/cmds/Makefile.inc
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@ -6,6 +6,7 @@ OBJS += passes/cmds/show.o
OBJS += passes/cmds/rename.o
OBJS += passes/cmds/connect.o
OBJS += passes/cmds/scatter.o
OBJS += passes/cmds/setundef.o
OBJS += passes/cmds/splitnets.o
OBJS += passes/cmds/stat.o

157
passes/cmds/setundef.cc Normal file
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@ -0,0 +1,157 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/sigtools.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
static int next_bit_mode;
static uint32_t next_bit_state;
static RTLIL::State next_bit()
{
if (next_bit_mode == 0)
return RTLIL::State::S0;
if (next_bit_mode == 1)
return RTLIL::State::S1;
// xorshift32
next_bit_state ^= next_bit_state << 13;
next_bit_state ^= next_bit_state >> 17;
next_bit_state ^= next_bit_state << 5;
log_assert(next_bit_state != 0);
return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
}
struct SetundefWorker
{
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
for (auto &c : sig.chunks)
if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
c.data.bits.at(0) = next_bit();
sig.optimize();
}
};
struct SetundefPass : public Pass {
SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" setundef [options] [selection]\n");
log("\n");
log("This command replaced undef (x) constants with defined (0/1) constants.\n");
log("\n");
log(" -undriven\n");
log(" also set undriven nets to constant values\n");
log("\n");
log(" -zero\n");
log(" replace with bits cleared (0)\n");
log("\n");
log(" -one\n");
log(" replace with bits set (1)\n");
log("\n");
log(" -random <seed>\n");
log(" replace with random bits using the specified integer als seed\n");
log(" value for the random number generator.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
bool got_value = false;
bool undriven_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-undriven") {
undriven_mode = true;
continue;
}
if (args[argidx] == "-zero") {
got_value = true;
next_bit_mode = 0;
continue;
}
if (args[argidx] == "-one") {
got_value = true;
next_bit_mode = 1;
continue;
}
if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
got_value = true;
next_bit_mode = 2;
next_bit_state = atoi(args[++argidx].c_str()) + 1;
for (int i = 0; i < 10; i++)
next_bit();
continue;
}
break;
}
extra_args(args, argidx, design);
if (!got_value)
log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
for (auto &mod_it : design->modules)
{
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))
continue;
if (undriven_mode)
{
if (!module->processes.empty())
log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
SigMap sigmap(module);
SigPool undriven_signals;
for (auto &it : module->wires)
if (!it.second->port_input)
undriven_signals.add(sigmap(it.second));
CellTypes ct(design);
for (auto &it : module->cells)
for (auto &conn : it.second->connections)
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
undriven_signals.del(sigmap(conn.second));
RTLIL::SigSpec sig = undriven_signals.export_all();
for (auto &c : sig.chunks) {
RTLIL::SigSpec bits;
for (int i = 0; i < c.width; i++)
bits.append(next_bit());
bits.optimize();
module->connections.push_back(RTLIL::SigSig(c, bits));
}
}
module->rewrite_sigspecs(SetundefWorker());
}
}
} SetundefPass;

6
techlibs/common/Makefile.inc
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@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
cat techlibs/common/simlib.v techlibs/common/simcells.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v
EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v
share/simlib.v: techlibs/common/simlib.v
mkdir -p share
@ -19,3 +19,7 @@ share/blackbox.v: techlibs/common/blackbox.v
mkdir -p share
cp techlibs/common/blackbox.v share/blackbox.v
share/pmux2mux.v: techlibs/common/pmux2mux.v
mkdir -p share
cp techlibs/common/pmux2mux.v share/pmux2mux.v

7
techlibs/common/pmux2mux.v
View File

@ -13,10 +13,9 @@ output reg [WIDTH-1:0] Y;
integer i;
always @* begin
Y <= A;
for (i = 0; i < S_WIDTH; i=i+1)
if (S[i])
Y <= B[WIDTH*i +: WIDTH];
Y <= A;
for (i = 0; i < S_WIDTH; i=i+1)
if (S[i]) Y <= B[WIDTH*i +: WIDTH];
end
endmodule

22
techlibs/common/simlib.v
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@ -53,6 +53,28 @@ assign Y = ~A_BUF.val;
endmodule
// --------------------------------------------------------
module \$bu0 (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
`INPUT_A
output [Y_WIDTH-1:0] Y;
generate
if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
assign Y[A_WIDTH-1:0] = A_BUF.val;
assign Y[Y_WIDTH-1:A_WIDTH] = 0;
end else begin:B
assign Y = +A_BUF.val;
end
endgenerate
endmodule
// --------------------------------------------------------
module \$pos (A, Y);

6
techlibs/common/stdcells.v
View File

@ -456,7 +456,7 @@ wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
.Cin(1'b1),
.Y(Y_buf),
.Cout(carry),
.Csign(carry_sign),
.Csign(carry_sign)
);
// ALU flags
@ -505,7 +505,7 @@ wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
.Cin(1'b1),
.Y(Y_buf),
.Cout(carry),
.Csign(carry_sign),
.Csign(carry_sign)
);
// ALU flags
@ -849,7 +849,7 @@ assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
.A(A_buf_u),
.B(B_buf_u),
.Y(Y_u),
.R(R_u),
.R(R_u)
);
assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;