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yosys
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4878 Commits

Author SHA1 Message Date
Jim Lawson 34153adef4 Append (instead of over-writing) EXTRA_FLAGS 2019-02-15 11:56:51 -08:00
Jim Lawson 5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00
Jim Lawson fc1c9aa11f Update cells supported for verilog to FIRRTL conversion. 
Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
 2019-02-15 11:14:17 -08:00
Clifford Wolf 807b3c7697 Fix sign handling of real constants 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-13 12:36:47 +01:00
David Shah e0bc190879 ecp5: Add ECLKSYNCB blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-13 11:23:25 +00:00
Eddie Hung c23e3f0751 Missing headers for Xcode? 2019-02-12 09:24:13 -08:00
Eddie Hung 6faad18874 Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger 2019-02-12 09:21:46 -08:00
Eddie Hung a2ae393811 Use module->add{Not,And}Gate() functions 2019-02-12 09:21:15 -08:00
Clifford Wolf 1f2548a564
Merge pull request #802 from whitequark/write_verilog_async_mem_ports 
write_verilog: correctly emit asynchronous transparent ports
 2019-02-12 14:41:34 +01:00
Clifford Wolf b9f6ed40b6
Merge pull request #806 from daveshah1/fsm_opt_no_reset 
fsm_opt: Fix runtime error for FSMs without a reset state
 2019-02-12 14:39:39 +01:00
David Shah 7913baedd8 ecp5: Full set of IO-related blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-12 12:04:41 +00:00
Eddie Hung 04c580fde7 Do not break for constraints 2019-02-11 13:28:00 -08:00
Eddie Hung 727ba52504 No increment line_count for binary ANDs 2019-02-11 13:24:21 -08:00
Eddie Hung bb4164481d Do not ignore newline after AND in binary AIG 2019-02-11 11:51:44 -08:00
Eddie Hung fb6df09dd2 Merge remote-tracking branch 'origin/dff_init' into read_aiger 2019-02-08 14:42:08 -08:00
Eddie Hung 8886fa5506 addDff -> addDffGate as per @daveshah1 2019-02-08 13:17:53 -08:00
Eddie Hung afc3c4b613 Fix tabulation 2019-02-08 13:17:02 -08:00
Eddie Hung aa66d8f12f -module_name arg to go before -clk_name 2019-02-08 12:49:55 -08:00
Eddie Hung 587872236e Support and differentiate between ASCII and binary AIG testing 2019-02-08 12:41:59 -08:00
Eddie Hung 391ec75b07 Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
Eddie Hung fb8ad440a3 Allow module name to be determined by argument too 2019-02-08 12:40:43 -08:00
Eddie Hung f1befe1b44 Refactor into AigerReader class 2019-02-08 12:04:26 -08:00
Eddie Hung 2a8cc36578 Parse binary AIG files 2019-02-08 11:45:16 -08:00
Eddie Hung 4e6c5e4672 Add binary AIGs converted from AAG 2019-02-08 11:41:25 -08:00
Eddie Hung 09d758f0a3 Refactor to parse_aiger_header() 2019-02-08 10:54:31 -08:00
Eddie Hung 36c56bf412 Add comment 2019-02-08 08:37:44 -08:00
Eddie Hung 5e24251a61 Handle reset logic in latches 2019-02-08 08:37:18 -08:00
Eddie Hung 652e414392 Change literal vars from int to unsigned 2019-02-08 08:09:30 -08:00
Eddie Hung fafa972238 Create clk outside of latch loop 2019-02-08 08:08:49 -08:00
Eddie Hung 02f603ac1a Handle latch symbols too 2019-02-08 08:05:27 -08:00
Eddie Hung 5a593ff41c Remove return after log_error 2019-02-08 08:04:48 -08:00
Eddie Hung 6dbeda1807 Add support for symbol tables 2019-02-08 08:03:40 -08:00
Eddie Hung 791f93181d Stub for binary AIGER 2019-02-08 07:31:04 -08:00
David Shah a4515712cb fsm_opt: Fix runtime error for FSMs without a reset state 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-07 10:35:36 +00:00
Eddie Hung e8f4dc739c Cope WIDTH of ff/latch cells is default of zero 2019-02-06 15:51:12 -08:00
Eddie Hung 40db2f2eb6 Refactor 2019-02-06 14:58:47 -08:00
Eddie Hung 20ca795b87 Remove check for cell->name[0] == '$' 2019-02-06 14:53:40 -08:00
Eddie Hung 4167b15de5 Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig 2019-02-06 14:31:11 -08:00
Eddie Hung 3f87cf86cc Revert most of autotest.sh; for non *.v use Yosys to translate 2019-02-06 14:30:19 -08:00
Eddie Hung c373640a3a Refactor 2019-02-06 14:28:44 -08:00
Eddie Hung 8241db6960 write_verilog to cope with init attr on q when -noexpr 2019-02-06 14:17:09 -08:00
Eddie Hung 742b4e01b4 Add INIT parameter to all ff/latch cells 2019-02-06 14:16:26 -08:00
Eddie Hung 115883f467 Add tests for simple cases using defparam 2019-02-06 14:15:17 -08:00
Eddie Hung 281f2aadca Add -B option to autotest.sh to append to backend_opts 2019-02-06 14:14:55 -08:00
Eddie Hung 03cf1532a7 Extend testcase 2019-02-06 14:02:11 -08:00
David Shah 95789c6136 ecp5: Use abc -dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah 58c22dae31 abc: Improved recovered netnames, also preserve src on nets with dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah 7ef2333497 ice40: Use abc -dress in synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah 8524a479b1 abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-06 22:23:13 +01:00
Eddie Hung a9674bd2ec Add testcase 2019-02-06 12:49:30 -08:00