Commit Graph

9677 Commits

Author SHA1 Message Date
Alberto Gonzalez b63b2dbbc3
Clean up pseudo-private member usage in `passes/sat/eval.cc`. 2020-03-28 03:11:23 +00:00
Eddie Hung 348e892314 kernel: pass-by-value into Design::scratchpad_set_string() too 2020-03-27 12:21:09 -07:00
Claire Wolf 1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
Peter Crozier f8c065ed1c Inline productions to follow house style. 2020-03-27 16:21:45 +00:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
Claire Wolf 4c38895fab
Merge pull request #1815 from boqwxp/fix-ef-optimize
Fix solver output parsing for exists-forall optimization
2020-03-27 16:48:38 +01:00
Alberto Gonzalez 6040593994
Revert over-aggressive change to a more modest cleanup. 2020-03-27 09:46:40 +00:00
Eddie Hung 6ca7844cec kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
Alberto Gonzalez d72cb8ea2a
Do not change solver output parsing for non-exists-forall problems. 2020-03-26 23:00:00 +00:00
Eddie Hung d40f12252b kernel: clear some more ShareWorker state 2020-03-26 15:05:45 -07:00
Eddie Hung f97b90e40b kernel: Cell::set{Port,Param}() to pass by value, but use std::move
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
2020-03-26 14:33:06 -07:00
Claire Wolf 590d8eccb7
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
techmap: Fix cell names with _TECHMAP_REPLACE_.*
2020-03-26 19:03:37 +01:00
Alberto Gonzalez 5accf08ef9
Skip reading stdout from the solver that if it isn't a line reading only "sat", "unsat", or "unknown". 2020-03-26 01:21:01 +00:00
Miodrag Milanovic aad92abce9 Enable ENABLE_LIBYOSYS when ENABLE_PYOSYS is set 2020-03-25 10:02:56 +01:00
Sahand Kashani 6c2b220af5 Remove use of auto for simple types + simplify src attribute computation 2020-03-24 21:07:08 +01:00
Claire Wolf c9555c9ade Revert part of 0fda8308 from #1746 that broke other smtbmc flows
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-24 17:33:46 +01:00
Peter Crozier 9a8a644ad1 Error duplicate declarations of a typedef name in the same scope. 2020-03-24 14:35:21 +00:00
Sahand Kashani 018116e478 Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src attribute 2020-03-24 10:55:21 +01:00
Peter Crozier ecc22f7fed Support module/package/interface/block scope for typedef names. 2020-03-23 20:07:22 +00:00
N. Engelhardt 3e46faa58c
Merge pull request #1763 from boqwxp/issue1762
Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
2020-03-23 20:14:13 +01:00
Alberto Gonzalez 0da65d498b
Do not warn on empty selection with prefixed `arg_memb`.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-03-23 17:50:11 +00:00
Alberto Gonzalez ca4e5dd56e
Suppress warnings for empty `select` arguments when `-count` or `-assert-*` options are set. 2020-03-23 17:30:53 +00:00
Alberto Gonzalez 1b333d49ef
Add tests for `select` command warnings. 2020-03-23 17:30:53 +00:00
N. Engelhardt b86905d952
Merge pull request #1803 from Grazfather/typedef
Support standard typedef grammar (Fixed)
2020-03-23 13:43:35 +01:00
N. Engelhardt eb2bf340fb
Merge pull request #1805 from hofstee/master
fix typo in `write_smt2` help
2020-03-23 12:33:05 +01:00
Marcin Kościelnicki c2bf11e42a techmap: Fix cell names with _TECHMAP_REPLACE_.*
Fixes #1804.
2020-03-23 11:17:07 +01:00
N. Engelhardt 91d12f4d59
Merge pull request #1785 from boqwxp/mitercc_cleanup
Clean up pseudo-private member usage in `passes/sat/miter.cc`.
2020-03-23 11:10:39 +01:00
Teguh Hofstee b08932cb81 fix typo in `write_smt2` help 2020-03-23 02:14:26 -07:00
Sahand Kashani f48fb26c0f Indentation conventions 2020-03-23 09:01:17 +01:00
Sahand Kashani-Akhavan 566e08485a
Const parameter in function (backends/firrtl/firrtl.cc)
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-03-23 08:56:28 +01:00
Alberto Gonzalez 5026f36250
Warn on empty selection for `add` command. 2020-03-23 05:58:12 +00:00
Peter Crozier 6cad865d12 Simplify was not being called for packages. Broke typedef enums. 2020-03-22 18:20:46 -07:00
Peter Crozier c06eda2504 Build pkg_user_types before parsing in case of changes in the design. 2020-03-22 18:20:46 -07:00
Peter 0aaa36ca6d Clear pkg_user_types if no packages following a 'design -reset-vlog'. 2020-03-22 18:20:46 -07:00
Peter 6d8d6b402f Revert typedef tests to standard grammar. 2020-03-22 18:20:46 -07:00
Peter 14f32028ec Parser changes to support typedef. 2020-03-22 18:20:46 -07:00
R. Ou c34969d3f1 iopadmap: Attempt to give new wires/cells meaningful names 2020-03-22 23:01:09 +01:00
David Shah beab15b77c
Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix
ice40: Map unmapped 'mince' DFFs to gate level
2020-03-21 17:35:27 +00:00
Sahand Kashani 21492914a2 Strip quotes around fileinfo strings
Yosys puts quotes around the string that represents the fileinfo whereas
firrtl does not. So when firrtl sees quotes, it escapes them with an extra
backslash which makes it hard to read afterwards.
2020-03-21 15:57:53 +01:00
Sahand Kashani c0b2a9af2e Add fileinfo to firrtl backend for assignments and non-instance cells 2020-03-21 12:54:23 +01:00
Eddie Hung f22f2000bd
Merge pull request #1795 from smunaut/fix_abc9_spram
ice40: Fix typos in SPRAM ABC9 timing specs
2020-03-20 16:13:46 -07:00
Eddie Hung 0c0dc4ffc3 opt_expr: fix failing $xnor test 2020-03-20 14:39:08 -07:00
Eddie Hung 6274f0b075 opt_expr: add failing $xnor test 2020-03-20 14:38:50 -07:00
Sylvain Munaut c15ce5a73e ice40: Fix typos in SPRAM ABC9 timing specs
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-20 22:19:55 +01:00
David Shah fa77fb857b Add test for abc9+mince issue
Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:35:28 +00:00
David Shah e813624f21 ice40: Map unmapped 'mince' DFFs to gate level
Signed-off-by: David Shah <dave@ds0.me>
2020-03-20 20:29:16 +00:00
Eddie Hung 317c18fc6f Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
Sahand Kashani 3e04e29dec Refactor fileinfo emission characters to single location 2020-03-20 18:31:12 +01:00
Eddie Hung af16ca9dd4 opt_expr: fix missing brace 2020-03-20 09:17:53 -07:00
Marcin Kościelnicki 9b982e929c xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00