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5069 Commits

Author SHA1 Message Date
Clifford Wolf 161565be10 Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) 2013-03-31 11:19:11 +02:00
Clifford Wolf 5640b7d607 Added test cases from 2012 paper on comparison of foss verilog synthesis tools 2013-03-31 11:17:56 +02:00
Clifford Wolf 04843bdcbe Added k68 (m68k compatible cpu) test case from verilator 2013-03-31 11:00:46 +02:00
Clifford Wolf 88af5b6a16 Improved opt_share for reduce cells 2013-03-29 11:19:21 +01:00
Clifford Wolf 0d48b846ac Improved opt_share for commutative standard cells 2013-03-29 11:01:26 +01:00
Clifford Wolf d60fbaf664 Added EXTRA_TARGETS Makefile variable 2013-03-28 16:53:40 +01:00
Clifford Wolf eff8c68dd9 Improved Makefile: Added ENABLE_* switches 2013-03-28 16:50:50 +01:00
Clifford Wolf 73fba5164f Implemented TCL support (only via -c option at the moment) 2013-03-28 12:26:17 +01:00
Clifford Wolf b9870a364e Improved subcircuit verbose output (added portmapper results) 2013-03-28 11:36:54 +01:00
Clifford Wolf c46597b697 Fixed svgviewer hacks for builtin files 2013-03-28 10:47:35 +01:00
Clifford Wolf 8edf4f378a Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file 2013-03-28 10:12:50 +01:00
Clifford Wolf 7bfc7b61a8 Implemented proper handling of stub placeholder modules 2013-03-28 09:20:10 +01:00
Clifford Wolf 98fcb5daa3 Keep viewport transform stable on reload in yosys-svgviewer 2013-03-27 18:48:38 +01:00
Clifford Wolf 92cf7ae2f7 Added check: only one module for "show" unless format is "ps" 2013-03-27 18:31:42 +01:00
Clifford Wolf 35a02ee81e Now using SVG and yosys-svgviewer per default in show command 2013-03-27 18:14:16 +01:00
Clifford Wolf 9c401b58a2 Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib 2013-03-27 10:51:15 +01:00
Clifford Wolf 62b9e16f87 Imported svgviewer from qt4.8 
This is from commit 543486a41963f8d20d9771d2107cdd5a22894bdb in the
Qt git repository: git://gitorious.org/qt/qt.git
 2013-03-27 06:57:57 +01:00
Clifford Wolf 041c06bd9d Create nice errors when calling RTLIL::Module::derive() of base class 2013-03-26 19:27:49 +01:00
Clifford Wolf 6a231816fa Collect parameters in hierarchy -generate (and do nothing with them) 2013-03-26 19:11:53 +01:00
Clifford Wolf 26f2439551 Tiny bugfix in simlib.v 2013-03-26 19:06:28 +01:00
Clifford Wolf 7a99349de4 Improvements and bugfixes for generate blocks with local signals 2013-03-26 11:31:34 +01:00
Clifford Wolf 6a382f2aba Fixed handling of unconditional generate blocks 2013-03-26 09:44:54 +01:00
Clifford Wolf 227520f94d Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
Clifford Wolf 3737964809 Improved verbose output of subcircuit 2013-03-25 11:08:52 +01:00
Clifford Wolf 0f5378b559 Improved method for finding fsm_expand candidates 2013-03-25 02:24:11 +01:00
Clifford Wolf 4a7d624bef Added hierarchy -generate command for generating skeletton modules 2013-03-25 02:14:33 +01:00
Clifford Wolf 4bd6f1ee8e Changed fsm_expand to merge multiplexers more aggressively 2013-03-24 17:59:44 +01:00
Clifford Wolf d9bc024d29 Renamed hansimem.v test case to mem_arst.v 2013-03-24 15:25:08 +01:00
Clifford Wolf e1a80b356e Fixed handling of show -viewer 2013-03-24 15:21:57 +01:00
Clifford Wolf 2887e4305f Fixed handling of internal signals in show command 2013-03-24 15:15:28 +01:00
Clifford Wolf 181b479e77 Improved show -colors color assignments 2013-03-24 13:32:56 +01:00
Clifford Wolf bbae24bdf7 Added show -strech and renamed -widthlabels to -width 2013-03-24 13:27:11 +01:00
Clifford Wolf f921b06fb0 Added -widthlabels options to chow command 2013-03-24 13:11:06 +01:00
Clifford Wolf 05ae20f260 Added -notypes option to intersynth backend 2013-03-24 12:05:25 +01:00
Clifford Wolf 8cc1c87ab8 Reorganized TODOs 2013-03-24 11:23:54 +01:00
Clifford Wolf df9753d398 Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
Clifford Wolf 6960df7285 Fixed stdcells.v for $adff with undef reset value 2013-03-24 10:43:05 +01:00
Clifford Wolf 3a5244e913 Another fix in mem2reg ast simplify logic 2013-03-24 10:42:08 +01:00
Clifford Wolf 55c50dc499 Added -colors option to show command 2013-03-24 10:41:24 +01:00
Clifford Wolf c3c9e5a02f Added hansimem testcase (memory with async reset) 2013-03-24 10:40:40 +01:00
Clifford Wolf bb3357c027 Improved mem2reg handling in ast simplifier 2013-03-24 09:27:01 +01:00
Clifford Wolf a0fa259d81 Fixed gcc build (intersynth backend) 2013-03-23 19:01:58 +01:00
Clifford Wolf e45d1c8865 Tiny fixes to verilog parser 2013-03-23 18:54:31 +01:00
Clifford Wolf bee57c808a Various improvements in intersynth backend 2013-03-23 12:02:09 +01:00
Clifford Wolf 80aefb3eaa Added intersynth backend 2013-03-23 10:58:14 +01:00
Clifford Wolf 47325fb271 Added help -write-tex-command-reference-manual option 2013-03-21 11:33:56 +01:00
Clifford Wolf 69ce1191c0 Added eclipse CDT project files to .gitignore 2013-03-21 10:59:35 +01:00
Clifford Wolf 8f610dca58 Added -S option for simple synthesis to gate logic 2013-03-21 09:52:21 +01:00
Clifford Wolf 87c7717566 Avoid verilog-2k in verilog backend 2013-03-21 09:51:25 +01:00
Clifford Wolf 91b94ef57b Disabled the per-default dumping of ILANG code 2013-03-21 09:12:32 +01:00