riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,028 Commits 87 Branches 48 Tags 35 MiB
Commit Graph

14028 Commits

Author SHA1 Message Date
Clifford Wolf 88fbdd4916 Fixed algorithmic complexity of AST simplification of long expressions 2014-01-20 20:25:20 +01:00
Ahmed Irfan aa3cb20e1e slice bug corrected 2014-01-20 18:35:52 +01:00
Ahmed Irfan c347f2825f assert feature 2014-01-20 10:45:02 +01:00
Ahmed Irfan b7adf4c7a0 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-01-20 09:58:04 +01:00
Clifford Wolf 32a91458a7 Added hilomap command 2014-01-19 21:58:58 +01:00
Clifford Wolf 03a876c7e8 Added sat -tempinduc and sat -prove-asserts 2014-01-19 16:35:17 +01:00
Clifford Wolf c36bac0e10 Added $assert support to satgen 2014-01-19 15:37:56 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 9a1eb45c75 Added Verilog parser support for asserts 2014-01-19 04:18:22 +01:00
Ahmed Irfan 234d0d0e1c script added 2014-01-18 21:54:52 +01:00
Ahmed Irfan 90483f489b Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-18 19:45:16 +01:00
Clifford Wolf 3d7a1491aa Fixed $lut simlib model for a wider range of tools 2014-01-18 19:31:40 +01:00
Clifford Wolf 13359d65ba Fixed parsing of verilog macros at end of line 2014-01-18 19:22:20 +01:00
Clifford Wolf 2fbaaaca7a More changes to simlib to make it friendlier to a wider range of tools 2014-01-18 19:13:43 +01:00
Clifford Wolf 4a9e133fab Fixed a type in $mem model in simlib.v 2014-01-18 18:54:50 +01:00
Ahmed Irfan b281e13263 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys 2014-01-18 18:11:26 +01:00
Ahmed Irfan 1dd797ab09 Merge branch 'master' of https://github.com/cliffordwolf/yosys 2014-01-18 18:10:31 +01:00
Ahmed Irfan da8af91552 pmux2mux 2014-01-18 17:29:55 +01:00
Clifford Wolf bef17eeb10 Removed cases of trailing comma in stdcells.v 2014-01-18 15:36:17 +01:00
Clifford Wolf 5b96675696 Added $bu0 cell to simlib.v 2014-01-18 15:35:15 +01:00
Clifford Wolf 839af272ad Improved setundef random number generator 2014-01-18 02:56:36 +01:00
Clifford Wolf 091d9abc3e Added setundef command 2014-01-17 23:14:36 +01:00
Clifford Wolf 548d5aafa4 Some improvements in log_dump_val_worker() templates 2014-01-17 23:14:17 +01:00
Clifford Wolf db9cf544b8 Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
Ahmed Irfan 9a689f33a5 verilog default options pull 
shift operator width issues
 2014-01-17 19:32:35 +01:00
Ahmed Irfan fc3f2961be Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-17 19:07:41 +01:00
Ahmed Irfan f2ee57f798 Merge pull request #4 from cliffordwolf/master 
verilog defaults
 2014-01-17 10:07:05 -08:00
Clifford Wolf 6170cfe9cd Added verilog_defaults command 2014-01-17 17:22:29 +01:00
Clifford Wolf 2e370d5a2f Added support for $adff with undef data inputs to opt_rmdff 2014-01-17 16:42:40 +01:00
Clifford Wolf 651ce67d97 Added select -assert-none and -assert-any 2014-01-17 16:34:50 +01:00
Ahmed Irfan be7707c5cf Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-17 10:50:59 +01:00
Ahmed Irfan 2d7bcaf2f2 Merge pull request #3 from cliffordwolf/master 
memory_unpack
 2014-01-17 01:48:55 -08:00
Clifford Wolf f3154f5694 Added automatic memid generation to memory_unpack command 2014-01-17 00:15:15 +01:00
Clifford Wolf 4d8318ad1b Added memory_unpack command 2014-01-17 00:05:02 +01:00
Ahmed Irfan c7a2e582aa slice error corrected 2014-01-16 20:16:01 +01:00
Ahmed Irfan 3a1490888d width issues 
dff cell for more than one registers
 2014-01-15 17:36:33 +01:00
Ahmed Irfan 8661626157 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-15 11:26:44 +01:00
Ahmed Irfan 66198d8591 Merge pull request #2 from cliffordwolf/master 
hierarchy
 2014-01-15 02:20:34 -08:00
Clifford Wolf 11c7df40c3 Merge pull request #20 from mschmoelzer/master 
Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))
 2014-01-14 11:51:28 -08:00
Martin Schmölzer aa17f16fec Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) 
This fixes compilation errors on Arch Linux.

Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
 2014-01-14 20:12:45 +01:00
Clifford Wolf 0c5b1f32d4 Added hierarchy -libdir option 2014-01-14 19:28:20 +01:00
Clifford Wolf 9a00980129 renamed LibertyParer to LibertyParser 2014-01-14 18:57:47 +01:00
Clifford Wolf c1da7661a5 Added "+" to list of liberty token characters 2014-01-14 18:56:29 +01:00
Ahmed Irfan 661b5a993e BTOR backend 2014-01-14 12:03:53 +01:00
Ahmed Irfan 1091c24d00 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor 2014-01-14 11:25:06 +01:00
Ahmed Irfan b4ce7fee06 Merge pull request #1 from cliffordwolf/master 
Added "opt_const -mux_undef"
 2014-01-14 02:22:10 -08:00
Clifford Wolf 54275c61ee Added "opt_const -mux_undef" 2014-01-14 11:10:29 +01:00
Clifford Wolf a3d94bf888 Fixed typo in frontends/ast/simplify.cc 2014-01-12 21:04:42 +01:00
Clifford Wolf bc541b47ea Improved performance of freduce input cone reduction 2014-01-04 13:10:51 +01:00
Clifford Wolf b791af174e Improved freduce performance on const signals 2014-01-04 00:06:36 +01:00