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Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor

This commit is contained in:
Ahmed Irfan 2014-01-17 19:07:41 +01:00
parent be7707c5cf f2ee57f798
commit fc3f2961be
4 changed files with 119 additions and 7 deletions
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66
frontends/verilog/verilog_frontend.cc
View File

@ -38,6 +38,9 @@ using namespace VERILOG_FRONTEND;
// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
static std::vector<std::string> verilog_defaults;
static std::list<std::vector<std::string>> verilog_defaults_stack;
struct VerilogFrontend : public Frontend {
VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { }
virtual void help()
@ -108,6 +111,9 @@ struct VerilogFrontend : public Frontend {
log(" add 'dir' to the directories which are used when searching include\n");
log(" files\n");
log("\n");
log("The command 'verilog_defaults' can be used to register default options for\n");
log("subsequent calls to 'read_verilog'.\n");
log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
@ -128,6 +134,8 @@ struct VerilogFrontend : public Frontend {
log_header("Executing Verilog-2005 frontend.\n");
args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
@ -248,3 +256,61 @@ void frontend_verilog_yyerror(char const *fmt, ...)
exit(1);
}
struct VerilogDefaults : public Pass {
VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" verilog_defaults -add [options]\n");
log("\n");
log("Add the sepcified options to the list of default options to read_verilog.\n");
log("\n");
log("\n");
log(" verilog_defaults -clear");
log("\n");
log("Clear the list of verilog default options.\n");
log("\n");
log("\n");
log(" verilog_defaults -push");
log(" verilog_defaults -pop");
log("\n");
log("Push or pop the list of default options to a stack. Note that -push does\n");
log("not imply -clear.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design*)
{
if (args.size() == 0)
cmd_error(args, 1, "Missing argument.");
if (args[1] == "-add") {
verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
return;
}
if (args.size() != 2)
cmd_error(args, 2, "Extra argument.");
if (args[1] == "-clear") {
verilog_defaults.clear();
return;
}
if (args[1] == "-push") {
verilog_defaults_stack.push_back(verilog_defaults);
return;
}
if (args[1] == "-pop") {
if (verilog_defaults_stack.empty()) {
verilog_defaults.clear();
} else {
verilog_defaults.swap(verilog_defaults_stack.back());
verilog_defaults_stack.pop_back();
}
return;
}
}
} VerilogDefaults;

3
kernel/rtlil.h
View File

@ -227,6 +227,9 @@ struct RTLIL::Selection {
if (!full_selection && selected_modules.count(module->name) == 0)
selected_members[module->name].insert(member->name);
}
bool empty() const {
return !full_selection && selected_modules.empty() && selected_members.empty();
}
};
struct RTLIL::Design {

51
passes/cmds/select.cc
View File

@ -656,6 +656,7 @@ struct SelectPass : public Pass {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" select [ -add | -del | -set <name> ] <selection>\n");
log(" select [ -assert-none | -assert-any ] <selection>\n");
log(" select [ -list | -write <filename> | -count | -clear ]\n");
log(" select -module <modname>\n");
log("\n");
@ -676,6 +677,14 @@ struct SelectPass : public Pass {
log(" do not modify the current selection. instead save the new selection\n");
log(" under the given name (see @<name> below).\n");
log("\n");
log(" -assert-none\n");
log(" asserts that the given selection is empty. i.e. produce an error if\n");
log(" any object matching the selection is found.\n");
log("\n");
log(" -assert-any\n");
log(" asserts that the given selection is non-empty. i.e. produce an error\n");
log(" if no object matching the selection is found.\n");
log("\n");
log(" -list\n");
log(" list all objects in the current selection\n");
log("\n");
@ -802,6 +811,8 @@ struct SelectPass : public Pass {
bool list_mode = false;
bool count_mode = false;
bool got_module = false;
bool assert_none = false;
bool assert_any = false;
std::string write_file;
std::string set_name;
@ -819,6 +830,14 @@ struct SelectPass : public Pass {
del_mode = true;
continue;
}
if (arg == "-assert-none") {
assert_none = true;
continue;
}
if (arg == "-assert-any") {
assert_any = true;
continue;
}
if (arg == "-clear") {
clear_mode = true;
continue;
@ -853,16 +872,16 @@ struct SelectPass : public Pass {
}
if (clear_mode && args.size() != 2)
log_cmd_error("Option -clear can not be combined with other options.\n");
log_cmd_error("Option -clear can not be combined with any other options.\n");
if (add_mode && del_mode)
log_cmd_error("Options -add and -del can not be combined.\n");
if (add_mode + del_mode + assert_none + assert_any > 1)
log_cmd_error("Options -add, -del, -assert-none or -assert-any can not be combined.\n");
if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode))
log_cmd_error("Options -list, -write and -count can not be combined with -add or -del.\n");
if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any))
log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none or -assert-any.\n");
if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode))
log_cmd_error("Option -set can not be combined with -list, -write, -count, -add or -del.\n");
if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode || assert_none || assert_any))
log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none or -assert-any.\n");
if (work_stack.size() == 0 && got_module) {
RTLIL::Selection sel;
@ -943,6 +962,24 @@ struct SelectPass : public Pass {
return;
}
if (assert_none)
{
if (work_stack.size() == 0)
log_cmd_error("No selection to check.\n");
if (!work_stack.back().empty())
log_error("Assertation failed: selection is not empty.\n");
return;
}
if (assert_any)
{
if (work_stack.size() == 0)
log_cmd_error("No selection to check.\n");
if (work_stack.back().empty())
log_error("Assertation failed: selection is empty.\n");
return;
}
if (!set_name.empty())
{
if (work_stack.size() == 0)

6
passes/opt/opt_rmdff.cc
View File

@ -92,6 +92,12 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
}
}
if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) {
RTLIL::SigSig conn(sig_q, val_rv);
mod->connections.push_back(conn);
goto delete_dff;
}
if (sig_d.is_fully_const() && sig_r.width == 0) {
RTLIL::SigSig conn(sig_q, sig_d);
mod->connections.push_back(conn);