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232 Commits

Author SHA1 Message Date
Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-29 16:32:44 +01:00
Clifford Wolf 9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Clifford Wolf b02d9c2634 Fix handling of cases that look like sva labels, fixes #862 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-10 16:27:18 -07:00
Clifford Wolf e7a34d342e Also add support for labels on sva module items, fixes #699 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-08 22:55:09 -08:00
Clifford Wolf 22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf 17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Sylvain Munaut 58fb2ac818 verilog_parser: Properly handle recursion when processing attributes 
Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-12-14 12:48:00 +01:00
Clifford Wolf 36ea98385f Add warning for SV "restrict" without "property" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 15:57:17 +01:00
Clifford Wolf 5ab58d4930 Fix minor typo in error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-25 13:20:00 +02:00
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Clifford Wolf f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
argama 097da32e1a ignore protect endprotect 2018-10-16 21:33:37 +08:00
Ruben Undheim 736105b046 Handle FIXME for modport members without type directly in front 2018-10-13 20:50:33 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Clifford Wolf 8fde05dfa5 Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-24 20:51:16 +02:00
Clifford Wolf eb452ffb28 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-23 10:32:54 +02:00
Clifford Wolf ddc1761f1a Add "make coverage" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 14:22:21 +02:00
Clifford Wolf 4d269f9b25
Merge pull request #610 from udif/udif_specify_round2 
More specify/endspecify fixes
 2018-08-23 14:43:25 +02:00
Udi Finkelstein 042b3074f8 Added -no_dump_ptr flag for AST dump options in 'read_verilog' 
This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
 2018-08-23 15:26:02 +03:00
Udi Finkelstein fbfc677df3 Fixed all known specify/endspecify issues, without breaking 'make test'. 
Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
 2018-08-20 17:27:45 +03:00
Udi Finkelstein 95241c8f4d Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , 
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
 2018-08-20 00:08:08 +03:00
Udi Finkelstein 28cfc75a90 A few minor enhancements to specify block parsing. 
Just remember specify blocks are parsed but ignored.
 2018-08-15 20:14:52 +03:00
Clifford Wolf 67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Clifford Wolf d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl 
Detect illegal port declaration, e.g input/output/inout keyword must …
 2018-08-15 13:14:23 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Henner Zeller 68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Henner Zeller b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Udi Finkelstein 8b7580b0a1 Detect illegal port declaration, e.g input/output/inout keyword must be the first. 2018-06-06 22:27:25 +03:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Jim Paris 4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris 872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf a572b49538 Replace -ignore_redef with -[no]overwrite 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-03 15:25:59 +02:00
Dan Gisselquist e060375f23 Support more character literals 2018-05-03 12:35:01 +02:00
Clifford Wolf 2d7f3123f0 Add statement labels for immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-13 11:52:28 +02:00
Clifford Wolf 66ffc99695 Allow "property" in immediate assertions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-12 14:28:28 +02:00
Clifford Wolf 5ea2c53604 Add read_verilog anyseq/anyconst/allseq/allconst attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-04-06 14:35:11 +02:00
Udi Finkelstein 6378e2cd46 First draft of Verilog parser support for specify blocks and parameters. 
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
 2018-03-27 14:34:00 +02:00
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf 34005348b6 Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00
Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
Clifford Wolf 5b6e52118c Accept real-valued delay values 2017-11-18 10:01:30 +01:00
William D. Jones abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 
(Oreilly 'Flex & Bison' page 189)
 2017-09-30 06:39:07 +03:00
Clifford Wolf 2c04d883b1 Minor coding style fix 2017-09-26 13:50:14 +02:00
Clifford Wolf cb1d439d10 Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master 2017-09-26 13:48:13 +02:00