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222 Commits

Author SHA1 Message Date
gatecat 493b5e03e7 manual: Fix cell-stmt order 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-03 18:17:10 -07:00
Miodrag Milanovic cb17eeaf50 Update manual 2022-01-03 11:57:11 +01:00
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Miodrag Milanovic 71e762d68c Update manual 2021-12-03 09:57:14 +01:00
Gabriel Somlo 9a413803eb manual: fix pdflatex inputenc undefined char error 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-11-07 03:05:03 +01:00
Miodrag Milanovic 598f51c6a1 Update command reference 2021-11-05 10:04:15 +01:00
Miodrag Milanovic 55f07fe56f Update command reference part of manual 2021-10-29 13:10:50 +02:00
Marcelina Kościelnicka ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Claire Xenia Wolf 2d95a7da9c Intersynth URL 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-06-09 12:42:52 +02:00
Claire Xenia Wolf a734face3a More deadname stuff 2021-06-09 12:33:41 +02:00
Claire Xenia Wolf 0ada13cbe2 Use HTTPS for website links, gatecat email 
git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
 2021-06-09 12:16:56 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
N. Engelhardt d9ec35a526 split CodingReadme into multiple files 2021-03-22 19:16:25 +01:00
Zachary Snow c8b45a4a82 bugpoint: add runner option 2021-03-17 15:54:00 -04:00
Marcelina Kościelnicka 89c74ffd71 verilog: Use proc memory writes in the frontend. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka 4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Claire Xen 7d2097b005
Update command-reference-manual.tex 2021-03-04 16:45:21 +01:00
Robert Baruch ca4b1afcb6 RTLIL Documentation: switch in process is optional 2021-02-27 09:58:03 -08:00
Robert Baruch 2bb3fc654a Further juggles the wording of "character". 2020-11-25 12:02:35 -08:00
Robert Baruch 5d1bb79895 Clarifies how character encodings work. 2020-11-25 11:57:17 -08:00
Robert Baruch 1faf0e6dcc Clarifies whitespace and eol. 2020-11-25 10:06:22 -08:00
Robert Baruch 5615c41907 Cleans up doublequotes 2020-11-25 09:58:36 -08:00
Robert Baruch 09f6e9d6b6 Clarifies use of integers, and character set. 2020-11-25 09:53:39 -08:00
Robert Baruch 39af3e629f Clarifies processes, corrects some attributes 2020-11-25 08:59:25 -08:00
Robert Baruch be938b3094 Refactors for attributes. 2020-11-24 21:59:53 -08:00
Robert Baruch 278b542273 Cleans up some descriptions and syntax 
Now all rules ending in "-stmt" end in eol.
 2020-11-24 15:27:30 -08:00
Robert Baruch d3d28e287f Adds missing "end" and eol to module. 2020-11-22 21:08:58 -08:00
Robert Baruch c5a2ae01cd Update to Values #2 2020-11-22 18:50:41 -08:00
Robert Baruch 5159dda826 Update to Values section 2020-11-22 18:48:21 -08:00
Robert Baruch 1034422c58 Adds appendix on RTLIL text format 2020-11-22 12:56:29 -08:00
whitequark eae88df016 manual: fix typo. 2020-08-27 16:34:48 +00:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
Marcelina Kościelnicka 2db270cbc7 Add latches to the manual. 2020-06-26 23:27:14 +02:00
Marcelina Kościelnicka 80a0cf9bb8 Add a few more gate types to the manual. 2020-06-26 23:27:14 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types 
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
 2020-06-23 15:40:02 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
Xiretza 8b0ec3c3a2
Use in-tree include directory in manual build 
This is basically the same issue as in tests/various/plugin.sh,
which uses yosys-config to compile a plugin. `yosys-config --cxxflags`
points to `$PREFIX/share/` (/usr/local/share by default), which might
not exist yet or might be out of date. Building directly from the
headers in ./share/ avoids this.
 2020-05-30 11:21:40 +02:00
clairexen 94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells 
Fix modulo/remainder semantics
 2020-05-29 16:37:23 +02:00
whitequark efa7424fb9 Restrict RTLIL::IdString to not contain whitespace or control chars. 
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
 2020-05-29 06:43:18 +00:00
Xiretza f88bef7672
Document division and modulo cells 2020-05-28 22:59:04 +02:00
Xiretza edd8ff2c07
Add flooring division operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
 2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator 
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
 2020-05-28 22:59:03 +02:00
Eddie Hung c34d57de2e Update CHANGELOG and manual for departure from upstream 2020-04-27 12:08:45 -07:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Teguh Hofstee b08932cb81 fix typo in `write_smt2` help 2020-03-23 02:14:26 -07:00
whitequark 161eba253f manual: explain RTLIL::Wire::{upto,offset}. 2020-02-09 14:54:07 +00:00
Claire Wolf 8f40113826
Merge pull request #1553 from whitequark/manual-dffx 
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
 2020-01-28 09:41:08 +01:00