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Document division and modulo cells
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@ -139,6 +139,8 @@ Verilog & Cell Type \\
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\lstinline[language=Verilog]; Y = A * B; & {\tt \$mul} \\
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\lstinline[language=Verilog]; Y = A / B; & {\tt \$div} \\
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\lstinline[language=Verilog]; Y = A % B; & {\tt \$mod} \\
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\multicolumn{1}{c}{\tt [N/A]} & {\tt \$divfloor} \\
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\multicolumn{1}{c}{\tt [N/A]} & {\tt \$modfoor} \\
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\lstinline[language=Verilog]; Y = A ** B; & {\tt \$pow} \\
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\end{tabular}
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\caption{Cell types for binary operators with their corresponding Verilog expressions.}
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@ -161,6 +163,27 @@ For the binary cells that output a logical value ({\tt \$logic\_and}, {\tt \$log
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{\tt \$gt}), when the \B{Y\_WIDTH} parameter is greater than 1, the output is zero-extended,
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and only the least significant bit varies.
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Division and modulo cells are available in two rounding modes. The original {\tt \$div} and {\tt \$mod}
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cells are based on truncating division, and correspond to the semantics of the verilog {\tt /} and
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{\tt \%} operators. The {\tt \$divfloor} and {\tt \$modfloor} cells represent flooring division and
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flooring modulo, the latter of which is also known as ``remainder'' in several languages. See
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table~\ref{tab:CellLib_divmod} for a side-by-side comparison between the different semantics.
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\begin{table}[h]
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\hfil
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\begin{tabular}{lr|rr|rr}
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\multirow{2}{*}{Division} & \multirow{2}{*}{Result} & \multicolumn{2}{c|}{Truncating} & \multicolumn{2}{c}{Flooring} \\
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& & {\tt \$div} & {\tt \$mod} & {\tt \$divfloor} & {\tt \$modfloor} \\
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\hline
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{\tt -10 / 3} & {\tt -3.3} & {\tt -3} & {\tt -1} & {\tt -4} & {\tt 2} \\
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{\tt 10 / -3} & {\tt -3.3} & {\tt -3} & {\tt 1} & {\tt -4} & {\tt -2} \\
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{\tt -10 / -3} & {\tt 3.3} & {\tt 3} & {\tt -1} & {\tt 3} & {\tt -1} \\
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{\tt 10 / 3} & {\tt 3.3} & {\tt 3} & {\tt 1} & {\tt 3} & {\tt 1} \\
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\end{tabular}
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\caption{Comparison between different rounding modes for division and modulo cells.}
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\label{tab:CellLib_divmod}
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\end{table}
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\subsection{Multiplexers}
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Multiplexers are generated by the Verilog HDL frontend for {\tt
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