riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

RTLIL Documentation: switch in process is optional

This commit is contained in:
Robert Baruch 2021-02-27 09:58:03 -08:00
parent d882b6fe3c
commit ca4b1afcb6
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
manual/CHAPTER_TextRtlil.tex
View File

@ -241,7 +241,7 @@ See Sec.~\ref{sec:rtlil_process} for an overview of processes.
<proc-stmt> ::= "process" <id> <eol>
<process-body> ::= <assign-stmt>$*$ <switch> <assign-stmt>$*$ <sync>$*$
<process-body> ::= <assign-stmt>$*$ <switch>$?$ <assign-stmt>$*$ <sync>$*$
<assign-stmt> ::= "assign" <dest-sigspec> <src-sigspec> <eol>